| *SPEF "ieee 1481-1999" |
| *DESIGN "user_project_wrapper" |
| *DATE "11:11:11 Fri 11 11, 1111" |
| *VENDOR "OpenRCX" |
| *PROGRAM "Parallel Extraction" |
| *VERSION "1.0" |
| *DESIGN_FLOW "NAME_SCOPE LOCAL" "PIN_CAP NONE" |
| *DIVIDER / |
| *DELIMITER : |
| *BUS_DELIMITER [] |
| *T_UNIT 1 NS |
| *C_UNIT 1 PF |
| *R_UNIT 1 OHM |
| *L_UNIT 1 HENRY |
| |
| *NAME_MAP |
| *1 io_in[0] |
| *2 io_in[10] |
| *3 io_in[11] |
| *4 io_in[12] |
| *5 io_in[13] |
| *6 io_in[14] |
| *7 io_in[15] |
| *8 io_in[16] |
| *9 io_in[17] |
| *10 io_in[18] |
| *11 io_in[19] |
| *12 io_in[1] |
| *13 io_in[20] |
| *14 io_in[21] |
| *15 io_in[22] |
| *16 io_in[23] |
| *17 io_in[24] |
| *18 io_in[25] |
| *19 io_in[26] |
| *20 io_in[27] |
| *21 io_in[28] |
| *22 io_in[29] |
| *23 io_in[2] |
| *24 io_in[30] |
| *25 io_in[31] |
| *26 io_in[32] |
| *27 io_in[33] |
| *28 io_in[34] |
| *29 io_in[35] |
| *30 io_in[36] |
| *31 io_in[37] |
| *32 io_in[3] |
| *33 io_in[4] |
| *34 io_in[5] |
| *35 io_in[6] |
| *36 io_in[7] |
| *37 io_in[8] |
| *38 io_in[9] |
| *39 io_oeb[0] |
| *40 io_oeb[10] |
| *41 io_oeb[11] |
| *42 io_oeb[12] |
| *43 io_oeb[13] |
| *44 io_oeb[14] |
| *45 io_oeb[15] |
| *46 io_oeb[16] |
| *47 io_oeb[17] |
| *48 io_oeb[18] |
| *49 io_oeb[19] |
| *50 io_oeb[1] |
| *51 io_oeb[20] |
| *52 io_oeb[21] |
| *53 io_oeb[22] |
| *54 io_oeb[23] |
| *55 io_oeb[24] |
| *56 io_oeb[25] |
| *57 io_oeb[26] |
| *58 io_oeb[27] |
| *59 io_oeb[28] |
| *60 io_oeb[29] |
| *61 io_oeb[2] |
| *62 io_oeb[30] |
| *63 io_oeb[31] |
| *64 io_oeb[32] |
| *65 io_oeb[33] |
| *66 io_oeb[34] |
| *67 io_oeb[35] |
| *68 io_oeb[36] |
| *69 io_oeb[37] |
| *70 io_oeb[3] |
| *71 io_oeb[4] |
| *72 io_oeb[5] |
| *73 io_oeb[6] |
| *74 io_oeb[7] |
| *75 io_oeb[8] |
| *76 io_oeb[9] |
| *77 io_out[0] |
| *78 io_out[10] |
| *79 io_out[11] |
| *80 io_out[12] |
| *81 io_out[13] |
| *82 io_out[14] |
| *83 io_out[15] |
| *84 io_out[16] |
| *85 io_out[17] |
| *86 io_out[18] |
| *87 io_out[19] |
| *88 io_out[1] |
| *89 io_out[20] |
| *90 io_out[21] |
| *91 io_out[22] |
| *92 io_out[23] |
| *93 io_out[24] |
| *94 io_out[25] |
| *95 io_out[26] |
| *96 io_out[27] |
| *97 io_out[28] |
| *98 io_out[29] |
| *99 io_out[2] |
| *100 io_out[30] |
| *101 io_out[31] |
| *102 io_out[32] |
| *103 io_out[33] |
| *104 io_out[34] |
| *105 io_out[35] |
| *106 io_out[36] |
| *107 io_out[37] |
| *108 io_out[3] |
| *109 io_out[4] |
| *110 io_out[5] |
| *111 io_out[6] |
| *112 io_out[7] |
| *113 io_out[8] |
| *114 io_out[9] |
| *115 la_data_in[0] |
| *116 la_data_in[10] |
| *117 la_data_in[11] |
| *118 la_data_in[12] |
| *119 la_data_in[13] |
| *120 la_data_in[14] |
| *121 la_data_in[15] |
| *122 la_data_in[16] |
| *123 la_data_in[17] |
| *124 la_data_in[18] |
| *125 la_data_in[19] |
| *126 la_data_in[1] |
| *127 la_data_in[20] |
| *128 la_data_in[21] |
| *129 la_data_in[22] |
| *130 la_data_in[23] |
| *131 la_data_in[24] |
| *132 la_data_in[25] |
| *133 la_data_in[26] |
| *134 la_data_in[27] |
| *135 la_data_in[28] |
| *136 la_data_in[29] |
| *137 la_data_in[2] |
| *138 la_data_in[30] |
| *139 la_data_in[31] |
| *140 la_data_in[32] |
| *141 la_data_in[33] |
| *142 la_data_in[34] |
| *143 la_data_in[35] |
| *144 la_data_in[36] |
| *145 la_data_in[37] |
| *146 la_data_in[38] |
| *147 la_data_in[39] |
| *148 la_data_in[3] |
| *149 la_data_in[40] |
| *150 la_data_in[41] |
| *151 la_data_in[42] |
| *152 la_data_in[43] |
| *153 la_data_in[44] |
| *154 la_data_in[45] |
| *155 la_data_in[46] |
| *156 la_data_in[47] |
| *157 la_data_in[48] |
| *158 la_data_in[49] |
| *159 la_data_in[4] |
| *160 la_data_in[50] |
| *161 la_data_in[51] |
| *162 la_data_in[52] |
| *163 la_data_in[53] |
| *164 la_data_in[54] |
| *165 la_data_in[55] |
| *166 la_data_in[56] |
| *167 la_data_in[57] |
| *168 la_data_in[58] |
| *169 la_data_in[59] |
| *170 la_data_in[5] |
| *171 la_data_in[60] |
| *172 la_data_in[61] |
| *173 la_data_in[62] |
| *174 la_data_in[63] |
| *175 la_data_in[6] |
| *176 la_data_in[7] |
| *177 la_data_in[8] |
| *178 la_data_in[9] |
| *179 la_data_out[0] |
| *180 la_data_out[10] |
| *181 la_data_out[11] |
| *182 la_data_out[12] |
| *183 la_data_out[13] |
| *184 la_data_out[14] |
| *185 la_data_out[15] |
| *186 la_data_out[16] |
| *187 la_data_out[17] |
| *188 la_data_out[18] |
| *189 la_data_out[19] |
| *190 la_data_out[1] |
| *191 la_data_out[20] |
| *192 la_data_out[21] |
| *193 la_data_out[22] |
| *194 la_data_out[23] |
| *195 la_data_out[24] |
| *196 la_data_out[25] |
| *197 la_data_out[26] |
| *198 la_data_out[27] |
| *199 la_data_out[28] |
| *200 la_data_out[29] |
| *201 la_data_out[2] |
| *202 la_data_out[30] |
| *203 la_data_out[31] |
| *204 la_data_out[32] |
| *205 la_data_out[33] |
| *206 la_data_out[34] |
| *207 la_data_out[35] |
| *208 la_data_out[36] |
| *209 la_data_out[37] |
| *210 la_data_out[38] |
| *211 la_data_out[39] |
| *212 la_data_out[3] |
| *213 la_data_out[40] |
| *214 la_data_out[41] |
| *215 la_data_out[42] |
| *216 la_data_out[43] |
| *217 la_data_out[44] |
| *218 la_data_out[45] |
| *219 la_data_out[46] |
| *220 la_data_out[47] |
| *221 la_data_out[48] |
| *222 la_data_out[49] |
| *223 la_data_out[4] |
| *224 la_data_out[50] |
| *225 la_data_out[51] |
| *226 la_data_out[52] |
| *227 la_data_out[53] |
| *228 la_data_out[54] |
| *229 la_data_out[55] |
| *230 la_data_out[56] |
| *231 la_data_out[57] |
| *232 la_data_out[58] |
| *233 la_data_out[59] |
| *234 la_data_out[5] |
| *235 la_data_out[60] |
| *236 la_data_out[61] |
| *237 la_data_out[62] |
| *238 la_data_out[63] |
| *239 la_data_out[6] |
| *240 la_data_out[7] |
| *241 la_data_out[8] |
| *242 la_data_out[9] |
| *243 la_oenb[0] |
| *244 la_oenb[10] |
| *245 la_oenb[11] |
| *246 la_oenb[12] |
| *247 la_oenb[13] |
| *248 la_oenb[14] |
| *249 la_oenb[15] |
| *250 la_oenb[16] |
| *251 la_oenb[17] |
| *252 la_oenb[18] |
| *253 la_oenb[19] |
| *254 la_oenb[1] |
| *255 la_oenb[20] |
| *256 la_oenb[21] |
| *257 la_oenb[22] |
| *258 la_oenb[23] |
| *259 la_oenb[24] |
| *260 la_oenb[25] |
| *261 la_oenb[26] |
| *262 la_oenb[27] |
| *263 la_oenb[28] |
| *264 la_oenb[29] |
| *265 la_oenb[2] |
| *266 la_oenb[30] |
| *267 la_oenb[31] |
| *268 la_oenb[32] |
| *269 la_oenb[33] |
| *270 la_oenb[34] |
| *271 la_oenb[35] |
| *272 la_oenb[36] |
| *273 la_oenb[37] |
| *274 la_oenb[38] |
| *275 la_oenb[39] |
| *276 la_oenb[3] |
| *277 la_oenb[40] |
| *278 la_oenb[41] |
| *279 la_oenb[42] |
| *280 la_oenb[43] |
| *281 la_oenb[44] |
| *282 la_oenb[45] |
| *283 la_oenb[46] |
| *284 la_oenb[47] |
| *285 la_oenb[48] |
| *286 la_oenb[49] |
| *287 la_oenb[4] |
| *288 la_oenb[50] |
| *289 la_oenb[51] |
| *290 la_oenb[52] |
| *291 la_oenb[53] |
| *292 la_oenb[54] |
| *293 la_oenb[55] |
| *294 la_oenb[56] |
| *295 la_oenb[57] |
| *296 la_oenb[58] |
| *297 la_oenb[59] |
| *298 la_oenb[5] |
| *299 la_oenb[60] |
| *300 la_oenb[61] |
| *301 la_oenb[62] |
| *302 la_oenb[63] |
| *303 la_oenb[6] |
| *304 la_oenb[7] |
| *305 la_oenb[8] |
| *306 la_oenb[9] |
| *307 user_clock2 |
| *308 user_irq[0] |
| *309 user_irq[1] |
| *310 user_irq[2] |
| *313 wb_clk_i |
| *314 wb_rst_i |
| *315 wbs_ack_o |
| *316 wbs_adr_i[0] |
| *317 wbs_adr_i[10] |
| *318 wbs_adr_i[11] |
| *319 wbs_adr_i[12] |
| *320 wbs_adr_i[13] |
| *321 wbs_adr_i[14] |
| *322 wbs_adr_i[15] |
| *323 wbs_adr_i[16] |
| *324 wbs_adr_i[17] |
| *325 wbs_adr_i[18] |
| *326 wbs_adr_i[19] |
| *327 wbs_adr_i[1] |
| *328 wbs_adr_i[20] |
| *329 wbs_adr_i[21] |
| *330 wbs_adr_i[22] |
| *331 wbs_adr_i[23] |
| *332 wbs_adr_i[24] |
| *333 wbs_adr_i[25] |
| *334 wbs_adr_i[26] |
| *335 wbs_adr_i[27] |
| *336 wbs_adr_i[28] |
| *337 wbs_adr_i[29] |
| *338 wbs_adr_i[2] |
| *339 wbs_adr_i[30] |
| *340 wbs_adr_i[31] |
| *341 wbs_adr_i[3] |
| *342 wbs_adr_i[4] |
| *343 wbs_adr_i[5] |
| *344 wbs_adr_i[6] |
| *345 wbs_adr_i[7] |
| *346 wbs_adr_i[8] |
| *347 wbs_adr_i[9] |
| *348 wbs_cyc_i |
| *349 wbs_dat_i[0] |
| *350 wbs_dat_i[10] |
| *351 wbs_dat_i[11] |
| *352 wbs_dat_i[12] |
| *353 wbs_dat_i[13] |
| *354 wbs_dat_i[14] |
| *355 wbs_dat_i[15] |
| *356 wbs_dat_i[16] |
| *357 wbs_dat_i[17] |
| *358 wbs_dat_i[18] |
| *359 wbs_dat_i[19] |
| *360 wbs_dat_i[1] |
| *361 wbs_dat_i[20] |
| *362 wbs_dat_i[21] |
| *363 wbs_dat_i[22] |
| *364 wbs_dat_i[23] |
| *365 wbs_dat_i[24] |
| *366 wbs_dat_i[25] |
| *367 wbs_dat_i[26] |
| *368 wbs_dat_i[27] |
| *369 wbs_dat_i[28] |
| *370 wbs_dat_i[29] |
| *371 wbs_dat_i[2] |
| *372 wbs_dat_i[30] |
| *373 wbs_dat_i[31] |
| *374 wbs_dat_i[3] |
| *375 wbs_dat_i[4] |
| *376 wbs_dat_i[5] |
| *377 wbs_dat_i[6] |
| *378 wbs_dat_i[7] |
| *379 wbs_dat_i[8] |
| *380 wbs_dat_i[9] |
| *381 wbs_dat_o[0] |
| *382 wbs_dat_o[10] |
| *383 wbs_dat_o[11] |
| *384 wbs_dat_o[12] |
| *385 wbs_dat_o[13] |
| *386 wbs_dat_o[14] |
| *387 wbs_dat_o[15] |
| *388 wbs_dat_o[16] |
| *389 wbs_dat_o[17] |
| *390 wbs_dat_o[18] |
| *391 wbs_dat_o[19] |
| *392 wbs_dat_o[1] |
| *393 wbs_dat_o[20] |
| *394 wbs_dat_o[21] |
| *395 wbs_dat_o[22] |
| *396 wbs_dat_o[23] |
| *397 wbs_dat_o[24] |
| *398 wbs_dat_o[25] |
| *399 wbs_dat_o[26] |
| *400 wbs_dat_o[27] |
| *401 wbs_dat_o[28] |
| *402 wbs_dat_o[29] |
| *403 wbs_dat_o[2] |
| *404 wbs_dat_o[30] |
| *405 wbs_dat_o[31] |
| *406 wbs_dat_o[3] |
| *407 wbs_dat_o[4] |
| *408 wbs_dat_o[5] |
| *409 wbs_dat_o[6] |
| *410 wbs_dat_o[7] |
| *411 wbs_dat_o[8] |
| *412 wbs_dat_o[9] |
| *413 wbs_sel_i[0] |
| *414 wbs_sel_i[1] |
| *415 wbs_sel_i[2] |
| *416 wbs_sel_i[3] |
| *417 wbs_stb_i |
| *418 wbs_we_i |
| *419 wrapped_vga_clock |
| |
| *PORTS |
| io_in[0] I |
| io_in[10] I |
| io_in[11] I |
| io_in[12] I |
| io_in[13] I |
| io_in[14] I |
| io_in[15] I |
| io_in[16] I |
| io_in[17] I |
| io_in[18] I |
| io_in[19] I |
| io_in[1] I |
| io_in[20] I |
| io_in[21] I |
| io_in[22] I |
| io_in[23] I |
| io_in[24] I |
| io_in[25] I |
| io_in[26] I |
| io_in[27] I |
| io_in[28] I |
| io_in[29] I |
| io_in[2] I |
| io_in[30] I |
| io_in[31] I |
| io_in[32] I |
| io_in[33] I |
| io_in[34] I |
| io_in[35] I |
| io_in[36] I |
| io_in[37] I |
| io_in[3] I |
| io_in[4] I |
| io_in[5] I |
| io_in[6] I |
| io_in[7] I |
| io_in[8] I |
| io_in[9] I |
| io_oeb[0] O |
| io_oeb[10] O |
| io_oeb[11] O |
| io_oeb[12] O |
| io_oeb[13] O |
| io_oeb[14] O |
| io_oeb[15] O |
| io_oeb[16] O |
| io_oeb[17] O |
| io_oeb[18] O |
| io_oeb[19] O |
| io_oeb[1] O |
| io_oeb[20] O |
| io_oeb[21] O |
| io_oeb[22] O |
| io_oeb[23] O |
| io_oeb[24] O |
| io_oeb[25] O |
| io_oeb[26] O |
| io_oeb[27] O |
| io_oeb[28] O |
| io_oeb[29] O |
| io_oeb[2] O |
| io_oeb[30] O |
| io_oeb[31] O |
| io_oeb[32] O |
| io_oeb[33] O |
| io_oeb[34] O |
| io_oeb[35] O |
| io_oeb[36] O |
| io_oeb[37] O |
| io_oeb[3] O |
| io_oeb[4] O |
| io_oeb[5] O |
| io_oeb[6] O |
| io_oeb[7] O |
| io_oeb[8] O |
| io_oeb[9] O |
| io_out[0] O |
| io_out[10] O |
| io_out[11] O |
| io_out[12] O |
| io_out[13] O |
| io_out[14] O |
| io_out[15] O |
| io_out[16] O |
| io_out[17] O |
| io_out[18] O |
| io_out[19] O |
| io_out[1] O |
| io_out[20] O |
| io_out[21] O |
| io_out[22] O |
| io_out[23] O |
| io_out[24] O |
| io_out[25] O |
| io_out[26] O |
| io_out[27] O |
| io_out[28] O |
| io_out[29] O |
| io_out[2] O |
| io_out[30] O |
| io_out[31] O |
| io_out[32] O |
| io_out[33] O |
| io_out[34] O |
| io_out[35] O |
| io_out[36] O |
| io_out[37] O |
| io_out[3] O |
| io_out[4] O |
| io_out[5] O |
| io_out[6] O |
| io_out[7] O |
| io_out[8] O |
| io_out[9] O |
| la_data_in[0] I |
| la_data_in[10] I |
| la_data_in[11] I |
| la_data_in[12] I |
| la_data_in[13] I |
| la_data_in[14] I |
| la_data_in[15] I |
| la_data_in[16] I |
| la_data_in[17] I |
| la_data_in[18] I |
| la_data_in[19] I |
| la_data_in[1] I |
| la_data_in[20] I |
| la_data_in[21] I |
| la_data_in[22] I |
| la_data_in[23] I |
| la_data_in[24] I |
| la_data_in[25] I |
| la_data_in[26] I |
| la_data_in[27] I |
| la_data_in[28] I |
| la_data_in[29] I |
| la_data_in[2] I |
| la_data_in[30] I |
| la_data_in[31] I |
| la_data_in[32] I |
| la_data_in[33] I |
| la_data_in[34] I |
| la_data_in[35] I |
| la_data_in[36] I |
| la_data_in[37] I |
| la_data_in[38] I |
| la_data_in[39] I |
| la_data_in[3] I |
| la_data_in[40] I |
| la_data_in[41] I |
| la_data_in[42] I |
| la_data_in[43] I |
| la_data_in[44] I |
| la_data_in[45] I |
| la_data_in[46] I |
| la_data_in[47] I |
| la_data_in[48] I |
| la_data_in[49] I |
| la_data_in[4] I |
| la_data_in[50] I |
| la_data_in[51] I |
| la_data_in[52] I |
| la_data_in[53] I |
| la_data_in[54] I |
| la_data_in[55] I |
| la_data_in[56] I |
| la_data_in[57] I |
| la_data_in[58] I |
| la_data_in[59] I |
| la_data_in[5] I |
| la_data_in[60] I |
| la_data_in[61] I |
| la_data_in[62] I |
| la_data_in[63] I |
| la_data_in[6] I |
| la_data_in[7] I |
| la_data_in[8] I |
| la_data_in[9] I |
| la_data_out[0] O |
| la_data_out[10] O |
| la_data_out[11] O |
| la_data_out[12] O |
| la_data_out[13] O |
| la_data_out[14] O |
| la_data_out[15] O |
| la_data_out[16] O |
| la_data_out[17] O |
| la_data_out[18] O |
| la_data_out[19] O |
| la_data_out[1] O |
| la_data_out[20] O |
| la_data_out[21] O |
| la_data_out[22] O |
| la_data_out[23] O |
| la_data_out[24] O |
| la_data_out[25] O |
| la_data_out[26] O |
| la_data_out[27] O |
| la_data_out[28] O |
| la_data_out[29] O |
| la_data_out[2] O |
| la_data_out[30] O |
| la_data_out[31] O |
| la_data_out[32] O |
| la_data_out[33] O |
| la_data_out[34] O |
| la_data_out[35] O |
| la_data_out[36] O |
| la_data_out[37] O |
| la_data_out[38] O |
| la_data_out[39] O |
| la_data_out[3] O |
| la_data_out[40] O |
| la_data_out[41] O |
| la_data_out[42] O |
| la_data_out[43] O |
| la_data_out[44] O |
| la_data_out[45] O |
| la_data_out[46] O |
| la_data_out[47] O |
| la_data_out[48] O |
| la_data_out[49] O |
| la_data_out[4] O |
| la_data_out[50] O |
| la_data_out[51] O |
| la_data_out[52] O |
| la_data_out[53] O |
| la_data_out[54] O |
| la_data_out[55] O |
| la_data_out[56] O |
| la_data_out[57] O |
| la_data_out[58] O |
| la_data_out[59] O |
| la_data_out[5] O |
| la_data_out[60] O |
| la_data_out[61] O |
| la_data_out[62] O |
| la_data_out[63] O |
| la_data_out[6] O |
| la_data_out[7] O |
| la_data_out[8] O |
| la_data_out[9] O |
| la_oenb[0] I |
| la_oenb[10] I |
| la_oenb[11] I |
| la_oenb[12] I |
| la_oenb[13] I |
| la_oenb[14] I |
| la_oenb[15] I |
| la_oenb[16] I |
| la_oenb[17] I |
| la_oenb[18] I |
| la_oenb[19] I |
| la_oenb[1] I |
| la_oenb[20] I |
| la_oenb[21] I |
| la_oenb[22] I |
| la_oenb[23] I |
| la_oenb[24] I |
| la_oenb[25] I |
| la_oenb[26] I |
| la_oenb[27] I |
| la_oenb[28] I |
| la_oenb[29] I |
| la_oenb[2] I |
| la_oenb[30] I |
| la_oenb[31] I |
| la_oenb[32] I |
| la_oenb[33] I |
| la_oenb[34] I |
| la_oenb[35] I |
| la_oenb[36] I |
| la_oenb[37] I |
| la_oenb[38] I |
| la_oenb[39] I |
| la_oenb[3] I |
| la_oenb[40] I |
| la_oenb[41] I |
| la_oenb[42] I |
| la_oenb[43] I |
| la_oenb[44] I |
| la_oenb[45] I |
| la_oenb[46] I |
| la_oenb[47] I |
| la_oenb[48] I |
| la_oenb[49] I |
| la_oenb[4] I |
| la_oenb[50] I |
| la_oenb[51] I |
| la_oenb[52] I |
| la_oenb[53] I |
| la_oenb[54] I |
| la_oenb[55] I |
| la_oenb[56] I |
| la_oenb[57] I |
| la_oenb[58] I |
| la_oenb[59] I |
| la_oenb[5] I |
| la_oenb[60] I |
| la_oenb[61] I |
| la_oenb[62] I |
| la_oenb[63] I |
| la_oenb[6] I |
| la_oenb[7] I |
| la_oenb[8] I |
| la_oenb[9] I |
| user_clock2 I |
| user_irq[0] O |
| user_irq[1] O |
| user_irq[2] O |
| wb_clk_i I |
| wb_rst_i I |
| wbs_ack_o O |
| wbs_adr_i[0] I |
| wbs_adr_i[10] I |
| wbs_adr_i[11] I |
| wbs_adr_i[12] I |
| wbs_adr_i[13] I |
| wbs_adr_i[14] I |
| wbs_adr_i[15] I |
| wbs_adr_i[16] I |
| wbs_adr_i[17] I |
| wbs_adr_i[18] I |
| wbs_adr_i[19] I |
| wbs_adr_i[1] I |
| wbs_adr_i[20] I |
| wbs_adr_i[21] I |
| wbs_adr_i[22] I |
| wbs_adr_i[23] I |
| wbs_adr_i[24] I |
| wbs_adr_i[25] I |
| wbs_adr_i[26] I |
| wbs_adr_i[27] I |
| wbs_adr_i[28] I |
| wbs_adr_i[29] I |
| wbs_adr_i[2] I |
| wbs_adr_i[30] I |
| wbs_adr_i[31] I |
| wbs_adr_i[3] I |
| wbs_adr_i[4] I |
| wbs_adr_i[5] I |
| wbs_adr_i[6] I |
| wbs_adr_i[7] I |
| wbs_adr_i[8] I |
| wbs_adr_i[9] I |
| wbs_cyc_i I |
| wbs_dat_i[0] I |
| wbs_dat_i[10] I |
| wbs_dat_i[11] I |
| wbs_dat_i[12] I |
| wbs_dat_i[13] I |
| wbs_dat_i[14] I |
| wbs_dat_i[15] I |
| wbs_dat_i[16] I |
| wbs_dat_i[17] I |
| wbs_dat_i[18] I |
| wbs_dat_i[19] I |
| wbs_dat_i[1] I |
| wbs_dat_i[20] I |
| wbs_dat_i[21] I |
| wbs_dat_i[22] I |
| wbs_dat_i[23] I |
| wbs_dat_i[24] I |
| wbs_dat_i[25] I |
| wbs_dat_i[26] I |
| wbs_dat_i[27] I |
| wbs_dat_i[28] I |
| wbs_dat_i[29] I |
| wbs_dat_i[2] I |
| wbs_dat_i[30] I |
| wbs_dat_i[31] I |
| wbs_dat_i[3] I |
| wbs_dat_i[4] I |
| wbs_dat_i[5] I |
| wbs_dat_i[6] I |
| wbs_dat_i[7] I |
| wbs_dat_i[8] I |
| wbs_dat_i[9] I |
| wbs_dat_o[0] O |
| wbs_dat_o[10] O |
| wbs_dat_o[11] O |
| wbs_dat_o[12] O |
| wbs_dat_o[13] O |
| wbs_dat_o[14] O |
| wbs_dat_o[15] O |
| wbs_dat_o[16] O |
| wbs_dat_o[17] O |
| wbs_dat_o[18] O |
| wbs_dat_o[19] O |
| wbs_dat_o[1] O |
| wbs_dat_o[20] O |
| wbs_dat_o[21] O |
| wbs_dat_o[22] O |
| wbs_dat_o[23] O |
| wbs_dat_o[24] O |
| wbs_dat_o[25] O |
| wbs_dat_o[26] O |
| wbs_dat_o[27] O |
| wbs_dat_o[28] O |
| wbs_dat_o[29] O |
| wbs_dat_o[2] O |
| wbs_dat_o[30] O |
| wbs_dat_o[31] O |
| wbs_dat_o[3] O |
| wbs_dat_o[4] O |
| wbs_dat_o[5] O |
| wbs_dat_o[6] O |
| wbs_dat_o[7] O |
| wbs_dat_o[8] O |
| wbs_dat_o[9] O |
| wbs_sel_i[0] I |
| wbs_sel_i[1] I |
| wbs_sel_i[2] I |
| wbs_sel_i[3] I |
| wbs_stb_i I |
| wbs_we_i I |
| |
| *D_NET *1 0.195403 |
| *CONN |
| *P io_in[0] I |
| *I *419:io_in[0] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[0] 0.0323536 |
| 2 *419:io_in[0] 0.0298529 |
| 3 *1:10 0.0298529 |
| 4 *1:8 0.0354948 |
| 5 *1:7 0.0354948 |
| 6 *1:5 0.0323536 |
| *RES |
| 1 io_in[0] *1:5 354.825 |
| 2 *1:5 *1:7 4.5 |
| 3 *1:7 *1:8 353.79 |
| 4 *1:8 *1:10 4.5 |
| 5 *1:10 *419:io_in[0] 324.045 |
| *END |
| |
| *D_NET *2 0.196605 |
| *CONN |
| *P io_in[10] I |
| *I *419:io_in[10] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[10] 0.000890476 |
| 2 *419:io_in[10] 0.0614299 |
| 3 *2:10 0.0614299 |
| 4 *2:8 0.0359821 |
| 5 *2:7 0.0368726 |
| *RES |
| 1 io_in[10] *2:7 13.725 |
| 2 *2:7 *2:8 359.19 |
| 3 *2:8 *2:10 4.5 |
| 4 *2:10 *419:io_in[10] 669.645 |
| *END |
| |
| *D_NET *3 0.211313 |
| *CONN |
| *P io_in[11] I |
| *I *419:io_in[11] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[11] 0.000280649 |
| 2 *419:io_in[11] 0.000253574 |
| 3 *3:16 0.0350765 |
| 4 *3:15 0.034823 |
| 5 *3:13 0.0702994 |
| 6 *3:11 0.0705801 |
| 7 *3:16 *91:10 0 |
| *RES |
| 1 io_in[11] *3:11 2.655 |
| 2 *3:11 *3:13 766.53 |
| 3 *3:13 *3:15 4.5 |
| 4 *3:15 *3:16 347.49 |
| 5 *3:16 *419:io_in[11] 11.5904 |
| *END |
| |
| *D_NET *4 0.263763 |
| *CONN |
| *P io_in[12] I |
| *I *419:io_in[12] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[12] 0.000215438 |
| 2 *419:io_in[12] 0.000881417 |
| 3 *4:16 0.0445163 |
| 4 *4:15 0.0436348 |
| 5 *4:13 0.0717957 |
| 6 *4:11 0.0720111 |
| 7 *4:16 *7:17 0.000572841 |
| 8 *4:16 *8:19 0.0301355 |
| *RES |
| 1 io_in[12] *4:11 2.115 |
| 2 *4:11 *4:13 782.91 |
| 3 *4:13 *4:15 4.5 |
| 4 *4:15 *4:16 455.85 |
| 5 *4:16 *419:io_in[12] 13.005 |
| *END |
| |
| *D_NET *5 0.222276 |
| *CONN |
| *P io_in[13] I |
| *I *419:io_in[13] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[13] 0.000145659 |
| 2 *419:io_in[13] 0.00107029 |
| 3 *5:16 0.0481195 |
| 4 *5:15 0.0470492 |
| 5 *5:13 0.0628727 |
| 6 *5:11 0.0630183 |
| 7 *419:io_in[13] *37:19 0 |
| 8 *5:16 *100:12 0 |
| *RES |
| 1 io_in[13] *5:11 1.575 |
| 2 *5:11 *5:13 686.97 |
| 3 *5:13 *5:15 4.5 |
| 4 *5:15 *5:16 470.07 |
| 5 *5:16 *419:io_in[13] 27.3874 |
| *END |
| |
| *D_NET *6 0.239127 |
| *CONN |
| *P io_in[14] I |
| *I *419:io_in[14] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[14] 0.00397136 |
| 2 *419:io_in[14] 0.000353687 |
| 3 *6:12 0.0543311 |
| 4 *6:11 0.0539774 |
| 5 *6:9 0.0607997 |
| 6 *6:7 0.064771 |
| 7 *419:io_in[14] *93:10 5.4397e-05 |
| 8 *6:12 *38:12 0 |
| 9 *6:12 *93:10 0.000868212 |
| *RES |
| 1 io_in[14] *6:7 43.425 |
| 2 *6:7 *6:9 664.2 |
| 3 *6:9 *6:11 4.5 |
| 4 *6:11 *6:12 541.89 |
| 5 *6:12 *419:io_in[14] 12.9052 |
| *END |
| |
| *D_NET *7 0.305791 |
| *CONN |
| *P io_in[15] I |
| *I *419:io_in[15] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[15] 0.00433622 |
| 2 *419:io_in[15] 0.000941763 |
| 3 *7:17 0.00325416 |
| 4 *7:12 0.0704213 |
| 5 *7:11 0.0681089 |
| 6 *7:9 0.055017 |
| 7 *7:7 0.0593532 |
| 8 *7:12 *32:19 0 |
| 9 *7:12 *39:17 0 |
| 10 *7:12 *39:21 0 |
| 11 *7:12 *61:11 0 |
| 12 *7:12 *70:11 0.00370839 |
| 13 *7:12 *72:14 0 |
| 14 *7:12 *87:13 0.0143612 |
| 15 *7:17 *8:19 0.0257164 |
| 16 *4:16 *7:17 0.000572841 |
| *RES |
| 1 io_in[15] *7:7 43.245 |
| 2 *7:7 *7:9 549.54 |
| 3 *7:9 *7:11 4.5 |
| 4 *7:11 *7:12 764.73 |
| 5 *7:12 *7:17 49.23 |
| 6 *7:17 *419:io_in[15] 8.865 |
| *END |
| |
| *D_NET *8 0.785433 |
| *CONN |
| *P io_in[16] I |
| *I *419:io_in[16] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[16] 0.000164983 |
| 2 *419:io_in[16] 0.00089733 |
| 3 *8:19 0.00409443 |
| 4 *8:18 0.0031971 |
| 5 *8:16 0.0290178 |
| 6 *8:15 0.0290178 |
| 7 *8:13 0.0595723 |
| 8 *8:11 0.0597373 |
| 9 *8:16 *40:12 0.000683868 |
| 10 *8:16 *61:11 0 |
| 11 *8:16 *71:11 0.000746036 |
| 12 *8:16 *79:11 0.447808 |
| 13 *8:16 *81:13 0.000663143 |
| 14 *8:16 *101:11 0.0732974 |
| 15 *8:19 *50:8 0.0206836 |
| 16 *4:16 *8:19 0.0301355 |
| 17 *7:17 *8:19 0.0257164 |
| *RES |
| 1 io_in[16] *8:11 1.935 |
| 2 *8:11 *8:13 594.99 |
| 3 *8:13 *8:15 4.5 |
| 4 *8:15 *8:16 656.55 |
| 5 *8:16 *8:18 4.5 |
| 6 *8:18 *8:19 80.91 |
| 7 *8:19 *419:io_in[16] 13.185 |
| *END |
| |
| *D_NET *9 0.430438 |
| *CONN |
| *P io_in[17] I |
| *I *419:io_in[17] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[17] 0.00073246 |
| 2 *419:io_in[17] 0.00223037 |
| 3 *9:14 0.00824978 |
| 4 *9:13 0.00601941 |
| 5 *9:11 0.0569686 |
| 6 *9:10 0.0569686 |
| 7 *9:8 0.0238198 |
| 8 *9:7 0.0245522 |
| 9 *9:8 *13:10 0 |
| 10 *9:8 *46:13 0.00389597 |
| 11 *9:8 *46:15 0.0129313 |
| 12 *9:8 *48:11 0.0164128 |
| 13 *9:8 *85:11 0.056388 |
| 14 *9:8 *87:17 0.115698 |
| 15 *9:14 *49:17 0.0455705 |
| *RES |
| 1 io_in[17] *9:7 11.025 |
| 2 *9:7 *9:8 416.97 |
| 3 *9:8 *9:10 4.5 |
| 4 *9:10 *9:11 569.61 |
| 5 *9:11 *9:13 4.5 |
| 6 *9:13 *9:14 93.15 |
| 7 *9:14 *419:io_in[17] 34.963 |
| *END |
| |
| *D_NET *10 0.312395 |
| *CONN |
| *P io_in[18] I |
| *I *419:io_in[18] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[18] 0.000104982 |
| 2 *419:io_in[18] 0.000707736 |
| 3 *10:22 0.00438518 |
| 4 *10:21 0.00391463 |
| 5 *10:16 0.0183155 |
| 6 *10:15 0.0180783 |
| 7 *10:13 0.0693492 |
| 8 *10:11 0.0694542 |
| 9 *10:16 *45:14 0.0777535 |
| 10 *10:16 *75:10 6.21698e-05 |
| 11 *10:21 *30:16 0.00411217 |
| 12 *10:21 *68:10 0.00046262 |
| 13 *10:22 *59:8 0.0439538 |
| 14 *10:22 *90:8 0.00174075 |
| *RES |
| 1 io_in[18] *10:11 1.395 |
| 2 *10:11 *10:13 692.01 |
| 3 *10:13 *10:15 4.5 |
| 4 *10:15 *10:16 337.77 |
| 5 *10:16 *10:21 15.03 |
| 6 *10:21 *10:22 71.19 |
| 7 *10:22 *419:io_in[18] 10.845 |
| *END |
| |
| *D_NET *11 0.243974 |
| *CONN |
| *P io_in[19] I |
| *I *419:io_in[19] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[19] 0.000950832 |
| 2 *419:io_in[19] 0.00112027 |
| 3 *11:11 0.0649591 |
| 4 *11:10 0.0638389 |
| 5 *11:8 0.0311276 |
| 6 *11:7 0.0320784 |
| 7 *11:8 io_oeb[14] 0 |
| 8 *11:8 io_oeb[21] 0 |
| 9 *11:8 *13:10 0 |
| 10 *11:8 *14:10 0 |
| 11 *11:11 *74:8 0.0498985 |
| *RES |
| 1 io_in[19] *11:7 13.725 |
| 2 *11:7 *11:8 339.57 |
| 3 *11:8 *11:10 4.5 |
| 4 *11:10 *11:11 669.87 |
| 5 *11:11 *419:io_in[19] 15.705 |
| *END |
| |
| *D_NET *12 0.182383 |
| *CONN |
| *P io_in[1] I |
| *I *419:io_in[1] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[1] 0.000280649 |
| 2 *419:io_in[1] 0.038048 |
| 3 *12:18 0.038048 |
| 4 *12:16 0.0286075 |
| 5 *12:15 0.0286075 |
| 6 *12:13 0.0242554 |
| 7 *12:11 0.0245361 |
| *RES |
| 1 io_in[1] *12:11 2.655 |
| 2 *12:11 *12:13 265.77 |
| 3 *12:13 *12:15 4.5 |
| 4 *12:15 *12:16 285.21 |
| 5 *12:16 *12:18 4.5 |
| 6 *12:18 *419:io_in[1] 413.145 |
| *END |
| |
| *D_NET *13 0.162664 |
| *CONN |
| *P io_in[20] I |
| *I *419:io_in[20] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[20] 0.00097235 |
| 2 *419:io_in[20] 0.0090363 |
| 3 *13:13 0.0090363 |
| 4 *13:11 0.0682775 |
| 5 *13:10 0.0692499 |
| 6 *419:io_in[20] *89:14 0.00609185 |
| 7 *9:8 *13:10 0 |
| 8 *11:8 *13:10 0 |
| *RES |
| 1 io_in[20] *13:10 18.495 |
| 2 *13:10 *13:11 681.03 |
| 3 *13:11 *13:13 4.5 |
| 4 *13:13 *419:io_in[20] 124.245 |
| *END |
| |
| *D_NET *14 0.143401 |
| *CONN |
| *P io_in[21] I |
| *I *419:io_in[21] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[21] 0.00115169 |
| 2 *419:io_in[21] 7.31006e-05 |
| 3 *14:17 0.00256769 |
| 4 *14:11 0.0604352 |
| 5 *14:10 0.0590923 |
| 6 *14:10 *87:17 0 |
| 7 *14:17 *37:19 0.0200808 |
| 8 *11:8 *14:10 0 |
| *RES |
| 1 io_in[21] *14:10 19.575 |
| 2 *14:10 *14:11 579.15 |
| 3 *14:11 *14:17 46.8 |
| 4 *14:17 *419:io_in[21] 9.74739 |
| *END |
| |
| *D_NET *15 0.152061 |
| *CONN |
| *P io_in[22] I |
| *I *419:io_in[22] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[22] 0.000290594 |
| 2 *419:io_in[22] 0.000416581 |
| 3 *15:19 0.00269729 |
| 4 *15:13 0.0616461 |
| 5 *15:11 0.059656 |
| 6 *15:13 *91:10 0.000393572 |
| 7 *15:19 *87:8 0.0208064 |
| 8 *15:19 *101:11 0.00615481 |
| *RES |
| 1 io_in[22] *15:11 3.015 |
| 2 *15:11 *15:13 594.63 |
| 3 *15:13 *15:19 48.42 |
| 4 *15:19 *419:io_in[22] 8.145 |
| *END |
| |
| *D_NET *16 0.140372 |
| *CONN |
| *P io_in[23] I |
| *I *419:io_in[23] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[23] 0.000104982 |
| 2 *419:io_in[23] 0.0094561 |
| 3 *16:15 0.0094561 |
| 4 *16:13 0.0606248 |
| 5 *16:11 0.0607298 |
| 6 *16:13 *18:16 0 |
| *RES |
| 1 io_in[23] *16:11 1.395 |
| 2 *16:11 *16:13 605.61 |
| 3 *16:13 *16:15 4.5 |
| 4 *16:15 *419:io_in[23] 100.125 |
| *END |
| |
| *D_NET *17 0.388068 |
| *CONN |
| *P io_in[24] I |
| *I *419:io_in[24] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[24] 0.0262269 |
| 2 *419:io_in[24] 0.00014207 |
| 3 *17:8 0.0478583 |
| 4 *17:7 0.0477163 |
| 5 *17:5 0.0262269 |
| 6 *17:8 *21:16 0.214017 |
| 7 *17:8 *40:12 0.00153439 |
| 8 *17:8 *55:14 0 |
| 9 *17:8 *66:8 0.0206836 |
| 10 *17:8 *101:8 0.00366209 |
| *RES |
| 1 io_in[24] *17:5 285.705 |
| 2 *17:5 *17:7 4.5 |
| 3 *17:7 *17:8 635.67 |
| 4 *17:8 *419:io_in[24] 5.985 |
| *END |
| |
| *D_NET *18 0.155465 |
| *CONN |
| *P io_in[25] I |
| *I *419:io_in[25] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[25] 0.000237175 |
| 2 *419:io_in[25] 0.00952647 |
| 3 *18:18 0.00952647 |
| 4 *18:16 0.0599673 |
| 5 *18:15 0.0599673 |
| 6 *18:13 0.00800164 |
| 7 *18:11 0.00823881 |
| 8 *16:13 *18:16 0 |
| *RES |
| 1 io_in[25] *18:11 2.295 |
| 2 *18:11 *18:13 87.21 |
| 3 *18:13 *18:15 4.5 |
| 4 *18:15 *18:16 598.95 |
| 5 *18:16 *18:18 4.5 |
| 6 *18:18 *419:io_in[25] 101.565 |
| *END |
| |
| *D_NET *19 0.125748 |
| *CONN |
| *P io_in[26] I |
| *I *419:io_in[26] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[26] 0.00010158 |
| 2 *419:io_in[26] 0.0015846 |
| 3 *19:16 0.0467772 |
| 4 *19:15 0.0451926 |
| 5 *19:13 0.0159954 |
| 6 *19:11 0.0160969 |
| *RES |
| 1 io_in[26] *19:11 1.215 |
| 2 *19:11 *19:13 173.61 |
| 3 *19:13 *19:15 4.5 |
| 4 *19:15 *19:16 451.53 |
| 5 *19:16 *419:io_in[26] 19.665 |
| *END |
| |
| *D_NET *20 0.124098 |
| *CONN |
| *P io_in[27] I |
| *I *419:io_in[27] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[27] 0.000310538 |
| 2 *419:io_in[27] 0.000985163 |
| 3 *20:16 0.0377683 |
| 4 *20:15 0.0367831 |
| 5 *20:13 0.023934 |
| 6 *20:11 0.0242445 |
| 7 *419:io_in[27] *52:14 6.90477e-06 |
| 8 *419:io_in[27] *93:11 0 |
| 9 *419:io_in[27] *98:13 6.52783e-05 |
| *RES |
| 1 io_in[27] *20:11 2.835 |
| 2 *20:11 *20:13 233.01 |
| 3 *20:13 *20:15 4.5 |
| 4 *20:15 *20:16 367.47 |
| 5 *20:16 *419:io_in[27] 27.7474 |
| *END |
| |
| *D_NET *21 0.31322 |
| *CONN |
| *P io_in[28] I |
| *I *419:io_in[28] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[28] 0.000167681 |
| 2 *419:io_in[28] 0.000172243 |
| 3 *21:16 0.0173921 |
| 4 *21:15 0.0172199 |
| 5 *21:13 0.0294332 |
| 6 *21:11 0.0296009 |
| 7 *21:16 *101:8 0.00521694 |
| 8 *17:8 *21:16 0.214017 |
| *RES |
| 1 io_in[28] *21:11 1.755 |
| 2 *21:11 *21:13 285.93 |
| 3 *21:13 *21:15 4.5 |
| 4 *21:15 *21:16 313.83 |
| 5 *21:16 *419:io_in[28] 6.165 |
| *END |
| |
| *D_NET *22 0.242186 |
| *CONN |
| *P io_in[29] I |
| *I *419:io_in[29] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[29] 0.0155824 |
| 2 *419:io_in[29] 0.000295132 |
| 3 *22:11 0.00283812 |
| 4 *22:10 0.00254299 |
| 5 *22:8 0.0339271 |
| 6 *22:7 0.0339271 |
| 7 *22:5 0.0155824 |
| 8 *22:11 *42:8 0.0551395 |
| 9 *22:11 *58:8 0.00615439 |
| 10 *22:11 *64:8 0.00225883 |
| 11 *22:11 *73:8 0.0573774 |
| 12 *22:11 *89:8 0.000335457 |
| 13 *22:11 *96:8 0.0162253 |
| *RES |
| 1 io_in[29] *22:5 168.165 |
| 2 *22:5 *22:7 4.5 |
| 3 *22:7 *22:8 338.13 |
| 4 *22:8 *22:10 4.5 |
| 5 *22:10 *22:11 113.13 |
| 6 *22:11 *419:io_in[29] 7.065 |
| *END |
| |
| *D_NET *23 0.157699 |
| *CONN |
| *P io_in[2] I |
| *I *419:io_in[2] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[2] 0.000215438 |
| 2 *419:io_in[2] 0.0493593 |
| 3 *23:18 0.0493593 |
| 4 *23:16 0.016359 |
| 5 *23:15 0.016359 |
| 6 *23:13 0.0129157 |
| 7 *23:11 0.0131311 |
| *RES |
| 1 io_in[2] *23:11 2.115 |
| 2 *23:11 *23:13 141.57 |
| 3 *23:13 *23:15 4.5 |
| 4 *23:15 *23:16 163.17 |
| 5 *23:16 *23:18 4.5 |
| 6 *23:18 *419:io_in[2] 537.345 |
| *END |
| |
| *D_NET *24 0.0777088 |
| *CONN |
| *P io_in[30] I |
| *I *419:io_in[30] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[30] 0.000237175 |
| 2 *419:io_in[30] 0.00121317 |
| 3 *24:16 0.0174712 |
| 4 *24:15 0.0162581 |
| 5 *24:13 0.0211227 |
| 6 *24:11 0.0213599 |
| 7 *419:io_in[30] *49:13 0 |
| 8 *419:io_in[30] *93:11 0 |
| 9 *419:io_in[30] *98:13 4.66274e-05 |
| 10 *419:io_in[30] *98:14 0 |
| *RES |
| 1 io_in[30] *24:11 2.295 |
| 2 *24:11 *24:13 227.61 |
| 3 *24:13 *24:15 4.5 |
| 4 *24:15 *24:16 162.27 |
| 5 *24:16 *419:io_in[30] 29.9074 |
| *END |
| |
| *D_NET *25 0.165314 |
| *CONN |
| *P io_in[31] I |
| *I *419:io_in[31] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[31] 0.00010158 |
| 2 *419:io_in[31] 0.000588953 |
| 3 *25:19 0.00163467 |
| 4 *25:18 0.00104572 |
| 5 *25:16 0.0204448 |
| 6 *25:15 0.0204448 |
| 7 *25:13 0.0158561 |
| 8 *25:11 0.0159577 |
| 9 *25:19 *54:8 0.032266 |
| 10 *25:19 *59:8 0.00160165 |
| 11 *25:19 *63:8 0.0531548 |
| 12 *25:19 *86:13 0.00221731 |
| *RES |
| 1 io_in[31] *25:11 1.215 |
| 2 *25:11 *25:13 170.91 |
| 3 *25:13 *25:15 4.5 |
| 4 *25:15 *25:16 203.13 |
| 5 *25:16 *25:18 4.5 |
| 6 *25:18 *25:19 76.95 |
| 7 *25:19 *419:io_in[31] 9.765 |
| *END |
| |
| *D_NET *26 0.119046 |
| *CONN |
| *P io_in[32] I |
| *I *419:io_in[32] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[32] 0.000310538 |
| 2 *419:io_in[32] 0.000751389 |
| 3 *26:16 0.00527137 |
| 4 *26:15 0.00451998 |
| 5 *26:13 0.0272117 |
| 6 *26:11 0.0275223 |
| 7 *26:16 *60:8 0.0534583 |
| *RES |
| 1 io_in[32] *26:11 2.835 |
| 2 *26:11 *26:13 291.51 |
| 3 *26:13 *26:15 4.5 |
| 4 *26:15 *26:16 78.39 |
| 5 *26:16 *419:io_in[32] 11.745 |
| *END |
| |
| *D_NET *27 0.0400662 |
| *CONN |
| *P io_in[33] I |
| *I *419:io_in[33] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[33] 0.00156645 |
| 2 *419:io_in[33] 0.0184666 |
| 3 *27:10 0.0200331 |
| *RES |
| 1 io_in[33] *27:10 24.795 |
| 2 *27:10 *419:io_in[33] 178.425 |
| *END |
| |
| *D_NET *28 0.0405681 |
| *CONN |
| *P io_in[34] I |
| *I *419:io_in[34] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[34] 0.0194104 |
| 2 *419:io_in[34] 0.0008736 |
| 3 *28:5 0.020284 |
| 4 *28:5 *59:8 0 |
| 5 *28:5 *314:8 0 |
| *RES |
| 1 io_in[34] *28:5 211.005 |
| 2 *28:5 *419:io_in[34] 11.925 |
| *END |
| |
| *D_NET *29 0.0577165 |
| *CONN |
| *P io_in[35] I |
| *I *419:io_in[35] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[35] 0.000237175 |
| 2 *419:io_in[35] 0.000147297 |
| 3 *29:22 0.00758816 |
| 4 *29:21 0.00744087 |
| 5 *29:19 0.0126837 |
| 6 *29:18 0.0131 |
| 7 *29:13 0.00834915 |
| 8 *29:11 0.00817004 |
| 9 *29:13 *105:10 0 |
| *RES |
| 1 io_in[35] *29:11 2.295 |
| 2 *29:11 *29:13 85.95 |
| 3 *29:13 *29:18 13.05 |
| 4 *29:18 *29:19 137.79 |
| 5 *29:19 *29:21 4.5 |
| 6 *29:21 *29:22 73.71 |
| 7 *29:22 *419:io_in[35] 1.485 |
| *END |
| |
| *D_NET *30 0.124911 |
| *CONN |
| *P io_in[36] I |
| *I *419:io_in[36] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[36] 0.00010158 |
| 2 *419:io_in[36] 0.00014207 |
| 3 *30:16 0.0121588 |
| 4 *30:15 0.0120168 |
| 5 *30:13 0.0262048 |
| 6 *30:11 0.0263064 |
| 7 *30:16 *66:8 0.0427789 |
| 8 *30:16 *68:10 0.00108942 |
| 9 *30:16 *68:12 0 |
| 10 *10:21 *30:16 0.00411217 |
| *RES |
| 1 io_in[36] *30:11 1.215 |
| 2 *30:11 *30:13 285.75 |
| 3 *30:13 *30:15 4.5 |
| 4 *30:15 *30:16 154.53 |
| 5 *30:16 *419:io_in[36] 5.985 |
| *END |
| |
| *D_NET *31 0.0937783 |
| *CONN |
| *P io_in[37] I |
| *I *419:io_in[37] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[37] 0.000310538 |
| 2 *419:io_in[37] 0.00937309 |
| 3 *31:18 0.00937309 |
| 4 *31:16 0.0289142 |
| 5 *31:15 0.0289142 |
| 6 *31:13 0.00829137 |
| 7 *31:11 0.00860191 |
| *RES |
| 1 io_in[37] *31:11 2.835 |
| 2 *31:11 *31:13 89.91 |
| 3 *31:13 *31:15 4.5 |
| 4 *31:15 *31:16 288.45 |
| 5 *31:16 *31:18 4.5 |
| 6 *31:18 *419:io_in[37] 98.865 |
| *END |
| |
| *D_NET *32 0.340504 |
| *CONN |
| *P io_in[3] I |
| *I *419:io_in[3] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[3] 0.000145659 |
| 2 *419:io_in[3] 0.000587619 |
| 3 *32:19 0.0169639 |
| 4 *32:18 0.0163763 |
| 5 *32:16 0.0172074 |
| 6 *32:15 0.0172074 |
| 7 *32:13 0.0402882 |
| 8 *32:11 0.0404339 |
| 9 *32:19 *39:17 0.00700417 |
| 10 *32:19 *39:21 0.0165993 |
| 11 *32:19 *49:13 0.000686965 |
| 12 *32:19 *72:14 0.143674 |
| 13 *32:19 *92:11 0.000264222 |
| 14 *32:19 *110:13 0.0230646 |
| 15 *7:12 *32:19 0 |
| *RES |
| 1 io_in[3] *32:11 1.575 |
| 2 *32:11 *32:13 441.27 |
| 3 *32:13 *32:15 4.5 |
| 4 *32:15 *32:16 170.37 |
| 5 *32:16 *32:18 4.5 |
| 6 *32:18 *32:19 304.47 |
| 7 *32:19 *419:io_in[3] 19.0174 |
| *END |
| |
| *D_NET *33 0.133035 |
| *CONN |
| *P io_in[4] I |
| *I *419:io_in[4] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[4] 0.00395713 |
| 2 *419:io_in[4] 0.0285873 |
| 3 *33:14 0.0324349 |
| 4 *33:9 0.0333411 |
| 5 *33:7 0.0334507 |
| 6 *33:9 *75:11 0.00126412 |
| *RES |
| 1 io_in[4] *33:7 43.425 |
| 2 *33:7 *33:9 325.44 |
| 3 *33:9 *33:14 46.89 |
| 4 *33:14 *419:io_in[4] 310.545 |
| *END |
| |
| *D_NET *34 0.126264 |
| *CONN |
| *P io_in[5] I |
| *I *419:io_in[5] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[5] 0.0602513 |
| 2 *419:io_in[5] 0.00288057 |
| 3 *34:5 0.0631318 |
| *RES |
| 1 io_in[5] *34:5 657.585 |
| 2 *34:5 *419:io_in[5] 37.935 |
| *END |
| |
| *D_NET *35 0.19885 |
| *CONN |
| *P io_in[6] I |
| *I *419:io_in[6] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[6] 0.000280649 |
| 2 *419:io_in[6] 0.0015154 |
| 3 *35:19 0.0268495 |
| 4 *35:18 0.0268491 |
| 5 *35:13 0.0386924 |
| 6 *35:11 0.037458 |
| 7 *419:io_in[6] *52:13 0 |
| 8 *35:19 *419:io_in[9] 0 |
| 9 *35:19 *51:17 0.0672054 |
| *RES |
| 1 io_in[6] *35:11 2.655 |
| 2 *35:11 *35:13 404.73 |
| 3 *35:13 *35:18 24.03 |
| 4 *35:18 *35:19 318.69 |
| 5 *35:19 *419:io_in[6] 27.3404 |
| *END |
| |
| *D_NET *36 0.154907 |
| *CONN |
| *P io_in[7] I |
| *I *419:io_in[7] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[7] 0.000215438 |
| 2 *419:io_in[7] 0.0300633 |
| 3 *36:18 0.0300633 |
| 4 *36:16 0.0148348 |
| 5 *36:15 0.0148348 |
| 6 *36:13 0.0323397 |
| 7 *36:11 0.0325552 |
| *RES |
| 1 io_in[7] *36:11 2.115 |
| 2 *36:11 *36:13 352.17 |
| 3 *36:13 *36:15 4.5 |
| 4 *36:15 *36:16 147.51 |
| 5 *36:16 *36:18 4.5 |
| 6 *36:18 *419:io_in[7] 326.745 |
| *END |
| |
| *D_NET *37 0.188182 |
| *CONN |
| *P io_in[8] I |
| *I *419:io_in[8] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[8] 0.000145659 |
| 2 *419:io_in[8] 0.000980041 |
| 3 *37:19 0.0291341 |
| 4 *37:18 0.0281541 |
| 5 *37:16 0.0147484 |
| 6 *37:15 0.0147484 |
| 7 *37:13 0.0362613 |
| 8 *37:11 0.0364069 |
| 9 *37:19 *93:11 0.00752255 |
| 10 *37:19 *97:13 0 |
| 11 *419:io_in[13] *37:19 0 |
| 12 *14:17 *37:19 0.0200808 |
| *RES |
| 1 io_in[8] *37:11 1.575 |
| 2 *37:11 *37:13 395.37 |
| 3 *37:13 *37:15 4.5 |
| 4 *37:15 *37:16 147.33 |
| 5 *37:16 *37:18 4.5 |
| 6 *37:18 *37:19 323.37 |
| 7 *37:19 *419:io_in[8] 22.7974 |
| *END |
| |
| *D_NET *38 0.175364 |
| *CONN |
| *P io_in[9] I |
| *I *419:io_in[9] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[9] 0.00401407 |
| 2 *419:io_in[9] 0.00139047 |
| 3 *38:12 0.0225204 |
| 4 *38:11 0.0211299 |
| 5 *38:9 0.0610837 |
| 6 *38:7 0.0650977 |
| 7 *419:io_in[9] *93:11 0.000127448 |
| 8 *6:12 *38:12 0 |
| 9 *35:19 *419:io_in[9] 0 |
| *RES |
| 1 io_in[9] *38:7 43.425 |
| 2 *38:7 *38:9 665.64 |
| 3 *38:9 *38:11 4.5 |
| 4 *38:11 *38:12 210.87 |
| 5 *38:12 *419:io_in[9] 32.2474 |
| *END |
| |
| *D_NET *39 0.214907 |
| *CONN |
| *P io_oeb[0] O |
| *I *419:io_oeb[0] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[0] 0.000310538 |
| 2 *419:io_oeb[0] 0.00130657 |
| 3 *39:25 0.0607264 |
| 4 *39:24 0.0604159 |
| 5 *39:22 0.032346 |
| 6 *39:21 0.0336188 |
| 7 *39:17 0.00257944 |
| 8 *7:12 *39:17 0 |
| 9 *7:12 *39:21 0 |
| 10 *32:19 *39:17 0.00700417 |
| 11 *32:19 *39:21 0.0165993 |
| *RES |
| 1 *419:io_oeb[0] *39:17 31.0774 |
| 2 *39:17 *39:21 28.53 |
| 3 *39:21 *39:22 321.39 |
| 4 *39:22 *39:24 4.5 |
| 5 *39:24 *39:25 662.67 |
| 6 *39:25 io_oeb[0] 2.835 |
| *END |
| |
| *D_NET *40 0.204425 |
| *CONN |
| *P io_oeb[10] O |
| *I *419:io_oeb[10] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[10] 0.000310538 |
| 2 *419:io_oeb[10] 0.00106035 |
| 3 *40:16 0.0604927 |
| 4 *40:15 0.0601822 |
| 5 *40:13 0.0324695 |
| 6 *40:12 0.0335298 |
| 7 *40:12 *55:14 0 |
| 8 *40:12 *61:11 0.0141125 |
| 9 *40:12 *101:11 4.89586e-05 |
| 10 *8:16 *40:12 0.000683868 |
| 11 *17:8 *40:12 0.00153439 |
| *RES |
| 1 *419:io_oeb[10] *40:12 32.625 |
| 2 *40:12 *40:13 324.27 |
| 3 *40:13 *40:15 4.5 |
| 4 *40:15 *40:16 657.27 |
| 5 *40:16 io_oeb[10] 2.835 |
| *END |
| |
| *D_NET *41 0.249775 |
| *CONN |
| *P io_oeb[11] O |
| *I *419:io_oeb[11] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[11] 0.00111512 |
| 2 *419:io_oeb[11] 0.0375001 |
| 3 *41:8 0.0420594 |
| 4 *41:7 0.0409443 |
| 5 *41:5 0.0375001 |
| 6 *41:5 *110:17 0.0906558 |
| *RES |
| 1 *419:io_oeb[11] *41:5 666.945 |
| 2 *41:5 *41:7 4.5 |
| 3 *41:7 *41:8 408.87 |
| 4 *41:8 io_oeb[11] 16.425 |
| *END |
| |
| *D_NET *42 0.372954 |
| *CONN |
| *P io_oeb[12] O |
| *I *419:io_oeb[12] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[12] 0.000167681 |
| 2 *419:io_oeb[12] 0.000308523 |
| 3 *42:14 0.0598027 |
| 4 *42:13 0.059635 |
| 5 *42:11 0.0556261 |
| 6 *42:10 0.0556261 |
| 7 *42:8 0.00248335 |
| 8 *42:7 0.00279187 |
| 9 *42:8 *44:8 0.0551395 |
| 10 *42:8 *53:8 0.000725313 |
| 11 *42:8 *64:8 0.0185872 |
| 12 *42:8 *73:8 0.00692089 |
| 13 *22:11 *42:8 0.0551395 |
| *RES |
| 1 *419:io_oeb[12] *42:7 7.245 |
| 2 *42:7 *42:8 109.89 |
| 3 *42:8 *42:10 4.5 |
| 4 *42:10 *42:11 554.31 |
| 5 *42:11 *42:13 4.5 |
| 6 *42:13 *42:14 651.87 |
| 7 *42:14 io_oeb[12] 1.755 |
| *END |
| |
| *D_NET *43 0.244656 |
| *CONN |
| *P io_oeb[13] O |
| *I *419:io_oeb[13] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[13] 0.00010158 |
| 2 *419:io_oeb[13] 0.000379914 |
| 3 *43:13 0.0698042 |
| 4 *43:12 0.0697026 |
| 5 *43:10 0.0520407 |
| 6 *43:9 0.0524206 |
| 7 *43:10 *70:10 0.000205865 |
| *RES |
| 1 *419:io_oeb[13] *43:9 12.9052 |
| 2 *43:9 *43:10 520.29 |
| 3 *43:10 *43:12 4.5 |
| 4 *43:12 *43:13 761.13 |
| 5 *43:13 io_oeb[13] 1.215 |
| *END |
| |
| *D_NET *44 0.348745 |
| *CONN |
| *P io_oeb[14] O |
| *I *419:io_oeb[14] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[14] 0.0568877 |
| 2 *419:io_oeb[14] 0.000332209 |
| 3 *44:13 0.0568877 |
| 4 *44:11 0.0686129 |
| 5 *44:10 0.0686129 |
| 6 *44:8 0.00253211 |
| 7 *44:7 0.00286432 |
| 8 *44:8 *53:8 0.0231874 |
| 9 *44:8 *73:8 0.000745992 |
| 10 *44:8 *78:8 0.00244792 |
| 11 *44:8 *86:14 0.0104942 |
| 12 *11:8 io_oeb[14] 0 |
| 13 *42:8 *44:8 0.0551395 |
| *RES |
| 1 *419:io_oeb[14] *44:7 7.425 |
| 2 *44:7 *44:8 109.53 |
| 3 *44:8 *44:10 4.5 |
| 4 *44:10 *44:11 684.09 |
| 5 *44:11 *44:13 4.5 |
| 6 *44:13 io_oeb[14] 622.125 |
| *END |
| |
| *D_NET *45 0.39008 |
| *CONN |
| *P io_oeb[15] O |
| *I *419:io_oeb[15] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[15] 0.000224243 |
| 2 *419:io_oeb[15] 0.00238098 |
| 3 *45:17 0.0695672 |
| 4 *45:16 0.0693429 |
| 5 *45:14 0.0201261 |
| 6 *45:13 0.0225071 |
| 7 *45:13 *53:8 0 |
| 8 *45:13 *63:7 0 |
| 9 *45:13 *63:8 0.0163505 |
| 10 *45:13 *72:8 0.00012693 |
| 11 *45:13 *86:14 0 |
| 12 *45:14 *75:10 0.000901462 |
| 13 *45:14 *82:11 0.034504 |
| 14 *45:14 *109:11 0.0762946 |
| 15 *10:16 *45:14 0.0777535 |
| *RES |
| 1 *419:io_oeb[15] *45:13 47.565 |
| 2 *45:13 *45:14 602.19 |
| 3 *45:14 *45:16 4.5 |
| 4 *45:16 *45:17 692.37 |
| 5 *45:17 io_oeb[15] 2.475 |
| *END |
| |
| *D_NET *46 0.225466 |
| *CONN |
| *P io_oeb[16] O |
| *I *419:io_oeb[16] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[16] 0.000708774 |
| 2 *419:io_oeb[16] 0.0377949 |
| 3 *46:15 0.00491899 |
| 4 *46:13 0.00520844 |
| 5 *46:8 0.0613695 |
| 6 *46:7 0.0603713 |
| 7 *46:5 0.0377949 |
| 8 *46:8 io_out[17] 3.68254e-05 |
| 9 *46:13 *85:11 0.000435189 |
| 10 *9:8 *46:13 0.00389597 |
| 11 *9:8 *46:15 0.0129313 |
| *RES |
| 1 *419:io_oeb[16] *46:5 410.445 |
| 2 *46:5 *46:7 4.5 |
| 3 *46:7 *46:8 602.73 |
| 4 *46:8 *46:13 22.41 |
| 5 *46:13 *46:15 54.36 |
| 6 *46:15 io_oeb[16] 10.845 |
| *END |
| |
| *D_NET *47 0.217291 |
| *CONN |
| *P io_oeb[17] O |
| *I *419:io_oeb[17] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[17] 0.000164983 |
| 2 *419:io_oeb[17] 0.00310524 |
| 3 *47:17 0.0684647 |
| 4 *47:16 0.0682997 |
| 5 *47:14 0.0336875 |
| 6 *47:13 0.0336875 |
| 7 *47:11 0.00310524 |
| 8 *47:11 *75:11 0.00428972 |
| 9 *47:11 *84:10 0.00248679 |
| 10 *47:11 *86:14 0 |
| *RES |
| 1 *419:io_oeb[17] *47:11 45.945 |
| 2 *47:11 *47:13 4.5 |
| 3 *47:13 *47:14 366.75 |
| 4 *47:14 *47:16 4.5 |
| 5 *47:16 *47:17 681.57 |
| 6 *47:17 io_oeb[17] 1.935 |
| *END |
| |
| *D_NET *48 0.214596 |
| *CONN |
| *P io_oeb[18] O |
| *I *419:io_oeb[18] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[18] 0.000635658 |
| 2 *419:io_oeb[18] 0.0139917 |
| 3 *48:11 0.00675403 |
| 4 *48:10 0.00611837 |
| 5 *48:8 0.0624614 |
| 6 *48:7 0.0624614 |
| 7 *48:5 0.0139917 |
| 8 *48:11 *87:17 0.0317688 |
| 9 *9:8 *48:11 0.0164128 |
| *RES |
| 1 *419:io_oeb[18] *48:5 151.245 |
| 2 *48:5 *48:7 4.5 |
| 3 *48:7 *48:8 623.25 |
| 4 *48:8 *48:10 4.5 |
| 5 *48:10 *48:11 117.27 |
| 6 *48:11 io_oeb[18] 10.665 |
| *END |
| |
| *D_NET *49 0.210993 |
| *CONN |
| *P io_oeb[19] O |
| *I *419:io_oeb[19] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[19] 0.000104982 |
| 2 *419:io_oeb[19] 0.00158787 |
| 3 *49:20 0.0577727 |
| 4 *49:19 0.0576677 |
| 5 *49:17 0.0155125 |
| 6 *49:16 0.0169152 |
| 7 *49:13 0.00299053 |
| 8 *49:13 *98:13 0.0121229 |
| 9 *49:16 *98:13 6.13758e-05 |
| 10 *419:io_in[30] *49:13 0 |
| 11 *9:14 *49:17 0.0455705 |
| 12 *32:19 *49:13 0.000686965 |
| *RES |
| 1 *419:io_oeb[19] *49:13 44.4874 |
| 2 *49:13 *49:16 18.09 |
| 3 *49:16 *49:17 197.01 |
| 4 *49:17 *49:19 4.5 |
| 5 *49:19 *49:20 576.27 |
| 6 *49:20 io_oeb[19] 1.395 |
| *END |
| |
| *D_NET *50 0.20375 |
| *CONN |
| *P io_oeb[1] O |
| *I *419:io_oeb[1] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[1] 0.000237175 |
| 2 *419:io_oeb[1] 0.000867157 |
| 3 *50:11 0.0716912 |
| 4 *50:10 0.0714541 |
| 5 *50:8 0.018975 |
| 6 *50:7 0.0198422 |
| 7 *8:19 *50:8 0.0206836 |
| *RES |
| 1 *419:io_oeb[1] *50:7 13.005 |
| 2 *50:7 *50:8 202.05 |
| 3 *50:8 *50:10 4.5 |
| 4 *50:10 *50:11 782.91 |
| 5 *50:11 io_oeb[1] 2.295 |
| *END |
| |
| *D_NET *51 0.207378 |
| *CONN |
| *P io_oeb[20] O |
| *I *419:io_oeb[20] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[20] 0.000224243 |
| 2 *419:io_oeb[20] 0.0017478 |
| 3 *51:20 0.0586936 |
| 4 *51:19 0.0584693 |
| 5 *51:17 0.00712691 |
| 6 *51:16 0.00887471 |
| 7 *51:16 *92:11 0.00503575 |
| 8 *35:19 *51:17 0.0672054 |
| *RES |
| 1 *419:io_oeb[20] *51:16 42.0574 |
| 2 *51:16 *51:17 118.89 |
| 3 *51:17 *51:19 4.5 |
| 4 *51:19 *51:20 584.19 |
| 5 *51:20 io_oeb[20] 2.475 |
| *END |
| |
| *D_NET *52 0.12065 |
| *CONN |
| *P io_oeb[21] O |
| *I *419:io_oeb[21] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[21] 0.00112874 |
| 2 *419:io_oeb[21] 0.00103053 |
| 3 *52:14 0.0592491 |
| 4 *52:13 0.0591509 |
| 5 io_oeb[21] *87:17 0 |
| 6 *52:13 *93:11 0 |
| 7 *52:13 *98:13 8.39292e-05 |
| 8 *419:io_in[27] *52:14 6.90477e-06 |
| 9 *419:io_in[6] *52:13 0 |
| 10 *11:8 io_oeb[21] 0 |
| *RES |
| 1 *419:io_oeb[21] *52:13 28.2874 |
| 2 *52:13 *52:14 580.77 |
| 3 *52:14 io_oeb[21] 20.295 |
| *END |
| |
| *D_NET *53 0.249316 |
| *CONN |
| *P io_oeb[22] O |
| *I *419:io_oeb[22] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[22] 0.000671366 |
| 2 *419:io_oeb[22] 0.000360359 |
| 3 *53:16 0.00438783 |
| 4 *53:11 0.0726604 |
| 5 *53:10 0.0689439 |
| 6 *53:8 0.00395757 |
| 7 *53:7 0.00431793 |
| 8 *53:8 *64:8 0.0378595 |
| 9 *53:8 *86:14 0.00333644 |
| 10 *53:8 *95:8 0.0270431 |
| 11 *53:8 *96:8 0.00186498 |
| 12 *53:16 io_out[22] 0 |
| 13 *42:8 *53:8 0.000725313 |
| 14 *44:8 *53:8 0.0231874 |
| 15 *45:13 *53:8 0 |
| *RES |
| 1 *419:io_oeb[22] *53:7 7.605 |
| 2 *53:7 *53:8 99.63 |
| 3 *53:8 *53:10 4.5 |
| 4 *53:10 *53:11 688.23 |
| 5 *53:11 *53:16 49.23 |
| 6 *53:16 io_oeb[22] 6.525 |
| *END |
| |
| *D_NET *54 0.211562 |
| *CONN |
| *P io_oeb[23] O |
| *I *419:io_oeb[23] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[23] 0.000290594 |
| 2 *419:io_oeb[23] 0.000606807 |
| 3 *54:17 0.00718315 |
| 4 *54:16 0.00689256 |
| 5 *54:14 0.0127092 |
| 6 *54:13 0.0127092 |
| 7 *54:11 0.0629723 |
| 8 *54:10 0.0629723 |
| 9 *54:8 0.0011428 |
| 10 *54:7 0.00174961 |
| 11 *54:8 *59:8 0.00633741 |
| 12 *54:8 *63:8 0.00373018 |
| 13 *25:19 *54:8 0.032266 |
| *RES |
| 1 *419:io_oeb[23] *54:7 9.945 |
| 2 *54:7 *54:8 62.91 |
| 3 *54:8 *54:10 4.5 |
| 4 *54:10 *54:11 628.47 |
| 5 *54:11 *54:13 4.5 |
| 6 *54:13 *54:14 139.05 |
| 7 *54:14 *54:16 4.5 |
| 8 *54:16 *54:17 68.67 |
| 9 *54:17 io_oeb[23] 3.015 |
| *END |
| |
| *D_NET *55 0.243444 |
| *CONN |
| *P io_oeb[24] O |
| *I *419:io_oeb[24] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[24] 0.00125262 |
| 2 *419:io_oeb[24] 0.000469779 |
| 3 *55:17 0.0261522 |
| 4 *55:16 0.0248996 |
| 5 *55:14 0.0537262 |
| 6 *55:13 0.0537835 |
| 7 *55:8 0.00260507 |
| 8 *55:7 0.00301758 |
| 9 *55:8 *90:11 0.0483027 |
| 10 *55:8 *107:8 0.0228931 |
| 11 *55:13 *71:11 0.00317066 |
| 12 *55:13 *79:11 0.00317066 |
| 13 *17:8 *55:14 0 |
| 14 *40:12 *55:14 0 |
| *RES |
| 1 *419:io_oeb[24] *55:7 9.045 |
| 2 *55:7 *55:8 70.83 |
| 3 *55:8 *55:13 13.59 |
| 4 *55:13 *55:14 536.31 |
| 5 *55:14 *55:16 4.5 |
| 6 *55:16 *55:17 271.44 |
| 7 *55:17 io_oeb[24] 13.185 |
| *END |
| |
| *D_NET *56 0.204769 |
| *CONN |
| *P io_oeb[25] O |
| *I *419:io_oeb[25] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[25] 0.000258912 |
| 2 *419:io_oeb[25] 0.000974214 |
| 3 *56:17 0.00878101 |
| 4 *56:16 0.0085221 |
| 5 *56:14 0.0458284 |
| 6 *56:13 0.0458284 |
| 7 *56:11 0.00660797 |
| 8 *56:10 0.00758218 |
| 9 *56:11 *93:11 0.0803856 |
| *RES |
| 1 *419:io_oeb[25] *56:10 22.7974 |
| 2 *56:10 *56:11 121.77 |
| 3 *56:11 *56:13 4.5 |
| 4 *56:13 *56:14 457.83 |
| 5 *56:14 *56:16 4.5 |
| 6 *56:16 *56:17 92.61 |
| 7 *56:17 io_oeb[25] 2.475 |
| *END |
| |
| *D_NET *57 0.273654 |
| *CONN |
| *P io_oeb[26] O |
| *I *419:io_oeb[26] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[26] 0.000123625 |
| 2 *419:io_oeb[26] 0.000691043 |
| 3 *57:11 0.02702 |
| 4 *57:10 0.0268964 |
| 5 *57:8 0.0330405 |
| 6 *57:7 0.0337316 |
| 7 *57:8 *60:8 0.15215 |
| *RES |
| 1 *419:io_oeb[26] *57:7 11.385 |
| 2 *57:7 *57:8 428.31 |
| 3 *57:8 *57:10 4.5 |
| 4 *57:10 *57:11 291.15 |
| 5 *57:11 io_oeb[26] 1.395 |
| *END |
| |
| *D_NET *58 0.130419 |
| *CONN |
| *P io_oeb[27] O |
| *I *419:io_oeb[27] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[27] 0.000332275 |
| 2 *419:io_oeb[27] 0.000241929 |
| 3 *58:14 0.0138566 |
| 4 *58:13 0.0135243 |
| 5 *58:11 0.0427975 |
| 6 *58:10 0.0427975 |
| 7 *58:8 0.00286209 |
| 8 *58:7 0.00310402 |
| 9 *58:8 *89:8 0.00151268 |
| 10 *58:8 *96:8 0.00298401 |
| 11 *58:8 *109:11 0.000251762 |
| 12 *22:11 *58:8 0.00615439 |
| *RES |
| 1 *419:io_oeb[27] *58:7 6.705 |
| 2 *58:7 *58:8 48.33 |
| 3 *58:8 *58:10 4.5 |
| 4 *58:10 *58:11 426.87 |
| 5 *58:11 *58:13 4.5 |
| 6 *58:13 *58:14 146.61 |
| 7 *58:14 io_oeb[27] 3.015 |
| *END |
| |
| *D_NET *59 0.184414 |
| *CONN |
| *P io_oeb[28] O |
| *I *419:io_oeb[28] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[28] 0.000191629 |
| 2 *419:io_oeb[28] 0.000707367 |
| 3 *59:14 0.0139588 |
| 4 *59:13 0.0137672 |
| 5 *59:11 0.0364681 |
| 6 *59:10 0.0364681 |
| 7 *59:8 0.00486682 |
| 8 *59:7 0.00557419 |
| 9 *59:8 *63:8 0.000202052 |
| 10 *59:8 *86:13 0.00172827 |
| 11 *59:8 *90:8 0.0185888 |
| 12 *10:22 *59:8 0.0439538 |
| 13 *25:19 *59:8 0.00160165 |
| 14 *28:5 *59:8 0 |
| 15 *54:8 *59:8 0.00633741 |
| *RES |
| 1 *419:io_oeb[28] *59:7 10.665 |
| 2 *59:7 *59:8 128.79 |
| 3 *59:8 *59:10 4.5 |
| 4 *59:10 *59:11 363.33 |
| 5 *59:11 *59:13 4.5 |
| 6 *59:13 *59:14 149.31 |
| 7 *59:14 io_oeb[28] 1.935 |
| *END |
| |
| *D_NET *60 0.288947 |
| *CONN |
| *P io_oeb[29] O |
| *I *419:io_oeb[29] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[29] 0.00125262 |
| 2 *419:io_oeb[29] 0.000706956 |
| 3 *60:11 0.0271149 |
| 4 *60:10 0.0258623 |
| 5 *60:8 0.0138473 |
| 6 *60:7 0.0145542 |
| 7 *26:16 *60:8 0.0534583 |
| 8 *57:8 *60:8 0.15215 |
| *RES |
| 1 *419:io_oeb[29] *60:7 11.565 |
| 2 *60:7 *60:8 270.63 |
| 3 *60:8 *60:10 4.5 |
| 4 *60:10 *60:11 278.46 |
| 5 *60:11 io_oeb[29] 13.185 |
| *END |
| |
| *D_NET *61 0.193072 |
| *CONN |
| *P io_oeb[2] O |
| *I *419:io_oeb[2] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[2] 0.000167681 |
| 2 *419:io_oeb[2] 0.000290299 |
| 3 *61:17 0.0335267 |
| 4 *61:16 0.033359 |
| 5 *61:14 0.0190607 |
| 6 *61:13 0.0190607 |
| 7 *61:11 0.0270467 |
| 8 *61:10 0.027337 |
| 9 *61:11 *70:11 0.0189618 |
| 10 *61:11 *101:11 0.000149208 |
| 11 *7:12 *61:11 0 |
| 12 *8:16 *61:11 0 |
| 13 *40:12 *61:11 0.0141125 |
| *RES |
| 1 *419:io_oeb[2] *61:10 16.1374 |
| 2 *61:10 *61:11 316.35 |
| 3 *61:11 *61:13 4.5 |
| 4 *61:13 *61:14 189.09 |
| 5 *61:14 *61:16 4.5 |
| 6 *61:16 *61:17 365.67 |
| 7 *61:17 io_oeb[2] 1.755 |
| *END |
| |
| *D_NET *62 0.0637209 |
| *CONN |
| *P io_oeb[30] O |
| *I *419:io_oeb[30] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[30] 0.00112395 |
| 2 *419:io_oeb[30] 0.0165351 |
| 3 *62:8 0.0153254 |
| 4 *62:7 0.0142014 |
| 5 *62:5 0.0165351 |
| *RES |
| 1 *419:io_oeb[30] *62:5 177.165 |
| 2 *62:5 *62:7 4.5 |
| 3 *62:7 *62:8 141.75 |
| 4 *62:8 io_oeb[30] 16.065 |
| *END |
| |
| *D_NET *63 0.148048 |
| *CONN |
| *P io_oeb[31] O |
| *I *419:io_oeb[31] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[31] 0.00357479 |
| 2 *419:io_oeb[31] 0.000605598 |
| 3 *63:11 0.019339 |
| 4 *63:10 0.0157643 |
| 5 *63:8 0.0161618 |
| 6 *63:7 0.0167674 |
| 7 *63:8 *72:8 0.0013553 |
| 8 *63:8 *86:13 0.000397886 |
| 9 *63:8 *90:8 0.000335716 |
| 10 *63:8 *95:8 0 |
| 11 *63:8 *113:8 0.000308258 |
| 12 *25:19 *63:8 0.0531548 |
| 13 *45:13 *63:7 0 |
| 14 *45:13 *63:8 0.0163505 |
| 15 *54:8 *63:8 0.00373018 |
| 16 *59:8 *63:8 0.000202052 |
| *RES |
| 1 *419:io_oeb[31] *63:7 9.585 |
| 2 *63:7 *63:8 235.17 |
| 3 *63:8 *63:10 4.5 |
| 4 *63:10 *63:11 157.05 |
| 5 *63:11 io_oeb[31] 39.105 |
| *END |
| |
| *D_NET *64 0.124688 |
| *CONN |
| *P io_oeb[32] O |
| *I *419:io_oeb[32] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[32] 0.000332275 |
| 2 *419:io_oeb[32] 0.000332209 |
| 3 *64:14 0.0140223 |
| 4 *64:13 0.01369 |
| 5 *64:11 0.00852887 |
| 6 *64:10 0.00852887 |
| 7 *64:8 0.00117903 |
| 8 *64:7 0.00151124 |
| 9 *64:8 *96:8 0.0124956 |
| 10 *64:14 *419:wb_clk_i 0.00536215 |
| 11 *22:11 *64:8 0.00225883 |
| 12 *42:8 *64:8 0.0185872 |
| 13 *53:8 *64:8 0.0378595 |
| *RES |
| 1 *419:io_oeb[32] *64:7 7.425 |
| 2 *64:7 *64:8 54.81 |
| 3 *64:8 *64:10 4.5 |
| 4 *64:10 *64:11 84.69 |
| 5 *64:11 *64:13 4.5 |
| 6 *64:13 *64:14 173.61 |
| 7 *64:14 io_oeb[32] 3.015 |
| *END |
| |
| *D_NET *65 0.0481863 |
| *CONN |
| *P io_oeb[33] O |
| *I *419:io_oeb[33] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[33] 0.000191629 |
| 2 *419:io_oeb[33] 0.00911997 |
| 3 *65:11 0.00874013 |
| 4 *65:10 0.0085485 |
| 5 *65:8 0.00623303 |
| 6 *65:7 0.00623303 |
| 7 *65:5 0.00911997 |
| *RES |
| 1 *419:io_oeb[33] *65:5 96.165 |
| 2 *65:5 *65:7 4.5 |
| 3 *65:7 *65:8 62.19 |
| 4 *65:8 *65:10 4.5 |
| 5 *65:10 *65:11 92.61 |
| 6 *65:11 io_oeb[33] 1.935 |
| *END |
| |
| *D_NET *66 0.1729 |
| *CONN |
| *P io_oeb[34] O |
| *I *419:io_oeb[34] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[34] 0.00125262 |
| 2 *419:io_oeb[34] 0.000172243 |
| 3 *66:11 0.026324 |
| 4 *66:10 0.0250714 |
| 5 *66:8 0.00513483 |
| 6 *66:7 0.00530707 |
| 7 *66:8 *101:8 0.0413059 |
| 8 *66:8 *314:11 0.00486914 |
| 9 *17:8 *66:8 0.0206836 |
| 10 *30:16 *66:8 0.0427789 |
| *RES |
| 1 *419:io_oeb[34] *66:7 6.165 |
| 2 *66:7 *66:8 126.45 |
| 3 *66:8 *66:10 4.5 |
| 4 *66:10 *66:11 273.06 |
| 5 *66:11 io_oeb[34] 13.185 |
| *END |
| |
| *D_NET *67 0.0690405 |
| *CONN |
| *P io_oeb[35] O |
| *I *419:io_oeb[35] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[35] 0.000258912 |
| 2 *419:io_oeb[35] 0.00853611 |
| 3 *67:11 0.00929364 |
| 4 *67:10 0.00903473 |
| 5 *67:8 0.0166905 |
| 6 *67:7 0.0166905 |
| 7 *67:5 0.00853611 |
| *RES |
| 1 *419:io_oeb[35] *67:5 90.765 |
| 2 *67:5 *67:7 4.5 |
| 3 *67:7 *67:8 166.41 |
| 4 *67:8 *67:10 4.5 |
| 5 *67:10 *67:11 98.01 |
| 6 *67:11 io_oeb[35] 2.475 |
| *END |
| |
| *D_NET *68 0.0923118 |
| *CONN |
| *P io_oeb[36] O |
| *I *419:io_oeb[36] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[36] 0.000123625 |
| 2 *419:io_oeb[36] 0.00329798 |
| 3 *68:15 0.0261444 |
| 4 *68:14 0.0260207 |
| 5 *68:12 0.0159375 |
| 6 *68:10 0.0192355 |
| 7 *10:21 *68:10 0.00046262 |
| 8 *30:16 *68:10 0.00108942 |
| 9 *30:16 *68:12 0 |
| *RES |
| 1 *419:io_oeb[36] *68:10 43.335 |
| 2 *68:10 *68:12 159.3 |
| 3 *68:12 *68:14 4.5 |
| 4 *68:14 *68:15 284.31 |
| 5 *68:15 io_oeb[36] 1.395 |
| *END |
| |
| *D_NET *69 0.115587 |
| *CONN |
| *P io_oeb[37] O |
| *I *419:io_oeb[37] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[37] 0.000332275 |
| 2 *419:io_oeb[37] 2.05233e-05 |
| 3 *69:13 0.00987936 |
| 4 *69:12 0.00954708 |
| 5 *69:10 0.0358178 |
| 6 *69:9 0.0358178 |
| 7 *69:7 0.00519845 |
| 8 *69:5 0.00521897 |
| 9 *69:7 *71:11 0.0080199 |
| 10 *69:7 *101:11 0.00573516 |
| *RES |
| 1 *419:io_oeb[37] *69:5 0.225 |
| 2 *69:5 *69:7 85.41 |
| 3 *69:7 *69:9 4.5 |
| 4 *69:9 *69:10 357.21 |
| 5 *69:10 *69:12 4.5 |
| 6 *69:12 *69:13 103.41 |
| 7 *69:13 io_oeb[37] 3.015 |
| *END |
| |
| *D_NET *70 0.183167 |
| *CONN |
| *P io_oeb[3] O |
| *I *419:io_oeb[3] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[3] 0.00010158 |
| 2 *419:io_oeb[3] 0.000235193 |
| 3 *70:17 0.0598038 |
| 4 *70:16 0.0597022 |
| 5 *70:14 0.012643 |
| 6 *70:13 0.012643 |
| 7 *70:11 0.00746326 |
| 8 *70:10 0.00769846 |
| 9 *70:11 *101:11 0 |
| 10 *7:12 *70:11 0.00370839 |
| 11 *43:10 *70:10 0.000205865 |
| 12 *61:11 *70:11 0.0189618 |
| *RES |
| 1 *419:io_oeb[3] *70:10 16.3174 |
| 2 *70:10 *70:11 107.37 |
| 3 *70:11 *70:13 4.5 |
| 4 *70:13 *70:14 124.47 |
| 5 *70:14 *70:16 4.5 |
| 6 *70:16 *70:17 654.57 |
| 7 *70:17 io_oeb[3] 1.215 |
| *END |
| |
| *D_NET *71 0.316031 |
| *CONN |
| *P io_oeb[4] O |
| *I *419:io_oeb[4] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[4] 0.00060551 |
| 2 *419:io_oeb[4] 0.00316539 |
| 3 *71:14 0.00635202 |
| 4 *71:13 0.00574651 |
| 5 *71:11 0.0415401 |
| 6 *71:10 0.0415401 |
| 7 *71:8 0.00316539 |
| 8 *71:8 *74:8 0.0231386 |
| 9 *71:11 *79:11 0.175505 |
| 10 *71:11 *81:13 0.00304632 |
| 11 *71:11 *101:11 0.000290125 |
| 12 *8:16 *71:11 0.000746036 |
| 13 *55:13 *71:11 0.00317066 |
| 14 *69:7 *71:11 0.0080199 |
| *RES |
| 1 *419:io_oeb[4] *71:8 49.995 |
| 2 *71:8 *71:10 4.5 |
| 3 *71:10 *71:11 779.85 |
| 4 *71:11 *71:13 4.5 |
| 5 *71:13 *71:14 57.33 |
| 6 *71:14 io_oeb[4] 10.665 |
| *END |
| |
| *D_NET *72 0.319848 |
| *CONN |
| *P io_oeb[5] O |
| *I *419:io_oeb[5] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[5] 0.000310538 |
| 2 *419:io_oeb[5] 0.000630482 |
| 3 *72:14 0.0513453 |
| 4 *72:13 0.0510348 |
| 5 *72:11 0.0108207 |
| 6 *72:10 0.0108207 |
| 7 *72:8 0.000871017 |
| 8 *72:7 0.0015015 |
| 9 *72:8 *75:11 0.00114392 |
| 10 *72:8 *84:10 0.0078541 |
| 11 *72:8 *113:8 0.0383588 |
| 12 *7:12 *72:14 0 |
| 13 *32:19 *72:14 0.143674 |
| 14 *45:13 *72:8 0.00012693 |
| 15 *63:8 *72:8 0.0013553 |
| *RES |
| 1 *419:io_oeb[5] *72:7 10.125 |
| 2 *72:7 *72:8 55.53 |
| 3 *72:8 *72:10 4.5 |
| 4 *72:10 *72:11 106.29 |
| 5 *72:11 *72:13 4.5 |
| 6 *72:13 *72:14 649.17 |
| 7 *72:14 io_oeb[5] 2.835 |
| *END |
| |
| *D_NET *73 0.271272 |
| *CONN |
| *P io_oeb[6] O |
| *I *419:io_oeb[6] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[6] 0.000237175 |
| 2 *419:io_oeb[6] 0.000261151 |
| 3 *73:14 0.0595411 |
| 4 *73:13 0.0593039 |
| 5 *73:11 0.0169829 |
| 6 *73:10 0.0169829 |
| 7 *73:8 0.002999 |
| 8 *73:7 0.00326015 |
| 9 *73:8 *78:8 0.0378574 |
| 10 *73:8 *89:8 0.00880242 |
| 11 *22:11 *73:8 0.0573774 |
| 12 *42:8 *73:8 0.00692089 |
| 13 *44:8 *73:8 0.000745992 |
| *RES |
| 1 *419:io_oeb[6] *73:7 6.885 |
| 2 *73:7 *73:8 118.53 |
| 3 *73:8 *73:10 4.5 |
| 4 *73:10 *73:11 167.85 |
| 5 *73:11 *73:13 4.5 |
| 6 *73:13 *73:14 646.47 |
| 7 *73:14 io_oeb[6] 2.295 |
| *END |
| |
| *D_NET *74 0.397559 |
| *CONN |
| *P io_oeb[7] O |
| *I *419:io_oeb[7] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[7] 0.000621435 |
| 2 *419:io_oeb[7] 0.00116469 |
| 3 *74:14 0.00724455 |
| 4 *74:13 0.00662311 |
| 5 *74:11 0.0757531 |
| 6 *74:10 0.0757531 |
| 7 *74:8 0.00265287 |
| 8 *74:7 0.00381756 |
| 9 *74:11 *112:13 0.0699371 |
| 10 *74:14 *79:14 0.0809546 |
| 11 *11:11 *74:8 0.0498985 |
| 12 *71:8 *74:8 0.0231386 |
| *RES |
| 1 *419:io_oeb[7] *74:7 15.885 |
| 2 *74:7 *74:8 73.17 |
| 3 *74:8 *74:10 4.5 |
| 4 *74:10 *74:11 779.49 |
| 5 *74:11 *74:13 4.5 |
| 6 *74:13 *74:14 118.71 |
| 7 *74:14 io_oeb[7] 10.845 |
| *END |
| |
| *D_NET *75 0.213002 |
| *CONN |
| *P io_oeb[8] O |
| *I *419:io_oeb[8] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[8] 0.00010158 |
| 2 *419:io_oeb[8] 0.000682717 |
| 3 *75:17 0.0333774 |
| 4 *75:16 0.0332758 |
| 5 *75:14 0.0301742 |
| 6 *75:13 0.0301742 |
| 7 *75:11 0.0185225 |
| 8 *75:10 0.0192052 |
| 9 *75:11 *84:10 0.0139882 |
| 10 *75:11 *86:14 0 |
| 11 *75:11 *113:8 0.0258393 |
| 12 *10:16 *75:10 6.21698e-05 |
| 13 *33:9 *75:11 0.00126412 |
| 14 *45:14 *75:10 0.000901462 |
| 15 *47:11 *75:11 0.00428972 |
| 16 *72:8 *75:11 0.00114392 |
| *RES |
| 1 *419:io_oeb[8] *75:10 14.895 |
| 2 *75:10 *75:11 314.73 |
| 3 *75:11 *75:13 4.5 |
| 4 *75:13 *75:14 300.15 |
| 5 *75:14 *75:16 4.5 |
| 6 *75:16 *75:17 362.97 |
| 7 *75:17 io_oeb[8] 1.215 |
| *END |
| |
| *D_NET *76 0.193028 |
| *CONN |
| *P io_oeb[9] O |
| *I *419:io_oeb[9] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[9] 0.0305436 |
| 2 *419:io_oeb[9] 0.0354635 |
| 3 *76:10 0.0305436 |
| 4 *76:8 0.0305068 |
| 5 *76:7 0.0305068 |
| 6 *76:5 0.0354635 |
| *RES |
| 1 *419:io_oeb[9] *76:5 345.645 |
| 2 *76:5 *76:7 4.5 |
| 3 *76:7 *76:8 304.11 |
| 4 *76:8 *76:10 4.5 |
| 5 *76:10 io_oeb[9] 333.225 |
| *END |
| |
| *D_NET *77 0.189791 |
| *CONN |
| *P io_out[0] O |
| *I *419:io_out[0] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[0] 0.000332275 |
| 2 *419:io_out[0] 0.0431193 |
| 3 *77:11 0.0238301 |
| 4 *77:10 0.0234978 |
| 5 *77:8 0.0279462 |
| 6 *77:7 0.0279462 |
| 7 *77:5 0.0431193 |
| *RES |
| 1 *419:io_out[0] *77:5 421.245 |
| 2 *77:5 *77:7 4.5 |
| 3 *77:7 *77:8 278.73 |
| 4 *77:8 *77:10 4.5 |
| 5 *77:10 *77:11 257.67 |
| 6 *77:11 io_out[0] 3.015 |
| *END |
| |
| *D_NET *78 0.269199 |
| *CONN |
| *P io_out[10] O |
| *I *419:io_out[10] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[10] 0.000332275 |
| 2 *419:io_out[10] 0.000241929 |
| 3 *78:14 0.00490958 |
| 4 *78:13 0.00457731 |
| 5 *78:11 0.0403274 |
| 6 *78:10 0.0403274 |
| 7 *78:8 0.0412168 |
| 8 *78:7 0.0414587 |
| 9 *78:8 *86:14 0 |
| 10 *78:8 *89:8 0.00735578 |
| 11 *78:8 *109:11 0.0481469 |
| 12 *44:8 *78:8 0.00244792 |
| 13 *73:8 *78:8 0.0378574 |
| *RES |
| 1 *419:io_out[10] *78:7 6.705 |
| 2 *78:7 *78:8 651.51 |
| 3 *78:8 *78:10 4.5 |
| 4 *78:10 *78:11 402.57 |
| 5 *78:11 *78:13 4.5 |
| 6 *78:13 *78:14 49.77 |
| 7 *78:14 io_out[10] 3.015 |
| *END |
| |
| *D_NET *79 0.808062 |
| *CONN |
| *P io_out[11] O |
| *I *419:io_out[11] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[11] 0.000637361 |
| 2 *419:io_out[11] 0.00278466 |
| 3 *79:14 0.0324703 |
| 4 *79:13 0.031833 |
| 5 *79:11 0.0145285 |
| 6 *79:10 0.0173131 |
| 7 *79:11 *81:13 0.00105689 |
| 8 *8:16 *79:11 0.447808 |
| 9 *55:13 *79:11 0.00317066 |
| 10 *71:11 *79:11 0.175505 |
| 11 *74:14 *79:14 0.0809546 |
| *RES |
| 1 *419:io_out[11] *79:10 36.135 |
| 2 *79:10 *79:11 768.33 |
| 3 *79:11 *79:13 4.5 |
| 4 *79:13 *79:14 370.53 |
| 5 *79:14 io_out[11] 11.025 |
| *END |
| |
| *D_NET *80 0.227987 |
| *CONN |
| *P io_out[12] O |
| *I *419:io_out[12] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[12] 0.000191629 |
| 2 *419:io_out[12] 0.0428997 |
| 3 *80:11 0.019579 |
| 4 *80:10 0.0193874 |
| 5 *80:8 0.0515147 |
| 6 *80:7 0.0515147 |
| 7 *80:5 0.0428997 |
| *RES |
| 1 *419:io_out[12] *80:5 467.145 |
| 2 *80:5 *80:7 4.5 |
| 3 *80:7 *80:8 514.17 |
| 4 *80:8 *80:10 4.5 |
| 5 *80:10 *80:11 211.77 |
| 6 *80:11 io_out[12] 1.935 |
| *END |
| |
| *D_NET *81 0.312799 |
| *CONN |
| *P io_out[13] O |
| *I *419:io_out[13] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[13] 0.000123625 |
| 2 *419:io_out[13] 0.000356235 |
| 3 *81:17 0.0709379 |
| 4 *81:16 0.0708143 |
| 5 *81:14 0.0499169 |
| 6 *81:13 0.0500119 |
| 7 *81:8 0.000705618 |
| 8 *81:7 0.000966833 |
| 9 *81:8 *87:8 0.0320995 |
| 10 *81:8 *114:8 0.0320995 |
| 11 *81:14 *111:12 0 |
| 12 *8:16 *81:13 0.000663143 |
| 13 *71:11 *81:13 0.00304632 |
| 14 *79:11 *81:13 0.00105689 |
| *RES |
| 1 *419:io_out[13] *81:7 7.785 |
| 2 *81:7 *81:8 47.07 |
| 3 *81:8 *81:13 13.41 |
| 4 *81:13 *81:14 498.51 |
| 5 *81:14 *81:16 4.5 |
| 6 *81:16 *81:17 773.37 |
| 7 *81:17 io_out[13] 1.395 |
| *END |
| |
| *D_NET *82 0.325779 |
| *CONN |
| *P io_out[14] O |
| *I *419:io_out[14] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[14] 0.00395544 |
| 2 *419:io_out[14] 0.000324123 |
| 3 *82:17 0.0589211 |
| 4 *82:16 0.0549657 |
| 5 *82:14 0.066237 |
| 6 *82:13 0.066237 |
| 7 *82:11 0.00516239 |
| 8 *82:10 0.00548651 |
| 9 *82:11 *109:11 0.0299862 |
| 10 *45:14 *82:11 0.034504 |
| *RES |
| 1 *419:io_out[14] *82:10 12.735 |
| 2 *82:10 *82:11 130.23 |
| 3 *82:11 *82:13 4.5 |
| 4 *82:13 *82:14 660.51 |
| 5 *82:14 *82:16 4.5 |
| 6 *82:16 *82:17 600.84 |
| 7 *82:17 io_out[14] 43.245 |
| *END |
| |
| *D_NET *83 0.239471 |
| *CONN |
| *P io_out[15] O |
| *I *419:io_out[15] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[15] 0.000290594 |
| 2 *419:io_out[15] 0.0571613 |
| 3 *83:8 0.0625743 |
| 4 *83:7 0.0622837 |
| 5 *83:5 0.0571613 |
| *RES |
| 1 *419:io_out[15] *83:5 622.485 |
| 2 *83:5 *83:7 4.5 |
| 3 *83:7 *83:8 621.81 |
| 4 *83:8 io_out[15] 3.015 |
| *END |
| |
| *D_NET *84 0.267977 |
| *CONN |
| *P io_out[16] O |
| *I *419:io_out[16] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[16] 0.000104982 |
| 2 *419:io_out[16] 0.0012354 |
| 3 *84:17 0.0686425 |
| 4 *84:16 0.0685375 |
| 5 *84:14 0.0505971 |
| 6 *84:13 0.051946 |
| 7 *84:10 0.00258423 |
| 8 *84:10 *86:14 0 |
| 9 *47:11 *84:10 0.00248679 |
| 10 *72:8 *84:10 0.0078541 |
| 11 *75:11 *84:10 0.0139882 |
| *RES |
| 1 *419:io_out[16] *84:10 48.375 |
| 2 *84:10 *84:13 17.19 |
| 3 *84:13 *84:14 495.81 |
| 4 *84:14 *84:16 4.5 |
| 5 *84:16 *84:17 684.27 |
| 6 *84:17 io_out[16] 1.395 |
| *END |
| |
| *D_NET *85 0.249124 |
| *CONN |
| *P io_out[17] O |
| *I *419:io_out[17] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[17] 0.000649026 |
| 2 *419:io_out[17] 0.0303307 |
| 3 *85:11 0.00478877 |
| 4 *85:10 0.00413975 |
| 5 *85:8 0.0610124 |
| 6 *85:7 0.0610124 |
| 7 *85:5 0.0303307 |
| 8 *9:8 *85:11 0.056388 |
| 9 *46:8 io_out[17] 3.68254e-05 |
| 10 *46:13 *85:11 0.000435189 |
| *RES |
| 1 *419:io_out[17] *85:5 329.445 |
| 2 *85:5 *85:7 4.5 |
| 3 *85:7 *85:8 609.03 |
| 4 *85:8 *85:10 4.5 |
| 5 *85:10 *85:11 81.63 |
| 6 *85:11 io_out[17] 10.845 |
| *END |
| |
| *D_NET *86 0.215459 |
| *CONN |
| *P io_out[18] O |
| *I *419:io_out[18] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[18] 0.00434204 |
| 2 *419:io_out[18] 0.00105257 |
| 3 *86:17 0.0697319 |
| 4 *86:16 0.0653899 |
| 5 *86:14 0.0277043 |
| 6 *86:13 0.0287569 |
| 7 *86:13 *90:8 0.000306879 |
| 8 *86:13 *108:7 0 |
| 9 *25:19 *86:13 0.00221731 |
| 10 *44:8 *86:14 0.0104942 |
| 11 *45:13 *86:14 0 |
| 12 *47:11 *86:14 0 |
| 13 *53:8 *86:14 0.00333644 |
| 14 *59:8 *86:13 0.00172827 |
| 15 *63:8 *86:13 0.000397886 |
| 16 *75:11 *86:14 0 |
| 17 *78:8 *86:14 0 |
| 18 *84:10 *86:14 0 |
| *RES |
| 1 *419:io_out[18] *86:13 33.885 |
| 2 *86:13 *86:14 337.59 |
| 3 *86:14 *86:16 4.5 |
| 4 *86:16 *86:17 652.14 |
| 5 *86:17 io_out[18] 43.245 |
| *END |
| |
| *D_NET *87 0.406301 |
| *CONN |
| *P io_out[19] O |
| *I *419:io_out[19] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[19] 0.000659344 |
| 2 *419:io_out[19] 0.00037216 |
| 3 *87:17 0.0163588 |
| 4 *87:16 0.0156994 |
| 5 *87:14 0.0586533 |
| 6 *87:13 0.0597674 |
| 7 *87:8 0.00426673 |
| 8 *87:7 0.00352487 |
| 9 *87:8 *88:8 0.0117228 |
| 10 *87:8 *109:10 0.0022709 |
| 11 *87:8 *114:8 0.00366209 |
| 12 *87:14 *112:12 0 |
| 13 *87:17 io_out[21] 0.0146098 |
| 14 io_oeb[21] *87:17 0 |
| 15 *7:12 *87:13 0.0143612 |
| 16 *9:8 *87:17 0.115698 |
| 17 *14:10 *87:17 0 |
| 18 *15:19 *87:8 0.0208064 |
| 19 *48:11 *87:17 0.0317688 |
| 20 *81:8 *87:8 0.0320995 |
| *RES |
| 1 *419:io_out[19] *87:7 7.965 |
| 2 *87:7 *87:8 80.37 |
| 3 *87:8 *87:13 29.79 |
| 4 *87:13 *87:14 585.99 |
| 5 *87:14 *87:16 4.5 |
| 6 *87:16 *87:17 275.49 |
| 7 *87:17 io_out[19] 10.845 |
| *END |
| |
| *D_NET *88 0.205674 |
| *CONN |
| *P io_out[1] O |
| *I *419:io_out[1] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[1] 0.000258912 |
| 2 *419:io_out[1] 0.000379173 |
| 3 *88:11 0.071202 |
| 4 *88:10 0.0709431 |
| 5 *88:8 0.019431 |
| 6 *88:7 0.0198101 |
| 7 *88:8 *109:10 0.00462364 |
| 8 *88:8 *114:8 0.00730371 |
| 9 *87:8 *88:8 0.0117228 |
| *RES |
| 1 *419:io_out[1] *88:7 7.785 |
| 2 *88:7 *88:8 213.75 |
| 3 *88:8 *88:10 4.5 |
| 4 *88:10 *88:11 777.69 |
| 5 *88:11 io_out[1] 2.475 |
| *END |
| |
| *D_NET *89 0.193819 |
| *CONN |
| *P io_out[20] O |
| *I *419:io_out[20] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[20] 0.000290594 |
| 2 *419:io_out[20] 0.0001932 |
| 3 *89:17 0.069461 |
| 4 *89:16 0.0691704 |
| 5 *89:14 0.00479522 |
| 6 *89:13 0.00521114 |
| 7 *89:8 0.00311859 |
| 8 *89:7 0.00289587 |
| 9 *89:8 *109:11 0.0145848 |
| 10 *419:io_in[20] *89:14 0.00609185 |
| 11 *22:11 *89:8 0.000335457 |
| 12 *58:8 *89:8 0.00151268 |
| 13 *73:8 *89:8 0.00880242 |
| 14 *78:8 *89:8 0.00735578 |
| *RES |
| 1 *419:io_out[20] *89:7 6.345 |
| 2 *89:7 *89:8 105.57 |
| 3 *89:8 *89:13 12.87 |
| 4 *89:13 *89:14 78.39 |
| 5 *89:14 *89:16 4.5 |
| 6 *89:16 *89:17 689.67 |
| 7 *89:17 io_out[20] 3.015 |
| *END |
| |
| *D_NET *90 0.250224 |
| *CONN |
| *P io_out[21] O |
| *I *419:io_out[21] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[21] 0.00183833 |
| 2 *419:io_out[21] 0.00119657 |
| 3 *90:11 0.0667981 |
| 4 *90:10 0.0649597 |
| 5 *90:8 0.00119657 |
| 6 *90:8 *113:8 0.0231893 |
| 7 *90:11 *107:8 0.00716051 |
| 8 *10:22 *90:8 0.00174075 |
| 9 *55:8 *90:11 0.0483027 |
| 10 *59:8 *90:8 0.0185888 |
| 11 *63:8 *90:8 0.000335716 |
| 12 *86:13 *90:8 0.000306879 |
| 13 *87:17 io_out[21] 0.0146098 |
| *RES |
| 1 *419:io_out[21] *90:8 48.375 |
| 2 *90:8 *90:10 4.5 |
| 3 *90:10 *90:11 691.11 |
| 4 *90:11 io_out[21] 36.675 |
| *END |
| |
| *D_NET *91 0.145543 |
| *CONN |
| *P io_out[22] O |
| *I *419:io_out[22] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[22] 0.000987786 |
| 2 *419:io_out[22] 0.000554422 |
| 3 *91:14 0.0591939 |
| 4 *91:13 0.0599354 |
| 5 *91:10 0.00228371 |
| 6 *91:13 *92:11 0.0221946 |
| 7 *3:16 *91:10 0 |
| 8 *15:13 *91:10 0.000393572 |
| 9 *53:16 io_out[22] 0 |
| *RES |
| 1 *419:io_out[22] *91:10 20.2774 |
| 2 *91:10 *91:13 36.63 |
| 3 *91:13 *91:14 581.85 |
| 4 *91:14 io_out[22] 18.675 |
| *END |
| |
| *D_NET *92 0.175355 |
| *CONN |
| *P io_out[23] O |
| *I *419:io_out[23] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[23] 0.000671366 |
| 2 *419:io_out[23] 0.00070057 |
| 3 *92:17 0.00619088 |
| 4 *92:16 0.00551951 |
| 5 *92:14 0.0583694 |
| 6 *92:13 0.0583694 |
| 7 *92:11 0.00866932 |
| 8 *92:10 0.00936989 |
| 9 *32:19 *92:11 0.000264222 |
| 10 *51:16 *92:11 0.00503575 |
| 11 *91:13 *92:11 0.0221946 |
| *RES |
| 1 *419:io_out[23] *92:10 20.0974 |
| 2 *92:10 *92:11 110.97 |
| 3 *92:11 *92:13 4.5 |
| 4 *92:13 *92:14 583.29 |
| 5 *92:14 *92:16 4.5 |
| 6 *92:16 *92:17 60.21 |
| 7 *92:17 io_out[23] 11.025 |
| *END |
| |
| *D_NET *93 0.237667 |
| *CONN |
| *P io_out[24] O |
| *I *419:io_out[24] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[24] 0.000215438 |
| 2 *419:io_out[24] 0.00066151 |
| 3 *93:17 0.00923593 |
| 4 *93:16 0.00902049 |
| 5 *93:14 0.0549872 |
| 6 *93:13 0.0549872 |
| 7 *93:11 0.00946995 |
| 8 *93:10 0.0101315 |
| 9 *419:io_in[14] *93:10 5.4397e-05 |
| 10 *419:io_in[27] *93:11 0 |
| 11 *419:io_in[30] *93:11 0 |
| 12 *419:io_in[9] *93:11 0.000127448 |
| 13 *6:12 *93:10 0.000868212 |
| 14 *37:19 *93:11 0.00752255 |
| 15 *52:13 *93:11 0 |
| 16 *56:11 *93:11 0.0803856 |
| *RES |
| 1 *419:io_out[24] *93:10 22.9774 |
| 2 *93:10 *93:11 157.41 |
| 3 *93:11 *93:13 4.5 |
| 4 *93:13 *93:14 549.45 |
| 5 *93:14 *93:16 4.5 |
| 6 *93:16 *93:17 98.01 |
| 7 *93:17 io_out[24] 2.115 |
| *END |
| |
| *D_NET *94 0.151475 |
| *CONN |
| *P io_out[25] O |
| *I *419:io_out[25] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[25] 0.00163658 |
| 2 *419:io_out[25] 0.0159227 |
| 3 *94:8 0.0598149 |
| 4 *94:7 0.0581783 |
| 5 *94:5 0.0159227 |
| 6 *94:8 *313:13 0 |
| *RES |
| 1 *419:io_out[25] *94:5 171.765 |
| 2 *94:5 *94:7 4.5 |
| 3 *94:7 *94:8 580.95 |
| 4 *94:8 io_out[25] 21.465 |
| *END |
| |
| *D_NET *95 0.171554 |
| *CONN |
| *P io_out[26] O |
| *I *419:io_out[26] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[26] 0.000280649 |
| 2 *419:io_out[26] 0.000379581 |
| 3 *95:14 0.0105789 |
| 4 *95:13 0.0102983 |
| 5 *95:11 0.0520932 |
| 6 *95:10 0.0520932 |
| 7 *95:8 0.0054738 |
| 8 *95:7 0.00585338 |
| 9 *95:8 *96:8 0.00746025 |
| 10 *53:8 *95:8 0.0270431 |
| 11 *63:8 *95:8 0 |
| *RES |
| 1 *419:io_out[26] *95:7 7.785 |
| 2 *95:7 *95:8 93.15 |
| 3 *95:8 *95:10 4.5 |
| 4 *95:10 *95:11 519.75 |
| 5 *95:11 *95:13 4.5 |
| 6 *95:13 *95:14 111.51 |
| 7 *95:14 io_out[26] 2.655 |
| *END |
| |
| *D_NET *96 0.160215 |
| *CONN |
| *P io_out[27] O |
| *I *419:io_out[27] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[27] 0.000145659 |
| 2 *419:io_out[27] 0.000308516 |
| 3 *96:14 0.00996161 |
| 4 *96:13 0.00981595 |
| 5 *96:11 0.0452794 |
| 6 *96:10 0.0452794 |
| 7 *96:8 0.00404306 |
| 8 *96:7 0.00435158 |
| 9 *22:11 *96:8 0.0162253 |
| 10 *53:8 *96:8 0.00186498 |
| 11 *58:8 *96:8 0.00298401 |
| 12 *64:8 *96:8 0.0124956 |
| 13 *95:8 *96:8 0.00746025 |
| *RES |
| 1 *419:io_out[27] *96:7 7.245 |
| 2 *96:7 *96:8 85.59 |
| 3 *96:8 *96:10 4.5 |
| 4 *96:10 *96:11 451.71 |
| 5 *96:11 *96:13 4.5 |
| 6 *96:13 *96:14 106.11 |
| 7 *96:14 io_out[27] 1.575 |
| *END |
| |
| *D_NET *97 0.107268 |
| *CONN |
| *P io_out[28] O |
| *I *419:io_out[28] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[28] 0.0240675 |
| 2 *419:io_out[28] 0.00168424 |
| 3 *97:16 0.0240675 |
| 4 *97:14 0.0278823 |
| 5 *97:13 0.0295665 |
| 6 *37:19 *97:13 0 |
| *RES |
| 1 *419:io_out[28] *97:13 34.2274 |
| 2 *97:13 *97:14 278.37 |
| 3 *97:14 *97:16 4.5 |
| 4 *97:16 io_out[28] 259.965 |
| *END |
| |
| *D_NET *98 0.100649 |
| *CONN |
| *P io_out[29] O |
| *I *419:io_out[29] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[29] 0.000215438 |
| 2 *419:io_out[29] 0.0015994 |
| 3 *98:17 0.021577 |
| 4 *98:16 0.0213616 |
| 5 *98:14 0.0209582 |
| 6 *98:13 0.0225576 |
| 7 *419:io_in[27] *98:13 6.52783e-05 |
| 8 *419:io_in[30] *98:13 4.66274e-05 |
| 9 *419:io_in[30] *98:14 0 |
| 10 *49:13 *98:13 0.0121229 |
| 11 *49:16 *98:13 6.13758e-05 |
| 12 *52:13 *98:13 8.39292e-05 |
| *RES |
| 1 *419:io_out[29] *98:13 42.3274 |
| 2 *98:13 *98:14 209.25 |
| 3 *98:14 *98:16 4.5 |
| 4 *98:16 *98:17 230.31 |
| 5 *98:17 io_out[29] 2.115 |
| *END |
| |
| *D_NET *99 0.170622 |
| *CONN |
| *P io_out[2] O |
| *I *419:io_out[2] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[2] 0.00100159 |
| 2 *419:io_out[2] 4.01718e-05 |
| 3 *99:10 0.0743241 |
| 4 *99:9 0.0733225 |
| 5 *99:7 0.0109467 |
| 6 *99:5 0.0109868 |
| *RES |
| 1 *419:io_out[2] *99:5 0.405 |
| 2 *99:5 *99:7 108.81 |
| 3 *99:7 *99:9 4.5 |
| 4 *99:9 *99:10 720.99 |
| 5 *99:10 io_out[2] 19.215 |
| *END |
| |
| *D_NET *100 0.134535 |
| *CONN |
| *P io_out[30] O |
| *I *419:io_out[30] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[30] 0.00188969 |
| 2 *419:io_out[30] 0.00160183 |
| 3 *100:16 0.0153237 |
| 4 *100:15 0.013434 |
| 5 *100:13 0.0204696 |
| 6 *100:12 0.0220714 |
| 7 *100:13 *111:13 0.0597452 |
| 8 *5:16 *100:12 0 |
| *RES |
| 1 *419:io_out[30] *100:12 28.7257 |
| 2 *100:12 *100:13 258.03 |
| 3 *100:13 *100:15 4.5 |
| 4 *100:15 *100:16 134.19 |
| 5 *100:16 io_out[30] 24.165 |
| *END |
| |
| *D_NET *101 0.220741 |
| *CONN |
| *P io_out[31] O |
| *I *419:io_out[31] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[31] 0.000611329 |
| 2 *419:io_out[31] 0.000188168 |
| 3 *101:14 0.00849793 |
| 4 *101:13 0.0078866 |
| 5 *101:11 0.0189137 |
| 6 *101:10 0.0189137 |
| 7 *101:8 0.00339369 |
| 8 *101:7 0.00358186 |
| 9 *101:8 *314:11 0.0228931 |
| 10 *8:16 *101:11 0.0732974 |
| 11 *15:19 *101:11 0.00615481 |
| 12 *17:8 *101:8 0.00366209 |
| 13 *21:16 *101:8 0.00521694 |
| 14 *40:12 *101:11 4.89586e-05 |
| 15 *61:11 *101:11 0.000149208 |
| 16 *66:8 *101:8 0.0413059 |
| 17 *69:7 *101:11 0.00573516 |
| 18 *70:11 *101:11 0 |
| 19 *71:11 *101:11 0.000290125 |
| *RES |
| 1 *419:io_out[31] *101:7 6.345 |
| 2 *101:7 *101:8 84.33 |
| 3 *101:8 *101:10 4.5 |
| 4 *101:10 *101:11 279.99 |
| 5 *101:11 *101:13 4.5 |
| 6 *101:13 *101:14 78.75 |
| 7 *101:14 io_out[31] 10.665 |
| *END |
| |
| *D_NET *102 0.0383944 |
| *CONN |
| *P io_out[32] O |
| *I *419:io_out[32] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[32] 0.00342789 |
| 2 *419:io_out[32] 0.0157693 |
| 3 *102:5 0.0191972 |
| *RES |
| 1 *419:io_out[32] *102:5 169.065 |
| 2 *102:5 io_out[32] 43.875 |
| *END |
| |
| *D_NET *103 0.0363852 |
| *CONN |
| *P io_out[33] O |
| *I *419:io_out[33] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[33] 0.00122119 |
| 2 *419:io_out[33] 0.0169714 |
| 3 *103:5 0.0181926 |
| *RES |
| 1 *419:io_out[33] *103:5 182.025 |
| 2 *103:5 io_out[33] 21.195 |
| *END |
| |
| *D_NET *104 0.0494266 |
| *CONN |
| *P io_out[34] O |
| *I *419:io_out[34] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[34] 0.000215438 |
| 2 *419:io_out[34] 0.00329621 |
| 3 *104:10 0.0214171 |
| 4 *104:9 0.0244978 |
| *RES |
| 1 *419:io_out[34] *104:9 36.675 |
| 2 *104:9 *104:10 207.45 |
| 3 *104:10 io_out[34] 2.115 |
| *END |
| |
| *D_NET *105 0.0608946 |
| *CONN |
| *P io_out[35] O |
| *I *419:io_out[35] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[35] 0.00238169 |
| 2 *419:io_out[35] 9.37343e-05 |
| 3 *105:15 0.00465455 |
| 4 *105:10 0.0202574 |
| 5 *105:9 0.0179845 |
| 6 *105:7 0.00771451 |
| 7 *105:5 0.00780824 |
| 8 *105:15 *314:5 0 |
| 9 *29:13 *105:10 0 |
| *RES |
| 1 *419:io_out[35] *105:5 0.945 |
| 2 *105:5 *105:7 76.41 |
| 3 *105:7 *105:9 4.5 |
| 4 *105:9 *105:10 195.93 |
| 5 *105:10 *105:15 31.59 |
| 6 *105:15 io_out[35] 25.065 |
| *END |
| |
| *D_NET *106 0.0754244 |
| *CONN |
| *P io_out[36] O |
| *I *419:io_out[36] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[36] 0.000280649 |
| 2 *419:io_out[36] 0.00751146 |
| 3 *106:11 0.0103258 |
| 4 *106:10 0.0100452 |
| 5 *106:8 0.0198749 |
| 6 *106:7 0.0198749 |
| 7 *106:5 0.00751146 |
| *RES |
| 1 *419:io_out[36] *106:5 79.965 |
| 2 *106:5 *106:7 4.5 |
| 3 *106:7 *106:8 198.27 |
| 4 *106:8 *106:10 4.5 |
| 5 *106:10 *106:11 108.81 |
| 6 *106:11 io_out[36] 2.655 |
| *END |
| |
| *D_NET *107 0.137536 |
| *CONN |
| *P io_out[37] O |
| *I *419:io_out[37] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[37] 0.000611329 |
| 2 *419:io_out[37] 0.000439606 |
| 3 *107:16 0.00414716 |
| 4 *107:11 0.0293644 |
| 5 *107:10 0.0258285 |
| 6 *107:8 0.0233257 |
| 7 *107:7 0.0237653 |
| 8 *55:8 *107:8 0.0228931 |
| 9 *90:11 *107:8 0.00716051 |
| *RES |
| 1 *419:io_out[37] *107:7 8.865 |
| 2 *107:7 *107:8 259.65 |
| 3 *107:8 *107:10 4.5 |
| 4 *107:10 *107:11 282.51 |
| 5 *107:11 *107:16 44.19 |
| 6 *107:16 io_out[37] 6.165 |
| *END |
| |
| *D_NET *108 0.143424 |
| *CONN |
| *P io_out[3] O |
| *I *419:io_out[3] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[3] 0.000123625 |
| 2 *419:io_out[3] 0.00552949 |
| 3 *108:10 0.0661827 |
| 4 *108:9 0.0660591 |
| 5 *108:7 0.00552949 |
| 6 *86:13 *108:7 0 |
| *RES |
| 1 *419:io_out[3] *108:7 49.455 |
| 2 *108:7 *108:9 4.5 |
| 3 *108:9 *108:10 723.33 |
| 4 *108:10 io_out[3] 1.395 |
| *END |
| |
| *D_NET *109 0.235729 |
| *CONN |
| *P io_out[4] O |
| *I *419:io_out[4] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[4] 0.00248495 |
| 2 *419:io_out[4] 0.00180316 |
| 3 *109:11 0.0279821 |
| 4 *109:10 0.0273003 |
| 5 *45:14 *109:11 0.0762946 |
| 6 *58:8 *109:11 0.000251762 |
| 7 *78:8 *109:11 0.0481469 |
| 8 *82:11 *109:11 0.0299862 |
| 9 *87:8 *109:10 0.0022709 |
| 10 *88:8 *109:10 0.00462364 |
| 11 *89:8 *109:11 0.0145848 |
| *RES |
| 1 *419:io_out[4] *109:10 36.315 |
| 2 *109:10 *109:11 771.57 |
| 3 *109:11 io_out[4] 33.975 |
| *END |
| |
| *D_NET *110 0.198925 |
| *CONN |
| *P io_out[5] O |
| *I *419:io_out[5] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[5] 0.000332275 |
| 2 *419:io_out[5] 0.000611305 |
| 3 *110:17 0.0379026 |
| 4 *110:16 0.0398618 |
| 5 *110:13 0.00408854 |
| 6 *110:10 0.00240841 |
| 7 *32:19 *110:13 0.0230646 |
| 8 *41:5 *110:17 0.0906558 |
| *RES |
| 1 *419:io_out[5] *110:10 19.1974 |
| 2 *110:10 *110:13 37.89 |
| 3 *110:13 *110:16 26.55 |
| 4 *110:16 *110:17 668.07 |
| 5 *110:17 io_out[5] 3.015 |
| *END |
| |
| *D_NET *111 0.205394 |
| *CONN |
| *P io_out[6] O |
| *I *419:io_out[6] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[6] 0.000258912 |
| 2 *419:io_out[6] 0.00161168 |
| 3 *111:19 0.0616348 |
| 4 *111:18 0.0647837 |
| 5 *111:13 0.00957803 |
| 6 *111:12 0.00778195 |
| 7 *81:14 *111:12 0 |
| 8 *100:13 *111:13 0.0597452 |
| *RES |
| 1 *419:io_out[6] *111:12 28.9057 |
| 2 *111:12 *111:13 103.95 |
| 3 *111:13 *111:18 42.75 |
| 4 *111:18 *111:19 668.07 |
| 5 *111:19 io_out[6] 2.475 |
| *END |
| |
| *D_NET *112 0.226107 |
| *CONN |
| *P io_out[7] O |
| *I *419:io_out[7] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[7] 0.000191629 |
| 2 *419:io_out[7] 0.0018716 |
| 3 *112:19 0.0602243 |
| 4 *112:18 0.0600327 |
| 5 *112:16 0.00959966 |
| 6 *112:15 0.00959966 |
| 7 *112:13 0.0063891 |
| 8 *112:12 0.0082607 |
| 9 *74:11 *112:13 0.0699371 |
| 10 *87:14 *112:12 0 |
| *RES |
| 1 *419:io_out[7] *112:12 31.6057 |
| 2 *112:12 *112:13 101.25 |
| 3 *112:13 *112:15 4.5 |
| 4 *112:15 *112:16 95.85 |
| 5 *112:16 *112:18 4.5 |
| 6 *112:18 *112:19 654.57 |
| 7 *112:19 io_out[7] 1.935 |
| *END |
| |
| *D_NET *113 0.250246 |
| *CONN |
| *P io_out[8] O |
| *I *419:io_out[8] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[8] 0.000123625 |
| 2 *419:io_out[8] 0.000648337 |
| 3 *113:14 0.0361315 |
| 4 *113:13 0.0360078 |
| 5 *113:11 0.0281038 |
| 6 *113:10 0.0281038 |
| 7 *113:8 0.0163917 |
| 8 *113:7 0.01704 |
| 9 *63:8 *113:8 0.000308258 |
| 10 *72:8 *113:8 0.0383588 |
| 11 *75:11 *113:8 0.0258393 |
| 12 *90:8 *113:8 0.0231893 |
| *RES |
| 1 *419:io_out[8] *113:7 10.305 |
| 2 *113:7 *113:8 315.09 |
| 3 *113:8 *113:10 4.5 |
| 4 *113:10 *113:11 279.27 |
| 5 *113:11 *113:13 4.5 |
| 6 *113:13 *113:14 392.67 |
| 7 *113:14 io_out[8] 1.395 |
| *END |
| |
| *D_NET *114 0.243096 |
| *CONN |
| *P io_out[9] O |
| *I *419:io_out[9] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[9] 0.00399814 |
| 2 *419:io_out[9] 0.000326062 |
| 3 *114:11 0.0714666 |
| 4 *114:10 0.0674685 |
| 5 *114:8 0.0282229 |
| 6 *114:7 0.0285489 |
| 7 *81:8 *114:8 0.0320995 |
| 8 *87:8 *114:8 0.00366209 |
| 9 *88:8 *114:8 0.00730371 |
| *RES |
| 1 *419:io_out[9] *114:7 7.605 |
| 2 *114:7 *114:8 312.75 |
| 3 *114:8 *114:10 4.5 |
| 4 *114:10 *114:11 734.58 |
| 5 *114:11 io_out[9] 43.245 |
| *END |
| |
| *D_NET *313 0.10389 |
| *CONN |
| *P wb_clk_i I |
| *I *419:wb_clk_i I *D wrapped_vga_clock |
| *CAP |
| 1 wb_clk_i 0.000291157 |
| 2 *419:wb_clk_i 0.0134678 |
| 3 *313:15 0.0134678 |
| 4 *313:13 0.0355052 |
| 5 *313:11 0.0357963 |
| 6 *64:14 *419:wb_clk_i 0.00536215 |
| 7 *94:8 *313:13 0 |
| *RES |
| 1 wb_clk_i *313:11 3.015 |
| 2 *313:11 *313:13 354.33 |
| 3 *313:13 *313:15 4.5 |
| 4 *313:15 *419:wb_clk_i 170.325 |
| *END |
| |
| *D_NET *314 0.135663 |
| *CONN |
| *P wb_rst_i I |
| *I *419:wb_rst_i I *D wrapped_vga_clock |
| *CAP |
| 1 wb_rst_i 0.026316 |
| 2 *419:wb_rst_i 0.000232589 |
| 3 *314:11 0.00350075 |
| 4 *314:10 0.00326817 |
| 5 *314:8 0.0241334 |
| 6 *314:7 0.0241334 |
| 7 *314:5 0.026316 |
| 8 *28:5 *314:8 0 |
| 9 *66:8 *314:11 0.00486914 |
| 10 *101:8 *314:11 0.0228931 |
| 11 *105:15 *314:5 0 |
| *RES |
| 1 wb_rst_i *314:5 262.665 |
| 2 *314:5 *314:7 4.5 |
| 3 *314:7 *314:8 262.53 |
| 4 *314:8 *314:10 4.5 |
| 5 *314:10 *314:11 54.99 |
| 6 *314:11 *419:wb_rst_i 6.525 |
| *END |
