| *SPEF "ieee 1481-1999" |
| *DESIGN "user_project_wrapper" |
| *DATE "11:11:11 Fri 11 11, 1111" |
| *VENDOR "OpenRCX" |
| *PROGRAM "Parallel Extraction" |
| *VERSION "1.0" |
| *DESIGN_FLOW "NAME_SCOPE LOCAL" "PIN_CAP NONE" |
| *DIVIDER / |
| *DELIMITER : |
| *BUS_DELIMITER [] |
| *T_UNIT 1 NS |
| *C_UNIT 1 PF |
| *R_UNIT 1 OHM |
| *L_UNIT 1 HENRY |
| |
| *NAME_MAP |
| *1 io_in[0] |
| *2 io_in[10] |
| *3 io_in[11] |
| *4 io_in[12] |
| *5 io_in[13] |
| *6 io_in[14] |
| *7 io_in[15] |
| *8 io_in[16] |
| *9 io_in[17] |
| *10 io_in[18] |
| *11 io_in[19] |
| *12 io_in[1] |
| *13 io_in[20] |
| *14 io_in[21] |
| *15 io_in[22] |
| *16 io_in[23] |
| *17 io_in[24] |
| *18 io_in[25] |
| *19 io_in[26] |
| *20 io_in[27] |
| *21 io_in[28] |
| *22 io_in[29] |
| *23 io_in[2] |
| *24 io_in[30] |
| *25 io_in[31] |
| *26 io_in[32] |
| *27 io_in[33] |
| *28 io_in[34] |
| *29 io_in[35] |
| *30 io_in[36] |
| *31 io_in[37] |
| *32 io_in[3] |
| *33 io_in[4] |
| *34 io_in[5] |
| *35 io_in[6] |
| *36 io_in[7] |
| *37 io_in[8] |
| *38 io_in[9] |
| *39 io_oeb[0] |
| *40 io_oeb[10] |
| *41 io_oeb[11] |
| *42 io_oeb[12] |
| *43 io_oeb[13] |
| *44 io_oeb[14] |
| *45 io_oeb[15] |
| *46 io_oeb[16] |
| *47 io_oeb[17] |
| *48 io_oeb[18] |
| *49 io_oeb[19] |
| *50 io_oeb[1] |
| *51 io_oeb[20] |
| *52 io_oeb[21] |
| *53 io_oeb[22] |
| *54 io_oeb[23] |
| *55 io_oeb[24] |
| *56 io_oeb[25] |
| *57 io_oeb[26] |
| *58 io_oeb[27] |
| *59 io_oeb[28] |
| *60 io_oeb[29] |
| *61 io_oeb[2] |
| *62 io_oeb[30] |
| *63 io_oeb[31] |
| *64 io_oeb[32] |
| *65 io_oeb[33] |
| *66 io_oeb[34] |
| *67 io_oeb[35] |
| *68 io_oeb[36] |
| *69 io_oeb[37] |
| *70 io_oeb[3] |
| *71 io_oeb[4] |
| *72 io_oeb[5] |
| *73 io_oeb[6] |
| *74 io_oeb[7] |
| *75 io_oeb[8] |
| *76 io_oeb[9] |
| *77 io_out[0] |
| *78 io_out[10] |
| *79 io_out[11] |
| *80 io_out[12] |
| *81 io_out[13] |
| *82 io_out[14] |
| *83 io_out[15] |
| *84 io_out[16] |
| *85 io_out[17] |
| *86 io_out[18] |
| *87 io_out[19] |
| *88 io_out[1] |
| *89 io_out[20] |
| *90 io_out[21] |
| *91 io_out[22] |
| *92 io_out[23] |
| *93 io_out[24] |
| *94 io_out[25] |
| *95 io_out[26] |
| *96 io_out[27] |
| *97 io_out[28] |
| *98 io_out[29] |
| *99 io_out[2] |
| *100 io_out[30] |
| *101 io_out[31] |
| *102 io_out[32] |
| *103 io_out[33] |
| *104 io_out[34] |
| *105 io_out[35] |
| *106 io_out[36] |
| *107 io_out[37] |
| *108 io_out[3] |
| *109 io_out[4] |
| *110 io_out[5] |
| *111 io_out[6] |
| *112 io_out[7] |
| *113 io_out[8] |
| *114 io_out[9] |
| *115 la_data_in[0] |
| *116 la_data_in[10] |
| *117 la_data_in[11] |
| *118 la_data_in[12] |
| *119 la_data_in[13] |
| *120 la_data_in[14] |
| *121 la_data_in[15] |
| *122 la_data_in[16] |
| *123 la_data_in[17] |
| *124 la_data_in[18] |
| *125 la_data_in[19] |
| *126 la_data_in[1] |
| *127 la_data_in[20] |
| *128 la_data_in[21] |
| *129 la_data_in[22] |
| *130 la_data_in[23] |
| *131 la_data_in[24] |
| *132 la_data_in[25] |
| *133 la_data_in[26] |
| *134 la_data_in[27] |
| *135 la_data_in[28] |
| *136 la_data_in[29] |
| *137 la_data_in[2] |
| *138 la_data_in[30] |
| *139 la_data_in[31] |
| *140 la_data_in[32] |
| *141 la_data_in[33] |
| *142 la_data_in[34] |
| *143 la_data_in[35] |
| *144 la_data_in[36] |
| *145 la_data_in[37] |
| *146 la_data_in[38] |
| *147 la_data_in[39] |
| *148 la_data_in[3] |
| *149 la_data_in[40] |
| *150 la_data_in[41] |
| *151 la_data_in[42] |
| *152 la_data_in[43] |
| *153 la_data_in[44] |
| *154 la_data_in[45] |
| *155 la_data_in[46] |
| *156 la_data_in[47] |
| *157 la_data_in[48] |
| *158 la_data_in[49] |
| *159 la_data_in[4] |
| *160 la_data_in[50] |
| *161 la_data_in[51] |
| *162 la_data_in[52] |
| *163 la_data_in[53] |
| *164 la_data_in[54] |
| *165 la_data_in[55] |
| *166 la_data_in[56] |
| *167 la_data_in[57] |
| *168 la_data_in[58] |
| *169 la_data_in[59] |
| *170 la_data_in[5] |
| *171 la_data_in[60] |
| *172 la_data_in[61] |
| *173 la_data_in[62] |
| *174 la_data_in[63] |
| *175 la_data_in[6] |
| *176 la_data_in[7] |
| *177 la_data_in[8] |
| *178 la_data_in[9] |
| *179 la_data_out[0] |
| *180 la_data_out[10] |
| *181 la_data_out[11] |
| *182 la_data_out[12] |
| *183 la_data_out[13] |
| *184 la_data_out[14] |
| *185 la_data_out[15] |
| *186 la_data_out[16] |
| *187 la_data_out[17] |
| *188 la_data_out[18] |
| *189 la_data_out[19] |
| *190 la_data_out[1] |
| *191 la_data_out[20] |
| *192 la_data_out[21] |
| *193 la_data_out[22] |
| *194 la_data_out[23] |
| *195 la_data_out[24] |
| *196 la_data_out[25] |
| *197 la_data_out[26] |
| *198 la_data_out[27] |
| *199 la_data_out[28] |
| *200 la_data_out[29] |
| *201 la_data_out[2] |
| *202 la_data_out[30] |
| *203 la_data_out[31] |
| *204 la_data_out[32] |
| *205 la_data_out[33] |
| *206 la_data_out[34] |
| *207 la_data_out[35] |
| *208 la_data_out[36] |
| *209 la_data_out[37] |
| *210 la_data_out[38] |
| *211 la_data_out[39] |
| *212 la_data_out[3] |
| *213 la_data_out[40] |
| *214 la_data_out[41] |
| *215 la_data_out[42] |
| *216 la_data_out[43] |
| *217 la_data_out[44] |
| *218 la_data_out[45] |
| *219 la_data_out[46] |
| *220 la_data_out[47] |
| *221 la_data_out[48] |
| *222 la_data_out[49] |
| *223 la_data_out[4] |
| *224 la_data_out[50] |
| *225 la_data_out[51] |
| *226 la_data_out[52] |
| *227 la_data_out[53] |
| *228 la_data_out[54] |
| *229 la_data_out[55] |
| *230 la_data_out[56] |
| *231 la_data_out[57] |
| *232 la_data_out[58] |
| *233 la_data_out[59] |
| *234 la_data_out[5] |
| *235 la_data_out[60] |
| *236 la_data_out[61] |
| *237 la_data_out[62] |
| *238 la_data_out[63] |
| *239 la_data_out[6] |
| *240 la_data_out[7] |
| *241 la_data_out[8] |
| *242 la_data_out[9] |
| *243 la_oenb[0] |
| *244 la_oenb[10] |
| *245 la_oenb[11] |
| *246 la_oenb[12] |
| *247 la_oenb[13] |
| *248 la_oenb[14] |
| *249 la_oenb[15] |
| *250 la_oenb[16] |
| *251 la_oenb[17] |
| *252 la_oenb[18] |
| *253 la_oenb[19] |
| *254 la_oenb[1] |
| *255 la_oenb[20] |
| *256 la_oenb[21] |
| *257 la_oenb[22] |
| *258 la_oenb[23] |
| *259 la_oenb[24] |
| *260 la_oenb[25] |
| *261 la_oenb[26] |
| *262 la_oenb[27] |
| *263 la_oenb[28] |
| *264 la_oenb[29] |
| *265 la_oenb[2] |
| *266 la_oenb[30] |
| *267 la_oenb[31] |
| *268 la_oenb[32] |
| *269 la_oenb[33] |
| *270 la_oenb[34] |
| *271 la_oenb[35] |
| *272 la_oenb[36] |
| *273 la_oenb[37] |
| *274 la_oenb[38] |
| *275 la_oenb[39] |
| *276 la_oenb[3] |
| *277 la_oenb[40] |
| *278 la_oenb[41] |
| *279 la_oenb[42] |
| *280 la_oenb[43] |
| *281 la_oenb[44] |
| *282 la_oenb[45] |
| *283 la_oenb[46] |
| *284 la_oenb[47] |
| *285 la_oenb[48] |
| *286 la_oenb[49] |
| *287 la_oenb[4] |
| *288 la_oenb[50] |
| *289 la_oenb[51] |
| *290 la_oenb[52] |
| *291 la_oenb[53] |
| *292 la_oenb[54] |
| *293 la_oenb[55] |
| *294 la_oenb[56] |
| *295 la_oenb[57] |
| *296 la_oenb[58] |
| *297 la_oenb[59] |
| *298 la_oenb[5] |
| *299 la_oenb[60] |
| *300 la_oenb[61] |
| *301 la_oenb[62] |
| *302 la_oenb[63] |
| *303 la_oenb[6] |
| *304 la_oenb[7] |
| *305 la_oenb[8] |
| *306 la_oenb[9] |
| *307 user_clock2 |
| *308 user_irq[0] |
| *309 user_irq[1] |
| *310 user_irq[2] |
| *313 wb_clk_i |
| *314 wb_rst_i |
| *315 wbs_ack_o |
| *316 wbs_adr_i[0] |
| *317 wbs_adr_i[10] |
| *318 wbs_adr_i[11] |
| *319 wbs_adr_i[12] |
| *320 wbs_adr_i[13] |
| *321 wbs_adr_i[14] |
| *322 wbs_adr_i[15] |
| *323 wbs_adr_i[16] |
| *324 wbs_adr_i[17] |
| *325 wbs_adr_i[18] |
| *326 wbs_adr_i[19] |
| *327 wbs_adr_i[1] |
| *328 wbs_adr_i[20] |
| *329 wbs_adr_i[21] |
| *330 wbs_adr_i[22] |
| *331 wbs_adr_i[23] |
| *332 wbs_adr_i[24] |
| *333 wbs_adr_i[25] |
| *334 wbs_adr_i[26] |
| *335 wbs_adr_i[27] |
| *336 wbs_adr_i[28] |
| *337 wbs_adr_i[29] |
| *338 wbs_adr_i[2] |
| *339 wbs_adr_i[30] |
| *340 wbs_adr_i[31] |
| *341 wbs_adr_i[3] |
| *342 wbs_adr_i[4] |
| *343 wbs_adr_i[5] |
| *344 wbs_adr_i[6] |
| *345 wbs_adr_i[7] |
| *346 wbs_adr_i[8] |
| *347 wbs_adr_i[9] |
| *348 wbs_cyc_i |
| *349 wbs_dat_i[0] |
| *350 wbs_dat_i[10] |
| *351 wbs_dat_i[11] |
| *352 wbs_dat_i[12] |
| *353 wbs_dat_i[13] |
| *354 wbs_dat_i[14] |
| *355 wbs_dat_i[15] |
| *356 wbs_dat_i[16] |
| *357 wbs_dat_i[17] |
| *358 wbs_dat_i[18] |
| *359 wbs_dat_i[19] |
| *360 wbs_dat_i[1] |
| *361 wbs_dat_i[20] |
| *362 wbs_dat_i[21] |
| *363 wbs_dat_i[22] |
| *364 wbs_dat_i[23] |
| *365 wbs_dat_i[24] |
| *366 wbs_dat_i[25] |
| *367 wbs_dat_i[26] |
| *368 wbs_dat_i[27] |
| *369 wbs_dat_i[28] |
| *370 wbs_dat_i[29] |
| *371 wbs_dat_i[2] |
| *372 wbs_dat_i[30] |
| *373 wbs_dat_i[31] |
| *374 wbs_dat_i[3] |
| *375 wbs_dat_i[4] |
| *376 wbs_dat_i[5] |
| *377 wbs_dat_i[6] |
| *378 wbs_dat_i[7] |
| *379 wbs_dat_i[8] |
| *380 wbs_dat_i[9] |
| *381 wbs_dat_o[0] |
| *382 wbs_dat_o[10] |
| *383 wbs_dat_o[11] |
| *384 wbs_dat_o[12] |
| *385 wbs_dat_o[13] |
| *386 wbs_dat_o[14] |
| *387 wbs_dat_o[15] |
| *388 wbs_dat_o[16] |
| *389 wbs_dat_o[17] |
| *390 wbs_dat_o[18] |
| *391 wbs_dat_o[19] |
| *392 wbs_dat_o[1] |
| *393 wbs_dat_o[20] |
| *394 wbs_dat_o[21] |
| *395 wbs_dat_o[22] |
| *396 wbs_dat_o[23] |
| *397 wbs_dat_o[24] |
| *398 wbs_dat_o[25] |
| *399 wbs_dat_o[26] |
| *400 wbs_dat_o[27] |
| *401 wbs_dat_o[28] |
| *402 wbs_dat_o[29] |
| *403 wbs_dat_o[2] |
| *404 wbs_dat_o[30] |
| *405 wbs_dat_o[31] |
| *406 wbs_dat_o[3] |
| *407 wbs_dat_o[4] |
| *408 wbs_dat_o[5] |
| *409 wbs_dat_o[6] |
| *410 wbs_dat_o[7] |
| *411 wbs_dat_o[8] |
| *412 wbs_dat_o[9] |
| *413 wbs_sel_i[0] |
| *414 wbs_sel_i[1] |
| *415 wbs_sel_i[2] |
| *416 wbs_sel_i[3] |
| *417 wbs_stb_i |
| *418 wbs_we_i |
| *419 wrapped_vga_clock |
| |
| *PORTS |
| io_in[0] I |
| io_in[10] I |
| io_in[11] I |
| io_in[12] I |
| io_in[13] I |
| io_in[14] I |
| io_in[15] I |
| io_in[16] I |
| io_in[17] I |
| io_in[18] I |
| io_in[19] I |
| io_in[1] I |
| io_in[20] I |
| io_in[21] I |
| io_in[22] I |
| io_in[23] I |
| io_in[24] I |
| io_in[25] I |
| io_in[26] I |
| io_in[27] I |
| io_in[28] I |
| io_in[29] I |
| io_in[2] I |
| io_in[30] I |
| io_in[31] I |
| io_in[32] I |
| io_in[33] I |
| io_in[34] I |
| io_in[35] I |
| io_in[36] I |
| io_in[37] I |
| io_in[3] I |
| io_in[4] I |
| io_in[5] I |
| io_in[6] I |
| io_in[7] I |
| io_in[8] I |
| io_in[9] I |
| io_oeb[0] O |
| io_oeb[10] O |
| io_oeb[11] O |
| io_oeb[12] O |
| io_oeb[13] O |
| io_oeb[14] O |
| io_oeb[15] O |
| io_oeb[16] O |
| io_oeb[17] O |
| io_oeb[18] O |
| io_oeb[19] O |
| io_oeb[1] O |
| io_oeb[20] O |
| io_oeb[21] O |
| io_oeb[22] O |
| io_oeb[23] O |
| io_oeb[24] O |
| io_oeb[25] O |
| io_oeb[26] O |
| io_oeb[27] O |
| io_oeb[28] O |
| io_oeb[29] O |
| io_oeb[2] O |
| io_oeb[30] O |
| io_oeb[31] O |
| io_oeb[32] O |
| io_oeb[33] O |
| io_oeb[34] O |
| io_oeb[35] O |
| io_oeb[36] O |
| io_oeb[37] O |
| io_oeb[3] O |
| io_oeb[4] O |
| io_oeb[5] O |
| io_oeb[6] O |
| io_oeb[7] O |
| io_oeb[8] O |
| io_oeb[9] O |
| io_out[0] O |
| io_out[10] O |
| io_out[11] O |
| io_out[12] O |
| io_out[13] O |
| io_out[14] O |
| io_out[15] O |
| io_out[16] O |
| io_out[17] O |
| io_out[18] O |
| io_out[19] O |
| io_out[1] O |
| io_out[20] O |
| io_out[21] O |
| io_out[22] O |
| io_out[23] O |
| io_out[24] O |
| io_out[25] O |
| io_out[26] O |
| io_out[27] O |
| io_out[28] O |
| io_out[29] O |
| io_out[2] O |
| io_out[30] O |
| io_out[31] O |
| io_out[32] O |
| io_out[33] O |
| io_out[34] O |
| io_out[35] O |
| io_out[36] O |
| io_out[37] O |
| io_out[3] O |
| io_out[4] O |
| io_out[5] O |
| io_out[6] O |
| io_out[7] O |
| io_out[8] O |
| io_out[9] O |
| la_data_in[0] I |
| la_data_in[10] I |
| la_data_in[11] I |
| la_data_in[12] I |
| la_data_in[13] I |
| la_data_in[14] I |
| la_data_in[15] I |
| la_data_in[16] I |
| la_data_in[17] I |
| la_data_in[18] I |
| la_data_in[19] I |
| la_data_in[1] I |
| la_data_in[20] I |
| la_data_in[21] I |
| la_data_in[22] I |
| la_data_in[23] I |
| la_data_in[24] I |
| la_data_in[25] I |
| la_data_in[26] I |
| la_data_in[27] I |
| la_data_in[28] I |
| la_data_in[29] I |
| la_data_in[2] I |
| la_data_in[30] I |
| la_data_in[31] I |
| la_data_in[32] I |
| la_data_in[33] I |
| la_data_in[34] I |
| la_data_in[35] I |
| la_data_in[36] I |
| la_data_in[37] I |
| la_data_in[38] I |
| la_data_in[39] I |
| la_data_in[3] I |
| la_data_in[40] I |
| la_data_in[41] I |
| la_data_in[42] I |
| la_data_in[43] I |
| la_data_in[44] I |
| la_data_in[45] I |
| la_data_in[46] I |
| la_data_in[47] I |
| la_data_in[48] I |
| la_data_in[49] I |
| la_data_in[4] I |
| la_data_in[50] I |
| la_data_in[51] I |
| la_data_in[52] I |
| la_data_in[53] I |
| la_data_in[54] I |
| la_data_in[55] I |
| la_data_in[56] I |
| la_data_in[57] I |
| la_data_in[58] I |
| la_data_in[59] I |
| la_data_in[5] I |
| la_data_in[60] I |
| la_data_in[61] I |
| la_data_in[62] I |
| la_data_in[63] I |
| la_data_in[6] I |
| la_data_in[7] I |
| la_data_in[8] I |
| la_data_in[9] I |
| la_data_out[0] O |
| la_data_out[10] O |
| la_data_out[11] O |
| la_data_out[12] O |
| la_data_out[13] O |
| la_data_out[14] O |
| la_data_out[15] O |
| la_data_out[16] O |
| la_data_out[17] O |
| la_data_out[18] O |
| la_data_out[19] O |
| la_data_out[1] O |
| la_data_out[20] O |
| la_data_out[21] O |
| la_data_out[22] O |
| la_data_out[23] O |
| la_data_out[24] O |
| la_data_out[25] O |
| la_data_out[26] O |
| la_data_out[27] O |
| la_data_out[28] O |
| la_data_out[29] O |
| la_data_out[2] O |
| la_data_out[30] O |
| la_data_out[31] O |
| la_data_out[32] O |
| la_data_out[33] O |
| la_data_out[34] O |
| la_data_out[35] O |
| la_data_out[36] O |
| la_data_out[37] O |
| la_data_out[38] O |
| la_data_out[39] O |
| la_data_out[3] O |
| la_data_out[40] O |
| la_data_out[41] O |
| la_data_out[42] O |
| la_data_out[43] O |
| la_data_out[44] O |
| la_data_out[45] O |
| la_data_out[46] O |
| la_data_out[47] O |
| la_data_out[48] O |
| la_data_out[49] O |
| la_data_out[4] O |
| la_data_out[50] O |
| la_data_out[51] O |
| la_data_out[52] O |
| la_data_out[53] O |
| la_data_out[54] O |
| la_data_out[55] O |
| la_data_out[56] O |
| la_data_out[57] O |
| la_data_out[58] O |
| la_data_out[59] O |
| la_data_out[5] O |
| la_data_out[60] O |
| la_data_out[61] O |
| la_data_out[62] O |
| la_data_out[63] O |
| la_data_out[6] O |
| la_data_out[7] O |
| la_data_out[8] O |
| la_data_out[9] O |
| la_oenb[0] I |
| la_oenb[10] I |
| la_oenb[11] I |
| la_oenb[12] I |
| la_oenb[13] I |
| la_oenb[14] I |
| la_oenb[15] I |
| la_oenb[16] I |
| la_oenb[17] I |
| la_oenb[18] I |
| la_oenb[19] I |
| la_oenb[1] I |
| la_oenb[20] I |
| la_oenb[21] I |
| la_oenb[22] I |
| la_oenb[23] I |
| la_oenb[24] I |
| la_oenb[25] I |
| la_oenb[26] I |
| la_oenb[27] I |
| la_oenb[28] I |
| la_oenb[29] I |
| la_oenb[2] I |
| la_oenb[30] I |
| la_oenb[31] I |
| la_oenb[32] I |
| la_oenb[33] I |
| la_oenb[34] I |
| la_oenb[35] I |
| la_oenb[36] I |
| la_oenb[37] I |
| la_oenb[38] I |
| la_oenb[39] I |
| la_oenb[3] I |
| la_oenb[40] I |
| la_oenb[41] I |
| la_oenb[42] I |
| la_oenb[43] I |
| la_oenb[44] I |
| la_oenb[45] I |
| la_oenb[46] I |
| la_oenb[47] I |
| la_oenb[48] I |
| la_oenb[49] I |
| la_oenb[4] I |
| la_oenb[50] I |
| la_oenb[51] I |
| la_oenb[52] I |
| la_oenb[53] I |
| la_oenb[54] I |
| la_oenb[55] I |
| la_oenb[56] I |
| la_oenb[57] I |
| la_oenb[58] I |
| la_oenb[59] I |
| la_oenb[5] I |
| la_oenb[60] I |
| la_oenb[61] I |
| la_oenb[62] I |
| la_oenb[63] I |
| la_oenb[6] I |
| la_oenb[7] I |
| la_oenb[8] I |
| la_oenb[9] I |
| user_clock2 I |
| user_irq[0] O |
| user_irq[1] O |
| user_irq[2] O |
| wb_clk_i I |
| wb_rst_i I |
| wbs_ack_o O |
| wbs_adr_i[0] I |
| wbs_adr_i[10] I |
| wbs_adr_i[11] I |
| wbs_adr_i[12] I |
| wbs_adr_i[13] I |
| wbs_adr_i[14] I |
| wbs_adr_i[15] I |
| wbs_adr_i[16] I |
| wbs_adr_i[17] I |
| wbs_adr_i[18] I |
| wbs_adr_i[19] I |
| wbs_adr_i[1] I |
| wbs_adr_i[20] I |
| wbs_adr_i[21] I |
| wbs_adr_i[22] I |
| wbs_adr_i[23] I |
| wbs_adr_i[24] I |
| wbs_adr_i[25] I |
| wbs_adr_i[26] I |
| wbs_adr_i[27] I |
| wbs_adr_i[28] I |
| wbs_adr_i[29] I |
| wbs_adr_i[2] I |
| wbs_adr_i[30] I |
| wbs_adr_i[31] I |
| wbs_adr_i[3] I |
| wbs_adr_i[4] I |
| wbs_adr_i[5] I |
| wbs_adr_i[6] I |
| wbs_adr_i[7] I |
| wbs_adr_i[8] I |
| wbs_adr_i[9] I |
| wbs_cyc_i I |
| wbs_dat_i[0] I |
| wbs_dat_i[10] I |
| wbs_dat_i[11] I |
| wbs_dat_i[12] I |
| wbs_dat_i[13] I |
| wbs_dat_i[14] I |
| wbs_dat_i[15] I |
| wbs_dat_i[16] I |
| wbs_dat_i[17] I |
| wbs_dat_i[18] I |
| wbs_dat_i[19] I |
| wbs_dat_i[1] I |
| wbs_dat_i[20] I |
| wbs_dat_i[21] I |
| wbs_dat_i[22] I |
| wbs_dat_i[23] I |
| wbs_dat_i[24] I |
| wbs_dat_i[25] I |
| wbs_dat_i[26] I |
| wbs_dat_i[27] I |
| wbs_dat_i[28] I |
| wbs_dat_i[29] I |
| wbs_dat_i[2] I |
| wbs_dat_i[30] I |
| wbs_dat_i[31] I |
| wbs_dat_i[3] I |
| wbs_dat_i[4] I |
| wbs_dat_i[5] I |
| wbs_dat_i[6] I |
| wbs_dat_i[7] I |
| wbs_dat_i[8] I |
| wbs_dat_i[9] I |
| wbs_dat_o[0] O |
| wbs_dat_o[10] O |
| wbs_dat_o[11] O |
| wbs_dat_o[12] O |
| wbs_dat_o[13] O |
| wbs_dat_o[14] O |
| wbs_dat_o[15] O |
| wbs_dat_o[16] O |
| wbs_dat_o[17] O |
| wbs_dat_o[18] O |
| wbs_dat_o[19] O |
| wbs_dat_o[1] O |
| wbs_dat_o[20] O |
| wbs_dat_o[21] O |
| wbs_dat_o[22] O |
| wbs_dat_o[23] O |
| wbs_dat_o[24] O |
| wbs_dat_o[25] O |
| wbs_dat_o[26] O |
| wbs_dat_o[27] O |
| wbs_dat_o[28] O |
| wbs_dat_o[29] O |
| wbs_dat_o[2] O |
| wbs_dat_o[30] O |
| wbs_dat_o[31] O |
| wbs_dat_o[3] O |
| wbs_dat_o[4] O |
| wbs_dat_o[5] O |
| wbs_dat_o[6] O |
| wbs_dat_o[7] O |
| wbs_dat_o[8] O |
| wbs_dat_o[9] O |
| wbs_sel_i[0] I |
| wbs_sel_i[1] I |
| wbs_sel_i[2] I |
| wbs_sel_i[3] I |
| wbs_stb_i I |
| wbs_we_i I |
| |
| *D_NET *1 0.194351 |
| *CONN |
| *P io_in[0] I |
| *I *419:io_in[0] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[0] 0.00336627 |
| 2 *419:io_in[0] 0.000830991 |
| 3 *1:12 0.0343335 |
| 4 *1:11 0.0335025 |
| 5 *1:9 0.0572169 |
| 6 *1:7 0.0605832 |
| 7 *1:12 *21:16 0.000113545 |
| 8 *1:12 *57:8 0 |
| 9 *1:12 *66:8 0.00440371 |
| *RES |
| 1 io_in[0] *1:7 37.305 |
| 2 *1:7 *1:9 627.84 |
| 3 *1:9 *1:11 4.5 |
| 4 *1:11 *1:12 353.79 |
| 5 *1:12 *419:io_in[0] 12.645 |
| *END |
| |
| *D_NET *2 0.194733 |
| *CONN |
| *P io_in[10] I |
| *I *419:io_in[10] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[10] 0.00340899 |
| 2 *419:io_in[10] 0.0140486 |
| 3 *2:14 0.0140486 |
| 4 *2:12 0.0355252 |
| 5 *2:11 0.0355252 |
| 6 *2:9 0.0443837 |
| 7 *2:7 0.0477927 |
| *RES |
| 1 io_in[10] *2:7 37.305 |
| 2 *2:7 *2:9 484.74 |
| 3 *2:9 *2:11 4.5 |
| 4 *2:11 *2:12 353.79 |
| 5 *2:12 *2:14 4.5 |
| 6 *2:14 *419:io_in[10] 151.245 |
| *END |
| |
| *D_NET *3 0.224892 |
| *CONN |
| *P io_in[11] I |
| *I *419:io_in[11] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[11] 0.00025457 |
| 2 *419:io_in[11] 0.000252292 |
| 3 *3:16 0.0345199 |
| 4 *3:15 0.0342676 |
| 5 *3:13 0.0776713 |
| 6 *3:11 0.0779259 |
| 7 *3:16 *91:16 0 |
| *RES |
| 1 io_in[11] *3:11 3.195 |
| 2 *3:11 *3:13 760.23 |
| 3 *3:13 *3:15 4.5 |
| 4 *3:15 *3:16 342.09 |
| 5 *3:16 *419:io_in[11] 11.5904 |
| *END |
| |
| *D_NET *4 0.487975 |
| *CONN |
| *P io_in[12] I |
| *I *419:io_in[12] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[12] 0.000731295 |
| 2 *419:io_in[12] 0.000677067 |
| 3 *4:14 0.00512728 |
| 4 *4:13 0.00445021 |
| 5 *4:11 0.0705451 |
| 6 *4:10 0.0705451 |
| 7 *4:8 0.0208446 |
| 8 *4:7 0.0215759 |
| 9 *4:8 *79:14 0.202969 |
| 10 *4:11 *73:14 0 |
| 11 *4:14 *7:13 0.00777426 |
| 12 *4:14 *71:8 0.00668995 |
| 13 *4:14 *114:8 0.0760445 |
| *RES |
| 1 io_in[12] *4:7 12.645 |
| 2 *4:7 *4:8 340.11 |
| 3 *4:8 *4:10 4.5 |
| 4 *4:10 *4:11 765.99 |
| 5 *4:11 *4:13 4.5 |
| 6 *4:13 *4:14 111.51 |
| 7 *4:14 *419:io_in[12] 10.485 |
| *END |
| |
| *D_NET *5 0.220841 |
| *CONN |
| *P io_in[13] I |
| *I *419:io_in[13] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[13] 0.0626378 |
| 2 *419:io_in[13] 0.000378631 |
| 3 *5:8 0.047429 |
| 4 *5:7 0.0470504 |
| 5 *5:5 0.0626378 |
| 6 *5:8 *419:io_in[21] 0.0007071 |
| *RES |
| 1 io_in[13] *5:5 684.585 |
| 2 *5:5 *5:7 4.5 |
| 3 *5:7 *5:8 471.69 |
| 4 *5:8 *419:io_in[13] 12.9052 |
| *END |
| |
| *D_NET *6 0.236566 |
| *CONN |
| *P io_in[14] I |
| *I *419:io_in[14] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[14] 0.000186415 |
| 2 *419:io_in[14] 0.000378631 |
| 3 *6:16 0.0536098 |
| 4 *6:15 0.0532312 |
| 5 *6:13 0.0641421 |
| 6 *6:11 0.0643286 |
| 7 *6:16 *38:16 0 |
| 8 *6:16 *93:13 0.000689199 |
| *RES |
| 1 io_in[14] *6:11 2.655 |
| 2 *6:11 *6:13 700.83 |
| 3 *6:13 *6:15 4.5 |
| 4 *6:15 *6:16 533.79 |
| 5 *6:16 *419:io_in[14] 12.9052 |
| *END |
| |
| *D_NET *7 0.476758 |
| *CONN |
| *P io_in[15] I |
| *I *419:io_in[15] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[15] 0.0589672 |
| 2 *419:io_in[15] 0.000683931 |
| 3 *7:13 0.0029325 |
| 4 *7:8 0.0580182 |
| 5 *7:7 0.0557696 |
| 6 *7:5 0.0589672 |
| 7 *7:8 *11:16 0.224246 |
| 8 *7:8 *15:17 0.0014299 |
| 9 *7:8 *55:13 4.14464e-05 |
| 10 *7:8 *69:7 0.000746036 |
| 11 *7:8 *101:13 0.00491141 |
| 12 *7:13 *71:8 0.0022709 |
| 13 *4:14 *7:13 0.00777426 |
| *RES |
| 1 io_in[15] *7:5 588.825 |
| 2 *7:5 *7:7 4.5 |
| 3 *7:7 *7:8 756.81 |
| 4 *7:8 *7:13 46.53 |
| 5 *7:13 *419:io_in[15] 6.345 |
| *END |
| |
| *D_NET *8 0.329984 |
| *CONN |
| *P io_in[16] I |
| *I *419:io_in[16] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[16] 0.000194772 |
| 2 *419:io_in[16] 0.00118063 |
| 3 *8:19 0.0104169 |
| 4 *8:18 0.00923632 |
| 5 *8:16 0.0603722 |
| 6 *8:15 0.0603722 |
| 7 *8:13 0.0524871 |
| 8 *8:11 0.0526819 |
| 9 *8:16 *73:14 0 |
| 10 *8:19 *74:8 0.0830414 |
| *RES |
| 1 io_in[16] *8:11 2.655 |
| 2 *8:11 *8:13 524.07 |
| 3 *8:13 *8:15 4.5 |
| 4 *8:15 *8:16 654.03 |
| 5 *8:16 *8:18 4.5 |
| 6 *8:18 *8:19 145.53 |
| 7 *8:19 *419:io_in[16] 16.065 |
| *END |
| |
| *D_NET *9 0.283795 |
| *CONN |
| *P io_in[17] I |
| *I *419:io_in[17] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[17] 0.000794415 |
| 2 *419:io_in[17] 0.0016455 |
| 3 *9:14 0.0345951 |
| 4 *9:13 0.0329496 |
| 5 *9:11 0.0568572 |
| 6 *9:10 0.0568572 |
| 7 *9:8 0.00582111 |
| 8 *9:7 0.00661552 |
| 9 *9:8 *10:8 0.00254896 |
| 10 *9:8 *83:11 0.0244948 |
| 11 *9:14 *111:13 0.0606156 |
| *RES |
| 1 io_in[17] *9:7 12.465 |
| 2 *9:7 *9:8 110.07 |
| 3 *9:8 *9:10 4.5 |
| 4 *9:10 *9:11 567.45 |
| 5 *9:11 *9:13 4.5 |
| 6 *9:13 *9:14 395.55 |
| 7 *9:14 *419:io_in[17] 29.383 |
| *END |
| |
| *D_NET *10 0.57453 |
| *CONN |
| *P io_in[18] I |
| *I *419:io_in[18] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[18] 0.000818101 |
| 2 *419:io_in[18] 0.000635821 |
| 3 *10:14 0.00282837 |
| 4 *10:13 0.00219255 |
| 5 *10:11 0.0685204 |
| 6 *10:10 0.0685204 |
| 7 *10:8 0.0109655 |
| 8 *10:7 0.0117836 |
| 9 *10:8 *83:11 0.0976688 |
| 10 *10:8 *86:14 0.0843644 |
| 11 *10:8 *87:11 0.12092 |
| 12 *10:14 *45:10 0.00292197 |
| 13 *10:14 *47:10 0.0197078 |
| 14 *10:14 *53:13 0.0119987 |
| 15 *10:14 *59:8 0.0439519 |
| 16 *10:14 *64:8 0.00963632 |
| 17 *10:14 *75:11 0.0131164 |
| 18 *10:14 *84:8 0.0014299 |
| 19 *10:14 *99:10 0 |
| 20 *10:14 *108:10 0 |
| 21 *9:8 *10:8 0.00254896 |
| *RES |
| 1 io_in[18] *10:7 12.645 |
| 2 *10:7 *10:8 316.89 |
| 3 *10:8 *10:10 4.5 |
| 4 *10:10 *10:11 682.83 |
| 5 *10:11 *10:13 4.5 |
| 6 *10:13 *10:14 88.83 |
| 7 *10:14 *419:io_in[18] 10.125 |
| *END |
| |
| *D_NET *11 0.4438 |
| *CONN |
| *P io_in[19] I |
| *I *419:io_in[19] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[19] 0.00014121 |
| 2 *419:io_in[19] 7.83558e-05 |
| 3 *11:19 0.00261535 |
| 4 *11:18 0.002537 |
| 5 *11:16 0.0166328 |
| 6 *11:15 0.0166328 |
| 7 *11:13 0.0589684 |
| 8 *11:11 0.0591096 |
| 9 *11:16 *40:12 0.000705627 |
| 10 *11:16 *70:11 0 |
| 11 *11:19 *15:17 0.0201926 |
| 12 *11:19 *50:8 0.00536015 |
| 13 *11:19 *79:10 0.0183513 |
| 14 *11:19 *87:8 0.0115386 |
| 15 *11:19 *109:10 0.00668995 |
| 16 *7:8 *11:16 0.224246 |
| *RES |
| 1 io_in[19] *11:11 2.115 |
| 2 *11:11 *11:13 588.69 |
| 3 *11:13 *11:15 4.5 |
| 4 *11:15 *11:16 324.63 |
| 5 *11:16 *11:18 4.5 |
| 6 *11:18 *11:19 84.15 |
| 7 *11:19 *419:io_in[19] 5.265 |
| *END |
| |
| *D_NET *12 0.18101 |
| *CONN |
| *P io_in[1] I |
| *I *419:io_in[1] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[1] 0.000257266 |
| 2 *419:io_in[1] 0.0146097 |
| 3 *12:18 0.0146097 |
| 4 *12:16 0.0286439 |
| 5 *12:15 0.0286439 |
| 6 *12:13 0.046994 |
| 7 *12:11 0.0472512 |
| *RES |
| 1 io_in[1] *12:11 3.195 |
| 2 *12:11 *12:13 515.97 |
| 3 *12:13 *12:15 4.5 |
| 4 *12:15 *12:16 285.21 |
| 5 *12:16 *12:18 4.5 |
| 6 *12:18 *419:io_in[1] 156.645 |
| *END |
| |
| *D_NET *13 0.161985 |
| *CONN |
| *P io_in[20] I |
| *I *419:io_in[20] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[20] 0.068233 |
| 2 *419:io_in[20] 0.00231596 |
| 3 *13:8 0.0127458 |
| 4 *13:7 0.0104299 |
| 5 *13:5 0.068233 |
| 6 *419:io_in[20] *47:14 2.71992e-05 |
| *RES |
| 1 io_in[20] *13:5 680.625 |
| 2 *13:5 *13:7 4.5 |
| 3 *13:7 *13:8 101.43 |
| 4 *13:8 *419:io_in[20] 32.535 |
| *END |
| |
| *D_NET *14 0.133753 |
| *CONN |
| *P io_in[21] I |
| *I *419:io_in[21] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[21] 0.00219212 |
| 2 *419:io_in[21] 0.00112253 |
| 3 *14:11 0.0586425 |
| 4 *14:10 0.0597121 |
| 5 *419:io_in[21] *49:11 0 |
| 6 *14:10 io_out[21] 0.00851726 |
| 7 *14:10 *87:11 0.0028598 |
| 8 *14:11 *100:12 0 |
| 9 *5:8 *419:io_in[21] 0.0007071 |
| *RES |
| 1 io_in[21] *14:10 41.715 |
| 2 *14:10 *14:11 574.29 |
| 3 *14:11 *419:io_in[21] 30.6274 |
| *END |
| |
| *D_NET *15 0.144745 |
| *CONN |
| *P io_in[22] I |
| *I *419:io_in[22] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[22] 0.0037316 |
| 2 *419:io_in[22] 0.000122764 |
| 3 *15:17 0.00212818 |
| 4 *15:9 0.0571196 |
| 5 *15:7 0.0588458 |
| 6 *15:9 *91:16 0.000490239 |
| 7 *15:17 *69:7 0.000683868 |
| 8 *7:8 *15:17 0.0014299 |
| 9 *11:19 *15:17 0.0201926 |
| *RES |
| 1 io_in[22] *15:7 37.305 |
| 2 *15:7 *15:9 552.6 |
| 3 *15:9 *15:17 49.32 |
| 4 *15:17 *419:io_in[22] 0.945 |
| *END |
| |
| *D_NET *16 0.148108 |
| *CONN |
| *P io_in[23] I |
| *I *419:io_in[23] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[23] 0.00161926 |
| 2 *419:io_in[23] 0.0080462 |
| 3 *16:13 0.0080462 |
| 4 *16:11 0.0591976 |
| 5 *16:10 0.0608168 |
| 6 *16:10 *54:14 0.0103824 |
| *RES |
| 1 io_in[23] *16:10 32.175 |
| 2 *16:10 *16:11 591.21 |
| 3 *16:11 *16:13 4.5 |
| 4 *16:13 *419:io_in[23] 85.365 |
| *END |
| |
| *D_NET *17 0.205295 |
| *CONN |
| *P io_in[24] I |
| *I *419:io_in[24] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[24] 0.000142137 |
| 2 *419:io_in[24] 0.00014207 |
| 3 *17:16 0.0595554 |
| 4 *17:15 0.0594133 |
| 5 *17:13 0.0291406 |
| 6 *17:11 0.0292827 |
| 7 *17:16 *26:16 0.0149757 |
| 8 *17:16 *40:12 0.00153439 |
| 9 *17:16 *55:14 0 |
| 10 *17:16 *107:8 0.011109 |
| *RES |
| 1 io_in[24] *17:11 1.935 |
| 2 *17:11 *17:13 285.75 |
| 3 *17:13 *17:15 4.5 |
| 4 *17:15 *17:16 627.57 |
| 5 *17:16 *419:io_in[24] 5.985 |
| *END |
| |
| *D_NET *18 0.155835 |
| *CONN |
| *P io_in[25] I |
| *I *419:io_in[25] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[25] 8.93818e-05 |
| 2 *419:io_in[25] 0.0095265 |
| 3 *18:18 0.0095265 |
| 4 *18:16 0.0594369 |
| 5 *18:15 0.0594369 |
| 6 *18:13 0.00886476 |
| 7 *18:11 0.00895415 |
| *RES |
| 1 io_in[25] *18:11 1.395 |
| 2 *18:11 *18:13 87.21 |
| 3 *18:13 *18:15 4.5 |
| 4 *18:15 *18:16 593.55 |
| 5 *18:16 *18:18 4.5 |
| 6 *18:18 *419:io_in[25] 101.565 |
| *END |
| |
| *D_NET *19 0.124325 |
| *CONN |
| *P io_in[26] I |
| *I *419:io_in[26] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[26] 0.00123228 |
| 2 *419:io_in[26] 0.00157035 |
| 3 *19:12 0.0462186 |
| 4 *19:11 0.0446482 |
| 5 *19:9 0.0147115 |
| 6 *19:7 0.0159438 |
| *RES |
| 1 io_in[26] *19:7 13.185 |
| 2 *19:7 *19:9 160.74 |
| 3 *19:9 *19:11 4.5 |
| 4 *19:11 *19:12 446.13 |
| 5 *19:12 *419:io_in[26] 19.665 |
| *END |
| |
| *D_NET *20 0.119049 |
| *CONN |
| *P io_in[27] I |
| *I *419:io_in[27] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[27] 0.000253241 |
| 2 *419:io_in[27] 0.000925634 |
| 3 *20:16 0.0371804 |
| 4 *20:15 0.0362548 |
| 5 *20:13 0.0214381 |
| 6 *20:11 0.0216913 |
| 7 *419:io_in[27] *49:11 0 |
| 8 *419:io_in[27] *52:13 0.00130557 |
| *RES |
| 1 io_in[27] *20:11 3.015 |
| 2 *20:11 *20:13 233.01 |
| 3 *20:13 *20:15 4.5 |
| 4 *20:15 *20:16 362.07 |
| 5 *20:16 *419:io_in[27] 27.7474 |
| *END |
| |
| *D_NET *21 0.300482 |
| *CONN |
| *P io_in[28] I |
| *I *419:io_in[28] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[28] 0.000182736 |
| 2 *419:io_in[28] 0.000721204 |
| 3 *21:16 0.0179088 |
| 4 *21:15 0.0171876 |
| 5 *21:13 0.0269256 |
| 6 *21:11 0.0271084 |
| 7 *21:16 *57:8 0.210335 |
| 8 *1:12 *21:16 0.000113545 |
| *RES |
| 1 io_in[28] *21:11 2.475 |
| 2 *21:11 *21:13 291.33 |
| 3 *21:13 *21:15 4.5 |
| 4 *21:15 *21:16 308.43 |
| 5 *21:16 *419:io_in[28] 11.565 |
| *END |
| |
| *D_NET *22 0.209204 |
| *CONN |
| *P io_in[29] I |
| *I *419:io_in[29] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[29] 0.000132518 |
| 2 *419:io_in[29] 0.000317452 |
| 3 *22:19 0.00202594 |
| 4 *22:18 0.00170849 |
| 5 *22:16 0.0334002 |
| 6 *22:15 0.0334002 |
| 7 *22:13 0.0152455 |
| 8 *22:11 0.015378 |
| 9 *22:19 *44:8 0.0343795 |
| 10 *22:19 *53:14 0.00224847 |
| 11 *22:19 *73:8 0.0573821 |
| 12 *22:19 *95:8 0.00754325 |
| 13 *22:19 *109:11 0.00604285 |
| *RES |
| 1 io_in[29] *22:11 1.935 |
| 2 *22:11 *22:13 165.51 |
| 3 *22:13 *22:15 4.5 |
| 4 *22:15 *22:16 332.91 |
| 5 *22:16 *22:18 4.5 |
| 6 *22:18 *22:19 115.83 |
| 7 *22:19 *419:io_in[29] 7.245 |
| *END |
| |
| *D_NET *23 0.156186 |
| *CONN |
| *P io_in[2] I |
| *I *419:io_in[2] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[2] 0.000125412 |
| 2 *419:io_in[2] 0.0163452 |
| 3 *23:18 0.0163452 |
| 4 *23:16 0.016364 |
| 5 *23:15 0.016364 |
| 6 *23:13 0.0452584 |
| 7 *23:11 0.0453838 |
| *RES |
| 1 io_in[2] *23:11 2.115 |
| 2 *23:11 *23:13 497.07 |
| 3 *23:13 *23:15 4.5 |
| 4 *23:15 *23:16 163.17 |
| 5 *23:16 *23:18 4.5 |
| 6 *23:18 *419:io_in[2] 175.545 |
| *END |
| |
| *D_NET *24 0.0783582 |
| *CONN |
| *P io_in[30] I |
| *I *419:io_in[30] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[30] 8.47422e-05 |
| 2 *419:io_in[30] 0.00111356 |
| 3 *24:16 0.0170666 |
| 4 *24:15 0.015953 |
| 5 *24:13 0.0210502 |
| 6 *24:11 0.021135 |
| 7 *419:io_in[30] *49:11 0 |
| 8 *419:io_in[30] *52:13 0.00180292 |
| 9 *419:io_in[30] *98:11 0 |
| 10 *24:16 *49:10 0.000152161 |
| 11 *24:16 *52:14 0 |
| *RES |
| 1 io_in[30] *24:11 1.395 |
| 2 *24:11 *24:13 227.61 |
| 3 *24:13 *24:15 4.5 |
| 4 *24:15 *24:16 159.57 |
| 5 *24:16 *419:io_in[30] 29.9074 |
| *END |
| |
| *D_NET *25 0.117043 |
| *CONN |
| *P io_in[31] I |
| *I *419:io_in[31] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[31] 0.00124651 |
| 2 *419:io_in[31] 0.000643714 |
| 3 *25:15 0.0113374 |
| 4 *25:14 0.0106937 |
| 5 *25:12 0.0201154 |
| 6 *25:11 0.0201154 |
| 7 *25:9 0.00885578 |
| 8 *25:7 0.0101023 |
| 9 *419:io_in[31] *53:13 5.21694e-05 |
| 10 *25:15 *53:14 0 |
| 11 *25:15 *63:8 0.0139253 |
| 12 *25:15 *96:10 0.0199554 |
| *RES |
| 1 io_in[31] *25:7 13.185 |
| 2 *25:7 *25:9 95.94 |
| 3 *25:9 *25:11 4.5 |
| 4 *25:11 *25:12 200.07 |
| 5 *25:12 *25:14 4.5 |
| 6 *25:14 *25:15 137.97 |
| 7 *25:15 *419:io_in[31] 10.575 |
| *END |
| |
| *D_NET *26 0.0850684 |
| *CONN |
| *P io_in[32] I |
| *I *419:io_in[32] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[32] 0.000240014 |
| 2 *419:io_in[32] 0.000202416 |
| 3 *26:16 0.00478404 |
| 4 *26:15 0.00458163 |
| 5 *26:13 0.0266773 |
| 6 *26:11 0.0269173 |
| 7 *26:16 *107:8 0.00668995 |
| 8 *17:16 *26:16 0.0149757 |
| *RES |
| 1 io_in[32] *26:11 3.015 |
| 2 *26:11 *26:13 286.11 |
| 3 *26:13 *26:15 4.5 |
| 4 *26:15 *26:16 75.69 |
| 5 *26:16 *419:io_in[32] 6.345 |
| *END |
| |
| *D_NET *27 0.0358893 |
| *CONN |
| *P io_in[33] I |
| *I *419:io_in[33] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[33] 0.000180294 |
| 2 *419:io_in[33] 0.0092151 |
| 3 *27:18 0.00939345 |
| 4 *27:13 0.00854925 |
| 5 *27:11 0.00855119 |
| *RES |
| 1 io_in[33] *27:11 2.475 |
| 2 *27:11 *27:13 91.17 |
| 3 *27:13 *27:18 10.71 |
| 4 *27:18 *419:io_in[33] 97.605 |
| *END |
| |
| *D_NET *28 0.0411965 |
| *CONN |
| *P io_in[34] I |
| *I *419:io_in[34] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[34] 0.000132518 |
| 2 *419:io_in[34] 0.00109494 |
| 3 *28:13 0.0204657 |
| 4 *28:11 0.0195033 |
| 5 *28:13 *314:16 0 |
| *RES |
| 1 io_in[34] *28:11 1.935 |
| 2 *28:11 *28:13 211.05 |
| 3 *28:13 *419:io_in[34] 14.625 |
| *END |
| |
| *D_NET *29 0.057255 |
| *CONN |
| *P io_in[35] I |
| *I *419:io_in[35] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[35] 0.00241972 |
| 2 *419:io_in[35] 0.000147297 |
| 3 *29:22 0.0057042 |
| 4 *29:21 0.0055569 |
| 5 *29:19 0.0182038 |
| 6 *29:18 0.0205036 |
| 7 *29:15 0.00471948 |
| 8 *29:19 *66:11 0 |
| *RES |
| 1 io_in[35] *29:15 31.005 |
| 2 *29:15 *29:18 27.45 |
| 3 *29:18 *29:19 198.63 |
| 4 *29:19 *29:21 4.5 |
| 5 *29:21 *29:22 54.81 |
| 6 *29:22 *419:io_in[35] 1.485 |
| *END |
| |
| *D_NET *30 0.175863 |
| *CONN |
| *P io_in[36] I |
| *I *419:io_in[36] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[36] 0.00123228 |
| 2 *419:io_in[36] 0.00014207 |
| 3 *30:12 0.00813969 |
| 4 *30:11 0.00799762 |
| 5 *30:9 0.0249494 |
| 6 *30:7 0.0261817 |
| 7 *30:12 *45:13 0.000724234 |
| 8 *30:12 *68:10 0.00111397 |
| 9 *30:12 *68:12 0 |
| 10 *30:12 *107:8 0.105382 |
| *RES |
| 1 io_in[36] *30:7 13.185 |
| 2 *30:7 *30:9 272.88 |
| 3 *30:9 *30:11 4.5 |
| 4 *30:11 *30:12 154.53 |
| 5 *30:12 *419:io_in[36] 5.985 |
| *END |
| |
| *D_NET *31 0.0934581 |
| *CONN |
| *P io_in[37] I |
| *I *419:io_in[37] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[37] 0.000240014 |
| 2 *419:io_in[37] 0.00883198 |
| 3 *31:18 0.00883198 |
| 4 *31:16 0.0289097 |
| 5 *31:15 0.0289097 |
| 6 *31:13 0.00874735 |
| 7 *31:11 0.00898736 |
| *RES |
| 1 io_in[37] *31:11 3.015 |
| 2 *31:11 *31:13 95.31 |
| 3 *31:13 *31:15 4.5 |
| 4 *31:15 *31:16 288.45 |
| 5 *31:16 *31:18 4.5 |
| 6 *31:18 *419:io_in[37] 93.465 |
| *END |
| |
| *D_NET *32 0.219104 |
| *CONN |
| *P io_in[3] I |
| *I *419:io_in[3] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[3] 0.0600853 |
| 2 *419:io_in[3] 0.000302502 |
| 3 *32:11 0.00336037 |
| 4 *32:10 0.00305787 |
| 5 *32:8 0.0169599 |
| 6 *32:7 0.0169599 |
| 7 *32:5 0.0600853 |
| 8 *32:8 *60:8 0 |
| 9 *32:11 *70:11 0.0555172 |
| 10 *32:11 *79:11 0.00277586 |
| *RES |
| 1 io_in[3] *32:5 659.025 |
| 2 *32:5 *32:7 4.5 |
| 3 *32:7 *32:8 167.67 |
| 4 *32:8 *32:10 4.5 |
| 5 *32:10 *32:11 80.37 |
| 6 *32:11 *419:io_in[3] 16.3174 |
| *END |
| |
| *D_NET *33 0.145185 |
| *CONN |
| *P io_in[4] I |
| *I *419:io_in[4] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[4] 0.00138055 |
| 2 *419:io_in[4] 0.0673341 |
| 3 *33:10 0.0712118 |
| 4 *33:7 0.00525821 |
| *RES |
| 1 io_in[4] *33:7 18.225 |
| 2 *33:7 *33:10 43.11 |
| 3 *33:10 *419:io_in[4] 658.845 |
| *END |
| |
| *D_NET *34 0.125012 |
| *CONN |
| *P io_in[5] I |
| *I *419:io_in[5] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[5] 0.00336627 |
| 2 *419:io_in[5] 0.0028157 |
| 3 *34:9 0.0591395 |
| 4 *34:7 0.0596901 |
| 5 *34:9 *76:5 0 |
| *RES |
| 1 io_in[5] *34:7 37.305 |
| 2 *34:7 *34:9 615.06 |
| 3 *34:9 *419:io_in[5] 34.875 |
| *END |
| |
| *D_NET *35 0.242168 |
| *CONN |
| *P io_in[6] I |
| *I *419:io_in[6] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[6] 0.000257266 |
| 2 *419:io_in[6] 0.000986417 |
| 3 *35:19 0.00992841 |
| 4 *35:18 0.0104383 |
| 5 *35:13 0.0512109 |
| 6 *35:11 0.0499718 |
| 7 *35:19 *419:io_in[8] 7.14953e-05 |
| 8 *35:19 *49:11 0.119304 |
| *RES |
| 1 io_in[6] *35:11 3.195 |
| 2 *35:11 *35:13 542.97 |
| 3 *35:13 *35:18 23.85 |
| 4 *35:18 *35:19 172.71 |
| 5 *35:19 *419:io_in[6] 22.9774 |
| *END |
| |
| *D_NET *36 0.153075 |
| *CONN |
| *P io_in[7] I |
| *I *419:io_in[7] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[7] 0.000125412 |
| 2 *419:io_in[7] 0.0153612 |
| 3 *36:18 0.0153612 |
| 4 *36:16 0.0145807 |
| 5 *36:15 0.0145807 |
| 6 *36:13 0.0464702 |
| 7 *36:11 0.0465956 |
| *RES |
| 1 io_in[7] *36:11 2.115 |
| 2 *36:11 *36:13 507.87 |
| 3 *36:13 *36:15 4.5 |
| 4 *36:15 *36:16 144.81 |
| 5 *36:16 *36:18 4.5 |
| 6 *36:18 *419:io_in[7] 164.745 |
| *END |
| |
| *D_NET *37 0.161892 |
| *CONN |
| *P io_in[8] I |
| *I *419:io_in[8] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[8] 0.0652527 |
| 2 *419:io_in[8] 0.00126636 |
| 3 *37:8 0.0156576 |
| 4 *37:7 0.0143913 |
| 5 *37:5 0.0652527 |
| 6 *419:io_in[8] *100:13 0 |
| 7 *35:19 *419:io_in[8] 7.14953e-05 |
| *RES |
| 1 io_in[8] *37:5 710.325 |
| 2 *37:5 *37:7 4.5 |
| 3 *37:7 *37:8 143.37 |
| 4 *37:8 *419:io_in[8] 30.6274 |
| *END |
| |
| *D_NET *38 0.175625 |
| *CONN |
| *P io_in[9] I |
| *I *419:io_in[9] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[9] 0.000182043 |
| 2 *419:io_in[9] 0.00100668 |
| 3 *38:16 0.021887 |
| 4 *38:15 0.0208803 |
| 5 *38:13 0.0644688 |
| 6 *38:11 0.0646509 |
| 7 *419:io_in[9] *49:11 0 |
| 8 *419:io_in[9] *93:13 0.00254896 |
| 9 *419:io_in[9] *93:14 0 |
| 10 *6:16 *38:16 0 |
| *RES |
| 1 io_in[9] *38:11 2.655 |
| 2 *38:11 *38:13 702.27 |
| 3 *38:13 *38:15 4.5 |
| 4 *38:15 *38:16 208.17 |
| 5 *38:16 *419:io_in[9] 29.5474 |
| *END |
| |
| *D_NET *39 0.211126 |
| *CONN |
| *P io_oeb[0] O |
| *I *419:io_oeb[0] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[0] 0.0590321 |
| 2 *419:io_oeb[0] 0.000655246 |
| 3 *39:16 0.0590321 |
| 4 *39:14 0.0321022 |
| 5 *39:13 0.0345297 |
| 6 *39:10 0.00308268 |
| 7 *39:10 *97:12 0 |
| 8 *39:13 *61:11 0.0189618 |
| 9 *39:13 *110:11 0.00373007 |
| *RES |
| 1 *419:io_oeb[0] *39:10 19.1974 |
| 2 *39:10 *39:13 48.15 |
| 3 *39:13 *39:14 319.05 |
| 4 *39:14 *39:16 4.5 |
| 5 *39:16 io_oeb[0] 648.225 |
| *END |
| |
| *D_NET *40 0.202086 |
| *CONN |
| *P io_oeb[10] O |
| *I *419:io_oeb[10] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[10] 0.0595842 |
| 2 *419:io_oeb[10] 0.00106184 |
| 3 *40:15 0.0595842 |
| 4 *40:13 0.0322206 |
| 5 *40:12 0.0332824 |
| 6 *40:12 *55:14 0 |
| 7 *40:12 *70:11 0.0141125 |
| 8 *11:16 *40:12 0.000705627 |
| 9 *17:16 *40:12 0.00153439 |
| *RES |
| 1 *419:io_oeb[10] *40:12 32.625 |
| 2 *40:12 *40:13 321.57 |
| 3 *40:13 *40:15 4.5 |
| 4 *40:15 io_oeb[10] 650.925 |
| *END |
| |
| *D_NET *41 0.212647 |
| *CONN |
| *P io_oeb[11] O |
| *I *419:io_oeb[11] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[11] 0.000157263 |
| 2 *419:io_oeb[11] 0.0111141 |
| 3 *41:11 0.0463459 |
| 4 *41:10 0.0461886 |
| 5 *41:8 0.0402778 |
| 6 *41:7 0.0402778 |
| 7 *41:5 0.0111141 |
| 8 *41:5 *110:17 0.0171713 |
| *RES |
| 1 *419:io_oeb[11] *41:5 167.445 |
| 2 *41:5 *41:7 4.5 |
| 3 *41:7 *41:8 401.85 |
| 4 *41:8 *41:10 4.5 |
| 5 *41:10 *41:11 505.17 |
| 6 *41:11 io_oeb[11] 2.475 |
| *END |
| |
| *D_NET *42 0.345428 |
| *CONN |
| *P io_oeb[12] O |
| *I *419:io_oeb[12] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[12] 0.00336458 |
| 2 *419:io_oeb[12] 0.000181173 |
| 3 *42:14 0.0570806 |
| 4 *42:13 0.053716 |
| 5 *42:11 0.054963 |
| 6 *42:10 0.054963 |
| 7 *42:8 0.00190105 |
| 8 *42:7 0.00208222 |
| 9 *42:8 *71:11 0.0302764 |
| 10 *42:8 *86:8 0.000670915 |
| 11 *42:8 *89:8 0.0862288 |
| 12 *42:11 *51:16 0 |
| *RES |
| 1 *419:io_oeb[12] *42:7 6.165 |
| 2 *42:7 *42:8 131.49 |
| 3 *42:8 *42:10 4.5 |
| 4 *42:10 *42:11 547.83 |
| 5 *42:11 *42:13 4.5 |
| 6 *42:13 *42:14 587.34 |
| 7 *42:14 io_oeb[12] 37.125 |
| *END |
| |
| *D_NET *43 0.242047 |
| *CONN |
| *P io_oeb[13] O |
| *I *419:io_oeb[13] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[13] 0.000205039 |
| 2 *419:io_oeb[13] 0.000378631 |
| 3 *43:13 0.069327 |
| 4 *43:12 0.0691219 |
| 5 *43:10 0.051224 |
| 6 *43:9 0.0516027 |
| 7 *43:10 *56:14 0 |
| 8 *43:10 *70:10 0.000187963 |
| *RES |
| 1 *419:io_oeb[13] *43:9 12.9052 |
| 2 *43:9 *43:10 512.19 |
| 3 *43:10 *43:12 4.5 |
| 4 *43:12 *43:13 754.83 |
| 5 *43:13 io_oeb[13] 3.015 |
| *END |
| |
| *D_NET *44 0.339044 |
| *CONN |
| *P io_oeb[14] O |
| *I *419:io_oeb[14] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[14] 0.000109487 |
| 2 *419:io_oeb[14] 0.000329474 |
| 3 *44:14 0.059105 |
| 4 *44:13 0.0589955 |
| 5 *44:11 0.0677944 |
| 6 *44:10 0.0677944 |
| 7 *44:8 0.00107513 |
| 8 *44:7 0.0014046 |
| 9 *44:8 *73:8 0.00692156 |
| 10 *44:8 *78:8 0.0341308 |
| 11 *44:8 *109:11 0.00700445 |
| 12 *22:19 *44:8 0.0343795 |
| *RES |
| 1 *419:io_oeb[14] *44:7 7.425 |
| 2 *44:7 *44:8 79.83 |
| 3 *44:8 *44:10 4.5 |
| 4 *44:10 *44:11 675.99 |
| 5 *44:11 *44:13 4.5 |
| 6 *44:13 *44:14 645.57 |
| 7 *44:14 io_oeb[14] 1.935 |
| *END |
| |
| *D_NET *45 0.341179 |
| *CONN |
| *P io_oeb[15] O |
| *I *419:io_oeb[15] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[15] 0.00023048 |
| 2 *419:io_oeb[15] 0.000683192 |
| 3 *45:17 0.0689415 |
| 4 *45:16 0.068711 |
| 5 *45:14 0.0320007 |
| 6 *45:13 0.0322236 |
| 7 *45:10 0.00227016 |
| 8 *45:7 0.00273045 |
| 9 *45:10 *47:10 0.00727387 |
| 10 *45:10 *53:13 0.0119988 |
| 11 *45:10 *108:10 6.52783e-05 |
| 12 *45:13 *68:10 0.000724234 |
| 13 *45:14 *71:11 0.0729374 |
| 14 *45:14 *82:11 0.0367424 |
| 15 *10:14 *45:10 0.00292197 |
| 16 *30:12 *45:13 0.000724234 |
| *RES |
| 1 *419:io_oeb[15] *45:7 10.485 |
| 2 *45:7 *45:10 45.09 |
| 3 *45:10 *45:13 9.81 |
| 4 *45:13 *45:14 581.13 |
| 5 *45:14 *45:16 4.5 |
| 6 *45:16 *45:17 686.07 |
| 7 *45:17 io_oeb[15] 3.015 |
| *END |
| |
| *D_NET *46 0.228361 |
| *CONN |
| *P io_oeb[16] O |
| *I *419:io_oeb[16] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[16] 0.00243728 |
| 2 *419:io_oeb[16] 0.0410819 |
| 3 *46:8 0.0620011 |
| 4 *46:7 0.0595638 |
| 5 *46:5 0.0410819 |
| 6 io_oeb[16] *83:11 0.0221946 |
| *RES |
| 1 *419:io_oeb[16] *46:5 445.545 |
| 2 *46:5 *46:7 4.5 |
| 3 *46:7 *46:8 594.45 |
| 4 *46:8 io_oeb[16] 49.275 |
| *END |
| |
| *D_NET *47 0.455088 |
| *CONN |
| *P io_oeb[17] O |
| *I *419:io_oeb[17] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[17] 0.06845 |
| 2 *419:io_oeb[17] 0.00189132 |
| 3 *47:16 0.06845 |
| 4 *47:14 0.0173098 |
| 5 *47:13 0.018198 |
| 6 *47:10 0.00277951 |
| 7 *47:10 *75:11 0.00058025 |
| 8 *47:14 *84:14 0.220516 |
| 9 *47:14 *89:16 0.0299037 |
| 10 *419:io_in[20] *47:14 2.71992e-05 |
| 11 *10:14 *47:10 0.0197078 |
| 12 *45:10 *47:10 0.00727387 |
| *RES |
| 1 *419:io_oeb[17] *47:10 45.855 |
| 2 *47:10 *47:13 12.51 |
| 3 *47:13 *47:14 350.01 |
| 4 *47:14 *47:16 4.5 |
| 5 *47:16 io_oeb[17] 683.145 |
| *END |
| |
| *D_NET *48 0.179479 |
| *CONN |
| *P io_oeb[18] O |
| *I *419:io_oeb[18] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[18] 0.000176918 |
| 2 *419:io_oeb[18] 0.0271201 |
| 3 *48:8 0.0626195 |
| 4 *48:7 0.0624426 |
| 5 *48:5 0.0271201 |
| *RES |
| 1 *419:io_oeb[18] *48:5 263.385 |
| 2 *48:5 *48:7 4.5 |
| 3 *48:7 *48:8 623.07 |
| 4 *48:8 io_oeb[18] 2.475 |
| *END |
| |
| *D_NET *49 0.26349 |
| *CONN |
| *P io_oeb[19] O |
| *I *419:io_oeb[19] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[19] 0.00105436 |
| 2 *419:io_oeb[19] 0.000852172 |
| 3 *49:14 0.0582843 |
| 4 *49:13 0.05723 |
| 5 *49:11 0.0127219 |
| 6 *49:10 0.0135741 |
| 7 io_oeb[19] *87:11 0.000146876 |
| 8 *49:10 *52:14 0.000170062 |
| 9 *49:11 *52:13 0 |
| 10 *49:11 *93:13 0 |
| 11 *419:io_in[21] *49:11 0 |
| 12 *419:io_in[27] *49:11 0 |
| 13 *419:io_in[30] *49:11 0 |
| 14 *419:io_in[9] *49:11 0 |
| 15 *24:16 *49:10 0.000152161 |
| 16 *35:19 *49:11 0.119304 |
| *RES |
| 1 *419:io_oeb[19] *49:10 22.7974 |
| 2 *49:10 *49:11 212.67 |
| 3 *49:11 *49:13 4.5 |
| 4 *49:13 *49:14 571.59 |
| 5 *49:14 io_oeb[19] 20.115 |
| *END |
| |
| *D_NET *50 0.200082 |
| *CONN |
| *P io_oeb[1] O |
| *I *419:io_oeb[1] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[1] 0.000157263 |
| 2 *419:io_oeb[1] 0.000138676 |
| 3 *50:11 0.0702685 |
| 4 *50:10 0.0701113 |
| 5 *50:8 0.0182079 |
| 6 *50:7 0.0183466 |
| 7 *50:8 *109:10 0.0174921 |
| 8 *11:19 *50:8 0.00536015 |
| *RES |
| 1 *419:io_oeb[1] *50:7 5.625 |
| 2 *50:7 *50:8 201.87 |
| 3 *50:8 *50:10 4.5 |
| 4 *50:10 *50:11 769.23 |
| 5 *50:11 io_oeb[1] 2.475 |
| *END |
| |
| *D_NET *51 0.17855 |
| *CONN |
| *P io_oeb[20] O |
| *I *419:io_oeb[20] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[20] 0.00023048 |
| 2 *419:io_oeb[20] 0.0014035 |
| 3 *51:16 0.0580602 |
| 4 *51:15 0.0578298 |
| 5 *51:13 0.00895335 |
| 6 *51:12 0.0103569 |
| 7 *51:13 *97:13 0.0392291 |
| 8 *51:13 *100:13 0.00248679 |
| 9 *42:11 *51:16 0 |
| *RES |
| 1 *419:io_oeb[20] *51:12 27.043 |
| 2 *51:12 *51:13 124.29 |
| 3 *51:13 *51:15 4.5 |
| 4 *51:15 *51:16 577.71 |
| 5 *51:16 io_oeb[20] 3.015 |
| *END |
| |
| *D_NET *52 0.123014 |
| *CONN |
| *P io_oeb[21] O |
| *I *419:io_oeb[21] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[21] 0.000123355 |
| 2 *419:io_oeb[21] 0.00135689 |
| 3 *52:14 0.0583539 |
| 4 *52:13 0.0595874 |
| 5 *52:13 *98:11 0.000313958 |
| 6 *419:io_in[27] *52:13 0.00130557 |
| 7 *419:io_in[30] *52:13 0.00180292 |
| 8 *24:16 *52:14 0 |
| 9 *49:10 *52:14 0.000170062 |
| 10 *49:11 *52:13 0 |
| *RES |
| 1 *419:io_oeb[21] *52:13 34.7674 |
| 2 *52:13 *52:14 582.39 |
| 3 *52:14 io_oeb[21] 1.935 |
| *END |
| |
| *D_NET *53 0.226014 |
| *CONN |
| *P io_oeb[22] O |
| *I *419:io_oeb[22] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[22] 0.0689922 |
| 2 *419:io_oeb[22] 0.00109655 |
| 3 *53:16 0.0689922 |
| 4 *53:14 0.00831452 |
| 5 *53:13 0.00941107 |
| 6 *53:14 *95:8 0.00144234 |
| 7 *53:14 *109:11 0.041467 |
| 8 *419:io_in[31] *53:13 5.21694e-05 |
| 9 *10:14 *53:13 0.0119987 |
| 10 *22:19 *53:14 0.00224847 |
| 11 *25:15 *53:14 0 |
| 12 *45:10 *53:13 0.0119988 |
| *RES |
| 1 *419:io_oeb[22] *53:13 39.105 |
| 2 *53:13 *53:14 124.11 |
| 3 *53:14 *53:16 4.5 |
| 4 *53:16 io_oeb[22] 688.725 |
| *END |
| |
| *D_NET *54 0.228108 |
| *CONN |
| *P io_oeb[23] O |
| *I *419:io_oeb[23] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[23] 0.000830123 |
| 2 *419:io_oeb[23] 0.000246394 |
| 3 *54:14 0.0140151 |
| 4 *54:13 0.0131849 |
| 5 *54:11 0.0680329 |
| 6 *54:10 0.0680329 |
| 7 *54:8 0.000643663 |
| 8 *54:7 0.000890057 |
| 9 *54:8 *58:8 0.0184644 |
| 10 *54:8 *73:8 0.00298407 |
| 11 *54:8 *89:8 0.00522218 |
| 12 *54:8 *95:8 0.0251788 |
| 13 *16:10 *54:14 0.0103824 |
| *RES |
| 1 *419:io_oeb[23] *54:7 6.705 |
| 2 *54:7 *54:8 49.41 |
| 3 *54:8 *54:10 4.5 |
| 4 *54:10 *54:11 679.23 |
| 5 *54:11 *54:13 4.5 |
| 6 *54:13 *54:14 150.75 |
| 7 *54:14 io_oeb[23] 12.825 |
| *END |
| |
| *D_NET *55 0.219202 |
| *CONN |
| *P io_oeb[24] O |
| *I *419:io_oeb[24] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[24] 0.000180294 |
| 2 *419:io_oeb[24] 0.000469779 |
| 3 *55:17 0.026257 |
| 4 *55:16 0.0260768 |
| 5 *55:14 0.0529407 |
| 6 *55:13 0.0532229 |
| 7 *55:8 0.00429957 |
| 8 *55:7 0.00448714 |
| 9 *55:8 *101:8 0.0481799 |
| 10 *55:13 *101:13 0.00304632 |
| 11 *7:8 *55:13 4.14464e-05 |
| 12 *17:16 *55:14 0 |
| 13 *40:12 *55:14 0 |
| *RES |
| 1 *419:io_oeb[24] *55:7 9.045 |
| 2 *55:7 *55:8 70.65 |
| 3 *55:8 *55:13 13.59 |
| 4 *55:13 *55:14 528.39 |
| 5 *55:14 *55:16 4.5 |
| 6 *55:16 *55:17 284.31 |
| 7 *55:17 io_oeb[24] 2.475 |
| *END |
| |
| *D_NET *56 0.140686 |
| *CONN |
| *P io_oeb[25] O |
| *I *419:io_oeb[25] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[25] 0.000132518 |
| 2 *419:io_oeb[25] 0.0013741 |
| 3 *56:17 0.018559 |
| 4 *56:16 0.0184265 |
| 5 *56:14 0.0455408 |
| 6 *56:13 0.0469149 |
| 7 *56:13 *98:11 0.00951176 |
| 8 *56:13 *112:13 0.000226914 |
| 9 *43:10 *56:14 0 |
| *RES |
| 1 *419:io_oeb[25] *56:13 38.5474 |
| 2 *56:13 *56:14 454.95 |
| 3 *56:14 *56:16 4.5 |
| 4 *56:16 *56:17 200.61 |
| 5 *56:17 io_oeb[25] 1.935 |
| *END |
| |
| *D_NET *57 0.326885 |
| *CONN |
| *P io_oeb[26] O |
| *I *419:io_oeb[26] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[26] 8.47422e-05 |
| 2 *419:io_oeb[26] 0.00069103 |
| 3 *57:11 0.0269135 |
| 4 *57:10 0.0268288 |
| 5 *57:8 0.0284306 |
| 6 *57:7 0.0291216 |
| 7 *57:8 *66:8 0.00448043 |
| 8 *1:12 *57:8 0 |
| 9 *21:16 *57:8 0.210335 |
| *RES |
| 1 *419:io_oeb[26] *57:7 11.385 |
| 2 *57:7 *57:8 422.91 |
| 3 *57:8 *57:10 4.5 |
| 4 *57:10 *57:11 291.15 |
| 5 *57:11 io_oeb[26] 1.395 |
| *END |
| |
| *D_NET *58 0.165434 |
| *CONN |
| *P io_oeb[27] O |
| *I *419:io_oeb[27] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[27] 0.000829874 |
| 2 *419:io_oeb[27] 0.000222713 |
| 3 *58:11 0.0432993 |
| 4 *58:10 0.0424694 |
| 5 *58:8 0.00968529 |
| 6 *58:7 0.009908 |
| 7 *58:8 *71:11 0.000580251 |
| 8 *58:8 *89:8 0.00453839 |
| 9 *58:8 *95:8 0.0354367 |
| 10 *54:8 *58:8 0.0184644 |
| *RES |
| 1 *419:io_oeb[27] *58:7 6.525 |
| 2 *58:7 *58:8 186.03 |
| 3 *58:8 *58:10 4.5 |
| 4 *58:10 *58:11 424.17 |
| 5 *58:11 io_oeb[27] 13.365 |
| *END |
| |
| *D_NET *59 0.238928 |
| *CONN |
| *P io_oeb[28] O |
| *I *419:io_oeb[28] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[28] 0.00024934 |
| 2 *419:io_oeb[28] 0.000628279 |
| 3 *59:14 0.0177689 |
| 4 *59:13 0.0175196 |
| 5 *59:11 0.0358609 |
| 6 *59:10 0.0358609 |
| 7 *59:8 0.00227215 |
| 8 *59:7 0.00290043 |
| 9 *59:8 *63:8 0.0673267 |
| 10 *59:8 *64:8 0.00940827 |
| 11 *59:8 *72:8 0.000766759 |
| 12 *59:8 *84:8 0.00441372 |
| 13 *10:14 *59:8 0.0439519 |
| *RES |
| 1 *419:io_oeb[28] *59:7 9.945 |
| 2 *59:7 *59:8 107.19 |
| 3 *59:8 *59:10 4.5 |
| 4 *59:10 *59:11 357.21 |
| 5 *59:11 *59:13 4.5 |
| 6 *59:13 *59:14 170.91 |
| 7 *59:14 io_oeb[28] 3.015 |
| *END |
| |
| *D_NET *60 0.11738 |
| *CONN |
| *P io_oeb[29] O |
| *I *419:io_oeb[29] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[29] 0.000194171 |
| 2 *419:io_oeb[29] 0.00121789 |
| 3 *60:11 0.0307925 |
| 4 *60:10 0.0305984 |
| 5 *60:8 0.0266796 |
| 6 *60:7 0.0278975 |
| 7 *32:8 *60:8 0 |
| *RES |
| 1 *419:io_oeb[29] *60:7 16.785 |
| 2 *60:7 *60:8 265.23 |
| 3 *60:8 *60:10 4.5 |
| 4 *60:10 *60:11 296.55 |
| 5 *60:11 io_oeb[29] 2.475 |
| *END |
| |
| *D_NET *61 0.447698 |
| *CONN |
| *P io_oeb[2] O |
| *I *419:io_oeb[2] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[2] 0.00335035 |
| 2 *419:io_oeb[2] 0.000398266 |
| 3 *61:17 0.0160456 |
| 4 *61:16 0.0126952 |
| 5 *61:14 0.0192543 |
| 6 *61:13 0.0192543 |
| 7 *61:11 0.0268892 |
| 8 *61:10 0.0272874 |
| 9 *61:10 *101:14 0.00104339 |
| 10 *61:11 io_oeb[5] 0.270501 |
| 11 *61:11 *79:11 0 |
| 12 *61:11 *110:11 0.0320174 |
| 13 *39:13 *61:11 0.0189618 |
| *RES |
| 1 *419:io_oeb[2] *61:10 19.0174 |
| 2 *61:10 *61:11 499.95 |
| 3 *61:11 *61:13 4.5 |
| 4 *61:13 *61:14 191.97 |
| 5 *61:14 *61:16 4.5 |
| 6 *61:16 *61:17 139.14 |
| 7 *61:17 io_oeb[2] 37.125 |
| *END |
| |
| *D_NET *62 0.0629577 |
| *CONN |
| *P io_oeb[30] O |
| *I *419:io_oeb[30] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[30] 0.00271196 |
| 2 *419:io_oeb[30] 0.0149957 |
| 3 *62:8 0.0164831 |
| 4 *62:7 0.0137712 |
| 5 *62:5 0.0149957 |
| *RES |
| 1 *419:io_oeb[30] *62:5 160.965 |
| 2 *62:5 *62:7 4.5 |
| 3 *62:7 *62:8 137.25 |
| 4 *62:8 io_oeb[30] 34.245 |
| *END |
| |
| *D_NET *63 0.180332 |
| *CONN |
| *P io_oeb[31] O |
| *I *419:io_oeb[31] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[31] 9.91126e-05 |
| 2 *419:io_oeb[31] 0.000604593 |
| 3 *63:14 0.0162738 |
| 4 *63:13 0.0161747 |
| 5 *63:11 0.0155747 |
| 6 *63:10 0.0155747 |
| 7 *63:8 0.00336863 |
| 8 *63:7 0.00397322 |
| 9 *63:8 *72:8 0.00677618 |
| 10 *63:8 *96:10 0.0199556 |
| 11 *63:8 *113:8 0.000704589 |
| 12 *63:11 *91:20 0 |
| 13 *25:15 *63:8 0.0139253 |
| 14 *59:8 *63:8 0.0673267 |
| *RES |
| 1 *419:io_oeb[31] *63:7 9.765 |
| 2 *63:7 *63:8 110.97 |
| 3 *63:8 *63:10 4.5 |
| 4 *63:10 *63:11 154.53 |
| 5 *63:11 *63:13 4.5 |
| 6 *63:13 *63:14 157.41 |
| 7 *63:14 io_oeb[31] 1.395 |
| *END |
| |
| *D_NET *64 0.0818731 |
| *CONN |
| *P io_oeb[32] O |
| *I *419:io_oeb[32] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[32] 0.012796 |
| 2 *419:io_oeb[32] 0.00065368 |
| 3 *64:13 0.012796 |
| 4 *64:11 0.00887509 |
| 5 *64:10 0.00887509 |
| 6 *64:8 0.00287889 |
| 7 *64:7 0.00353257 |
| 8 io_oeb[32] *419:wb_clk_i 0.0122743 |
| 9 *64:8 *104:13 0.000146863 |
| 10 *10:14 *64:8 0.00963632 |
| 11 *59:8 *64:8 0.00940827 |
| *RES |
| 1 *419:io_oeb[32] *64:7 10.305 |
| 2 *64:7 *64:8 54.81 |
| 3 *64:8 *64:10 4.5 |
| 4 *64:10 *64:11 87.75 |
| 5 *64:11 *64:13 4.5 |
| 6 *64:13 io_oeb[32] 173.565 |
| *END |
| |
| *D_NET *65 0.0487402 |
| *CONN |
| *P io_oeb[33] O |
| *I *419:io_oeb[33] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[33] 0.000240014 |
| 2 *419:io_oeb[33] 0.00829931 |
| 3 *65:11 0.00956274 |
| 4 *65:10 0.00932272 |
| 5 *65:8 0.00650804 |
| 6 *65:7 0.00650804 |
| 7 *65:5 0.00829931 |
| 8 *65:8 *103:10 0 |
| *RES |
| 1 *419:io_oeb[33] *65:5 88.065 |
| 2 *65:5 *65:7 4.5 |
| 3 *65:7 *65:8 64.89 |
| 4 *65:8 *65:10 4.5 |
| 5 *65:10 *65:11 100.71 |
| 6 *65:11 io_oeb[33] 3.015 |
| *END |
| |
| *D_NET *66 0.0857191 |
| *CONN |
| *P io_oeb[34] O |
| *I *419:io_oeb[34] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[34] 0.000180294 |
| 2 *419:io_oeb[34] 0.000721204 |
| 3 *66:11 0.0269209 |
| 4 *66:10 0.0267406 |
| 5 *66:8 0.0107754 |
| 6 *66:7 0.0114966 |
| 7 *1:12 *66:8 0.00440371 |
| 8 *29:19 *66:11 0 |
| 9 *57:8 *66:8 0.00448043 |
| *RES |
| 1 *419:io_oeb[34] *66:7 11.565 |
| 2 *66:7 *66:8 129.15 |
| 3 *66:8 *66:10 4.5 |
| 4 *66:10 *66:11 291.33 |
| 5 *66:11 io_oeb[34] 2.475 |
| *END |
| |
| *D_NET *67 0.0687537 |
| *CONN |
| *P io_oeb[35] O |
| *I *419:io_oeb[35] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[35] 0.000132518 |
| 2 *419:io_oeb[35] 0.00931607 |
| 3 *67:11 0.00836309 |
| 4 *67:10 0.00823058 |
| 5 *67:8 0.0166977 |
| 6 *67:7 0.0166977 |
| 7 *67:5 0.00931607 |
| *RES |
| 1 *419:io_oeb[35] *67:5 98.865 |
| 2 *67:5 *67:7 4.5 |
| 3 *67:7 *67:8 166.41 |
| 4 *67:8 *67:10 4.5 |
| 5 *67:10 *67:11 89.91 |
| 6 *67:11 io_oeb[35] 1.935 |
| *END |
| |
| *D_NET *68 0.0923985 |
| *CONN |
| *P io_oeb[36] O |
| *I *419:io_oeb[36] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[36] 8.47422e-05 |
| 2 *419:io_oeb[36] 0.00328378 |
| 3 *68:15 0.0260521 |
| 4 *68:14 0.0259674 |
| 5 *68:12 0.0159442 |
| 6 *68:10 0.019228 |
| 7 *68:12 *107:8 0 |
| 8 *30:12 *68:10 0.00111397 |
| 9 *30:12 *68:12 0 |
| 10 *45:13 *68:10 0.000724234 |
| *RES |
| 1 *419:io_oeb[36] *68:10 43.335 |
| 2 *68:10 *68:12 159.3 |
| 3 *68:12 *68:14 4.5 |
| 4 *68:14 *68:15 284.31 |
| 5 *68:15 io_oeb[36] 1.395 |
| *END |
| |
| *D_NET *69 0.107162 |
| *CONN |
| *P io_oeb[37] O |
| *I *419:io_oeb[37] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[37] 0.00184873 |
| 2 *419:io_oeb[37] 2.02066e-05 |
| 3 *69:10 0.0373642 |
| 4 *69:9 0.0355155 |
| 5 *69:7 0.0154818 |
| 6 *69:5 0.015502 |
| 7 *69:10 *314:13 0 |
| 8 *7:8 *69:7 0.000746036 |
| 9 *15:17 *69:7 0.000683868 |
| *RES |
| 1 *419:io_oeb[37] *69:5 0.225 |
| 2 *69:5 *69:7 169.11 |
| 3 *69:7 *69:9 4.5 |
| 4 *69:9 *69:10 354.33 |
| 5 *69:10 io_oeb[37] 24.165 |
| *END |
| |
| *D_NET *70 0.226698 |
| *CONN |
| *P io_oeb[3] O |
| *I *419:io_oeb[3] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[3] 0.000205039 |
| 2 *419:io_oeb[3] 0.0002122 |
| 3 *70:17 0.0588061 |
| 4 *70:16 0.0586011 |
| 5 *70:14 0.0128661 |
| 6 *70:13 0.0128661 |
| 7 *70:11 0.00655578 |
| 8 *70:10 0.00676798 |
| 9 *70:11 *79:11 0 |
| 10 *11:16 *70:11 0 |
| 11 *32:11 *70:11 0.0555172 |
| 12 *40:12 *70:11 0.0141125 |
| 13 *43:10 *70:10 0.000187963 |
| *RES |
| 1 *419:io_oeb[3] *70:10 16.1374 |
| 2 *70:10 *70:11 112.77 |
| 3 *70:11 *70:13 4.5 |
| 4 *70:13 *70:14 126.99 |
| 5 *70:14 *70:16 4.5 |
| 6 *70:16 *70:17 642.87 |
| 7 *70:17 io_oeb[3] 3.015 |
| *END |
| |
| *D_NET *71 0.285824 |
| *CONN |
| *P io_oeb[4] O |
| *I *419:io_oeb[4] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[4] 0.00074722 |
| 2 *419:io_oeb[4] 0.00070928 |
| 3 *71:16 0.00381517 |
| 4 *71:11 0.0408416 |
| 5 *71:10 0.0377737 |
| 6 *71:8 0.00349383 |
| 7 *71:7 0.00420311 |
| 8 *71:8 *88:8 0.0257164 |
| 9 *71:8 *114:8 0.00366209 |
| 10 *71:11 *82:11 0.0343382 |
| 11 *71:11 *86:8 0.00447623 |
| 12 *71:11 *89:8 0.00181535 |
| 13 *71:16 io_out[4] 0.0114773 |
| 14 *4:14 *71:8 0.00668995 |
| 15 *7:13 *71:8 0.0022709 |
| 16 *42:8 *71:11 0.0302764 |
| 17 *45:14 *71:11 0.0729374 |
| 18 *58:8 *71:11 0.000580251 |
| *RES |
| 1 *419:io_oeb[4] *71:7 10.665 |
| 2 *71:7 *71:8 63.63 |
| 3 *71:8 *71:10 4.5 |
| 4 *71:10 *71:11 765.99 |
| 5 *71:11 *71:16 47.07 |
| 6 *71:16 io_oeb[4] 8.325 |
| *END |
| |
| *D_NET *72 0.517741 |
| *CONN |
| *P io_oeb[5] O |
| *I *419:io_oeb[5] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[5] 0.0359087 |
| 2 *419:io_oeb[5] 0.00057507 |
| 3 *72:13 0.0359087 |
| 4 *72:11 0.010718 |
| 5 *72:10 0.010718 |
| 6 *72:8 0.0049474 |
| 7 *72:7 0.00552247 |
| 8 io_oeb[5] *79:11 0 |
| 9 *72:8 *84:8 0.0448213 |
| 10 *72:8 *113:8 0.0905774 |
| 11 *59:8 *72:8 0.000766759 |
| 12 *61:11 io_oeb[5] 0.270501 |
| 13 *63:8 *72:8 0.00677618 |
| *RES |
| 1 *419:io_oeb[5] *72:7 9.585 |
| 2 *72:7 *72:8 131.13 |
| 3 *72:8 *72:10 4.5 |
| 4 *72:10 *72:11 105.75 |
| 5 *72:11 *72:13 4.5 |
| 6 *72:13 io_oeb[5] 567.225 |
| *END |
| |
| *D_NET *73 0.28369 |
| *CONN |
| *P io_oeb[6] O |
| *I *419:io_oeb[6] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[6] 0.000157263 |
| 2 *419:io_oeb[6] 0.000287934 |
| 3 *73:14 0.0588468 |
| 4 *73:13 0.0586896 |
| 5 *73:11 0.0167059 |
| 6 *73:10 0.0167059 |
| 7 *73:8 0.00160525 |
| 8 *73:7 0.00189319 |
| 9 *73:8 *78:8 0.000746036 |
| 10 *73:8 *86:8 0.0542738 |
| 11 *73:8 *89:8 0.00207621 |
| 12 *73:8 *95:8 0.00441406 |
| 13 *4:11 *73:14 0 |
| 14 *8:16 *73:14 0 |
| 15 *22:19 *73:8 0.0573821 |
| 16 *44:8 *73:8 0.00692156 |
| 17 *54:8 *73:8 0.00298407 |
| *RES |
| 1 *419:io_oeb[6] *73:7 7.065 |
| 2 *73:7 *73:8 118.53 |
| 3 *73:8 *73:10 4.5 |
| 4 *73:10 *73:11 165.33 |
| 5 *73:11 *73:13 4.5 |
| 6 *73:13 *73:14 640.17 |
| 7 *73:14 io_oeb[6] 2.475 |
| *END |
| |
| *D_NET *74 0.361641 |
| *CONN |
| *P io_oeb[7] O |
| *I *419:io_oeb[7] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[7] 0.00339307 |
| 2 *419:io_oeb[7] 0.00116467 |
| 3 *74:11 0.0717858 |
| 4 *74:10 0.0683927 |
| 5 *74:8 0.00555666 |
| 6 *74:7 0.00672133 |
| 7 *74:8 *81:8 0.121585 |
| 8 *8:19 *74:8 0.0830414 |
| *RES |
| 1 *419:io_oeb[7] *74:7 15.885 |
| 2 *74:7 *74:8 188.01 |
| 3 *74:8 *74:10 4.5 |
| 4 *74:10 *74:11 742.86 |
| 5 *74:11 io_oeb[7] 37.125 |
| *END |
| |
| *D_NET *75 0.218658 |
| *CONN |
| *P io_oeb[8] O |
| *I *419:io_oeb[8] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[8] 0.000205039 |
| 2 *419:io_oeb[8] 0.00197332 |
| 3 *75:17 0.0586273 |
| 4 *75:16 0.0584222 |
| 5 *75:14 0.0297271 |
| 6 *75:13 0.0297271 |
| 7 *75:11 0.00197332 |
| 8 *75:11 *84:8 0.0243061 |
| 9 *10:14 *75:11 0.0131164 |
| 10 *47:10 *75:11 0.00058025 |
| *RES |
| 1 *419:io_oeb[8] *75:11 49.185 |
| 2 *75:11 *75:13 4.5 |
| 3 *75:13 *75:14 295.11 |
| 4 *75:14 *75:16 4.5 |
| 5 *75:16 *75:17 637.47 |
| 6 *75:17 io_oeb[8] 3.015 |
| *END |
| |
| *D_NET *76 0.18385 |
| *CONN |
| *P io_oeb[9] O |
| *I *419:io_oeb[9] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[9] 0.000109487 |
| 2 *419:io_oeb[9] 0.0158817 |
| 3 *76:11 0.0460583 |
| 4 *76:10 0.0459488 |
| 5 *76:8 0.029985 |
| 6 *76:7 0.029985 |
| 7 *76:5 0.0158817 |
| 8 *34:9 *76:5 0 |
| *RES |
| 1 *419:io_oeb[9] *76:5 170.145 |
| 2 *76:5 *76:7 4.5 |
| 3 *76:7 *76:8 298.71 |
| 4 *76:8 *76:10 4.5 |
| 5 *76:10 *76:11 502.47 |
| 6 *76:11 io_oeb[9] 1.935 |
| *END |
| |
| *D_NET *77 0.178595 |
| *CONN |
| *P io_out[0] O |
| *I *419:io_out[0] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[0] 0.00333442 |
| 2 *419:io_out[0] 0.0153612 |
| 3 *77:11 0.0462484 |
| 4 *77:10 0.042914 |
| 5 *77:8 0.0276881 |
| 6 *77:7 0.0276881 |
| 7 *77:5 0.0153612 |
| *RES |
| 1 *419:io_out[0] *77:5 164.745 |
| 2 *77:5 *77:7 4.5 |
| 3 *77:7 *77:8 276.03 |
| 4 *77:8 *77:10 4.5 |
| 5 *77:10 *77:11 471.24 |
| 6 *77:11 io_out[0] 36.945 |
| *END |
| |
| *D_NET *78 0.277829 |
| *CONN |
| *P io_out[10] O |
| *I *419:io_out[10] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[10] 0.00337714 |
| 2 *419:io_out[10] 0.000364824 |
| 3 *78:14 0.0578871 |
| 4 *78:13 0.05451 |
| 5 *78:11 0.040264 |
| 6 *78:10 0.040264 |
| 7 *78:8 0.000824194 |
| 8 *78:7 0.00118902 |
| 9 *78:8 *86:8 0.000815977 |
| 10 *78:8 *109:11 0.0434562 |
| 11 *78:11 *89:13 0 |
| 12 *44:8 *78:8 0.0341308 |
| 13 *73:8 *78:8 0.000746036 |
| *RES |
| 1 *419:io_out[10] *78:7 7.605 |
| 2 *78:7 *78:8 62.91 |
| 3 *78:8 *78:10 4.5 |
| 4 *78:10 *78:11 400.77 |
| 5 *78:11 *78:13 4.5 |
| 6 *78:13 *78:14 595.44 |
| 7 *78:14 io_out[10] 36.945 |
| *END |
| |
| *D_NET *79 0.430969 |
| *CONN |
| *P io_out[11] O |
| *I *419:io_out[11] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[11] 0.000761468 |
| 2 *419:io_out[11] 0.000583227 |
| 3 *79:14 0.0238463 |
| 4 *79:13 0.0230848 |
| 5 *79:11 0.0689719 |
| 6 *79:10 0.0695551 |
| 7 *79:10 *87:8 0.0200699 |
| 8 *79:11 *110:11 0 |
| 9 io_oeb[5] *79:11 0 |
| 10 *4:8 *79:14 0.202969 |
| 11 *11:19 *79:10 0.0183513 |
| 12 *32:11 *79:11 0.00277586 |
| 13 *61:11 *79:11 0 |
| 14 *70:11 *79:11 0 |
| *RES |
| 1 *419:io_out[11] *79:10 39.015 |
| 2 *79:10 *79:11 760.41 |
| 3 *79:11 *79:13 4.5 |
| 4 *79:13 *79:14 362.43 |
| 5 *79:14 io_out[11] 12.825 |
| *END |
| |
| *D_NET *80 0.225646 |
| *CONN |
| *P io_out[12] O |
| *I *419:io_out[12] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[12] 0.000106424 |
| 2 *419:io_out[12] 0.0160494 |
| 3 *80:11 0.0457726 |
| 4 *80:10 0.0456662 |
| 5 *80:8 0.051001 |
| 6 *80:7 0.051001 |
| 7 *80:5 0.0160494 |
| *RES |
| 1 *419:io_out[12] *80:5 172.845 |
| 2 *80:5 *80:7 4.5 |
| 3 *80:7 *80:8 508.77 |
| 4 *80:8 *80:10 4.5 |
| 5 *80:10 *80:11 499.77 |
| 6 *80:11 io_out[12] 1.755 |
| *END |
| |
| *D_NET *81 0.358987 |
| *CONN |
| *P io_out[13] O |
| *I *419:io_out[13] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[13] 0.000256796 |
| 2 *419:io_out[13] 0.00113451 |
| 3 *81:11 0.0716628 |
| 4 *81:10 0.071406 |
| 5 *81:8 0.0459035 |
| 6 *81:7 0.047038 |
| 7 *74:8 *81:8 0.121585 |
| *RES |
| 1 *419:io_out[13] *81:7 15.705 |
| 2 *81:7 *81:8 537.39 |
| 3 *81:8 *81:10 4.5 |
| 4 *81:10 *81:11 779.31 |
| 5 *81:11 io_out[13] 3.375 |
| *END |
| |
| *D_NET *82 0.32812 |
| *CONN |
| *P io_out[14] O |
| *I *419:io_out[14] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[14] 0.000141338 |
| 2 *419:io_out[14] 0.000329579 |
| 3 *82:17 0.0566724 |
| 4 *82:16 0.0565311 |
| 5 *82:14 0.0654241 |
| 6 *82:13 0.0654241 |
| 7 *82:11 0.0060934 |
| 8 *82:10 0.00642298 |
| 9 *82:14 *84:13 0 |
| 10 *45:14 *82:11 0.0367424 |
| 11 *71:11 *82:11 0.0343382 |
| *RES |
| 1 *419:io_out[14] *82:10 12.735 |
| 2 *82:10 *82:11 149.13 |
| 3 *82:11 *82:13 4.5 |
| 4 *82:13 *82:14 652.41 |
| 5 *82:14 *82:16 4.5 |
| 6 *82:16 *82:17 618.57 |
| 7 *82:17 io_out[14] 2.295 |
| *END |
| |
| *D_NET *83 0.359407 |
| *CONN |
| *P io_out[15] O |
| *I *419:io_out[15] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[15] 0.000830123 |
| 2 *419:io_out[15] 0.0181414 |
| 3 *83:11 0.0285227 |
| 4 *83:10 0.0276925 |
| 5 *83:8 0.0608543 |
| 6 *83:7 0.0608543 |
| 7 *83:5 0.0181414 |
| 8 *83:8 io_out[19] 1.22751e-05 |
| 9 io_oeb[16] *83:11 0.0221946 |
| 10 *9:8 *83:11 0.0244948 |
| 11 *10:8 *83:11 0.0976688 |
| *RES |
| 1 *419:io_out[15] *83:5 194.445 |
| 2 *83:5 *83:7 4.5 |
| 3 *83:7 *83:8 607.23 |
| 4 *83:8 *83:10 4.5 |
| 5 *83:10 *83:11 425.07 |
| 6 *83:11 io_out[15] 12.825 |
| *END |
| |
| *D_NET *84 0.497717 |
| *CONN |
| *P io_out[16] O |
| *I *419:io_out[16] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[16] 0.000159064 |
| 2 *419:io_out[16] 0.000636547 |
| 3 *84:17 0.0686011 |
| 4 *84:16 0.0684421 |
| 5 *84:14 0.0290058 |
| 6 *84:13 0.0297806 |
| 7 *84:8 0.00287138 |
| 8 *84:7 0.00273309 |
| 9 *10:14 *84:8 0.0014299 |
| 10 *47:14 *84:14 0.220516 |
| 11 *59:8 *84:8 0.00441372 |
| 12 *72:8 *84:8 0.0448213 |
| 13 *75:11 *84:8 0.0243061 |
| 14 *82:14 *84:13 0 |
| *RES |
| 1 *419:io_out[16] *84:7 9.765 |
| 2 *84:7 *84:8 64.89 |
| 3 *84:8 *84:13 16.29 |
| 4 *84:13 *84:14 459.63 |
| 5 *84:14 *84:16 4.5 |
| 6 *84:16 *84:17 683.37 |
| 7 *84:17 io_out[16] 2.295 |
| *END |
| |
| *D_NET *85 0.197055 |
| *CONN |
| *P io_out[17] O |
| *I *419:io_out[17] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[17] 0.00370319 |
| 2 *419:io_out[17] 0.037473 |
| 3 *85:8 0.0610547 |
| 4 *85:7 0.0573515 |
| 5 *85:5 0.037473 |
| *RES |
| 1 *419:io_out[17] *85:5 406.485 |
| 2 *85:5 *85:7 4.5 |
| 3 *85:7 *85:8 572.4 |
| 4 *85:8 io_out[17] 36.945 |
| *END |
| |
| *D_NET *86 0.353491 |
| *CONN |
| *P io_out[18] O |
| *I *419:io_out[18] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[18] 0.000794415 |
| 2 *419:io_out[18] 0.000264248 |
| 3 *86:14 0.00702054 |
| 4 *86:13 0.00622612 |
| 5 *86:11 0.0681591 |
| 6 *86:10 0.0681591 |
| 7 *86:8 0.0072441 |
| 8 *86:7 0.00750834 |
| 9 *86:8 *89:8 0.00701274 |
| 10 *86:8 *90:10 0.0258 |
| 11 *86:8 *109:11 0.010701 |
| 12 *10:8 *86:14 0.0843644 |
| 13 *42:8 *86:8 0.000670915 |
| 14 *71:11 *86:8 0.00447623 |
| 15 *73:8 *86:8 0.0542738 |
| 16 *78:8 *86:8 0.000815977 |
| *RES |
| 1 *419:io_out[18] *86:7 6.885 |
| 2 *86:7 *86:8 224.37 |
| 3 *86:8 *86:10 4.5 |
| 4 *86:10 *86:11 679.77 |
| 5 *86:11 *86:13 4.5 |
| 6 *86:13 *86:14 122.13 |
| 7 *86:14 io_out[18] 12.465 |
| *END |
| |
| *D_NET *87 0.33559 |
| *CONN |
| *P io_out[19] O |
| *I *419:io_out[19] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[19] 0.000838347 |
| 2 *419:io_out[19] 4.65051e-05 |
| 3 *87:11 0.0187934 |
| 4 *87:10 0.017955 |
| 5 *87:8 0.0624881 |
| 6 *87:7 0.0625346 |
| 7 *87:8 *91:16 0.00165714 |
| 8 *87:11 io_out[21] 0.015729 |
| 9 io_oeb[19] *87:11 0.000146876 |
| 10 *10:8 *87:11 0.12092 |
| 11 *11:19 *87:8 0.0115386 |
| 12 *14:10 *87:11 0.0028598 |
| 13 *79:10 *87:8 0.0200699 |
| 14 *83:8 io_out[19] 1.22751e-05 |
| *RES |
| 1 *419:io_out[19] *87:7 4.905 |
| 2 *87:7 *87:8 657.99 |
| 3 *87:8 *87:10 4.5 |
| 4 *87:10 *87:11 289.89 |
| 5 *87:11 io_out[19] 12.825 |
| *END |
| |
| *D_NET *88 0.214648 |
| *CONN |
| *P io_out[1] O |
| *I *419:io_out[1] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[1] 0.000189114 |
| 2 *419:io_out[1] 0.00063782 |
| 3 *88:11 0.070771 |
| 4 *88:10 0.0705819 |
| 5 *88:8 0.0193437 |
| 6 *88:7 0.0199815 |
| 7 *88:8 *114:8 0.00742646 |
| 8 *71:8 *88:8 0.0257164 |
| *RES |
| 1 *419:io_out[1] *88:7 10.485 |
| 2 *88:7 *88:8 213.93 |
| 3 *88:8 *88:10 4.5 |
| 4 *88:10 *88:11 774.09 |
| 5 *88:11 io_out[1] 2.835 |
| *END |
| |
| *D_NET *89 0.293095 |
| *CONN |
| *P io_out[20] O |
| *I *419:io_out[20] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[20] 0.000288506 |
| 2 *419:io_out[20] 0.00012051 |
| 3 *89:17 0.0687632 |
| 4 *89:16 0.0706932 |
| 5 *89:13 0.00267379 |
| 6 *89:8 0.00262088 |
| 7 *89:7 0.00228611 |
| 8 *89:7 *109:10 0.00025164 |
| 9 *89:8 *90:10 0.00859999 |
| 10 *42:8 *89:8 0.0862288 |
| 11 *47:14 *89:16 0.0299037 |
| 12 *54:8 *89:8 0.00522218 |
| 13 *58:8 *89:8 0.00453839 |
| 14 *71:11 *89:8 0.00181535 |
| 15 *73:8 *89:8 0.00207621 |
| 16 *78:11 *89:13 0 |
| 17 *86:8 *89:8 0.00701274 |
| *RES |
| 1 *419:io_out[20] *89:7 6.345 |
| 2 *89:7 *89:8 137.97 |
| 3 *89:8 *89:13 13.23 |
| 4 *89:13 *89:16 47.79 |
| 5 *89:16 *89:17 683.01 |
| 6 *89:17 io_out[20] 3.375 |
| *END |
| |
| *D_NET *90 0.249407 |
| *CONN |
| *P io_out[21] O |
| *I *419:io_out[21] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[21] 0.00156418 |
| 2 *419:io_out[21] 0.000767667 |
| 3 *90:11 0.0660425 |
| 4 *90:10 0.065246 |
| 5 *90:11 *101:8 0.0571408 |
| 6 *14:10 io_out[21] 0.00851726 |
| 7 *86:8 *90:10 0.0258 |
| 8 *87:11 io_out[21] 0.015729 |
| 9 *89:8 *90:10 0.00859999 |
| *RES |
| 1 *419:io_out[21] *90:10 48.555 |
| 2 *90:10 *90:11 679.41 |
| 3 *90:11 io_out[21] 39.915 |
| *END |
| |
| *D_NET *91 0.145163 |
| *CONN |
| *P io_out[22] O |
| *I *419:io_out[22] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[22] 0.00369575 |
| 2 *419:io_out[22] 0.00104756 |
| 3 *91:20 0.0581124 |
| 4 *91:19 0.056034 |
| 5 *91:16 0.00266493 |
| 6 *91:16 *98:11 0.000882809 |
| 7 *91:19 *92:11 0.0205782 |
| 8 *3:16 *91:16 0 |
| 9 *15:9 *91:16 0.000490239 |
| 10 *63:11 *91:20 0 |
| 11 *87:8 *91:16 0.00165714 |
| *RES |
| 1 *419:io_out[22] *91:16 38.4574 |
| 2 *91:16 *91:19 34.29 |
| 3 *91:19 *91:20 543.96 |
| 4 *91:20 io_out[22] 36.945 |
| *END |
| |
| *D_NET *92 0.169239 |
| *CONN |
| *P io_out[23] O |
| *I *419:io_out[23] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[23] 0.000212626 |
| 2 *419:io_out[23] 0.000962731 |
| 3 *92:14 0.0583463 |
| 4 *92:13 0.0581336 |
| 5 *92:11 0.0150215 |
| 6 *92:10 0.0159843 |
| 7 *92:11 *112:13 0 |
| 8 *91:19 *92:11 0.0205782 |
| *RES |
| 1 *419:io_out[23] *92:10 22.7974 |
| 2 *92:10 *92:11 174.33 |
| 3 *92:11 *92:13 4.5 |
| 4 *92:13 *92:14 580.77 |
| 5 *92:14 io_out[23] 2.835 |
| *END |
| |
| *D_NET *93 0.160394 |
| *CONN |
| *P io_out[24] O |
| *I *419:io_out[24] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[24] 0.00123228 |
| 2 *419:io_out[24] 0.00098346 |
| 3 *93:17 0.0229427 |
| 4 *93:16 0.0217104 |
| 5 *93:14 0.0546515 |
| 6 *93:13 0.055635 |
| 7 *419:io_in[9] *93:13 0.00254896 |
| 8 *419:io_in[9] *93:14 0 |
| 9 *6:16 *93:13 0.000689199 |
| 10 *49:11 *93:13 0 |
| *RES |
| 1 *419:io_out[24] *93:13 31.8874 |
| 2 *93:13 *93:14 545.85 |
| 3 *93:14 *93:16 4.5 |
| 4 *93:16 *93:17 236.34 |
| 5 *93:17 io_out[24] 13.185 |
| *END |
| |
| *D_NET *94 0.150116 |
| *CONN |
| *P io_out[25] O |
| *I *419:io_out[25] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[25] 0.000240014 |
| 2 *419:io_out[25] 0.00772185 |
| 3 *94:11 0.00998356 |
| 4 *94:10 0.00974354 |
| 5 *94:8 0.0573523 |
| 6 *94:7 0.0573523 |
| 7 *94:5 0.00772185 |
| *RES |
| 1 *419:io_out[25] *94:5 82.665 |
| 2 *94:5 *94:7 4.5 |
| 3 *94:7 *94:8 572.49 |
| 4 *94:8 *94:10 4.5 |
| 5 *94:10 *94:11 106.11 |
| 6 *94:11 io_out[25] 3.015 |
| *END |
| |
| *D_NET *95 0.196224 |
| *CONN |
| *P io_out[26] O |
| *I *419:io_out[26] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[26] 0.0013425 |
| 2 *419:io_out[26] 0.00027008 |
| 3 *95:11 0.0529288 |
| 4 *95:10 0.0515863 |
| 5 *95:8 0.00790547 |
| 6 *95:7 0.00817555 |
| 7 *95:11 io_out[32] 0 |
| 8 *95:11 *313:13 0 |
| 9 *22:19 *95:8 0.00754325 |
| 10 *53:14 *95:8 0.00144234 |
| 11 *54:8 *95:8 0.0251788 |
| 12 *58:8 *95:8 0.0354367 |
| 13 *73:8 *95:8 0.00441406 |
| *RES |
| 1 *419:io_out[26] *95:7 6.885 |
| 2 *95:7 *95:8 190.35 |
| 3 *95:8 *95:10 4.5 |
| 4 *95:10 *95:11 515.25 |
| 5 *95:11 io_out[26] 18.765 |
| *END |
| |
| *D_NET *96 0.162435 |
| *CONN |
| *P io_out[27] O |
| *I *419:io_out[27] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[27] 0.000132518 |
| 2 *419:io_out[27] 0.0011762 |
| 3 *96:14 0.0150964 |
| 4 *96:13 0.0149639 |
| 5 *96:11 0.0449895 |
| 6 *96:10 0.0461657 |
| 7 *25:15 *96:10 0.0199554 |
| 8 *63:8 *96:10 0.0199556 |
| *RES |
| 1 *419:io_out[27] *96:10 42.975 |
| 2 *96:10 *96:11 448.65 |
| 3 *96:11 *96:13 4.5 |
| 4 *96:13 *96:14 162.81 |
| 5 *96:14 io_out[27] 1.935 |
| *END |
| |
| *D_NET *97 0.248749 |
| *CONN |
| *P io_out[28] O |
| *I *419:io_out[28] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[28] 8.47422e-05 |
| 2 *419:io_out[28] 0.00147656 |
| 3 *97:19 0.00832397 |
| 4 *97:18 0.00823923 |
| 5 *97:16 0.0268912 |
| 6 *97:15 0.0268912 |
| 7 *97:13 0.00692436 |
| 8 *97:12 0.00840092 |
| 9 *97:13 *100:13 0.122288 |
| 10 *39:10 *97:12 0 |
| 11 *51:13 *97:13 0.0392291 |
| *RES |
| 1 *419:io_out[28] *97:12 27.5204 |
| 2 *97:12 *97:13 177.03 |
| 3 *97:13 *97:15 4.5 |
| 4 *97:15 *97:16 268.65 |
| 5 *97:16 *97:18 4.5 |
| 6 *97:18 *97:19 89.91 |
| 7 *97:19 io_out[28] 1.395 |
| *END |
| |
| *D_NET *98 0.0979398 |
| *CONN |
| *P io_out[29] O |
| *I *419:io_out[29] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[29] 0.00124651 |
| 2 *419:io_out[29] 0.000689092 |
| 3 *98:17 0.00879605 |
| 4 *98:16 0.00754953 |
| 5 *98:14 0.0207024 |
| 6 *98:13 0.0207024 |
| 7 *98:11 0.0134281 |
| 8 *98:10 0.0141172 |
| 9 *98:11 *112:13 0 |
| 10 *419:io_in[30] *98:11 0 |
| 11 *52:13 *98:11 0.000313958 |
| 12 *56:13 *98:11 0.00951176 |
| 13 *91:16 *98:11 0.000882809 |
| *RES |
| 1 *419:io_out[29] *98:10 20.0974 |
| 2 *98:10 *98:11 152.55 |
| 3 *98:11 *98:13 4.5 |
| 4 *98:13 *98:14 206.73 |
| 5 *98:14 *98:16 4.5 |
| 6 *98:16 *98:17 82.44 |
| 7 *98:17 io_out[29] 13.185 |
| *END |
| |
| *D_NET *99 0.154706 |
| *CONN |
| *P io_out[2] O |
| *I *419:io_out[2] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[2] 9.35618e-05 |
| 2 *419:io_out[2] 0.00113921 |
| 3 *99:14 0.0656157 |
| 4 *99:13 0.0655222 |
| 5 *99:11 0.0105979 |
| 6 *99:10 0.0117371 |
| 7 *10:14 *99:10 0 |
| *RES |
| 1 *419:io_out[2] *99:10 19.395 |
| 2 *99:10 *99:11 105.93 |
| 3 *99:11 *99:13 4.5 |
| 4 *99:13 *99:14 718.47 |
| 5 *99:14 io_out[2] 1.755 |
| *END |
| |
| *D_NET *100 0.190454 |
| *CONN |
| *P io_out[30] O |
| *I *419:io_out[30] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[30] 0.00160985 |
| 2 *419:io_out[30] 0.00130097 |
| 3 *100:16 0.0149841 |
| 4 *100:15 0.0133743 |
| 5 *100:13 0.0165546 |
| 6 *100:12 0.0178556 |
| 7 *419:io_in[8] *100:13 0 |
| 8 *14:11 *100:12 0 |
| 9 *51:13 *100:13 0.00248679 |
| 10 *97:13 *100:13 0.122288 |
| *RES |
| 1 *419:io_out[30] *100:12 26.0257 |
| 2 *100:12 *100:13 260.73 |
| 3 *100:13 *100:15 4.5 |
| 4 *100:15 *100:16 133.47 |
| 5 *100:16 io_out[30] 21.465 |
| *END |
| |
| *D_NET *101 0.18633 |
| *CONN |
| *P io_out[31] O |
| *I *419:io_out[31] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[31] 0.000180294 |
| 2 *419:io_out[31] 0.000439606 |
| 3 *101:17 0.0263741 |
| 4 *101:16 0.0261938 |
| 5 *101:14 0.00735787 |
| 6 *101:13 0.00755425 |
| 7 *101:8 0.00183244 |
| 8 *101:7 0.00207567 |
| 9 *7:8 *101:13 0.00491141 |
| 10 *55:8 *101:8 0.0481799 |
| 11 *55:13 *101:13 0.00304632 |
| 12 *61:10 *101:14 0.00104339 |
| 13 *90:11 *101:8 0.0571408 |
| *RES |
| 1 *419:io_out[31] *101:7 8.865 |
| 2 *101:7 *101:8 83.79 |
| 3 *101:8 *101:13 16.11 |
| 4 *101:13 *101:14 74.61 |
| 5 *101:14 *101:16 4.5 |
| 6 *101:16 *101:17 281.61 |
| 7 *101:17 io_out[31] 2.475 |
| *END |
| |
| *D_NET *102 0.0376311 |
| *CONN |
| *P io_out[32] O |
| *I *419:io_out[32] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[32] 0.00272601 |
| 2 *419:io_out[32] 0.0160895 |
| 3 *102:5 0.0188155 |
| 4 *95:11 io_out[32] 0 |
| *RES |
| 1 *419:io_out[32] *102:5 172.845 |
| 2 *102:5 io_out[32] 37.035 |
| *END |
| |
| *D_NET *103 0.0377249 |
| *CONN |
| *P io_out[33] O |
| *I *419:io_out[33] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[33] 8.47422e-05 |
| 2 *419:io_out[33] 0.0090311 |
| 3 *103:11 0.00953937 |
| 4 *103:10 0.0097466 |
| 5 *103:5 0.00932307 |
| 6 *65:8 *103:10 0 |
| *RES |
| 1 *419:io_out[33] *103:5 86.625 |
| 2 *103:5 *103:10 11.79 |
| 3 *103:10 *103:11 102.15 |
| 4 *103:11 io_out[33] 1.395 |
| *END |
| |
| *D_NET *104 0.0449212 |
| *CONN |
| *P io_out[34] O |
| *I *419:io_out[34] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[34] 0.00123228 |
| 2 *419:io_out[34] 0.00347278 |
| 3 *104:14 0.0189144 |
| 4 *104:13 0.0211549 |
| 5 *104:14 *105:10 0 |
| 6 *64:8 *104:13 0.000146863 |
| *RES |
| 1 *419:io_out[34] *104:13 47.205 |
| 2 *104:13 *104:14 193.14 |
| 3 *104:14 io_out[34] 13.185 |
| *END |
| |
| *D_NET *105 0.0618943 |
| *CONN |
| *P io_out[35] O |
| *I *419:io_out[35] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[35] 0.0028236 |
| 2 *419:io_out[35] 0.00322054 |
| 3 *105:13 0.00999521 |
| 4 *105:12 0.00717161 |
| 5 *105:10 0.0177314 |
| 6 *105:9 0.0209519 |
| 7 *104:14 *105:10 0 |
| *RES |
| 1 *419:io_out[35] *105:9 35.955 |
| 2 *105:9 *105:10 193.23 |
| 3 *105:10 *105:12 4.5 |
| 4 *105:12 *105:13 71.55 |
| 5 *105:13 io_out[35] 35.325 |
| *END |
| |
| *D_NET *106 0.0773312 |
| *CONN |
| *P io_out[36] O |
| *I *419:io_out[36] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[36] 0.00020073 |
| 2 *419:io_out[36] 0.00801767 |
| 3 *106:11 0.0107789 |
| 4 *106:10 0.0105782 |
| 5 *106:8 0.019869 |
| 6 *106:7 0.019869 |
| 7 *106:5 0.00801767 |
| *RES |
| 1 *419:io_out[36] *106:5 85.365 |
| 2 *106:5 *106:7 4.5 |
| 3 *106:7 *106:8 198.27 |
| 4 *106:8 *106:10 4.5 |
| 5 *106:10 *106:11 103.41 |
| 6 *106:11 io_out[36] 2.475 |
| *END |
| |
| *D_NET *107 0.258115 |
| *CONN |
| *P io_out[37] O |
| *I *419:io_out[37] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[37] 0.000148695 |
| 2 *419:io_out[37] 0.000172243 |
| 3 *107:11 0.029222 |
| 4 *107:10 0.0290734 |
| 5 *107:8 0.0193222 |
| 6 *107:7 0.0194944 |
| 7 *107:8 *314:19 0.0375006 |
| 8 *17:16 *107:8 0.011109 |
| 9 *26:16 *107:8 0.00668995 |
| 10 *30:12 *107:8 0.105382 |
| 11 *68:12 *107:8 0 |
| *RES |
| 1 *419:io_out[37] *107:7 6.165 |
| 2 *107:7 *107:8 296.01 |
| 3 *107:8 *107:10 4.5 |
| 4 *107:10 *107:11 285.93 |
| 5 *107:11 io_out[37] 1.935 |
| *END |
| |
| *D_NET *108 0.141497 |
| *CONN |
| *P io_out[3] O |
| *I *419:io_out[3] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[3] 0.000256796 |
| 2 *419:io_out[3] 0.00126567 |
| 3 *108:14 0.0650864 |
| 4 *108:13 0.0691936 |
| 5 *108:10 0.00562965 |
| 6 *108:10 *314:16 0 |
| 7 *10:14 *108:10 0 |
| 8 *45:10 *108:10 6.52783e-05 |
| *RES |
| 1 *419:io_out[3] *108:10 21.195 |
| 2 *108:10 *108:13 48.15 |
| 3 *108:13 *108:14 710.37 |
| 4 *108:14 io_out[3] 3.375 |
| *END |
| |
| *D_NET *109 0.268784 |
| *CONN |
| *P io_out[4] O |
| *I *419:io_out[4] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[4] 0.00186907 |
| 2 *419:io_out[4] 0.00108306 |
| 3 *109:11 0.0610177 |
| 4 *109:10 0.0602317 |
| 5 *109:11 *113:8 0 |
| 6 *11:19 *109:10 0.00668995 |
| 7 *22:19 *109:11 0.00604285 |
| 8 *44:8 *109:11 0.00700445 |
| 9 *50:8 *109:10 0.0174921 |
| 10 *53:14 *109:11 0.041467 |
| 11 *71:16 io_out[4] 0.0114773 |
| 12 *78:8 *109:11 0.0434562 |
| 13 *86:8 *109:11 0.010701 |
| 14 *89:7 *109:10 0.00025164 |
| *RES |
| 1 *419:io_out[4] *109:10 35.595 |
| 2 *109:10 *109:11 760.95 |
| 3 *109:11 io_out[4] 35.955 |
| *END |
| |
| *D_NET *110 0.172128 |
| *CONN |
| *P io_out[5] O |
| *I *419:io_out[5] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[5] 0.00333442 |
| 2 *419:io_out[5] 0.000564113 |
| 3 *110:17 0.0530964 |
| 4 *110:16 0.0519769 |
| 5 *110:11 0.005944 |
| 6 *110:10 0.00429319 |
| 7 *39:13 *110:11 0.00373007 |
| 8 *41:5 *110:17 0.0171713 |
| 9 *61:11 *110:11 0.0320174 |
| 10 *79:11 *110:11 0 |
| *RES |
| 1 *419:io_out[5] *110:10 18.8374 |
| 2 *110:10 *110:11 65.79 |
| 3 *110:11 *110:16 30.69 |
| 4 *110:16 *110:17 592.74 |
| 5 *110:17 io_out[5] 36.945 |
| *END |
| |
| *D_NET *111 0.205565 |
| *CONN |
| *P io_out[6] O |
| *I *419:io_out[6] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[6] 0.000189114 |
| 2 *419:io_out[6] 0.00158428 |
| 3 *111:19 0.0596096 |
| 4 *111:18 0.0625363 |
| 5 *111:13 0.0112808 |
| 6 *111:12 0.00974921 |
| 7 *9:14 *111:13 0.0606156 |
| *RES |
| 1 *419:io_out[6] *111:12 28.9057 |
| 2 *111:12 *111:13 117.45 |
| 3 *111:13 *111:18 40.05 |
| 4 *111:18 *111:19 648.27 |
| 5 *111:19 io_out[6] 2.835 |
| *END |
| |
| *D_NET *112 0.160456 |
| *CONN |
| *P io_out[7] O |
| *I *419:io_out[7] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[7] 0.000102052 |
| 2 *419:io_out[7] 0.00168039 |
| 3 *112:17 0.0681027 |
| 4 *112:16 0.0680006 |
| 5 *112:14 0.0103317 |
| 6 *112:13 0.0120121 |
| 7 *56:13 *112:13 0.000226914 |
| 8 *92:11 *112:13 0 |
| 9 *98:11 *112:13 0 |
| *RES |
| 1 *419:io_out[7] *112:13 34.9474 |
| 2 *112:13 *112:14 102.87 |
| 3 *112:14 *112:16 4.5 |
| 4 *112:16 *112:17 740.07 |
| 5 *112:17 io_out[7] 1.755 |
| *END |
| |
| *D_NET *113 0.271785 |
| *CONN |
| *P io_out[8] O |
| *I *419:io_out[8] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[8] 0.000256796 |
| 2 *419:io_out[8] 0.000551384 |
| 3 *113:14 0.0362864 |
| 4 *113:13 0.0360296 |
| 5 *113:11 0.0274143 |
| 6 *113:10 0.0274143 |
| 7 *113:8 0.0259994 |
| 8 *113:7 0.0265508 |
| 9 *63:8 *113:8 0.000704589 |
| 10 *72:8 *113:8 0.0905774 |
| 11 *109:11 *113:8 0 |
| *RES |
| 1 *419:io_out[8] *113:7 9.405 |
| 2 *113:7 *113:8 306.99 |
| 3 *113:8 *113:10 4.5 |
| 4 *113:10 *113:11 272.97 |
| 5 *113:11 *113:13 4.5 |
| 6 *113:13 *113:14 394.47 |
| 7 *113:14 io_out[8] 3.375 |
| *END |
| |
| *D_NET *114 0.280375 |
| *CONN |
| *P io_out[9] O |
| *I *419:io_out[9] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[9] 0.000141338 |
| 2 *419:io_out[9] 0.000607647 |
| 3 *114:11 0.0712414 |
| 4 *114:10 0.0711001 |
| 5 *114:8 0.0247721 |
| 6 *114:7 0.0253797 |
| 7 *4:14 *114:8 0.0760445 |
| 8 *71:8 *114:8 0.00366209 |
| 9 *88:8 *114:8 0.00742646 |
| *RES |
| 1 *419:io_out[9] *114:7 10.305 |
| 2 *114:7 *114:8 307.35 |
| 3 *114:8 *114:10 4.5 |
| 4 *114:10 *114:11 773.91 |
| 5 *114:11 io_out[9] 2.295 |
| *END |
| |
| *D_NET *313 0.10747 |
| *CONN |
| *P wb_clk_i I |
| *I *419:wb_clk_i I *D wrapped_vga_clock |
| *CAP |
| 1 wb_clk_i 0.000210953 |
| 2 *419:wb_clk_i 0.0118789 |
| 3 *313:15 0.0118789 |
| 4 *313:13 0.0354951 |
| 5 *313:11 0.035706 |
| 6 *313:11 *314:13 2.5829e-05 |
| 7 io_oeb[32] *419:wb_clk_i 0.0122743 |
| 8 *95:11 *313:13 0 |
| *RES |
| 1 wb_clk_i *313:11 2.655 |
| 2 *313:11 *313:13 354.33 |
| 3 *313:13 *313:15 4.5 |
| 4 *313:15 *419:wb_clk_i 173.025 |
| *END |
| |
| *D_NET *314 0.146704 |
| *CONN |
| *P wb_rst_i I |
| *I *419:wb_rst_i I *D wrapped_vga_clock |
| *CAP |
| 1 wb_rst_i 0.00026944 |
| 2 *419:wb_rst_i 0.000202416 |
| 3 *314:19 0.00341151 |
| 4 *314:18 0.00320909 |
| 5 *314:16 0.0246095 |
| 6 *314:15 0.0246095 |
| 7 *314:13 0.0262984 |
| 8 *314:11 0.0265678 |
| 9 *28:13 *314:16 0 |
| 10 *69:10 *314:13 0 |
| 11 *107:8 *314:19 0.0375006 |
| 12 *108:10 *314:16 0 |
| 13 *313:11 *314:13 2.5829e-05 |
| *RES |
| 1 wb_rst_i *314:11 3.015 |
| 2 *314:11 *314:13 262.71 |
| 3 *314:13 *314:15 4.5 |
| 4 *314:15 *314:16 267.75 |
| 5 *314:16 *314:18 4.5 |
| 6 *314:18 *314:19 54.99 |
| 7 *314:19 *419:wb_rst_i 6.345 |
| *END |
