cgf: Enable PL_RESIZER_DESIGN
diff --git a/openlane/serv_0/config.tcl b/openlane/serv_0/config.tcl index 8978994..f9d6def 100644 --- a/openlane/serv_0/config.tcl +++ b/openlane/serv_0/config.tcl
@@ -27,7 +27,9 @@ set ::env(CLOCK_PORT) "" set ::env(CLOCK_NET) {clk serv_clk} set ::env(CLOCK_PERIOD) 50 -set ::env(SYNTH_MAX_FANOUT) 16 +set ::env(SYNTH_MAX_FANOUT) 5 +set ::env(SYNTH_SIZING) 1 +set ::env(CLOCK_BUFFER_FANOUT) 20 set ::env(FP_IO_HLENGTH) 2 set ::env(FP_IO_VLENGTH) 2 @@ -41,7 +43,7 @@ set ::env(PL_TARGET_DENSITY) 0.55 # Enable all optimizations -set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0 +set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 1 set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 1 set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) 1
diff --git a/openlane/serv_1/config.tcl b/openlane/serv_1/config.tcl index 5fa3f87..6164f84 100644 --- a/openlane/serv_1/config.tcl +++ b/openlane/serv_1/config.tcl
@@ -27,7 +27,9 @@ set ::env(CLOCK_PORT) "" set ::env(CLOCK_NET) {clk serv_clk} set ::env(CLOCK_PERIOD) 50 -set ::env(SYNTH_MAX_FANOUT) 16 +set ::env(SYNTH_MAX_FANOUT) 5 +set ::env(SYNTH_SIZING) 1 +set ::env(CLOCK_BUFFER_FANOUT) 20 set ::env(FP_IO_HLENGTH) 2 set ::env(FP_IO_VLENGTH) 2 @@ -41,7 +43,7 @@ set ::env(PL_TARGET_DENSITY) 0.55 # Enable all optimizations -set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0 +set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 1 set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 1 set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) 1
diff --git a/openlane/serv_2/config.tcl b/openlane/serv_2/config.tcl index 20618d0..8d09dc9 100644 --- a/openlane/serv_2/config.tcl +++ b/openlane/serv_2/config.tcl
@@ -27,7 +27,9 @@ set ::env(CLOCK_PORT) "" set ::env(CLOCK_NET) {clk serv_clk} set ::env(CLOCK_PERIOD) 50 -set ::env(SYNTH_MAX_FANOUT) 16 +set ::env(SYNTH_MAX_FANOUT) 5 +set ::env(SYNTH_SIZING) 1 +set ::env(CLOCK_BUFFER_FANOUT) 20 set ::env(FP_IO_HLENGTH) 2 set ::env(FP_IO_VLENGTH) 2 @@ -41,7 +43,7 @@ set ::env(PL_TARGET_DENSITY) 0.55 # Enable all optimizations -set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0 +set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 1 set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 1 set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) 1