rtl: Add second serv variant
diff --git a/.github/workflows/user_project_ci.yml b/.github/workflows/user_project_ci.yml index 8df3076..1a70f6f 100644 --- a/.github/workflows/user_project_ci.yml +++ b/.github/workflows/user_project_ci.yml
@@ -62,37 +62,15 @@ with: python-version: '3.10' - - name: harden tiny_user_project + - name: harden serv_0 run: | - make tiny_user_project - find openlane/tiny_user_project/runs/tiny_user_project/ + make serv_0 + find openlane/serv_0/runs/serv_0/ - - name: show tiny_user_project metrics + - name: harden serv_1 run: | - python << EOF >> $GITHUB_STEP_SUMMARY - import csv - import pathlib - - print('# tiny_user_project') - print('## metrics') - metrics = pathlib.Path('openlane/tiny_user_project/runs/tiny_user_project/reports/metrics.csv') - with metrics.open() as f: - d = list(csv.DictReader(f))[0] - print('key|value') - print('---|-----') - for k,v in d.items(): - print(f'{k}|{v}') - EOF - - - name: show tiny_user_project reports - run: | - cat << EOF >> $GITHUB_STEP_SUMMARY - ## manufacturability - - \`\`\` - `cat openlane/tiny_user_project/runs/tiny_user_project/reports/manufacturability.rpt` - \`\`\` - EOF + make serv_1 + find openlane/serv_1/runs/serv_1/ - name: harden user_project_wrapper run: | @@ -214,8 +192,8 @@ - name: create layout png run: | - QT_QPA_PLATFORM=minimal klayout gds/tiny_user_project.gds -z -r scripts/klayout_save_image.py - cp layout.png layout-serv.png + QT_QPA_PLATFORM=minimal klayout gds/serv_0.gds -z -r scripts/klayout_save_image.py + cp layout.png layout-serv0.png QT_QPA_PLATFORM=minimal klayout gds/user_project_wrapper.gds -z -r scripts/klayout_save_image.py - name: populate img cache uses: actions/cache@v3
diff --git a/openlane/tiny_user_project/config.tcl b/openlane/serv_0/config.tcl similarity index 89% rename from openlane/tiny_user_project/config.tcl rename to openlane/serv_0/config.tcl index 926e4cd..7db1c69 100644 --- a/openlane/tiny_user_project/config.tcl +++ b/openlane/serv_0/config.tcl
@@ -15,7 +15,7 @@ set script_dir [file dirname [file normalize [info script]/../../]] -set ::env(DESIGN_NAME) tiny_user_project +set ::env(DESIGN_NAME) serv_0 set ::env(DESIGN_IS_CORE) 0 set ::env(PDK) "gf180mcuC" @@ -24,7 +24,7 @@ #set ::env(RUN_KLAYOUT) 0 set ::env(CLOCK_TREE_SYNTH) 1 -set ::env(CLOCK_PORT) {io_in[8]} +set ::env(CLOCK_PORT) {io_in[8] io_in[12]} #set ::env(CLOCK_NET) "" set ::env(CLOCK_PERIOD) 50 set ::env(SYNTH_MAX_FANOUT) 16 @@ -54,9 +54,9 @@ ## Internal Macros ### Macro PDN Connections set ::env(FP_PDN_MACRO_HOOKS) "\ - mod.u_cpu.rf_ram.RAM0 vdd vss vdd vss" + u_cpu.rf_ram.RAM0 vdd vss vdd vss" set ::env(FP_PDN_MACROS) "\ - mod.u_cpu.rf_ram.RAM0" + u_cpu.rf_ram.RAM0" set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg @@ -65,14 +65,11 @@ set ::env(DESIGN_DIR) $script_dir/../../verilog - #$::env(DESIGN_DIR)/blocks/serv/rtl/serv_rf_ram.v \ - set ::env(VERILOG_FILES) "\ $::env(DESIGN_DIR)/rtl/defines.v \ - $::env(DESIGN_DIR)/rtl/top.v \ + $::env(DESIGN_DIR)/rtl/serv_0.v \ $::env(DESIGN_DIR)/rtl/serv_rf_ram_gf180.v \ $::env(DESIGN_DIR)/rtl/scanchain_gf180.v \ - $::env(DESIGN_DIR)/rtl/tiny_user_project.v \ $::env(DESIGN_DIR)/blocks/serv/rtl/serv_top.v \ $::env(DESIGN_DIR)/blocks/serv/rtl/serv_synth_wrapper.v \ $::env(DESIGN_DIR)/blocks/serv/rtl/serv_mem_if.v \ @@ -90,11 +87,10 @@ $::env(DESIGN_DIR)/blocks/serv/rtl/serv_state.v \ $::env(DESIGN_DIR)/blocks/serv/rtl/serv_csr.v \ $::env(DESIGN_DIR)/blocks/serv/servant/servant_arbiter.v \ - $::env(DESIGN_DIR)/blocks/serv/servant/servant_mux.v \ - $::env(DESIGN_DIR)/blocks/serv/servant/servant_gpio.v" + $::env(DESIGN_DIR)/blocks/serv/servant/servant_mux.v" set ::env(VERILOG_FILES_BLACKBOX) "\ - $::env(DESIGN_DIR)/rtl/gf180mcu_fd_sc_mcu7t5v0_bb.v \ + $::env(DESIGN_DIR)/rtl/bb/gf180mcu_fd_sc_mcu7t5v0.v \ $::env(PDK_ROOT)/$::env(PDK)/libs.ref/gf180mcu_fd_ip_sram/verilog/gf180mcu_fd_ip_sram__sram256x8m8wm1.v" set ::env(EXTRA_LEFS) "\
diff --git a/openlane/serv_0/macro.cfg b/openlane/serv_0/macro.cfg new file mode 100644 index 0000000..ddbadba --- /dev/null +++ b/openlane/serv_0/macro.cfg
@@ -0,0 +1 @@ +u_cpu.rf_ram.RAM0 80 80 W
diff --git a/openlane/tiny_user_project/pdn.tcl b/openlane/serv_0/pdn.tcl similarity index 100% rename from openlane/tiny_user_project/pdn.tcl rename to openlane/serv_0/pdn.tcl
diff --git a/openlane/serv_0/pin_order.cfg b/openlane/serv_0/pin_order.cfg new file mode 100644 index 0000000..4310156 --- /dev/null +++ b/openlane/serv_0/pin_order.cfg
@@ -0,0 +1,8 @@ +#BUS_SORT + +#E +io_in.* +io_out.* +io_oeb.* + +
diff --git a/openlane/tiny_user_project/config.tcl b/openlane/serv_1/config.tcl similarity index 62% copy from openlane/tiny_user_project/config.tcl copy to openlane/serv_1/config.tcl index 926e4cd..75fd958 100644 --- a/openlane/tiny_user_project/config.tcl +++ b/openlane/serv_1/config.tcl
@@ -15,7 +15,7 @@ set script_dir [file dirname [file normalize [info script]/../../]] -set ::env(DESIGN_NAME) tiny_user_project +set ::env(DESIGN_NAME) serv_1 set ::env(DESIGN_IS_CORE) 0 set ::env(PDK) "gf180mcuC" @@ -24,7 +24,7 @@ #set ::env(RUN_KLAYOUT) 0 set ::env(CLOCK_TREE_SYNTH) 1 -set ::env(CLOCK_PORT) {io_in[8]} +set ::env(CLOCK_PORT) {io_in[13] o_in[17]} #set ::env(CLOCK_NET) "" set ::env(CLOCK_PERIOD) 50 set ::env(SYNTH_MAX_FANOUT) 16 @@ -51,33 +51,20 @@ set ::env(VDD_NETS) [list {vdd}] set ::env(GND_NETS) [list {vss}] -## Internal Macros -### Macro PDN Connections -set ::env(FP_PDN_MACRO_HOOKS) "\ - mod.u_cpu.rf_ram.RAM0 vdd vss vdd vss" -set ::env(FP_PDN_MACROS) "\ - mod.u_cpu.rf_ram.RAM0" - set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg -## Internal Macros -set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro.cfg - set ::env(DESIGN_DIR) $script_dir/../../verilog - #$::env(DESIGN_DIR)/blocks/serv/rtl/serv_rf_ram.v \ - set ::env(VERILOG_FILES) "\ $::env(DESIGN_DIR)/rtl/defines.v \ - $::env(DESIGN_DIR)/rtl/top.v \ - $::env(DESIGN_DIR)/rtl/serv_rf_ram_gf180.v \ + $::env(DESIGN_DIR)/rtl/serv_1.v \ $::env(DESIGN_DIR)/rtl/scanchain_gf180.v \ - $::env(DESIGN_DIR)/rtl/tiny_user_project.v \ $::env(DESIGN_DIR)/blocks/serv/rtl/serv_top.v \ $::env(DESIGN_DIR)/blocks/serv/rtl/serv_synth_wrapper.v \ $::env(DESIGN_DIR)/blocks/serv/rtl/serv_mem_if.v \ $::env(DESIGN_DIR)/blocks/serv/rtl/serv_rf_if.v \ $::env(DESIGN_DIR)/blocks/serv/rtl/serv_rf_top.v \ + $::env(DESIGN_DIR)/blocks/serv/rtl/serv_rf_ram.v \ $::env(DESIGN_DIR)/blocks/serv/rtl/serv_rf_ram_if.v \ $::env(DESIGN_DIR)/blocks/serv/rtl/serv_alu.v \ $::env(DESIGN_DIR)/blocks/serv/rtl/serv_ctrl.v \ @@ -90,41 +77,9 @@ $::env(DESIGN_DIR)/blocks/serv/rtl/serv_state.v \ $::env(DESIGN_DIR)/blocks/serv/rtl/serv_csr.v \ $::env(DESIGN_DIR)/blocks/serv/servant/servant_arbiter.v \ - $::env(DESIGN_DIR)/blocks/serv/servant/servant_mux.v \ - $::env(DESIGN_DIR)/blocks/serv/servant/servant_gpio.v" + $::env(DESIGN_DIR)/blocks/serv/servant/servant_mux.v" set ::env(VERILOG_FILES_BLACKBOX) "\ - $::env(DESIGN_DIR)/rtl/gf180mcu_fd_sc_mcu7t5v0_bb.v \ - $::env(PDK_ROOT)/$::env(PDK)/libs.ref/gf180mcu_fd_ip_sram/verilog/gf180mcu_fd_ip_sram__sram256x8m8wm1.v" - -set ::env(EXTRA_LEFS) "\ - $::env(PDK_ROOT)/$::env(PDK)/libs.ref/gf180mcu_fd_ip_sram/lef/gf180mcu_fd_ip_sram__sram256x8m8wm1.lef" -set ::env(EXTRA_GDS_FILES) "\ - $::env(PDK_ROOT)/$::env(PDK)/libs.ref/gf180mcu_fd_ip_sram/gds/gf180mcu_fd_ip_sram__sram256x8m8wm1.gds" -set ::env(EXTRA_LIBS) "\ - $::env(PDK_ROOT)/$::env(PDK)/libs.ref/gf180mcu_fd_ip_sram/liberty/gf180mcu_fd_ip_sram__sram256x8m8wm1__tt_025C_1v80.lib" - -set ::env(QUIT_ON_MISMATCHES) 0 - -## PDN -set ::env(PDN_CFG) $script_dir/pdn.tcl -set ::env(FP_PDN_ENABLE_MACROS_GRID) 1 -set ::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS) 1 - -## PDN -set ::env(FP_PDN_VPITCH) 30 -#set ::env(FP_PDN_HPITCH) 30 - -#set ::env(FP_PDN_VWIDTH) 3 -#set ::env(FP_PDN_CORE_RING) 0 - -## LVS -set ::env(MAGIC_DRC_USE_GDS) 0 -set ::env(MAGIC_WRITE_FULL_LEF) 0 -set ::env(RUN_MAGIC_DRC) 0 -set ::env(QUIT_ON_MAGIC_DRC) 0 + $::env(DESIGN_DIR)/rtl/bb/gf180mcu_fd_sc_mcu7t5v0.v" set ::env(RUN_CVC) 1 - -# Temporary ignore -set ::env(QUIT_ON_LVS_ERROR) 0 \ No newline at end of file
diff --git a/openlane/serv_1/pin_order.cfg b/openlane/serv_1/pin_order.cfg new file mode 100644 index 0000000..4310156 --- /dev/null +++ b/openlane/serv_1/pin_order.cfg
@@ -0,0 +1,8 @@ +#BUS_SORT + +#E +io_in.* +io_out.* +io_oeb.* + +
diff --git a/openlane/tiny_user_project/macro.cfg b/openlane/tiny_user_project/macro.cfg deleted file mode 100644 index 32dc4d8..0000000 --- a/openlane/tiny_user_project/macro.cfg +++ /dev/null
@@ -1 +0,0 @@ -mod.u_cpu.rf_ram.RAM0 80 80 W
diff --git a/openlane/tiny_user_project/pin_order.cfg b/openlane/tiny_user_project/pin_order.cfg deleted file mode 100644 index df5ed5b..0000000 --- a/openlane/tiny_user_project/pin_order.cfg +++ /dev/null
@@ -1,12 +0,0 @@ -#BUS_SORT - -#S -wb_.* -wbs_.* -la_.* -irq.* - -#N -io_.* -user_.* -
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl index 4155c34..99d4797 100644 --- a/openlane/user_project_wrapper/config.tcl +++ b/openlane/user_project_wrapper/config.tcl
@@ -33,15 +33,16 @@ $::env(DESIGN_DIR)/../../verilog/rtl/user_project_wrapper.v" ## Clock configurations -set ::env(CLOCK_PORT) "user_clock2" -set ::env(CLOCK_NET) "mprj.clk" +set ::env(CLOCK_PORT) {io[8]} +set ::env(CLOCK_NET) "" set ::env(CLOCK_PERIOD) "50" ## Internal Macros ### Macro PDN Connections set ::env(FP_PDN_MACRO_HOOKS) "\ - mprj vdd vss vdd vss" + u_serv_0 vdd vss vdd vss, \ + u_serv_1 vdd vss vdd vss" ### Macro Placement set ::env(MACRO_PLACEMENT_CFG) $::env(DESIGN_DIR)/macro.cfg @@ -49,13 +50,16 @@ ### Black-box verilog and views set ::env(VERILOG_FILES_BLACKBOX) "\ $::env(CARAVEL_ROOT)/verilog/rtl/defines.v \ - $::env(DESIGN_DIR)/../../verilog/rtl/tiny_user_project.v" + $::env(DESIGN_DIR)/../../verilog/rtl/serv_0.v \ + $::env(DESIGN_DIR)/../../verilog/rtl/serv_1.v" set ::env(EXTRA_LEFS) "\ - $::env(DESIGN_DIR)/../../lef/tiny_user_project.lef" + $::env(DESIGN_DIR)/../../lef/serv_0.lef \ + $::env(DESIGN_DIR)/../../lef/serv_1.lef" set ::env(EXTRA_GDS_FILES) "\ - $::env(DESIGN_DIR)/../../gds/tiny_user_project.gds" + $::env(DESIGN_DIR)/../../gds/serv_0.gds \ + $::env(DESIGN_DIR)/../../gds/serv_1.gds" set ::env(RT_MAX_LAYER) {Metal4} @@ -84,8 +88,6 @@ set ::env(QUIT_ON_MAGIC_DRC) 0 set ::env(RUN_MAGIC_DRC) 0 -# Temporary ignore -set ::env(QUIT_ON_LVS_ERROR) 0 # YOU ARE NOT ALLOWED TO CHANGE ANY VARIABLES DEFINED IN THE FIXED WRAPPER CFGS source $::env(DESIGN_DIR)/fixed_dont_change/fixed_wrapper_cfgs.tcl
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg index 9420fb9..ab8b6d7 100644 --- a/openlane/user_project_wrapper/macro.cfg +++ b/openlane/user_project_wrapper/macro.cfg
@@ -1 +1,2 @@ -mprj 500 500 N \ No newline at end of file +u_serv_0 500 500 N +u_serv_1 500 1000 N \ No newline at end of file
diff --git a/verilog/rtl/gf180mcu_fd_sc_mcu7t5v0_bb.v b/verilog/rtl/bb/gf180mcu_fd_sc_mcu7t5v0.v similarity index 100% rename from verilog/rtl/gf180mcu_fd_sc_mcu7t5v0_bb.v rename to verilog/rtl/bb/gf180mcu_fd_sc_mcu7t5v0.v
diff --git a/verilog/rtl/top.v b/verilog/rtl/serv_0.v similarity index 85% rename from verilog/rtl/top.v rename to verilog/rtl/serv_0.v index b3d84fd..f4d1aab 100644 --- a/verilog/rtl/top.v +++ b/verilog/rtl/serv_0.v
@@ -1,10 +1,20 @@ +// Copyright 2022 Google LLC. +// SPDX-License-Identifier: Apache-2.0 `default_nettype none -// Keep I/O fixed for TinyTapeout -module gregdavill_serv_top( - input [7:0] io_in, - output [7:0] io_out - ); +// tiny_user_project top module instance +// generated by configure.py +module serv_0( +`ifdef USE_POWER_PINS + inout vdd, // User area 5.0V supply + inout vss, // User area ground +`endif + + // IOs + input [4:0] io_in, + output [4:0] io_out, + output [4:0] io_oeb, +); wire clk = io_in[0]; wire reset = io_in[1]; @@ -121,4 +131,9 @@ timer_irq}) // 1 ); -endmodule +// all output enabled +assign io_oeb[4:0] = 5'b0; + +endmodule // tiny_user_project + +`default_nettype wire \ No newline at end of file
diff --git a/verilog/rtl/top.v b/verilog/rtl/serv_1.v similarity index 85% copy from verilog/rtl/top.v copy to verilog/rtl/serv_1.v index b3d84fd..efddff3 100644 --- a/verilog/rtl/top.v +++ b/verilog/rtl/serv_1.v
@@ -1,10 +1,20 @@ +// Copyright 2022 Google LLC. +// SPDX-License-Identifier: Apache-2.0 `default_nettype none -// Keep I/O fixed for TinyTapeout -module gregdavill_serv_top( - input [7:0] io_in, - output [7:0] io_out - ); +// tiny_user_project top module instance +// generated by configure.py +module serv_1( +`ifdef USE_POWER_PINS + inout vdd, // User area 5.0V supply + inout vss, // User area ground +`endif + + // IOs + input [4:0] io_in, + output [4:0] io_out, + output [4:0] io_oeb, +); wire clk = io_in[0]; wire reset = io_in[1]; @@ -121,4 +131,9 @@ timer_irq}) // 1 ); -endmodule +// all output enabled +assign io_oeb[4:0] = 5'b0; + +endmodule // tiny_user_project + +`default_nettype wire \ No newline at end of file
diff --git a/verilog/rtl/tiny_user_project.v b/verilog/rtl/tiny_user_project.v deleted file mode 100644 index 60265e9..0000000 --- a/verilog/rtl/tiny_user_project.v +++ /dev/null
@@ -1,52 +0,0 @@ -// Copyright 2022 Google LLC. -// SPDX-License-Identifier: Apache-2.0 -`default_nettype none - -// tiny_user_project top module instance -// generated by configure.py -module tiny_user_project( -`ifdef USE_POWER_PINS - inout vdd, // User area 5.0V supply - inout vss, // User area ground -`endif - - // Wishbone Slave ports (WB MI A) - input wb_clk_i, - input wb_rst_i, - input wbs_stb_i, - input wbs_cyc_i, - input wbs_we_i, - input [3:0] wbs_sel_i, - input [31:0] wbs_dat_i, - input [31:0] wbs_adr_i, - output wbs_ack_o, - output [31:0] wbs_dat_o, - - // Logic Analyzer Signals - input [63:0] la_data_in, - output [63:0] la_data_out, - input [63:0] la_oenb, - - // IOs - input [`MPRJ_IO_PADS-1:0] io_in, - output [`MPRJ_IO_PADS-1:0] io_out, - output [`MPRJ_IO_PADS-1:0] io_oeb, - - // Independent clock (on independent integer divider) - input user_clock2, - - // User maskable interrupt signals - output [2:0] user_irq -); - -// pass input and output pins defined in user_defines.v -gregdavill_serv_top mod ( - io_in[12:8], - io_out[14:13] -); -// all output enabled -assign io_oeb[14:13] = 8'b0; - -endmodule // tiny_user_project - -`default_nettype wire \ No newline at end of file
diff --git a/verilog/rtl/tiny_user_project.v.jinja2 b/verilog/rtl/tiny_user_project.v.jinja2 deleted file mode 100644 index c5035fd..0000000 --- a/verilog/rtl/tiny_user_project.v.jinja2 +++ /dev/null
@@ -1,52 +0,0 @@ -// Copyright 2022 Google LLC. -// SPDX-License-Identifier: Apache-2.0 -`default_nettype none - -// tiny_user_project top module instance -// generated by configure.py -module tiny_user_project( -`ifdef USE_POWER_PINS - inout vdd, // User area 5.0V supply - inout vss, // User area ground -`endif - - // Wishbone Slave ports (WB MI A) - input wb_clk_i, - input wb_rst_i, - input wbs_stb_i, - input wbs_cyc_i, - input wbs_we_i, - input [3:0] wbs_sel_i, - input [31:0] wbs_dat_i, - input [31:0] wbs_adr_i, - output wbs_ack_o, - output [31:0] wbs_dat_o, - - // Logic Analyzer Signals - input [63:0] la_data_in, - output [63:0] la_data_out, - input [63:0] la_oenb, - - // IOs - input [`MPRJ_IO_PADS-1:0] io_in, - output [`MPRJ_IO_PADS-1:0] io_out, - output [`MPRJ_IO_PADS-1:0] io_oeb, - - // Independent clock (on independent integer divider) - input user_clock2, - - // User maskable interrupt signals - output [2:0] user_irq -); - -// pass input and output pins defined in user_defines.v -{{ module_name }} mod ( - io_in[{{ io_in_range[1] - 1 }}:{{ io_in_range[0] }}], - io_out[{{ io_out_range[1] - 1 }}:{{ io_out_range[0] }}] -); -// all output enabled -assign io_oeb[{{ io_out_range[1] - 1 }}:{{ io_out_range[0] }}] = 8'b0; - -endmodule // tiny_user_project - -`default_nettype wire \ No newline at end of file
diff --git a/verilog/rtl/user_defines.v.jinja2 b/verilog/rtl/user_defines.v.jinja2 deleted file mode 100644 index c935c87..0000000 --- a/verilog/rtl/user_defines.v.jinja2 +++ /dev/null
@@ -1,68 +0,0 @@ -// SPDX-FileCopyrightText: 2020 Efabless Corporation -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// SPDX-License-Identifier: Apache-2.0 - -`default_nettype none - -`ifndef __USER_DEFINES_H -// User GPIO initial configuration parameters -`define __USER_DEFINES_H - -// deliberately erroneous placeholder value; user required to config GPIO's to other -`define GPIO_MODE_INVALID 13'hXXXX - -// Authoritive source of these MODE defs is: caravel/verilog/rtl/user_defines.v -// Useful GPIO mode values. These match the names used in defs.h. -// -`define GPIO_MODE_MGMT_STD_INPUT_NOPULL 13'h0403 -`define GPIO_MODE_MGMT_STD_INPUT_PULLDOWN 13'h0c01 -`define GPIO_MODE_MGMT_STD_INPUT_PULLUP 13'h0801 -`define GPIO_MODE_MGMT_STD_OUTPUT 13'h1809 -`define GPIO_MODE_MGMT_STD_BIDIRECTIONAL 13'h1801 -`define GPIO_MODE_MGMT_STD_ANALOG 13'h000b - -`define GPIO_MODE_USER_STD_INPUT_NOPULL 13'h0402 -`define GPIO_MODE_USER_STD_INPUT_PULLDOWN 13'h0c00 -`define GPIO_MODE_USER_STD_INPUT_PULLUP 13'h0800 -`define GPIO_MODE_USER_STD_OUTPUT 13'h1808 -`define GPIO_MODE_USER_STD_BIDIRECTIONAL 13'h1800 -`define GPIO_MODE_USER_STD_OUT_MONITORED 13'h1802 -`define GPIO_MODE_USER_STD_ANALOG 13'h000a - -// The power-on configuration for GPIO 0 to 4 is fixed and cannot be -// modified (allowing the SPI and debug to always be accessible unless -// overridden by a flash program). - -// The values below can be any of the standard types defined above, -// or they can be any 13-bit value if the user wants a non-standard -// startup state for the GPIO. By default, every GPIO from 5 to 37 -// is set to power up as an input controlled by the management SoC. -// Users may want to redefine these so that the user project powers -// up in a state that can be used immediately without depending on -// the management SoC to run a startup program to configure the GPIOs. - -// tiny_user_project i/o -// generated by configure.py - -{% for n in range(5, 38) -%} -{%- if io_in_range[0] <= n < io_in_range[1] %} -`define USER_CONFIG_GPIO_{{ n }}_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL -{%- elif io_out_range[0] <= n < io_out_range[1] %} -`define USER_CONFIG_GPIO_{{ n }}_INIT `GPIO_MODE_USER_STD_OUTPUT -{%- else %} -`define USER_CONFIG_GPIO_{{ n }}_INIT `GPIO_MODE_INVALID -{%- endif -%} -{% endfor %} - -`endif // __USER_DEFINES_H
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v index 7c2ee74..375b780 100644 --- a/verilog/rtl/user_project_wrapper.v +++ b/verilog/rtl/user_project_wrapper.v
@@ -70,41 +70,28 @@ /* User project is instantiated here */ /*--------------------------------------*/ -tiny_user_project mprj ( +serv_0 u_serv_0 ( `ifdef USE_POWER_PINS .vdd(vdd), .vss(vss), `endif - - // MGMT SoC Wishbone Slave - - .wb_clk_i(wb_clk_i), - .wb_rst_i(wb_rst_i), - .wbs_stb_i(wbs_stb_i), - .wbs_cyc_i(wbs_cyc_i), - .wbs_we_i(wbs_we_i), - .wbs_sel_i(wbs_sel_i), - .wbs_dat_i(wbs_dat_i), - .wbs_adr_i(wbs_adr_i), - .wbs_ack_o(wbs_ack_o), - .wbs_dat_o(wbs_dat_o), - - // Logic Analyzer - - .la_data_in(la_data_in), - .la_data_out(la_data_out), - .la_oenb (la_oenb), - // IO Pads - .io_in (io_in), - .io_out(io_out), - .io_oeb(io_oeb), + .io_in (io_in[12:8]), + .io_out(io_out[12:8]), + .io_oeb(io_oeb[12:8]) +); - .user_clock2(user_clock2), +serv_1 u_serv_1 ( +`ifdef USE_POWER_PINS + .vdd(vdd), + .vss(vss), +`endif + // IO Pads - // IRQ - .user_irq(user_irq) + .io_in (io_in[17:13]), + .io_out(io_out[17:13]), + .io_oeb(io_oeb[17:13]) ); endmodule // user_project_wrapper