rtl: Add inital serv project

diff --git a/.gitmodules b/.gitmodules
new file mode 100644
index 0000000..9d7cf4d
--- /dev/null
+++ b/.gitmodules

@@ -0,0 +1,3 @@
+[submodule "verilog/blocks/serv"]
+	path = verilog/blocks/serv
+	url = git@github.com:olofk/serv.git

diff --git a/openlane/tiny_user_project/config.json b/openlane/tiny_user_project/config.json
index 652cdce..f544398 100644
--- a/openlane/tiny_user_project/config.json
+++ b/openlane/tiny_user_project/config.json

@@ -2,17 +2,33 @@
     "DESIGN_NAME": "tiny_user_project",
     "DESIGN_IS_CORE": 0,
     "VERILOG_FILES": [
-        "dir::../../verilog/rtl/user_module.v",
-        "dir::../../verilog/rtl/cells.v",
-        "dir::../../verilog/rtl/defines.v",
         "dir::../../verilog/rtl/tiny_user_project.v"
+        "dir::../../verilog/rtl/top.v",
+        "dir::../../verilog/rtl/scanchain.v",
+        "dir::../../verilog/rtl/wb_mux.v",
+        "dir::../../verilog/blocks/serv/rtl/serv_top.v",
+        "dir::../../verilog/blocks/serv/rtl/serv_synth_wrapper.v",
+        "dir::../../verilog/blocks/serv/rtl/serv_mem_if.v",
+        "dir::../../verilog/blocks/serv/rtl/serv_rf_if.v",
+        "dir::../../verilog/blocks/serv/rtl/serv_rf_ram_if.v",
+        "dir::../../verilog/blocks/serv/rtl/serv_alu.v",
+        "dir::../../verilog/blocks/serv/rtl/serv_ctrl.v",
+        "dir::../../verilog/blocks/serv/rtl/serv_bufreg2.v",
+        "dir::../../verilog/blocks/serv/rtl/serv_bufreg.v",
+        "dir::../../verilog/blocks/serv/rtl/serv_immdec.v",
+        "dir::../../verilog/blocks/serv/rtl/serv_decode.v",
+        "dir::../../verilog/blocks/serv/rtl/serv_state.v",
+        "dir::../../verilog/blocks/serv/rtl/serv_csr.v",
+        "dir::../../verilog/blocks/serv/servant/servant_arbiter.v",
+        "dir::../../verilog/blocks/serv/servant/servant_mux.v",
+        "dir::../../verilog/blocks/serv/servant/servant_gpio.v"
     ],
     "CLOCK_PERIOD": 24,
     "CLOCK_PORT": "",
     "CLOCK_NET": "",
     "FP_SIZING": "absolute",
-    "DIE_AREA": "0 0 1100 800",
-    "PL_BASIC_PLACEMENT": 1,
+    "DIE_AREA": "0 0 600 680",
+    "PL_BASIC_PLACEMENT": 0,
     "PL_TARGET_DENSITY": 0.55,
     "SYNTH_USE_PG_PINS_DEFINES": "USE_POWER_PINS",
     "VDD_NETS": [
@@ -25,19 +41,10 @@
     "RUN_CVC": 1,
     "RUN_KLAYOUT_XOR": 0,
     "RUN_KLAYOUT_DRC": 0,
-    "pdk::sky130*": {
-        "DECAP_CELL": [
-            "sky130_fd_sc_hd__decap_3",
-            "sky130_fd_sc_hd__decap_4",
-            "sky130_fd_sc_hd__decap_6",
-            "sky130_fd_sc_hd__decap_8",
-            "sky130_ef_sc_hd__decap_12"
-        ],
-        "RT_MAX_LAYER": "met4"
-    },
+    "SYNTH_READ_BLACKBOX_LIB": 0, 
     "pdk::gf180mcuC": {
         "STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0",
         "RT_MAX_LAYER": "Metal4",
         "SYNTH_MAX_FANOUT": 4
     }
-}
+}
\ No newline at end of file

diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index c496bfb..314035c 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg

@@ -1,2 +1,2 @@
-mprj 800 1100 N
+mprj 1200 1160 N
 

diff --git a/scripts/create_svg.py b/scripts/create_svg.py
new file mode 100644
index 0000000..0bac98b
--- /dev/null
+++ b/scripts/create_svg.py

@@ -0,0 +1,8 @@
+import gdstk
+import pathlib
+gds = sorted(pathlib.Path('.').glob('gds/tiny_user_project.gds'))
+library = gdstk.read_gds(gds[-1])
+top_cells = library.top_level()
+top_cells[0].write_svg('gds_render.svg')
+import cairosvg
+cairosvg.svg2png(url='gds_render.svg', write_to='gds_render.png')
\ No newline at end of file

diff --git a/verilog/blocks/serv b/verilog/blocks/serv
new file mode 160000
index 0000000..7c004e8
--- /dev/null
+++ b/verilog/blocks/serv

@@ -0,0 +1 @@
+Subproject commit 7c004e8f7b0776cf4664a5311625f534eaff49f1

diff --git a/verilog/rtl/cells.v b/verilog/rtl/cells.v
deleted file mode 100644
index fb6db62..0000000
--- a/verilog/rtl/cells.v
+++ /dev/null

@@ -1,96 +0,0 @@
-`define default_netname none
-
-module buffer_cell (
-    input wire in,
-    output wire out
-    );
-    assign out = in;
-endmodule
-
-module and_cell (
-    input wire a,
-    input wire b,
-    output wire out
-    );
-
-    assign out = a & b;
-endmodule
-
-module or_cell (
-    input wire a,
-    input wire b,
-    output wire out
-    );
-
-    assign out = a | b;
-endmodule
-
-module xor_cell (
-    input wire a,
-    input wire b,
-    output wire out
-    );
-
-    assign out = a ^ b;
-endmodule
-
-module nand_cell (
-    input wire a,
-    input wire b,
-    output wire out
-    );
-
-    assign out = !(a&b);
-endmodule
-
-module not_cell (
-    input wire in,
-    output wire out
-    );
-
-    assign out = !in;
-endmodule
-
-module mux_cell (
-    input wire a,
-    input wire b,
-    input wire sel,
-    output wire out
-    );
-
-    assign out = sel ? b : a;
-endmodule
-
-module dff_cell (
-    input wire clk,
-    input wire d,
-    output reg q,
-    output wire notq
-    );
-
-    assign notq = !q;
-    always @(posedge clk)
-        q <= d;
-
-endmodule
-
-module dffsr_cell (
-    input wire clk,
-    input wire d,
-    input wire s,
-    input wire r,
-    output reg q,
-    output wire notq
-    );
-
-    assign notq = !q;
-
-    always @(posedge clk or posedge s or posedge r) begin
-        if (r)
-            q <= '0;
-        else if (s)
-            q <= '1;
-        else
-            q <= d;
-    end
-endmodule

diff --git a/verilog/rtl/pin_order.cfg b/verilog/rtl/pin_order.cfg
new file mode 100644
index 0000000..0b85c63
--- /dev/null
+++ b/verilog/rtl/pin_order.cfg

@@ -0,0 +1,9 @@
+#N
+
+#S
+
+#E
+
+#W
+io_in.*
+io_out.*

diff --git a/verilog/rtl/scanchain.v b/verilog/rtl/scanchain.v
new file mode 100644
index 0000000..ea7ff4e
--- /dev/null
+++ b/verilog/rtl/scanchain.v

@@ -0,0 +1,62 @@
+`default_nettype none
+
+module scanchain_local #(
+    parameter SCAN_LENGTH = 2)
+  (
+    input wire clk_in,
+    input wire data_in,
+    input wire scan_select_in,
+    input wire latch_enable_in,
+    output wire clk_out,
+    output wire data_out,
+    output wire scan_select_out,
+    output wire latch_enable_out,
+
+    // io, names from point of view of the user module
+    input wire [SCAN_LENGTH-1:0] module_data_out,
+    output wire [SCAN_LENGTH-1:0] module_data_in
+  );
+
+  // input buffers
+  // Looking at results from multiple projects the buffering is a bit
+  // inconsistent. So instead, we ensure at least clk buf
+  wire clk;
+  always @(*) begin
+    clk <= clk_in;
+  end
+
+  // output buffers
+  // Same as for input, to try and be more consistent, we make our own
+  wire data_out_i;
+  always @(*) begin
+    clk_out <= clk;
+    data_out <= data_out_i;
+    scan_select_out <= scan_select_in;
+    latch_enable_out <= latch_enable_in;
+  end
+
+
+  // wires needed
+  wire [SCAN_LENGTH-1:0] scan_data_out;   // output of the each scan chain flop
+  wire [SCAN_LENGTH-1:0] scan_data_in;    // input of each scan chain flop
+
+  // scan chain - link all the flops, with data coming from data_in
+  assign scan_data_in = {scan_data_out[SCAN_LENGTH-2:0], data_in};
+
+  // end of the chain is a negedge FF to increase hold margin between blocks
+  always @(negedge clk) begin
+    data_out_i <= scan_data_out[SCAN_LENGTH-1];
+  end
+
+  // scan flops have a mux on their inputs to choose either data from the user module or the previous flop's output
+  always @(posedge clk) begin
+    if(scan_select_in)
+      scan_data_out <= module_data_out;
+    else
+      scan_data_out <= scan_data_in;
+  end
+  
+  /* Because we control the clock into serv, we can avoid the extra latches here */
+  assign module_data_in = scan_data_out;
+
+endmodule

diff --git a/verilog/rtl/tiny_user_project.v b/verilog/rtl/tiny_user_project.v
index b16a4ad..b3d7135 100644
--- a/verilog/rtl/tiny_user_project.v
+++ b/verilog/rtl/tiny_user_project.v

@@ -40,7 +40,7 @@
 );
 
 // pass input and output pins defined in user_defines.v
-user_module_334445762078310996 mod (
+gregdavill_serv_top u_mod (
     io_in[15:8],
     io_out[23:16]
 );

diff --git a/verilog/rtl/top.v b/verilog/rtl/top.v
new file mode 100644
index 0000000..085c991
--- /dev/null
+++ b/verilog/rtl/top.v

@@ -0,0 +1,184 @@
+`default_nettype none
+
+// Keep I/O fixed for TinyTapeout
+module gregdavill_serv_top(
+    input [7:0] io_in,
+    output [7:0] io_out
+  );
+
+  wire clk =   io_in[0];
+  wire reset = io_in[7];
+
+  wire data =         io_in[4];
+  wire scan_select =  io_in[5];
+  wire latch_enable = io_in[6];
+  wire serv_clk =     io_in[7];
+
+  wire timer_irq;
+
+  parameter reset_strategy = "MINI";
+  parameter sim = 0;
+  parameter with_csr = 0;
+  parameter [0:0] compress = 0;
+  parameter [0:0] align = 0;
+
+  wire [4+with_csr:0] wreg0;
+  wire [4+with_csr:0] wreg1;
+  wire [4+with_csr:0] rreg0;
+  wire [4+with_csr:0] rreg1;
+  wire 	      rf_wreq;
+  wire 	      rf_rreq;
+  wire 	      wen0;
+  wire 	      wen1;
+  wire 	      wdata0;
+  wire 	      wdata1;
+  wire 	      rf_ready;
+  wire 	      rdata0;
+  wire 	      rdata1;
+
+  wire [31:0] 	wb_ibus_adr;
+  wire [31:0] 	wb_ibus_rdt;
+  wire 	wb_ibus_cyc;
+  wire 	wb_ibus_ack;
+
+  wire [31:0] 	wb_dbus_adr;
+  wire [31:0] 	wb_dbus_dat;
+  wire [3:0] 	wb_dbus_sel;
+  wire [31:0] 	wb_dbus_rdt;
+  wire 	wb_dbus_we;
+  wire 	wb_dbus_cyc;
+  wire 	wb_dbus_ack;
+
+  wire [31:0] 	wb_dmem_adr;
+  wire [31:0] 	wb_dmem_dat;
+  wire [3:0] 	wb_dmem_sel;
+  wire [31:0] 	wb_dmem_rdt;
+  wire 	wb_dmem_we;
+  wire 	wb_dmem_cyc;
+  wire 	wb_dmem_ack;
+
+  wire [31:0] 	wb_mem_adr;
+  wire [31:0] 	wb_mem_dat;
+  wire [3:0] 	wb_mem_sel;
+  wire [31:0] 	wb_mem_rdt;
+  wire 	wb_mem_we;
+  wire 	wb_mem_cyc;
+  wire 	wb_mem_ack;
+
+  wire 	wb_gpio_dat;
+  wire 	wb_gpio_we;
+  wire 	wb_gpio_cyc;
+  wire 	wb_gpio_rdt;
+
+
+  servant_arbiter u_arbiter (
+    .i_wb_cpu_dbus_adr (wb_dbus_adr),
+    .i_wb_cpu_dbus_dat (wb_dbus_dat),
+    .i_wb_cpu_dbus_sel (wb_dbus_sel),
+    .i_wb_cpu_dbus_we  (wb_dbus_we ),
+    .i_wb_cpu_dbus_cyc (wb_dbus_cyc),
+    .o_wb_cpu_dbus_rdt (wb_dbus_rdt),
+    .o_wb_cpu_dbus_ack (wb_dbus_ack),
+
+    .i_wb_cpu_ibus_adr (wb_ibus_adr),
+    .i_wb_cpu_ibus_cyc (wb_ibus_cyc),
+    .o_wb_cpu_ibus_rdt (wb_ibus_rdt),
+    .o_wb_cpu_ibus_ack (wb_ibus_ack),
+
+    .o_wb_cpu_adr (wb_mem_adr),
+    .o_wb_cpu_dat (wb_mem_dat),
+    .o_wb_cpu_sel (wb_mem_sel),
+    .o_wb_cpu_we  (wb_mem_we ),
+    .o_wb_cpu_cyc (wb_mem_cyc),
+    .i_wb_cpu_rdt (wb_mem_rdt),
+    .i_wb_cpu_ack (wb_mem_ack)
+  );
+
+
+  serv_top #(
+    .RESET_PC (32'h0000_0000),
+    .PRE_REGISTER(1),
+    .RESET_STRATEGY (reset_strategy),
+    .WITH_CSR (with_csr),
+    .COMPRESSED(compress),
+    .ALIGN(align))
+  cpu
+  (
+    .clk          (serv_clk),
+    .i_rst        (reset),
+    .i_timer_irq  (timer_irq),
+
+    .o_rf_rreq    (rf_rreq),
+    .o_rf_wreq    (rf_wreq),
+    .i_rf_ready   (rf_ready),
+    .o_wreg0      (wreg0),
+    .o_wreg1      (wreg1),
+    .o_wen0       (wen0),
+    .o_wen1       (wen1),
+    .o_wdata0     (wdata0),
+    .o_wdata1     (wdata1),
+    .o_rreg0      (rreg0),
+    .o_rreg1      (rreg1),
+    .i_rdata0     (rdata0),
+    .i_rdata1     (rdata1),
+
+    .o_ibus_adr   (wb_ibus_adr),
+    .o_ibus_cyc   (wb_ibus_cyc),
+    .i_ibus_rdt   (wb_ibus_rdt),
+    .i_ibus_ack   (wb_ibus_ack),
+
+    .o_dbus_adr   (wb_dbus_adr),
+    .o_dbus_dat   (wb_dbus_dat),
+    .o_dbus_sel   (wb_dbus_sel),
+    .o_dbus_we    (wb_dbus_we),
+    .o_dbus_cyc   (wb_dbus_cyc),
+    .i_dbus_rdt   (wb_dbus_rdt),
+    .i_dbus_ack   (wb_dbus_ack)
+  );
+
+
+  scanchain_local #(
+    .SCAN_LENGTH(96))
+  u_scanchain_local
+  (
+    // Inputs from TinyTapeout scanchain to our internal scanchain
+    .clk_in          (clk),
+    .data_in         (data),
+    .scan_select_in  (scan_select),
+
+    // Pass all signals out from our internal scanchain, only really need data
+    .clk_out         (io_out[0]),
+    .data_out        (io_out[1]),
+    .scan_select_out (io_out[2]),
+
+    // data
+    .module_data_out ({
+      // Bus interface
+      wb_mem_adr[31:0],   // 32
+      wb_mem_dat,         // 32
+      wb_mem_sel,         // 4
+      wb_mem_we,          // 1
+      wb_mem_cyc,         // 1
+      // RF interface
+      rf_wreq,            // 1
+      rf_rreq,            // 1
+      wreg0,              // 5
+      wreg1,              // 5
+      wen0,               // 1
+      wen1,               // 1
+      wdata0,             // 1
+      wdata1,             // 1
+      rreg0,              // 5
+      rreg1}),            // 5
+
+    .module_data_in  ({
+      // Bus interface
+      wb_mem_rdt,         // 32
+      wb_mem_ack,         // 1
+      timer_irq,          // 1
+      rf_ready,           // 1
+      rdata0,             // 1
+      rdata1})            // 1
+  );
+
+endmodule

diff --git a/verilog/rtl/user_module.v b/verilog/rtl/user_module.v
deleted file mode 100644
index aea8267..0000000
--- a/verilog/rtl/user_module.v
+++ /dev/null

@@ -1,88 +0,0 @@
-/* Automatically generated from https://wokwi.com/projects/334445762078310996 */
-
-`default_nettype none
-
-module user_module_334445762078310996(
-  input [7:0] io_in,
-  output [7:0] io_out
-);
-  wire net1 = 1'b1;
-  wire net2 = 1'b0;
-  wire net3;
-  wire net4;
-  wire net5;
-  wire net6;
-  wire net7;
-  wire net8 = 1'b1;
-  wire net9 = 1'b0;
-  wire net10;
-  wire net11;
-  wire net12 = 1'b1;
-  wire net13 = 1'b0;
-  wire net14;
-  wire net15 = 1'b1;
-  wire net16 = 1'b0;
-  wire net17;
-  wire net18 = 1'b0;
-  wire net19 = 1'b1;
-  wire net20;
-  wire net21 = 1'b1;
-  wire net22;
-  wire net23;
-  wire net24 = 1'b0;
-  wire net25 = 1'b0;
-
-  and_cell gate1 (
-    .a (net3)
-  );
-  or_cell gate2 (
-
-  );
-  xor_cell gate3 (
-
-  );
-  nand_cell gate4 (
-    .a (net4),
-    .b (net5),
-    .out (net6)
-  );
-  not_cell gate5 (
-    .in (net7),
-    .out (net5)
-  );
-  buffer_cell gate6 (
-
-  );
-  mux_cell mux1 (
-    .a (net8),
-    .b (net9),
-    .sel (net10),
-    .out (net11)
-  );
-  dff_cell flipflop1 (
-
-  );
-  mux_cell mux2 (
-    .a (net12),
-    .b (net13),
-    .sel (net10),
-    .out (net14)
-  );
-  mux_cell mux3 (
-    .a (net15),
-    .b (net16),
-    .sel (net10),
-    .out (net17)
-  );
-  mux_cell mux4 (
-    .a (net18),
-    .b (net19),
-    .sel (net10),
-    .out (net20)
-  );
-  and_cell gate7 (
-    .a (net22),
-    .b (net23),
-    .out (net4)
-  );
-endmodule

diff --git a/verilog/rtl/wokwi_diagram.json b/verilog/rtl/wokwi_diagram.json
deleted file mode 100644
index 357c5bd..0000000
--- a/verilog/rtl/wokwi_diagram.json
+++ /dev/null

@@ -1,167 +0,0 @@
-{
-  "version": 1,
-  "author": "Uri Shaked",
-  "editor": "wokwi",
-  "parts": [
-    {
-      "type": "wokwi-dip-switch-8",
-      "id": "sw1",
-      "top": 31.3,
-      "left": -45.8,
-      "rotate": 90,
-      "attrs": {}
-    },
-    { "type": "wokwi-vcc", "id": "pwr1", "top": -124.04, "left": -134.4, "attrs": {} },
-    { "type": "wokwi-gnd", "id": "gnd1", "top": 67.2, "left": 681, "attrs": {} },
-    { "type": "wokwi-gate-and-2", "id": "gate1", "top": -211.2, "left": -96, "attrs": {} },
-    { "type": "wokwi-gate-or-2", "id": "gate2", "top": -276.8, "left": 148.67, "attrs": {} },
-    { "type": "wokwi-gate-xor-2", "id": "gate3", "top": -276.8, "left": 13.2, "attrs": {} },
-    { "type": "wokwi-gate-nand-2", "id": "gate4", "top": 364.8, "left": 201.6, "attrs": {} },
-    { "type": "wokwi-gate-not", "id": "gate5", "top": 393.6, "left": 96, "attrs": {} },
-    { "type": "wokwi-gate-buffer", "id": "gate6", "top": -181.2, "left": 55.2, "attrs": {} },
-    { "type": "wokwi-mux-2", "id": "mux1", "top": -67.2, "left": 86.4, "attrs": {} },
-    {
-      "type": "wokwi-flip-flop-d",
-      "id": "flipflop1",
-      "top": -323.6,
-      "left": -244.13,
-      "attrs": {}
-    },
-    {
-      "type": "wokwi-clock-generator",
-      "id": "clkgen1",
-      "top": -256.93,
-      "left": -250,
-      "attrs": {}
-    },
-    {
-      "type": "wokwi-led-bar-graph",
-      "id": "bargraph1",
-      "top": -62.4,
-      "left": 600,
-      "attrs": { "color": "lime" }
-    },
-    { "type": "wokwi-vcc", "id": "pwr2", "top": -124.04, "left": 57.6, "attrs": {} },
-    { "type": "wokwi-vcc", "id": "pwr3", "top": -268.04, "left": -28.8, "attrs": {} },
-    { "type": "wokwi-gnd", "id": "gnd2", "top": -18.71, "left": 76.2, "attrs": {} },
-    { "type": "wokwi-mux-2", "id": "mux2", "top": -9.6, "left": 172.8, "attrs": {} },
-    { "type": "wokwi-mux-2", "id": "mux3", "top": 57.6, "left": 240, "attrs": {} },
-    { "type": "wokwi-mux-2", "id": "mux4", "top": 144, "left": 326.4, "attrs": {} },
-    { "type": "wokwi-vcc", "id": "pwr4", "top": 19.96, "left": 230.4, "attrs": {} },
-    { "type": "wokwi-vcc", "id": "pwr5", "top": 165.84, "left": 317, "rotate": 180, "attrs": {} },
-    { "type": "wokwi-vcc", "id": "pwr6", "top": -37.64, "left": 163.2, "attrs": {} },
-    { "type": "wokwi-gnd", "id": "gnd3", "top": 28.8, "left": 162.6, "attrs": {} },
-    { "type": "wokwi-gnd", "id": "gnd4", "top": 96, "left": 229.8, "attrs": {} },
-    { "type": "wokwi-gnd", "id": "gnd5", "top": 101, "left": 325.2, "rotate": 180, "attrs": {} },
-    {
-      "type": "wokwi-dip-switch-8",
-      "id": "sw2",
-      "top": 342.76,
-      "left": -65.04,
-      "rotate": 90,
-      "attrs": {}
-    },
-    { "type": "wokwi-vcc", "id": "pwr7", "top": 298.36, "left": -67.2, "attrs": {} },
-    { "type": "wokwi-gate-and-2", "id": "gate7", "top": 326.4, "left": 96, "attrs": {} },
-    {
-      "type": "wokwi-resistor",
-      "id": "r1",
-      "top": -27.98,
-      "left": 9.21,
-      "rotate": 90,
-      "attrs": { "value": "1000" }
-    },
-    {
-      "type": "wokwi-gnd",
-      "id": "gnd7",
-      "top": -95.97,
-      "left": -1.54,
-      "rotate": 180,
-      "attrs": {}
-    },
-    {
-      "type": "wokwi-resistor",
-      "id": "r2",
-      "top": 278.2,
-      "left": -2.2,
-      "rotate": 90,
-      "attrs": { "value": "1000" }
-    },
-    {
-      "type": "wokwi-resistor",
-      "id": "r3",
-      "top": 278.2,
-      "left": 26.6,
-      "rotate": 90,
-      "attrs": { "value": "1000" }
-    },
-    {
-      "type": "wokwi-resistor",
-      "id": "r4",
-      "top": 278.2,
-      "left": 55.4,
-      "rotate": 90,
-      "attrs": { "value": "1000" }
-    },
-    { "type": "wokwi-gnd", "id": "gnd8", "top": 216.2, "left": 47.8, "rotate": 180, "attrs": {} }
-  ],
-  "connections": [
-    [ "mux1:OUT", "bargraph1:A1", "green", [ "v0" ] ],
-    [ "pwr1:VCC", "sw1:1a", "red", [ "v0" ] ],
-    [ "pwr2:VCC", "mux1:A", "red", [ "v0" ] ],
-    [ "mux1:B", "gnd2:GND", "green", [ "h0" ] ],
-    [ "bargraph1:C1", "bargraph1:C2", "green", [ "v0" ] ],
-    [ "bargraph1:C2", "bargraph1:C3", "green", [ "h0" ] ],
-    [ "bargraph1:C3", "bargraph1:C4", "green", [ "h0" ] ],
-    [ "bargraph1:C4", "bargraph1:C5", "green", [ "h0" ] ],
-    [ "bargraph1:C5", "bargraph1:C6", "green", [ "h0" ] ],
-    [ "bargraph1:C6", "bargraph1:C7", "green", [ "h0" ] ],
-    [ "bargraph1:C7", "bargraph1:C8", "green", [ "h0" ] ],
-    [ "bargraph1:C8", "bargraph1:C9", "green", [ "h0" ] ],
-    [ "bargraph1:C10", "bargraph1:C9", "green", [ "h0" ] ],
-    [ "bargraph1:C10", "gnd1:GND", "green", [ "h0" ] ],
-    [ "sw1:1b", "mux1:SEL", "green", [ "h0" ] ],
-    [ "pwr6:VCC", "mux2:A", "red", [ "v0" ] ],
-    [ "gnd3:GND", "mux2:B", "black", [ "v0" ] ],
-    [ "pwr4:VCC", "mux3:A", "red", [ "v0" ] ],
-    [ "gnd4:GND", "mux3:B", "black", [ "v0" ] ],
-    [ "gnd5:GND", "mux4:A", "black", [ "v0" ] ],
-    [ "pwr5:VCC", "mux4:B", "red", [ "v0" ] ],
-    [ "sw1:1b", "mux2:SEL", "green", [ "h0" ] ],
-    [ "sw1:1b", "mux3:SEL", "green", [ "h0" ] ],
-    [ "sw1:1b", "mux4:SEL", "green", [ "h0" ] ],
-    [ "mux2:OUT", "bargraph1:A2", "green", [ "v0" ] ],
-    [ "mux3:OUT", "bargraph1:A3", "green", [ "v0" ] ],
-    [ "mux4:OUT", "bargraph1:A4", "green", [ "v0" ] ],
-    [ "pwr7:VCC", "sw2:1a", "red", [ "v0" ] ],
-    [ "sw1:1a", "sw1:2a", "green", [ "h0" ] ],
-    [ "sw1:2a", "sw1:3a", "green", [ "h0" ] ],
-    [ "sw2:1a", "sw2:2a", "green", [ "h0" ] ],
-    [ "sw2:2a", "sw2:3a", "green", [ "h0" ] ],
-    [ "sw2:3a", "sw2:4a", "green", [ "h0" ] ],
-    [ "sw2:4a", "sw2:5a", "green", [ "h0" ] ],
-    [ "sw2:5a", "sw2:6a", "green", [ "h0" ] ],
-    [ "sw2:6a", "sw2:7a", "green", [ "h0" ] ],
-    [ "sw2:7a", "sw2:8a", "green", [ "h0" ] ],
-    [ "sw2:1b", "gate7:A", "green", [ "h0" ] ],
-    [ "sw2:2b", "gate7:B", "green", [ "h0" ] ],
-    [ "sw2:3b", "gate5:IN", "green", [ "h0" ] ],
-    [ "gate5:OUT", "gate4:B", "green", [ "v0" ] ],
-    [ "gate7:OUT", "gate4:A", "green", [ "v0" ] ],
-    [ "r1:2", "sw1:1b", "green", [ "h1.74", "v16.62" ] ],
-    [ "gnd7:GND", "r1:1", "black", [ "v0" ] ],
-    [ "r2:1", "gnd8:GND", "green", [ "h0" ] ],
-    [ "r4:1", "r3:1", "green", [ "h0" ] ],
-    [ "r3:1", "r2:1", "green", [ "h0" ] ],
-    [
-      "gate1:A",
-      "clkgen1:CLK",
-      "green",
-      [ "h0", "v-48", "h-28.8", "v67.2", "h-57.6", "v38.4", "h-28.8", "v-57.6", "h28.8" ]
-    ],
-    [ "r2:2", "sw2:1b", "green", [ "h-9.6", "v17.8" ] ],
-    [ "r3:2", "sw2:2b", "green", [ "h-9.6", "v27.4" ] ],
-    [ "r4:2", "sw2:3b", "green", [ "h-9.6", "v27.4" ] ],
-    [ "bargraph1:A8", "gate4:OUT", "green", [ "h-37.9", "v305.65", "h-269.3" ] ]
-  ]
-}
\ No newline at end of file