rtl: fix typo
diff --git a/info.yaml b/info.yaml index 1d18a3a..ffd2ce2 100644 --- a/info.yaml +++ b/info.yaml
@@ -9,6 +9,8 @@ - verilog/blocks/serv/rtl/serv_synth_wrapper.v - verilog/blocks/serv/rtl/serv_mem_if.v - verilog/blocks/serv/rtl/serv_rf_if.v + - verilog/blocks/serv/rtl/serv_rf_top.v + - verilog/blocks/serv/rtl/serv_rf_ram.v - verilog/blocks/serv/rtl/serv_rf_ram_if.v - verilog/blocks/serv/rtl/serv_alu.v - verilog/blocks/serv/rtl/serv_ctrl.v @@ -16,6 +18,8 @@ - verilog/blocks/serv/rtl/serv_bufreg.v - verilog/blocks/serv/rtl/serv_immdec.v - verilog/blocks/serv/rtl/serv_decode.v + - verilog/blocks/serv/rtl/serv_compdec.v + - verilog/blocks/serv/rtl/serv_aligner.v - verilog/blocks/serv/rtl/serv_state.v - verilog/blocks/serv/rtl/serv_csr.v - verilog/blocks/serv/servant/servant_arbiter.v
diff --git a/openlane/tiny_user_project/config.json b/openlane/tiny_user_project/config.json index 381fb19..43b225c 100644 --- a/openlane/tiny_user_project/config.json +++ b/openlane/tiny_user_project/config.json
@@ -8,6 +8,8 @@ "dir::../../verilog/blocks/serv/rtl/serv_synth_wrapper.v", "dir::../../verilog/blocks/serv/rtl/serv_mem_if.v", "dir::../../verilog/blocks/serv/rtl/serv_rf_if.v", + "dir::../../verilog/blocks/serv/rtl/serv_rf_top.v", + "dir::../../verilog/blocks/serv/rtl/serv_rf_ram.v", "dir::../../verilog/blocks/serv/rtl/serv_rf_ram_if.v", "dir::../../verilog/blocks/serv/rtl/serv_alu.v", "dir::../../verilog/blocks/serv/rtl/serv_ctrl.v", @@ -15,6 +17,8 @@ "dir::../../verilog/blocks/serv/rtl/serv_bufreg.v", "dir::../../verilog/blocks/serv/rtl/serv_immdec.v", "dir::../../verilog/blocks/serv/rtl/serv_decode.v", + "dir::../../verilog/blocks/serv/rtl/serv_compdec.v", + "dir::../../verilog/blocks/serv/rtl/serv_aligner.v", "dir::../../verilog/blocks/serv/rtl/serv_state.v", "dir::../../verilog/blocks/serv/rtl/serv_csr.v", "dir::../../verilog/blocks/serv/servant/servant_arbiter.v", @@ -29,7 +33,7 @@ "FP_SIZING": "absolute", "DIE_AREA": "0 0 600 680", "PL_BASIC_PLACEMENT": 0, - "PL_TARGET_DENSITY": 0.55, + "PL_TARGET_DENSITY": 0.70, "SYNTH_USE_PG_PINS_DEFINES": "USE_POWER_PINS", "VDD_NETS": [ "vdd"
diff --git a/verilog/rtl/scanchain.v b/verilog/rtl/scanchain.v index ea7ff4e..8f62ea3 100644 --- a/verilog/rtl/scanchain.v +++ b/verilog/rtl/scanchain.v
@@ -6,11 +6,9 @@ input wire clk_in, input wire data_in, input wire scan_select_in, - input wire latch_enable_in, output wire clk_out, output wire data_out, output wire scan_select_out, - output wire latch_enable_out, // io, names from point of view of the user module input wire [SCAN_LENGTH-1:0] module_data_out, @@ -21,19 +19,15 @@ // Looking at results from multiple projects the buffering is a bit // inconsistent. So instead, we ensure at least clk buf wire clk; - always @(*) begin - clk <= clk_in; - end + assign clk = clk_in; // output buffers // Same as for input, to try and be more consistent, we make our own wire data_out_i; - always @(*) begin - clk_out <= clk; - data_out <= data_out_i; - scan_select_out <= scan_select_in; - latch_enable_out <= latch_enable_in; - end + + assign clk_out = clk; + assign data_out = data_out_i; + assign scan_select_out = scan_select_in; // wires needed
diff --git a/verilog/rtl/top.v b/verilog/rtl/top.v index a5bd65e..0095ec5 100644 --- a/verilog/rtl/top.v +++ b/verilog/rtl/top.v
@@ -11,7 +11,7 @@ wire data = io_in[2]; wire scan_select = io_in[3]; - wire serv_clk = io_in[5]; + wire serv_clk = io_in[4]; wire timer_irq; @@ -28,14 +28,6 @@ wire wb_dbus_cyc; wire wb_dbus_ack; - wire [31:0] wb_dmem_adr; - wire [31:0] wb_dmem_dat; - wire [3:0] wb_dmem_sel; - wire [31:0] wb_dmem_rdt; - wire wb_dmem_we; - wire wb_dmem_cyc; - wire wb_dmem_ack; - wire [31:0] wb_mem_adr; wire [31:0] wb_mem_dat; wire [3:0] wb_mem_sel; @@ -69,32 +61,34 @@ -module serv_rf_top - #(.RESET_PC(32'd0), + serv_rf_top #( + .RESET_PC(32'd0), .COMPRESSED(1), .ALIGN(1), .MDU(0), .PRE_REGISTER(1), - .RESET_STRATEGY = "MINI", + .RESET_STRATEGY("MINI"), .WITH_CSR(1), - .RF_WIDTH(2), - ( - input wire serv_clk, - input wire i_rst, - input wire i_timer_irq, + .RF_WIDTH(2)) + u_cpu + ( + .clk (serv_clk), + .i_rst (reset), + .i_timer_irq (timer_irq), - output wire [31:0] o_ibus_adr, - output wire o_ibus_cyc, - input wire [31:0] i_ibus_rdt, - input wire i_ibus_ack, - output wire [31:0] o_dbus_adr, - output wire [31:0] o_dbus_dat, - output wire [3:0] o_dbus_sel, - output wire o_dbus_we , - output wire o_dbus_cyc, - input wire [31:0] i_dbus_rdt, - input wire i_dbus_ack, - ); + .o_ibus_adr (wb_ibus_adr), + .o_ibus_cyc (wb_ibus_cyc), + .i_ibus_rdt (wb_ibus_rdt), + .i_ibus_ack (wb_ibus_ack), + + .o_dbus_adr (wb_dbus_adr), + .o_dbus_dat (wb_dbus_dat), + .o_dbus_sel (wb_dbus_sel), + .o_dbus_we (wb_dbus_we), + .o_dbus_cyc (wb_dbus_cyc), + .i_dbus_rdt (wb_dbus_rdt), + .i_dbus_ack (wb_dbus_ack) + ); scanchain_local #(