rtl: update serv to include internal rf

info.yaml

diff --git a/info.yaml b/info.yaml
index 839c192..1d18a3a 100644
--- a/info.yaml
+++ b/info.yaml
@@ -42,21 +42,12 @@
   clock_hz:     0       # Clock frequency in Hz (if required) we are expecting max clock frequency to be ~6khz. Provided on input 0.
   picture:      "tbd"      # relative path to a picture in your repository
   inputs:               # a description of what the inputs do
-    - clock
+    - clk
     - reset
-    - none
-    - none
-    - none
-    - none
-    - none
-    - none
+    - data
+    - scan_select
+    - serv_clk
   outputs:
-    - segment a         # a description of what the outputs do
-    - segment b
-    - segment c
-    - segment d
-    - segment e
-    - segment f
-    - segment g
-    - none
+    - clk out         # a description of what the outputs do
+    - data out
 

verilog/rtl/top.v

diff --git a/verilog/rtl/top.v b/verilog/rtl/top.v
index 085c991..a5bd65e 100644
--- a/verilog/rtl/top.v
+++ b/verilog/rtl/top.v
@@ -7,35 +7,14 @@
   );
 
   wire clk =   io_in[0];
-  wire reset = io_in[7];
+  wire reset = io_in[1];
 
-  wire data =         io_in[4];
-  wire scan_select =  io_in[5];
-  wire latch_enable = io_in[6];
-  wire serv_clk =     io_in[7];
+  wire data =         io_in[2];
+  wire scan_select =  io_in[3];
+  wire serv_clk =     io_in[5];
 
   wire timer_irq;
 
-  parameter reset_strategy = "MINI";
-  parameter sim = 0;
-  parameter with_csr = 0;
-  parameter [0:0] compress = 0;
-  parameter [0:0] align = 0;
-
-  wire [4+with_csr:0] wreg0;
-  wire [4+with_csr:0] wreg1;
-  wire [4+with_csr:0] rreg0;
-  wire [4+with_csr:0] rreg1;
-  wire 	      rf_wreq;
-  wire 	      rf_rreq;
-  wire 	      wen0;
-  wire 	      wen1;
-  wire 	      wdata0;
-  wire 	      wdata1;
-  wire 	      rf_ready;
-  wire 	      rdata0;
-  wire 	      rdata1;
-
   wire [31:0] 	wb_ibus_adr;
   wire [31:0] 	wb_ibus_rdt;
   wire 	wb_ibus_cyc;
@@ -65,12 +44,6 @@
   wire 	wb_mem_cyc;
   wire 	wb_mem_ack;
 
-  wire 	wb_gpio_dat;
-  wire 	wb_gpio_we;
-  wire 	wb_gpio_cyc;
-  wire 	wb_gpio_rdt;
-
-
   servant_arbiter u_arbiter (
     .i_wb_cpu_dbus_adr (wb_dbus_adr),
     .i_wb_cpu_dbus_dat (wb_dbus_dat),
@@ -95,50 +68,37 @@
   );
 
 
-  serv_top #(
-    .RESET_PC (32'h0000_0000),
+
+module serv_rf_top
+  #(.RESET_PC(32'd0),
+    .COMPRESSED(1),
+    .ALIGN(1),
+    .MDU(0),
     .PRE_REGISTER(1),
-    .RESET_STRATEGY (reset_strategy),
-    .WITH_CSR (with_csr),
-    .COMPRESSED(compress),
-    .ALIGN(align))
-  cpu
-  (
-    .clk          (serv_clk),
-    .i_rst        (reset),
-    .i_timer_irq  (timer_irq),
+    .RESET_STRATEGY = "MINI",
+    .WITH_CSR(1),
+    .RF_WIDTH(2),
+	(
+   input wire 	      serv_clk,
+   input wire 	      i_rst,
+   input wire 	      i_timer_irq,
 
-    .o_rf_rreq    (rf_rreq),
-    .o_rf_wreq    (rf_wreq),
-    .i_rf_ready   (rf_ready),
-    .o_wreg0      (wreg0),
-    .o_wreg1      (wreg1),
-    .o_wen0       (wen0),
-    .o_wen1       (wen1),
-    .o_wdata0     (wdata0),
-    .o_wdata1     (wdata1),
-    .o_rreg0      (rreg0),
-    .o_rreg1      (rreg1),
-    .i_rdata0     (rdata0),
-    .i_rdata1     (rdata1),
-
-    .o_ibus_adr   (wb_ibus_adr),
-    .o_ibus_cyc   (wb_ibus_cyc),
-    .i_ibus_rdt   (wb_ibus_rdt),
-    .i_ibus_ack   (wb_ibus_ack),
-
-    .o_dbus_adr   (wb_dbus_adr),
-    .o_dbus_dat   (wb_dbus_dat),
-    .o_dbus_sel   (wb_dbus_sel),
-    .o_dbus_we    (wb_dbus_we),
-    .o_dbus_cyc   (wb_dbus_cyc),
-    .i_dbus_rdt   (wb_dbus_rdt),
-    .i_dbus_ack   (wb_dbus_ack)
-  );
+   output wire [31:0] o_ibus_adr,
+   output wire 	      o_ibus_cyc,
+   input wire [31:0]  i_ibus_rdt,
+   input wire 	      i_ibus_ack,
+   output wire [31:0] o_dbus_adr,
+   output wire [31:0] o_dbus_dat,
+   output wire [3:0]  o_dbus_sel,
+   output wire 	      o_dbus_we ,
+   output wire 	      o_dbus_cyc,
+   input wire [31:0]  i_dbus_rdt,
+   input wire 	      i_dbus_ack,
+   );
 
 
   scanchain_local #(
-    .SCAN_LENGTH(96))
+    .SCAN_LENGTH(70))
   u_scanchain_local
   (
     // Inputs from TinyTapeout scanchain to our internal scanchain
@@ -149,7 +109,7 @@
     // Pass all signals out from our internal scanchain, only really need data
     .clk_out         (io_out[0]),
     .data_out        (io_out[1]),
-    .scan_select_out (io_out[2]),
+    .scan_select_out (),
 
     // data
     .module_data_out ({
@@ -158,27 +118,13 @@
       wb_mem_dat,         // 32
       wb_mem_sel,         // 4
       wb_mem_we,          // 1
-      wb_mem_cyc,         // 1
-      // RF interface
-      rf_wreq,            // 1
-      rf_rreq,            // 1
-      wreg0,              // 5
-      wreg1,              // 5
-      wen0,               // 1
-      wen1,               // 1
-      wdata0,             // 1
-      wdata1,             // 1
-      rreg0,              // 5
-      rreg1}),            // 5
-
+      wb_mem_cyc}),       // 1
+     
     .module_data_in  ({
       // Bus interface
       wb_mem_rdt,         // 32
       wb_mem_ack,         // 1
-      timer_irq,          // 1
-      rf_ready,           // 1
-      rdata0,             // 1
-      rdata1})            // 1
+      timer_irq})         // 1
   );
 
 endmodule