openlane/tiny_user_project/config.json

{
    "DESIGN_NAME": "tiny_user_project",
    "DESIGN_IS_CORE": 0,
    "VERILOG_FILES": [
        "dir::../../verilog/rtl/top.v",
        "dir::../../verilog/rtl/scanchain.v",
        "dir::../../verilog/blocks/serv/rtl/serv_top.v",
        "dir::../../verilog/blocks/serv/rtl/serv_synth_wrapper.v",
        "dir::../../verilog/blocks/serv/rtl/serv_mem_if.v",
        "dir::../../verilog/blocks/serv/rtl/serv_rf_if.v",
        "dir::../../verilog/blocks/serv/rtl/serv_rf_top.v",
        "dir::../../verilog/blocks/serv/rtl/serv_rf_ram.v",
        "dir::../../verilog/blocks/serv/rtl/serv_rf_ram_if.v",
        "dir::../../verilog/blocks/serv/rtl/serv_alu.v",
        "dir::../../verilog/blocks/serv/rtl/serv_ctrl.v",
        "dir::../../verilog/blocks/serv/rtl/serv_bufreg2.v",
        "dir::../../verilog/blocks/serv/rtl/serv_bufreg.v",
        "dir::../../verilog/blocks/serv/rtl/serv_immdec.v",
        "dir::../../verilog/blocks/serv/rtl/serv_decode.v",
        "dir::../../verilog/blocks/serv/rtl/serv_compdec.v",
        "dir::../../verilog/blocks/serv/rtl/serv_aligner.v",
        "dir::../../verilog/blocks/serv/rtl/serv_state.v",
        "dir::../../verilog/blocks/serv/rtl/serv_csr.v",
        "dir::../../verilog/blocks/serv/servant/servant_arbiter.v",
        "dir::../../verilog/blocks/serv/servant/servant_mux.v",
        "dir::../../verilog/blocks/serv/servant/servant_gpio.v",
        "dir::../../verilog/rtl/defines.v",
        "dir::../../verilog/rtl/tiny_user_project.v"
    ],
    "CLOCK_PERIOD": 24,
    "CLOCK_PORT": "",
    "CLOCK_NET": "",
    "FP_SIZING": "absolute",
    "DIE_AREA": "0 0 690 800",
    "PL_BASIC_PLACEMENT": 0,
    "PL_TARGET_DENSITY": 0.55,
    "SYNTH_USE_PG_PINS_DEFINES": "USE_POWER_PINS",
    "VDD_NETS": [
        "vdd"
    ],
    "GND_NETS": [
        "vss"
    ],
    "DIODE_INSERTION_STRATEGY": 4,
    "RUN_CVC": 1,
    "RUN_KLAYOUT_XOR": 0,
    "RUN_KLAYOUT_DRC": 0,
    "SYNTH_READ_BLACKBOX_LIB": 0,
    "pdk::gf180mcuC": {
        "STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0",
        "RT_MAX_LAYER": "Metal4",
        "SYNTH_MAX_FANOUT": 4
    }
}