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foss-eda-tools/third_party/shuttle/gf180mcu/mpw-000/slot-001/6254d133ca6979a493f0d12495f758135423bc22^!/.
commit
6254d133ca6979a493f0d12495f758135423bc22
[log]
author
Greg Davill <greg.davill@gmail.com>
Sun Dec 04 15:31:55 2022 +1030
committer
Greg Davill <greg.davill@gmail.com>
Sun Dec 04 15:31:55 2022 +1030
tree
b1bf2e0537e68bcaddf99bf1ab731d6fcace76dc
parent
ed545f83e62462d10e964a4f2af2d5a0cf5df00f [diff]
cfg: Experimenting with SRAM IP config

diff --git a/openlane/tiny_user_project/config.tcl b/openlane/tiny_user_project/config.tcl
index f09173b..8a33cad 100644
--- a/openlane/tiny_user_project/config.tcl
+++ b/openlane/tiny_user_project/config.tcl

@@ -20,42 +20,43 @@
 
 set ::env(PDK) "gf180mcuC"
 set ::env(STD_CELL_LIBRARY) "gf180mcu_fd_sc_mcu7t5v0"
+set ::env(RT_MAX_LAYER) "Metal4"
 
 set ::env(RUN_KLAYOUT) 		0
-set ::env(CLOCK_TREE_SYNTH) 0
+set ::env(CLOCK_TREE_SYNTH) 1
 set ::env(CLOCK_PORT) 		{io_in[8]}
 #set ::env(CLOCK_NET) ""
-set ::env(CLOCK_PERIOD) 	"45"
+set ::env(CLOCK_PERIOD) 	50
+set ::env(SYNTH_MAX_FANOUT) 16
 
 set ::env(FP_IO_HLENGTH) 2
 set ::env(FP_IO_VLENGTH) 2
 
 ## Floorplan
 set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 700 500"
-
+set ::env(DIE_AREA) "0 0 800 700"
 
 ## Placement
 set ::env(PL_BASIC_PLACEMENT) 0
 set ::env(PL_TARGET_DENSITY) 0.55
 
-set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 1
+# Enable all optimizations
+set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
 set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 1
+set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) 1
 
-## Diode Insertion
-set ::env(DIODE_INSERTION_STRATEGY) 		4
+# Diode insertion strategy number 4 for gf-180mcu
+set ::env(DIODE_INSERTION_STRATEGY) 4
 
-# connect to first digital rails
-set ::env(VDD_NETS) [list {VDD}]
-set ::env(GND_NETS) [list {VSS}]
+set ::env(VDD_NETS) [list {vdd}]
+set ::env(GND_NETS) [list {vss}]
 
-
-# save some time
-set ::env(RUN_KLAYOUT_XOR) 0
-set ::env(RUN_KLAYOUT_DRC) 0
-
-# don't put clock buffers on the outputs
-set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 0
+## Internal Macros
+### Macro PDN Connections
+set ::env(FP_PDN_MACRO_HOOKS) "\
+	mod.u_cpu.rf_ram.RAM0 vdd vss vdd vss"
+set ::env(FP_PDN_MACROS) "\
+	mod.u_cpu.rf_ram.RAM0"
     
 ## Internal Macros
 set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro.cfg
@@ -91,8 +92,8 @@
     $::env(DESIGN_DIR)/blocks/serv/servant/servant_gpio.v"
 
 set ::env(VERILOG_FILES_BLACKBOX) "\
-	$::env(DESIGN_DIR)/rtl/gf180mcu_fd_sc_mcu7t5v0_bb.v \
-	$::env(PDK_ROOT)/$::env(PDK)/libs.ref/gf180mcu_fd_ip_sram/verilog/gf180mcu_fd_ip_sram__sram256x8m8wm1.v"
+	$::env(DESIGN_DIR)/rtl/gf180mcu_fd_sc_mcu7t5v0_bb.v"
+#	$::env(PDK_ROOT)/$::env(PDK)/libs.ref/gf180mcu_fd_ip_sram/verilog/gf180mcu_fd_ip_sram__sram256x8m8wm1.v"
 
 set ::env(EXTRA_LEFS) "\
 	$::env(PDK_ROOT)/$::env(PDK)/libs.ref/gf180mcu_fd_ip_sram/lef/gf180mcu_fd_ip_sram__sram256x8m8wm1.lef"
@@ -101,16 +102,26 @@
 set ::env(EXTRA_LIBS) "\
     $::env(PDK_ROOT)/$::env(PDK)/libs.ref/gf180mcu_fd_ip_sram/liberty/gf180mcu_fd_ip_sram__sram256x8m8wm1__tt_025C_1v80.lib"
 
-set ::env(FP_PDN_MACRO_HOOKS) "\
-  u_cpu.rf_ram.RAM0 VDD VSS VDD VSS
-  "
+set ::env(QUIT_ON_MISMATCHES) 0
 
-#set ::env(PDN_CFG) $script_dir/pdn.tcl
+## PDN
+set ::env(PDN_CFG) $script_dir/pdn.tcl
+set ::env(FP_PDN_ENABLE_MACROS_GRID) 1
 set ::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS) 1
 
+## PDN
+set ::env(FP_PDN_VPITCH) 30
+#set ::env(FP_PDN_HPITCH) 30
+
+set ::env(FP_PDN_VWIDTH) 3
+#set ::env(FP_PDN_CORE_RING_VWIDTH) 1.6
+
 ## LVS
 set ::env(MAGIC_DRC_USE_GDS) 0
 set ::env(RUN_MAGIC_DRC) 0
 set ::env(QUIT_ON_MAGIC_DRC) 0
 
+set ::env(RUN_CVC) 0
+
+# Temporary ignore
 set ::env(QUIT_ON_LVS_ERROR) 0
\ No newline at end of file

diff --git a/openlane/tiny_user_project/macro.cfg b/openlane/tiny_user_project/macro.cfg
index ac06333..2a86b9f 100644
--- a/openlane/tiny_user_project/macro.cfg
+++ b/openlane/tiny_user_project/macro.cfg

@@ -1 +1 @@
-mod.u_cpu.rf_ram.RAM0 50 50 FS
+mod.u_cpu.rf_ram.RAM0 120 120 W

diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index d4e4d14..4a3872c 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl

@@ -83,5 +83,13 @@
 set ::env(RUN_TAP_DECAP_INSERTION) 0
 set ::env(CLOCK_TREE_SYNTH) 0
 
+## DRC skips due to SRAM IP
+set ::env(MAGIC_DRC_USE_GDS) 0
+set ::env(RUN_MAGIC_DRC) 0
+set ::env(QUIT_ON_MAGIC_DRC) 0
+
+# Temporary ignore
+set ::env(QUIT_ON_LVS_ERROR) 0
+
 # YOU ARE NOT ALLOWED TO CHANGE ANY VARIABLES DEFINED IN THE FIXED WRAPPER CFGS 
 source $::env(DESIGN_DIR)/fixed_dont_change/fixed_wrapper_cfgs.tcl

diff --git a/verilog/rtl/gf180mcu_fd_sc_mcu7t5v0_bb.v b/verilog/rtl/gf180mcu_fd_sc_mcu7t5v0_bb.v
index 2a0fbda..e1546cb 100644
--- a/verilog/rtl/gf180mcu_fd_sc_mcu7t5v0_bb.v
+++ b/verilog/rtl/gf180mcu_fd_sc_mcu7t5v0_bb.v

@@ -13,7 +13,7 @@
 // See the License for the specific language governing permissions and
 // limitations under the License.
 
-
+(*blackbox*)
 module gf180mcu_fd_sc_mcu7t5v0__sdffq_1( SE, SI, D, CLK, Q, VDD, VSS );
 input CLK, D, SE, SI;
 inout VDD, VSS;
@@ -21,27 +21,46 @@
 reg notifier;
 endmodule
 
+(*blackbox*)
 module gf180mcu_fd_sc_mcu7t5v0__buf_1( I, Z, VDD, VSS );
 input I;
 inout VDD, VSS;
 output Z;
 endmodule
 
+(*blackbox*)
 module gf180mcu_fd_sc_mcu7t5v0__buf_2( I, Z, VDD, VSS );
 input I;
 inout VDD, VSS;
 output Z;
 endmodule
 
+(*blackbox*)
 module gf180mcu_fd_sc_mcu7t5v0__buf_4( I, Z, VDD, VSS );
 input I;
 inout VDD, VSS;
 output Z;
 endmodule
 
+(*blackbox*)
 module gf180mcu_fd_sc_mcu7t5v0__dffnq_1( CLKN, D, Q, VDD, VSS );
 input CLKN, D;
 inout VDD, VSS;
 output Q;
 reg notifier;
 endmodule
+
+(*blackbox*)
+module gf180mcu_fd_ip_sram__sram256x8m8wm1 (
+input           CLK,
+input           CEN,    //Chip Enable
+input           GWEN,   //Global Write Enable
+input   [7:0]  	WEN,    //Write Enable
+input   [7:0]   A,
+input   [7:0]  	D,
+output	[7:0]	Q,
+inout		VDD,
+inout		VSS
+);
+
+endmodule
\ No newline at end of file

diff --git a/verilog/rtl/serv_rf_ram_gf180.v b/verilog/rtl/serv_rf_ram_gf180.v
index 653eaa2..af0a910 100644
--- a/verilog/rtl/serv_rf_ram_gf180.v
+++ b/verilog/rtl/serv_rf_ram_gf180.v

@@ -1,5 +1,5 @@
 module serv_rf_ram
-  #(parameter width=0,
+  #(parameter width=8,
     parameter csr_regs=4,
     parameter depth=32*(32+csr_regs)/width)
    (input wire i_clk,
@@ -9,22 +9,22 @@
     input wire [$clog2(depth)-1:0] i_raddr,
     output wire [width-1:0] 	   o_rdata);
 
-//   reg [width-1:0] 		   memory [0:depth-1];
+  wire [width-1:0] 		 data ;
+  reg [width-1:0] 		   rdata ;
 
-   wire [width-1:0] 		 data ;
-   reg [width-1:0] 		   rdata ;
-
+  wire [$clog2(depth)-1:0] addr;
+  assign addr = i_wen ? i_waddr : i_raddr;
 
 gf180mcu_fd_ip_sram__sram256x8m8wm1 RAM0 (
 	.CLK(i_clk),
 	.CEN(1'b0), // Active LOW chip enable
 	.GWEN(~i_wen), // Active LOW Write enable
 	.WEN({8{~i_wen}}), // Active LOW
-	.A(i_wen ? i_waddr : i_raddr),
+	.A(addr),
 	.D(i_wdata),
 	.Q(data),
-	.VDD(1'b1),
-	.VSS(1'b0)
+	.VDD(),
+	.VSS()
 );
 
    /* Reads from reg x0 needs to return 0