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foss-eda-tools/third_party/shuttle/gf180mcu/mpw-000/slot-001/599786a0e8b449ae0ea3ea6bb7d0b96bf1e2b124/./sdf/serv_0.sdf
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(COND A1===1'b1 && A2===1'b0
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(SETUP (negedge D) (posedge CLK) (0.133:0.138:0.142))
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(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.215:0.215:0.215))
(SETUP (negedge D) (posedge CLK) (0.239:0.239:0.239))
(HOLD (posedge D) (posedge CLK) (0.065:0.065:0.065))
(HOLD (negedge D) (posedge CLK) (0.077:0.077:0.077))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__dffq_1")
(INSTANCE _3215_)
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.916:0.916:0.916) (0.798:0.798:0.798))
)
)
(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.208:0.208:0.208))
(SETUP (negedge D) (posedge CLK) (0.236:0.236:0.236))
(HOLD (posedge D) (posedge CLK) (0.072:0.072:0.072))
(HOLD (negedge D) (posedge CLK) (0.080:0.080:0.080))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__dffq_1")
(INSTANCE _3216_)
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.010:1.010:1.010) (0.883:0.883:0.883))
)
)
(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.138:0.138:0.138))
(SETUP (negedge D) (posedge CLK) (0.164:0.164:0.164))
(HOLD (posedge D) (posedge CLK) (0.119:0.119:0.119))
(HOLD (negedge D) (posedge CLK) (0.143:0.143:0.143))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__dffq_1")
(INSTANCE _3217_)
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.983:0.983:0.983) (0.860:0.860:0.860))
)
)
(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.139:0.139:0.139))
(SETUP (negedge D) (posedge CLK) (0.152:0.152:0.152))
(HOLD (posedge D) (posedge CLK) (0.110:0.110:0.110))
(HOLD (negedge D) (posedge CLK) (0.155:0.155:0.155))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__dffq_1")
(INSTANCE _3218_)
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.887:0.887:0.887) (0.791:0.791:0.791))
)
)
(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.159:0.159:0.159))
(SETUP (negedge D) (posedge CLK) (0.273:0.273:0.273))
(HOLD (posedge D) (posedge CLK) (0.120:0.120:0.120))
(HOLD (negedge D) (posedge CLK) (0.050:0.050:0.050))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__dffq_1")
(INSTANCE _3219_)
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.276:1.276:1.276) (1.058:1.058:1.058))
)
)
(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.140:0.141:0.142))
(SETUP (negedge D) (posedge CLK) (0.235:0.241:0.248))
(HOLD (posedge D) (posedge CLK) (0.126:0.127:0.127))
(HOLD (negedge D) (posedge CLK) (0.085:0.080:0.074))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__dffq_1")
(INSTANCE _3220_)
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.976:0.976:0.976) (0.858:0.858:0.858))
)
)
(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.139:0.146:0.153))
(SETUP (negedge D) (posedge CLK) (0.169:0.273:0.378))
(HOLD (posedge D) (posedge CLK) (0.114:0.115:0.116))
(HOLD (negedge D) (posedge CLK) (0.140:0.054:-0.031))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__dffq_1")
(INSTANCE _3221_)
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.887:0.887:0.887) (0.796:0.796:0.796))
)
)
(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.128:0.134:0.139))
(SETUP (negedge D) (posedge CLK) (0.157:0.240:0.324))
(HOLD (posedge D) (posedge CLK) (0.123:0.125:0.126))
(HOLD (negedge D) (posedge CLK) (0.150:0.082:0.013))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__clkbuf_1")
(INSTANCE _3379_)
(DELAY
(ABSOLUTE
(IOPATH I Z (0.244:0.244:0.244) (0.249:0.249:0.249))
)
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__clkbuf_1")
(INSTANCE _3380_)
(DELAY
(ABSOLUTE
(IOPATH I Z (0.249:0.249:0.249) (0.252:0.252:0.252))
)
)
)
(CELL
(CELLTYPE "gf180mcu_fd_ip_sram__sram256x8m8wm1")
(INSTANCE u_cpu\.rf_ram\.RAM0)
(DELAY
(ABSOLUTE
(COND CEN== 1'b0 && GWEN== 1'b1
(IOPATH CLK Q[0] (16.433:16.433:16.433) (17.332:17.332:17.332)))
(COND CEN== 1'b0 && GWEN== 1'b1
(IOPATH CLK Q[1] (16.347:16.347:16.347) (17.261:17.261:17.261)))
(COND CEN== 1'b0 && GWEN== 1'b1
(IOPATH CLK Q[2] (16.341:16.341:16.341) (17.254:17.254:17.254)))
(COND CEN== 1'b0 && GWEN== 1'b1
(IOPATH CLK Q[3] (16.403:16.403:16.403) (17.307:17.307:17.307)))
(COND CEN== 1'b0 && GWEN== 1'b1
(IOPATH CLK Q[4] (16.428:16.428:16.428) (17.327:17.327:17.327)))
(COND CEN== 1'b0 && GWEN== 1'b1
(IOPATH CLK Q[5] (16.479:16.479:16.479) (17.369:17.369:17.369)))
(COND CEN== 1'b0 && GWEN== 1'b1
(IOPATH CLK Q[6] (16.497:16.497:16.497) (17.384:17.384:17.384)))
(COND CEN== 1'b0 && GWEN== 1'b1
(IOPATH CLK Q[7] (16.508:16.508:16.508) (17.393:17.393:17.393)))
)
)
(TIMINGCHECK
(HOLD (posedge D[0]) (posedge CLK) (0.682:0.682:0.682))
(HOLD (negedge D[0]) (posedge CLK) (1.782:1.782:1.782))
(HOLD (posedge D[1]) (posedge CLK) (0.607:0.607:0.607))
(HOLD (negedge D[1]) (posedge CLK) (1.633:1.633:1.633))
(HOLD (posedge D[2]) (posedge CLK) (0.627:0.627:0.627))
(HOLD (negedge D[2]) (posedge CLK) (1.672:1.672:1.672))
(HOLD (posedge D[3]) (posedge CLK) (0.695:0.695:0.695))
(HOLD (negedge D[3]) (posedge CLK) (1.806:1.806:1.806))
(HOLD (posedge D[4]) (posedge CLK) (0.708:0.708:0.708))
(HOLD (negedge D[4]) (posedge CLK) (1.832:1.832:1.832))
(HOLD (posedge D[5]) (posedge CLK) (0.634:0.634:0.634))
(HOLD (negedge D[5]) (posedge CLK) (1.687:1.687:1.687))
(HOLD (posedge D[6]) (posedge CLK) (0.659:0.659:0.659))
(HOLD (negedge D[6]) (posedge CLK) (1.735:1.735:1.735))
(HOLD (posedge D[7]) (posedge CLK) (0.663:0.663:0.663))
(HOLD (negedge D[7]) (posedge CLK) (1.888:1.888:1.887))
(SETUP (posedge D[0]) (posedge CLK) (2.132:2.132:2.132))
(SETUP (negedge D[0]) (posedge CLK) (0.344:0.344:0.344))
(SETUP (posedge D[1]) (posedge CLK) (2.205:2.205:2.205))
(SETUP (negedge D[1]) (posedge CLK) (0.493:0.493:0.493))
(SETUP (posedge D[2]) (posedge CLK) (2.186:2.186:2.186))
(SETUP (negedge D[2]) (posedge CLK) (0.454:0.454:0.454))
(SETUP (posedge D[3]) (posedge CLK) (2.120:2.120:2.120))
(SETUP (negedge D[3]) (posedge CLK) (0.320:0.320:0.320))
(SETUP (posedge D[4]) (posedge CLK) (2.107:2.107:2.107))
(SETUP (negedge D[4]) (posedge CLK) (0.294:0.294:0.294))
(SETUP (posedge D[5]) (posedge CLK) (2.179:2.179:2.179))
(SETUP (negedge D[5]) (posedge CLK) (0.439:0.439:0.439))
(SETUP (posedge D[6]) (posedge CLK) (2.155:2.155:2.155))
(SETUP (negedge D[6]) (posedge CLK) (0.391:0.391:0.391))
(SETUP (posedge D[7]) (posedge CLK) (2.151:2.151:2.151))
(SETUP (negedge D[7]) (posedge CLK) (0.238:0.239:0.239))
(HOLD (posedge A[0]) (posedge CLK) (1.268:1.267:1.266))
(HOLD (negedge A[0]) (posedge CLK) (1.487:1.487:1.487))
(HOLD (posedge A[1]) (posedge CLK) (1.263:1.263:1.263))
(HOLD (negedge A[1]) (posedge CLK) (1.484:1.484:1.484))
(HOLD (posedge A[2]) (posedge CLK) (1.308:1.271:1.235))
(HOLD (negedge A[2]) (posedge CLK) (1.554:1.521:1.488))
(HOLD (posedge A[3]) (posedge CLK) (1.328:1.277:1.226))
(HOLD (negedge A[3]) (posedge CLK) (1.522:1.498:1.474))
(HOLD (posedge A[4]) (posedge CLK) (1.251:1.216:1.181))
(HOLD (negedge A[4]) (posedge CLK) (1.536:1.515:1.493))
(HOLD (posedge A[5]) (posedge CLK) (1.357:1.323:1.289))
(HOLD (negedge A[5]) (posedge CLK) (1.547:1.531:1.515))
(HOLD (posedge A[6]) (posedge CLK) (1.256:1.221:1.185))
(HOLD (negedge A[6]) (posedge CLK) (1.536:1.505:1.473))
(HOLD (posedge A[7]) (posedge CLK) (1.373:1.348:1.323))
(HOLD (negedge A[7]) (posedge CLK) (1.545:1.533:1.521))
(SETUP (posedge A[0]) (posedge CLK) (1.818:1.819:1.820))
(SETUP (negedge A[0]) (posedge CLK) (2.059:2.060:2.060))
(SETUP (posedge A[1]) (posedge CLK) (1.823:1.824:1.824))
(SETUP (negedge A[1]) (posedge CLK) (2.062:2.062:2.063))
(SETUP (posedge A[2]) (posedge CLK) (1.779:1.817:1.855))
(SETUP (negedge A[2]) (posedge CLK) (1.995:2.027:2.058))
(SETUP (posedge A[3]) (posedge CLK) (1.760:1.813:1.866))
(SETUP (negedge A[3]) (posedge CLK) (2.022:2.048:2.074))
(SETUP (posedge A[4]) (posedge CLK) (1.837:1.878:1.920))
(SETUP (negedge A[4]) (posedge CLK) (2.007:2.030:2.053))
(SETUP (posedge A[5]) (posedge CLK) (1.731:1.764:1.797))
(SETUP (negedge A[5]) (posedge CLK) (2.000:2.015:2.029))
(SETUP (posedge A[6]) (posedge CLK) (1.831:1.872:1.914))
(SETUP (negedge A[6]) (posedge CLK) (2.007:2.041:2.074))
(SETUP (posedge A[7]) (posedge CLK) (1.715:1.740:1.765))
(SETUP (negedge A[7]) (posedge CLK) (2.001:2.012:2.023))
(HOLD (posedge WEN[0]) (posedge CLK) (2.447:2.447:2.447))
(HOLD (negedge WEN[0]) (posedge CLK) (1.120:1.120:1.120))
(HOLD (posedge WEN[1]) (posedge CLK) (2.488:2.488:2.488))
(HOLD (negedge WEN[1]) (posedge CLK) (1.173:1.173:1.173))
(HOLD (posedge WEN[2]) (posedge CLK) (2.488:2.488:2.488))
(HOLD (negedge WEN[2]) (posedge CLK) (1.173:1.173:1.173))
(HOLD (posedge WEN[3]) (posedge CLK) (2.313:2.313:2.313))
(HOLD (negedge WEN[3]) (posedge CLK) (1.066:1.066:1.066))
(HOLD (posedge WEN[4]) (posedge CLK) (2.331:2.331:2.331))
(HOLD (negedge WEN[4]) (posedge CLK) (1.008:1.008:1.008))
(HOLD (posedge WEN[5]) (posedge CLK) (2.331:2.331:2.331))
(HOLD (negedge WEN[5]) (posedge CLK) (1.008:1.008:1.008))
(HOLD (posedge WEN[6]) (posedge CLK) (2.331:2.331:2.331))
(HOLD (negedge WEN[6]) (posedge CLK) (1.008:1.008:1.008))
(HOLD (posedge WEN[7]) (posedge CLK) (2.331:2.331:2.331))
(HOLD (negedge WEN[7]) (posedge CLK) (1.008:1.008:1.008))
(SETUP (posedge WEN[0]) (posedge CLK) (0.000:0.000:0.000))
(SETUP (negedge WEN[0]) (posedge CLK) (0.864:0.864:0.864))
(SETUP (posedge WEN[1]) (posedge CLK) (0.000:0.000:0.000))
(SETUP (negedge WEN[1]) (posedge CLK) (0.811:0.811:0.811))
(SETUP (posedge WEN[2]) (posedge CLK) (0.000:0.000:0.000))
(SETUP (negedge WEN[2]) (posedge CLK) (0.811:0.811:0.811))
(SETUP (posedge WEN[3]) (posedge CLK) (0.000:0.000:0.000))
(SETUP (negedge WEN[3]) (posedge CLK) (0.917:0.917:0.917))
(SETUP (posedge WEN[4]) (posedge CLK) (0.000:0.000:0.000))
(SETUP (negedge WEN[4]) (posedge CLK) (0.974:0.974:0.974))
(SETUP (posedge WEN[5]) (posedge CLK) (0.000:0.000:0.000))
(SETUP (negedge WEN[5]) (posedge CLK) (0.974:0.974:0.974))
(SETUP (posedge WEN[6]) (posedge CLK) (0.000:0.000:0.000))
(SETUP (negedge WEN[6]) (posedge CLK) (0.974:0.974:0.974))
(SETUP (posedge WEN[7]) (posedge CLK) (0.000:0.000:0.000))
(SETUP (negedge WEN[7]) (posedge CLK) (0.974:0.974:0.974))
(HOLD (posedge GWEN) (posedge CLK) (2.357:2.357:2.357))
(HOLD (negedge GWEN) (posedge CLK) (1.120:1.120:1.120))
(SETUP (posedge GWEN) (posedge CLK) (1.984:1.984:1.984))
(SETUP (negedge GWEN) (posedge CLK) (2.440:2.440:2.440))
(HOLD (posedge CEN) (posedge CLK) (3.942:3.942:3.942))
(HOLD (negedge CEN) (posedge CLK) (4.157:4.157:4.157))
(SETUP (posedge CEN) (posedge CLK) (1.444:1.444:1.444))
(SETUP (negedge CEN) (posedge CLK) (1.077:1.077:1.077))
(WIDTH (posedge CLK) (10.915:10.915:10.915))
(WIDTH (negedge CLK) (10.289:10.289:10.289))
(PERIOD CLK (22.470:22.470:22.470))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__clkbuf_1")
(INSTANCE u_scanchain_local\.input_buf_clk)
(DELAY
(ABSOLUTE
(IOPATH I Z (0.279:0.279:0.279) (0.282:0.282:0.282))
)
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__dffnq_1")
(INSTANCE u_scanchain_local\.out_flop)
(DELAY
(ABSOLUTE
(IOPATH CLKN Q (1.147:1.147:1.147) (0.975:0.975:0.975))
)
)
(TIMINGCHECK
(SETUP (posedge D) (negedge CLKN) (-0.181:-0.181:-0.181))
(SETUP (negedge D) (negedge CLKN) (-0.015:-0.015:-0.015))
(HOLD (posedge D) (negedge CLKN) (0.493:0.493:0.493))
(HOLD (negedge D) (negedge CLKN) (0.310:0.310:0.310))
(WIDTH (posedge CLKN) (0.406:0.406:0.406))
(WIDTH (negedge CLKN) (0.446:0.446:0.446))
(PERIOD CLKN (1.091:1.091:1.091))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__clkbuf_1")
(INSTANCE u_scanchain_local\.output_buffers\[2\])
(DELAY
(ABSOLUTE
(IOPATH I Z (0.261:0.261:0.261) (0.253:0.253:0.253))
)
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__clkbuf_1")
(INSTANCE u_scanchain_local\.output_buffers\[3\])
(DELAY
(ABSOLUTE
(IOPATH I Z (0.395:0.395:0.395) (0.480:0.480:0.480))
)
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[0\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (2.106:2.106:2.106) (1.693:1.693:1.693))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (2.106:2.106:2.106) (1.693:1.693:1.693)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (2.106:2.106:2.106) (1.693:1.693:1.693)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (2.106:2.106:2.106) (1.693:1.693:1.693)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (2.106:2.106:2.106) (1.693:1.693:1.693)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.421:0.420:0.419))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.396:0.422:0.448))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.421:0.420:0.419))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.398:0.425:0.451))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.289:-0.287:-0.285))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.025:0.010:-0.004))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.289:-0.287:-0.285))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.025:0.010:-0.004))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.430:0.430:0.430))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.789:0.789:0.789))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.451:0.451:0.451))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.552:0.552:0.552))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.004:-0.004:-0.004))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.652:-0.652:-0.652))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.277:-0.277:-0.277))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.054:-0.054:-0.054))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.426:0.426:0.426))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.403:0.403:0.403))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.426:0.426:0.426))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.404:0.404:0.404))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.294:-0.294:-0.294))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.023:0.023:0.023))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.294:-0.294:-0.294))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.023:0.023:0.023))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[10\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.379:1.379:1.379) (1.223:1.223:1.223))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.379:1.379:1.379) (1.223:1.223:1.223)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.379:1.379:1.379) (1.223:1.223:1.223)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.379:1.379:1.379) (1.223:1.223:1.223)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.379:1.379:1.379) (1.223:1.223:1.223)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.407:0.407:0.407))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.440:0.440:0.440))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.407:0.407:0.407))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.440:0.440:0.440))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.251:-0.251:-0.251))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.004:-0.004:-0.004))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.251:-0.251:-0.251))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.004:-0.004:-0.004))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.495:0.495:0.495))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.642:0.642:0.642))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.408:0.408:0.408))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.437:0.437:0.437))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.060:-0.060:-0.060))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.483:-0.483:-0.483))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.240:-0.240:-0.240))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.003:-0.003:-0.003))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.424:0.424:0.424))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.527:0.527:0.527))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.424:0.424:0.424))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.527:0.527:0.527))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.241:-0.241:-0.241))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.046:-0.046:-0.046))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.241:-0.241:-0.241))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.046:-0.046:-0.046))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[11\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.189:1.189:1.189) (1.102:1.102:1.102))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.189:1.189:1.189) (1.102:1.102:1.102)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.189:1.189:1.189) (1.102:1.102:1.102)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.189:1.189:1.189) (1.102:1.102:1.102)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.189:1.189:1.189) (1.102:1.102:1.102)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.415:0.415:0.415))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.476:0.476:0.476))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.415:0.415:0.415))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.476:0.476:0.476))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.249:-0.249:-0.249))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.024:-0.024:-0.024))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.249:-0.249:-0.249))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.024:-0.024:-0.024))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.490:0.490:0.490))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.715:0.715:0.715))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.430:0.430:0.430))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.518:0.518:0.518))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.068:-0.068:-0.068))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.558:-0.558:-0.558))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.253:-0.253:-0.253))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.051:-0.051:-0.051))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.423:0.423:0.423))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.504:0.504:0.504))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.423:0.423:0.423))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.504:0.504:0.504))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.247:-0.247:-0.247))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.040:-0.040:-0.040))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.247:-0.247:-0.247))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.040:-0.040:-0.040))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[12\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.405:1.405:1.405) (1.232:1.232:1.232))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.405:1.405:1.405) (1.232:1.232:1.232)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.405:1.405:1.405) (1.232:1.232:1.232)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.405:1.405:1.405) (1.232:1.232:1.232)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.405:1.405:1.405) (1.232:1.232:1.232)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.424:0.424:0.424))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.510:0.510:0.510))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.424:0.424:0.424))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.510:0.510:0.510))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.239:-0.239:-0.239))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.047:-0.047:-0.047))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.239:-0.239:-0.239))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.047:-0.047:-0.047))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.507:0.507:0.507))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.591:0.591:0.591))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.396:0.396:0.396))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.413:0.413:0.413))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.068:-0.068:-0.068))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.419:-0.419:-0.419))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.227:-0.227:-0.227))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.014:0.014:0.014))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.427:0.427:0.427))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.492:0.492:0.492))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.427:0.427:0.427))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.492:0.492:0.492))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.248:-0.248:-0.248))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.044:-0.044:-0.044))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.248:-0.248:-0.248))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.044:-0.044:-0.044))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[13\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.384:1.384:1.384) (1.218:1.218:1.218))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.384:1.384:1.384) (1.218:1.218:1.218)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.384:1.384:1.384) (1.218:1.218:1.218)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.384:1.384:1.384) (1.218:1.218:1.218)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.384:1.384:1.384) (1.218:1.218:1.218)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.412:0.412:0.412))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.457:0.457:0.457))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.412:0.412:0.412))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.457:0.457:0.457))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.244:-0.244:-0.244))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.018:-0.018:-0.018))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.244:-0.244:-0.244))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.018:-0.018:-0.018))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.516:0.516:0.516))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.642:0.642:0.642))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.416:0.416:0.416))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.456:0.456:0.456))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.080:-0.080:-0.080))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.470:-0.470:-0.470))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.234:-0.234:-0.234))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.019:-0.019:-0.019))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.431:0.431:0.431))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.536:0.536:0.536))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.431:0.431:0.431))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.536:0.536:0.536))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.239:-0.239:-0.239))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.058:-0.058:-0.058))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.239:-0.239:-0.239))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.058:-0.058:-0.058))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[14\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.128:1.128:1.128) (1.056:1.056:1.056))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.127:1.127:1.127) (1.056:1.056:1.056)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.127:1.127:1.127) (1.056:1.056:1.056)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.128:1.128:1.128) (1.056:1.056:1.056)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.128:1.128:1.128) (1.056:1.056:1.056)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.422:0.422:0.422))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.495:0.495:0.495))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.422:0.422:0.422))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.495:0.495:0.495))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.241:-0.241:-0.241))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.041:-0.041:-0.041))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.241:-0.241:-0.241))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.041:-0.041:-0.041))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.507:0.507:0.507))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.591:0.591:0.591))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.396:0.396:0.396))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.413:0.413:0.413))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.068:-0.068:-0.068))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.419:-0.419:-0.419))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.227:-0.227:-0.227))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.014:0.014:0.014))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.430:0.430:0.430))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.530:0.530:0.530))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.430:0.430:0.430))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.530:0.530:0.530))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.240:-0.240:-0.240))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.056:-0.056:-0.056))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.240:-0.240:-0.240))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.056:-0.056:-0.056))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[15\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.406:1.406:1.406) (1.232:1.232:1.232))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.405:1.405:1.405) (1.232:1.232:1.232)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.405:1.405:1.405) (1.232:1.232:1.232)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.406:1.406:1.406) (1.232:1.232:1.232)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.406:1.406:1.406) (1.232:1.232:1.232)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.412:0.412:0.412))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.457:0.457:0.457))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.412:0.412:0.412))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.457:0.457:0.457))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.244:-0.244:-0.244))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.018:-0.018:-0.018))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.244:-0.244:-0.244))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.018:-0.018:-0.018))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.515:0.515:0.515))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.646:0.646:0.646))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.441:0.441:0.441))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.458:0.458:0.458))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.085:-0.085:-0.085))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.474:-0.474:-0.474))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.021:-0.021:-0.021))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.426:0.426:0.426))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.489:0.489:0.489))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.426:0.426:0.426))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.490:0.490:0.490))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.248:-0.248:-0.248))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.043:-0.043:-0.043))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.248:-0.248:-0.248))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.043:-0.043:-0.043))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[16\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.411:1.411:1.411) (1.239:1.239:1.239))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.411:1.411:1.411) (1.239:1.239:1.239)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.411:1.411:1.411) (1.239:1.239:1.239)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.411:1.411:1.411) (1.239:1.239:1.239)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.411:1.411:1.411) (1.239:1.239:1.239)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.408:0.408:0.408))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.442:0.442:0.442))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.408:0.408:0.408))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.442:0.442:0.442))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.250:-0.250:-0.250))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.007:-0.007:-0.007))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.250:-0.250:-0.250))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.007:-0.007:-0.007))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.505:0.505:0.505))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.639:0.639:0.639))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.411:0.411:0.411))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.444:0.444:0.444))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.069:-0.069:-0.069))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.474:-0.474:-0.474))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.236:-0.236:-0.236))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.008:-0.008:-0.008))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.427:0.427:0.427))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.524:0.524:0.524))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.427:0.427:0.427))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.524:0.524:0.524))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.242:-0.242:-0.242))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.050:-0.050:-0.050))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.242:-0.242:-0.242))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.050:-0.050:-0.050))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[17\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.554:1.554:1.554) (1.329:1.329:1.329))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.554:1.554:1.554) (1.329:1.329:1.329)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.554:1.554:1.554) (1.329:1.329:1.329)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.554:1.554:1.554) (1.329:1.329:1.329)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.554:1.554:1.554) (1.329:1.329:1.329)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.408:0.408:0.408))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.443:0.443:0.443))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.408:0.408:0.408))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.443:0.443:0.443))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.250:-0.250:-0.250))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.008:-0.008:-0.008))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.250:-0.250:-0.250))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.008:-0.008:-0.008))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.505:0.505:0.505))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.639:0.639:0.639))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.411:0.411:0.411))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.444:0.444:0.444))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.069:-0.069:-0.069))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.474:-0.474:-0.474))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.236:-0.236:-0.236))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.008:-0.008:-0.008))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.427:0.427:0.427))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.523:0.523:0.523))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.427:0.427:0.427))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.523:0.523:0.523))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.242:-0.242:-0.242))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.049:-0.049:-0.049))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.242:-0.242:-0.242))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.049:-0.049:-0.049))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[18\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.165:1.165:1.165) (1.083:1.083:1.083))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.165:1.165:1.165) (1.083:1.083:1.083)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.165:1.165:1.165) (1.083:1.083:1.083)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.165:1.165:1.165) (1.083:1.083:1.083)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.165:1.165:1.165) (1.083:1.083:1.083)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.408:0.408:0.408))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.445:0.445:0.445))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.408:0.408:0.408))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.445:0.445:0.445))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.249:-0.249:-0.249))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.009:-0.009:-0.009))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.249:-0.249:-0.249))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.009:-0.009:-0.009))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.505:0.505:0.505))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.627:0.627:0.627))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.406:0.406:0.406))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.435:0.435:0.435))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.068:-0.068:-0.068))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.460:-0.460:-0.460))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.234:-0.234:-0.234))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.002:-0.002:-0.002))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.429:0.429:0.429))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.553:0.553:0.553))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.429:0.429:0.429))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.553:0.553:0.553))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.235:-0.235:-0.235))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.058:-0.058:-0.058))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.235:-0.235:-0.235))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.058:-0.058:-0.058))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[19\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.064:1.064:1.064) (1.018:1.018:1.018))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.064:1.064:1.064) (1.018:1.018:1.018)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.064:1.064:1.064) (1.018:1.018:1.018)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.064:1.064:1.064) (1.018:1.018:1.018)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.064:1.064:1.064) (1.018:1.018:1.018)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.409:0.409:0.409))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.448:0.448:0.448))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.409:0.409:0.409))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.448:0.448:0.448))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.248:-0.248:-0.248))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.011:-0.011:-0.011))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.248:-0.248:-0.248))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.011:-0.011:-0.011))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.505:0.505:0.505))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.627:0.627:0.627))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.406:0.406:0.406))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.435:0.435:0.435))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.068:-0.068:-0.068))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.460:-0.460:-0.460))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.234:-0.234:-0.234))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.002:-0.002:-0.002))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.424:0.424:0.424))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.483:0.483:0.483))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.424:0.424:0.424))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.483:0.483:0.483))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.251:-0.251:-0.251))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.037:-0.037:-0.037))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.251:-0.251:-0.251))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.037:-0.037:-0.037))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[1\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.995:1.995:1.995) (1.623:1.623:1.623))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.995:1.995:1.995) (1.623:1.623:1.623)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.995:1.995:1.995) (1.623:1.623:1.623)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.995:1.995:1.995) (1.623:1.623:1.623)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.995:1.995:1.995) (1.623:1.623:1.623)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.421:0.420:0.420))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.399:0.414:0.429))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.421:0.420:0.420))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.400:0.416:0.431))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.290:-0.289:-0.288))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.022:0.012:0.002))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.290:-0.289:-0.288))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.022:0.012:0.002))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.430:0.430:0.430))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.789:0.789:0.789))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.451:0.451:0.451))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.552:0.552:0.552))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.004:-0.004:-0.004))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.652:-0.652:-0.652))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.277:-0.277:-0.277))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.054:-0.054:-0.054))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.416:0.416:0.416))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.606:0.606:0.606))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.416:0.416:0.416))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.609:0.609:0.610))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.241:-0.241:-0.241))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.029:-0.029:-0.029))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.240:-0.240:-0.240))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.029:-0.029:-0.029))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[20\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.094:1.094:1.094) (1.037:1.037:1.037))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.094:1.094:1.094) (1.037:1.037:1.037)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.094:1.094:1.094) (1.037:1.037:1.037)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.094:1.094:1.094) (1.037:1.037:1.037)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.094:1.094:1.094) (1.037:1.037:1.037)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.409:0.409:0.409))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.446:0.446:0.446))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.409:0.409:0.409))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.446:0.446:0.446))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.249:-0.249:-0.249))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.010:-0.010:-0.010))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.249:-0.249:-0.249))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.010:-0.010:-0.010))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.505:0.505:0.505))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.627:0.627:0.627))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.406:0.406:0.406))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.435:0.435:0.435))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.068:-0.068:-0.068))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.460:-0.460:-0.460))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.234:-0.234:-0.234))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.002:-0.002:-0.002))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.421:0.421:0.421))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.472:0.472:0.472))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.421:0.421:0.421))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.472:0.472:0.472))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.252:-0.252:-0.252))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.030:-0.030:-0.030))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.252:-0.252:-0.252))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.030:-0.030:-0.030))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[21\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.018:1.018:1.018) (0.959:0.959:0.959))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.018:1.018:1.018) (0.959:0.959:0.959)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.018:1.018:1.018) (0.959:0.959:0.959)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.018:1.018:1.018) (0.959:0.959:0.959)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.018:1.018:1.018) (0.959:0.959:0.959)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.472:0.472:0.472))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.539:0.539:0.539))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.472:0.472:0.472))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.539:0.539:0.539))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.240:-0.240:-0.240))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.080:-0.080:-0.080))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.240:-0.240:-0.240))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.080:-0.080:-0.080))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.594:0.594:0.594))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.685:0.685:0.685))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.467:0.467:0.467))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.529:0.529:0.529))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.143:-0.143:-0.143))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.454:-0.454:-0.454))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.233:-0.233:-0.233))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.081:-0.081:-0.081))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.480:0.480:0.480))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.570:0.570:0.570))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.480:0.480:0.480))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.570:0.570:0.570))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.103:-0.103:-0.103))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.103:-0.103:-0.103))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[22\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.069:1.069:1.069) (1.021:1.021:1.021))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.069:1.069:1.069) (1.021:1.021:1.021)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.069:1.069:1.069) (1.021:1.021:1.021)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.069:1.069:1.069) (1.021:1.021:1.021)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.069:1.069:1.069) (1.021:1.021:1.021)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.421:0.421:0.421))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.515:0.515:0.515))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.421:0.421:0.421))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.515:0.515:0.515))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.240:-0.240:-0.240))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.043:-0.043:-0.043))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.240:-0.240:-0.240))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.043:-0.043:-0.043))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.505:0.505:0.505))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.627:0.627:0.627))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.406:0.406:0.406))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.435:0.435:0.435))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.068:-0.068:-0.068))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.460:-0.460:-0.460))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.234:-0.234:-0.234))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.002:-0.002:-0.002))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.422:0.422:0.422))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.476:0.476:0.476))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.422:0.422:0.422))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.476:0.476:0.477))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.252:-0.252:-0.252))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.033:-0.033:-0.033))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.252:-0.252:-0.252))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.033:-0.033:-0.033))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[23\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.150:1.150:1.150) (1.063:1.063:1.063))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.149:1.149:1.149) (1.063:1.063:1.063)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.149:1.149:1.149) (1.063:1.063:1.063)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.150:1.150:1.150) (1.063:1.063:1.063)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.150:1.150:1.150) (1.063:1.063:1.063)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.426:0.426:0.426))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.490:0.490:0.490))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.426:0.426:0.426))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.489:0.489:0.489))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.238:-0.238:-0.238))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.041:-0.041:-0.041))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.238:-0.238:-0.238))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.041:-0.041:-0.041))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.534:0.534:0.534))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.660:0.660:0.660))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.431:0.431:0.431))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.485:0.485:0.485))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.099:-0.099:-0.099))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.477:-0.477:-0.477))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.232:-0.232:-0.232))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.043:-0.043:-0.043))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.431:0.431:0.431))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.500:0.501:0.501))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.431:0.431:0.431))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.501:0.501:0.501))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.244:-0.244:-0.244))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.053:-0.053:-0.053))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.244:-0.244:-0.244))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.053:-0.053:-0.053))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[24\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.074:1.074:1.074) (0.995:0.995:0.995))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.074:1.074:1.074) (0.995:0.995:0.995)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.074:1.074:1.074) (0.995:0.995:0.995)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.074:1.074:1.074) (0.995:0.995:0.995)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.074:1.074:1.074) (0.995:0.995:0.995)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.473:0.473:0.473))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.540:0.540:0.540))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.473:0.473:0.473))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.540:0.540:0.540))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.240:-0.240:-0.240))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.081:-0.081:-0.081))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.240:-0.240:-0.240))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.081:-0.081:-0.081))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.591:0.591:0.591))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.632:0.632:0.632))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.449:0.449:0.449))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.493:0.493:0.493))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.130:-0.130:-0.130))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.404:-0.404:-0.404))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.220:-0.220:-0.220))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.047:-0.047:-0.047))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.484:0.484:0.484))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.580:0.580:0.580))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.484:0.484:0.484))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.580:0.580:0.580))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.243:-0.243:-0.243))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.108:-0.108:-0.108))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.243:-0.243:-0.243))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.108:-0.108:-0.108))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[25\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.158:1.158:1.158) (1.078:1.078:1.078))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.158:1.158:1.158) (1.078:1.078:1.078)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.158:1.158:1.158) (1.078:1.078:1.078)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.158:1.158:1.158) (1.078:1.078:1.078)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.158:1.158:1.158) (1.078:1.078:1.078)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.408:0.408:0.408))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.444:0.444:0.444))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.408:0.408:0.408))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.444:0.444:0.444))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.249:-0.249:-0.249))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.009:-0.009:-0.009))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.249:-0.249:-0.249))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.009:-0.009:-0.009))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.498:0.498:0.498))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.577:0.577:0.577))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.387:0.387:0.387))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.398:0.398:0.398))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.059:-0.059:-0.059))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.411:-0.411:-0.411))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.227:-0.227:-0.227))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.027:0.027:0.027))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.424:0.424:0.424))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.482:0.482:0.482))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.424:0.424:0.424))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.482:0.482:0.482))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.251:-0.251:-0.251))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.037:-0.037:-0.037))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.251:-0.251:-0.251))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.037:-0.037:-0.037))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[26\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.129:1.129:1.129) (1.050:1.050:1.050))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.128:1.128:1.128) (1.050:1.050:1.050)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.128:1.128:1.128) (1.050:1.050:1.050)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.129:1.129:1.129) (1.050:1.050:1.050)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.129:1.129:1.129) (1.050:1.050:1.050)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.418:0.418:0.418))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.477:0.477:0.477))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.418:0.418:0.418))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.477:0.477:0.477))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.236:-0.236:-0.236))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.033:-0.033:-0.033))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.236:-0.236:-0.236))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.033:-0.033:-0.033))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.534:0.534:0.534))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.660:0.660:0.660))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.431:0.431:0.431))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.485:0.485:0.485))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.099:-0.099:-0.099))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.477:-0.477:-0.477))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.232:-0.232:-0.232))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.043:-0.043:-0.043))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.435:0.435:0.435))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.511:0.511:0.511))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.435:0.435:0.435))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.511:0.511:0.511))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.242:-0.242:-0.242))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.059:-0.059:-0.059))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.242:-0.242:-0.242))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.059:-0.059:-0.059))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[27\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.143:1.143:1.143) (1.069:1.069:1.069))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.143:1.143:1.143) (1.069:1.069:1.069)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.143:1.143:1.143) (1.069:1.069:1.069)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.143:1.143:1.143) (1.069:1.069:1.069)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.143:1.143:1.143) (1.069:1.069:1.069)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.408:0.408:0.408))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.443:0.443:0.443))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.408:0.408:0.408))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.443:0.443:0.443))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.250:-0.250:-0.250))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.008:-0.008:-0.008))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.250:-0.250:-0.250))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.008:-0.008:-0.008))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.505:0.505:0.505))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.639:0.639:0.639))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.411:0.411:0.411))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.444:0.444:0.444))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.069:-0.069:-0.069))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.474:-0.474:-0.474))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.236:-0.236:-0.236))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.008:-0.008:-0.008))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.423:0.423:0.423))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.480:0.480:0.480))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.423:0.423:0.423))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.480:0.480:0.480))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.251:-0.251:-0.251))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.035:-0.035:-0.035))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.251:-0.251:-0.251))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.035:-0.035:-0.035))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[28\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.319:1.319:1.319) (1.180:1.180:1.180))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.319:1.319:1.319) (1.180:1.180:1.180)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.319:1.319:1.319) (1.180:1.180:1.180)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.319:1.319:1.319) (1.180:1.180:1.180)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.319:1.319:1.319) (1.180:1.180:1.180)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.408:0.408:0.408))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.442:0.442:0.442))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.408:0.408:0.408))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.442:0.442:0.442))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.250:-0.250:-0.250))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.008:-0.008:-0.008))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.250:-0.250:-0.250))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.008:-0.008:-0.008))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.505:0.505:0.505))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.639:0.639:0.639))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.411:0.411:0.411))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.444:0.444:0.444))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.069:-0.069:-0.069))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.474:-0.474:-0.474))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.236:-0.236:-0.236))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.008:-0.008:-0.008))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.423:0.423:0.423))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.479:0.479:0.479))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.423:0.423:0.423))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.479:0.479:0.479))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.251:-0.251:-0.251))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.034:-0.034:-0.034))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.251:-0.251:-0.251))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.034:-0.034:-0.034))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[29\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.219:1.219:1.219) (1.113:1.113:1.113))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.218:1.218:1.218) (1.113:1.113:1.113)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.218:1.218:1.218) (1.113:1.113:1.113)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.219:1.219:1.219) (1.113:1.113:1.113)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.219:1.219:1.219) (1.113:1.113:1.113)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.412:0.412:0.412))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.456:0.456:0.456))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.412:0.412:0.412))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.456:0.456:0.456))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.244:-0.244:-0.244))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.017:-0.017:-0.017))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.244:-0.244:-0.244))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.017:-0.017:-0.017))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.515:0.515:0.515))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.646:0.646:0.646))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.441:0.441:0.441))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.458:0.458:0.458))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.085:-0.085:-0.085))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.474:-0.474:-0.474))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.021:-0.021:-0.021))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.430:0.430:0.430))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.517:0.517:0.517))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.430:0.430:0.430))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.517:0.517:0.517))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.243:-0.243:-0.243))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.054:-0.054:-0.054))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.243:-0.243:-0.243))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.054:-0.054:-0.054))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[2\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.715:1.715:1.715) (1.415:1.415:1.415))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.715:1.715:1.715) (1.415:1.415:1.415)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.715:1.715:1.715) (1.415:1.415:1.415)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.715:1.715:1.715) (1.415:1.415:1.415)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.714:1.714:1.714) (1.415:1.415:1.415)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.433:0.434:0.434))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.493:0.504:0.516))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.433:0.434:0.434))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.493:0.504:0.516))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.235:-0.235:-0.236))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.044:-0.052:-0.060))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.235:-0.235:-0.236))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.044:-0.052:-0.060))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.549:0.549:0.549))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.666:0.666:0.666))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.438:0.438:0.438))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.497:0.497:0.497))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.111:-0.111:-0.111))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.471:-0.471:-0.471))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.232:-0.232:-0.232))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.054:-0.054:-0.054))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.452:0.452:0.452))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.579:0.579:0.579))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.452:0.452:0.452))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.579:0.579:0.579))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.231:-0.231:-0.231))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.086:-0.086:-0.086))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.231:-0.231:-0.231))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.086:-0.086:-0.086))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[30\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.204:1.204:1.204) (1.104:1.104:1.104))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.203:1.203:1.203) (1.104:1.104:1.104)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.203:1.203:1.203) (1.104:1.104:1.104)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.204:1.204:1.204) (1.104:1.104:1.104)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.204:1.204:1.204) (1.104:1.104:1.104)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.425:0.425:0.425))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.523:0.523:0.523))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.425:0.425:0.425))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.523:0.523:0.523))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.237:-0.237:-0.237))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.051:-0.051:-0.051))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.237:-0.237:-0.237))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.051:-0.051:-0.051))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.515:0.515:0.515))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.646:0.646:0.646))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.441:0.441:0.441))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.458:0.458:0.458))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.085:-0.085:-0.085))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.474:-0.474:-0.474))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.021:-0.021:-0.021))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.429:0.429:0.429))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.500:0.500:0.500))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.429:0.429:0.429))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.500:0.500:0.500))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.247:-0.247:-0.247))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.049:-0.049:-0.049))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.247:-0.247:-0.247))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.049:-0.049:-0.049))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[31\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.285:1.285:1.285) (1.159:1.159:1.159))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.285:1.285:1.285) (1.159:1.159:1.159)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.285:1.285:1.285) (1.159:1.159:1.159)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.285:1.285:1.285) (1.159:1.159:1.159)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.285:1.285:1.285) (1.159:1.159:1.159)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.408:0.408:0.408))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.442:0.442:0.442))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.408:0.408:0.408))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.442:0.442:0.442))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.250:-0.250:-0.250))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.007:-0.007:-0.007))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.250:-0.250:-0.250))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.007:-0.007:-0.007))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.502:0.502:0.502))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.642:0.642:0.642))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.434:0.434:0.434))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.446:0.446:0.446))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.076:-0.076:-0.076))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.477:-0.477:-0.477))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.248:-0.248:-0.248))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.010:-0.010:-0.010))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.424:0.424:0.424))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.486:0.486:0.486))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.424:0.424:0.424))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.486:0.486:0.486))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.250:-0.250:-0.250))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.039:-0.039:-0.039))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.250:-0.250:-0.250))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.039:-0.039:-0.039))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[32\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.255:1.255:1.255) (1.140:1.140:1.140))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.255:1.255:1.255) (1.140:1.140:1.140)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.255:1.255:1.255) (1.140:1.140:1.140)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.255:1.255:1.255) (1.140:1.140:1.140)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.255:1.255:1.255) (1.140:1.140:1.140)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.412:0.412:0.412))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.459:0.459:0.459))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.412:0.412:0.412))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.459:0.459:0.459))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.016:-0.016:-0.016))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.016:-0.016:-0.016))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.498:0.498:0.498))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.678:0.678:0.678))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.443:0.443:0.443))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.483:0.483:0.483))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.070:-0.070:-0.070))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.513:-0.513:-0.513))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.253:-0.253:-0.253))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.033:-0.033:-0.033))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.425:0.425:0.425))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.498:0.498:0.498))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.425:0.425:0.425))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.498:0.498:0.498))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.248:-0.248:-0.248))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.043:-0.043:-0.043))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.248:-0.248:-0.248))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.043:-0.043:-0.043))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[33\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.366:1.366:1.366) (1.210:1.210:1.210))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.366:1.366:1.366) (1.210:1.210:1.210)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.366:1.366:1.366) (1.210:1.210:1.210)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.366:1.366:1.366) (1.210:1.210:1.210)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.366:1.366:1.366) (1.210:1.210:1.210)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.408:0.408:0.408))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.443:0.443:0.443))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.408:0.408:0.408))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.443:0.443:0.443))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.250:-0.250:-0.250))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.008:-0.008:-0.008))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.250:-0.250:-0.250))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.008:-0.008:-0.008))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.498:0.498:0.498))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.678:0.678:0.678))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.443:0.443:0.443))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.483:0.483:0.483))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.070:-0.070:-0.070))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.513:-0.513:-0.513))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.253:-0.253:-0.253))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.033:-0.033:-0.033))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.425:0.425:0.425))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.492:0.492:0.492))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.425:0.425:0.425))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.492:0.492:0.492))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.249:-0.249:-0.249))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.042:-0.042:-0.042))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.249:-0.249:-0.249))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.042:-0.042:-0.042))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[34\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.708:0.708:0.708) (0.764:0.764:0.764))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.708:0.708:0.708) (0.764:0.764:0.764)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.708:0.708:0.708) (0.764:0.764:0.764)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.708:0.708:0.708) (0.764:0.764:0.764)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.708:0.708:0.708) (0.764:0.764:0.764)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.408:0.408:0.408))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.443:0.443:0.443))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.408:0.408:0.408))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.443:0.443:0.443))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.250:-0.250:-0.250))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.008:-0.008:-0.008))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.250:-0.250:-0.250))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.008:-0.008:-0.008))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.498:0.498:0.498))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.678:0.678:0.678))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.443:0.443:0.443))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.483:0.483:0.483))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.070:-0.070:-0.070))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.513:-0.513:-0.513))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.253:-0.253:-0.253))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.033:-0.033:-0.033))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.426:0.426:0.426))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.514:0.514:0.514))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.426:0.426:0.426))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.514:0.514:0.514))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.244:-0.244:-0.244))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.047:-0.047:-0.047))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.244:-0.244:-0.244))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.047:-0.047:-0.047))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[35\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.734:0.734:0.734) (0.786:0.786:0.786))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.734:0.734:0.734) (0.786:0.786:0.786)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.734:0.734:0.734) (0.786:0.786:0.786)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.734:0.734:0.734) (0.786:0.786:0.786)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.734:0.734:0.734) (0.786:0.786:0.786)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.412:0.412:0.412))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.457:0.457:0.457))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.412:0.412:0.412))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.457:0.457:0.457))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.015:-0.015:-0.015))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.015:-0.015:-0.015))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.498:0.498:0.498))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.678:0.678:0.678))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.443:0.443:0.443))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.483:0.483:0.483))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.070:-0.070:-0.070))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.513:-0.513:-0.513))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.253:-0.253:-0.253))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.033:-0.033:-0.033))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.415:0.415:0.415))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.438:0.438:0.438))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.415:0.415:0.415))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.438:0.438:0.438))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.254:-0.254:-0.254))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.001:-0.001:-0.001))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.254:-0.254:-0.254))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.001:-0.001:-0.001))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[36\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.718:0.718:0.718) (0.773:0.773:0.773))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.718:0.718:0.718) (0.773:0.773:0.773)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.718:0.718:0.718) (0.773:0.773:0.773)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.718:0.718:0.718) (0.773:0.773:0.773)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.718:0.718:0.718) (0.773:0.773:0.773)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.409:0.409:0.409))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.438:0.438:0.438))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.409:0.409:0.409))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.438:0.438:0.438))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.249:-0.249:-0.249))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.005:-0.005:-0.005))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.249:-0.249:-0.249))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.005:-0.005:-0.005))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.498:0.498:0.498))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.678:0.678:0.678))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.443:0.443:0.443))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.483:0.483:0.483))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.070:-0.070:-0.070))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.513:-0.513:-0.513))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.253:-0.253:-0.253))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.033:-0.033:-0.033))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.415:0.415:0.415))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.442:0.442:0.442))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.415:0.415:0.415))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.442:0.442:0.442))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.254:-0.254:-0.254))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.004:-0.004:-0.004))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.254:-0.254:-0.254))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.004:-0.004:-0.004))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[37\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.622:1.622:1.622) (1.389:1.389:1.389))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.622:1.622:1.622) (1.389:1.389:1.389)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.622:1.622:1.622) (1.389:1.389:1.389)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.622:1.622:1.622) (1.389:1.389:1.389)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.622:1.622:1.622) (1.389:1.389:1.389)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.426:0.426:0.426))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.388:0.388:0.388))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.426:0.426:0.426))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.390:0.390:0.390))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.298:-0.298:-0.298))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.032:0.032:0.032))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.298:-0.298:-0.298))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.032:0.032:0.032))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.420:0.420:0.420))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.797:0.797:0.797))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.453:0.453:0.453))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.553:0.553:0.553))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.003:0.003:0.003))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.662:-0.662:-0.662))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.280:-0.280:-0.280))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.052:-0.052:-0.052))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.431:0.431:0.431))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.388:0.388:0.388))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.431:0.431:0.431))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.385:0.385:0.385))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.299:-0.299:-0.299))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.037:0.037:0.037))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.299:-0.299:-0.299))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.037:0.037:0.037))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[38\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.768:0.768:0.768) (0.821:0.821:0.821))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.768:0.768:0.768) (0.821:0.821:0.821)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.768:0.768:0.768) (0.821:0.821:0.821)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.768:0.768:0.768) (0.821:0.821:0.821)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.768:0.768:0.768) (0.821:0.821:0.821)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.427:0.427:0.427))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.384:0.384:0.384))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.427:0.427:0.427))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.387:0.387:0.387))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.299:-0.299:-0.299))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.036:0.036:0.036))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.299:-0.299:-0.299))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.036:0.036:0.036))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.409:0.409:0.409))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.826:0.826:0.826))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.452:0.452:0.452))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.589:0.589:0.589))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.015:0.015:0.015))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.691:-0.691:-0.691))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.274:-0.274:-0.274))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.068:-0.068:-0.068))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.438:0.438:0.438))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.497:0.497:0.497))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.432:0.432:0.432))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.497:0.497:0.497))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.281:-0.281:-0.281))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.014:-0.014:-0.014))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.281:-0.281:-0.281))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.014:-0.014:-0.014))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[39\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.782:0.782:0.782) (0.833:0.833:0.833))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.782:0.782:0.782) (0.833:0.833:0.833)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.782:0.782:0.782) (0.833:0.833:0.833)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.782:0.782:0.782) (0.833:0.833:0.833)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.782:0.782:0.782) (0.833:0.833:0.833)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.427:0.427:0.427))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.390:0.390:0.391))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.427:0.427:0.427))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.392:0.392:0.392))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.299:-0.299:-0.299))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.029:0.029:0.029))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.299:-0.299:-0.299))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.029:0.029:0.029))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.408:0.408:0.408))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.827:0.827:0.827))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.452:0.452:0.452))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.588:0.588:0.588))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.015:0.015:0.015))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.692:-0.692:-0.692))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.275:-0.275:-0.275))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.068:-0.068:-0.068))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.432:0.432:0.432))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.387:0.387:0.387))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.432:0.432:0.432))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.384:0.384:0.384))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.300:-0.300:-0.300))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.038:0.038:0.038))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.300:-0.300:-0.300))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.038:0.038:0.038))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[3\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.650:1.650:1.650) (1.374:1.374:1.374))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.650:1.650:1.650) (1.374:1.374:1.374)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.650:1.650:1.650) (1.374:1.374:1.374)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.650:1.650:1.650) (1.374:1.374:1.374)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.650:1.650:1.650) (1.374:1.374:1.374)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.433:0.435:0.436))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.495:0.509:0.523))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.433:0.435:0.436))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.494:0.509:0.523))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.235:-0.236:-0.237))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.045:-0.055:-0.065))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.235:-0.236:-0.237))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.045:-0.055:-0.065))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.549:0.549:0.549))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.666:0.666:0.666))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.438:0.438:0.438))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.497:0.497:0.497))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.111:-0.111:-0.111))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.471:-0.471:-0.471))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.232:-0.232:-0.232))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.054:-0.054:-0.054))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.451:0.451:0.451))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.645:0.645:0.645))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.451:0.451:0.451))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.645:0.645:0.645))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.212:-0.212:-0.212))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.099:-0.099:-0.099))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.212:-0.212:-0.212))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.098:-0.098:-0.098))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[40\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.790:0.790:0.790) (0.839:0.839:0.839))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.790:0.790:0.790) (0.840:0.840:0.840)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.789:0.789:0.789) (0.839:0.839:0.839)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.790:0.790:0.790) (0.839:0.839:0.839)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.790:0.790:0.790) (0.839:0.839:0.839)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.427:0.426:0.426))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.386:0.388:0.390))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.427:0.426:0.426))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.388:0.390:0.392))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.299:-0.299:-0.298))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.033:0.032:0.030))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.299:-0.299:-0.298))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.033:0.032:0.030))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.408:0.408:0.408))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.827:0.827:0.827))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.452:0.452:0.452))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.588:0.588:0.588))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.015:0.015:0.015))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.692:-0.692:-0.692))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.275:-0.275:-0.275))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.068:-0.068:-0.068))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.432:0.432:0.432))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.389:0.389:0.389))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.432:0.432:0.432))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.385:0.385:0.385))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.300:-0.300:-0.300))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.037:0.037:0.037))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.300:-0.300:-0.300))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.037:0.037:0.037))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[41\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.808:0.808:0.808) (0.855:0.855:0.855))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.808:0.808:0.808) (0.855:0.855:0.855)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.807:0.807:0.807) (0.855:0.855:0.855)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.808:0.808:0.808) (0.855:0.855:0.855)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.808:0.808:0.808) (0.855:0.855:0.855)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.427:0.426:0.425))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.384:0.407:0.430))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.427:0.426:0.425))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.387:0.411:0.435))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.299:-0.297:-0.294))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.035:0.020:0.004))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.299:-0.297:-0.294))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.035:0.020:0.004))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.408:0.408:0.408))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.827:0.827:0.827))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.452:0.452:0.452))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.588:0.588:0.588))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.015:0.015:0.015))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.692:-0.692:-0.692))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.275:-0.275:-0.275))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.068:-0.068:-0.068))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.432:0.432:0.432))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.389:0.389:0.389))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.432:0.432:0.432))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.386:0.386:0.386))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.301:-0.301:-0.301))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.036:0.036:0.036))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.301:-0.301:-0.301))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.036:0.036:0.036))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[42\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.792:0.792:0.792) (0.842:0.842:0.842))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.792:0.792:0.792) (0.842:0.842:0.842)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.792:0.792:0.792) (0.842:0.842:0.842)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.792:0.792:0.792) (0.842:0.842:0.842)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.792:0.792:0.792) (0.842:0.842:0.842)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.426:0.425:0.424))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.385:0.408:0.431))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.426:0.425:0.424))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.388:0.412:0.436))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.298:-0.295:-0.293))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.034:0.019:0.003))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.298:-0.295:-0.293))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.034:0.019:0.003))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.409:0.409:0.409))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.826:0.826:0.826))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.452:0.452:0.452))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.589:0.589:0.589))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.015:0.015:0.015))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.691:-0.691:-0.691))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.274:-0.274:-0.274))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.068:-0.068:-0.068))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.431:0.431:0.431))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.392:0.392:0.392))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.431:0.431:0.431))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.388:0.388:0.388))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.300:-0.300:-0.300))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.034:0.034:0.034))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.300:-0.300:-0.300))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.034:0.034:0.034))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[43\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.766:0.766:0.766) (0.819:0.819:0.819))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.766:0.766:0.766) (0.819:0.819:0.819)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.766:0.766:0.766) (0.819:0.819:0.819)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.766:0.766:0.766) (0.819:0.819:0.819)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.766:0.766:0.766) (0.819:0.819:0.819)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.427:0.426:0.425))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.386:0.412:0.438))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.427:0.426:0.425))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.389:0.415:0.442))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.299:-0.296:-0.293))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.033:0.018:0.002))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.299:-0.296:-0.293))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.033:0.018:0.002))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.420:0.420:0.420))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.798:0.798:0.798))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.454:0.454:0.454))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.552:0.552:0.552))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.004:0.004:0.004))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.664:-0.664:-0.664))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.281:-0.281:-0.281))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.052:-0.052:-0.052))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.432:0.432:0.432))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.390:0.390:0.390))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.432:0.432:0.432))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.386:0.386:0.386))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.301:-0.301:-0.301))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.036:0.036:0.036))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.301:-0.301:-0.301))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.036:0.036:0.036))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[44\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.786:0.786:0.786) (0.835:0.835:0.835))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.786:0.786:0.786) (0.835:0.835:0.835)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.786:0.786:0.786) (0.835:0.835:0.835)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.786:0.786:0.786) (0.835:0.835:0.835)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.786:0.786:0.786) (0.835:0.835:0.835)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.415:0.414:0.413))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.395:0.399:0.403))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.415:0.414:0.413))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.403:0.405:0.406))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.279:-0.279:-0.278))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.026:0.022:0.018))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.279:-0.279:-0.278))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.026:0.022:0.018))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.452:0.452:0.452))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.730:0.730:0.730))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.444:0.444:0.444))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.498:0.498:0.498))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.025:-0.025:-0.025))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.591:-0.591:-0.591))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.276:-0.276:-0.276))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.032:-0.032:-0.032))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.418:0.418:0.418))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.398:0.398:0.398))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.418:0.418:0.418))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.397:0.397:0.397))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.280:-0.280:-0.280))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.032:0.032:0.032))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.280:-0.280:-0.280))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.032:0.032:0.032))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[45\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.857:0.857:0.857) (0.891:0.891:0.891))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.857:0.857:0.857) (0.891:0.891:0.891)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.857:0.857:0.857) (0.891:0.891:0.891)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.857:0.857:0.857) (0.891:0.891:0.891)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.857:0.857:0.857) (0.891:0.891:0.891)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.414:0.413:0.412))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.397:0.425:0.454))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.414:0.413:0.412))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.403:0.429:0.455))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.279:-0.277:-0.275))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.025:0.007:-0.011))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.279:-0.277:-0.275))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.025:0.007:-0.011))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.452:0.452:0.452))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.730:0.730:0.730))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.444:0.444:0.444))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.498:0.498:0.498))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.025:-0.025:-0.025))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.591:-0.591:-0.591))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.276:-0.276:-0.276))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.032:-0.032:-0.032))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.418:0.418:0.418))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.402:0.402:0.402))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.418:0.418:0.418))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.401:0.401:0.401))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.281:-0.281:-0.281))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.028:0.028:0.028))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.281:-0.281:-0.281))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.028:0.028:0.028))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[46\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.733:0.733:0.733) (0.785:0.785:0.785))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.733:0.733:0.733) (0.785:0.785:0.785)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.733:0.733:0.733) (0.785:0.785:0.785)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.733:0.733:0.733) (0.785:0.785:0.785)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.733:0.733:0.733) (0.785:0.785:0.785)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.408:0.411:0.413))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.440:0.450:0.459))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.408:0.411:0.413))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.440:0.449:0.459))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.249:-0.247:-0.245))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.007:-0.011:-0.016))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.249:-0.247:-0.245))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.007:-0.011:-0.016))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.501:0.501:0.501))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.657:0.657:0.657))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.439:0.439:0.439))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.460:0.460:0.460))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.075:-0.075:-0.075))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.492:-0.492:-0.492))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.251:-0.251:-0.251))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.020:-0.020:-0.020))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.416:0.417:0.417))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.449:0.449:0.449))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.415:0.415:0.415))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.449:0.449:0.449))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.252:-0.252:-0.252))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.010:-0.010:-0.010))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.252:-0.252:-0.252))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.010:-0.010:-0.010))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[47\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.666:0.666:0.666) (0.722:0.722:0.722))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.666:0.666:0.666) (0.722:0.722:0.722)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.666:0.666:0.666) (0.722:0.722:0.722)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.666:0.666:0.666) (0.722:0.722:0.722)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.666:0.666:0.666) (0.722:0.722:0.722)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.434:0.437:0.439))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.491:0.501:0.510))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.434:0.437:0.439))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.491:0.500:0.510))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.235:-0.237:-0.238))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.042:-0.049:-0.056))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.235:-0.237:-0.238))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.042:-0.049:-0.056))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.554:0.554:0.554))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.680:0.680:0.680))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.470:0.470:0.470))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.510:0.510:0.510))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.111:-0.111:-0.111))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.483:-0.483:-0.483))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.246:-0.246:-0.246))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.062:-0.062:-0.062))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.437:0.437:0.437))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.494:0.494:0.494))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.437:0.437:0.437))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.494:0.494:0.494))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.238:-0.238:-0.238))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.042:-0.042:-0.042))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.238:-0.238:-0.238))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.042:-0.042:-0.042))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[48\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.687:0.687:0.687) (0.741:0.741:0.741))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.687:0.687:0.687) (0.741:0.741:0.741)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.687:0.687:0.687) (0.741:0.741:0.741)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.687:0.687:0.687) (0.740:0.740:0.740)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.687:0.687:0.687) (0.741:0.741:0.741)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.434:0.434:0.434))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.491:0.492:0.493))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.434:0.434:0.434))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.491:0.492:0.492))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.237:-0.236:-0.236))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.042:-0.043:-0.043))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.237:-0.236:-0.236))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.042:-0.043:-0.043))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.545:0.545:0.545))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.609:0.609:0.609))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.416:0.416:0.416))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.451:0.451:0.451))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.097:-0.097:-0.097))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.409:-0.409:-0.409))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.219:-0.219:-0.219))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.016:-0.016:-0.016))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.437:0.437:0.437))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.492:0.492:0.492))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.438:0.438:0.438))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.492:0.492:0.492))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.238:-0.238:-0.238))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.040:-0.040:-0.040))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.238:-0.238:-0.238))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.040:-0.040:-0.040))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[49\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.674:0.674:0.674) (0.729:0.729:0.729))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.674:0.674:0.674) (0.729:0.729:0.729)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.674:0.674:0.674) (0.729:0.729:0.729)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.674:0.674:0.674) (0.729:0.729:0.729)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.674:0.674:0.674) (0.729:0.729:0.729)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.434:0.437:0.440))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.492:0.506:0.521))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.434:0.437:0.440))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.491:0.506:0.521))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.235:-0.237:-0.238))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.043:-0.053:-0.064))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.235:-0.237:-0.238))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.043:-0.053:-0.064))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.545:0.545:0.545))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.609:0.609:0.609))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.416:0.416:0.416))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.451:0.451:0.451))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.097:-0.097:-0.097))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.409:-0.409:-0.409))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.219:-0.219:-0.219))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.016:-0.016:-0.016))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.437:0.437:0.437))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.494:0.494:0.494))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.437:0.437:0.437))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.494:0.494:0.494))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.238:-0.238:-0.238))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.042:-0.042:-0.042))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.238:-0.238:-0.238))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.042:-0.042:-0.042))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[4\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.550:1.550:1.550) (1.311:1.311:1.311))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.550:1.550:1.550) (1.311:1.311:1.311)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.550:1.550:1.550) (1.311:1.311:1.311)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.550:1.550:1.550) (1.311:1.311:1.311)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.550:1.550:1.550) (1.311:1.311:1.311)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.433:0.435:0.436))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.494:0.510:0.525))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.433:0.435:0.436))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.494:0.509:0.525))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.235:-0.236:-0.237))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.045:-0.056:-0.067))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.235:-0.236:-0.237))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.045:-0.056:-0.067))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.549:0.549:0.549))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.666:0.666:0.666))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.438:0.438:0.438))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.497:0.497:0.497))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.111:-0.111:-0.111))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.471:-0.471:-0.471))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.232:-0.232:-0.232))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.054:-0.054:-0.054))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.451:0.451:0.451))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.631:0.631:0.631))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.451:0.451:0.451))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.631:0.631:0.631))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.216:-0.216:-0.216))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.097:-0.097:-0.097))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.216:-0.216:-0.216))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.097:-0.097:-0.097))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[50\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.690:0.690:0.690) (0.743:0.743:0.743))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.690:0.690:0.690) (0.743:0.743:0.743)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.690:0.690:0.690) (0.743:0.743:0.743)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.690:0.690:0.690) (0.743:0.743:0.743)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.690:0.690:0.690) (0.743:0.743:0.743)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.434:0.434:0.434))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.487:0.492:0.497))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.434:0.434:0.434))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.487:0.492:0.497))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.236:-0.236:-0.235))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.040:-0.043:-0.047))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.236:-0.236:-0.235))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.040:-0.043:-0.047))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.545:0.545:0.545))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.609:0.609:0.609))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.416:0.416:0.416))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.451:0.451:0.451))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.097:-0.097:-0.097))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.409:-0.409:-0.409))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.219:-0.219:-0.219))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.016:-0.016:-0.016))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.437:0.437:0.437))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.493:0.493:0.493))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.437:0.437:0.437))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.493:0.493:0.493))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.238:-0.238:-0.238))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.041:-0.041:-0.041))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.238:-0.238:-0.238))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.041:-0.041:-0.041))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[51\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.688:0.688:0.688) (0.741:0.741:0.741))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.688:0.688:0.688) (0.741:0.741:0.741)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.688:0.688:0.688) (0.741:0.741:0.741)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.688:0.688:0.688) (0.741:0.741:0.741)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.688:0.688:0.688) (0.741:0.741:0.741)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.434:0.437:0.440))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.491:0.500:0.509))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.434:0.437:0.440))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.491:0.500:0.509))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.235:-0.237:-0.238))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.042:-0.049:-0.055))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.235:-0.237:-0.238))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.042:-0.049:-0.055))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.545:0.545:0.545))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.609:0.609:0.609))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.416:0.416:0.416))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.451:0.451:0.451))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.097:-0.097:-0.097))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.409:-0.409:-0.409))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.219:-0.219:-0.219))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.016:-0.016:-0.016))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.437:0.437:0.437))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.495:0.495:0.495))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.437:0.437:0.437))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.495:0.495:0.495))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.238:-0.238:-0.238))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.042:-0.042:-0.042))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.238:-0.238:-0.238))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.042:-0.042:-0.042))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[52\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.673:0.673:0.673) (0.726:0.726:0.726))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.673:0.673:0.673) (0.726:0.726:0.726)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.673:0.673:0.673) (0.726:0.726:0.726)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.673:0.673:0.673) (0.726:0.726:0.726)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.673:0.673:0.673) (0.726:0.726:0.726)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.450:0.450:0.450))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.509:0.510:0.511))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.450:0.450:0.450))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.509:0.510:0.511))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.237:-0.237:-0.236))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.055:-0.055:-0.056))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.237:-0.237:-0.236))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.055:-0.055:-0.056))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.567:0.567:0.567))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.623:0.623:0.623))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.432:0.432:0.432))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.474:0.474:0.474))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.112:-0.112:-0.112))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.409:-0.409:-0.409))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.218:-0.218:-0.218))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.034:-0.034:-0.034))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.456:0.456:0.456))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.516:0.516:0.516))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.456:0.456:0.456))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.516:0.516:0.516))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.237:-0.237:-0.237))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.060:-0.060:-0.060))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.237:-0.237:-0.237))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.060:-0.060:-0.060))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[53\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.742:0.742:0.742) (0.791:0.791:0.791))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.742:0.742:0.742) (0.791:0.791:0.791)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.742:0.742:0.742) (0.791:0.791:0.791)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.742:0.742:0.742) (0.791:0.791:0.791)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.742:0.742:0.742) (0.791:0.791:0.791)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.413:0.417:0.421))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.458:0.471:0.484))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.413:0.417:0.421))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.458:0.471:0.484))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.242:-0.241:-0.240))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.019:-0.027:-0.035))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.242:-0.241:-0.240))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.019:-0.027:-0.035))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.521:0.521:0.521))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.633:0.633:0.633))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.437:0.437:0.437))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.452:0.452:0.452))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.088:-0.088:-0.088))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.458:-0.458:-0.458))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.240:-0.240:-0.240))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.016:-0.016:-0.016))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.419:0.419:0.419))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.462:0.462:0.462))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.418:0.418:0.418))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.462:0.462:0.462))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.017:-0.017:-0.017))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.017:-0.017:-0.017))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[54\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.713:0.713:0.713) (0.768:0.768:0.768))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.713:0.713:0.713) (0.768:0.768:0.768)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.713:0.713:0.713) (0.768:0.768:0.768)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.713:0.713:0.713) (0.768:0.768:0.768)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.713:0.713:0.713) (0.768:0.768:0.768)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.410:0.410:0.410))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.436:0.436:0.436))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.410:0.410:0.410))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.436:0.436:0.436))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.248:-0.248:-0.248))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.002:-0.002:-0.002))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.248:-0.248:-0.248))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.002:-0.002:-0.002))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.505:0.505:0.505))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.629:0.629:0.629))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.418:0.418:0.418))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.436:0.436:0.436))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.071:-0.071:-0.071))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.464:-0.464:-0.464))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.240:-0.240:-0.240))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.003:-0.003:-0.003))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.415:0.415:0.415))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.445:0.445:0.445))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.415:0.415:0.415))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.445:0.445:0.445))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.253:-0.253:-0.253))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.006:-0.006:-0.006))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.253:-0.253:-0.253))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.006:-0.006:-0.006))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[55\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.690:0.690:0.690) (0.746:0.746:0.746))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.690:0.690:0.690) (0.746:0.746:0.746)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.690:0.690:0.690) (0.746:0.746:0.746)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.690:0.690:0.690) (0.746:0.746:0.746)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.690:0.690:0.690) (0.746:0.746:0.746)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.414:0.416:0.417))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.455:0.462:0.468))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.414:0.416:0.417))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.455:0.462:0.468))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.242:-0.242:-0.241))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.018:-0.021:-0.025))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.242:-0.242:-0.241))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.018:-0.021:-0.025))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.521:0.521:0.521))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.633:0.633:0.633))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.437:0.437:0.437))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.452:0.452:0.452))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.088:-0.088:-0.088))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.458:-0.458:-0.458))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.240:-0.240:-0.240))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.016:-0.016:-0.016))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.418:0.418:0.418))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.458:0.459:0.459))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.419:0.419:0.419))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.458:0.459:0.459))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.015:-0.015:-0.015))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.015:-0.015:-0.015))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[56\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.696:0.696:0.696) (0.752:0.752:0.752))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.696:0.696:0.696) (0.752:0.752:0.752)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.696:0.696:0.696) (0.752:0.752:0.752)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.696:0.696:0.696) (0.752:0.752:0.752)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.696:0.696:0.696) (0.752:0.752:0.752)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.416:0.416:0.416))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.454:0.454:0.454))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.416:0.416:0.416))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.454:0.454:0.454))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.243:-0.243:-0.243))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.015:-0.015:-0.015))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.243:-0.243:-0.243))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.015:-0.015:-0.015))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.521:0.521:0.521))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.633:0.633:0.633))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.437:0.437:0.437))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.452:0.452:0.452))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.088:-0.088:-0.088))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.458:-0.458:-0.458))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.240:-0.240:-0.240))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.016:-0.016:-0.016))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.418:0.418:0.418))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.458:0.458:0.458))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.420:0.420:0.420))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.458:0.458:0.458))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.014:-0.014:-0.014))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.014:-0.014:-0.014))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[57\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.641:0.641:0.641) (0.698:0.698:0.698))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.641:0.641:0.641) (0.698:0.698:0.698)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.641:0.641:0.641) (0.698:0.698:0.698)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.641:0.641:0.641) (0.698:0.698:0.698)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.641:0.641:0.641) (0.698:0.698:0.698)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.452:0.453:0.453))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.511:0.517:0.523))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.452:0.453:0.453))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.511:0.517:0.523))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.235:-0.237:-0.238))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.056:-0.061:-0.066))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.235:-0.237:-0.238))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.056:-0.061:-0.066))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.564:0.564:0.564))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.611:0.611:0.611))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.427:0.427:0.427))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.467:0.467:0.467))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.109:-0.109:-0.109))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.397:-0.397:-0.397))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.215:-0.215:-0.215))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.027:-0.027:-0.027))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.455:0.455:0.455))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.513:0.514:0.514))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.455:0.455:0.455))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.513:0.514:0.514))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.237:-0.237:-0.237))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.058:-0.058:-0.058))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.237:-0.237:-0.237))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.058:-0.058:-0.058))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[58\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.659:0.659:0.659) (0.714:0.714:0.714))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.659:0.659:0.659) (0.714:0.714:0.714)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.659:0.659:0.659) (0.714:0.714:0.714)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.659:0.659:0.659) (0.713:0.713:0.713)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.659:0.659:0.659) (0.714:0.714:0.714)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.451:0.452:0.453))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.509:0.514:0.518))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.451:0.452:0.453))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.509:0.513:0.518))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.235:-0.235:-0.234))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.055:-0.058:-0.062))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.235:-0.235:-0.234))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.055:-0.058:-0.062))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.564:0.564:0.564))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.611:0.611:0.611))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.427:0.427:0.427))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.467:0.467:0.467))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.109:-0.109:-0.109))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.397:-0.397:-0.397))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.215:-0.215:-0.215))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.027:-0.027:-0.027))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.455:0.455:0.455))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.513:0.513:0.513))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.455:0.455:0.455))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.513:0.513:0.513))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.238:-0.238:-0.238))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.057:-0.057:-0.057))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.238:-0.238:-0.238))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.057:-0.057:-0.057))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[59\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.709:0.709:0.709) (0.764:0.764:0.764))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.709:0.709:0.709) (0.764:0.764:0.764)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.709:0.709:0.709) (0.764:0.764:0.764)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.709:0.709:0.709) (0.764:0.764:0.764)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.709:0.709:0.709) (0.764:0.764:0.764)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.409:0.408:0.408))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.437:0.443:0.449))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.409:0.408:0.408))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.437:0.443:0.449))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.249:-0.249:-0.250))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.005:-0.008:-0.011))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.249:-0.249:-0.250))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.005:-0.008:-0.011))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.501:0.501:0.501))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.657:0.657:0.657))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.439:0.439:0.439))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.460:0.460:0.460))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.075:-0.075:-0.075))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.492:-0.492:-0.492))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.251:-0.251:-0.251))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.020:-0.020:-0.020))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.415:0.415:0.415))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.441:0.441:0.441))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.415:0.415:0.415))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.441:0.441:0.441))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.254:-0.254:-0.254))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.003:-0.003:-0.003))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.254:-0.254:-0.254))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.003:-0.003:-0.003))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[5\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.728:0.728:0.728) (0.774:0.774:0.774))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.728:0.728:0.728) (0.774:0.774:0.774)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.728:0.728:0.728) (0.774:0.774:0.774)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.728:0.728:0.728) (0.774:0.774:0.774)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.728:0.728:0.728) (0.774:0.774:0.774)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.434:0.435:0.436))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.497:0.512:0.527))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.434:0.435:0.436))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.497:0.512:0.526))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.235:-0.236:-0.238))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.047:-0.057:-0.068))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.235:-0.236:-0.238))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.047:-0.057:-0.068))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.549:0.549:0.549))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.666:0.666:0.666))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.438:0.438:0.438))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.497:0.497:0.497))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.111:-0.111:-0.111))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.471:-0.471:-0.471))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.232:-0.232:-0.232))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.054:-0.054:-0.054))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.452:0.452:0.452))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.609:0.609:0.609))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.452:0.452:0.452))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.609:0.609:0.609))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.224:-0.224:-0.223))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.093:-0.093:-0.093))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.224:-0.224:-0.223))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.093:-0.093:-0.093))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[60\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.706:0.706:0.706) (0.762:0.762:0.762))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.706:0.706:0.706) (0.762:0.762:0.762)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.706:0.706:0.706) (0.762:0.762:0.762)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.706:0.706:0.706) (0.762:0.762:0.762)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.706:0.706:0.706) (0.762:0.762:0.762)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.409:0.408:0.408))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.437:0.443:0.449))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.409:0.408:0.408))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.437:0.443:0.449))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.249:-0.249:-0.250))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.005:-0.008:-0.011))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.249:-0.249:-0.250))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.005:-0.008:-0.011))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.501:0.501:0.501))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.657:0.657:0.657))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.439:0.439:0.439))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.460:0.460:0.460))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.075:-0.075:-0.075))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.492:-0.492:-0.492))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.251:-0.251:-0.251))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.020:-0.020:-0.020))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.415:0.415:0.415))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.439:0.439:0.439))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.415:0.415:0.415))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.439:0.439:0.439))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.253:-0.253:-0.253))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.002:-0.002:-0.002))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.253:-0.253:-0.253))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.002:-0.002:-0.002))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[61\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.703:0.703:0.703) (0.758:0.758:0.758))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.703:0.703:0.703) (0.758:0.758:0.758)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.703:0.703:0.703) (0.758:0.758:0.758)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.703:0.703:0.703) (0.758:0.758:0.758)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.703:0.703:0.703) (0.758:0.758:0.758)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.415:0.414:0.414))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.454:0.460:0.465))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.415:0.414:0.414))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.454:0.459:0.464))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.242:-0.242:-0.242))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.016:-0.019:-0.023))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.242:-0.242:-0.242))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.016:-0.019:-0.023))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.521:0.521:0.521))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.646:0.646:0.646))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.443:0.443:0.443))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.463:0.463:0.463))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.089:-0.089:-0.089))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.471:-0.471:-0.471))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.243:-0.243:-0.243))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.024:-0.024:-0.024))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.418:0.418:0.418))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.458:0.458:0.458))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.420:0.420:0.420))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.458:0.458:0.458))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.015:-0.015:-0.015))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.015:-0.015:-0.015))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[62\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.738:0.738:0.738) (0.788:0.788:0.788))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.738:0.738:0.738) (0.788:0.788:0.788)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.738:0.738:0.738) (0.788:0.788:0.788)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.738:0.738:0.738) (0.788:0.788:0.788)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.738:0.738:0.738) (0.788:0.788:0.788)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.415:0.414:0.414))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.455:0.459:0.463))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.415:0.414:0.414))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.455:0.459:0.462))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.242:-0.242:-0.242))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.017:-0.019:-0.022))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.242:-0.242:-0.242))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.017:-0.019:-0.022))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.521:0.521:0.521))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.646:0.646:0.646))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.443:0.443:0.443))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.463:0.463:0.463))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.089:-0.089:-0.089))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.471:-0.471:-0.471))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.243:-0.243:-0.243))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.024:-0.024:-0.024))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.418:0.418:0.418))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.459:0.459:0.459))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.419:0.419:0.419))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.459:0.459:0.459))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.015:-0.015:-0.015))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.015:-0.015:-0.015))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[63\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.703:0.703:0.703) (0.757:0.757:0.757))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.703:0.703:0.703) (0.757:0.757:0.757)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.703:0.703:0.703) (0.757:0.757:0.757)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.703:0.703:0.703) (0.757:0.757:0.757)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.703:0.703:0.703) (0.757:0.757:0.757)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.414:0.414:0.414))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.457:0.462:0.467))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.414:0.414:0.414))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.457:0.462:0.467))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.242:-0.242:-0.242))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.019:-0.022:-0.024))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.242:-0.242:-0.242))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.019:-0.022:-0.024))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.521:0.521:0.521))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.646:0.646:0.646))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.443:0.443:0.443))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.463:0.463:0.463))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.089:-0.089:-0.089))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.471:-0.471:-0.471))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.243:-0.243:-0.243))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.024:-0.024:-0.024))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.420:0.420:0.420))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.463:0.463:0.463))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.419:0.419:0.419))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.463:0.463:0.463))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.018:-0.018:-0.018))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.018:-0.018:-0.018))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[64\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.735:0.735:0.735) (0.787:0.787:0.787))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.735:0.735:0.735) (0.787:0.787:0.787)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.735:0.735:0.735) (0.787:0.787:0.787)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.735:0.735:0.735) (0.787:0.787:0.787)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.735:0.735:0.735) (0.787:0.787:0.787)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.408:0.408:0.408))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.439:0.443:0.448))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.408:0.408:0.408))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.439:0.443:0.448))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.249:-0.249:-0.249))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.006:-0.008:-0.010))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.249:-0.249:-0.249))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.006:-0.008:-0.010))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.494:0.494:0.494))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.570:0.570:0.570))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.384:0.384:0.384))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.394:0.394:0.394))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.055:-0.055:-0.055))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.405:-0.405:-0.405))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.225:-0.225:-0.225))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.032:0.032:0.032))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.415:0.415:0.415))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.440:0.440:0.440))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.415:0.415:0.415))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.440:0.440:0.440))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.254:-0.254:-0.254))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.003:-0.003:-0.003))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.254:-0.254:-0.254))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.003:-0.003:-0.003))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[65\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.704:0.704:0.704) (0.758:0.758:0.758))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.704:0.704:0.704) (0.758:0.758:0.758)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.704:0.704:0.704) (0.758:0.758:0.758)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.704:0.704:0.704) (0.758:0.758:0.758)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.704:0.704:0.704) (0.758:0.758:0.758)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.414:0.414:0.413))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.456:0.460:0.464))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.414:0.414:0.413))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.456:0.460:0.464))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.242:-0.242:-0.242))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.018:-0.020:-0.023))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.242:-0.242:-0.242))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.018:-0.020:-0.023))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.521:0.521:0.521))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.646:0.646:0.646))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.443:0.443:0.443))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.463:0.463:0.463))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.089:-0.089:-0.089))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.471:-0.471:-0.471))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.243:-0.243:-0.243))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.024:-0.024:-0.024))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.419:0.419:0.419))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.461:0.461:0.461))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.418:0.418:0.418))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.461:0.461:0.461))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.016:-0.016:-0.016))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.016:-0.016:-0.016))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[66\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.716:0.716:0.716) (0.769:0.769:0.769))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.716:0.716:0.716) (0.769:0.769:0.769)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.716:0.716:0.716) (0.769:0.769:0.769)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.716:0.716:0.716) (0.769:0.769:0.769)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.716:0.716:0.716) (0.769:0.769:0.769)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.413:0.414:0.415))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.458:0.463:0.468))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.413:0.414:0.415))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.458:0.463:0.467))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.242:-0.242:-0.242))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.019:-0.022:-0.025))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.242:-0.242:-0.242))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.019:-0.022:-0.025))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.521:0.521:0.521))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.646:0.646:0.646))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.443:0.443:0.443))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.463:0.463:0.463))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.089:-0.089:-0.089))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.471:-0.471:-0.471))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.243:-0.243:-0.243))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.024:-0.024:-0.024))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.418:0.418:0.418))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.459:0.459:0.460))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.419:0.419:0.419))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.459:0.459:0.460))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.015:-0.015:-0.015))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.015:-0.015:-0.015))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[67\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.771:0.771:0.771) (0.823:0.823:0.823))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.771:0.771:0.771) (0.823:0.823:0.823)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.771:0.771:0.771) (0.823:0.823:0.823)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.771:0.771:0.771) (0.823:0.823:0.823)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.771:0.771:0.771) (0.823:0.823:0.823)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.416:0.415:0.414))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.393:0.399:0.406))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.416:0.415:0.414))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.400:0.404:0.407))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.279:-0.279:-0.279))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.028:0.022:0.016))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.279:-0.279:-0.279))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.028:0.022:0.016))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.452:0.452:0.452))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.730:0.730:0.730))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.444:0.444:0.444))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.498:0.498:0.498))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.025:-0.025:-0.025))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.591:-0.591:-0.591))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.276:-0.276:-0.276))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.032:-0.032:-0.032))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.418:0.418:0.418))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.401:0.401:0.401))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.418:0.418:0.418))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.400:0.400:0.400))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.280:-0.280:-0.280))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.029:0.029:0.029))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.280:-0.280:-0.280))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.029:0.029:0.029))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[68\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.723:0.723:0.723) (0.776:0.776:0.776))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.723:0.723:0.723) (0.776:0.776:0.776)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.723:0.723:0.723) (0.776:0.776:0.776)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.723:0.723:0.723) (0.776:0.776:0.776)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.723:0.723:0.723) (0.776:0.776:0.776)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.410:0.410:0.411))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.448:0.450:0.453))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.410:0.410:0.411))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.448:0.450:0.452))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.247:-0.247:-0.246))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.012:-0.013:-0.014))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.247:-0.247:-0.246))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.012:-0.013:-0.014))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.496:0.496:0.496))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.731:0.731:0.731))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.455:0.455:0.455))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.545:0.545:0.545))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.062:-0.062:-0.062))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.562:-0.562:-0.562))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.254:-0.254:-0.254))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.071:-0.071:-0.071))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.416:0.416:0.416))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.448:0.448:0.448))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.416:0.416:0.416))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.448:0.448:0.448))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.251:-0.251:-0.251))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.007:-0.007:-0.007))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.251:-0.251:-0.251))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.007:-0.007:-0.007))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[69\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.748:0.748:0.748) (0.803:0.803:0.803))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.748:0.748:0.748) (0.803:0.803:0.803)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.748:0.748:0.748) (0.803:0.803:0.803)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.748:0.748:0.748) (0.803:0.803:0.803)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.748:0.748:0.748) (0.803:0.803:0.803)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.415:0.414:0.413))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.396:0.413:0.429))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.415:0.414:0.413))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.403:0.416:0.430))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.279:-0.278:-0.277))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.025:0.012:-0.001))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.279:-0.278:-0.277))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.025:0.012:-0.001))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.452:0.452:0.452))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.730:0.730:0.730))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.444:0.444:0.444))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.498:0.498:0.498))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.025:-0.025:-0.025))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.591:-0.591:-0.591))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.276:-0.276:-0.276))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.032:-0.032:-0.032))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.418:0.418:0.418))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.400:0.400:0.400))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.418:0.418:0.418))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.400:0.400:0.400))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.280:-0.280:-0.280))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.030:0.030:0.030))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.280:-0.280:-0.280))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.030:0.030:0.030))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[6\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.434:1.434:1.434) (1.238:1.238:1.238))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.434:1.434:1.434) (1.238:1.238:1.238)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.434:1.434:1.434) (1.238:1.238:1.238)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.434:1.434:1.434) (1.238:1.238:1.238)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.434:1.434:1.434) (1.238:1.238:1.238)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.433:0.433:0.433))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.490:0.490:0.490))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.433:0.433:0.433))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.490:0.490:0.490))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.236:-0.236:-0.236))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.041:-0.041:-0.041))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.236:-0.236:-0.236))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.041:-0.041:-0.041))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.554:0.554:0.554))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.742:0.742:0.742))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.465:0.465:0.465))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.578:0.578:0.578))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.112:-0.112:-0.112))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.543:-0.543:-0.543))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.100:-0.100:-0.100))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.438:0.438:0.438))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.496:0.496:0.496))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.436:0.436:0.436))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.496:0.496:0.496))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.239:-0.239:-0.239))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.044:-0.044:-0.044))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.239:-0.239:-0.239))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.044:-0.044:-0.044))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[7\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.583:1.583:1.583) (1.351:1.351:1.351))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.583:1.583:1.583) (1.351:1.351:1.351)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.583:1.583:1.583) (1.351:1.351:1.351)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.583:1.583:1.583) (1.351:1.351:1.351)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.583:1.583:1.583) (1.351:1.351:1.351)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.406:0.406:0.406))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.427:0.427:0.427))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.406:0.406:0.406))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.428:0.428:0.428))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.254:-0.254:-0.254))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.002:0.002:0.002))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.254:-0.254:-0.254))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.002:0.002:0.002))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.466:0.466:0.466))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.780:0.780:0.780))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.454:0.454:0.454))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.597:0.597:0.597))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.026:-0.026:-0.026))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.622:-0.622:-0.622))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.246:-0.246:-0.246))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.088:-0.088:-0.088))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.424:0.424:0.424))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.525:0.525:0.525))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.424:0.424:0.424))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.525:0.525:0.525))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.242:-0.242:-0.242))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.045:-0.045:-0.045))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.242:-0.242:-0.242))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.045:-0.045:-0.045))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[8\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.549:1.549:1.549) (1.344:1.344:1.344))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.549:1.549:1.549) (1.344:1.344:1.344)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.549:1.549:1.549) (1.344:1.344:1.344)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.549:1.549:1.549) (1.344:1.344:1.344)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.549:1.549:1.549) (1.344:1.344:1.344)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.429:0.429:0.429))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.423:0.423:0.423))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.429:0.429:0.429))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.427:0.427:0.427))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.288:-0.288:-0.288))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.008:0.008:0.008))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.288:-0.288:-0.288))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.008:0.008:0.008))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.420:0.420:0.420))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.797:0.797:0.797))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.453:0.453:0.453))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.553:0.553:0.553))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.003:0.003:0.003))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.662:-0.662:-0.662))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.280:-0.280:-0.280))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.052:-0.052:-0.052))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.438:0.438:0.438))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.498:0.498:0.498))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.432:0.431:0.431))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.498:0.498:0.498))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.281:-0.281:-0.281))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.014:-0.014:-0.014))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.281:-0.281:-0.281))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.014:-0.014:-0.014))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[9\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.500:1.500:1.500) (1.298:1.298:1.298))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.500:1.500:1.500) (1.298:1.298:1.298)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.500:1.500:1.500) (1.298:1.298:1.298)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.500:1.500:1.500) (1.298:1.298:1.298)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.500:1.500:1.500) (1.298:1.298:1.298)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.406:0.406:0.406))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.437:0.437:0.437))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.406:0.406:0.406))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.437:0.437:0.437))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.252:-0.252:-0.252))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.002:-0.002:-0.002))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.252:-0.252:-0.252))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.002:-0.002:-0.002))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.490:0.490:0.490))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.715:0.715:0.715))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.430:0.430:0.430))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.518:0.518:0.518))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.068:-0.068:-0.068))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.558:-0.558:-0.558))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.253:-0.253:-0.253))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.051:-0.051:-0.051))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.424:0.424:0.424))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.528:0.528:0.528))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.424:0.424:0.424))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.528:0.528:0.528))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.241:-0.241:-0.241))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.046:-0.046:-0.046))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.241:-0.241:-0.241))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.046:-0.046:-0.046))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__dlyb_1")
(INSTANCE input1)
(DELAY
(ABSOLUTE
(IOPATH I Z (1.153:1.153:1.153) (1.387:1.387:1.387))
)
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__buf_1")
(INSTANCE input2)
(DELAY
(ABSOLUTE
(IOPATH I Z (2.112:2.112:2.112) (1.552:1.552:1.552))
)
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__dlyb_1")
(INSTANCE input3)
(DELAY
(ABSOLUTE
(IOPATH I Z (0.957:0.957:0.957) (1.250:1.250:1.250))
)
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__dlyb_1")
(INSTANCE input4)
(DELAY
(ABSOLUTE
(IOPATH I Z (0.904:0.904:0.904) (1.040:1.040:1.040))
)
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__dlyb_1")
(INSTANCE input5)
(DELAY
(ABSOLUTE
(IOPATH I Z (0.898:0.898:0.898) (1.213:1.213:1.213))
)
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__clkbuf_3")
(INSTANCE output6)
(DELAY
(ABSOLUTE
(IOPATH I Z (0.422:0.422:0.422) (0.433:0.433:0.433))
)
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__clkbuf_3")
(INSTANCE output7)
(DELAY
(ABSOLUTE
(IOPATH I Z (0.420:0.420:0.420) (0.431:0.431:0.431))
)
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__clkbuf_4")
(INSTANCE fanout8)
(DELAY
(ABSOLUTE
(IOPATH I Z (0.648:0.648:0.648) (0.649:0.649:0.649))
)
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__dlyc_1")
(INSTANCE fanout9)
(DELAY
(ABSOLUTE
(IOPATH I Z (1.700:1.700:1.700) (1.981:1.981:1.981))
)
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__dlyb_1")
(INSTANCE fanout10)
(DELAY
(ABSOLUTE
(IOPATH I Z (1.426:1.426:1.426) (1.674:1.674:1.674))
)
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__clkbuf_2")
(INSTANCE fanout11)
(DELAY
(ABSOLUTE
(IOPATH I Z (0.844:0.844:0.844) (0.839:0.839:0.839))
)
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__buf_1")
(INSTANCE fanout12)
(DELAY
(ABSOLUTE
(IOPATH I Z (0.971:0.971:0.971) (1.065:1.065:1.065))
)
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__clkbuf_1")
(INSTANCE fanout13)
(DELAY
(ABSOLUTE
(IOPATH I Z (0.736:0.736:0.736) (0.743:0.743:0.743))
)
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__dlyb_1")
(INSTANCE fanout14)
(DELAY
(ABSOLUTE
(IOPATH I Z (0.961:0.961:0.961) (1.152:1.152:1.152))
)
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__dlyc_1")
(INSTANCE fanout15)
(DELAY
(ABSOLUTE
(IOPATH I Z (1.869:1.869:1.869) (2.036:2.036:2.036))
)
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__clkbuf_1")
(INSTANCE fanout16)
(DELAY
(ABSOLUTE
(IOPATH I Z (0.774:0.774:0.774) (0.782:0.782:0.782))
)
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__dlyc_1")
(INSTANCE fanout17)
(DELAY
(ABSOLUTE
(IOPATH I Z (1.979:1.979:1.979) (2.187:2.187:2.187))
)
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__dlyb_1")
(INSTANCE fanout18)
(DELAY
(ABSOLUTE
(IOPATH I Z (1.370:1.370:1.370) (1.476:1.476:1.476))
)
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__dlyb_1")
(INSTANCE fanout19)
(DELAY
(ABSOLUTE
(IOPATH I Z (1.169:1.169:1.169) (1.376:1.376:1.376))
)
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__dlyb_1")
(INSTANCE fanout20)
(DELAY
(ABSOLUTE
(IOPATH I Z (1.270:1.270:1.270) (1.657:1.657:1.657))
)
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__clkbuf_1")
(INSTANCE fanout21)
(DELAY
(ABSOLUTE
(IOPATH I Z (0.617:0.617:0.617) (0.652:0.652:0.652))
)
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__dlyc_1")
(INSTANCE fanout22)
(DELAY
(ABSOLUTE
(IOPATH I Z (2.012:2.012:2.012) (2.598:2.598:2.598))
)
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__clkbuf_1")
(INSTANCE fanout23)
(DELAY
(ABSOLUTE
(IOPATH I Z (1.470:1.470:1.470) (1.565:1.565:1.565))
)
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