rtl: Add extra serv instance
diff --git a/.github/workflows/user_project_ci.yml b/.github/workflows/user_project_ci.yml index 1a70f6f..9204fa2 100644 --- a/.github/workflows/user_project_ci.yml +++ b/.github/workflows/user_project_ci.yml
@@ -71,6 +71,11 @@ run: | make serv_1 find openlane/serv_1/runs/serv_1/ + + - name: harden serv_2 + run: | + make serv_2 + find openlane/serv_2/runs/serv_2/ - name: harden user_project_wrapper run: |
diff --git a/openlane/serv_2/config.tcl b/openlane/serv_2/config.tcl new file mode 100644 index 0000000..20618d0 --- /dev/null +++ b/openlane/serv_2/config.tcl
@@ -0,0 +1,85 @@ +# SPDX-FileCopyrightText: 2020 Efabless Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# SPDX-License-Identifier: Apache-2.0 + +set script_dir [file dirname [file normalize [info script]/../../]] + +set ::env(DESIGN_NAME) serv_2 +set ::env(DESIGN_IS_CORE) 0 + +set ::env(PDK) "gf180mcuC" +set ::env(STD_CELL_LIBRARY) "gf180mcu_fd_sc_mcu7t5v0" +set ::env(RT_MAX_LAYER) {Metal4} + +#set ::env(RUN_KLAYOUT) 0 +set ::env(CLOCK_TREE_SYNTH) 1 +set ::env(CLOCK_PORT) "" +set ::env(CLOCK_NET) {clk serv_clk} +set ::env(CLOCK_PERIOD) 50 +set ::env(SYNTH_MAX_FANOUT) 16 + +set ::env(FP_IO_HLENGTH) 2 +set ::env(FP_IO_VLENGTH) 2 + +## Floorplan +set ::env(FP_SIZING) absolute +set ::env(DIE_AREA) "0 0 700 600" + +## Placement +set ::env(PL_BASIC_PLACEMENT) 0 +set ::env(PL_TARGET_DENSITY) 0.55 + +# Enable all optimizations +set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0 +set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 1 +set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) 1 + +# Diode insertion strategy number 4 for gf-180mcu +set ::env(DIODE_INSERTION_STRATEGY) 4 + +set ::env(VDD_NETS) [list {vdd}] +set ::env(GND_NETS) [list {vss}] + +set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg + +set ::env(DESIGN_DIR) $script_dir/../../verilog + +set ::env(VERILOG_FILES) "\ + $::env(DESIGN_DIR)/rtl/defines.v \ + $::env(DESIGN_DIR)/rtl/serv_2.v \ + $::env(DESIGN_DIR)/rtl/scanchain.v \ + $::env(DESIGN_DIR)/blocks/serv/rtl/serv_top.v \ + $::env(DESIGN_DIR)/blocks/serv/rtl/serv_synth_wrapper.v \ + $::env(DESIGN_DIR)/blocks/serv/rtl/serv_mem_if.v \ + $::env(DESIGN_DIR)/blocks/serv/rtl/serv_rf_if.v \ + $::env(DESIGN_DIR)/blocks/serv/rtl/serv_rf_top.v \ + $::env(DESIGN_DIR)/blocks/serv/rtl/serv_rf_ram.v \ + $::env(DESIGN_DIR)/blocks/serv/rtl/serv_rf_ram_if.v \ + $::env(DESIGN_DIR)/blocks/serv/rtl/serv_alu.v \ + $::env(DESIGN_DIR)/blocks/serv/rtl/serv_ctrl.v \ + $::env(DESIGN_DIR)/blocks/serv/rtl/serv_bufreg2.v \ + $::env(DESIGN_DIR)/blocks/serv/rtl/serv_bufreg.v \ + $::env(DESIGN_DIR)/blocks/serv/rtl/serv_immdec.v \ + $::env(DESIGN_DIR)/blocks/serv/rtl/serv_decode.v \ + $::env(DESIGN_DIR)/blocks/serv/rtl/serv_compdec.v \ + $::env(DESIGN_DIR)/blocks/serv/rtl/serv_aligner.v \ + $::env(DESIGN_DIR)/blocks/serv/rtl/serv_state.v \ + $::env(DESIGN_DIR)/blocks/serv/rtl/serv_csr.v \ + $::env(DESIGN_DIR)/blocks/serv/servant/servant_arbiter.v \ + $::env(DESIGN_DIR)/blocks/serv/servant/servant_mux.v" + +set ::env(VERILOG_FILES_BLACKBOX) "\ + $::env(DESIGN_DIR)/rtl/bb/gf180mcu_fd_sc_mcu7t5v0.v" + +set ::env(RUN_CVC) 1
diff --git a/openlane/serv_2/pin_order.cfg b/openlane/serv_2/pin_order.cfg new file mode 100644 index 0000000..4310156 --- /dev/null +++ b/openlane/serv_2/pin_order.cfg
@@ -0,0 +1,8 @@ +#BUS_SORT + +#E +io_in.* +io_out.* +io_oeb.* + +
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl index 99d4797..e5fd617 100644 --- a/openlane/user_project_wrapper/config.tcl +++ b/openlane/user_project_wrapper/config.tcl
@@ -42,7 +42,8 @@ ### Macro PDN Connections set ::env(FP_PDN_MACRO_HOOKS) "\ u_serv_0 vdd vss vdd vss, \ - u_serv_1 vdd vss vdd vss" + u_serv_1 vdd vss vdd vss, \ + u_serv_2 vdd vss vdd vss" ### Macro Placement set ::env(MACRO_PLACEMENT_CFG) $::env(DESIGN_DIR)/macro.cfg @@ -51,15 +52,18 @@ set ::env(VERILOG_FILES_BLACKBOX) "\ $::env(CARAVEL_ROOT)/verilog/rtl/defines.v \ $::env(DESIGN_DIR)/../../verilog/rtl/serv_0.v \ - $::env(DESIGN_DIR)/../../verilog/rtl/serv_1.v" + $::env(DESIGN_DIR)/../../verilog/rtl/serv_1.v \ + $::env(DESIGN_DIR)/../../verilog/rtl/serv_2.v" set ::env(EXTRA_LEFS) "\ $::env(DESIGN_DIR)/../../lef/serv_0.lef \ - $::env(DESIGN_DIR)/../../lef/serv_1.lef" + $::env(DESIGN_DIR)/../../lef/serv_1.lef \ + $::env(DESIGN_DIR)/../../lef/serv_2.lef" set ::env(EXTRA_GDS_FILES) "\ $::env(DESIGN_DIR)/../../gds/serv_0.gds \ - $::env(DESIGN_DIR)/../../gds/serv_1.gds" + $::env(DESIGN_DIR)/../../gds/serv_1.gds \ + $::env(DESIGN_DIR)/../../gds/serv_2.gds" set ::env(RT_MAX_LAYER) {Metal4}
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg index 8c5bf85..8e1c957 100644 --- a/openlane/user_project_wrapper/macro.cfg +++ b/openlane/user_project_wrapper/macro.cfg
@@ -1,2 +1,3 @@ u_serv_0 500 500 N -u_serv_1 500 1250 N \ No newline at end of file +u_serv_1 500 1250 N +u_serv_2 500 2000 N \ No newline at end of file
diff --git a/verilog/rtl/serv_2.v b/verilog/rtl/serv_2.v new file mode 100644 index 0000000..9cfd631 --- /dev/null +++ b/verilog/rtl/serv_2.v
@@ -0,0 +1,139 @@ +// Copyright 2022 Google LLC. +// SPDX-License-Identifier: Apache-2.0 +`default_nettype none + +// tiny_user_project top module instance +// generated by configure.py +module serv_2( +`ifdef USE_POWER_PINS + inout vdd, // User area 5.0V supply + inout vss, // User area ground +`endif + + // IOs + input [4:0] io_in, + output [4:0] io_out, + output [4:0] io_oeb, +); + + wire clk = io_in[0]; + wire reset = io_in[1]; + + wire data = io_in[2]; + wire scan_select = io_in[3]; + wire serv_clk = io_in[4]; + + wire timer_irq; + + wire [31:0] wb_ibus_adr; + wire [31:0] wb_ibus_rdt; + wire wb_ibus_cyc; + wire wb_ibus_ack; + + wire [31:0] wb_dbus_adr; + wire [31:0] wb_dbus_dat; + wire [3:0] wb_dbus_sel; + wire [31:0] wb_dbus_rdt; + wire wb_dbus_we; + wire wb_dbus_cyc; + wire wb_dbus_ack; + + wire [31:0] wb_mem_adr; + wire [31:0] wb_mem_dat; + wire [3:0] wb_mem_sel; + wire [31:0] wb_mem_rdt; + wire wb_mem_we; + wire wb_mem_cyc; + wire wb_mem_ack; + + servant_arbiter u_arbiter ( + .i_wb_cpu_dbus_adr (wb_dbus_adr), + .i_wb_cpu_dbus_dat (wb_dbus_dat), + .i_wb_cpu_dbus_sel (wb_dbus_sel), + .i_wb_cpu_dbus_we (wb_dbus_we ), + .i_wb_cpu_dbus_cyc (wb_dbus_cyc), + .o_wb_cpu_dbus_rdt (wb_dbus_rdt), + .o_wb_cpu_dbus_ack (wb_dbus_ack), + + .i_wb_cpu_ibus_adr (wb_ibus_adr), + .i_wb_cpu_ibus_cyc (wb_ibus_cyc), + .o_wb_cpu_ibus_rdt (wb_ibus_rdt), + .o_wb_cpu_ibus_ack (wb_ibus_ack), + + .o_wb_cpu_adr (wb_mem_adr), + .o_wb_cpu_dat (wb_mem_dat), + .o_wb_cpu_sel (wb_mem_sel), + .o_wb_cpu_we (wb_mem_we ), + .o_wb_cpu_cyc (wb_mem_cyc), + .i_wb_cpu_rdt (wb_mem_rdt), + .i_wb_cpu_ack (wb_mem_ack) + ); + + + + serv_rf_top #( + .RESET_PC(32'd0), + .COMPRESSED(1), + .ALIGN(1), + .MDU(0), + .PRE_REGISTER(1), + .RESET_STRATEGY("MINI"), + .WITH_CSR(1), + .RF_WIDTH(8)) + u_cpu + ( + .clk (serv_clk), + .i_rst (reset), + .i_timer_irq (timer_irq), + + .o_ibus_adr (wb_ibus_adr), + .o_ibus_cyc (wb_ibus_cyc), + .i_ibus_rdt (wb_ibus_rdt), + .i_ibus_ack (wb_ibus_ack), + + .o_dbus_adr (wb_dbus_adr), + .o_dbus_dat (wb_dbus_dat), + .o_dbus_sel (wb_dbus_sel), + .o_dbus_we (wb_dbus_we), + .o_dbus_cyc (wb_dbus_cyc), + .i_dbus_rdt (wb_dbus_rdt), + .i_dbus_ack (wb_dbus_ack) + ); + + + scanchain_local #( + .SCAN_LENGTH(70)) + u_scanchain_local + ( + // Inputs from TinyTapeout scanchain to our internal scanchain + .clk_in (clk), + .data_in (data), + .scan_select_in (scan_select), + + // Pass all signals out from our internal scanchain, only really need data + .clk_out (io_out[0]), + .data_out (io_out[1]), + .scan_select_out (), + + // data + .module_data_out ({ + // Bus interface + wb_mem_adr[31:0], // 32 + wb_mem_dat, // 32 + wb_mem_sel, // 4 + wb_mem_we, // 1 + wb_mem_cyc}), // 1 + + .module_data_in ({ + // Bus interface + wb_mem_rdt, // 32 + wb_mem_ack, // 1 + timer_irq}) // 1 + ); + +// all output enabled +assign io_oeb[4:0] = 5'b0; + +endmodule // tiny_user_project + +`default_nettype wire \ No newline at end of file
diff --git a/verilog/rtl/user_defines.v b/verilog/rtl/user_defines.v index 7622d93..fe6d1bb 100644 --- a/verilog/rtl/user_defines.v +++ b/verilog/rtl/user_defines.v
@@ -54,27 +54,30 @@ // generated by configure.py -`define USER_CONFIG_GPIO_5_INIT `GPIO_MODE_INVALID -`define USER_CONFIG_GPIO_6_INIT `GPIO_MODE_INVALID -`define USER_CONFIG_GPIO_7_INIT `GPIO_MODE_INVALID +`define USER_CONFIG_GPIO_5_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL +`define USER_CONFIG_GPIO_6_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL +`define USER_CONFIG_GPIO_7_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL `define USER_CONFIG_GPIO_8_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL `define USER_CONFIG_GPIO_9_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL -`define USER_CONFIG_GPIO_10_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL -`define USER_CONFIG_GPIO_11_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL +`define USER_CONFIG_GPIO_10_INIT `GPIO_MODE_USER_STD_OUTPUT +`define USER_CONFIG_GPIO_11_INIT `GPIO_MODE_USER_STD_OUTPUT + `define USER_CONFIG_GPIO_12_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL -`define USER_CONFIG_GPIO_13_INIT `GPIO_MODE_USER_STD_OUTPUT -`define USER_CONFIG_GPIO_14_INIT `GPIO_MODE_USER_STD_OUTPUT -`define USER_CONFIG_GPIO_15_INIT `GPIO_MODE_INVALID -`define USER_CONFIG_GPIO_16_INIT `GPIO_MODE_INVALID -`define USER_CONFIG_GPIO_17_INIT `GPIO_MODE_INVALID -`define USER_CONFIG_GPIO_18_INIT `GPIO_MODE_INVALID -`define USER_CONFIG_GPIO_19_INIT `GPIO_MODE_INVALID -`define USER_CONFIG_GPIO_20_INIT `GPIO_MODE_INVALID -`define USER_CONFIG_GPIO_21_INIT `GPIO_MODE_INVALID -`define USER_CONFIG_GPIO_22_INIT `GPIO_MODE_INVALID -`define USER_CONFIG_GPIO_23_INIT `GPIO_MODE_INVALID -`define USER_CONFIG_GPIO_24_INIT `GPIO_MODE_INVALID -`define USER_CONFIG_GPIO_25_INIT `GPIO_MODE_INVALID +`define USER_CONFIG_GPIO_13_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL +`define USER_CONFIG_GPIO_14_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL +`define USER_CONFIG_GPIO_15_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL +`define USER_CONFIG_GPIO_16_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL +`define USER_CONFIG_GPIO_17_INIT `GPIO_MODE_USER_STD_OUTPUT +`define USER_CONFIG_GPIO_18_INIT `GPIO_MODE_USER_STD_OUTPUT + +`define USER_CONFIG_GPIO_19_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL +`define USER_CONFIG_GPIO_20_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL +`define USER_CONFIG_GPIO_21_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL +`define USER_CONFIG_GPIO_22_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL +`define USER_CONFIG_GPIO_23_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL +`define USER_CONFIG_GPIO_24_INIT `GPIO_MODE_USER_STD_OUTPUT +`define USER_CONFIG_GPIO_25_INIT `GPIO_MODE_USER_STD_OUTPUT + `define USER_CONFIG_GPIO_26_INIT `GPIO_MODE_INVALID `define USER_CONFIG_GPIO_27_INIT `GPIO_MODE_INVALID `define USER_CONFIG_GPIO_28_INIT `GPIO_MODE_INVALID
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v index 375b780..5a1b5fc 100644 --- a/verilog/rtl/user_project_wrapper.v +++ b/verilog/rtl/user_project_wrapper.v
@@ -77,9 +77,9 @@ `endif // IO Pads - .io_in (io_in[12:8]), - .io_out(io_out[12:8]), - .io_oeb(io_oeb[12:8]) + .io_in (io_in[9:5]), + .io_out(io_out[11:10]), + .io_oeb(io_oeb[11:10]) ); serv_1 u_serv_1 ( @@ -89,9 +89,21 @@ `endif // IO Pads - .io_in (io_in[17:13]), - .io_out(io_out[17:13]), - .io_oeb(io_oeb[17:13]) + .io_in (io_in[16:12]), + .io_out(io_out[18:17]), + .io_oeb(io_oeb[18:17]) +); + +serv_2 u_serv_2 ( +`ifdef USE_POWER_PINS + .vdd(vdd), + .vss(vss), +`endif + // IO Pads + + .io_in (io_in[23:19]), + .io_out(io_out[25:24]), + .io_oeb(io_oeb[25:24]) ); endmodule // user_project_wrapper