commit | 209d84dbde00810ba3cdccec906801d82d601b2a | [log] [tgz] |
---|---|---|
author | Greg Davill <greg.davill@gmail.com> | Sun Dec 04 18:19:40 2022 +1030 |
committer | Greg Davill <greg.davill@gmail.com> | Sun Dec 04 18:19:40 2022 +1030 |
tree | 8eabc11f92510beb48836b4a978a1bb66cd09d33 | |
parent | 6254d133ca6979a493f0d12495f758135423bc22 [diff] |
cfg: update openlane configs
An award winning CPU design fit into the GF180 MPW0 Shuttle.
To keep the design simple this project places a Serv CPU with a scan-chain around it connecting it's wishbone bus which is a combination of data and instructions out via I/O pins.
Another I/O pin is responsible for handling clock and reset. Operation will run as follows:
In this manner we should be able to implement external peripherals like UARTs, timers, and GPIOs. The external controller can be a microcontroller, FPGA, or the caravel harness SoC.