cfg: update openlane configs
diff --git a/openlane/tiny_user_project/config.tcl b/openlane/tiny_user_project/config.tcl index 8a33cad..926e4cd 100644 --- a/openlane/tiny_user_project/config.tcl +++ b/openlane/tiny_user_project/config.tcl
@@ -20,9 +20,9 @@ set ::env(PDK) "gf180mcuC" set ::env(STD_CELL_LIBRARY) "gf180mcu_fd_sc_mcu7t5v0" -set ::env(RT_MAX_LAYER) "Metal4" +set ::env(RT_MAX_LAYER) {Metal4} -set ::env(RUN_KLAYOUT) 0 +#set ::env(RUN_KLAYOUT) 0 set ::env(CLOCK_TREE_SYNTH) 1 set ::env(CLOCK_PORT) {io_in[8]} #set ::env(CLOCK_NET) "" @@ -34,7 +34,7 @@ ## Floorplan set ::env(FP_SIZING) absolute -set ::env(DIE_AREA) "0 0 800 700" +set ::env(DIE_AREA) "0 0 700 600" ## Placement set ::env(PL_BASIC_PLACEMENT) 0 @@ -57,7 +57,9 @@ mod.u_cpu.rf_ram.RAM0 vdd vss vdd vss" set ::env(FP_PDN_MACROS) "\ mod.u_cpu.rf_ram.RAM0" - + +set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg + ## Internal Macros set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro.cfg @@ -92,8 +94,8 @@ $::env(DESIGN_DIR)/blocks/serv/servant/servant_gpio.v" set ::env(VERILOG_FILES_BLACKBOX) "\ - $::env(DESIGN_DIR)/rtl/gf180mcu_fd_sc_mcu7t5v0_bb.v" -# $::env(PDK_ROOT)/$::env(PDK)/libs.ref/gf180mcu_fd_ip_sram/verilog/gf180mcu_fd_ip_sram__sram256x8m8wm1.v" + $::env(DESIGN_DIR)/rtl/gf180mcu_fd_sc_mcu7t5v0_bb.v \ + $::env(PDK_ROOT)/$::env(PDK)/libs.ref/gf180mcu_fd_ip_sram/verilog/gf180mcu_fd_ip_sram__sram256x8m8wm1.v" set ::env(EXTRA_LEFS) "\ $::env(PDK_ROOT)/$::env(PDK)/libs.ref/gf180mcu_fd_ip_sram/lef/gf180mcu_fd_ip_sram__sram256x8m8wm1.lef" @@ -113,15 +115,16 @@ set ::env(FP_PDN_VPITCH) 30 #set ::env(FP_PDN_HPITCH) 30 -set ::env(FP_PDN_VWIDTH) 3 -#set ::env(FP_PDN_CORE_RING_VWIDTH) 1.6 +#set ::env(FP_PDN_VWIDTH) 3 +#set ::env(FP_PDN_CORE_RING) 0 ## LVS set ::env(MAGIC_DRC_USE_GDS) 0 +set ::env(MAGIC_WRITE_FULL_LEF) 0 set ::env(RUN_MAGIC_DRC) 0 set ::env(QUIT_ON_MAGIC_DRC) 0 -set ::env(RUN_CVC) 0 +set ::env(RUN_CVC) 1 # Temporary ignore set ::env(QUIT_ON_LVS_ERROR) 0 \ No newline at end of file
diff --git a/openlane/tiny_user_project/macro.cfg b/openlane/tiny_user_project/macro.cfg index 2a86b9f..32dc4d8 100644 --- a/openlane/tiny_user_project/macro.cfg +++ b/openlane/tiny_user_project/macro.cfg
@@ -1 +1 @@ -mod.u_cpu.rf_ram.RAM0 120 120 W +mod.u_cpu.rf_ram.RAM0 80 80 W
diff --git a/openlane/tiny_user_project/pin_order.cfg b/openlane/tiny_user_project/pin_order.cfg index 202bd93..df5ed5b 100644 --- a/openlane/tiny_user_project/pin_order.cfg +++ b/openlane/tiny_user_project/pin_order.cfg
@@ -8,4 +8,5 @@ #N io_.* +user_.*
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl index 4a3872c..4155c34 100644 --- a/openlane/user_project_wrapper/config.tcl +++ b/openlane/user_project_wrapper/config.tcl
@@ -36,11 +36,7 @@ set ::env(CLOCK_PORT) "user_clock2" set ::env(CLOCK_NET) "mprj.clk" -set ::env(CLOCK_PERIOD) "24" - -set ::env(VDD_NETS) [list {vdd}] -set ::env(GND_NETS) [list {vss}] -set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS" +set ::env(CLOCK_PERIOD) "50" ## Internal Macros ### Macro PDN Connections @@ -52,7 +48,7 @@ ### Black-box verilog and views set ::env(VERILOG_FILES_BLACKBOX) "\ - $::env(DESIGN_DIR)/../../verilog/rtl/defines.v \ + $::env(CARAVEL_ROOT)/verilog/rtl/defines.v \ $::env(DESIGN_DIR)/../../verilog/rtl/tiny_user_project.v" set ::env(EXTRA_LEFS) "\ @@ -85,8 +81,8 @@ ## DRC skips due to SRAM IP set ::env(MAGIC_DRC_USE_GDS) 0 -set ::env(RUN_MAGIC_DRC) 0 set ::env(QUIT_ON_MAGIC_DRC) 0 +set ::env(RUN_MAGIC_DRC) 0 # Temporary ignore set ::env(QUIT_ON_LVS_ERROR) 0
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg index 1c8063a..9420fb9 100644 --- a/openlane/user_project_wrapper/macro.cfg +++ b/openlane/user_project_wrapper/macro.cfg
@@ -1 +1 @@ -mprj 2010 1900 N +mprj 500 500 N \ No newline at end of file
diff --git a/verilog/rtl/pin_order.cfg b/verilog/rtl/pin_order.cfg deleted file mode 100644 index 0b85c63..0000000 --- a/verilog/rtl/pin_order.cfg +++ /dev/null
@@ -1,9 +0,0 @@ -#N - -#S - -#E - -#W -io_in.* -io_out.*