commit | 40ced4acffb548d2cb16d0d549cf83d3be5827bf | [log] [tgz] |
---|---|---|
author | tinybot <bot@tinytapeout.com> | Sun Dec 04 08:00:57 2022 +0000 |
committer | tinybot <bot@tinytapeout.com> | Sun Dec 04 08:00:57 2022 +0000 |
tree | 7a45abe168447e089c34fc0575d6d6e896bff781 | |
parent | 209d84dbde00810ba3cdccec906801d82d601b2a [diff] |
harden project [skip ci]
An award winning CPU design fit into the GF180 MPW0 Shuttle.
To keep the design simple this project places a Serv CPU with a scan-chain around it connecting it's wishbone bus which is a combination of data and instructions out via I/O pins.
Another I/O pin is responsible for handling clock and reset. Operation will run as follows:
In this manner we should be able to implement external peripherals like UARTs, timers, and GPIOs. The external controller can be a microcontroller, FPGA, or the caravel harness SoC.