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foss-eda-tools / third_party / shuttle / gf180mcu / mpw-000 / slot-001 / 2311ae57c4d661cf5405a7f6e352b278b4f3f94b / . / sdf / serv_0.sdf
blob: 8fe87dae0369d13b7b8962b03d3f54ee4c96f233 [file] [log] [blame]
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(IOPATH A3 Z (0.361:0.361:0.361) (0.898:0.898:0.898))
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(COND A1===1'b1 && A2===1'b0
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(COND A1===1'b0 && A2===1'b1
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(COND A1===1'b0 && A2===1'b1
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(IOPATH S Z (0.638:0.638:0.638) (0.638:0.638:0.638))
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(COND B1===1'b0 && B2===1'b1
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(COND B1===1'b0 && B2===1'b0
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(COND B1===1'b0 && B2===1'b1
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(COND B1===1'b0 && B2===1'b0
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(IOPATH B1 ZN (0.530:0.538:0.547) (0.356:0.356:0.357))
(COND A1===1'b1 && A2===1'b0
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(COND A1===1'b0 && A2===1'b1
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(COND A1===1'b0 && A2===1'b0
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(IOPATH A2 ZN (0.298:0.315:0.331) (0.117:0.117:0.116))
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(COND A1===1'b1 && A2===1'b1
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(COND A1===1'b1 && A2===1'b0
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(IOPATH C ZN (0.486:0.486:0.486) (0.274:0.274:0.274))
(COND A1===1'b1 && A2===1'b1
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(COND A1===1'b1 && A2===1'b0
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(COND A1===1'b0 && A2===1'b1
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(COND A1===1'b0 && A2===1'b1
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(CELL
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(COND A1===1'b0 && A2===1'b0 && A3===1'b1
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(SETUP (negedge D) (posedge CLK) (0.184:0.218:0.252))
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(SETUP (negedge D) (posedge CLK) (0.166:0.180:0.195))
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(SETUP (negedge D) (posedge CLK) (0.179:0.179:0.179))
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(SETUP (negedge D) (posedge CLK) (0.200:0.200:0.200))
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(SETUP (negedge D) (posedge CLK) (0.169:0.169:0.169))
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(SETUP (negedge D) (posedge CLK) (0.386:0.386:0.386))
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(IOPATH CLK Q (0.998:0.998:0.998) (0.849:0.849:0.849))
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(SETUP (posedge D) (posedge CLK) (0.195:0.203:0.211))
(SETUP (negedge D) (posedge CLK) (0.204:0.228:0.252))
(HOLD (posedge D) (posedge CLK) (0.065:0.064:0.063))
(HOLD (negedge D) (posedge CLK) (0.108:0.086:0.065))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.836:0.836:0.836) (0.751:0.751:0.751))
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(SETUP (posedge D) (posedge CLK) (0.126:0.126:0.126))
(SETUP (negedge D) (posedge CLK) (0.143:0.143:0.143))
(HOLD (posedge D) (posedge CLK) (0.113:0.113:0.113))
(HOLD (negedge D) (posedge CLK) (0.167:0.167:0.166))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(INSTANCE _3231_)
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(IOPATH CLK Q (0.799:0.799:0.799) (0.715:0.715:0.715))
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(SETUP (posedge D) (posedge CLK) (0.170:0.170:0.170))
(SETUP (negedge D) (posedge CLK) (0.180:0.180:0.180))
(HOLD (posedge D) (posedge CLK) (0.088:0.088:0.088))
(HOLD (negedge D) (posedge CLK) (0.130:0.130:0.130))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(DELAY
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(IOPATH CLK Q (0.840:0.840:0.840) (0.748:0.748:0.748))
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(SETUP (negedge D) (posedge CLK) (0.212:0.212:0.212))
(HOLD (posedge D) (posedge CLK) (0.087:0.087:0.087))
(HOLD (negedge D) (posedge CLK) (0.102:0.102:0.102))
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(WIDTH (negedge CLK) (0.553:0.553:0.553))
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(SETUP (negedge D) (posedge CLK) (0.178:0.178:0.178))
(HOLD (posedge D) (posedge CLK) (0.093:0.093:0.093))
(HOLD (negedge D) (posedge CLK) (0.132:0.132:0.132))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
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(SETUP (negedge D) (posedge CLK) (0.181:0.181:0.181))
(HOLD (posedge D) (posedge CLK) (0.089:0.089:0.089))
(HOLD (negedge D) (posedge CLK) (0.129:0.129:0.129))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(INSTANCE _3235_)
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(IOPATH CLK Q (0.887:0.887:0.887) (0.792:0.792:0.792))
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(SETUP (posedge D) (posedge CLK) (0.139:0.139:0.139))
(SETUP (negedge D) (posedge CLK) (0.153:0.153:0.153))
(HOLD (posedge D) (posedge CLK) (0.112:0.112:0.112))
(HOLD (negedge D) (posedge CLK) (0.154:0.154:0.154))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(INSTANCE _3236_)
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(SETUP (posedge D) (posedge CLK) (0.151:0.151:0.151))
(SETUP (negedge D) (posedge CLK) (0.179:0.179:0.179))
(HOLD (posedge D) (posedge CLK) (0.111:0.111:0.111))
(HOLD (negedge D) (posedge CLK) (0.130:0.130:0.130))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(INSTANCE _3237_)
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(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.168:0.168:0.168))
(SETUP (negedge D) (posedge CLK) (0.237:0.237:0.237))
(HOLD (posedge D) (posedge CLK) (0.107:0.107:0.107))
(HOLD (negedge D) (posedge CLK) (0.079:0.079:0.079))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(INSTANCE _3238_)
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(ABSOLUTE
(IOPATH CLK Q (1.066:1.066:1.066) (0.894:0.894:0.894))
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(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.202:0.204:0.206))
(SETUP (negedge D) (posedge CLK) (0.216:0.225:0.233))
(HOLD (posedge D) (posedge CLK) (0.064:0.064:0.063))
(HOLD (negedge D) (posedge CLK) (0.096:0.089:0.082))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__dffq_1")
(INSTANCE _3239_)
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.971:0.971:0.971) (0.857:0.857:0.857))
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(SETUP (posedge D) (posedge CLK) (0.133:0.136:0.139))
(SETUP (negedge D) (posedge CLK) (0.137:0.215:0.293))
(HOLD (posedge D) (posedge CLK) (0.121:0.122:0.123))
(HOLD (negedge D) (posedge CLK) (0.168:0.102:0.037))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(INSTANCE _3240_)
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(SETUP (negedge D) (posedge CLK) (0.176:0.211:0.246))
(HOLD (posedge D) (posedge CLK) (0.121:0.122:0.122))
(HOLD (negedge D) (posedge CLK) (0.133:0.104:0.075))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(INSTANCE _3241_)
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(IOPATH CLK Q (0.828:0.828:0.828) (0.741:0.741:0.741))
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(SETUP (posedge D) (posedge CLK) (0.177:0.178:0.179))
(SETUP (negedge D) (posedge CLK) (0.190:0.209:0.229))
(HOLD (posedge D) (posedge CLK) (0.091:0.091:0.091))
(HOLD (negedge D) (posedge CLK) (0.121:0.104:0.086))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
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(INSTANCE _3242_)
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(SETUP (posedge D) (posedge CLK) (0.186:0.188:0.190))
(SETUP (negedge D) (posedge CLK) (0.231:0.241:0.250))
(HOLD (posedge D) (posedge CLK) (0.084:0.084:0.083))
(HOLD (negedge D) (posedge CLK) (0.085:0.077:0.068))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(INSTANCE _3243_)
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.180:1.180:1.180) (0.977:0.977:0.977))
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(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.152:0.152:0.152))
(SETUP (negedge D) (posedge CLK) (0.168:0.168:0.168))
(HOLD (posedge D) (posedge CLK) (0.095:0.095:0.095))
(HOLD (negedge D) (posedge CLK) (0.143:0.143:0.143))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__dffq_1")
(INSTANCE _3244_)
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.215:1.215:1.215) (0.999:0.999:0.999))
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(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.153:0.153:0.153))
(SETUP (negedge D) (posedge CLK) (0.169:0.169:0.169))
(HOLD (posedge D) (posedge CLK) (0.094:0.094:0.094))
(HOLD (negedge D) (posedge CLK) (0.143:0.143:0.143))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(CELL
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(INSTANCE _3245_)
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.265:1.265:1.265) (1.034:1.034:1.034))
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(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.147:0.147:0.147))
(SETUP (negedge D) (posedge CLK) (0.163:0.163:0.163))
(HOLD (posedge D) (posedge CLK) (0.098:0.098:0.098))
(HOLD (negedge D) (posedge CLK) (0.147:0.147:0.147))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(CELL
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(INSTANCE _3246_)
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.298:1.298:1.298) (1.055:1.055:1.055))
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(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.147:0.147:0.147))
(SETUP (negedge D) (posedge CLK) (0.163:0.163:0.163))
(HOLD (posedge D) (posedge CLK) (0.099:0.099:0.099))
(HOLD (negedge D) (posedge CLK) (0.148:0.148:0.148))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(CELL
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(INSTANCE _3247_)
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.572:1.572:1.572) (1.224:1.224:1.224))
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(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.156:0.156:0.156))
(SETUP (negedge D) (posedge CLK) (0.171:0.171:0.171))
(HOLD (posedge D) (posedge CLK) (0.093:0.093:0.093))
(HOLD (negedge D) (posedge CLK) (0.140:0.140:0.140))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(CELL
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(INSTANCE _3248_)
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.587:1.587:1.587) (1.248:1.248:1.248))
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(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.118:0.118:0.118))
(SETUP (negedge D) (posedge CLK) (0.134:0.134:0.134))
(HOLD (posedge D) (posedge CLK) (0.118:0.118:0.118))
(HOLD (negedge D) (posedge CLK) (0.174:0.174:0.174))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(CELL
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(INSTANCE _3249_)
(DELAY
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(IOPATH CLK Q (1.497:1.497:1.497) (1.191:1.191:1.191))
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(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.118:0.118:0.118))
(SETUP (negedge D) (posedge CLK) (0.134:0.134:0.134))
(HOLD (posedge D) (posedge CLK) (0.118:0.118:0.118))
(HOLD (negedge D) (posedge CLK) (0.175:0.175:0.175))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(CELL
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(INSTANCE _3250_)
(DELAY
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(IOPATH CLK Q (1.674:1.674:1.674) (1.292:1.292:1.292))
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(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.168:0.177:0.186))
(SETUP (negedge D) (posedge CLK) (0.181:0.202:0.222))
(HOLD (posedge D) (posedge CLK) (0.092:0.092:0.092))
(HOLD (negedge D) (posedge CLK) (0.129:0.111:0.092))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(CELL
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(INSTANCE _3410_)
(DELAY
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(CELL
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(INSTANCE _3411_)
(DELAY
(ABSOLUTE
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(CELL
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(INSTANCE u_cpu\.rf_ram\.RAM0)
(DELAY
(ABSOLUTE
(COND CEN== 1'b0 && GWEN== 1'b1
(IOPATH CLK Q[0] (16.309:16.309:16.309) (17.214:17.214:17.214)))
(COND CEN== 1'b0 && GWEN== 1'b1
(IOPATH CLK Q[1] (16.295:16.295:16.295) (17.197:17.197:17.197)))
(COND CEN== 1'b0 && GWEN== 1'b1
(IOPATH CLK Q[2] (16.333:16.333:16.333) (17.245:17.245:17.245)))
(COND CEN== 1'b0 && GWEN== 1'b1
(IOPATH CLK Q[3] (16.350:16.350:16.350) (17.263:17.263:17.263)))
(COND CEN== 1'b0 && GWEN== 1'b1
(IOPATH CLK Q[4] (16.407:16.407:16.407) (17.310:17.310:17.310)))
(COND CEN== 1'b0 && GWEN== 1'b1
(IOPATH CLK Q[5] (16.428:16.428:16.428) (17.327:17.327:17.327)))
(COND CEN== 1'b0 && GWEN== 1'b1
(IOPATH CLK Q[6] (16.482:16.482:16.482) (17.371:17.371:17.371)))
(COND CEN== 1'b0 && GWEN== 1'b1
(IOPATH CLK Q[7] (16.456:16.456:16.456) (17.350:17.350:17.350)))
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(TIMINGCHECK
(HOLD (posedge D[0]) (posedge CLK) (0.753:0.753:0.753))
(HOLD (negedge D[0]) (posedge CLK) (1.985:1.985:1.985))
(HOLD (posedge D[1]) (posedge CLK) (0.739:0.739:0.739))
(HOLD (negedge D[1]) (posedge CLK) (1.973:1.973:1.973))
(HOLD (posedge D[2]) (posedge CLK) (0.723:0.723:0.723))
(HOLD (negedge D[2]) (posedge CLK) (1.960:1.960:1.960))
(HOLD (posedge D[3]) (posedge CLK) (0.713:0.713:0.713))
(HOLD (negedge D[3]) (posedge CLK) (1.949:1.949:1.949))
(HOLD (posedge D[4]) (posedge CLK) (0.639:0.639:0.639))
(HOLD (negedge D[4]) (posedge CLK) (1.858:1.858:1.858))
(HOLD (posedge D[5]) (posedge CLK) (0.645:0.645:0.645))
(HOLD (negedge D[5]) (posedge CLK) (1.866:1.866:1.866))
(HOLD (posedge D[6]) (posedge CLK) (0.669:0.669:0.669))
(HOLD (negedge D[6]) (posedge CLK) (1.895:1.895:1.895))
(HOLD (posedge D[7]) (posedge CLK) (0.614:0.614:0.614))
(HOLD (negedge D[7]) (posedge CLK) (1.826:1.826:1.826))
(SETUP (posedge D[0]) (posedge CLK) (2.059:2.059:2.059))
(SETUP (negedge D[0]) (posedge CLK) (0.140:0.140:0.140))
(SETUP (posedge D[1]) (posedge CLK) (2.075:2.075:2.075))
(SETUP (negedge D[1]) (posedge CLK) (0.152:0.152:0.152))
(SETUP (posedge D[2]) (posedge CLK) (2.092:2.092:2.092))
(SETUP (negedge D[2]) (posedge CLK) (0.165:0.165:0.165))
(SETUP (posedge D[3]) (posedge CLK) (2.102:2.102:2.102))
(SETUP (negedge D[3]) (posedge CLK) (0.176:0.176:0.176))
(SETUP (posedge D[4]) (posedge CLK) (2.174:2.174:2.174))
(SETUP (negedge D[4]) (posedge CLK) (0.268:0.268:0.268))
(SETUP (posedge D[5]) (posedge CLK) (2.168:2.168:2.168))
(SETUP (negedge D[5]) (posedge CLK) (0.260:0.260:0.260))
(SETUP (posedge D[6]) (posedge CLK) (2.145:2.145:2.145))
(SETUP (negedge D[6]) (posedge CLK) (0.231:0.231:0.231))
(SETUP (posedge D[7]) (posedge CLK) (2.199:2.199:2.199))
(SETUP (negedge D[7]) (posedge CLK) (0.300:0.300:0.300))
(HOLD (posedge A[0]) (posedge CLK) (1.284:1.284:1.284))
(HOLD (negedge A[0]) (posedge CLK) (1.495:1.495:1.495))
(HOLD (posedge A[1]) (posedge CLK) (1.310:1.310:1.310))
(HOLD (negedge A[1]) (posedge CLK) (1.511:1.511:1.511))
(HOLD (posedge A[2]) (posedge CLK) (1.376:1.349:1.322))
(HOLD (negedge A[2]) (posedge CLK) (1.552:1.532:1.513))
(HOLD (posedge A[3]) (posedge CLK) (1.344:1.308:1.273))
(HOLD (negedge A[3]) (posedge CLK) (1.539:1.524:1.508))
(HOLD (posedge A[4]) (posedge CLK) (1.347:1.312:1.278))
(HOLD (negedge A[4]) (posedge CLK) (1.539:1.524:1.509))
(HOLD (posedge A[5]) (posedge CLK) (1.351:1.317:1.282))
(HOLD (negedge A[5]) (posedge CLK) (1.545:1.528:1.512))
(HOLD (posedge A[6]) (posedge CLK) (1.350:1.316:1.281))
(HOLD (negedge A[6]) (posedge CLK) (1.541:1.525:1.508))
(HOLD (posedge A[7]) (posedge CLK) (1.294:1.292:1.289))
(HOLD (negedge A[7]) (posedge CLK) (1.427:1.408:1.388))
(SETUP (posedge A[0]) (posedge CLK) (1.799:1.799:1.799))
(SETUP (negedge A[0]) (posedge CLK) (2.047:2.047:2.047))
(SETUP (posedge A[1]) (posedge CLK) (1.774:1.774:1.774))
(SETUP (negedge A[1]) (posedge CLK) (2.030:2.030:2.030))
(SETUP (posedge A[2]) (posedge CLK) (1.710:1.736:1.763))
(SETUP (negedge A[2]) (posedge CLK) (1.995:2.011:2.027))
(SETUP (posedge A[3]) (posedge CLK) (1.741:1.776:1.811))
(SETUP (negedge A[3]) (posedge CLK) (2.003:2.018:2.033))
(SETUP (posedge A[4]) (posedge CLK) (1.738:1.772:1.806))
(SETUP (negedge A[4]) (posedge CLK) (2.003:2.018:2.033))
(SETUP (posedge A[5]) (posedge CLK) (1.734:1.768:1.801))
(SETUP (negedge A[5]) (posedge CLK) (2.000:2.014:2.029))
(SETUP (posedge A[6]) (posedge CLK) (1.735:1.768:1.802))
(SETUP (negedge A[6]) (posedge CLK) (2.002:2.018:2.033))
(SETUP (posedge A[7]) (posedge CLK) (1.789:1.792:1.795))
(SETUP (negedge A[7]) (posedge CLK) (2.120:2.141:2.162))
(HOLD (posedge WEN[0]) (posedge CLK) (2.387:2.387:2.387))
(HOLD (negedge WEN[0]) (posedge CLK) (1.127:1.127:1.127))
(HOLD (posedge WEN[1]) (posedge CLK) (2.387:2.387:2.387))
(HOLD (negedge WEN[1]) (posedge CLK) (1.126:1.126:1.126))
(HOLD (posedge WEN[2]) (posedge CLK) (2.387:2.387:2.387))
(HOLD (negedge WEN[2]) (posedge CLK) (1.126:1.126:1.126))
(HOLD (posedge WEN[3]) (posedge CLK) (2.387:2.387:2.387))
(HOLD (negedge WEN[3]) (posedge CLK) (1.126:1.126:1.126))
(HOLD (posedge WEN[4]) (posedge CLK) (2.387:2.387:2.387))
(HOLD (negedge WEN[4]) (posedge CLK) (1.126:1.126:1.126))
(HOLD (posedge WEN[5]) (posedge CLK) (2.387:2.387:2.387))
(HOLD (negedge WEN[5]) (posedge CLK) (1.126:1.126:1.126))
(HOLD (posedge WEN[6]) (posedge CLK) (2.387:2.387:2.387))
(HOLD (negedge WEN[6]) (posedge CLK) (1.126:1.126:1.126))
(HOLD (posedge WEN[7]) (posedge CLK) (2.387:2.387:2.387))
(HOLD (negedge WEN[7]) (posedge CLK) (1.126:1.126:1.126))
(SETUP (posedge WEN[0]) (posedge CLK) (0.000:0.000:0.000))
(SETUP (negedge WEN[0]) (posedge CLK) (0.858:0.858:0.858))
(SETUP (posedge WEN[1]) (posedge CLK) (0.000:0.000:0.000))
(SETUP (negedge WEN[1]) (posedge CLK) (0.858:0.858:0.858))
(SETUP (posedge WEN[2]) (posedge CLK) (0.000:0.000:0.000))
(SETUP (negedge WEN[2]) (posedge CLK) (0.858:0.858:0.858))
(SETUP (posedge WEN[3]) (posedge CLK) (0.000:0.000:0.000))
(SETUP (negedge WEN[3]) (posedge CLK) (0.858:0.858:0.858))
(SETUP (posedge WEN[4]) (posedge CLK) (0.000:0.000:0.000))
(SETUP (negedge WEN[4]) (posedge CLK) (0.858:0.858:0.858))
(SETUP (posedge WEN[5]) (posedge CLK) (0.000:0.000:0.000))
(SETUP (negedge WEN[5]) (posedge CLK) (0.858:0.858:0.858))
(SETUP (posedge WEN[6]) (posedge CLK) (0.000:0.000:0.000))
(SETUP (negedge WEN[6]) (posedge CLK) (0.858:0.858:0.858))
(SETUP (posedge WEN[7]) (posedge CLK) (0.000:0.000:0.000))
(SETUP (negedge WEN[7]) (posedge CLK) (0.858:0.858:0.858))
(HOLD (posedge GWEN) (posedge CLK) (2.377:2.377:2.377))
(HOLD (negedge GWEN) (posedge CLK) (1.124:1.124:1.124))
(SETUP (posedge GWEN) (posedge CLK) (1.967:1.967:1.967))
(SETUP (negedge GWEN) (posedge CLK) (2.439:2.440:2.440))
(HOLD (posedge CEN) (posedge CLK) (3.937:3.937:3.937))
(HOLD (negedge CEN) (posedge CLK) (4.152:4.152:4.152))
(SETUP (posedge CEN) (posedge CLK) (1.448:1.448:1.448))
(SETUP (negedge CEN) (posedge CLK) (1.077:1.077:1.077))
(WIDTH (posedge CLK) (10.915:10.915:10.915))
(WIDTH (negedge CLK) (10.289:10.289:10.289))
(PERIOD CLK (22.470:22.470:22.470))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__clkbuf_1")
(INSTANCE u_scanchain_local\.input_buf_clk)
(DELAY
(ABSOLUTE
(IOPATH I Z (0.233:0.233:0.233) (0.246:0.246:0.246))
)
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__dffnq_1")
(INSTANCE u_scanchain_local\.out_flop)
(DELAY
(ABSOLUTE
(IOPATH CLKN Q (0.867:0.867:0.867) (0.713:0.713:0.713))
)
)
(TIMINGCHECK
(SETUP (posedge D) (negedge CLKN) (0.052:0.052:0.052))
(SETUP (negedge D) (negedge CLKN) (0.182:0.182:0.182))
(HOLD (posedge D) (negedge CLKN) (0.254:0.254:0.254))
(HOLD (negedge D) (negedge CLKN) (0.116:0.116:0.116))
(WIDTH (posedge CLKN) (0.406:0.406:0.406))
(WIDTH (negedge CLKN) (0.446:0.446:0.446))
(PERIOD CLKN (1.091:1.091:1.091))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__clkbuf_1")
(INSTANCE u_scanchain_local\.output_buffers\[2\])
(DELAY
(ABSOLUTE
(IOPATH I Z (0.216:0.216:0.216) (0.208:0.208:0.208))
)
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__clkbuf_1")
(INSTANCE u_scanchain_local\.output_buffers\[3\])
(DELAY
(ABSOLUTE
(IOPATH I Z (0.284:0.284:0.284) (0.287:0.287:0.287))
)
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[0\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.000:1.000:1.000) (0.975:0.975:0.975))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.000:1.000:1.000) (0.975:0.975:0.975)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.000:1.000:1.000) (0.975:0.975:0.975)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.000:1.000:1.000) (0.975:0.975:0.975)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.000:1.000:1.000) (0.975:0.975:0.975)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.411:0.412:0.412))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.462:0.464:0.465))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.411:0.412:0.412))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.462:0.463:0.464))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.020:-0.021:-0.021))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.020:-0.021:-0.021))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.513:0.513:0.513))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.654:0.654:0.654))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.434:0.434:0.434))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.464:0.464:0.464))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.082:-0.082:-0.082))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.484:-0.484:-0.484))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.243:-0.243:-0.243))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.024:-0.024:-0.024))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.421:0.421:0.421))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.477:0.477:0.477))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.420:0.420:0.420))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.478:0.478:0.478))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.250:-0.250:-0.250))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.034:-0.034:-0.034))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.250:-0.250:-0.250))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.034:-0.034:-0.034))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[10\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.439:1.439:1.439) (1.252:1.252:1.252))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.439:1.439:1.439) (1.252:1.252:1.252)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.439:1.439:1.439) (1.252:1.252:1.252)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.439:1.439:1.439) (1.252:1.252:1.252)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.439:1.439:1.439) (1.252:1.252:1.252)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.424:0.424:0.424))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.506:0.506:0.506))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.424:0.424:0.424))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.506:0.506:0.506))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.239:-0.239:-0.239))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.047:-0.047:-0.047))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.239:-0.239:-0.239))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.047:-0.047:-0.047))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.516:0.516:0.516))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.638:0.638:0.638))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.415:0.415:0.415))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.453:0.453:0.453))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.080:-0.080:-0.080))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.465:-0.465:-0.465))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.233:-0.233:-0.233))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.016:-0.016:-0.016))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.433:0.433:0.433))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.579:0.579:0.579))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.433:0.433:0.433))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.579:0.579:0.579))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.227:-0.227:-0.227))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.069:-0.069:-0.069))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.227:-0.227:-0.227))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.069:-0.069:-0.069))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[11\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.328:1.328:1.328) (1.158:1.158:1.158))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.328:1.328:1.328) (1.158:1.158:1.158)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.328:1.328:1.328) (1.158:1.158:1.158)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.328:1.328:1.328) (1.158:1.158:1.158)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.327:1.327:1.327) (1.158:1.158:1.158)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.479:0.479:0.479))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.622:0.622:0.622))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.479:0.479:0.479))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.622:0.622:0.622))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.232:-0.232:-0.232))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.115:-0.115:-0.115))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.232:-0.232:-0.232))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.115:-0.115:-0.115))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.590:0.590:0.590))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.724:0.724:0.724))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.476:0.476:0.476))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.563:0.563:0.563))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.143:-0.143:-0.143))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.498:-0.498:-0.498))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.242:-0.242:-0.242))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.104:-0.104:-0.104))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.482:0.482:0.482))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.621:0.621:0.621))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.482:0.482:0.482))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.621:0.621:0.621))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.233:-0.233:-0.233))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.118:-0.118:-0.118))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.233:-0.233:-0.233))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.118:-0.118:-0.118))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[12\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.405:1.405:1.405) (1.237:1.237:1.237))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.405:1.405:1.405) (1.237:1.237:1.237)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.405:1.405:1.405) (1.237:1.237:1.237)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.405:1.405:1.405) (1.237:1.237:1.237)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.405:1.405:1.405) (1.237:1.237:1.237)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.413:0.413:0.413))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.465:0.465:0.465))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.413:0.413:0.413))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.465:0.465:0.465))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.246:-0.246:-0.246))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.019:-0.019:-0.019))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.246:-0.246:-0.246))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.019:-0.019:-0.019))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.501:0.501:0.501))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.669:0.669:0.669))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.418:0.418:0.418))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.471:0.471:0.471))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.069:-0.069:-0.069))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.505:-0.505:-0.505))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.242:-0.242:-0.242))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.025:-0.025:-0.025))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.426:0.426:0.426))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.519:0.519:0.519))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.426:0.426:0.426))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.519:0.519:0.519))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.243:-0.243:-0.243))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.047:-0.047:-0.047))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.243:-0.243:-0.243))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.047:-0.047:-0.047))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[13\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.305:1.305:1.305) (1.168:1.168:1.168))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.304:1.304:1.304) (1.168:1.168:1.168)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.304:1.304:1.304) (1.168:1.168:1.168)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.305:1.305:1.305) (1.168:1.168:1.168)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.305:1.305:1.305) (1.168:1.168:1.168)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.412:0.412:0.412))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.457:0.457:0.457))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.412:0.412:0.412))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.457:0.457:0.457))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.244:-0.244:-0.244))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.018:-0.018:-0.018))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.244:-0.244:-0.244))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.018:-0.018:-0.018))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.516:0.516:0.516))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.638:0.638:0.638))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.415:0.415:0.415))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.453:0.453:0.453))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.080:-0.080:-0.080))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.465:-0.465:-0.465))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.233:-0.233:-0.233))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.016:-0.016:-0.016))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.431:0.431:0.431))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.534:0.534:0.534))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.431:0.431:0.431))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.534:0.534:0.534))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.239:-0.239:-0.239))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.058:-0.058:-0.058))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.239:-0.239:-0.239))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.058:-0.058:-0.058))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[14\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.495:1.495:1.495) (1.288:1.288:1.288))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.495:1.495:1.495) (1.288:1.288:1.288)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.495:1.495:1.495) (1.288:1.288:1.288)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.495:1.495:1.495) (1.288:1.288:1.288)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.495:1.495:1.495) (1.288:1.288:1.288)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.423:0.423:0.423))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.502:0.502:0.502))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.423:0.423:0.423))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.502:0.502:0.502))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.239:-0.239:-0.239))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.046:-0.046:-0.046))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.239:-0.239:-0.239))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.046:-0.046:-0.046))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.516:0.516:0.516))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.638:0.638:0.638))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.415:0.415:0.415))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.453:0.453:0.453))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.080:-0.080:-0.080))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.465:-0.465:-0.465))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.233:-0.233:-0.233))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.016:-0.016:-0.016))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.431:0.431:0.431))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.517:0.517:0.517))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.431:0.431:0.431))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.517:0.517:0.517))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.243:-0.243:-0.243))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.054:-0.054:-0.054))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.243:-0.243:-0.243))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.054:-0.054:-0.054))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[15\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.379:1.379:1.379) (1.218:1.218:1.218))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.379:1.379:1.379) (1.218:1.218:1.218)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.379:1.379:1.379) (1.218:1.218:1.218)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.379:1.379:1.379) (1.218:1.218:1.218)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.379:1.379:1.379) (1.218:1.218:1.218)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.409:0.409:0.409))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.448:0.448:0.448))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.409:0.409:0.409))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.448:0.448:0.448))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.248:-0.248:-0.248))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.011:-0.011:-0.011))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.248:-0.248:-0.248))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.011:-0.011:-0.011))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.505:0.505:0.505))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.645:0.645:0.645))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.437:0.437:0.437))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.451:0.451:0.451))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.078:-0.078:-0.078))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.478:-0.478:-0.478))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.248:-0.248:-0.248))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.014:-0.014:-0.014))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.429:0.429:0.429))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.545:0.545:0.545))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.429:0.429:0.429))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.545:0.545:0.545))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.237:-0.237:-0.237))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.056:-0.056:-0.056))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.237:-0.237:-0.237))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.056:-0.056:-0.056))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[16\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.268:1.268:1.268) (1.148:1.148:1.148))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.268:1.268:1.268) (1.148:1.148:1.148)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.268:1.268:1.268) (1.148:1.148:1.148)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.268:1.268:1.268) (1.148:1.148:1.148)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.268:1.268:1.268) (1.148:1.148:1.148)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.409:0.409:0.409))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.445:0.445:0.445))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.409:0.409:0.409))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.445:0.445:0.445))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.248:-0.248:-0.248))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.010:-0.010:-0.010))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.248:-0.248:-0.248))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.010:-0.010:-0.010))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.505:0.505:0.505))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.645:0.645:0.645))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.437:0.437:0.437))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.451:0.451:0.451))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.078:-0.078:-0.078))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.478:-0.478:-0.478))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.248:-0.248:-0.248))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.014:-0.014:-0.014))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.428:0.428:0.428))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.520:0.520:0.520))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.428:0.428:0.428))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.520:0.520:0.520))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.242:-0.242:-0.242))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.050:-0.050:-0.050))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.242:-0.242:-0.242))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.050:-0.050:-0.050))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[17\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.379:1.379:1.379) (1.218:1.218:1.218))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.379:1.379:1.379) (1.218:1.218:1.218)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.379:1.379:1.379) (1.218:1.218:1.218)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.379:1.379:1.379) (1.218:1.218:1.218)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.379:1.379:1.379) (1.218:1.218:1.218)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.409:0.409:0.409))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.446:0.446:0.446))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.409:0.409:0.409))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.446:0.446:0.446))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.248:-0.248:-0.248))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.010:-0.010:-0.010))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.248:-0.248:-0.248))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.010:-0.010:-0.010))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.505:0.505:0.505))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.645:0.645:0.645))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.437:0.437:0.437))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.451:0.451:0.451))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.078:-0.078:-0.078))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.478:-0.478:-0.478))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.248:-0.248:-0.248))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.014:-0.014:-0.014))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.426:0.426:0.426))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.498:0.498:0.498))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.426:0.426:0.426))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.498:0.498:0.498))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.248:-0.248:-0.248))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.045:-0.045:-0.045))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.248:-0.248:-0.248))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.045:-0.045:-0.045))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[18\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.177:1.177:1.177) (1.087:1.087:1.087))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.177:1.177:1.177) (1.087:1.087:1.087)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.177:1.177:1.177) (1.087:1.087:1.087)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.177:1.177:1.177) (1.087:1.087:1.087)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.177:1.177:1.177) (1.087:1.087:1.087)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.419:0.419:0.419))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.473:0.473:0.473))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.419:0.419:0.419))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.473:0.473:0.473))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.242:-0.242:-0.242))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.028:-0.028:-0.028))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.242:-0.242:-0.242))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.028:-0.028:-0.028))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.516:0.516:0.516))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.638:0.638:0.638))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.415:0.415:0.415))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.453:0.453:0.453))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.080:-0.080:-0.080))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.465:-0.465:-0.465))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.233:-0.233:-0.233))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.016:-0.016:-0.016))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.431:0.431:0.431))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.530:0.530:0.530))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.431:0.431:0.431))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.530:0.530:0.530))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.240:-0.240:-0.240))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.057:-0.057:-0.057))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.240:-0.240:-0.240))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.057:-0.057:-0.057))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[19\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.277:1.277:1.277) (1.151:1.151:1.151))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.276:1.276:1.276) (1.151:1.151:1.151)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.276:1.276:1.276) (1.151:1.151:1.151)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.277:1.277:1.277) (1.151:1.151:1.151)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.277:1.277:1.277) (1.151:1.151:1.151)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.411:0.411:0.411))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.453:0.453:0.453))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.411:0.411:0.411))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.452:0.452:0.452))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.246:-0.246:-0.246))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.014:-0.014:-0.014))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.246:-0.246:-0.246))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.014:-0.014:-0.014))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.511:0.511:0.511))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.636:0.636:0.636))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.412:0.412:0.412))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.448:0.448:0.448))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.075:-0.075:-0.075))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.467:-0.467:-0.467))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.234:-0.234:-0.234))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.012:-0.012:-0.012))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.427:0.427:0.427))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.491:0.491:0.491))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.427:0.427:0.427))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.491:0.491:0.491))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.249:-0.249:-0.249))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.043:-0.043:-0.043))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.249:-0.249:-0.249))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.043:-0.043:-0.043))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[1\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.001:1.001:1.001) (0.975:0.975:0.975))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.001:1.001:1.001) (0.975:0.975:0.975)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.001:1.001:1.001) (0.975:0.975:0.975)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.001:1.001:1.001) (0.975:0.975:0.975)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.001:1.001:1.001) (0.975:0.975:0.975)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.411:0.411:0.411))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.468:0.471:0.473))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.411:0.411:0.411))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.468:0.471:0.473))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.024:-0.026:-0.027))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.024:-0.026:-0.027))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.513:0.513:0.513))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.654:0.654:0.654))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.434:0.434:0.434))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.464:0.464:0.464))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.082:-0.082:-0.082))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.484:-0.484:-0.484))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.243:-0.243:-0.243))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.024:-0.024:-0.024))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.422:0.422:0.422))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.474:0.474:0.474))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.422:0.422:0.422))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.474:0.474:0.474))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.251:-0.251:-0.251))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.032:-0.032:-0.032))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.251:-0.251:-0.251))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.032:-0.032:-0.032))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[20\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.247:1.247:1.247) (1.135:1.135:1.135))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.247:1.247:1.247) (1.135:1.135:1.135)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.247:1.247:1.247) (1.135:1.135:1.135)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.247:1.247:1.247) (1.135:1.135:1.135)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.247:1.247:1.247) (1.135:1.135:1.135)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.409:0.409:0.409))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.445:0.445:0.445))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.409:0.409:0.409))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.445:0.445:0.445))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.248:-0.248:-0.248))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.009:-0.009:-0.009))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.248:-0.248:-0.248))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.009:-0.009:-0.009))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.505:0.505:0.505))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.645:0.645:0.645))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.437:0.437:0.437))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.451:0.451:0.451))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.078:-0.078:-0.078))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.478:-0.478:-0.478))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.248:-0.248:-0.248))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.014:-0.014:-0.014))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.426:0.426:0.426))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.501:0.501:0.501))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.426:0.426:0.426))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.501:0.501:0.501))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.247:-0.247:-0.247))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.045:-0.045:-0.045))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.247:-0.247:-0.247))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.045:-0.045:-0.045))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[21\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.336:1.336:1.336) (1.187:1.187:1.187))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.335:1.335:1.335) (1.187:1.187:1.187)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.335:1.335:1.335) (1.187:1.187:1.187)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.336:1.336:1.336) (1.187:1.187:1.187)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.336:1.336:1.336) (1.187:1.187:1.187)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.412:0.412:0.412))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.456:0.456:0.456))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.412:0.412:0.412))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.456:0.456:0.456))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.244:-0.244:-0.244))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.017:-0.017:-0.017))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.244:-0.244:-0.244))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.017:-0.017:-0.017))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.516:0.516:0.516))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.649:0.649:0.649))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.433:0.433:0.433))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.462:0.462:0.462))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.084:-0.084:-0.084))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.477:-0.477:-0.477))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.241:-0.241:-0.241))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.023:-0.023:-0.023))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.430:0.430:0.430))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.504:0.504:0.504))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.430:0.430:0.430))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.504:0.504:0.504))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.246:-0.246:-0.246))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.051:-0.051:-0.051))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.246:-0.246:-0.246))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.051:-0.051:-0.051))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[22\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.291:1.291:1.291) (1.161:1.161:1.161))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.291:1.291:1.291) (1.161:1.161:1.161)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.291:1.291:1.291) (1.161:1.161:1.161)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.291:1.291:1.291) (1.161:1.161:1.161)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.291:1.291:1.291) (1.161:1.161:1.161)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.423:0.423:0.423))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.511:0.511:0.511))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.423:0.423:0.423))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.511:0.511:0.511))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.240:-0.240:-0.240))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.045:-0.045:-0.045))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.240:-0.240:-0.240))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.045:-0.045:-0.045))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.510:0.510:0.510))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.632:0.632:0.632))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.411:0.411:0.411))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.444:0.444:0.444))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.074:-0.074:-0.074))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.463:-0.463:-0.463))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.234:-0.234:-0.234))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.009:-0.009:-0.009))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.429:0.429:0.429))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.517:0.517:0.517))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.429:0.429:0.429))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.517:0.517:0.517))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.243:-0.243:-0.243))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.051:-0.051:-0.051))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.243:-0.243:-0.243))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.051:-0.051:-0.051))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[23\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.364:1.364:1.364) (1.207:1.207:1.207))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.364:1.364:1.364) (1.207:1.207:1.207)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.364:1.364:1.364) (1.207:1.207:1.207)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.364:1.364:1.364) (1.207:1.207:1.207)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.364:1.364:1.364) (1.207:1.207:1.207)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.413:0.413:0.413))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.459:0.459:0.459))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.413:0.413:0.413))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.458:0.458:0.458))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.018:-0.018:-0.018))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.018:-0.018:-0.018))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.510:0.510:0.510))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.632:0.632:0.632))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.411:0.411:0.411))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.444:0.444:0.444))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.074:-0.074:-0.074))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.463:-0.463:-0.463))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.234:-0.234:-0.234))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.009:-0.009:-0.009))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.428:0.428:0.428))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.507:0.507:0.507))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.428:0.428:0.428))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.507:0.507:0.507))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.049:-0.049:-0.049))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.049:-0.049:-0.049))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[24\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.402:1.402:1.402) (1.231:1.231:1.231))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.402:1.402:1.402) (1.231:1.231:1.231)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.402:1.402:1.402) (1.231:1.231:1.231)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.402:1.402:1.402) (1.231:1.231:1.231)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.402:1.402:1.402) (1.231:1.231:1.231)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.410:0.410:0.410))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.450:0.450:0.450))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.410:0.410:0.410))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.450:0.450:0.450))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.247:-0.247:-0.247))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.013:-0.013:-0.013))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.247:-0.247:-0.247))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.013:-0.013:-0.013))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.510:0.510:0.510))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.632:0.632:0.632))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.411:0.411:0.411))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.444:0.444:0.444))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.074:-0.074:-0.074))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.463:-0.463:-0.463))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.234:-0.234:-0.234))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.009:-0.009:-0.009))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.429:0.429:0.429))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.522:0.522:0.522))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.429:0.429:0.429))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.522:0.522:0.522))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.242:-0.242:-0.242))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.053:-0.053:-0.053))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.242:-0.242:-0.242))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.053:-0.053:-0.053))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[25\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.517:1.517:1.517) (1.303:1.303:1.303))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.517:1.517:1.517) (1.303:1.303:1.303)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.517:1.517:1.517) (1.303:1.303:1.303)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.517:1.517:1.517) (1.303:1.303:1.303)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.517:1.517:1.517) (1.303:1.303:1.303)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.410:0.410:0.410))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.451:0.451:0.451))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.410:0.410:0.410))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.451:0.451:0.451))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.247:-0.247:-0.247))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.014:-0.014:-0.014))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.247:-0.247:-0.247))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.014:-0.014:-0.014))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.510:0.510:0.510))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.632:0.632:0.632))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.411:0.411:0.411))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.444:0.444:0.444))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.074:-0.074:-0.074))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.463:-0.463:-0.463))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.234:-0.234:-0.234))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.009:-0.009:-0.009))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.429:0.429:0.429))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.529:0.529:0.529))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.429:0.429:0.429))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.529:0.529:0.529))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.240:-0.240:-0.240))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.054:-0.054:-0.054))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.240:-0.240:-0.240))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.054:-0.054:-0.054))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[26\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.430:1.430:1.430) (1.244:1.244:1.244))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.430:1.430:1.430) (1.244:1.244:1.244)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.430:1.430:1.430) (1.244:1.244:1.244)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.430:1.430:1.430) (1.244:1.244:1.244)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.430:1.430:1.430) (1.244:1.244:1.244)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.414:0.414:0.414))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.464:0.464:0.464))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.414:0.414:0.414))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.463:0.463:0.463))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.241:-0.241:-0.241))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.023:-0.023:-0.023))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.241:-0.241:-0.241))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.023:-0.023:-0.023))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.520:0.520:0.520))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.624:0.624:0.624))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.411:0.411:0.411))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.446:0.446:0.446))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.082:-0.082:-0.082))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.447:-0.447:-0.447))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.229:-0.229:-0.229))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.012:-0.012:-0.012))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.435:0.435:0.435))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.565:0.565:0.565))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.435:0.435:0.435))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.565:0.565:0.565))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.232:-0.232:-0.232))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.068:-0.068:-0.068))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.232:-0.232:-0.232))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.068:-0.068:-0.068))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[27\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.528:1.528:1.528) (1.305:1.305:1.305))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.528:1.528:1.528) (1.305:1.305:1.305)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.528:1.528:1.528) (1.305:1.305:1.305)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.528:1.528:1.528) (1.305:1.305:1.305)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.528:1.528:1.528) (1.305:1.305:1.305)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.415:0.415:0.415))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.467:0.467:0.467))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.415:0.415:0.415))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.466:0.466:0.466))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.241:-0.241:-0.241))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.024:-0.024:-0.024))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.241:-0.241:-0.241))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.024:-0.024:-0.024))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.520:0.520:0.520))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.624:0.624:0.624))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.411:0.411:0.411))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.446:0.446:0.446))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.082:-0.082:-0.082))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.447:-0.447:-0.447))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.229:-0.229:-0.229))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.012:-0.012:-0.012))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.434:0.434:0.434))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.550:0.550:0.550))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.434:0.434:0.434))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.550:0.550:0.550))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.235:-0.235:-0.235))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.065:-0.065:-0.065))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.235:-0.235:-0.235))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.065:-0.065:-0.065))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[28\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.710:1.710:1.710) (1.420:1.420:1.420))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.710:1.710:1.710) (1.420:1.420:1.420)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.710:1.710:1.710) (1.420:1.420:1.420)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.710:1.710:1.710) (1.420:1.420:1.420)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.710:1.710:1.710) (1.420:1.420:1.420)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.415:0.415:0.415))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.466:0.466:0.466))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.415:0.415:0.415))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.466:0.466:0.466))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.241:-0.241:-0.241))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.024:-0.024:-0.024))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.241:-0.241:-0.241))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.024:-0.024:-0.024))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.520:0.520:0.520))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.624:0.624:0.624))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.411:0.411:0.411))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.446:0.446:0.446))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.082:-0.082:-0.082))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.447:-0.447:-0.447))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.229:-0.229:-0.229))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.012:-0.012:-0.012))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.435:0.435:0.435))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.570:0.570:0.570))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.435:0.435:0.435))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.570:0.570:0.570))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.231:-0.231:-0.231))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.069:-0.069:-0.069))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.231:-0.231:-0.231))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.069:-0.069:-0.069))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[29\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.725:1.725:1.725) (1.434:1.434:1.434))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.725:1.725:1.725) (1.434:1.434:1.434)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.725:1.725:1.725) (1.434:1.434:1.434)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.725:1.725:1.725) (1.434:1.434:1.434)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.725:1.725:1.725) (1.434:1.434:1.434)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.410:0.410:0.410))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.450:0.450:0.450))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.410:0.410:0.410))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.450:0.450:0.450))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.247:-0.247:-0.247))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.013:-0.013:-0.013))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.247:-0.247:-0.247))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.013:-0.013:-0.013))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.509:0.509:0.509))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.665:0.665:0.665))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.439:0.439:0.439))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.473:0.473:0.473))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.081:-0.081:-0.081))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.495:-0.495:-0.495))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.247:-0.247:-0.247))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.029:-0.029:-0.029))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.430:0.430:0.430))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.596:0.596:0.596))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.430:0.430:0.430))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.596:0.596:0.596))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.223:-0.223:-0.223))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.067:-0.067:-0.067))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.223:-0.223:-0.223))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.067:-0.067:-0.067))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[2\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.434:1.434:1.434) (1.255:1.255:1.255))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.434:1.434:1.434) (1.255:1.255:1.255)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.434:1.434:1.434) (1.255:1.255:1.255)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.434:1.434:1.434) (1.255:1.255:1.255)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.434:1.434:1.434) (1.255:1.255:1.255)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.407:0.407:0.407))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.444:0.449:0.453))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.407:0.407:0.407))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.444:0.448:0.453))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.251:-0.251:-0.251))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.008:-0.010:-0.012))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.251:-0.251:-0.251))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.008:-0.010:-0.012))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.501:0.501:0.501))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.669:0.669:0.669))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.418:0.418:0.418))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.471:0.471:0.471))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.069:-0.069:-0.069))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.505:-0.505:-0.505))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.242:-0.242:-0.242))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.025:-0.025:-0.025))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.425:0.425:0.425))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.506:0.506:0.506))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.425:0.425:0.425))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.506:0.506:0.506))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.246:-0.246:-0.246))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.044:-0.044:-0.044))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.246:-0.246:-0.246))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.044:-0.044:-0.044))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[30\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.740:1.740:1.740) (1.440:1.440:1.440))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.740:1.740:1.740) (1.440:1.440:1.440)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.740:1.740:1.740) (1.440:1.440:1.440)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.740:1.740:1.740) (1.440:1.440:1.440)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.740:1.740:1.740) (1.440:1.440:1.440)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.431:0.431:0.431))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.549:0.549:0.549))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.431:0.431:0.431))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.549:0.549:0.549))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.233:-0.233:-0.233))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.063:-0.063:-0.063))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.233:-0.233:-0.233))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.063:-0.063:-0.063))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.520:0.520:0.520))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.624:0.624:0.624))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.411:0.411:0.411))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.446:0.446:0.446))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.082:-0.082:-0.082))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.447:-0.447:-0.447))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.229:-0.229:-0.229))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.012:-0.012:-0.012))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.435:0.435:0.435))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.609:0.609:0.609))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.435:0.435:0.435))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.609:0.609:0.609))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.218:-0.218:-0.218))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.076:-0.076:-0.076))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.218:-0.218:-0.218))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.076:-0.076:-0.076))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[31\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.556:1.556:1.556) (1.324:1.324:1.324))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.556:1.556:1.556) (1.324:1.324:1.324)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.556:1.556:1.556) (1.324:1.324:1.324)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.556:1.556:1.556) (1.324:1.324:1.324)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.556:1.556:1.556) (1.324:1.324:1.324)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.415:0.415:0.415))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.466:0.466:0.466))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.415:0.415:0.415))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.465:0.465:0.465))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.241:-0.241:-0.241))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.024:-0.024:-0.024))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.241:-0.241:-0.241))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.024:-0.024:-0.024))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.520:0.520:0.520))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.624:0.624:0.624))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.411:0.411:0.411))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.446:0.446:0.446))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.082:-0.082:-0.082))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.447:-0.447:-0.447))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.229:-0.229:-0.229))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.012:-0.012:-0.012))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.435:0.435:0.435))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.615:0.615:0.615))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.435:0.435:0.435))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.615:0.615:0.615))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.217:-0.216:-0.216))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.077:-0.077:-0.077))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.217:-0.216:-0.216))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.077:-0.077:-0.077))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[32\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.572:1.572:1.572) (1.333:1.333:1.333))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.572:1.572:1.572) (1.333:1.333:1.333)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.572:1.572:1.572) (1.333:1.333:1.333)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.572:1.572:1.572) (1.333:1.333:1.333)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.572:1.572:1.572) (1.333:1.333:1.333)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.423:0.423:0.423))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.484:0.484:0.484))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.423:0.423:0.423))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.484:0.484:0.484))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.240:-0.240:-0.240))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.036:-0.036:-0.036))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.240:-0.240:-0.240))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.036:-0.036:-0.036))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.517:0.517:0.517))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.586:0.586:0.586))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.396:0.396:0.396))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.418:0.418:0.418))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.076:-0.076:-0.076))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.405:-0.405:-0.405))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.222:-0.222:-0.222))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.010:0.010:0.010))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.436:0.436:0.436))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.577:0.578:0.578))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.436:0.436:0.436))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.577:0.578:0.578))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.228:-0.228:-0.228))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.072:-0.072:-0.072))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.228:-0.228:-0.228))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.072:-0.072:-0.072))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[33\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.296:1.296:1.296) (1.159:1.159:1.159))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.296:1.296:1.296) (1.159:1.159:1.159)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.296:1.296:1.296) (1.159:1.159:1.159)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.296:1.296:1.296) (1.159:1.159:1.159)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.296:1.296:1.296) (1.159:1.159:1.159)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.416:0.416:0.416))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.462:0.462:0.462))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.416:0.416:0.416))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.461:0.461:0.461))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.241:-0.241:-0.241))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.022:-0.022:-0.022))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.241:-0.241:-0.241))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.022:-0.022:-0.022))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.517:0.517:0.517))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.586:0.586:0.586))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.396:0.396:0.396))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.418:0.418:0.418))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.076:-0.076:-0.076))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.405:-0.405:-0.405))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.222:-0.222:-0.222))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.010:0.010:0.010))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.436:0.436:0.436))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.581:0.581:0.581))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.436:0.436:0.436))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.581:0.581:0.581))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.227:-0.227:-0.227))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.073:-0.073:-0.073))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.227:-0.227:-0.227))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.073:-0.073:-0.073))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[34\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.727:0.727:0.727) (0.780:0.780:0.780))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.727:0.727:0.727) (0.780:0.780:0.780)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.727:0.727:0.727) (0.780:0.780:0.780)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.727:0.727:0.727) (0.779:0.779:0.779)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.728:0.728:0.728) (0.780:0.780:0.780)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.412:0.412:0.412))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.457:0.457:0.457))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.412:0.412:0.412))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.457:0.457:0.457))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.017:-0.017:-0.017))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.017:-0.017:-0.017))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.512:0.512:0.512))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.624:0.624:0.624))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.408:0.408:0.408))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.440:0.440:0.440))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.075:-0.075:-0.075))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.452:-0.452:-0.452))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.231:-0.231:-0.231))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.007:-0.007:-0.007))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.430:0.430:0.430))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.515:0.515:0.515))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.430:0.430:0.430))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.515:0.515:0.515))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.243:-0.243:-0.243))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.053:-0.053:-0.053))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.243:-0.243:-0.243))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.053:-0.053:-0.053))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[35\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.699:0.699:0.699) (0.754:0.754:0.754))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.699:0.699:0.699) (0.754:0.754:0.754)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.699:0.699:0.699) (0.754:0.754:0.754)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.699:0.699:0.699) (0.754:0.754:0.754)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.699:0.699:0.699) (0.754:0.754:0.754)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.418:0.418:0.418))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.471:0.471:0.471))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.418:0.418:0.418))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.471:0.471:0.471))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.242:-0.242:-0.242))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.026:-0.026:-0.026))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.242:-0.242:-0.242))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.026:-0.026:-0.026))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.512:0.512:0.512))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.624:0.624:0.624))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.408:0.408:0.408))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.440:0.440:0.440))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.075:-0.075:-0.075))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.452:-0.452:-0.452))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.231:-0.231:-0.231))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.007:-0.007:-0.007))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.418:0.418:0.418))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.454:0.454:0.454))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.417:0.417:0.417))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.454:0.454:0.454))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.248:-0.248:-0.248))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.012:-0.012:-0.012))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.248:-0.248:-0.248))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.012:-0.012:-0.012))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[36\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.697:0.697:0.697) (0.753:0.753:0.753))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.697:0.697:0.697) (0.753:0.753:0.753)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.697:0.697:0.697) (0.753:0.753:0.753)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.697:0.697:0.697) (0.753:0.753:0.753)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.697:0.697:0.697) (0.753:0.753:0.753)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.412:0.412:0.412))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.456:0.456:0.456))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.412:0.412:0.412))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.456:0.456:0.456))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.017:-0.017:-0.017))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.017:-0.017:-0.017))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.512:0.512:0.512))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.624:0.624:0.624))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.408:0.408:0.408))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.440:0.440:0.440))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.075:-0.075:-0.075))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.452:-0.452:-0.452))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.231:-0.231:-0.231))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.007:-0.007:-0.007))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.417:0.417:0.417))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.451:0.451:0.451))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.418:0.418:0.418))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.451:0.451:0.451))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.248:-0.248:-0.248))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.010:-0.010:-0.010))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.248:-0.248:-0.248))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.010:-0.010:-0.010))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[37\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.745:0.745:0.745) (0.795:0.795:0.795))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.745:0.745:0.745) (0.795:0.795:0.795)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.745:0.745:0.745) (0.795:0.795:0.795)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.745:0.745:0.745) (0.795:0.795:0.795)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.745:0.745:0.745) (0.795:0.795:0.795)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.412:0.412:0.412))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.450:0.450:0.450))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.412:0.412:0.412))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.450:0.450:0.450))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.014:-0.014:-0.014))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.014:-0.014:-0.014))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.512:0.512:0.512))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.624:0.624:0.624))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.408:0.408:0.408))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.440:0.440:0.440))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.075:-0.075:-0.075))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.452:-0.452:-0.452))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.231:-0.231:-0.231))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.007:-0.007:-0.007))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.417:0.417:0.417))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.451:0.451:0.451))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.418:0.418:0.418))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.451:0.451:0.451))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.248:-0.248:-0.248))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.010:-0.010:-0.010))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.248:-0.248:-0.248))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.010:-0.010:-0.010))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[38\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.747:0.747:0.747) (0.799:0.799:0.799))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.747:0.747:0.747) (0.799:0.799:0.799)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.747:0.747:0.747) (0.799:0.799:0.799)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.747:0.747:0.747) (0.799:0.799:0.799)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.747:0.747:0.747) (0.799:0.799:0.799)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.408:0.408:0.408))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.418:0.418:0.418))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.408:0.408:0.408))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.420:0.420:0.420))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.258:-0.258:-0.258))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.010:0.010:0.010))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.258:-0.258:-0.258))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.010:0.010:0.010))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.482:0.482:0.482))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.674:0.674:0.674))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.436:0.436:0.436))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.465:0.465:0.465))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.058:-0.058:-0.058))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.520:-0.520:-0.520))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.259:-0.259:-0.259))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.019:-0.019:-0.019))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.414:0.414:0.414))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.427:0.427:0.427))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.414:0.414:0.414))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.427:0.427:0.427))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.262:-0.262:-0.262))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.007:0.007:0.007))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.262:-0.262:-0.262))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.007:0.007:0.007))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[39\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.732:0.732:0.732) (0.787:0.787:0.787))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.732:0.732:0.732) (0.787:0.787:0.787)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.732:0.732:0.732) (0.787:0.787:0.787)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.732:0.732:0.732) (0.787:0.787:0.787)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.732:0.732:0.732) (0.787:0.787:0.787)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.407:0.407:0.407))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.432:0.432:0.432))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.407:0.407:0.407))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.433:0.433:0.433))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.259:-0.259:-0.259))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.000:0.000:0.000))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.259:-0.259:-0.259))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.000:0.000:0.000))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.482:0.482:0.482))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.674:0.674:0.674))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.436:0.436:0.436))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.465:0.465:0.465))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.058:-0.058:-0.058))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.520:-0.520:-0.520))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.259:-0.259:-0.259))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.019:-0.019:-0.019))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.414:0.414:0.414))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.424:0.424:0.424))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.414:0.414:0.414))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.424:0.424:0.424))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.263:-0.263:-0.263))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.010:0.010:0.010))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.263:-0.263:-0.263))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.010:0.010:0.010))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[3\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.435:1.435:1.435) (1.255:1.255:1.255))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.435:1.435:1.435) (1.255:1.255:1.255)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.435:1.435:1.435) (1.255:1.255:1.255)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.435:1.435:1.435) (1.255:1.255:1.255)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.435:1.435:1.435) (1.255:1.255:1.255)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.407:0.407:0.408))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.443:0.450:0.456))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.407:0.407:0.408))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.443:0.450:0.456))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.251:-0.250:-0.250))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.007:-0.010:-0.014))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.251:-0.250:-0.250))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.007:-0.010:-0.014))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.501:0.501:0.501))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.669:0.669:0.669))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.418:0.418:0.418))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.471:0.471:0.471))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.069:-0.069:-0.069))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.505:-0.505:-0.505))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.242:-0.242:-0.242))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.025:-0.025:-0.025))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.426:0.426:0.426))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.524:0.524:0.524))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.426:0.426:0.426))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.524:0.524:0.524))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.242:-0.242:-0.242))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.048:-0.048:-0.048))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.242:-0.242:-0.242))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.048:-0.048:-0.048))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[40\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.728:0.728:0.728) (0.780:0.780:0.780))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.728:0.728:0.728) (0.780:0.780:0.780)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.728:0.728:0.728) (0.780:0.780:0.780)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.728:0.728:0.728) (0.780:0.780:0.780)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.728:0.728:0.728) (0.780:0.780:0.780)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.411:0.412:0.413))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.452:0.455:0.458))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.411:0.412:0.413))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.452:0.454:0.457))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.244))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.015:-0.016:-0.018))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.244))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.015:-0.016:-0.018))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.512:0.512:0.512))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.624:0.624:0.624))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.408:0.408:0.408))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.440:0.440:0.440))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.075:-0.075:-0.075))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.452:-0.452:-0.452))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.231:-0.231:-0.231))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.007:-0.007:-0.007))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.417:0.417:0.417))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.452:0.452:0.452))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.418:0.418:0.418))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.452:0.452:0.452))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.248:-0.248:-0.248))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.010:-0.010:-0.010))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.248:-0.248:-0.248))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.010:-0.010:-0.010))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[41\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.735:0.735:0.735) (0.787:0.787:0.787))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.735:0.735:0.735) (0.787:0.787:0.787)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.735:0.735:0.735) (0.787:0.787:0.787)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.735:0.735:0.735) (0.787:0.787:0.787)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.735:0.735:0.735) (0.787:0.787:0.787)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.408:0.409:0.410))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.442:0.452:0.463))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.408:0.409:0.410))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.441:0.452:0.463))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.249:-0.248:-0.247))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.007:-0.013:-0.019))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.249:-0.248:-0.247))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.007:-0.013:-0.019))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.501:0.501:0.501))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.658:0.658:0.658))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.439:0.439:0.439))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.461:0.461:0.461))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.076:-0.076:-0.076))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.492:-0.492:-0.492))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.251:-0.251:-0.251))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.020:-0.020:-0.020))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.415:0.415:0.415))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.443:0.443:0.443))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.415:0.415:0.415))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.443:0.443:0.443))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.253:-0.253:-0.253))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.005:-0.005:-0.005))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.253:-0.253:-0.253))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.005:-0.005:-0.005))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[42\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.734:0.734:0.734) (0.786:0.786:0.786))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.734:0.734:0.734) (0.787:0.787:0.787)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.734:0.734:0.734) (0.786:0.786:0.786)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.734:0.734:0.734) (0.786:0.786:0.786)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.734:0.734:0.734) (0.786:0.786:0.786)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.409:0.409:0.408))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.438:0.446:0.454))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.409:0.409:0.408))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.438:0.446:0.454))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.249:-0.249:-0.249))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.006:-0.010:-0.014))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.249:-0.249:-0.249))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.006:-0.010:-0.014))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.501:0.501:0.501))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.658:0.658:0.658))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.439:0.439:0.439))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.461:0.461:0.461))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.076:-0.076:-0.076))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.492:-0.492:-0.492))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.251:-0.251:-0.251))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.020:-0.020:-0.020))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.415:0.415:0.415))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.443:0.443:0.443))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.415:0.415:0.415))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.443:0.443:0.443))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.253:-0.253:-0.253))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.004:-0.004:-0.004))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.253:-0.253:-0.253))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.004:-0.004:-0.004))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[43\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.729:0.729:0.729) (0.782:0.782:0.782))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.729:0.729:0.729) (0.782:0.782:0.782)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.729:0.729:0.729) (0.782:0.782:0.782)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.729:0.729:0.729) (0.782:0.782:0.782)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.729:0.729:0.729) (0.782:0.782:0.782)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.409:0.409:0.408))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.438:0.446:0.454))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.409:0.409:0.408))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.438:0.446:0.454))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.249:-0.249:-0.249))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.006:-0.010:-0.014))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.249:-0.249:-0.249))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.006:-0.010:-0.014))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.501:0.501:0.501))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.658:0.658:0.658))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.439:0.439:0.439))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.461:0.461:0.461))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.076:-0.076:-0.076))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.492:-0.492:-0.492))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.251:-0.251:-0.251))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.020:-0.020:-0.020))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.415:0.415:0.415))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.443:0.443:0.443))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.415:0.415:0.415))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.443:0.443:0.443))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.253:-0.253:-0.253))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.004:-0.004:-0.004))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.253:-0.253:-0.253))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.004:-0.004:-0.004))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[44\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.649:0.649:0.649) (0.702:0.702:0.702))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.649:0.649:0.649) (0.702:0.702:0.702)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.649:0.649:0.649) (0.702:0.702:0.702)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.649:0.649:0.649) (0.702:0.702:0.702)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.649:0.649:0.649) (0.702:0.702:0.702)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.471:0.472:0.473))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.536:0.538:0.540))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.471:0.472:0.473))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.536:0.538:0.540))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.242:-0.241:-0.241))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.077:-0.079:-0.080))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.242:-0.241:-0.241))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.077:-0.079:-0.080))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.591:0.591:0.591))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.631:0.631:0.631))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.449:0.449:0.449))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.493:0.493:0.493))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.131:-0.131:-0.131))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.401:-0.401:-0.401))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.219:-0.219:-0.219))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.047:-0.047:-0.047))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.475:0.475:0.475))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.538:0.538:0.538))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.475:0.475:0.475))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.538:0.538:0.538))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.244:-0.244:-0.244))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.080:-0.080:-0.080))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.244:-0.244:-0.244))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.080:-0.080:-0.080))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[45\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.640:0.640:0.640) (0.694:0.694:0.694))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.640:0.640:0.640) (0.694:0.694:0.694)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.640:0.640:0.640) (0.694:0.694:0.694)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.640:0.640:0.640) (0.694:0.694:0.694)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.640:0.640:0.640) (0.694:0.694:0.694)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.471:0.473:0.474))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.536:0.543:0.550))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.471:0.473:0.474))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.536:0.543:0.550))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.242:-0.241:-0.240))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.076:-0.083:-0.089))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.242:-0.241:-0.240))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.076:-0.083:-0.089))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.591:0.591:0.591))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.631:0.631:0.631))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.449:0.449:0.449))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.493:0.493:0.493))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.131:-0.131:-0.131))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.401:-0.401:-0.401))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.219:-0.219:-0.219))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.047:-0.047:-0.047))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.475:0.475:0.475))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.538:0.538:0.538))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.475:0.475:0.475))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.538:0.538:0.538))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.244:-0.244:-0.244))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.081:-0.081:-0.081))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.244:-0.244:-0.244))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.081:-0.081:-0.081))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[46\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.665:0.665:0.665) (0.717:0.717:0.717))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.665:0.665:0.665) (0.717:0.717:0.717)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.665:0.665:0.665) (0.717:0.717:0.717)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.665:0.665:0.665) (0.717:0.717:0.717)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.665:0.665:0.665) (0.717:0.717:0.717)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.468:0.470:0.471))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.532:0.538:0.544))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.468:0.470:0.471))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.532:0.538:0.544))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.241:-0.240:-0.239))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.073:-0.079:-0.084))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.241:-0.240:-0.239))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.073:-0.079:-0.084))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.589:0.589:0.589))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.634:0.634:0.634))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.449:0.449:0.449))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.492:0.492:0.492))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.129:-0.129:-0.129))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.406:-0.406:-0.406))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.220:-0.220:-0.220))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.047:-0.047:-0.047))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.472:0.472:0.472))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.534:0.534:0.534))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.472:0.472:0.472))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.534:0.534:0.534))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.243:-0.243:-0.243))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.077:-0.077:-0.077))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.243:-0.243:-0.243))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.077:-0.077:-0.077))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[47\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.738:0.738:0.738) (0.788:0.788:0.788))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.738:0.738:0.738) (0.788:0.788:0.788)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.738:0.738:0.738) (0.788:0.788:0.788)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.738:0.738:0.738) (0.788:0.788:0.788)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.738:0.738:0.738) (0.788:0.788:0.788)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.414:0.414:0.413))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.455:0.463:0.471))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.414:0.414:0.413))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.455:0.463:0.470))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.242:-0.242:-0.242))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.018:-0.022:-0.026))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.242:-0.242:-0.242))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.018:-0.022:-0.026))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.513:0.513:0.513))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.586:0.586:0.586))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.395:0.395:0.395))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.415:0.415:0.415))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.073:-0.073:-0.073))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.408:-0.408:-0.408))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.223:-0.223:-0.223))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.013:0.013:0.013))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.420:0.420:0.420))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.463:0.463:0.463))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.419:0.419:0.419))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.463:0.463:0.463))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.018:-0.018:-0.018))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.018:-0.018:-0.018))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[48\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.730:0.730:0.730) (0.781:0.781:0.781))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.730:0.730:0.730) (0.781:0.781:0.781)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.730:0.730:0.730) (0.781:0.781:0.781)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.730:0.730:0.730) (0.781:0.781:0.781)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.730:0.730:0.730) (0.781:0.781:0.781)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.415:0.414:0.414))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.459:0.460:0.461))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.415:0.414:0.414))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.459:0.460:0.461))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.242:-0.242:-0.242))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.020:-0.020:-0.021))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.242:-0.242:-0.242))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.020:-0.020:-0.021))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.513:0.513:0.513))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.586:0.586:0.586))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.395:0.395:0.395))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.415:0.415:0.415))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.073:-0.073:-0.073))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.408:-0.408:-0.408))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.223:-0.223:-0.223))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.013:0.013:0.013))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.420:0.420:0.420))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.464:0.464:0.464))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.419:0.419:0.419))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.464:0.464:0.464))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.018:-0.018:-0.018))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.018:-0.018:-0.018))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[49\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.697:0.697:0.697) (0.752:0.752:0.752))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.697:0.697:0.697) (0.753:0.753:0.753)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.697:0.697:0.697) (0.752:0.752:0.752)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.697:0.697:0.697) (0.752:0.752:0.752)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.697:0.697:0.697) (0.752:0.752:0.752)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.415:0.416:0.418))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.455:0.465:0.475))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.415:0.416:0.418))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.455:0.465:0.474))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.242:-0.242:-0.241))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.017:-0.023:-0.029))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.242:-0.242:-0.241))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.017:-0.023:-0.029))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.513:0.513:0.513))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.586:0.586:0.586))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.395:0.395:0.395))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.415:0.415:0.415))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.073:-0.073:-0.073))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.408:-0.408:-0.408))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.223:-0.223:-0.223))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.013:0.013:0.013))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.419:0.419:0.419))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.463:0.463:0.463))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.419:0.419:0.419))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.463:0.463:0.463))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.017:-0.017:-0.017))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.017:-0.017:-0.017))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[4\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.406:1.406:1.406) (1.237:1.237:1.237))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.405:1.405:1.405) (1.237:1.237:1.237)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.405:1.405:1.405) (1.237:1.237:1.237)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.406:1.406:1.406) (1.237:1.237:1.237)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.406:1.406:1.406) (1.237:1.237:1.237)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.407:0.407:0.407))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.446:0.449:0.453))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.407:0.407:0.407))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.445:0.449:0.452))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.251:-0.251:-0.250))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.008:-0.010:-0.012))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.251:-0.251:-0.250))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.008:-0.010:-0.012))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.501:0.501:0.501))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.669:0.669:0.669))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.418:0.418:0.418))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.471:0.471:0.471))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.069:-0.069:-0.069))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.505:-0.505:-0.505))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.242:-0.242:-0.242))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.025:-0.025:-0.025))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.426:0.426:0.426))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.524:0.524:0.524))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.426:0.426:0.426))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.524:0.524:0.524))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.242:-0.242:-0.242))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.048:-0.048:-0.048))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.242:-0.242:-0.242))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.048:-0.048:-0.048))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[50\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.640:0.640:0.640) (0.694:0.694:0.694))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.640:0.640:0.640) (0.694:0.694:0.694)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.640:0.640:0.640) (0.694:0.694:0.694)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.640:0.640:0.640) (0.694:0.694:0.694)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.640:0.640:0.640) (0.694:0.694:0.694)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.469:0.470:0.471))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.532:0.539:0.546))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.469:0.470:0.471))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.532:0.539:0.546))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.240:-0.240:-0.239))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.074:-0.080:-0.086))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.240:-0.240:-0.239))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.074:-0.080:-0.086))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.589:0.589:0.589))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.634:0.634:0.634))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.449:0.449:0.449))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.492:0.492:0.492))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.129:-0.129:-0.129))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.406:-0.406:-0.406))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.220:-0.220:-0.220))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.047:-0.047:-0.047))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.471:0.471:0.471))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.533:0.533:0.533))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.471:0.471:0.471))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.533:0.533:0.533))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.242:-0.242:-0.242))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.075:-0.075:-0.075))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.242:-0.242:-0.242))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.075:-0.075:-0.075))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[51\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.691:0.691:0.691) (0.747:0.747:0.747))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.691:0.691:0.691) (0.747:0.747:0.747)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.691:0.691:0.691) (0.747:0.747:0.747)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.691:0.691:0.691) (0.747:0.747:0.747)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.691:0.691:0.691) (0.747:0.747:0.747)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.414:0.417:0.421))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.457:0.467:0.477))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.414:0.417:0.421))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.457:0.467:0.476))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.242:-0.241:-0.241))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.018:-0.025:-0.031))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.242:-0.241:-0.241))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.018:-0.025:-0.031))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.513:0.513:0.513))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.583:0.583:0.583))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.394:0.394:0.394))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.414:0.414:0.414))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.072:-0.072:-0.072))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.406:-0.406:-0.406))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.223:-0.223:-0.223))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.014:0.014:0.014))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.418:0.418:0.418))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.460:0.460:0.460))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.418:0.418:0.418))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.460:0.460:0.460))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.016:-0.016:-0.016))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.016:-0.016:-0.016))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[52\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.695:0.695:0.695) (0.750:0.750:0.750))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.695:0.695:0.695) (0.750:0.750:0.750)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.695:0.695:0.695) (0.750:0.750:0.750)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.695:0.695:0.695) (0.750:0.750:0.750)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.695:0.695:0.695) (0.750:0.750:0.750)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.416:0.416:0.416))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.454:0.454:0.454))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.416:0.416:0.416))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.454:0.454:0.454))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.242:-0.242:-0.242))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.015:-0.015:-0.015))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.242:-0.242:-0.242))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.015:-0.015:-0.015))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.513:0.513:0.513))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.583:0.583:0.583))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.394:0.394:0.394))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.414:0.414:0.414))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.072:-0.072:-0.072))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.406:-0.406:-0.406))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.223:-0.223:-0.223))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.014:0.014:0.014))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.418:0.418:0.418))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.458:0.458:0.458))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.420:0.420:0.420))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.458:0.458:0.458))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.015:-0.015:-0.015))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.015:-0.015:-0.015))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[53\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.692:0.692:0.692) (0.748:0.748:0.748))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.692:0.692:0.692) (0.748:0.748:0.748)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.692:0.692:0.692) (0.748:0.748:0.748)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.692:0.692:0.692) (0.748:0.748:0.748)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.692:0.692:0.692) (0.748:0.748:0.748)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.414:0.415:0.416))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.452:0.460:0.469))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.414:0.415:0.416))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.452:0.460:0.468))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.243:-0.243:-0.242))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.015:-0.020:-0.025))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.243:-0.243:-0.242))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.015:-0.020:-0.025))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.514:0.514:0.514))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.615:0.615:0.615))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.406:0.406:0.406))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.436:0.436:0.436))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.076:-0.076:-0.076))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.441:-0.441:-0.441))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.229:-0.229:-0.229))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.004:-0.004:-0.004))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.418:0.418:0.418))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.455:0.455:0.455))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.419:0.419:0.419))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.455:0.455:0.455))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.246:-0.246:-0.246))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.013:-0.013:-0.013))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.246:-0.246:-0.246))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.013:-0.013:-0.013))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[54\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.707:0.707:0.707) (0.762:0.762:0.762))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.707:0.707:0.707) (0.762:0.762:0.762)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.707:0.707:0.707) (0.762:0.762:0.762)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.707:0.707:0.707) (0.762:0.762:0.762)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.707:0.707:0.707) (0.762:0.762:0.762)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.413:0.416:0.419))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.454:0.461:0.468))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.413:0.416:0.419))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.454:0.460:0.467))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.243:-0.243:-0.242))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.016:-0.020:-0.024))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.243:-0.243:-0.242))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.016:-0.020:-0.024))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.514:0.514:0.514))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.615:0.615:0.615))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.406:0.406:0.406))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.436:0.436:0.436))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.076:-0.076:-0.076))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.441:-0.441:-0.441))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.229:-0.229:-0.229))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.004:-0.004:-0.004))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.418:0.418:0.418))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.454:0.454:0.454))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.419:0.419:0.419))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.454:0.454:0.454))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.246:-0.246:-0.246))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.012:-0.012:-0.012))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.246:-0.246:-0.246))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.012:-0.012:-0.012))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[55\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.643:0.643:0.643) (0.698:0.698:0.698))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.643:0.643:0.643) (0.698:0.698:0.698)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.643:0.643:0.643) (0.698:0.698:0.698)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.643:0.643:0.643) (0.698:0.698:0.698)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.643:0.643:0.643) (0.698:0.698:0.698)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.463:0.464:0.465))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.523:0.530:0.536))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.463:0.464:0.465))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.523:0.530:0.536))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.239:-0.238:-0.237))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.066:-0.072:-0.077))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.239:-0.238:-0.237))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.066:-0.072:-0.077))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.584:0.584:0.584))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.661:0.661:0.661))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.454:0.454:0.454))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.509:0.509:0.509))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.132:-0.132:-0.132))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.437:-0.437:-0.437))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.227:-0.227:-0.227))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.063:-0.063:-0.063))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.467:0.467:0.467))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.528:0.528:0.528))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.467:0.467:0.467))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.528:0.528:0.528))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.240:-0.240:-0.240))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.071:-0.071:-0.071))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.240:-0.240:-0.240))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.071:-0.071:-0.071))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[56\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.713:0.713:0.713) (0.766:0.766:0.766))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.713:0.713:0.713) (0.766:0.766:0.766)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.713:0.713:0.713) (0.766:0.766:0.766)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.713:0.713:0.713) (0.766:0.766:0.766)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.713:0.713:0.713) (0.766:0.766:0.766)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.413:0.416:0.419))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.454:0.461:0.468))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.413:0.416:0.419))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.454:0.460:0.467))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.243:-0.243:-0.242))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.016:-0.020:-0.024))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.243:-0.243:-0.242))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.016:-0.020:-0.024))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.514:0.514:0.514))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.615:0.615:0.615))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.406:0.406:0.406))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.436:0.436:0.436))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.076:-0.076:-0.076))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.441:-0.441:-0.441))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.229:-0.229:-0.229))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.004:-0.004:-0.004))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.418:0.418:0.418))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.456:0.456:0.457))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.418:0.418:0.418))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.456:0.456:0.457))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.246:-0.246:-0.246))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.013:-0.013:-0.013))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.246:-0.246:-0.246))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.013:-0.013:-0.013))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[57\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.700:0.700:0.700) (0.755:0.755:0.755))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.700:0.700:0.700) (0.755:0.755:0.755)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.700:0.700:0.700) (0.755:0.755:0.755)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.700:0.700:0.700) (0.755:0.755:0.755)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.700:0.700:0.700) (0.755:0.755:0.755)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.413:0.415:0.417))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.453:0.459:0.466))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.413:0.415:0.417))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.453:0.459:0.466))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.243:-0.243:-0.242))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.016:-0.019:-0.023))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.243:-0.243:-0.242))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.016:-0.019:-0.023))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.514:0.514:0.514))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.615:0.615:0.615))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.406:0.406:0.406))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.436:0.436:0.436))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.076:-0.076:-0.076))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.441:-0.441:-0.441))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.229:-0.229:-0.229))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.003:-0.003:-0.003))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.418:0.418:0.418))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.457:0.457:0.457))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.418:0.418:0.418))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.457:0.457:0.457))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.246:-0.246:-0.246))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.014:-0.014:-0.014))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.246:-0.246:-0.246))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.014:-0.014:-0.014))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[58\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.641:0.641:0.641) (0.696:0.696:0.696))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.641:0.641:0.641) (0.696:0.696:0.696)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.640:0.640:0.640) (0.696:0.696:0.696)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.641:0.641:0.641) (0.696:0.696:0.696)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.641:0.641:0.641) (0.696:0.696:0.696)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.463:0.464:0.466))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.524:0.530:0.537))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.463:0.464:0.466))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.524:0.530:0.537))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.239:-0.238:-0.237))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.067:-0.072:-0.078))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.239:-0.238:-0.237))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.067:-0.072:-0.078))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.582:0.582:0.582))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.628:0.628:0.628))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.443:0.443:0.443))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.485:0.485:0.485))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.123:-0.123:-0.123))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.404:-0.404:-0.404))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.219:-0.219:-0.219))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.042:-0.042:-0.042))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.467:0.467:0.467))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.527:0.527:0.527))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.467:0.467:0.467))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.527:0.527:0.527))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.240:-0.240:-0.240))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.070:-0.070:-0.070))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.240:-0.240:-0.240))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.070:-0.070:-0.070))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[59\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.737:0.737:0.737) (0.788:0.788:0.788))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.737:0.737:0.737) (0.788:0.788:0.788)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.737:0.737:0.737) (0.788:0.788:0.788)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.737:0.737:0.737) (0.788:0.788:0.788)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.737:0.737:0.737) (0.788:0.788:0.788)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.414:0.413:0.413))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.451:0.456:0.461))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.414:0.413:0.413))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.451:0.456:0.461))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.243:-0.243:-0.243))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.014:-0.017:-0.021))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.243:-0.243:-0.243))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.014:-0.017:-0.021))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.510:0.510:0.510))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.584:0.584:0.584))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.394:0.394:0.394))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.412:0.412:0.412))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.070:-0.070:-0.070))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.408:-0.408:-0.408))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.224:-0.224:-0.224))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.016:0.016:0.016))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.418:0.418:0.418))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.456:0.456:0.456))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.418:0.418:0.418))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.456:0.456:0.456))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.246:-0.246:-0.246))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.013:-0.013:-0.013))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.246:-0.246:-0.246))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.013:-0.013:-0.013))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[5\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.696:0.696:0.696) (0.741:0.741:0.741))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.696:0.696:0.696) (0.742:0.742:0.742)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.696:0.696:0.696) (0.741:0.741:0.741)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.696:0.696:0.696) (0.741:0.741:0.741)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.696:0.696:0.696) (0.742:0.742:0.742)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.466:0.467:0.468))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.533:0.539:0.544))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.466:0.467:0.468))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.533:0.539:0.544))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.239:-0.238:-0.238))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.075:-0.079:-0.084))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.239:-0.238:-0.238))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.075:-0.079:-0.084))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.584:0.584:0.584))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.631:0.631:0.631))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.445:0.445:0.445))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.488:0.488:0.488))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.125:-0.125:-0.125))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.406:-0.406:-0.406))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.220:-0.220:-0.220))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.044:-0.044:-0.044))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.482:0.482:0.482))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.612:0.612:0.612))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.482:0.482:0.482))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.612:0.612:0.612))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.235:-0.235:-0.235))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.116:-0.116:-0.116))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.235:-0.235:-0.235))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.116:-0.116:-0.116))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[60\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.716:0.716:0.716) (0.769:0.769:0.769))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.716:0.716:0.716) (0.769:0.769:0.769)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.716:0.716:0.716) (0.769:0.769:0.769)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.716:0.716:0.716) (0.769:0.769:0.769)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.716:0.716:0.716) (0.769:0.769:0.769)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.411:0.414:0.416))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.448:0.455:0.462))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.411:0.414:0.416))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.447:0.454:0.461))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.246:-0.244:-0.243))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.012:-0.016:-0.020))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.246:-0.244:-0.243))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.012:-0.016:-0.020))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.512:0.512:0.512))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.629:0.629:0.629))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.431:0.431:0.431))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.442:0.442:0.442))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.081:-0.081:-0.081))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.458:-0.458:-0.458))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.242:-0.242:-0.242))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.008:-0.008:-0.008))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.417:0.417:0.417))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.454:0.454:0.454))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.417:0.417:0.417))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.454:0.454:0.454))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.249:-0.249:-0.249))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.011:-0.011:-0.011))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.249:-0.249:-0.249))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.011:-0.011:-0.011))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[61\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.720:0.720:0.720) (0.773:0.773:0.773))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.720:0.720:0.720) (0.773:0.773:0.773)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.720:0.720:0.720) (0.773:0.773:0.773)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.720:0.720:0.720) (0.773:0.773:0.773)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.720:0.720:0.720) (0.773:0.773:0.773)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.412:0.413:0.415))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.447:0.455:0.463))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.412:0.413:0.415))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.447:0.455:0.462))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.244))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.011:-0.016:-0.020))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.244))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.011:-0.016:-0.020))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.513:0.513:0.513))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.629:0.629:0.629))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.432:0.432:0.432))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.443:0.443:0.443))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.082:-0.082:-0.082))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.458:-0.458:-0.458))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.242:-0.242:-0.242))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.009:-0.009:-0.009))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.417:0.417:0.417))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.451:0.451:0.451))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.417:0.417:0.417))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.451:0.451:0.451))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.249:-0.249:-0.249))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.010:-0.010:-0.010))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.249:-0.249:-0.249))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.010:-0.010:-0.010))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[62\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.718:0.718:0.718) (0.771:0.771:0.771))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.718:0.718:0.718) (0.771:0.771:0.771)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.718:0.718:0.718) (0.771:0.771:0.771)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.718:0.718:0.718) (0.771:0.771:0.771)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.718:0.718:0.718) (0.771:0.771:0.771)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.412:0.411:0.411))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.446:0.450:0.455))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.412:0.411:0.411))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.446:0.450:0.455))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.246:-0.246:-0.246))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.010:-0.013:-0.016))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.246:-0.246:-0.246))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.010:-0.013:-0.016))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.512:0.512:0.512))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.629:0.629:0.629))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.431:0.431:0.431))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.442:0.442:0.442))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.081:-0.081:-0.081))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.458:-0.458:-0.458))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.242:-0.242:-0.242))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.008:-0.008:-0.008))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.417:0.417:0.417))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.451:0.451:0.451))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.417:0.417:0.417))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.451:0.451:0.451))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.249:-0.249:-0.249))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.010:-0.010:-0.010))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.249:-0.249:-0.249))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.010:-0.010:-0.010))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[63\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.704:0.704:0.704) (0.759:0.759:0.759))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.703:0.703:0.703) (0.759:0.759:0.759)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.704:0.704:0.704) (0.759:0.759:0.759)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.704:0.704:0.704) (0.759:0.759:0.759)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.704:0.704:0.704) (0.759:0.759:0.759)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.412:0.411:0.411))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.446:0.451:0.457))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.412:0.411:0.411))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.446:0.451:0.456))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.246:-0.246:-0.246))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.010:-0.014:-0.017))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.246:-0.246:-0.246))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.010:-0.014:-0.017))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.513:0.513:0.513))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.640:0.640:0.640))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.426:0.426:0.426))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.451:0.451:0.451))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.080:-0.080:-0.080))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.470:-0.470:-0.470))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.240:-0.240:-0.240))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.015:-0.015:-0.015))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.417:0.417:0.417))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.451:0.451:0.451))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.417:0.417:0.417))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.451:0.451:0.451))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.249:-0.249:-0.249))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.009:-0.009:-0.009))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.249:-0.249:-0.249))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.009:-0.009:-0.009))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[64\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.703:0.703:0.703) (0.758:0.758:0.758))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.703:0.703:0.703) (0.758:0.758:0.758)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.703:0.703:0.703) (0.758:0.758:0.758)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.703:0.703:0.703) (0.758:0.758:0.758)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.703:0.703:0.703) (0.758:0.758:0.758)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.413:0.414:0.415))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.458:0.464:0.470))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.413:0.414:0.415))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.458:0.463:0.469))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.242:-0.242:-0.242))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.019:-0.022:-0.026))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.242:-0.242:-0.242))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.019:-0.022:-0.026))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.517:0.517:0.517))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.625:0.625:0.625))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.410:0.410:0.410))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.445:0.445:0.445))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.080:-0.080:-0.080))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.449:-0.449:-0.449))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.230:-0.230:-0.230))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.011:-0.011:-0.011))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.418:0.418:0.418))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.458:0.458:0.458))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.419:0.419:0.419))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.458:0.458:0.458))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.014:-0.014:-0.014))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.014:-0.014:-0.014))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[65\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.725:0.725:0.725) (0.776:0.776:0.776))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.725:0.725:0.725) (0.776:0.776:0.776)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.725:0.725:0.725) (0.776:0.776:0.776)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.725:0.725:0.725) (0.776:0.776:0.776)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.725:0.725:0.725) (0.776:0.776:0.776)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.414:0.414:0.413))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.454:0.460:0.466))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.414:0.414:0.413))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.454:0.460:0.466))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.243:-0.242:-0.242))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.017:-0.020:-0.024))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.243:-0.242:-0.242))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.017:-0.020:-0.024))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.517:0.517:0.517))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.625:0.625:0.625))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.410:0.410:0.410))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.445:0.445:0.445))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.080:-0.080:-0.080))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.449:-0.449:-0.449))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.230:-0.230:-0.230))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.011:-0.011:-0.011))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.418:0.418:0.418))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.459:0.459:0.459))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.419:0.419:0.419))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.459:0.459:0.459))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.015:-0.015:-0.015))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.015:-0.015:-0.015))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[66\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.685:0.685:0.685) (0.741:0.741:0.741))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.685:0.685:0.685) (0.741:0.741:0.741)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.685:0.685:0.685) (0.741:0.741:0.741)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.685:0.685:0.685) (0.741:0.741:0.741)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.685:0.685:0.685) (0.741:0.741:0.741)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.417:0.418:0.419))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.468:0.477:0.487))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.417:0.418:0.419))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.467:0.477:0.486))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.238:-0.238:-0.238))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.026:-0.032:-0.039))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.238:-0.238:-0.238))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.026:-0.032:-0.039))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.520:0.520:0.520))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.577:0.577:0.577))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.394:0.394:0.394))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.419:0.419:0.419))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.075:-0.075:-0.075))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.393:-0.393:-0.393))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.214:-0.214:-0.214))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.011:0.011:0.011))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.421:0.421:0.421))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.474:0.474:0.474))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.421:0.421:0.421))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.474:0.474:0.474))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.240:-0.240:-0.240))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.024:-0.024:-0.024))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.240:-0.240:-0.240))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.024:-0.024:-0.024))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[67\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.713:0.713:0.713) (0.766:0.766:0.766))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.713:0.713:0.713) (0.766:0.766:0.766)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.713:0.713:0.713) (0.766:0.766:0.766)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.713:0.713:0.713) (0.766:0.766:0.766)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.713:0.713:0.713) (0.766:0.766:0.766)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.413:0.414:0.415))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.457:0.466:0.474))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.413:0.414:0.415))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.457:0.465:0.474))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.242:-0.242:-0.242))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.018:-0.024:-0.029))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.242:-0.242:-0.242))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.018:-0.024:-0.029))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.517:0.517:0.517))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.625:0.625:0.625))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.410:0.410:0.410))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.445:0.445:0.445))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.080:-0.080:-0.080))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.449:-0.449:-0.449))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.230:-0.230:-0.230))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.011:-0.011:-0.011))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.418:0.418:0.418))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.458:0.458:0.458))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.419:0.419:0.419))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.458:0.458:0.458))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.014:-0.014:-0.014))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.014:-0.014:-0.014))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[68\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.700:0.700:0.700) (0.755:0.755:0.755))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.700:0.700:0.700) (0.755:0.755:0.755)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.700:0.700:0.700) (0.755:0.755:0.755)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.700:0.700:0.700) (0.755:0.755:0.755)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.700:0.700:0.700) (0.755:0.755:0.755)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.413:0.414:0.415))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.456:0.466:0.476))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.413:0.414:0.415))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.456:0.466:0.475))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.242:-0.242:-0.242))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.018:-0.024:-0.030))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.242:-0.242:-0.242))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.018:-0.024:-0.030))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.517:0.517:0.517))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.625:0.625:0.625))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.410:0.410:0.410))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.445:0.445:0.445))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.080:-0.080:-0.080))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.449:-0.449:-0.449))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.230:-0.230:-0.230))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.011:-0.011:-0.011))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.418:0.418:0.418))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.460:0.460:0.460))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.418:0.418:0.418))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.460:0.460:0.460))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.015:-0.015:-0.015))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.015:-0.015:-0.015))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[69\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.742:0.742:0.742) (0.791:0.791:0.791))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.742:0.742:0.742) (0.791:0.791:0.791)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.742:0.742:0.742) (0.791:0.791:0.791)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.742:0.742:0.742) (0.791:0.791:0.791)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.742:0.742:0.742) (0.791:0.791:0.791)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.414:0.414:0.414))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.462:0.462:0.462))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.414:0.414:0.414))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.462:0.462:0.462))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.243:-0.243:-0.243))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.021:-0.021:-0.021))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.243:-0.243:-0.243))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.021:-0.021:-0.021))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.517:0.517:0.517))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.625:0.625:0.625))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.410:0.410:0.410))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.445:0.445:0.445))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.080:-0.080:-0.080))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.449:-0.449:-0.449))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.230:-0.230:-0.230))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.011:-0.011:-0.011))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.418:0.418:0.418))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.458:0.458:0.458))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.419:0.419:0.419))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.458:0.458:0.458))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.015:-0.015:-0.015))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.015:-0.015:-0.015))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[6\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.340:1.340:1.340) (1.195:1.195:1.195))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.340:1.340:1.340) (1.195:1.195:1.195)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.340:1.340:1.340) (1.195:1.195:1.195)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.340:1.340:1.340) (1.195:1.195:1.195)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.340:1.340:1.340) (1.195:1.195:1.195)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.412:0.412:0.412))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.460:0.460:0.460))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.412:0.412:0.412))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.460:0.460:0.460))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.246:-0.246:-0.246))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.016:-0.016:-0.016))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.246:-0.246:-0.246))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.016:-0.016:-0.016))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.494:0.494:0.494))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.579:0.579:0.579))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.387:0.387:0.387))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.395:0.395:0.395))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.056:-0.056:-0.056))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.416:-0.416:-0.416))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.230:-0.230:-0.230))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.029:0.029:0.029))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.415:0.415:0.415))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.442:0.442:0.442))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.414:0.414:0.414))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.442:0.442:0.442))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.254:-0.254:-0.254))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.005:-0.005:-0.005))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.254:-0.254:-0.254))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.005:-0.005:-0.005))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[7\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.584:1.584:1.584) (1.354:1.354:1.354))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.584:1.584:1.584) (1.354:1.354:1.354)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.584:1.584:1.584) (1.354:1.354:1.354)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.584:1.584:1.584) (1.354:1.354:1.354)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.584:1.584:1.584) (1.354:1.354:1.354)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.408:0.408:0.408))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.420:0.420:0.420))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.408:0.408:0.408))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.422:0.422:0.422))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.258:-0.258:-0.258))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.007:0.007:0.007))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.258:-0.258:-0.258))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.007:0.007:0.007))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.482:0.482:0.482))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.674:0.674:0.674))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.436:0.436:0.436))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.465:0.465:0.465))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.058:-0.058:-0.058))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.520:-0.520:-0.520))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.259:-0.259:-0.259))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.019:-0.019:-0.019))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.422:0.422:0.422))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.491:0.491:0.491))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.422:0.422:0.422))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.491:0.491:0.491))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.253:-0.253:-0.253))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.033:-0.033:-0.033))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.253:-0.253:-0.253))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.033:-0.033:-0.033))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[8\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.477:1.477:1.477) (1.286:1.286:1.286))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.477:1.477:1.477) (1.286:1.286:1.286)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.477:1.477:1.477) (1.286:1.286:1.286)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.477:1.477:1.477) (1.286:1.286:1.286)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.477:1.477:1.477) (1.286:1.286:1.286)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.408:0.408:0.408))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.437:0.437:0.437))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.408:0.408:0.408))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.437:0.437:0.437))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.254:-0.254:-0.254))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.002:-0.002:-0.002))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.254:-0.254:-0.254))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.002:-0.002:-0.002))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.482:0.482:0.482))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.674:0.674:0.674))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.436:0.436:0.436))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.465:0.465:0.465))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.058:-0.058:-0.058))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.520:-0.520:-0.520))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.259:-0.259:-0.259))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.019:-0.019:-0.019))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.425:0.425:0.425))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.535:0.535:0.535))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.425:0.425:0.425))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.535:0.535:0.535))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.242:-0.242:-0.242))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.044:-0.044:-0.044))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.242:-0.242:-0.242))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.044:-0.044:-0.044))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[9\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.641:1.641:1.641) (1.388:1.388:1.388))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.641:1.641:1.641) (1.388:1.388:1.388)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.641:1.641:1.641) (1.388:1.388:1.388)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.641:1.641:1.641) (1.388:1.388:1.388)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.641:1.641:1.641) (1.388:1.388:1.388)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.413:0.413:0.413))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.457:0.457:0.457))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.413:0.413:0.413))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.457:0.457:0.457))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.253:-0.253:-0.253))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.014:-0.014:-0.014))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.253:-0.253:-0.253))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.014:-0.014:-0.014))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.486:0.486:0.486))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.627:0.627:0.627))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.403:0.403:0.403))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.420:0.420:0.420))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.055:-0.055:-0.055))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.473:-0.473:-0.473))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.243:-0.243:-0.243))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.010:0.010:0.010))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.424:0.424:0.424))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.515:0.515:0.515))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.424:0.424:0.424))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.515:0.515:0.515))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.247:-0.247:-0.247))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.039:-0.039:-0.039))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.247:-0.247:-0.247))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.039:-0.039:-0.039))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__dlyb_1")
(INSTANCE input1)
(DELAY
(ABSOLUTE
(IOPATH I Z (0.880:0.880:0.880) (0.961:0.961:0.961))
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(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__buf_1")
(INSTANCE input2)
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(ABSOLUTE
(IOPATH I Z (0.793:0.793:0.793) (0.624:0.624:0.624))
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)
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(IOPATH I Z (0.983:0.983:0.983) (1.282:1.282:1.282))
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(IOPATH I Z (1.991:1.991:1.991) (2.104:2.104:2.104))
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