commit | 42b7c844d22f52b97b4c6c62b501acef09739dc0 | [log] [tgz] |
---|---|---|
author | Greg Davill <greg.davill@gmail.com> | Mon Dec 05 00:56:32 2022 +1030 |
committer | Greg Davill <greg.davill@gmail.com> | Mon Dec 05 00:58:33 2022 +1030 |
tree | 45f5425cfbb1eb2ce70fec188e52dfa2692d0215 | |
parent | 33dfe5c116d7b01cea0c5ece22e5bde5abcc7324 [diff] |
rtl: Add extra serv instance
An award winning CPU design fit into the GF180 MPW0 Shuttle.
To keep the design simple this project places a Serv CPU with a scan-chain around it connecting it's wishbone bus which is a combination of data and instructions out via I/O pins.
Another I/O pin is responsible for handling clock and reset. Operation will run as follows:
In this manner we should be able to implement external peripherals like UARTs, timers, and GPIOs. The external controller can be a microcontroller, FPGA, or the caravel harness SoC.