commit | 04b51ee3d3e8f1258dc60caf4ece37037c4e2965 | [log] [tgz] |
---|---|---|
author | tinybot <bot@tinytapeout.com> | Mon Dec 05 11:13:07 2022 +0000 |
committer | tinybot <bot@tinytapeout.com> | Mon Dec 05 11:13:07 2022 +0000 |
tree | 40c7d4dc97ba5ea94db65bc8138c26e0be391b4a | |
parent | a513925ce3452c0861422a3059772fa1ff96a6c5 [diff] |
harden project [skip ci]
An award winning CPU design fit into the GF180 MPW0 Shuttle.
To keep the design simple this project places a Serv CPU with a scan-chain around it connecting it's wishbone bus which is a combination of data and instructions out via I/O pins.
Another I/O pin is responsible for handling clock and reset. Operation will run as follows:
In this manner we should be able to implement external peripherals like UARTs, timers, and GPIOs. The external controller can be a microcontroller, FPGA, or the caravel harness SoC.