| commit | a513925ce3452c0861422a3059772fa1ff96a6c5 | [log] [tgz] |
|---|---|---|
| author | Greg Davill <greg.davill@gmail.com> | Mon Dec 05 21:22:12 2022 +1030 |
| committer | Greg Davill <greg.davill@gmail.com> | Mon Dec 05 21:22:12 2022 +1030 |
| tree | a8ca4b23c2a03cf6e17252645241ca897bf2f11c | |
| parent | da29cfe0e6732275435aceb348881a2ff8339034 [diff] |
gds: Add sram256x8m8wm1 with V5_Xtor fix
An award winning CPU design fit into the GF180 MPW0 Shuttle.
To keep the design simple this project places a Serv CPU with a scan-chain around it connecting it's wishbone bus which is a combination of data and instructions out via I/O pins.
Another I/O pin is responsible for handling clock and reset. Operation will run as follows:
In this manner we should be able to implement external peripherals like UARTs, timers, and GPIOs. The external controller can be a microcontroller, FPGA, or the caravel harness SoC.