| Tim Edwards | 55f4d0e | 2020-07-05 15:41:02 -0400 | [diff] [blame] | 1 | # TECHNAME.par --- Parameter file for GrayWolf |
| 2 | # NOTE: all distance units are in centimicrons unless otherwise stated |
| 3 | # WARNING: this is NOT tcl syntax! No Comments on end of actual data line. |
| 4 | # The vast majority of quantities here are not used (read instead from techLEF, etc.) |
| 5 | |
| 6 | RULES |
| 7 | # values are resistance in ohms/sq and capacitance in fF/um^2 |
| 8 | # TODO: properly pick directions |
| 9 | layer metal1 0.105 0.0001 horizontal |
| 10 | layer metal2 0.105 0.0001 vertical |
| 11 | layer metal3 0.105 0.0001 horizontal |
| 12 | #ifdef METAL5 |
| 13 | layer metal4 0.105 0.0001 vertical |
| 14 | layer metal5 0.105 0.0001 horizontal |
| 15 | #endif |
| 16 | |
| 17 | via via12 metal1 metal2 |
| 18 | via via23 metal2 metal3 |
| 19 | #ifdef METAL5 |
| 20 | via via34 metal3 metal4 |
| 21 | via via45 metal4 metal5 |
| 22 | #endif |
| 23 | |
| 24 | # 0.5 um |
| 25 | width metal1 50 |
| 26 | width metal2 60 |
| 27 | # 0.6 um |
| 28 | width metal3 60 |
| 29 | #ifdef METAL5 |
| 30 | width metal4 60 |
| 31 | width metal5 60 |
| 32 | #endif |
| 33 | |
| 34 | # TODO verify these two numbers |
| 35 | width via12 50 |
| 36 | width via23 50 |
| 37 | #ifdef METAL5 |
| 38 | width via34 50 |
| 39 | width via45 50 |
| 40 | #endif |
| 41 | |
| 42 | # Set spacing = track pitch - width, so that GrayWolf places pins |
| 43 | # on the right pitch. |
| 44 | # Pitches are (in um): |
| 45 | # metal1 = 200, metal2 = 160, metal3 = 200, metal4 = 320 |
| 46 | ## pitch m1: 1.3um m2: 1.4um m3: 1.3um |
| 47 | ## width m1: 0.5um m2: 0.6um m3: 0.6um |
| 48 | ## space 0.8 0.8 0.7 (pitch calc) |
| 49 | ## fab-space 0.45 0.5 0.6 |
| 50 | |
| 51 | spacing metal1 metal1 80 |
| 52 | spacing metal2 metal2 80 |
| 53 | spacing metal3 metal3 80 |
| 54 | #ifdef METAL5 |
| 55 | spacing metal4 metal4 80 |
| 56 | spacing metal5 metal5 80 |
| 57 | #endif |
| 58 | |
| 59 | # (WAS:) Stacked vias allowed |
| 60 | # spacing via12 via23 0 |
| 61 | |
| 62 | # To disable Stacked?: give non-zero spacing (centimicrons = 10 nanometer = 1/100 of micron) |
| 63 | # TODO need real value here: |
| 64 | spacing via12 via23 0 |
| 65 | #ifdef METAL5 |
| 66 | spacing via23 via34 0 |
| 67 | spacing via34 via45 0 |
| 68 | #endif |
| 69 | |
| 70 | # .2um .15um |
| 71 | overhang via12 metal1 20 |
| 72 | overhang via12 metal2 15 |
| 73 | |
| 74 | overhang via23 metal2 20 |
| 75 | overhang via23 metal3 15 |
| 76 | |
| 77 | #ifdef METAL5 |
| 78 | overhang via34 metal3 14 |
| 79 | overhang via34 metal4 16 |
| 80 | overhang via45 metal4 14 |
| 81 | overhang via45 metal5 16 |
| 82 | #endif |
| 83 | ENDRULES |
| 84 | |
| 85 | *vertical_wire_weight : 1.0 |
| 86 | *vertical_path_weight : 1.0 |
| 87 | *padspacing : variable |
| 88 | *rowSep : 0.0 0 |
| 89 | # min pitch of m1,m2,m3 (FIXME): |
| 90 | *track.pitch : 130 |
| 91 | *graphics.wait : off |
| 92 | *last_chance.wait : off |
| 93 | *random.seed : 12345 |
| 94 | # TODO: proper track.pitch number above, plus feedThruWidth below |
| 95 | |
| 96 | TWMC*chip.aspect.ratio : 1.0 |
| 97 | |
| 98 | # FIXME: Change width to width of minimum fill cell |
| 99 | TWSC*feedThruWidth : 280 layer 1 |
| 100 | TWSC*do.global.route : on |
| 101 | TWSC*ignore_feeds : true |
| 102 | TWSC*call_row_evener : true |
| 103 | TWSC*even_rows_maximally : true |
| 104 | # TWSC*no.graphics : on |
| 105 | |
| 106 | GENR*row_to_tile_spacing: 1 |
| 107 | # GENR*numrows : 6 |
| 108 | GENR*flip_alternate_rows : 1 |
