| Tim Edwards | 367711e | 2021-01-27 10:35:12 -0500 | [diff] [blame] | 1 | * |
| 2 | * spice test file for generating .prm files. |
| 3 | * |
| 4 | .lib /home/tim/projects/efabless/tech/XFAB/EFXH018D/libs.tech/models/lpmos/param.lib 3s |
| 5 | .lib /home/tim/projects/efabless/tech/XFAB/EFXH018D/libs.tech/models/lpmos/xh018.lib tm |
| 6 | * |
| 7 | .option TEMP=27 |
| 8 | * |
| 9 | * out1 - Output of Inverter to measure step response. |
| 10 | * |
| 11 | X0 out1 in1 GND GND ne L=0.18u W=0.8u |
| 12 | X1 out1 in1 VDD VDD pe L=0.18u W=1.0u |
| 13 | * |
| 14 | * out2 - Output of Inverter driven by out1 to determine slow-input effect. |
| 15 | * |
| 16 | X6 out2 out1 GND GND ne L=0.18u W=0.8u |
| 17 | X7 out2 out1 VDD VDD pe L=0.18u W=1.0u |
| 18 | * |
| 19 | * out3 - Output of a ne pulling up to determine dynamic-high resistance. |
| 20 | * |
| 21 | X2 out3 in2 VDD GND ne L=0.18u W=0.8u |
| 22 | * |
| 23 | * out4 - Output of a pe pulling down to determine dynamic-low resistance. |
| 24 | * |
| 25 | X3 out4 in3 GND VDD pe L=0.18u W=1.0u |
| 26 | * |
| 27 | * loading capacitors |
| 28 | * |
| 29 | C0 out1 GND 50f |
| 30 | C1 out2 GND 50f |
| 31 | C2 out3 GND 50f |
| 32 | C3 out4 GND 50f |
| 33 | |
| 34 | VDD VDD 0 DC 1.62 |
| 35 | * VGnd GND 0 DC 0 |
| 36 | RGnd GND 0 0.01 |
| 37 | Vmid mid 0 DC 0.9 |
| 38 | |
| 39 | Vin1 in1 0 0 pwl (0ns 0 0.1ns 1.62 40ns 1.62 40.1ns 0) |
| 40 | Vin2 in2 0 0 pwl (0ns 0 0.1ns 1.62) |
| 41 | Vin3 in3 0 5 pwl (0ns 1.62 0.1ns 0) |
| 42 | |
| 43 | .ic V(out4)=1.62 |
| 44 | |
| 45 | .tran 0.01ns 80ns |
| 46 | |
| 47 | .save all |
| 48 | |
| 49 | .end |
