Modified the liberty and verilog filters for gf180mcu to prevent
the filltie and endcap cells from being given the well and substrate
pins.
diff --git a/gf180mcu/custom/scripts/fix_related_bias_pins.py b/gf180mcu/custom/scripts/fix_related_bias_pins.py
index 5576eb1..19b4c05 100755
--- a/gf180mcu/custom/scripts/fix_related_bias_pins.py
+++ b/gf180mcu/custom/scripts/fix_related_bias_pins.py
@@ -24,6 +24,9 @@
print('fix_related_bias_pins.py: failed to open ' + inname + ' for reading.', file=sys.stderr)
return 1
+ if 'filltie' in inname or 'endcap' in inname:
+ return 0
+
# Process input with regexp
fixedlines = []
diff --git a/gf180mcu/custom/scripts/inc_verilog.py b/gf180mcu/custom/scripts/inc_verilog.py
index 2472a02..b13eda4 100755
--- a/gf180mcu/custom/scripts/inc_verilog.py
+++ b/gf180mcu/custom/scripts/inc_verilog.py
@@ -50,8 +50,11 @@
modified = True
else:
# Add in substrate and well pins
- fline = line.replace('VDD, VSS', 'VDD, VSS, VNW, VPW')
- fline = fline.replace('.VDD(VDD),.VSS(VSS)', '.VDD(VDD),.VSS(VSS),.VNW(VNW),.VPW(VPW)')
+ if 'filltie' in inname or 'endcap' in inname:
+ fline = line
+ else:
+ fline = line.replace('VDD, VSS', 'VDD, VSS, VNW, VPW')
+ fline = fline.replace('.VDD(VDD),.VSS(VSS)', '.VDD(VDD),.VSS(VSS),.VNW(VNW),.VPW(VPW)')
if fline != line:
modified = True
fixedlines.append(fline)
