Modifed the technology LEF-fixing script to add in via resistances
and fix the one incorrect layer resistance. Created a new script
to generate minimum and maximum corner versions of the nominal
technology LEF file. Fixed swapped area vs. perimeter capacitances
for metal5 in magic. Updated the Makefile and the openlane config
script to work with the modified names for the technology LEF and
the OpenRCX information files.
diff --git a/VERSION b/VERSION
index 3c89422..5c037ec 100644
--- a/VERSION
+++ b/VERSION
@@ -1 +1 @@
-1.0.292
+1.0.293
diff --git a/sky130/Makefile.in b/sky130/Makefile.in
index 8d25736..3a49b01 100644
--- a/sky130/Makefile.in
+++ b/sky130/Makefile.in
@@ -1219,6 +1219,7 @@
# Install all SkyWater digital standard cells.
${STAGE} -source ${SKYWATER_LIBS_PATH} -target ${STAGING_PATH}/${SKY130$*} \
-techlef %l/latest/tech/*.tlef filter=custom/scripts/fix_techlef$*.py \
+ rename=sky130_fd_sc_hd__nom.tlef \
-spice %l/latest/cells/*/*.spice compile-only \
sort=../common/sort_pdkfiles.py \
filter=custom/scripts/fix_device_models.py \
@@ -1247,6 +1248,9 @@
compile-only filter=custom/scripts/inc_verilog.py \
sort=../common/sort_pdkfiles.py \
-library digital sky130_fd_sc_hd 2>&1 | tee -a ${SKY130$*}_make.log
+ # Create minimum/maximum technology LEF files
+ ./custom/scripts/make_minmax_techlef.py ${EF_FORMAT} -variant=${SKY130$*} \
+ -library=hd 2>&1 | tee -a ${SKY130$*}_make.log || true
# Add a maskhint set for the tap cell .mag view to prevent problems writing
# when writing NSDM and PSDM to GDS during hierarchical adjustments.
${ADDPROP} ${STAGING_PATH}/${SKY130$*} sky130_fd_sc_hd \
@@ -1274,6 +1278,7 @@
# Install all SkyWater digital standard cells.
${STAGE} -source ${SKYWATER_LIBS_PATH} -target ${STAGING_PATH}/${SKY130$*} \
-techlef %l/latest/tech/*.tlef filter=custom/scripts/fix_techlef$*.py \
+ rename=sky130_fd_sc_hdll__nom.tlef \
-spice %l/latest/cells/*/*.spice compile-only \
sort=../common/sort_pdkfiles.py \
filter=custom/scripts/fix_device_models.py \
@@ -1296,6 +1301,9 @@
compile-only filter=custom/scripts/inc_verilog.py \
sort=../common/sort_pdkfiles.py \
-library digital sky130_fd_sc_hdll 2>&1 | tee -a ${SKY130$*}_make.log
+ # Create minimum/maximum technology LEF files
+ ./custom/scripts/make_minmax_techlef.py ${EF_FORMAT} -variant=${SKY130$*} \
+ -library=hdll 2>&1 | tee -a ${SKY130$*}_make.log || true
# Remove the base verilog files which have already been included into
# the libraries
${RM} ${STAGING_PATH}/${SKY130$*}/libs.ref/${HDLL_VERILOG}/*.*.v
@@ -1313,6 +1321,7 @@
# Install all SkyWater digital standard cells.
${STAGE} -source ${SKYWATER_LIBS_PATH} -target ${STAGING_PATH}/${SKY130$*} \
-techlef %l/latest/tech/*.tlef filter=custom/scripts/fix_techlef$*.py \
+ rename=sky130_fd_sc_hvl__nom.tlef \
-spice %l/latest/cells/*/*.spice compile-only \
no-copy=custom/sky130_fd_sc_hvl/spice/sky130_fd*.spice \
sort=../common/sort_pdkfiles.py \
@@ -1336,6 +1345,9 @@
compile-only filter=custom/scripts/inc_verilog.py \
sort=../common/sort_pdkfiles.py \
-library digital sky130_fd_sc_hvl 2>&1 | tee -a ${SKY130$*}_make.log
+ # Create minimum/maximum technology LEF files
+ ./custom/scripts/make_minmax_techlef.py ${EF_FORMAT} -variant=${SKY130$*} \
+ -library=hvl 2>&1 | tee -a ${SKY130$*}_make.log || true
# Add a maskhint to the HVL level shifter to represent the HVI layer as
# drawn in the GDS, and so eliminate the HVI-to-nwell DRC error.
${ADDPROP} ${STAGING_PATH}/${SKY130$*} sky130_fd_sc_hvl sky130_fd_sc_hvl__lsbufhv2lv_1 \
@@ -1355,6 +1367,7 @@
# Install all SkyWater digital standard cells.
${STAGE} -source ${SKYWATER_LIBS_PATH} -target ${STAGING_PATH}/${SKY130$*} \
-techlef %l/latest/tech/*.tlef filter=custom/scripts/fix_techlef$*.py \
+ rename=sky130_fd_sc_lp__nom.tlef \
-spice %l/latest/cells/*/*.spice compile-only \
sort=../common/sort_pdkfiles.py \
filter=custom/scripts/fix_device_models.py \
@@ -1377,6 +1390,9 @@
compile-only filter=custom/scripts/inc_verilog.py \
sort=../common/sort_pdkfiles.py \
-library digital sky130_fd_sc_lp 2>&1 | tee -a ${SKY130$*}_make.log
+ # Create minimum/maximum technology LEF files
+ ./custom/scripts/make_minmax_techlef.py ${EF_FORMAT} -variant=${SKY130$*} \
+ -library=lp 2>&1 | tee -a ${SKY130$*}_make.log || true
# Remove the base verilog files which have already been included into
# the libraries
${RM} ${STAGING_PATH}/${SKY130$*}/libs.ref/${LP_VERILOG}/*.*.v
@@ -1389,6 +1405,7 @@
# Install all SkyWater digital standard cells.
${STAGE} -source ${SKYWATER_LIBS_PATH} -target ${STAGING_PATH}/${SKY130$*} \
-techlef %l/latest/tech/*.tlef filter=custom/scripts/fix_techlef$*.py \
+ rename=sky130_fd_sc_hs__nom.tlef \
-spice %l/latest/cells/*/*.spice compile-only \
sort=../common/sort_pdkfiles.py \
filter=custom/scripts/fix_device_models.py \
@@ -1412,6 +1429,9 @@
compile-only filter=custom/scripts/inc_verilog.py \
sort=../common/sort_pdkfiles.py \
-library digital sky130_fd_sc_hs 2>&1 | tee -a ${SKY130$*}_make.log
+ # Create minimum/maximum technology LEF files
+ ./custom/scripts/make_minmax_techlef.py ${EF_FORMAT} -variant=${SKY130$*} \
+ -library=hs 2>&1 | tee -a ${SKY130$*}_make.log || true
# Remove the base verilog files which have already been included into
# the libraries
${RM} ${STAGING_PATH}/${SKY130$*}/libs.ref/${HS_VERILOG}/*.*.v
@@ -1420,6 +1440,7 @@
# Install all SkyWater digital standard cells.
${STAGE} -source ${SKYWATER_LIBS_PATH} -target ${STAGING_PATH}/${SKY130$*} \
-techlef %l/latest/tech/*.tlef filter=custom/scripts/fix_techlef$*.py \
+ rename=sky130_fd_sc_ms__nom.tlef \
-spice %l/latest/cells/*/*.spice compile-only \
sort=../common/sort_pdkfiles.py \
filter=custom/scripts/fix_device_models.py \
@@ -1442,6 +1463,9 @@
compile-only filter=custom/scripts/inc_verilog.py \
sort=../common/sort_pdkfiles.py \
-library digital sky130_fd_sc_ms 2>&1 | tee -a ${SKY130$*}_make.log
+ # Create minimum/maximum technology LEF files
+ ./custom/scripts/make_minmax_techlef.py ${EF_FORMAT} -variant=${SKY130$*} \
+ -library=ms 2>&1 | tee -a ${SKY130$*}_make.log || true
# Remove the base verilog files which have already been included into
# the libraries
${RM} ${STAGING_PATH}/${SKY130$*}/libs.ref/${MS_VERILOG}/*.*.v
@@ -1450,6 +1474,7 @@
# Install all SkyWater digital standard cells.
${STAGE} -source ${SKYWATER_LIBS_PATH} -target ${STAGING_PATH}/${SKY130$*} \
-techlef %l/latest/tech/*.tlef filter=custom/scripts/fix_techlef$*.py \
+ rename=sky130_fd_sc_ls__nom.tlef \
-spice %l/latest/cells/*/*.spice compile-only \
sort=../common/sort_pdkfiles.py \
filter=custom/scripts/fix_device_models.py \
@@ -1472,6 +1497,9 @@
compile-only filter=custom/scripts/inc_verilog.py \
sort=../common/sort_pdkfiles.py \
-library digital sky130_fd_sc_ls 2>&1 | tee -a ${SKY130$*}_make.log
+ # Create minimum/maximum technology LEF files
+ ./custom/scripts/make_minmax_techlef.py ${EF_FORMAT} -variant=${SKY130$*} \
+ -library=ls 2>&1 | tee -a ${SKY130$*}_make.log || true
# Remove the base verilog files which have already been included into
# the libraries
${RM} ${STAGING_PATH}/${SKY130$*}/libs.ref/${LS_VERILOG}/*.*.v
diff --git a/sky130/custom/scripts/fix_techlefA.py b/sky130/custom/scripts/fix_techlefA.py
index 76cc12e..fa992d9 100755
--- a/sky130/custom/scripts/fix_techlefA.py
+++ b/sky130/custom/scripts/fix_techlefA.py
@@ -3,7 +3,10 @@
# fix_techlefA ---
#
# This script adds the missing statement "USEMINSPACING OBS OFF" from
-# the technology LEF files for Sky130.
+# the technology LEF files for Sky130, adds missing RESISTANCE
+# values, and corrects the resistance value of local interconnect.
+# Note that resistance values are *nominal* and need to be modified for
+# corners.
#
# This script is a filter to be run by setting the name of this script as
# the value to "filter=" for the model install in the sky130 Makefile for
@@ -24,15 +27,33 @@
print('fix_techlefA.py: failed to open ' + inname + ' for reading.', file=sys.stderr)
return 1
+ # These are the resistance values per via type, by name. Valuse are in
+ # ohms and presented as a string.
+ via_res = {}
+ via_res['mcon'] = '9.30'
+ via_res['via'] = '4.50'
+ via_res['via2'] = '3.41'
+ via_res['via3'] = '3.41'
+ via_res['via4'] = '0.38'
+
# Process input with regexp
fixedlines = []
modified = False
- proprex = re.compile('[ \t]*MANUFACTURINGGRID')
+ proprex = re.compile('[ \t]*MANUFACTURINGGRID')
+ resrex = re.compile('[ \t]*ENCLOSURE ABOVE')
+ layerrex = re.compile('[ \t]*LAYER ([^ \t\n]+)')
+ resrex2 = re.compile('[ \t]*RESISTANCE RPERSQ 12.2 ;')
+ curlayer = None
for line in llines:
- fixedlines.append(line)
+ rmatch = resrex2.match(line)
+ if rmatch:
+ fixedlines.append(' RESISTANCE RPERSQ 12.8 ;')
+ modified = True
+ else:
+ fixedlines.append(line)
# Check for the MANUFACTURINGGRID statement in the file, and
# add the USEMINSPACING statement after it.
@@ -42,6 +63,15 @@
fixedlines.append('USEMINSPACING OBS OFF ;')
modified = True
+ rmatch = resrex.match(line)
+ if rmatch:
+ fixedlines.append(' RESISTANCE ' + via_res[curlayer] + ' ;')
+ modified = True
+
+ lmatch = layerrex.match(line)
+ if lmatch:
+ curlayer = lmatch.group(1)
+
# Write output
if outname == None:
for i in fixedlines:
diff --git a/sky130/custom/scripts/fix_techlefB.py b/sky130/custom/scripts/fix_techlefB.py
index bb18e90..731851d 100755
--- a/sky130/custom/scripts/fix_techlefB.py
+++ b/sky130/custom/scripts/fix_techlefB.py
@@ -3,7 +3,9 @@
# fix_techlefB ---
#
# This script adds the missing statement "USEMINSPACING OBS OFF" from
-# the technology LEF files for Sky130.
+# the technology LEF files for Sky130, adds missing RESISTANCE values,
+# and corrects the resistance value of local interconnect. Note that
+# resistance values are *nominal* and need to be modified for corners.
#
# This script also replaces the plate and fringing capacitance values for
# route layers from metal2 to metal5 based on the ReRAM stackup (sky130B).
@@ -27,6 +29,16 @@
print('fix_techlefB.py: failed to open ' + inname + ' for reading.', file=sys.stderr)
return 1
+ # These are the resistance values per via type, by name. Values are in
+ # ohms and presented as a string.
+
+ via_res = {}
+ via_res['mcon'] = '9.30'
+ via_res['via'] = '9.00'
+ via_res['via2'] = '3.41'
+ via_res['via3'] = '3.41'
+ via_res['via4'] = '0.38'
+
# These edge capacitance values get modified
edgevalues = [['37.759E-6', '32.918E-6'],
['40.989E-6', '37.065E-6'],
@@ -47,6 +59,10 @@
proprex = re.compile('[ \t]*MANUFACTURINGGRID')
edgerex = re.compile('[ \t]*EDGECAPACITANCE')
platerex = re.compile('[ \t]*CAPACITANCE[ \t]+CPERSQDIST')
+ resrex = re.compile('[ \t]*ENCLOSURE ABOVE')
+ layerrex = re.compile('[ \t]*LAYER ([^ \t\n]+)')
+ resrex2 = re.compile('[ \t]*RESISTANCE RPERSQ 12.2 ;')
+ curlayer = None
for line in llines:
@@ -54,13 +70,23 @@
# add the USEMINSPACING statement after it.
pmatch = proprex.match(line)
+ rmatch = resrex.match(line)
+ lmatch = layerrex.match(line)
if pmatch:
fixedlines.append(line)
fixedlines.append('USEMINSPACING OBS OFF ;')
modified = True
+ elif rmatch:
+ fixedlines.append(line)
+ fixedlines.append(' RESISTANCE ' + via_res[curlayer] + ' ;')
+ modified = True
+ elif lmatch:
+ fixedlines.append(line)
+ curlayer = lmatch.group(1)
else:
ematch = edgerex.match(line)
pmatch = platerex.match(line)
+ rmatch = resrex2.match(line)
if ematch:
found = False
for ecap in edgevalues:
@@ -81,6 +107,9 @@
break
if not found:
fixedlines.append(line)
+ elif rmatch:
+ fixedlines.append(' RESISTANCE RPERSQ 12.8 ;')
+ modified = True
else:
fixedlines.append(line)
diff --git a/sky130/custom/scripts/make_minmax_techlef.py b/sky130/custom/scripts/make_minmax_techlef.py
new file mode 100755
index 0000000..4871b5e
--- /dev/null
+++ b/sky130/custom/scripts/make_minmax_techlef.py
@@ -0,0 +1,148 @@
+#!/usr/bin/env python3
+#
+#--------------------------------------------------------------------
+# make_minmax_techlef.py --
+#
+# From a nominal technology LEF file, create the corresponding
+# technology files for the minimum and maximum process corners.
+# Currently this only considers the change in layer and via
+# resistance, not parasitic capacitance.
+#
+# Usage:
+#
+# make_minmax_techlef.py -variant=sky130A|sky130B
+# -library=hd|hs|lp|ls|ms|hdll|hvl
+# [-ef_format]
+#
+# Given the PDK variant and library name, finds the technology
+# LEF file in the staging area with the nominal corner values,
+# and creates two additional technology LEF files for the
+# minimum and maximum corners.
+#--------------------------------------------------------------------
+
+import os
+import re
+import sys
+
+options = []
+arguments = []
+for item in sys.argv[1:]:
+ if item.find('-', 0) == 0:
+ options.append(item[1:])
+ else:
+ arguments.append(item)
+
+variant = 'sky130A'
+lib = 'hd'
+tlefpath = variant + '/libs.ref/sky130_fd_sc_' + lib + '/techlef'
+
+if len(options) > 0:
+ for option in options:
+ if option.startswith('variant'):
+ variant = option.split('=')[1]
+ elif option.startswith('library'):
+ lib = option.split('=')[1]
+ tlefpath = variant + '/libs.ref/sky130_fd_sc_' + lib + '/techlef'
+ for option in options:
+ if option == 'ef_format':
+ tlefpath = variant + '/libs.ref/techLEF/sky130_fd_sc_' + lib
+elif len(arguments) > 0:
+ tlefpath = arguments[0]
+
+tlefbase = 'sky130_fd_sc_' + lib + '__'
+tlefnom = tlefbase + 'nom.tlef'
+
+resrex1 = re.compile('^[ \t]*RESISTANCE RPERSQ')
+resrex2 = re.compile('^[ \t]*RESISTANCE')
+layerrex = re.compile('^[ \t]*LAYER ([^ \t\n]+)')
+
+# Resistance values, by layer
+
+rnom = {}
+rmin = {}
+rmax = {}
+
+# Nominal values are for reference only; they're not used in the code below
+rnom['li1'] = '12.8'
+rnom['mcon'] = '9.3'
+rnom['met1'] = '0.125'
+rnom['via'] = '4.5'
+rnom['met2'] = '0.125'
+rnom['via2'] = '3.41'
+rnom['met3'] = '0.047'
+rnom['via3'] = '3.41'
+rnom['met4'] = '0.047'
+rnom['via4'] = '0.38'
+rnom['met5'] = '0.0285'
+
+rmin['li1'] = '9.2'
+rmin['mcon'] = '1.6'
+rmin['met1'] = '0.105'
+rmin['via'] = '2.0'
+rmin['met2'] = '0.105'
+rmin['via2'] = '0.5'
+rmin['met3'] = '0.038'
+rmin['via3'] = '0.5'
+rmin['met4'] = '0.038'
+rmin['via4'] = '0.012'
+rmin['met5'] = '0.0212'
+
+rmax['li1'] = '17.0'
+rmax['mcon'] = '23.0'
+rmax['met1'] = '0.145'
+rmax['via'] = '15.0'
+rmax['met2'] = '0.145'
+rmax['via2'] = '8.0'
+rmax['met3'] = '0.056'
+rmax['via3'] = '8.0'
+rmax['met4'] = '0.056'
+rmax['via4'] = '0.891'
+rmax['met5'] = '0.0358'
+
+if variant == 'sky130B':
+ rnom['via'] = '9.0'
+ rmin['via'] = '4.0'
+ rmax['via'] = '30.0'
+
+#--------------------------------------------------------------------
+
+infile_name = tlefpath + '/' + tlefnom
+print('Creating minimum and maximum corner variants of ' + infile_name)
+
+if not os.path.exists(infile_name):
+ print('Error: Cannot find file ' + infile_name)
+ sys.exit(1)
+
+for corner in ['min', 'max']:
+ tleffile = tlefbase + corner + '.tlef'
+ outfile_name = tlefpath + '/' + tleffile
+
+ infile = open(infile_name, 'r')
+ outfile = open(outfile_name, 'w')
+ curlayer = None
+ value = None
+
+ for line in infile:
+ rmatch1 = resrex1.match(line)
+ rmatch2 = resrex2.match(line)
+ lmatch = layerrex.match(line)
+ if lmatch:
+ curlayer = lmatch.group(1)
+ if curlayer in rnom:
+ if corner == 'min':
+ value = rmin[curlayer]
+ else:
+ value = rmax[curlayer]
+ else:
+ value = None
+ outfile.write(line)
+ elif value and rmatch1:
+ outfile.write(' RESISTANCE RPERSQ ' + value + ' ;\n')
+ elif value and rmatch2:
+ outfile.write(' RESISTANCE ' + value + ' ;\n')
+ else:
+ outfile.write(line)
+
+ infile.close()
+ outfile.close()
+
diff --git a/sky130/magic/sky130.tech b/sky130/magic/sky130.tech
index f34aad5..31c0835 100644
--- a/sky130/magic/sky130.tech
+++ b/sky130/magic/sky130.tech
@@ -5654,8 +5654,8 @@
defaultsidewall allm5 metal5 127.06
#ifdef RERAM
defaultareacap allm5 metal5 5.99
- defaultperimeter allm5 metal5 5.99
- defaultoverlap allm5 metal5 nwell,pwell well 36.83
+ defaultperimeter allm5 metal5 36.83
+ defaultoverlap allm5 metal5 nwell,pwell well 5.99
defaultsideoverlap allm5 metal5 nwell,pwell well 36.83
#metal5->diff
diff --git a/sky130/openlane/config.tcl b/sky130/openlane/config.tcl
index 2500198..8b4ead5 100755
--- a/sky130/openlane/config.tcl
+++ b/sky130/openlane/config.tcl
@@ -13,7 +13,9 @@
# Technology LEF
#ifdef EF_FORMAT
-set ::env(TECH_LEF) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/techLEF/$::env(STD_CELL_LIBRARY)/$::env(STD_CELL_LIBRARY).tlef"
+set ::env(TECH_LEF) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/techLEF/$::env(STD_CELL_LIBRARY)/$::env(STD_CELL_LIBRARY)__nom.tlef"
+set ::env(TECH_LEF_MIN) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/techLEF/$::env(STD_CELL_LIBRARY)/$::env(STD_CELL_LIBRARY)__min.tlef"
+set ::env(TECH_LEF_MAX) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/techLEF/$::env(STD_CELL_LIBRARY)/$::env(STD_CELL_LIBRARY)__max.tlef"
set ::env(CELLS_LEF) [glob "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/lef/$::env(STD_CELL_LIBRARY)/*.lef"]
set ::env(GDS_FILES) [glob "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/gds/$::env(STD_CELL_LIBRARY)/*.gds"]
set ::env(STD_CELL_LIBRARY_CDL) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/cdl/$::env(STD_CELL_LIBRARY)/$::env(STD_CELL_LIBRARY).cdl"
@@ -124,7 +126,9 @@
set ::env(DRC_EXCLUDE_CELL_LIST_OPT) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/openlane/$::env(STD_CELL_LIBRARY_OPT)/drc_exclude.cells"
# Open-RCX Rules File
-set ::env(RCX_RULES) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/openlane/rcx_rules.info"
+set ::env(RCX_RULES) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/openlane/rules.openrcx.$::env(PDK).nom.magic"
+set ::env(RCX_RULES_MIN) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/openlane/rules.openrcx.$::env(PDK).min.magic"
+set ::env(RCX_RULES_MAX) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/openlane/rules.openrcx.$::env(PDK).max.magic"
# VIAS RC Values
set ::env(VIAS_RC) "\
@@ -179,4 +183,4 @@
set ::env(GLB_RT_LAYER_ADJUSTMENTS) "0.99,0,0,0,0,0"
set ::env(RT_MIN_LAYER) "met1"
-set ::env(RT_MAX_LAYER) "met5"
\ No newline at end of file
+set ::env(RT_MAX_LAYER) "met5"
