Updated foundry_install to change the recent "hide" option addition to a more
general-purpose "lefopts" for passing "lef write" options to magic. With this,
and with an update of magic, new LEF views of all standard cells are now generated
that are all consistent and do not depend on the SkyWater LEF sources except for
annotation. LEF views of selected I/O cells were edited to remove DRC errors and
for the bus filler cells, to remove the obstruction layer from the area typically
used to drop additional cells into the padframe.
diff --git a/VERSION b/VERSION
index b0f2ad9..acbf873 100644
--- a/VERSION
+++ b/VERSION
@@ -1 +1 @@
-1.0.237
+1.0.238
diff --git a/common/foundry_install.py b/common/foundry_install.py
index 6328491..a755074 100755
--- a/common/foundry_install.py
+++ b/common/foundry_install.py
@@ -144,6 +144,10 @@
# the LEF files should not be used and LEF should be
# generated from layout.
#
+# lefopts: Followed by "=" and a comma-separated list of option
+# strings. If LEF views are generated from magic, use the
+# options specified.
+#
# noconvert: Install only; do not attempt to convert to other
# formats (applies only to GDS, CDL, and LEF).
#
@@ -1063,7 +1067,8 @@
# then compile one, because one does not want to have to have
# an include line for every single cell used in a design.
- create_lef_library(destlibdir, compname, do_compile_only, excludelist)
+ if not have_lefanno:
+ create_lef_library(destlibdir, compname, do_compile_only, excludelist)
if do_compile_only == True:
if newname and targname:
@@ -1150,6 +1155,7 @@
cdl_compile_only = False
lef_compile = False
lef_compile_only = False
+ lefopts = None
cdl_exclude = []
lef_exclude = []
@@ -1224,6 +1230,12 @@
spice_exclude = exclude_list
elif option[0] == 'verilog':
verilog_exclude = exclude_list
+
+ # Find options list for "lef write"
+ for item in option:
+ if item.split('=')[0] == 'lefopts':
+ if option[0] == 'lef':
+ lefopts = item.split('=')[1].strip('"')
devlist = []
pdklibrary = None
@@ -1439,10 +1451,7 @@
leffiles = []
lefmacros = []
- if have_lef:
- # Nothing to do; LEF macros were already installed.
- pass
- elif have_lefanno:
+ if have_lefanno:
# Find LEF file names in the source
if ef_format:
lefsrcdir = targetdir + lef_reflib + 'lef'
@@ -1478,7 +1487,9 @@
ltok = re.split(' |\t|\(', lline)
if ltok[0] == 'MACRO':
lefmacros.append(ltok[1])
-
+ elif have_lef:
+ # Nothing to do; LEF macros were already installed.
+ pass
elif have_verilog and os.path.isdir(vlibdir):
# Get list of abstract views to make from verilog modules
# (NOTE: no way to apply exclude list here!)
@@ -1573,7 +1584,7 @@
if not lefmacros:
print('No source for abstract views: Abstract views not made.')
- elif not have_lef:
+ elif have_lefanno or not have_lef:
# This library has a GDS database but no LEF database. Use
# magic to create abstract views of the GDS cells. If
# option "annotate" is given, then read the LEF file after
@@ -1595,7 +1606,10 @@
for lefmacro in lefmacros:
print('if {[cellname list exists ' + lefmacro + '] != 0} {', file=ofile)
print(' load ' + lefmacro, file=ofile)
- print(' lef write ' + lefdest + lefmacro + ' -hide', file=ofile)
+ if lefopts:
+ print(' lef write ' + lefdest + lefmacro + ' ' + lefopts, file=ofile)
+ else:
+ print(' lef write ' + lefdest + lefmacro, file=ofile)
print('}', file=ofile)
print('puts stdout "Done."', file=ofile)
diff --git a/sky130/Makefile.in b/sky130/Makefile.in
index 104364b..627a6b0 100644
--- a/sky130/Makefile.in
+++ b/sky130/Makefile.in
@@ -1002,19 +1002,22 @@
io-a:
# Install custom additions to I/O pad library
${STAGE} -source ./custom -target ${STAGING_PATH}/${SKY130A} \
- -verilog %l/verilog/*.v \
+ -verilog %l/verilog/*.v compile-only rename=sky130_ef_io \
-cdl %l/cdl/*.cdl \
-spice %l/spice/*.spice \
-gds %l/gds/*.gds options=custom/scripts/gds_import_setup.tcl \
- -lef %l/lef/*.lef compile-only rename=sky130_ef_io \
+ -lef %l/lef/*.lef exclude=sky130_fd_io__top_xres4v2.lef \
+ compile-only rename=sky130_ef_io \
+ -lef %l/lef/sky130_fd_io__top_xres4v2.lef \
-library general sky130_fd_io 2>&1 | tee -a ${SKY130A}_make.log
# Install SkyWater I/O pad library
${STAGE} -source ${SKYWATER_LIBS_PATH} -target ${STAGING_PATH}/${SKY130A} \
-cdl %l/latest/cells/*/*.cdl ignore=topography compile-only \
include=custom/sky130_fd_io/cdl/*.cdl \
sort=../common/sort_pdkfiles.py \
- -lef %l/latest/cells/*/*.lef annotate compile-only \
- include=custom/sky130_fd_io/lef/*.lef \
+ -lef %l/latest/cells/*/*.lef annotate lefopts=-hide compile-only \
+ no-copy=sky130_fd_io__top_xres4v2.lef \
+ include=sky130_fd_io__top_xres4v2.lef \
exclude=*.magic.lef,sky130_ef_io.lef \
sort=../common/sort_pdkfiles.py \
-doc %l/latest/cells/*/*.pdf \
@@ -1022,9 +1025,7 @@
-gds %l/latest/cells/*/*.gds compile-only \
sort=../common/sort_pdkfiles.py \
options=custom/scripts/sky130_fd_io_import.tcl \
- -verilog %l/latest/cells/*/*.*.v \
- -verilog %l/latest/cells/*/*.v exclude=*.*.v \
- include=custom/sky130_fd_io/verilog/*.v \
+ -verilog %l/latest/cells/*/*.v exclude=*.*.v,sky130_ef_io.v \
compile-only filter=custom/scripts/inc_verilog.py \
sort=../common/sort_pdkfiles.py \
-library general sky130_fd_io 2>&1 | tee -a ${SKY130A}_make.log
@@ -1051,9 +1052,10 @@
filter=custom/scripts/fix_device_models.py \
-cdl %l/latest/cells/*/*.cdl ignore=topography compile-only \
sort=../common/sort_pdkfiles.py \
- -lef %l/latest/cells/*/*.magic.lef \
+ -lef %l/latest/cells/*/*.lef \
+ exclude=*.magic.lef lefopts=-toplayer \
include=custom/sky130_fd_sc_hd/lef/sky130_ef*.lef \
- compile-only \
+ annotate compile-only \
sort=../common/sort_pdkfiles.py \
-doc %l/latest/cells/*/*.pdf \
-lib %l/latest/timing/*.lib filter=custom/scripts/add_wireloads.py \
@@ -1098,7 +1100,8 @@
filter=custom/scripts/fix_device_models.py \
-cdl %l/latest/cells/*/*.cdl ignore=topography compile-only \
sort=../common/sort_pdkfiles.py \
- -lef %l/latest/cells/*/*.magic.lef compile-only \
+ -lef %l/latest/cells/*/*.lef annotate compile-only \
+ exclude=*.magic.lef lefopts=-toplayer \
sort=../common/sort_pdkfiles.py \
-doc %l/latest/cells/*/*.pdf \
-lib %l/latest/timing/*.lib custom/scripts/add_wireloads.py \
@@ -1134,7 +1137,8 @@
filter=custom/scripts/fix_device_models.py \
-cdl %l/latest/cells/*/*.cdl ignore=topography compile-only \
sort=../common/sort_pdkfiles.py \
- -lef %l/latest/cells/*/*.magic.lef compile-only \
+ -lef %l/latest/cells/*/*.lef annotate compile-only \
+ exclude=*.magic.lef lefopts=-toplayer \
sort=../common/sort_pdkfiles.py \
-doc %l/latest/cells/*/*.pdf \
-lib %l/latest/timing/*.lib custom/scripts/add_wireloads.py \
@@ -1174,7 +1178,8 @@
filter=custom/scripts/fix_device_models.py \
-cdl %l/latest/cells/*/*.cdl ignore=topography compile-only \
sort=../common/sort_pdkfiles.py \
- -lef %l/latest/cells/*/*.magic.lef compile-only \
+ -lef %l/latest/cells/*/*.lef annotate compile-only \
+ exclude=*.magic.lef lefopts=-toplayer \
sort=../common/sort_pdkfiles.py \
-doc %l/latest/cells/*/*.pdf \
-lib %l/latest/timing/*.lib custom/scripts/add_wireloads.py \
@@ -1206,7 +1211,8 @@
filter=custom/scripts/fix_device_models.py \
-cdl %l/latest/cells/*/*.cdl ignore=topography compile-only \
sort=../common/sort_pdkfiles.py \
- -lef %l/latest/cells/*/*.magic.lef compile-only \
+ -lef %l/latest/cells/*/*.lef annotate compile-only \
+ exclude=*.magic.lef lefopts=-toplayer \
sort=../common/sort_pdkfiles.py \
-doc %l/latest/cells/*/*.pdf \
-lib %l/latest/timing/*.lib custom/scripts/add_wireloads.py \
@@ -1235,7 +1241,8 @@
filter=custom/scripts/fix_device_models.py \
-cdl %l/latest/cells/*/*.cdl ignore=topography compile-only \
sort=../common/sort_pdkfiles.py \
- -lef %l/latest/cells/*/*.magic.lef compile-only \
+ -lef %l/latest/cells/*/*.lef annotate compile-only \
+ exclude=*.magic.lef lefopts=-toplayer \
sort=../common/sort_pdkfiles.py \
-doc %l/latest/cells/*/*.pdf \
-lib %l/latest/timing/*.lib custom/scripts/add_wireloads.py \
@@ -1263,7 +1270,8 @@
filter=custom/scripts/fix_device_models.py \
-cdl %l/latest/cells/*/*.cdl ignore=topography compile-only \
sort=../common/sort_pdkfiles.py \
- -lef %l/latest/cells/*/*.magic.lef compile-only \
+ -lef %l/latest/cells/*/*.lef annotate compile-only \
+ exclude=*.magic.lef lefopts=-toplayer \
sort=../common/sort_pdkfiles.py \
-doc %l/latest/cells/*/*.pdf \
-lib %l/latest/timing/*.lib custom/scripts/add_wireloads.py \
diff --git a/sky130/custom/sky130_fd_io/lef/sky130_ef_io__com_bus_slice_10um.lef b/sky130/custom/sky130_fd_io/lef/sky130_ef_io__com_bus_slice_10um.lef
index 4948ee1..3d0f2a3 100644
--- a/sky130/custom/sky130_fd_io/lef/sky130_ef_io__com_bus_slice_10um.lef
+++ b/sky130/custom/sky130_fd_io/lef/sky130_ef_io__com_bus_slice_10um.lef
@@ -14,10 +14,6 @@
LAYER met4 ;
RECT 0.000 51.090 10.000 54.070 ;
END
- PORT
- LAYER met4 ;
- RECT 9.000 51.090 10.000 54.070 ;
- END
END AMUXBUS_A
PIN AMUXBUS_B
DIRECTION INOUT ;
@@ -26,10 +22,6 @@
LAYER met4 ;
RECT 0.000 46.330 10.000 49.310 ;
END
- PORT
- LAYER met4 ;
- RECT 9.000 46.330 10.000 49.310 ;
- END
END AMUXBUS_B
PIN VSSA
DIRECTION INOUT ;
@@ -54,26 +46,6 @@
LAYER met4 ;
RECT 0.000 34.700 10.000 38.150 ;
END
- PORT
- LAYER met5 ;
- RECT 9.000 45.700 10.000 54.700 ;
- END
- PORT
- LAYER met4 ;
- RECT 9.000 54.370 10.000 54.700 ;
- END
- PORT
- LAYER met4 ;
- RECT 9.000 45.700 10.000 46.030 ;
- END
- PORT
- LAYER met5 ;
- RECT 9.000 34.800 10.000 38.050 ;
- END
- PORT
- LAYER met4 ;
- RECT 9.000 34.700 10.000 38.150 ;
- END
END VSSA
PIN VDDA
DIRECTION INOUT ;
@@ -86,14 +58,6 @@
LAYER met4 ;
RECT 0.000 12.900 10.000 16.350 ;
END
- PORT
- LAYER met5 ;
- RECT 9.000 13.000 10.000 16.250 ;
- END
- PORT
- LAYER met4 ;
- RECT 9.000 12.900 10.000 16.350 ;
- END
END VDDA
PIN VSWITCH
DIRECTION INOUT ;
@@ -106,14 +70,6 @@
LAYER met4 ;
RECT 0.000 29.850 10.000 33.300 ;
END
- PORT
- LAYER met5 ;
- RECT 9.000 29.950 10.000 33.200 ;
- END
- PORT
- LAYER met4 ;
- RECT 9.000 29.850 10.000 33.300 ;
- END
END VSWITCH
PIN VDDIO_Q
DIRECTION INOUT ;
@@ -126,14 +82,6 @@
LAYER met4 ;
RECT 0.000 62.050 10.000 66.500 ;
END
- PORT
- LAYER met5 ;
- RECT 9.000 62.150 10.000 66.400 ;
- END
- PORT
- LAYER met4 ;
- RECT 9.000 62.050 10.000 66.500 ;
- END
END VDDIO_Q
PIN VCCHIB
DIRECTION INOUT ;
@@ -146,14 +94,6 @@
LAYER met4 ;
RECT 0.000 0.000 10.000 5.450 ;
END
- PORT
- LAYER met5 ;
- RECT 9.000 0.100 10.000 5.350 ;
- END
- PORT
- LAYER met4 ;
- RECT 9.000 0.000 10.000 5.450 ;
- END
END VCCHIB
PIN VDDIO
DIRECTION INOUT ;
@@ -174,22 +114,6 @@
LAYER met4 ;
RECT 0.000 17.750 10.000 22.400 ;
END
- PORT
- LAYER met5 ;
- RECT 9.000 68.000 10.000 92.950 ;
- END
- PORT
- LAYER met4 ;
- RECT 9.000 68.000 10.000 92.965 ;
- END
- PORT
- LAYER met5 ;
- RECT 9.000 17.850 10.000 22.300 ;
- END
- PORT
- LAYER met4 ;
- RECT 9.000 17.750 10.000 22.400 ;
- END
END VDDIO
PIN VCCD
DIRECTION INOUT ;
@@ -202,14 +126,6 @@
LAYER met4 ;
RECT 0.000 6.850 10.000 11.500 ;
END
- PORT
- LAYER met5 ;
- RECT 9.000 6.950 10.000 11.400 ;
- END
- PORT
- LAYER met4 ;
- RECT 9.000 6.850 10.000 11.500 ;
- END
END VCCD
PIN VSSIO
DIRECTION INOUT ;
@@ -226,18 +142,6 @@
LAYER met5 ;
RECT 0.000 173.750 10.000 197.965 ;
END
- PORT
- LAYER met5 ;
- RECT 9.000 23.900 10.000 28.350 ;
- END
- PORT
- LAYER met4 ;
- RECT 9.000 23.800 10.000 28.450 ;
- END
- PORT
- LAYER met5 ;
- RECT 9.000 173.750 10.000 197.965 ;
- END
END VSSIO
PIN VSSD
DIRECTION INOUT ;
@@ -250,14 +154,6 @@
LAYER met4 ;
RECT 0.000 39.550 10.000 44.200 ;
END
- PORT
- LAYER met5 ;
- RECT 9.000 39.650 10.000 44.100 ;
- END
- PORT
- LAYER met4 ;
- RECT 9.000 39.550 10.000 44.200 ;
- END
END VSSD
PIN VSSIO_Q
DIRECTION INOUT ;
@@ -270,18 +166,10 @@
LAYER met4 ;
RECT 0.000 56.200 10.000 60.650 ;
END
- PORT
- LAYER met5 ;
- RECT 9.000 56.300 10.000 60.550 ;
- END
- PORT
- LAYER met4 ;
- RECT 9.000 56.200 10.000 60.650 ;
- END
END VSSIO_Q
OBS
LAYER met4 ;
- RECT 0.000 93.365 10.000 197.965 ;
+ RECT 0.000 173.75 10.000 197.965 ;
RECT 0.000 66.900 10.000 67.600 ;
RECT 0.000 61.050 10.000 61.650 ;
RECT 0.000 55.100 10.000 55.800 ;
diff --git a/sky130/custom/sky130_fd_io/lef/sky130_ef_io__com_bus_slice_1um.lef b/sky130/custom/sky130_fd_io/lef/sky130_ef_io__com_bus_slice_1um.lef
index bd34ce3..319d9de 100644
--- a/sky130/custom/sky130_fd_io/lef/sky130_ef_io__com_bus_slice_1um.lef
+++ b/sky130/custom/sky130_fd_io/lef/sky130_ef_io__com_bus_slice_1um.lef
@@ -169,7 +169,7 @@
END VSSIO_Q
OBS
LAYER met4 ;
- RECT 0.000 93.365 1.000 197.965 ;
+ RECT 0.000 173.75 1.000 197.965 ;
RECT 0.000 66.900 1.000 67.600 ;
RECT 0.000 61.050 1.000 61.650 ;
RECT 0.000 55.100 1.000 55.800 ;
diff --git a/sky130/custom/sky130_fd_io/lef/sky130_ef_io__com_bus_slice_20um.lef b/sky130/custom/sky130_fd_io/lef/sky130_ef_io__com_bus_slice_20um.lef
index 2d650a0..c8130ad 100644
--- a/sky130/custom/sky130_fd_io/lef/sky130_ef_io__com_bus_slice_20um.lef
+++ b/sky130/custom/sky130_fd_io/lef/sky130_ef_io__com_bus_slice_20um.lef
@@ -14,10 +14,6 @@
LAYER met4 ;
RECT 0.000 51.090 20.000 54.070 ;
END
- PORT
- LAYER met4 ;
- RECT 19.000 51.090 20.000 54.070 ;
- END
END AMUXBUS_A
PIN AMUXBUS_B
DIRECTION INOUT ;
@@ -26,10 +22,6 @@
LAYER met4 ;
RECT 0.000 46.330 20.000 49.310 ;
END
- PORT
- LAYER met4 ;
- RECT 19.000 46.330 20.000 49.310 ;
- END
END AMUXBUS_B
PIN VSSA
DIRECTION INOUT ;
@@ -54,26 +46,6 @@
LAYER met4 ;
RECT 0.000 34.700 20.000 38.150 ;
END
- PORT
- LAYER met5 ;
- RECT 19.000 45.700 20.000 54.700 ;
- END
- PORT
- LAYER met4 ;
- RECT 19.000 54.370 20.000 54.700 ;
- END
- PORT
- LAYER met4 ;
- RECT 19.000 45.700 20.000 46.030 ;
- END
- PORT
- LAYER met5 ;
- RECT 19.000 34.800 20.000 38.050 ;
- END
- PORT
- LAYER met4 ;
- RECT 19.000 34.700 20.000 38.150 ;
- END
END VSSA
PIN VDDA
DIRECTION INOUT ;
@@ -86,14 +58,6 @@
LAYER met4 ;
RECT 0.000 12.900 20.000 16.350 ;
END
- PORT
- LAYER met5 ;
- RECT 19.000 13.000 20.000 16.250 ;
- END
- PORT
- LAYER met4 ;
- RECT 19.000 12.900 20.000 16.350 ;
- END
END VDDA
PIN VSWITCH
DIRECTION INOUT ;
@@ -106,14 +70,6 @@
LAYER met4 ;
RECT 0.000 29.850 20.000 33.300 ;
END
- PORT
- LAYER met5 ;
- RECT 19.000 29.950 20.000 33.200 ;
- END
- PORT
- LAYER met4 ;
- RECT 19.000 29.850 20.000 33.300 ;
- END
END VSWITCH
PIN VDDIO_Q
DIRECTION INOUT ;
@@ -126,14 +82,6 @@
LAYER met4 ;
RECT 0.000 62.050 20.000 66.500 ;
END
- PORT
- LAYER met5 ;
- RECT 19.000 62.150 20.000 66.400 ;
- END
- PORT
- LAYER met4 ;
- RECT 19.000 62.050 20.000 66.500 ;
- END
END VDDIO_Q
PIN VCCHIB
DIRECTION INOUT ;
@@ -146,14 +94,6 @@
LAYER met4 ;
RECT 0.000 0.000 20.000 5.450 ;
END
- PORT
- LAYER met5 ;
- RECT 19.000 0.100 20.000 5.350 ;
- END
- PORT
- LAYER met4 ;
- RECT 19.000 0.000 20.000 5.450 ;
- END
END VCCHIB
PIN VDDIO
DIRECTION INOUT ;
@@ -174,22 +114,6 @@
LAYER met4 ;
RECT 0.000 17.750 20.000 22.400 ;
END
- PORT
- LAYER met5 ;
- RECT 19.000 68.000 20.000 92.950 ;
- END
- PORT
- LAYER met4 ;
- RECT 19.000 68.000 20.000 92.965 ;
- END
- PORT
- LAYER met5 ;
- RECT 19.000 17.850 20.000 22.300 ;
- END
- PORT
- LAYER met4 ;
- RECT 19.000 17.750 20.000 22.400 ;
- END
END VDDIO
PIN VCCD
DIRECTION INOUT ;
@@ -202,14 +126,6 @@
LAYER met4 ;
RECT 0.000 6.850 20.000 11.500 ;
END
- PORT
- LAYER met5 ;
- RECT 19.000 6.950 20.000 11.400 ;
- END
- PORT
- LAYER met4 ;
- RECT 19.000 6.850 20.000 11.500 ;
- END
END VCCD
PIN VSSIO
DIRECTION INOUT ;
@@ -226,18 +142,6 @@
LAYER met5 ;
RECT 0.000 173.750 20.000 197.965 ;
END
- PORT
- LAYER met5 ;
- RECT 19.000 23.900 20.000 28.350 ;
- END
- PORT
- LAYER met4 ;
- RECT 19.000 23.800 20.000 28.450 ;
- END
- PORT
- LAYER met5 ;
- RECT 19.000 173.750 20.000 197.965 ;
- END
END VSSIO
PIN VSSD
DIRECTION INOUT ;
@@ -250,14 +154,6 @@
LAYER met4 ;
RECT 0.000 39.550 20.000 44.200 ;
END
- PORT
- LAYER met5 ;
- RECT 19.000 39.650 20.000 44.100 ;
- END
- PORT
- LAYER met4 ;
- RECT 19.000 39.550 20.000 44.200 ;
- END
END VSSD
PIN VSSIO_Q
DIRECTION INOUT ;
@@ -270,18 +166,10 @@
LAYER met4 ;
RECT 0.000 56.200 20.000 60.650 ;
END
- PORT
- LAYER met5 ;
- RECT 19.000 56.300 20.000 60.550 ;
- END
- PORT
- LAYER met4 ;
- RECT 19.000 56.200 20.000 60.650 ;
- END
END VSSIO_Q
OBS
LAYER met4 ;
- RECT 0.000 93.365 20.000 197.965 ;
+ RECT 0.000 173.75 20.000 197.965 ;
RECT 0.000 66.900 20.000 67.600 ;
RECT 0.000 61.050 20.000 61.650 ;
RECT 0.000 55.100 20.000 55.800 ;
diff --git a/sky130/custom/sky130_fd_io/lef/sky130_ef_io__com_bus_slice_5um.lef b/sky130/custom/sky130_fd_io/lef/sky130_ef_io__com_bus_slice_5um.lef
index 46f404e..3dd0b49 100644
--- a/sky130/custom/sky130_fd_io/lef/sky130_ef_io__com_bus_slice_5um.lef
+++ b/sky130/custom/sky130_fd_io/lef/sky130_ef_io__com_bus_slice_5um.lef
@@ -14,10 +14,6 @@
LAYER met4 ;
RECT 0.000 51.090 5.000 54.070 ;
END
- PORT
- LAYER met4 ;
- RECT 4.000 51.090 5.000 54.070 ;
- END
END AMUXBUS_A
PIN AMUXBUS_B
DIRECTION INOUT ;
@@ -26,10 +22,6 @@
LAYER met4 ;
RECT 0.000 46.330 5.000 49.310 ;
END
- PORT
- LAYER met4 ;
- RECT 4.000 46.330 5.000 49.310 ;
- END
END AMUXBUS_B
PIN VSSA
DIRECTION INOUT ;
@@ -54,26 +46,6 @@
LAYER met4 ;
RECT 0.000 34.700 5.000 38.150 ;
END
- PORT
- LAYER met5 ;
- RECT 4.000 45.700 5.000 54.700 ;
- END
- PORT
- LAYER met4 ;
- RECT 4.000 54.370 5.000 54.700 ;
- END
- PORT
- LAYER met4 ;
- RECT 4.000 45.700 5.000 46.030 ;
- END
- PORT
- LAYER met5 ;
- RECT 4.000 34.800 5.000 38.050 ;
- END
- PORT
- LAYER met4 ;
- RECT 4.000 34.700 5.000 38.150 ;
- END
END VSSA
PIN VDDA
DIRECTION INOUT ;
@@ -86,14 +58,6 @@
LAYER met4 ;
RECT 0.000 12.900 5.000 16.350 ;
END
- PORT
- LAYER met5 ;
- RECT 4.000 13.000 5.000 16.250 ;
- END
- PORT
- LAYER met4 ;
- RECT 4.000 12.900 5.000 16.350 ;
- END
END VDDA
PIN VSWITCH
DIRECTION INOUT ;
@@ -106,14 +70,6 @@
LAYER met4 ;
RECT 0.000 29.850 5.000 33.300 ;
END
- PORT
- LAYER met5 ;
- RECT 4.000 29.950 5.000 33.200 ;
- END
- PORT
- LAYER met4 ;
- RECT 4.000 29.850 5.000 33.300 ;
- END
END VSWITCH
PIN VDDIO_Q
DIRECTION INOUT ;
@@ -126,14 +82,6 @@
LAYER met4 ;
RECT 0.000 62.050 5.000 66.500 ;
END
- PORT
- LAYER met5 ;
- RECT 4.000 62.150 5.000 66.400 ;
- END
- PORT
- LAYER met4 ;
- RECT 4.000 62.050 5.000 66.500 ;
- END
END VDDIO_Q
PIN VCCHIB
DIRECTION INOUT ;
@@ -146,14 +94,6 @@
LAYER met4 ;
RECT 0.000 0.000 5.000 5.450 ;
END
- PORT
- LAYER met5 ;
- RECT 4.000 0.100 5.000 5.350 ;
- END
- PORT
- LAYER met4 ;
- RECT 4.000 0.000 5.000 5.450 ;
- END
END VCCHIB
PIN VDDIO
DIRECTION INOUT ;
@@ -174,22 +114,6 @@
LAYER met4 ;
RECT 0.000 17.750 5.000 22.400 ;
END
- PORT
- LAYER met5 ;
- RECT 4.000 68.000 5.000 92.950 ;
- END
- PORT
- LAYER met4 ;
- RECT 4.000 68.000 5.000 92.965 ;
- END
- PORT
- LAYER met5 ;
- RECT 4.000 17.850 5.000 22.300 ;
- END
- PORT
- LAYER met4 ;
- RECT 4.000 17.750 5.000 22.400 ;
- END
END VDDIO
PIN VCCD
DIRECTION INOUT ;
@@ -202,14 +126,6 @@
LAYER met4 ;
RECT 0.000 6.850 5.000 11.500 ;
END
- PORT
- LAYER met5 ;
- RECT 4.000 6.950 5.000 11.400 ;
- END
- PORT
- LAYER met4 ;
- RECT 4.000 6.850 5.000 11.500 ;
- END
END VCCD
PIN VSSIO
DIRECTION INOUT ;
@@ -226,18 +142,6 @@
LAYER met5 ;
RECT 0.000 173.750 5.000 197.965 ;
END
- PORT
- LAYER met5 ;
- RECT 4.000 23.900 5.000 28.350 ;
- END
- PORT
- LAYER met4 ;
- RECT 4.000 23.800 5.000 28.450 ;
- END
- PORT
- LAYER met5 ;
- RECT 4.000 173.750 5.000 197.965 ;
- END
END VSSIO
PIN VSSD
DIRECTION INOUT ;
@@ -250,14 +154,6 @@
LAYER met4 ;
RECT 0.000 39.550 5.000 44.200 ;
END
- PORT
- LAYER met5 ;
- RECT 4.000 39.650 5.000 44.100 ;
- END
- PORT
- LAYER met4 ;
- RECT 4.000 39.550 5.000 44.200 ;
- END
END VSSD
PIN VSSIO_Q
DIRECTION INOUT ;
@@ -270,18 +166,10 @@
LAYER met4 ;
RECT 0.000 56.200 5.000 60.650 ;
END
- PORT
- LAYER met5 ;
- RECT 4.000 56.300 5.000 60.550 ;
- END
- PORT
- LAYER met4 ;
- RECT 4.000 56.200 5.000 60.650 ;
- END
END VSSIO_Q
OBS
LAYER met4 ;
- RECT 0.000 93.365 5.000 197.965 ;
+ RECT 0.000 173.75 5.000 197.965 ;
RECT 0.000 66.900 5.000 67.600 ;
RECT 0.000 61.050 5.000 61.650 ;
RECT 0.000 55.100 5.000 55.800 ;
diff --git a/sky130/custom/sky130_fd_io/lef/sky130_ef_io__corner_pad.lef b/sky130/custom/sky130_fd_io/lef/sky130_ef_io__corner_pad.lef
index efab695..aeb9572 100644
--- a/sky130/custom/sky130_fd_io/lef/sky130_ef_io__corner_pad.lef
+++ b/sky130/custom/sky130_fd_io/lef/sky130_ef_io__corner_pad.lef
@@ -40,10 +40,6 @@
END
PORT
LAYER met5 ;
- RECT 0.630 56.020 0.640 56.030 ;
- END
- PORT
- LAYER met5 ;
RECT 0.000 40.835 1.335 44.085 ;
END
PORT
@@ -71,10 +67,6 @@
RECT 47.735 0.000 56.735 27.155 ;
END
PORT
- LAYER met5 ;
- RECT 51.285 0.630 51.295 0.640 ;
- END
- PORT
LAYER met4 ;
RECT 56.405 0.000 56.735 27.175 ;
END
@@ -243,10 +235,6 @@
RECT 0.000 179.785 1.435 204.000 ;
END
PORT
- LAYER met4 ;
- RECT 0.630 194.865 0.640 194.875 ;
- END
- PORT
LAYER met5 ;
RECT 25.935 0.000 30.385 1.270 ;
END
@@ -258,10 +246,6 @@
LAYER met4 ;
RECT 175.785 0.000 200.000 1.270 ;
END
- PORT
- LAYER met4 ;
- RECT 190.865 0.630 190.875 0.640 ;
- END
END VSSIO
PIN VSSD
DIRECTION INOUT ;
@@ -338,7 +322,6 @@
RECT 0.000 17.935 47.335 18.535 ;
RECT 4.185 12.485 47.335 17.935 ;
RECT 0.000 11.885 47.335 12.485 ;
- POLYGON 0.000 6.035 0.400 6.035 0.400 5.635 ;
RECT 0.400 5.635 2.035 6.035 ;
RECT 2.750 5.635 47.335 11.885 ;
RECT 0.000 1.670 47.335 5.635 ;
@@ -373,7 +356,6 @@
RECT 3.125 22.285 46.135 28.335 ;
RECT 3.070 19.035 46.135 22.285 ;
RECT 5.385 11.385 46.135 19.035 ;
- POLYGON 0.000 6.135 1.600 6.135 1.600 4.535 ;
RECT 1.600 4.535 2.135 6.135 ;
RECT 3.950 4.535 46.135 11.385 ;
RECT 0.000 2.870 46.135 4.535 ;
diff --git a/sky130/custom/sky130_fd_io/lef/sky130_fd_io__top_xres4v2.lef b/sky130/custom/sky130_fd_io/lef/sky130_fd_io__top_xres4v2.lef
new file mode 100644
index 0000000..8d65191
--- /dev/null
+++ b/sky130/custom/sky130_fd_io/lef/sky130_fd_io__top_xres4v2.lef
@@ -0,0 +1,554 @@
+VERSION 5.7 ;
+ NOWIREEXTENSIONATPIN ON ;
+ DIVIDERCHAR "/" ;
+ BUSBITCHARS "[]" ;
+MACRO sky130_fd_io__top_xres4v2
+ CLASS PAD ;
+ FOREIGN sky130_fd_io__top_xres4v2 ;
+ ORIGIN 0.000 0.000 ;
+ SIZE 75.000 BY 200.000 ;
+ SYMMETRY R90 ;
+ PIN PAD_A_ESD_H
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 17.245 0.000 18.910 0.565 ;
+ END
+ PORT
+ LAYER met2 ;
+ RECT 17.245 0.000 18.910 0.565 ;
+ END
+ END PAD_A_ESD_H
+ PIN XRES_H_N
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 28.935 0.000 29.665 0.330 ;
+ END
+ PORT
+ LAYER met2 ;
+ RECT 28.935 0.000 29.665 0.330 ;
+ END
+ END XRES_H_N
+ PIN FILT_IN_H
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 20.075 0.000 21.225 1.410 ;
+ END
+ PORT
+ LAYER met2 ;
+ RECT 20.075 0.000 21.225 1.410 ;
+ END
+ END FILT_IN_H
+ PIN ENABLE_VDDIO
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 8.400 0.000 8.920 0.330 ;
+ END
+ PORT
+ LAYER met2 ;
+ RECT 8.425 0.000 8.895 0.330 ;
+ END
+ END ENABLE_VDDIO
+ PIN TIE_WEAK_HI_H
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 72.190 0.000 73.260 0.330 ;
+ END
+ PORT
+ LAYER met2 ;
+ RECT 72.215 0.000 73.235 0.330 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 72.190 49.985 73.925 64.465 ;
+ END
+ END TIE_WEAK_HI_H
+ PIN ENABLE_H
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 12.285 0.000 12.545 0.330 ;
+ END
+ PORT
+ LAYER met1 ;
+ RECT 12.285 0.000 12.545 0.330 ;
+ END
+ END ENABLE_H
+ PIN PULLUP_H
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 14.555 0.000 15.135 0.330 ;
+ END
+ PORT
+ LAYER met1 ;
+ RECT 14.555 0.000 15.135 0.330 ;
+ END
+ END PULLUP_H
+ PIN EN_VDDIO_SIG_H
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 22.360 0.000 22.660 0.330 ;
+ END
+ PORT
+ LAYER met1 ;
+ RECT 22.360 0.000 22.660 0.330 ;
+ END
+ PORT
+ LAYER met2 ;
+ RECT 29.320 5.360 29.580 10.980 ;
+ END
+ END EN_VDDIO_SIG_H
+ PIN TIE_LO_ESD
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 27.580 0.000 28.230 0.330 ;
+ END
+ PORT
+ LAYER met1 ;
+ RECT 27.580 0.000 28.230 0.330 ;
+ END
+ END TIE_LO_ESD
+ PIN TIE_HI_ESD
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 30.505 0.000 31.155 0.330 ;
+ END
+ PORT
+ LAYER met1 ;
+ RECT 30.505 0.000 31.155 0.330 ;
+ END
+ END TIE_HI_ESD
+ PIN DISABLE_PULLUP_H
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 32.760 0.000 33.020 0.330 ;
+ END
+ PORT
+ LAYER met1 ;
+ RECT 32.760 0.000 33.020 0.330 ;
+ END
+ END DISABLE_PULLUP_H
+ PIN INP_SEL_H
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met1 ;
+ RECT 24.905 0.000 25.135 9.975 ;
+ END
+ END INP_SEL_H
+ PIN VSSIO
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 0.000 175.785 1.270 200.000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 73.730 25.835 75.000 30.485 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 73.730 175.785 75.000 200.000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 0.000 25.835 1.270 30.485 ;
+ END
+ PORT
+ LAYER met5 ;
+ RECT 0.000 175.785 1.270 200.000 ;
+ END
+ PORT
+ LAYER met5 ;
+ RECT 73.730 25.935 75.000 30.385 ;
+ END
+ PORT
+ LAYER met5 ;
+ RECT 73.730 175.785 75.000 200.000 ;
+ END
+ PORT
+ LAYER met5 ;
+ RECT 0.000 25.935 1.270 30.385 ;
+ END
+ END VSSIO
+ PIN VSSA
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 73.730 36.735 75.000 40.185 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 0.000 56.405 75.000 56.735 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 0.000 47.735 75.000 48.065 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 73.730 51.645 75.000 52.825 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 0.000 36.735 1.270 40.185 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 0.000 51.645 1.270 52.825 ;
+ END
+ PORT
+ LAYER met5 ;
+ RECT 73.730 47.735 75.000 56.735 ;
+ END
+ PORT
+ LAYER met5 ;
+ RECT 73.730 36.840 75.000 40.085 ;
+ END
+ PORT
+ LAYER met5 ;
+ RECT 0.000 36.840 1.270 40.085 ;
+ END
+ PORT
+ LAYER met5 ;
+ RECT 0.000 47.735 1.270 56.735 ;
+ END
+ END VSSA
+ PIN VSSD
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 73.730 41.585 75.000 46.235 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 0.000 41.585 1.270 46.235 ;
+ END
+ PORT
+ LAYER met5 ;
+ RECT 73.730 41.685 75.000 46.135 ;
+ END
+ PORT
+ LAYER met5 ;
+ RECT 0.000 41.685 1.270 46.135 ;
+ END
+ END VSSD
+ PIN AMUXBUS_B
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met4 ;
+ RECT 0.000 48.365 75.000 51.345 ;
+ END
+ END AMUXBUS_B
+ PIN AMUXBUS_A
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met4 ;
+ RECT 0.000 53.125 75.000 56.105 ;
+ END
+ END AMUXBUS_A
+ PIN VDDIO_Q
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 73.730 64.085 75.000 68.535 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 0.000 64.085 1.270 68.535 ;
+ END
+ PORT
+ LAYER met5 ;
+ RECT 73.730 64.185 75.000 68.435 ;
+ END
+ PORT
+ LAYER met5 ;
+ RECT 0.000 64.185 1.270 68.435 ;
+ END
+ END VDDIO_Q
+ PIN VDDIO
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 73.730 70.035 75.000 95.000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 73.730 19.785 75.000 24.435 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 0.000 70.035 1.270 95.000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 0.000 19.785 1.270 24.435 ;
+ END
+ PORT
+ LAYER met5 ;
+ RECT 73.730 19.885 75.000 24.335 ;
+ END
+ PORT
+ LAYER met5 ;
+ RECT 73.730 70.035 75.000 94.985 ;
+ END
+ PORT
+ LAYER met5 ;
+ RECT 0.000 70.035 1.270 94.985 ;
+ END
+ PORT
+ LAYER met5 ;
+ RECT 0.000 19.885 1.270 24.335 ;
+ END
+ END VDDIO
+ PIN VSWITCH
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 73.730 31.885 75.000 35.335 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 0.000 31.885 1.270 35.335 ;
+ END
+ PORT
+ LAYER met5 ;
+ RECT 73.730 31.985 75.000 35.235 ;
+ END
+ PORT
+ LAYER met5 ;
+ RECT 0.000 31.985 1.270 35.235 ;
+ END
+ END VSWITCH
+ PIN VDDA
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 74.035 14.935 75.000 18.385 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 0.000 14.935 0.965 18.385 ;
+ END
+ PORT
+ LAYER met5 ;
+ RECT 74.035 15.035 75.000 18.285 ;
+ END
+ PORT
+ LAYER met5 ;
+ RECT 0.000 15.035 0.965 18.285 ;
+ END
+ END VDDA
+ PIN VCCD
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 73.730 8.885 75.000 13.535 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 0.000 8.885 1.270 13.535 ;
+ END
+ PORT
+ LAYER met5 ;
+ RECT 73.730 8.985 75.000 13.435 ;
+ END
+ PORT
+ LAYER met5 ;
+ RECT 0.000 8.985 1.270 13.435 ;
+ END
+ END VCCD
+ PIN VCCHIB
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 73.730 2.035 75.000 7.485 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 0.000 2.035 1.270 7.485 ;
+ END
+ PORT
+ LAYER met5 ;
+ RECT 73.730 2.135 75.000 7.385 ;
+ END
+ PORT
+ LAYER met5 ;
+ RECT 0.000 2.135 1.270 7.385 ;
+ END
+ END VCCHIB
+ PIN VSSIO_Q
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 73.730 58.235 75.000 62.685 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 0.000 58.235 1.270 62.685 ;
+ END
+ PORT
+ LAYER met5 ;
+ RECT 73.730 58.335 75.000 62.585 ;
+ END
+ PORT
+ LAYER met5 ;
+ RECT 0.000 58.335 1.270 62.585 ;
+ END
+ END VSSIO_Q
+ PIN PAD
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met5 ;
+ RECT 17.250 108.455 54.435 164.285 ;
+ END
+ END PAD
+ OBS
+ LAYER nwell ;
+ RECT -0.515 168.515 75.620 170.210 ;
+ RECT -0.515 146.690 1.675 168.515 ;
+ RECT 73.095 146.690 75.620 168.515 ;
+ RECT -0.515 144.880 75.620 146.690 ;
+ LAYER pwell ;
+ RECT -0.290 140.685 75.290 144.565 ;
+ LAYER nwell ;
+ RECT -0.330 130.665 75.330 140.380 ;
+ LAYER pwell ;
+ RECT -0.130 129.315 41.750 130.355 ;
+ RECT 61.910 129.315 75.130 130.355 ;
+ RECT -0.130 124.135 75.130 129.315 ;
+ RECT -0.130 102.525 1.435 124.135 ;
+ RECT 73.560 102.525 75.130 124.135 ;
+ RECT -0.130 99.230 75.130 102.525 ;
+ RECT -0.130 97.995 58.470 99.230 ;
+ RECT 71.930 97.995 75.130 99.230 ;
+ RECT -0.130 96.735 75.130 97.995 ;
+ RECT -0.130 96.730 58.470 96.735 ;
+ LAYER li1 ;
+ RECT 0.000 144.435 75.000 199.220 ;
+ RECT -0.160 140.815 75.160 144.435 ;
+ RECT 0.000 130.225 75.000 140.815 ;
+ RECT -0.265 101.395 75.000 130.225 ;
+ RECT 0.000 0.185 75.000 101.395 ;
+ LAYER met1 ;
+ RECT 0.000 170.090 75.000 199.210 ;
+ RECT -0.145 131.275 75.145 170.090 ;
+ RECT 0.000 130.220 75.000 131.275 ;
+ RECT -0.145 95.895 75.145 130.220 ;
+ RECT 0.000 10.255 75.000 95.895 ;
+ RECT 0.000 0.610 24.625 10.255 ;
+ RECT 0.000 0.185 12.005 0.610 ;
+ RECT 12.825 0.185 14.275 0.610 ;
+ RECT 15.415 0.185 22.080 0.610 ;
+ RECT 22.940 0.185 24.625 0.610 ;
+ RECT 25.415 0.610 75.000 10.255 ;
+ RECT 25.415 0.185 27.300 0.610 ;
+ RECT 28.510 0.185 30.225 0.610 ;
+ RECT 31.435 0.185 32.480 0.610 ;
+ RECT 33.300 0.185 75.000 0.610 ;
+ LAYER met2 ;
+ RECT 0.340 11.260 74.915 199.210 ;
+ RECT 0.340 5.080 29.040 11.260 ;
+ RECT 29.860 5.080 74.915 11.260 ;
+ RECT 0.340 1.690 74.915 5.080 ;
+ RECT 0.340 0.845 19.795 1.690 ;
+ RECT 0.340 0.610 16.965 0.845 ;
+ RECT 0.340 0.000 8.145 0.610 ;
+ RECT 9.175 0.000 12.005 0.610 ;
+ RECT 12.825 0.000 14.275 0.610 ;
+ RECT 15.415 0.000 16.965 0.610 ;
+ RECT 19.190 0.000 19.795 0.845 ;
+ RECT 21.505 0.610 74.915 1.690 ;
+ RECT 21.505 0.000 22.080 0.610 ;
+ RECT 22.940 0.000 27.300 0.610 ;
+ RECT 28.510 0.000 28.655 0.610 ;
+ RECT 29.945 0.000 30.225 0.610 ;
+ RECT 31.435 0.000 32.480 0.610 ;
+ RECT 33.300 0.000 71.935 0.610 ;
+ RECT 73.515 0.000 74.915 0.610 ;
+ LAYER met3 ;
+ RECT 0.965 64.865 74.700 200.000 ;
+ RECT 0.965 49.585 71.790 64.865 ;
+ RECT 74.325 49.585 74.700 64.865 ;
+ RECT 0.965 1.810 74.700 49.585 ;
+ RECT 0.965 0.965 19.675 1.810 ;
+ RECT 0.965 0.730 16.845 0.965 ;
+ RECT 0.965 0.330 8.000 0.730 ;
+ RECT 9.320 0.330 16.845 0.730 ;
+ RECT 19.310 0.330 19.675 0.965 ;
+ RECT 21.625 0.730 74.700 1.810 ;
+ RECT 21.625 0.330 28.535 0.730 ;
+ RECT 30.065 0.330 71.790 0.730 ;
+ RECT 73.660 0.330 74.700 0.730 ;
+ LAYER met4 ;
+ RECT 1.670 175.385 73.330 200.000 ;
+ RECT 0.965 95.400 74.035 175.385 ;
+ RECT 1.670 69.635 73.330 95.400 ;
+ RECT 0.965 68.935 74.035 69.635 ;
+ RECT 1.670 63.685 73.330 68.935 ;
+ RECT 0.965 63.085 74.035 63.685 ;
+ RECT 1.670 57.835 73.330 63.085 ;
+ RECT 0.965 57.135 74.035 57.835 ;
+ RECT 1.670 51.745 73.330 52.725 ;
+ RECT 0.965 46.635 74.035 47.335 ;
+ RECT 1.670 41.185 73.330 46.635 ;
+ RECT 0.965 40.585 74.035 41.185 ;
+ RECT 1.670 36.335 73.330 40.585 ;
+ RECT 0.965 35.735 74.035 36.335 ;
+ RECT 1.670 31.485 73.330 35.735 ;
+ RECT 0.965 30.885 74.035 31.485 ;
+ RECT 1.670 25.435 73.330 30.885 ;
+ RECT 0.965 24.835 74.035 25.435 ;
+ RECT 1.670 19.385 73.330 24.835 ;
+ RECT 0.965 18.785 74.035 19.385 ;
+ RECT 1.365 14.535 73.635 18.785 ;
+ RECT 0.965 13.935 74.035 14.535 ;
+ RECT 1.670 8.485 73.330 13.935 ;
+ RECT 0.965 7.885 74.035 8.485 ;
+ RECT 1.670 2.035 73.330 7.885 ;
+ LAYER met5 ;
+ RECT 2.870 174.185 72.130 200.000 ;
+ RECT 0.000 165.885 75.000 174.185 ;
+ RECT 0.000 106.855 15.650 165.885 ;
+ RECT 56.035 106.855 75.000 165.885 ;
+ RECT 0.000 96.585 75.000 106.855 ;
+ RECT 2.870 18.285 72.130 96.585 ;
+ RECT 2.565 15.035 72.435 18.285 ;
+ RECT 2.870 2.135 72.130 15.035 ;
+ END
+END sky130_fd_io__top_xres4v2
+END LIBRARY
+
