Corrected the other cifinput style (vendorimport) with the same
additions for handling the special FET types in SRAM core cells as
was done in the previous commit.
diff --git a/VERSION b/VERSION
index 32c4ece..e1d2f8b 100644
--- a/VERSION
+++ b/VERSION
@@ -1 +1 @@
-1.0.63
+1.0.64
diff --git a/sky130/magic/sky130.tech b/sky130/magic/sky130.tech
index 975c3a4..fa731c9 100644
--- a/sky130/magic/sky130.tech
+++ b/sky130/magic/sky130.tech
@@ -3795,6 +3795,7 @@
layer pfethvt pfetarea
and HVTP
and-not STDCELL
+ and-not COREID
labels DIFF
# Always force nwell under pfet (nwell encloses pdiff by 0.18)
@@ -3867,7 +3868,7 @@
and STDCELL
labels DIFF
- layer npd DIFF
+ layer npass DIFF
and POLY
and-not PPLUS
and NPLUS
@@ -3875,13 +3876,16 @@
and COREID
labels DIFF
- # layer npass DIFF
- # and POLY
- # and-not PPLUS
- # and NPLUS
- # and-not NWELL
- # and COREID
- # labels DIFF
+ layer npd DIFF
+ and POLY
+ and-not PPLUS
+ and NPLUS
+ and-not NWELL
+ and COREID
+ # Shrink-grow operation eliminates the smaller npass device
+ shrink 70
+ grow 70
+ labels DIFF
layer nfetlvt DIFF
and POLY
@@ -4099,15 +4103,15 @@
layer scpfet POLY
and DIFF
- and-not HVTP
and diffresarea
+ and-not HVTP
and-not NPLUS
and STDCELL
layer scpfethvt POLY
and DIFF
- and HVTP
and diffresarea
+ and HVTP
and-not NPLUS
and STDCELL
