| { | |
| #define DESCRIPTION Skywater 0.13um CMOS, local interconnect + high-resistance poly | |
| #ifdef METAL5 | |
| #define OPTION1 + 5 metal layer backend stack | |
| #else | |
| #define OPTION1 | |
| #endif (METAL5) | |
| #ifdef MIM | |
| #define OPTION2 + MiM caps | |
| #else | |
| #define OPTION2 | |
| #endif (MIM) | |
| #ifdef REDISTRIBUTION | |
| #define OPTION3 + redistribution layer | |
| #else | |
| #define OPTION3 | |
| #endif (REDISTRIBUTION) | |
| #ifdef RERAM | |
| #define OPTION4 + ReRAM | |
| #else | |
| #define OPTION4 | |
| #endif (RERAM) | |
| "foundry": "SW", | |
| "foundry-name": "SkyWater", | |
| "node": "TECHNAME", | |
| "feature-size": "130nm", | |
| "status": "active", | |
| "description": "DESCRIPTION OPTION1 OPTION2 OPTION3 OPTION4", | |
| "options": [ | |
| #ifdef METAL5 | |
| #undef METAL5 | |
| #ifdef MIM || REDISTRIBUTION | |
| "METAL5", | |
| #else (!(MIM || REDISTRIBUTION)) | |
| "METAL5" | |
| #endif (!(MIM || REDISTRIBUTION)) | |
| #endif (METAL5) | |
| #ifdef MIM | |
| #undef MIM | |
| #ifdef (REDISTRIBUTION || RERAM) | |
| "MIM", | |
| #else | |
| "MIM" | |
| #endif (REDISTRIBUTION || RERAM) | |
| #endif (MIM) | |
| #ifdef RERAM | |
| #undef RERAM | |
| #ifdef (REDISTRIBUTION) | |
| "RERAM", | |
| #else | |
| "RERAM" | |
| #endif (REDISTRIBUTION) | |
| #endif (RERAM) | |
| #ifdef REDISTRIBUTION | |
| #undef REDISTRIBUTION | |
| "REDISTRIBUTION" | |
| #endif (REDISTRIBUTION) | |
| ], | |
| "stdcells": { | |
| "sky130_fd_sc_hd": "FD_SC_HD_COMMIT", | |
| "sky130_fd_sc_hdll": "FD_SC_HDLL_COMMIT", | |
| "sky130_fd_sc_hs": "FD_SC_HS_COMMIT", | |
| "sky130_fd_sc_hvl": "FD_SC_HVL_COMMIT", | |
| "sky130_fd_sc_lp": "FD_SC_LP_COMMIT", | |
| "sky130_fd_sc_ls": "FD_SC_LS_COMMIT", | |
| "sky130_fd_sc_ms": "FD_SC_MS_COMMIT", | |
| "sky130_osu_sc_t12": "OSU_T12_COMMIT", | |
| "sky130_osu_sc_t15": "OSU_T15_COMMIT", | |
| "sky130_osu_sc_t18": "OSU_T18_COMMIT" | |
| }, | |
| "iocells": { | |
| "sky130_fd_io": "FD_IO_COMMIT" | |
| }, | |
| "primitive": { | |
| "sky130_fd_pr": "FD_PR_COMMIT", | |
| "sky130_fd_pr_reram": "RERAM_COMMIT" | |
| }, | |
| "memory": { | |
| "sky130_sram_macros": "SRAM_COMMIT", | |
| "sky130_fd_bd_sram": "SRAM_BUILD_COMMIT" | |
| }, | |
| "other": { | |
| "sky130_ml_xx_hd": "ALPHA_COMMIT", | |
| "xschem_sky130": "XSCHEM_COMMIT", | |
| "klayout_sky130": "KLAYOUT_COMMIT", | |
| "precheck_sky130": "PRECHECK_COMMIT" | |
| }, | |
| "build": { | |
| "open_pdks": "OPEN_PDKS_VERSION", | |
| "magic": "MAGIC_VERSION" | |
| }, | |
| "commit": { | |
| "open_pdks": "OPEN_PDKS_COMMIT", | |
| "magic": "MAGIC_COMMIT" | |
| }, | |
| "reference": { | |
| "open_pdks": "9233c19260cd813c3fa67dd4594fe4cc67016832", | |
| "magic": "14afb4bd5207392dc6a2efb0b47cc176e28496ed", | |
| "sky130_fd_pr": "403964dc7f9cca5ec1a8cc7b4f2a6f532b781676", | |
| "sky130_fd_io": "b0c377d9c91b4152e0edd3a766a19185df819888", | |
| "sky130_fd_sc_hs": "c3d7991a9bcb4fc33cbd43262b44bb5560d6fdd0", | |
| "sky130_fd_sc_ms": "29650994547dd83610ccd0a29bae14d665a9e556", | |
| "sky130_fd_sc_ls": "4283919deb7eb4ed195c2b6e95431a812491f6d0", | |
| "sky130_fd_sc_lp": "091cb454662cc662a14b6c9d48567ada50288591", | |
| "sky130_fd_sc_hd": "9cb2d7cb8ed4619094263614039a61b6b2d22a88", | |
| "sky130_fd_sc_hdll": "bf6e0da690bce0e3947a56ab522dee0b15ced988", | |
| "sky130_fd_sc_hvl": "e5413e01fa071029ba84d9faa98d9acd80e75a38", | |
| "sky130_osu_sc_t12": "ac90ef0c622a9377a16b5218d9da3ac4169eeaaf", | |
| "sky130_osu_sc_t15": "95d1c19abb47e1b2945847acb4e817b1b8417c43", | |
| "sky130_osu_sc_t18": "aa2b509f3c8f32ea94fdb55ac9768754667c1658", | |
| "sky130_sram_macros": "5ad1c96053ee8223fe7e956e314646adfce605dd", | |
| "sky130_fd_bd_sram": "be33adbcf188fdeab5c061699847d9d440f7a084", | |
| "sky130_fd_pr_reram": "d6d2a3c6960aac0a0b12fc21221c31777bbf284d", | |
| "sky130_ml_xx_hd": "6eb3b0718552b034f1bf1870285ff135e3fb2dcb", | |
| "xschem_sky130": "95cbdad0ec5fa457ffb360b6ef5596802c8900ee", | |
| "klayout_sky130": "4ea0975391feacbdac697bf07029d8908d292613", | |
| "precheck_sky130": "86b7362dacd931bf1fd957c84501bfbe7955fa7c" | |
| } | |
| } |