Corrected pin connections in the verilog for sky130_ef_io (pins for
two cells incorrectly labeled while splitting the pad and core pins
on the power pads).
diff --git a/VERSION b/VERSION
index 5f7bf9c..754b84e 100644
--- a/VERSION
+++ b/VERSION
@@ -1 +1 @@
-1.0.178
+1.0.179
diff --git a/sky130/custom/sky130_fd_io/verilog/sky130_ef_io.v b/sky130/custom/sky130_fd_io/verilog/sky130_ef_io.v
index 530a4cb..426e9d0 100644
--- a/sky130/custom/sky130_fd_io/verilog/sky130_ef_io.v
+++ b/sky130/custom/sky130_fd_io/verilog/sky130_ef_io.v
@@ -43,7 +43,7 @@
.VSSD(VSSD),
.VSSIO_Q(VSSIO_Q),
.P_CORE(VCCD),
- .P_PAD(PAD_VCCD),
+ .P_PAD(VCCD_PAD),
.OGC_HVC(),
.AMUXBUS_A(AMUXBUS_A),
.AMUXBUS_B(AMUXBUS_B),
@@ -830,8 +830,8 @@
.VSSIO(VSSIO),
.VSSD(VSSD),
.VSSIO_Q(VSSIO_Q),
- .P_CORE(VDDIO_PAD),
- .P_PAD(VDDIO),
+ .P_CORE(VDDIO),
+ .P_PAD(VDDIO_PAD),
.OGC_HVC(),
.AMUXBUS_A(AMUXBUS_A),
.AMUXBUS_B(AMUXBUS_B),
