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foss-eda-tools/third_party/opencircuitdesign.com/open_pdks/aee66ce1fa4fa3cd5cb59bb9982dcdccbf8ab12a/./gf180mcu/magic/gf180mcu.tech
blob: da3c4aaec016f74e2e33a241398e3840953a4f4b [file]
###
### Source file TECHNAME.tech
### Process this file with the preproc.py macro processor
###
#----------------------------------------------------------
# Copyright (c) 2022 Efabless, Inc.
# Techfile created by R. Timothy Edwards for the Google/
# Global Foundries Open PDK project.
#
#----------------------------------------------------------
# This file is designed to be used with magic
# versions 8.3 or newer.
#
# Rules reflect lambda = 0.05um. Minimum grid is 0.005um
#----------------------------------------------------------
tech
format 34
TECHNAME
end
version
version REVISION
description "Global Foundries 180mcu: open PDK rules and DRC"
requires magic-8.3.411
end
#-----------------------------------------------------
# Tile planes
#-----------------------------------------------------
planes
dwell,dw
well,w
active,a
poly,p
metal1,m1
metal2,m2
#ifdef METALS3 || METALS4 || METALS5 || METALS6
metal3,m3
#endif (METALS3 || METALS4 || METALS5 || METALS6)
#ifdef METALS4 || METALS5 || METALS6
metal4,m4
#endif (METALS4 || METALS5 || METALS6)
#ifdef METALS5 || METALS6
metal5,m5
#endif (METALS5 || METALS6)
#ifdef METALS6
metaltp,mtp
#endif (METALS6)
block,b
comment,c
end
#-----------------------------------------------------
# Tile types
#-----------------------------------------------------
types
# Deep nwell
dwell deepnwell,dnwell,dnw
dwell isosubstrate,isosub
# Wells outside deep nwell
well nwell,nw
well pwell,pw
# Well obstruction layer
-well obswell
# Well resistors
well rnw,rnwell
well pbase,npn
well nbase,pnp
# Transistors
active nmos,ntransistor,nfet
active pmos,ptransistor,pfet
active nnmos,nntransistor,nnfet
active mvnmos,mvntransistor,mvnfet
active mvpmos,mvptransistor,mvpfet
active hvnmos,hvntransistor,hvnfet
active hvpmos,hvptransistor,hvpfet
active mvnnmos,mvnntransistor,mvnnfet
# Diffusions
active ndiff,ndiffusion,ndif
active pdiff,pdiffusion,pdif
active mvndiff,mvndiffusion,mvndif
active mvpdiff,mvpdiffusion,mvpdif
active ndiffc,ndcontact,ndc
active pdiffc,pdcontact,pdc
active mvndiffc,mvndcontact,mvndc
active mvpdiffc,mvpdcontact,mvpdc
active psubdiff,psubstratepdiff,ppdiff,ppd,psd
active nsubdiff,nsubstratendiff,nndiff,nnd,nsd
active mvpsubdiff,mvpsubstratepdiff,mvppdiff,mvppd,mvpsd
active mvnsubdiff,mvnsubstratendiff,mvnndiff,mvnnd,mvnsd
active psubdiffcont,psubstratepcontact,psc
active nsubdiffcont,nsubstratencontact,nsc
active mvpsubdiffcont,mvpsubstratepcontact,mvpsc
active mvnsubdiffcont,mvnsubstratencontact,mvnsc
active ldndiff,ldndiffusion,ldndif
active ldpdiff,ldpdiffusion,ldpdif
active ldndiffc,ldndcontact,ldndc
active ldpdiffc,ldpdcontact,ldpdc
-active obsactive
-active mvobsactive
# Layers for special SRAM rule exclusions
-active srammvnfet
-active srammvpfet
-active srammvndiff
-active srammvpdiff
-active srammvndc
-active srammvpdc
-active sramnfet
-active srampfet
-active sramndiff
-active srampdiff
-active sramndc
-active srampdc
# Varactors
active nvaractor,nvaract,nvar
active pvaractor,pvaract,pvar
active mvnvaractor,mvnvaract,mvnvar
active mvpvaractor,mvpvaract,mvpvar
# MOSCAPs
-active nmoscap,ncap
-active pmoscap,pcap
-active mvnmoscap,mvncap
-active mvpmoscap,mvpcap
# Poly
active polysilicon,poly,p
active polycontact,pcontact,polycut,pc,polyc
# Resistors
active npolyres,npres,rnp
active ppolyres,ppres,rpp
active npolysilicide,nsresistor,nspres,rnps
active ppolysilicide,psresistor,pspres,rpps
active efuse
#ifdef HRPOLY1K
active nhighres,nhires,hires
active mvnhighres,mvnhires,mvhires
#endif (HRPOLY1K)
active ndiffres,rnd,rdn,rndiff
active pdiffres,rpd,rdp,rpdiff
active ndiffsilicide,rnds,rdns,rndiffs
active pdiffsilicide,rpds,rdps,rpdiffs
active mvndiffres,mvrnd,mvrdn,mvrndiff
active mvpdiffres,mvrpd,mvrdp,mvrpdiff
active mvndiffsilicide,mvrnds,mvrdns,mvrndiffs
active mvpdiffsilicide,mvrpds,mvrdps,mvrpdiffs
# Diodes
active schottky,skdi
active schottkyc,skdic
active pdiode,pdi
active ndiode,ndi
active nndiode,nndi
active pdiodec,pdic
active ndiodec,ndic
active nndiodec,nndic
active mvpdiode,mvpdi
active mvndiode,mvndi
active mvnndiode,mvnndi
active mvpdiodec,mvpdic
active mvndiodec,mvndic
active mvnndiodec,mvnndic
-active filldiff
# Poly fill
-poly fillpoly
metal1 metal1,m1,met1
metal1 rmetal1,rm1,rmet1
-metal1 m1hole
metal1 via1,m2contact,m2cut,m2c,via,v,v1
-metal1 obsm1
-metal1 fillm1
-metal1 obsv1
metal1 padl
metal2 metal2,m2,met2
metal2 rmetal2,rm2,rmet2
-metal2 m2hole
metal2 via2,m3contact,m3cut,m3c,v2
-metal2 obsm2
-metal2 fillm2
-metal2 obsv2
#ifdef MIM
#ifdef METALS3
metal2 mimcap,mim,capm
metal2 mimcapcontact,mimcapc,mimcc,capmc
#elseif defined(METALS4)
metal3 mimcap,mim,capm
metal3 mimcapcontact,mimcapc,mimcc,capmc
#elseif defined(METALS5)
metal4 mimcap,mim,capm
metal4 mimcapcontact,mimcapc,mimcc,capmc
#elseif defined(METALS6)
metal5 mimcap,mim,capm
metal5 mimcapcontact,mimcapc,mimcc,capmc
#endif
#endif (MIM)
#ifdef METALS3 || METALS4 || METALS5 || METALS6
metal3 metal3,m3,met3
metal3 rmetal3,rm3,rmet3
-metal3 m3hole
-metal3 obsm3
-metal3 fillm3
#endif (METALS3 || METALS4 || METALS5 || METALS6)
#ifdef METALS4 || METALS5 || METALS6
metal3 via3,v3
metal4 metal4,m4,met4
metal4 rmetal4,rm4,rmet4
-metal4 m4hole
-metal4 obsm4
-metal4 fillm4
#endif (METALS4 || METALS5 || METALS6)
#ifdef (METALS5 || METALS6)
metal4 via4,v4
metal5 metal5,m5,met5
metal5 rm5,rmetal5,rmet5
-metal5 m5hole
-metal5 obsm5
-metal5 fillm5
#endif (METALS5 || METALS6)
#ifdef METALS6
metal5 viatp,vtp
metaltp metaltp,mtp,mettp
metaltp rmtp,rmetaltp,rmettp
-metaltp mtphole
-metaltp obsmtp
-metaltp fillmtp
#endif (METALS6)
block glass
block fillblock
-comment lvstext
comment comment
-comment obscomment
end
#-----------------------------------------------------
# Magic contact types
#-----------------------------------------------------
contact
pc poly metal1
ndc ndiff metal1
pdc pdiff metal1
nsc nsd metal1
psc psd metal1
ndic ndiode metal1
nndic nndiode metal1
pdic pdiode metal1
skdic schottky metal1
mvndc mvndiff metal1
mvpdc mvpdiff metal1
mvnsc mvnsd metal1
mvpsc mvpsd metal1
mvndic mvndiode metal1
mvpdic mvpdiode metal1
mvnndic mvnndiode metal1
srammvpdc srammvpdiff metal1
srammvndc srammvndiff metal1
srampdc srampdiff metal1
sramndc sramndiff metal1
ldndc ldndiff metal1
ldpdc ldpdiff metal1
via1 metal1 metal2
#ifdef METALS3 || METALS4 || METALS5 || METALS6
via2 metal2 metal3
#endif (METALS3 || METALS4 || METALS5 || METALS6)
#ifdef METALS4 || METALS5 || METALS6
via3 metal3 metal4
#endif (METALS4 || METALS5 || METALS6)
#ifdef METALS5 || METALS6
via4 metal4 metal5
#endif (METALS5 || METALS6)
#ifdef METALS6
viatp metal5 metaltp
#endif (METALS6)
#ifdef MIM
#ifdef METALS3
mimcc mimcap metal3
#elseif defined(METALS4)
mimcc mimcap metal4
#elseif defined(METALS5)
mimcc mimcap metal5
#elseif defined(METALS6)
mimcc mimcap metaltp
#endif
#endif (MIM)
stackable
#ifdef METALS3
padl m1 m2 m3 glass
#elseif defined(METALS4)
padl m1 m2 m3 m4 glass
#elseif defined(METALS5)
padl m1 m2 m3 m4 m5 glass
#elseif defined(METALS6)
padl m1 m2 m3 m4 m5 mtp glass
#else
padl m1 m2 glass
#endif
end
#-----------------------------------------------------
# Layer aliases
#-----------------------------------------------------
aliases
allnwell nwell,rnwell,nbase
allpsub space/w,pwell,pbase
# Similar to allpsub* but does not include space-on-well-plane
allpwell pwell
# Allsubwell contains space-on-well-plane but not obstruction-on-well-plane
# Used for defining anything under a device that does not touch active/substrate
allsubwell allnwell,allpsub
# Allwells contains obstruction-on-well-plane but not space-on-well-plane
allwells allnwell,allpwell,obswell
allnfets nfet,hvnfet,mvnfet,nnfet,mvnnfet,ncap,mvncap,srammvnfet,sramnfet
allnfetsnonnat nfet,hvnfet,mvnfet,ncap,mvncap,srammvnfet,sramnfet
allpfets pfet,hvpfet,mvpfet,pcap,mvpcap,srammvpfet,srampfet
allfets allnfets,allpfets,nvaractor,mvnvaractor,pvaractor,mvpvaractor
allfetsnonnat allnfetsnonnat,allpfets,nvaractor,mvnvaractor,pvaractor,mvpvaractor
allfetsmv hvnfet,mvnfet,hvpfet,mvpfet,mvnnfet,mvnvaractor,mvpvaractor,mvncap,mvpcap,srammvpfet,srammvnfet
alllvnactivenonfet *ndiff,*nsd,*ndiode,*nndiode,*sramndiff
allmvnactivenonfet *mvndiff,*mvnsd,*mvndiode,*mvnndiode,*ldndiff,*srammvndiff
allnactivenonfet alllvnactivenonfet,allmvnactivenonfet
allnactive allnactivenonfet,allnfets
alllvpactivenonfet *pdiff,*psd,*pdiode,*srampdiff
allmvpactivenonfet *mvpdiff,*mvpsd,*mvpdiode,*ldpdiff,*srammvpdiff
allpactivenonfet alllvpactivenonfet,allmvpactivenonfet
allpactive allpactivenonfet,allpfets
alllvactivenonfet alllvnactivenonfet,alllvpactivenonfet
allmvactivenonfet allmvnactivenonfet,allmvpactivenonfet
allactivenonfet allnactivenonfet,allpactivenonfet
allactive allactivenonfet,allfets
allactiveres ndiffres,pdiffres,mvndiffres,mvpdiffres
allndifflv *ndif,*nsd,*ndiode,*nndiode,ndiffres,nfet,nnfet,ncap,*sramndiff,sramnfet
allpdifflv *pdif,*psd,*pdiode,pdiffres,pfet,pcap,*srampdiff,srampfet
alldifflv allndifflv,allpdifflv
allndifflvnonfet *ndif,*nsd,*ndiode,*nndiode,ndiffres,*sramndiff
allpdifflvnonfet *pdif,*psd,*pdiode,pdiffres,*srampdiff
alldifflvnonfet allndifflvnonfet,allpdifflvnonfet
allndiffmv *mvndif,*mvnsd,*mvndiode,mvndiffres,hvnfet,mvnfet,mvnnfet,mvnvaractor,*mvnndiode,mvncap,*ldndiff,*srammvndiff,srammvnfet
allpdiffmv *mvpdif,*mvpsd,*mvpdiode,mvpdiffres,hvpfet,mvpfet,mvpvaractor,mvpcap,*ldpdiff,*srammvpdiff,srammvpfet
alldiffmv allndiffmv,allpdiffmv
allndiffmvnonfet *mvndif,*mvnsd,*mvndiode,mvndiffres,*mvnndiode,*ldndiff,*srammvndiff
allpdiffmvnonfet *mvpdif,*mvpsd,*mvpdiode,mvpdiffres,*ldpdiff,*srammvpdiff
alldiffmvnonfet allndiffmvnonfet,allpdiffmvnonfet
alldiffnonfet alldifflvnonfet,alldiffmvnonfet
alldiff alldifflv,alldiffmv
#ifdef HRPOLY1K
allpolyres rpp,rnp,rpps,rnps,hires,mvhires
allpolysblkres rpp,rnp,hires,mvhires
allsblkdev rnp,rpp,rnd,rpd,hires,mvhires,mvrnd,mvrpd
#else (!HRPOLY1K)
allpolyres rpp,rnp,rpps,rnps
allpolysblkres rpp,rnp
allsblkdev rnp,rpp,rnd,rpd,mvrnd,mvrpd
#endif (!HRPOLY1K)
allpolynonfet *poly,allpolyres
allpolynonres *poly,allfets
allpoly allpolynonfet,allfets
allpolynoncap *poly,allfets,allpolyres
allndiffcontlv ndc,nsc,ndic,nndic,sramndc
allpdiffcontlv pdc,psc,pdic,srampdc
allndiffcontmv mvndc,mvnsc,mvndic,mvnndic,srammvndc
allpdiffcontmv mvpdc,mvpsc,mvpdic,srammvpdc
allndiffcont allndiffcontlv,allndiffcontmv
allpdiffcont allpdiffcontlv,allpdiffcontmv
alldiffcontlv allndiffcontlv,allpdiffcontlv
alldiffcontmv allndiffcontmv,allpdiffcontmv
alldiffcont alldiffcontlv,alldiffcontmv
allcont alldiffcont,pc
allres allpolyres,allactiveres
alldiode *pdiode,*ndiode,*nndiode,*mvpdiode,*mvndiode,*mvnndiode,*schottky
allm1 *m1,rm1
allm2 *m2,rm2
#ifdef METALS3 || METALS4 || METALS5 || METALS6
#ifdef MIM && METALS4
allm3 *m3,rm3,*mimcap
#else (!(MIM && METALS4))
allm3 *m3,rm3
#endif (!(MIM && METALS4))
#endif (METALS3 || METALS4 || METALS5 || METALS6)
#ifdef METALS4 || METALS5 || METALS6
#ifdef MIM && METALS5
allm4 *m4,rm4,*mimcap
#else (!(MIM && METALS5))
allm4 *m4,rm4
#endif (!(MIM && METALS5))
#endif (METALS4 || METALS5 || METALS6)
#ifdef METALS5 || METALS6
#ifdef MIM && METALS6
allm5 *m5,rm5,*mimcap
#else (!(MIM && METALS6))
allm5 *m5,rm5
#endif (!(MIM && METALS6))
#endif (METALS5 || METALS6)
#ifdef METALS6
allmtp *mtp,rmtp
#endif (METALS6)
allpad padl
end
#-----------------------------------------------------
# Layer drawing styles
#-----------------------------------------------------
styles
styletype mos
dnwell cwell
isosub subcircuit
nwell nwell
rnwell nwell ntransistor_stripes
pwell pwell
ndiff ndiffusion
pdiff pdiffusion
nsd ndiff_in_nwell
psd pdiff_in_pwell
nfet ntransistor ntransistor_stripes
nnfet ntransistor ndiff_in_nwell
pfet ptransistor ptransistor_stripes
nvar polysilicon ndiff_in_nwell
pvar polysilicon pdiff_in_pwell
ndc ndiffusion metal1 contact_X'es
pdc pdiffusion metal1 contact_X'es
nsc ndiff_in_nwell metal1 contact_X'es
psc pdiff_in_pwell metal1 contact_X'es
ncap ntransistor ntransistor_stripes
pcap ptransistor ptransistor_stripes
nbase nwell ntransistor_stripes
pbase pwell ptransistor_stripes
mvndiff ndiffusion hvndiff_mask
mvpdiff pdiffusion hvpdiff_mask
mvnsd ndiff_in_nwell hvndiff_mask
mvpsd pdiff_in_pwell hvpdiff_mask
mvnfet ntransistor ntransistor_stripes hvndiff_mask
hvnfet ntransistor ntransistor_stripes hvndiff_mask
mvnnfet ntransistor ndiff_in_nwell hvndiff_mask
mvpfet ptransistor ptransistor_stripes hvpdiff_mask
hvpfet ptransistor ptransistor_stripes hvpdiff_mask
mvnvar polysilicon ndiff_in_nwell hvndiff_mask
mvpvar polysilicon pdiff_in_pwell hvpdiff_mask
ldndiff hvndiff
ldpdiff hvpdiff
mvndc ndiffusion metal1 contact_X'es hvndiff_mask
mvpdc pdiffusion metal1 contact_X'es hvpdiff_mask
mvnsc ndiff_in_nwell metal1 contact_X'es hvndiff_mask
mvpsc pdiff_in_pwell metal1 contact_X'es hvpdiff_mask
mvncap ntransistor ntransistor_stripes hvndiff_mask
mvpcap ptransistor ptransistor_stripes
ldndc hvndiff metal1 contact_X'es
ldpdc hvpdiff metal1 contact_X'es
srammvndiff ndiffusion hvndiff_mask
srammvpdiff pdiffusion hvpdiff_mask
srammvndc ndiffusion metal1 contact_X'es hvndiff_mask
srammvpdc pdiffusion metal1 contact_X'es hvpdiff_mask
srammvnfet ntransistor ntransistor_stripes
srammvpfet ptransistor ptransistor_stripes
sramndiff ndiffusion
srampdiff pdiffusion
sramndc ndiffusion metal1 contact_X'es
srampdc pdiffusion metal1 contact_X'es
sramnfet ntransistor ntransistor_stripes
srampfet ptransistor ptransistor_stripes
poly polysilicon
pc polysilicon metal1 contact_X'es
npolyres polysilicon silicide_block nselect2
ppolyres polysilicon silicide_block pselect2
efuse polysilicon electrode
pdiode pdiffusion pselect2
ndiode ndiffusion nselect2
nndiode ndiff_in_nwell nselect2
pdiodec pdiffusion pselect2 metal1 contact_X'es
ndiodec ndiffusion nselect2 metal1 contact_X'es
nndiodec ndiff_in_nwell nselect2 metal1 contact_X'es
schottky ndiffusion pdiffusion
schottkyc ndiffusion pdiffusion metal1 contact_X'es
mvpdiode pdiffusion pselect2 hvpdiff_mask
mvndiode ndiffusion nselect2 hvndiff_mask
mvnndiode ndiff_in_nwell nselect2 hvndiff_mask
mvpdiodec pdiffusion pselect2 metal1 contact_X'es hvpdiff_mask
mvndiodec ndiffusion nselect2 metal1 contact_X'es hvndiff_mask
mvnndiodec ndiff_in_nwell nselect2 metal1 contact_X'es hvndiff_mask
metal1 metal1
rm1 metal1 poly_resist_stripes
obsm1 metal1
fillm1 metal1
obsv1 metal1 metal2 via1arrow
m1hole obsmetal1
m2c metal1 metal2 via1arrow
metal2 metal2
rm2 metal2 poly_resist_stripes
obsm2 metal2
fillm2 metal2
obsv2 metal2 metal3 via2arrow
m2hole obsmetal2
#ifdef METALS3 || METALS4 || METALS5 || METALS6
m3c metal2 metal3 via2arrow
metal3 metal3
rm3 metal3 poly_resist_stripes
obsm3 metal3
fillm3 metal3
m3hole obsmetal3
#endif (METALS3 || METALS4 || METALS5 || METALS6)
#ifdef METALS4 || METALS5 || METALS6
via3 metal3 metal4 via3alt
metal4 metal4
rm4 metal4 poly_resist_stripes
obsm4 metal4
fillm4 metal4
m4hole obsmetal4
#endif (METALS4 || METALS5 || METALS6)
#ifdef METALS5 || METALS6
via4 metal4 metal5 via4
metal5 metal5
rm5 metal5 poly_resist_stripes
obsm5 metal5
fillm5 metal5
m5hole obsmetal5
#endif (METALS5 || METALS6)
#ifdef METALS6
viatp metal5 metal6 via5
metaltp metal6
rmtp metal6 poly_resist_stripes
obsmtp metal6
fillmtp metal6
mtphole obsmetal6
#endif (METALS6)
#ifdef MIM
#ifdef METALS3
mimcap metal2 mems
mimcc metal2 contact_X'es mems
#elseif defined(METALS4)
mimcap metal3 mems
mimcc metal3 contact_X'es mems
#elseif defined(METALS5)
mimcap metal4 mems
mimcc metal4 contact_X'es mems
#elseif defined(METALS6)
mimcap metal5 mems
mimcc metal5 contact_X'es mems
#endif
#endif (MIM)
glass overglass
rnp poly_resist poly_resist_stripes ndop_stripes
rpp poly_resist poly_resist_stripes pdop_stripes
rnps poly_resist ndop_stripes
rpps poly_resist pdop_stripes
#ifdef HRPOLY1K
nhighres poly_resist silicide_block
mvnhighres poly_resist silicide_block hvndiff_mask
#endif (HRPOLY1K)
ndiffres ndiffusion ndop_stripes
pdiffres pdiffusion pdop_stripes
mvndiffres ndiffusion hvndiff_mask ndop_stripes
mvpdiffres pdiffusion hvpdiff_mask pdop_stripes
comment comment
lvstext comment
error_p error_waffle
error_s error_waffle
error_ps error_waffle
fillblock cwell
obswell cwell
obsactive implant4
filldiff ndiffusion
fillpoly polysilicon
#ifdef METALS3
padl metal3 via3 overglass
#elseif defined(METALS4)
padl metal4 via4 overglass
#elseif defined(METALS5)
padl metal5 via5 overglass
#elseif defined(METALS6)
padl metal6 via6 overglass
#else
padl metal2 via2 overglass
#endif
magnet substrate_field_implant
rotate via3alt
fence via5
end
#-----------------------------------------------------
# Special paint/erase rules
#-----------------------------------------------------
compose
compose nfet poly ndiff
compose pfet poly pdiff
compose nvar poly nsd
compose pvar poly psd
compose mvnfet poly mvndiff
compose mvpfet poly mvpdiff
compose mvnvar poly mvnsd
compose mvpvar poly mvpsd
compose srammvpfet poly srammvpdiff
compose srammvnfet poly srammvndiff
compose srampfet poly srampdiff
compose sramnfet poly sramndiff
decompose hvpfet poly mvpdiff
decompose hvnfet poly mvndiff
#ifdef MIM
#ifdef METALS3
paint mimcap m2 mimcap
paint mimcapc m2 mimcapc
#elseif defined(METALS4)
paint mimcap m3 mimcap
paint mimcapc m3 mimcapc
#elseif defined(METALS5)
paint mimcap m4 mimcap
paint mimcapc m4 mimcapc
#elseif defined(METALS6)
paint mimcap m5 mimcap
paint mimcapc m5 mimcapc
#endif
#endif (MIM)
paint ndc nwell pdc
paint nfet nwell pfet
paint ndiff nwell pdiff
paint psd nwell nsd
paint psc nwell nsc
paint ldndiff nwell ldpdiff
paint pdc pwell ndc
paint pfet pwell nfet
paint pdiff pwell ndiff
paint nsd pwell psd
paint nsc pwell psc
paint ldpdiff pwell ldndiff
paint m1 obsm1 m1
paint m2 obsm2 m2
#ifdef METALS3 || METALS4 || METALS5 || METALS6
paint m3 obsm3 m3
#endif (METALS3 || METALS4 || METALS5 || METALS6)
#ifdef METALS4 || METALS5 || METALS6
paint m4 obsm4 m4
#endif (METALS4 || METALS5 || METALS6)
#ifdef METALS5 || METALS6
paint m5 obsm5 m5
#endif (METALS5 || METALS6)
#ifdef METALS6
paint mtp obsmtp mtp
#endif (METALS6)
end
#-----------------------------------------------------
# Electrical connectivity
#-----------------------------------------------------
connect
nwell,*nsd,*mvnsd,nbase,dnwell nwell,*nsd,*mvnsd,nbase,dnwell
pwell,*psd,*mvpsd,pbase,isosub pwell,*psd,*mvpsd,pbase,isosub
# Note: This connects butting taps even without a metal strap.
*nsd,*mvnsd *pdiff,*mvpdiff
*psd,*mvpsd *ndiff,*mvndiff
*m1 *m1
*m2 *m2
#ifdef METALS3 || METALS4 || METALS5 || METALS6
*m3 *m3
#endif (METALS3 || METALS4 || METALS5 || METALS6)
#ifdef METALS4 || METALS5 || METALS6
*m4 *m4
#endif (METALS4 || METALS5 || METALS6)
#ifdef METALS5 || METALS6
*m5 *m5
#endif (METALS5 || METALS6)
#ifdef METAL6
*mtp *mtp
#endif (METALS6)
#ifdef MIM
*mimcap *mimcap
#endif (MIM)
allnactivenonfet allnactivenonfet
allpactivenonfet allpactivenonfet
*poly,allfets *poly,allfets
*schottky *schottky
end
#-----------------------------------------------------
# CIF/GDS output layer definitions
#-----------------------------------------------------
# NOTE: All values in this section MUST be multiples of 25
# or else magic will scale below the allowed layout grid size
cifoutput
#-----------------------------------------------------
style gdsii
#-----------------------------------------------------
scalefactor 50 nanometers
options calma-permissive-labels
gridlimit 5
# This section used for actual GDSII output
#-----------------------------------------------------
# DNWELL
#-----------------------------------------------------
layer DNWELL dnwell
calma 12 0
#-----------------------------------------------------
# SUBCUT
#-----------------------------------------------------
layer SUBCUT isosub
calma 23 5
#-----------------------------------------------------
# NWELL
#-----------------------------------------------------
layer NWELL allnwell
# Require nwell under n-tap and p-diffusion
or *nsd,*mvnsd,*pdiff,*mvpdiff,allpfets,pdiffres,mvpdiffres
labels allnwell noport
close 1000000
calma 21 0
layer NWELLTXT
labels allnwell port
calma 21 10
#-----------------------------------------------------
# PWELL (LVPWELL)
#-----------------------------------------------------
layer PWELL allpwell
labels allpwell noport
calma 204 0
layer PWELLTXT
labels allpwell port
calma 204 10
#-----------------------------------------------------
# DIFF (COMP)
#-----------------------------------------------------
# LDFETs cut the diffusion under the gate
templayer ldbreak1 *ldndiff,*ldpdiff
grow 160
and hvnfet,hvpfet,mvnfet,mvpfet
templayer ldbreak hvnfet,hvpfet,mvnfet,mvpfet
grow 200
and ldndiff,ldpdiff
or ldbreak1
# Additional cut-back of LD diffusion for implant
templayer ldbreak2 hvnfet,hvpfet,mvnfet,mvpfet
grow 240
and ldndiff,ldpdiff
# Schottky diode drawn as abutting diffusion, but
# there is a 0.28um gap between the nsd and the
# Schottky diffusion.
templayer scsep *nsd
grow 280
layer DIFF schottky
and-not scsep
or alldiff
and-not ldbreak
labels alldiff,schottky
calma 22 0
layer DIFFFILL filldiff
labels filldiff
calma 22 4
#-----------------------------------------------------
# LDFET implants
#-----------------------------------------------------
layer MVNSD ldndiff
and-not ldbreak2
grow 800
calma 210 0
layer MVPSD ldpdiff
and-not ldbreak2
grow 800
calma 11 39
#-----------------------------------------------------
# Bipolar ID markers
#-----------------------------------------------------
layer BJTDRC nbase
grow 580
bloat-all pbase dnwell
grow 20
layer BJTLVS nbase
grow 580
bloat-all pbase dnwell
grow 20
#-----------------------------------------------------
# PPLUS, NPLUS
#-----------------------------------------------------
#ifdef HRPOLY1K
layer RESDEF
bloat-or hires,mvhires * 280 poly 0
grow 200
shrink 200
calma 110 5
# hires requires PPLUS around terminals
templayer HRTERM
bloat-all hires,mvhires *poly
and-not hires,mvhires
layer SBLK
bloat-or hires,mvhires * 280 poly 100
calma 49 0
#endif (HRPOLY1K)
# rnps requires NPLUS surround 0.18um
# rnp requires NPLUS surround 0.3um
# rnd requires NPLUS surround 0.18um
layer NPLUS
bloat-all rnp *poly
grow 120
bloat-all rnps *poly
bloat-all rnd *ndiff
grow 180
grow 180
shrink 180
mask-hints NPLUS
calma 32 0
# standard generation of NPLUS
templayer nwell_shrink nwell
shrink 430
templayer shortntap *nsd,*mvnsd
and-not dnwell
and-not nwell_shrink
grow 160
templayer shortdntap dnwell
and pwell
grow 430
and *nsd,*mvnsd
grow 160
layer NPLUS
bloat-or *ndif,*ndiode,*nndiode,ndiffres,*mvndif,*mvndiode,*mvnndiode,mvndiffres,*srammvndiff,*sramndiff * 160 allpactivenonfet 0
# NOTE: Rule CO.5a applies to butted contacts but Calibre rule is
# implemented for all contacts, so the Calibre rule is being followed.
bloat-or nsc,mvnsc * 95
bloat-or *nsd,*mvnsd * 20 allpactivenonfet 0
bloat-or allnfets,nvar,mvnvar * 230
or shortntap,shortdntap
grow 200
shrink 200
mask-hints NPLUS
calma 32 0
# rpps requires PPLUS surround 0.18um
# rpp requires PPLUS surround 0.30um
# rpd requires PPLUS surround 0.18um
layer PPLUS
bloat-all rpp *poly
grow 120
bloat-all rpps *poly
bloat-all rpd *pdiff
grow 180
grow 180
shrink 180
mask-hints PPLUS
calma 31 0
# standard generation of PPLUS, including hires resistors
templayer shortptap nwell
and-not dnwell
grow 430
and *psd,*mvpsd
grow 160
templayer pwell_shrink pwell
and dnwell
shrink 430
templayer shortdptap *psd,*mvpsd
and dnwell
and-not pwell_shrink
grow 160
layer PPLUS
#ifdef HRPOLY1K
or HRTERM
grow 200
and-not RESDEF
#endif (HRPOLY1K)
bloat-or *pdif,*pdiode,pdiffres,pfet,pcap,*mvpdif,*mvpdiode,mvpdiffres,hvpfet,mvpfet,mvpcap,*srammvpdiff,srammvpfet,*srampdiff,srampfet * 160 allnactivenonfet 0
# NOTE: Rule CO.5b applies to butted contacts but Calibre rule is
# implemented for all contacts, so the Calibre rule is being followed.
bloat-or psc,mvpsc * 95
bloat-or *psd,*mvpsd * 20 allnactivenonfet 0
bloat-or allpfets,pvar,mvpvar * 230
or shortptap,shortdptap
grow 200
shrink 200
calma 31 0
#-----------------------------------------------------
# DUALGATE (thickox)
#-----------------------------------------------------
layer DUALGATE
# NOTE: This rule requires satisfying PL.19; poly cannot
# cross a DUALGATE boundary.
bloat-all mvhires,allfetsmv *poly
# Rule DV.8 (DUALGATE around poly)
grow 400
# Rule DV.6 (DUALGATE around diff, LV substrate tap excepted)
bloat-or allndiffmv * 240 *psd 0
bloat-or allpdiffmv * 240
grow 219
shrink 219
mask-hints DUALGATE
calma 55 0
# DUALGATE completely covers deep nwell
layer DUALGATE
bloat-all alldiffmv dnwell
grow 500
grow 219
shrink 219
calma 55 0
#-----------------------------------------------------
# NAT
#-----------------------------------------------------
layer NAT
bloat-all *nndiode,nnfet *ndiff
bloat-all *mvnndiode,mvnnfet *mvndiff
grow 260
grow 309
shrink 309
calma 5 0
#-----------------------------------------------------
# FET5VDEF
#-----------------------------------------------------
# Ensure FET5VDEF surrounds all mv (5V) FET devices.
# This ensures that short length devices do not get
# flagged for DRC errors.
layer FET5VDEF
bloat-all mvnfet,mvpfet,srammvnfet,srammvpfet \
*mvndiff,*mvpdiff,mvndiffres,mvpdiffres
grow 100
calma 112 1
#-----------------------------------------------------
# POLY
#-----------------------------------------------------
layer POLY allpoly
close 224000
labels allpoly noport
calma 30 0
layer POLYTXT
labels allpoly port
calma 30 10
layer POLYFILL fillpoly
labels fillpoly
calma 30 4
layer PLFUSE efuse
calma 125 5
layer EFUSE efuse
bloat-all efuse *poly
calma 80 5
#-----------------------------------------------------
# CONT
#-----------------------------------------------------
# NOTE: Contact arrays defined at 200 spacing for large array rule (4x4),
# otherwise spacing is 180
layer contlarge allcont
shrink 615
grow 615
layer CONT allcont
and-not contlarge
squares-grid 5 220 250
calma 33 0
layer CONT allcont
and contlarge
squares-grid 5 220 280
calma 33 0
#-----------------------------------------------------
# MET1
#-----------------------------------------------------
layer MET1 allm1
labels allm1 noport
calma 34 0
layer MET1TXT
labels allm1 port
calma 34 10
layer M1BLOCK obsm1
labels obsm1
calma 34 5
layer M1FILL fillm1
labels fillm1
calma 34 4
#-----------------------------------------------------
# VIA1
#-----------------------------------------------------
templayer via1large via1
shrink 915
grow 915
layer VIA1 via1
and-not via1large
squares-grid 0 260 260
calma 35 0
layer VIA1 via1
and via1large
squares-grid 0 260 360
calma 35 0
#-----------------------------------------------------
# MET2
#-----------------------------------------------------
layer MET2 allm2
labels allm2 noport
calma 36 0
layer MET2TXT
labels allm2 port
calma 36 10
layer M2BLOCK obsm2
labels obsm2
calma 36 5
layer M2FILL fillm2
labels fillm2
calma 36 4
#ifdef METALS3 || METALA4 || METALS5 || METALS6
#-----------------------------------------------------
# VIA2
#-----------------------------------------------------
templayer via2large via2
shrink 915
grow 915
layer VIA2 via2
and-not via2large
squares-grid 10 260 260
calma 38 0
layer VIA2 via2
and via2large
squares-grid 10 260 360
calma 38 0
#ifdef MIM && METALS3
layer VIA2 mimcapc
squares-grid 40 260 500
calma 38 0
#endif (MIM && METALS3)
#-----------------------------------------------------
# MET3
#-----------------------------------------------------
layer MET3 allm3
labels allm3 noport
calma 42 0
layer MET3TXT
labels allm3 port
calma 42 10
layer M3BLOCK obsm3
labels obsm3
calma 42 5
layer M3FILL fillm3
labels fillm3
calma 42 4
#endif (METALS3 || METALA4 || METALS5 || METALS6)
#ifdef METALS4 || METALS5 || METALS6
#-----------------------------------------------------
# VIA3
#-----------------------------------------------------
templayer via3large via3
shrink 915
grow 915
layer VIA3 via3
and-not via3large
squares-grid 10 260 260
calma 40 0
layer VIA3 via3
and via3large
squares-grid 10 260 360
calma 40 0
#ifdef MIM && METALS4
layer VIA3 mimcapc
squares-grid 40 260 500
calma 40 0
#endif (MIM && METALS4)
#-----------------------------------------------------
# MET4
#-----------------------------------------------------
layer MET4 allm4
labels allm4 noport
calma 46 0
layer MET4TXT
labels allm4 port
calma 46 10
layer M4BLOCK obsm4
labels obsm4
calma 46 5
layer M4FILL fillm4
labels fillm4
calma 46 4
#endif (METALS4 || METALS5 || METALS6)
#ifdef METALS5 || METALS6
#-----------------------------------------------------
# VIA4
#-----------------------------------------------------
templayer via4large via4
shrink 915
grow 915
layer VIA4 via4
and-not via4large
squares-grid 10 260 260
calma 41 0
layer VIA4 via4
and via4large
squares-grid 10 260 360
calma 41 0
#ifdef (MIM && METALS5)
layer VIA4 mimcapc
squares-grid 40 260 500
calma 41 0
#endif (MIM && METALS5)
#-----------------------------------------------------
# MET5
#-----------------------------------------------------
layer MET5 allm5
labels allm5 noport
calma 81 0
layer MET5TXT
labels allm5 port
calma 81 10
layer M5BLOCK obsm5
labels obsm5
calma 81 5
layer M5FILL fillm5
labels fillm5
calma 81 4
#endif (METALS5 || METALS6)
#ifdef METALS6
#-----------------------------------------------------
# VIATP
#-----------------------------------------------------
templayer viatplarge viatp
shrink 975
grow 975
layer VIATP viatp
and-not viatplarge
squares-grid 10 260 260
calma 129 0
layer VIATP viatp
and viatplarge
squares-grid 10 160 360
calma 129 0
#ifdef MIM
layer VIATP mimcapc
squares-grid 40 260 500
calma 129 0
#endif (MIM)
#-----------------------------------------------------
# METTP
#-----------------------------------------------------
layer METTP allmtp
labels allmtp noport
calma 53 0
layer METTPTXT
labels allmtp port
calma 53 10
layer MTPBLOCK obsmtp
labels obsmtp
calma 53 5
layer MTPFILL fillmtp
labels fillmtp
calma 53 4
#endif (METALS6)
#-----------------------------------------------------
# GLASS
#-----------------------------------------------------
layer GLASS glass
calma 37 0
#-----------------------------------------------------
# PRBNDRY
#-----------------------------------------------------
templayer CELLBOUND
boundary
layer PRBNDRY CELLBOUND
calma 0 0
#ifdef MIM
#undef MIM
#-----------------------------------------------------
# CAPM
#-----------------------------------------------------
# NOTE: MiM bottom plate handled by alias "allm*" when MIM defined
layer CAPM *mimcap
labels mimcap
calma 75 0
layer CAPDEF *mimcap
grow 200
calma 117 5
layer CAP_LENGTH
mask-hints CAP_LENGTH
calma 117 10
#define MIM
#endif (MIM)
#-----------------------------------------------------
# SBLK
#-----------------------------------------------------
layer SBLK
bloat-all rnd *nfet
bloat-all rpd *pfet
bloat-all mvrnd *mvnfet,*hvnfet
bloat-all mvrpd *mvpfet,*hvpfet
and allfets
grow 220
bloat-or allsblkdev * 0 space/a 220
bloat-or allpolysblkres * 0 space/a 280
grow 215
shrink 215
mask-hints SBLK
calma 49 0
#-----------------------------------------------------
# RESDEF MARK
#-----------------------------------------------------
# Identify unsalicided drain areas in I/O ESD structures.
# These are not marked with RESDEF.
templayer esd_io
bloat-all mvndiffres *mvndiff,hvnfet,mvnfet
bloat-all mvpdiffres *mvpdiff,hvpfet,mvpfet
layer RESDEF allres
and-not esd_io
calma 110 5
#-----------------------------------------------------
# METAL RESISTOR IDs
#-----------------------------------------------------
layer MET1RES rm1
calma 110 11
layer MET2RES rm2
calma 110 12
#ifdef METALS3 || METALS4 || METALS5 || METALS6
layer MET3RES rm3
calma 110 13
#endif (METALS3 || METALS4 || METALS5 || METALS6)
#ifdef METALS4 || METALS5 || METALS6
layer MET4RES rm4
calma 110 14
#endif (METALS4 || METALS5 || METALS6)
#ifdef METALS5 || METALS6
layer MET5RES rm5
calma 110 15
#endif (METALS5 || METALS6)
#ifdef METALS6
layer METTPRES rmtp
calma 110 16
#endif (METALS6)
#-----------------------------------------------------
# DIODE MARK
#-----------------------------------------------------
layer DIODE alldiode
calma 115 5
#-----------------------------------------------------
# SCHOTTKY MARK
#-----------------------------------------------------
layer SCHOTTKY
bloat-all *schottky *nsd
grow 160
calma 241 0
#-----------------------------------------------------
# MOSCAP MARK
#-----------------------------------------------------
layer MOSCAP nvar,mvnvar,pvar,mvpvar,ncap,pcap,mvncap,mvpcap
calma 166 5
#ifdef HRPOLY1K
#-----------------------------------------------------
# HRES
#-----------------------------------------------------
layer HRES
bloat-all hires,mvhires *poly
grow 400
calma 62 0
#endif (HRPOLY1K)
#----------------------------------------------------------------------
# SRAM
# NOTE: Do not output SRAMDEF from magic layout. Only to be used
# with read-only cells (unless using mask hints).
#----------------------------------------------------------------------
layer SRAMDEF
# bloat-all srammvpfet,srammvnfet,*srammvpdiff,*srammvndiff CELLBOUND
# bloat-all srampfet,sramnfet,*srampdiff,*sramndiff CELLBOUND
mask-hints SRAMDEF
calma 108 5
# I/O pads should have latchup and ESD markers; these are not
# recognized layers and must be handled with mask hints.
layer LATCHUP_ID esd_io
mask-hints LATCHUP_ID
calma 137 5
layer ESD_ID esd_io
mask-hints ESD_ID
calma 24 5
#------------------------------------------------------------------------
# FILLBLOCK (NOTE: two layers define this on active, then poly & metal)
#------------------------------------------------------------------------
# layer FILLOBS fillblock
# calma 111 5
layer FILLOBS2 fillblock
calma 152 5
#----------------------------------------------------------
style metfill
#----------------------------------------------------------
# This section used for metal filling output by a sequence
# of cif paint commands
scalefactor 50 nanometers
options calma-permissive-labels
gridlimit 5
#-----------------------------------------------------
# Fill layer geometry
#-----------------------------------------------------
templayer fill_geometry_off0
bbox top
slots 0 2000 1000 0 2000 1000 1000 0
templayer fill_geometry_off1
bbox top
slots 0 2000 1000 0 2000 1000 1000 660
templayer fill_geometry_off2
bbox top
slots 0 2000 1000 0 2000 1000 1000 1320
#ifdef THICKMET3P0
templayer fill_geometry_thick
bbox top
slots 0 6000 2000 0 6000 2000 3000 2000
#endif (THICKMET3P0)
#-----------------------------------------------------
# Obstruction geometry
#-----------------------------------------------------
templayer obstruct_diff alldiff,schottky,filldiff,obsactive
grow 2010
shrink 500
grow 500
templayer obstruct_poly allpoly,fillpoly
grow 2010
shrink 500
grow 500
templayer obstruct_m1 allm1,allpad,fillm1,obsm1
grow 2010
shrink 500
grow 500
templayer obstruct_m2 allm2,allpad,fillm2,obsm2
grow 2010
shrink 500
grow 500
#ifdef METALS3 || METALS4 || METALS5 || METALS6
templayer obstruct_m3 allm3,allpad,fillm3,obsm3
grow 2010
shrink 500
grow 500
#endif (METALS3 || METALS4 || METALS5 || METALS6)
#ifdef METALS4 || METALS5 || METALS6
templayer obstruct_m4 allm4,allpad,fillm4,obsm4
grow 2010
shrink 500
grow 500
#endif (METALS4 || METALS5 || METALS6)
#ifdef METALS5 || METALS6
templayer obstruct_m5 allm5,allpad,fillm5,obsm5
grow 2010
shrink 500
grow 500
#endif (METALS5 || METALS6)
#ifdef METALS6
#ifdef THICKMET3P0
templayer obstruct_mtp allmtp,allpad,fillmtp,obsmtp
grow 2010
shrink 500
grow 500
#elseif THICKMET0P9 || THICKMET1P1
templayer obstruct_mtp allmtp,allpad,fillmtp,obsmtp
grow 2010
shrink 500
grow 500
#else (!(THICKMET3P0 || THICKMET1P1 || THICKMET0P9 )
templayer obstruct_mtp allmtp,allpad,fillmtp,obsmtp
grow 2010
shrink 500
grow 500
#endif
#endif (METALS6)
#-----------------------------------------------------
# DIFF FILL
#-----------------------------------------------------
layer difffill fill_geometry_off0
shrink 995
grow 995
#-----------------------------------------------------
# POLY FILL
#-----------------------------------------------------
layer polyfill fill_geometry_off1
and-not obstruct_m1
shrink 995
grow 995
#-----------------------------------------------------
# MET1 FILL
#-----------------------------------------------------
layer met1fill fill_geometry_off2
and-not obstruct_poly
and-not obstruct_m1
and-not obstruct_m2
shrink 995
grow 995
#-----------------------------------------------------
# MET2 FILL
#-----------------------------------------------------
layer met2fill fill_geometry_off0
and-not obstruct_m1
and-not obstruct_m2
shrink 995
grow 995
#ifdef METALS3 || METALS4 || METALS5 || METALS6
#-----------------------------------------------------
# MET3 FILL
#-----------------------------------------------------
layer met3fill fill_geometry_off1
and-not obstruct_m2
and-not obstruct_m3
shrink 995
grow 995
#endif (METALS3 || METALS4 || METALS5 || METALS6)
#ifdef METALS4 || METALS5 || METALS6
#-----------------------------------------------------
# MET4 FILL
#-----------------------------------------------------
layer met4fill fill_geometry_off2
and-not obstruct_m3
and-not obstruct_m4
shrink 995
grow 995
#endif (METALS4 || METALS5 || METALS6)
#ifdef METALS5 || METALS6
#-----------------------------------------------------
# MET5 FILL
#-----------------------------------------------------
layer met5fill fill_geometry_off0
and-not obstruct_m4
and-not obstruct_m5
shrink 995
grow 995
#endif (METALS5 || METALS6)
#ifdef METALS6
#-----------------------------------------------------
# METTP FILL
#-----------------------------------------------------
layer mettpfill fill_geometry_off1
and-not obstruct_m5
and-not obstruct_mtp
shrink 995
grow 995
#endif (METALS6)
#-----------------------------------------------------------------------
style drc
#-----------------------------------------------------------------------
# NOTE: this style is used for DRC only, not for GDS output
#-----------------------------------------------------------------------
scalefactor 50 nanometers
options calma-permissive-labels
gridlimit 5
# Check that all p-diff and n-ohmic have either nwell or dnwell
templayer missing_nwell *nsd,*mvnsd,*pdiff,*mvpdiff,*pdiode,pdiffres,mvpdiffres,pfet,hvpfet,mvpfet,srammvpfet,srampfet,mvnvaractor
and-not dnwell,nwell
# Check that all p-ohmic and n-diff have either pwell + dnwell
# or nothing. Can check the pwell surround at the same time.
templayer pohmic_missing_pwell *psd
grow 120
and dnwell
and-not pwell,pbase
templayer mvpohmic_missing_pwell *mvpsd,mvpvaractor
grow 160
and dnwell
and-not pwell
templayer ndiff_missing_pwell *ndiff,*ndiode,ndiffres,nfet,*sramndiff,sramnfet
grow 430
and dnwell
and-not pwell
templayer mvndiff_missing_pwell *mvndiff,mvndiffres,hvnfet,mvnfet,*srammvndiff,srammvnfet
grow 600
and dnwell
and-not pwell
# Check for MV and LV devices in the same dnwell
templayer mv_dnwell
bloat-all alldiffmv,schottky dnwell
templayer bad_dnwell
bloat-all alldifflv dnwell
and mv_dnwell
# Check pwell in dnwell
templayer pwell_in_dnwell pwell
and dnwell
and-not mv_dnwell
templayer mvpwell_in_dnwell pwell
and mv_dnwell
# Check for MV and LV devices in the same nwell
templayer mv_nwell
bloat-all alldiffmv nwell
templayer bad_nwell
# All low-voltage diffusion except tap diffusion (nsd, psd)
bloat-all *ndif,*ndiode,*nndiode,ndiffres,nfet,nnfet,ncap,*pdif,*pdiode,pdiffres,pfet,pcap,schottky nwell
and mv_nwell
# Check for nwell resistor in deep nwell
templayer bad_rnw rnw
and dnwell
# Check for minimum PPLUS and NPLUS area. NOTE: These are simplified
# versions of the cifoutput rules.
templayer check_pplus
bloat-or *pdif,*pdiode,pdiffres,pfet,pcap,*mvpdif,*mvpdiode,mvpdiffres,hvpfet,mvpfet,mvpcap,srammvpfet,srampfet * 160 allnactivenonfet 0
bloat-or psc,mvpsc * 95
bloat-or *psd,*mvpsd * 20 allnactivenonfet 0
grow 200
shrink 200
templayer check_nplus
bloat-or *ndif,*ndiode,*nndiode,ndiffres,nfet,*mvndif,*mvndiode,*mvnndiode,mvndiffres,hvnfet,hvnfet,mvnfet,*srammvndiff,srammvnfet,*sramndiff,sramnfet * 160 allpactivenonfet 0
bloat-or nsc,mvnsc * 95
bloat-or *nsd,*mvnsd * 20 allpactivenonfet 0
grow 200
shrink 200
# Define HRES layer for DRC checks
templayer res_hres
bloat-all mvhires,hires *poly
# Check for contact at correct position for HIRES, LRES, PRES resistors
templayer res_cont res_hres
bloat-all rnp,rpp *poly
and pc
squares-grid 5 220 250
templayer res_cont_space_min mvhires,hires
# SBLK larger than defined resistor by 0.1um
grow 100
# SBLK = resistor for rnp and rpp
or rnp,rpp
# SBLK spacing to contact
grow 220
and res_cont
# If anything remains, contact is too close.
templayer res_cont_space_max mvhires,hires
# SBLK larger than defined resistor by 0.1um
grow 100
# SBLK = resistor for rnp and rpp
or rnp,rpp
# SBLK spacing to contact
grow 220
# size of poly contact
grow 220
and res_cont
templayer res_no_cont res_cont
and-not res_cont_space_max
# If anything remains, contact is too far away
# Check for HRES to poly and diffusion spacing
templayer res_hres_grow res_hres
grow 700
templayer res_diff_space res_hres_grow
and alldiff
# If anything remains, HRES is too close to diffusion
templayer res_poly_space res_hres_grow
and-not res_hres
and allpoly
# If anything remains, HRES is too close to poly
# Check for MiM cap bottom plate to other metal spacing rule (< 1.2um)
templayer mim_bottom_plate
#ifdef METALS3
bloat-all *mim *m2
#endif
#ifdef METALS4
bloat-all *mim *m3
#endif
#ifdef METALS5
bloat-all *mim *m4
#endif
#ifdef METALS6
bloat-all *mim *m5
#endif
templayer mim_bottom_plate_space mim_bottom_plate
grow 1200
#ifdef METALS3
and m2
#endif
#ifdef METALS4
and m3
#endif
#ifdef METALS5
and m4
#endif
#ifdef METALS6
and m5
#endif
and-not mim_bottom_plate
# If anything remains, bottom plate is too close
# Check for MiM cap bottom plate surrounds contact (by 0.4um)
#ifdef METALS3
templayer mim_bot_cont_surround via2
#endif
#ifdef METALS4
templayer mim_bot_cont_surround via3
#endif
#ifdef METALS5
templayer mim_bot_cont_surround via4
#endif
#ifdef METALS6
templayer mim_bot_cont_surround viamt
#endif
and mim_bottom_plate
squares-grid 10 260 500
grow 400
and-not mim_bottom_plate
# If anything remains, not enough surround
end
#-----------------------------------------------------------------------
cifinput
#-----------------------------------------------------------------------
# NOTE: All values in this section MUST be multiples of 25
# or else magic will scale below the allowed layout grid size
style import
scalefactor 50 nanometers
gridlimit 5
options ignore-unknown-layer-labels
ignore CAPDEF
ignore EFUSE
ignore SOURCE
ignore VTEXT
ignore FILLOBS
ignore SCRIBE
ignore LATCHUP_ID
ignore IO_ID
ignore ESD_ID
layer pwell PWELL,PWELLTXT
and-not BJTDEF,BJTDRC
labels PWELL
labels PWELLTXT port
layer pbase PWELL,PWELLTXT
and BJTDEF,BJTDRC
layer nwell NWELL,NWELLTXT
and-not BJTDEF,BJTDRC
labels NWELL
labels NWELLTXT port
templayer nwellarea NWELL
copyup nwelcheck
# Copy nwell areas up for diffusion checks
templayer xnwelcheck nwelcheck
copyup nwelcheck
layer nbase NWELL,NWELLTXT
and BJTDEF,BJTDRC
layer dnwell DNWELL
labels DNWELL
layer isosub SUBCUT
labels SUBCUT
# Implicit nwell defined by DNWELL outside of PWELL
templayer nwelldef DNWELL
shrink 500
and-not PWELL
or NWELL,nwelcheck
templayer ndiffarea DIFF
and-not POLY
and-not nwelldef
and-not PPLUS
and-not SBLK
and-not DUALGATE
and NPLUS
copyup ndifcheck
layer ndiff ndiffarea
labels DIFF
layer filldiff DIFFFILL
labels DIFFFILL
# Copy ndiff areas up for contact checks
templayer xndifcheck ndifcheck
copyup ndifcheck
templayer mvndiffarea DIFF
and-not POLY
and-not nwelldef
and-not PPLUS
and-not SBLK
and DUALGATE
and NPLUS
copyup mvndifcheck
templayer sramexpand SRAMDEF
grow 210
layer mvndiff mvndiffarea
and-not SRAMDEF
layer srammvndiff mvndiffarea
and SRAMDEF
layer sramndiff ndiffarea
and SRAMDEF
# Copy mvndiff areas up for contact checks
templayer mvxndifcheck mvndifcheck
copyup mvndifcheck
# Save cathode areas of Schottky diodes
templayer sccathode SCHOTTKY
and DIFF
and NPLUS
# Grow Schottky anode so that drawn device abuts
# the cathode.
layer schottky SCHOTTKY
and DIFF
and-not NPLUS
and-not PPLUS
or sccathode
grow 140
shrink 140
and-not sccathode
# Schottky contact
layer schottkyc SCHOTTKY
and CONT
and DIFF
and-not NPLUS
and-not PPLUS
grow 145
shrink 140
layer ndiode DIFF
and NPLUS
and DIODE
and-not nwelldef
and-not POLY
and-not PPLUS
and-not DUALGATE
and-not NAT
layer nndiode DIFF
and NPLUS
and DIODE
and-not nwelldef
and-not POLY
and-not PPLUS
and-not DUALGATE
and NAT
templayer ndiodearea DIODE
and NPLUS
and-not nwelldef
and-not DUALGATE
copyup DIODE,NPLUS
layer ndiffres DIFF
and-not POLY
and SBLK
and NPLUS
and-not DUALGATE
templayer pdiffarea DIFF
and-not POLY
and nwelldef
and-not NPLUS
and-not SBLK
and-not DIODE
and PPLUS
and-not DUALGATE
copyup pdifcheck
layer pdiff pdiffarea
layer mvndiode DIFF
and NPLUS
and DIODE
and-not POLY
and-not PPLUS
and DUALGATE
and-not NAT
layer mvnndiode DIFF
and NPLUS
and DIODE
and-not POLY
and-not PPLUS
and DUALGATE
and NAT
templayer mvndiodearea DIODE
and NPLUS
and-not nwelldef
and DUALGATE
copyup DIODE,NPLUS
layer mvndiffres DIFF
and-not POLY
and SBLK
and NPLUS
and DUALGATE
templayer mvpdiffarea DIFF
and-not POLY
and nwelldef
and-not NPLUS
and-not SBLK
and-not DIODE
and DUALGATE
and PPLUS
copyup mvpdifcheck
layer mvpdiff mvpdiffarea
# Copy pdiff areas up for contact checks
templayer xpdifcheck pdifcheck
copyup pdifcheck
layer pdiode DIFF
and PPLUS
and-not POLY
and-not NPLUS
and-not DUALGATE
and DIODE
templayer pdiodearea DIODE
and PPLUS
copyup DIODE,PPLUS
# Define pfet areas as known pdiff,
# regardless of the presence of a
# well.
templayer pfetarea DIFF
and-not NPLUS
and-not DUALGATE
and POLY
layer pfet pfetarea
and-not MOSCAP
and-not sramexpand
layer srampfet pfetarea
and-not MOSCAP
and sramexpand
layer pcap pfetarea
and MOSCAP
templayer pfetexpand pfetarea
grow 530
# Always force nwell under pfet
layer nwell pfetarea
grow 310
# Copy mvpdiff areas up for contact checks
templayer mvxpdifcheck mvpdifcheck
copyup mvpdifcheck
layer mvpdiode DIFF
and PPLUS
and-not POLY
and-not NPLUS
and-not RESDEF
and DUALGATE
and DIODE
templayer mvpdiodearea DIODE
and PPLUS
copyup DIODE,PPLUS
# Define pfet areas as known pdiff,
# regardless of the presence of a
# well.
templayer mvpfetarea DIFF
and DUALGATE
and-not NPLUS
and POLY
layer hvpfet mvpfetarea
and-not MOSCAP
and-not FET5VDEF
and-not sramexpand
layer mvpfet mvpfetarea
and-not MOSCAP
and FET5VDEF
and-not sramexpand
layer srammvpfet mvpfetarea
and-not MOSCAP
and sramexpand
layer mvpcap mvpfetarea
and MOSCAP
and-not sramexpand
templayer mvpfetexpand mvpfetarea
grow 520
layer pdiff DIFF
and-not DUALGATE
and-not NPLUS
and-not POLY
and nwelldef
and pfetexpand
and-not sramexpand
layer srampdiff DIFF
and-not DUALGATE
and-not NPLUS
and-not POLY
and nwelldef
and sramexpand
layer pdiffres DIFF
and-not POLY
and PPLUS
and nwelldef
and SBLK
layer nfet DIFF
and POLY
and-not PPLUS
and-not DUALGATE
and-not nwelldef
and NPLUS
and-not NAT
and-not MOSCAP
and-not sramexpand
layer sramnfet DIFF
and POLY
and-not PPLUS
and-not DUALGATE
and-not nwelldef
and NPLUS
and-not NAT
and-not MOSCAP
and sramexpand
layer ncap DIFF
and POLY
and-not PPLUS
and-not DUALGATE
and-not nwelldef
and NPLUS
and-not NAT
and MOSCAP
layer nnfet DIFF
and POLY
and-not PPLUS
and-not DUALGATE
and-not nwelldef
and NPLUS
and NAT
templayer nsdarea DIFF
and NPLUS
and nwelldef
and-not POLY
and-not PPLUS
and-not DUALGATE
layer nsd nsdarea
templayer nsdexpand nsdarea
grow 500
# Copy nsub areas up for contact checks
templayer xnsubcheck nsubcheck
copyup nsubcheck
templayer psdarea DIFF
and PPLUS
and-not DUALGATE
and-not nwelldef
and-not POLY
and-not NPLUS
and-not pfetexpand
copyup psubcheck
layer psd psdarea
templayer psdexpand psdarea
grow 500
layer mvpdiff DIFF
and-not NPLUS
and-not POLY
and nwelldef
and DUALGATE
and mvpfetexpand
and-not sramexpand
layer srammvpdiff DIFF
and-not NPLUS
and-not POLY
and nwelldef
and DUALGATE
and sramexpand
layer mvpdiffres DIFF
and-not POLY
and PPLUS
and SBLK
and DUALGATE
layer hvnfet DIFF
and POLY
and-not PPLUS
and NPLUS
and-not NAT
and-not nwelldef
and DUALGATE
and-not MOSCAP
and-not FET5VDEF
and-not sramexpand
layer mvnfet DIFF
and POLY
and-not PPLUS
and NPLUS
and-not NAT
and-not nwelldef
and DUALGATE
and-not MOSCAP
and FET5VDEF
and-not sramexpand
layer srammvnfet DIFF
and POLY
and-not PPLUS
and NPLUS
and-not NAT
and-not nwelldef
and DUALGATE
and-not MOSCAP
and sramexpand
layer mvncap DIFF
and POLY
and-not PPLUS
and NPLUS
and-not NAT
and-not nwelldef
and DUALGATE
and MOSCAP
layer mvnnfet DIFF
and POLY
and-not PPLUS
and NPLUS
and NAT
and-not nwelldef
and DUALGATE
templayer mvnsdarea DIFF
and NPLUS
and-not POLY
and-not PPLUS
and nwelldef
and DUALGATE
copyup mvnsubcheck
layer mvnsd mvnsdarea
templayer mvnsdexpand mvnsdarea
grow 500
# Copy nsub areas up for contact checks
templayer mvxnsubcheck mvnsubcheck
copyup mvnsubcheck
templayer mvpsdarea DIFF
and PPLUS
and-not nwelldef
and-not POLY
and-not NPLUS
and DUALGATE
and-not mvpfetexpand
copyup mvpsubcheck
layer mvpsd mvpsdarea
templayer mvpsdexpand mvpsdarea
grow 500
# Copy psub areas up for contact checks
templayer xpsubcheck psubcheck
copyup psubcheck
templayer mvxpsubcheck mvpsubcheck
copyup mvpsubcheck
layer psd DIFF
and-not PPLUS
and-not NPLUS
and-not POLY
and-not DUALGATE
and-not pfetexpand
and psdexpand
layer nsd DIFF
and-not PPLUS
and-not NPLUS
and-not POLY
and nwelldef
and-not DUALGATE
and nsdexpand
layer mvpsd DIFF
and-not PPLUS
and-not NPLUS
and-not POLY
and-not nwelldef
and DUALGATE
and-not mvpfetexpand
and mvpsdexpand
layer mvnsd DIFF
and-not PPLUS
and-not NPLUS
and-not POLY
and nwelldef
and DUALGATE
and mvnsdexpand
templayer polyarea POLY
and-not DIFF
and-not SBLK
and-not PLFUSE
#ifdef HRPOLY1K
and-not HRES
#endif (HRPOLY1K)
copyup polycheck
layer poly polyarea,POLYTXT
and-not RESDEF
labels POLY
labels POLYTXT text
layer fillpoly POLYFILL
labels POLYFILL
# Copy poly areas up for contact checks
templayer xpolycheck polycheck
copyup polycheck
layer rpps POLY
and-not SBLK
and PPLUS
and RESDEF
layer rnps POLY
and-not SBLK
and NPLUS
and RESDEF
layer rpp POLY
and SBLK
and PPLUS
#ifdef HRPOLY1K
and-not HRES
#endif (HRPOLY1K)
and RESDEF
# POLY + SBLK without RESDEF may be a salicide-blocked transistor.
# The SBLK will be regenerated on GDS output and the poly should be
# treated as regular poly.
layer poly POLY
and-not DIFF
and SBLK
and-not RESDEF
layer efuse POLY
and-not DIFF
and PLFUSE
layer rnp POLY
and SBLK
and NPLUS
and RESDEF
#ifdef HRPOLY1K
and-not HRES
#endif (HRPOLY1K)
#ifdef HRPOLY1K
layer hires POLY
and SBLK
and HRES
and RESDEF
and-not DUALGATE
layer mvhires POLY
and SBLK
and HRES
and RESDEF
and DUALGATE
# We define poly under HRES but not under SBLK to be plain poly
layer poly POLY
and HRES
and-not SBLK
and-not RESDEF
#endif (HRPOLY1K)
layer ndc CONT
and DIFF
and NPLUS
and-not nwelldef
and MET1
and-not DUALGATE
and-not DIODE
and-not sramexpand
grow 145
shrink 140
layer sramndc CONT
and DIFF
and NPLUS
and-not nwelldef
and MET1
and-not DUALGATE
and-not DIODE
and sramexpand
grow 145
shrink 140
layer nsc CONT
and DIFF
and NPLUS
and nwelldef
and MET1
and-not DUALGATE
and-not DIODE
grow 145
shrink 140
layer pdc CONT
and DIFF
and PPLUS
and nwelldef
and MET1
and-not DUALGATE
and-not DIODE
and-not sramexpand
grow 145
shrink 140
layer pdc CONT
and DIFF
and PPLUS
and MET1
and-not DUALGATE
and-not DIODE
and pfetexpand
and-not sramexpand
grow 145
shrink 140
layer srampdc CONT
and DIFF
and PPLUS
and MET1
and-not DUALGATE
and-not DIODE
and sramexpand
grow 145
shrink 140
layer psc CONT
and DIFF
and PPLUS
and-not nwelldef
and MET1
and-not DUALGATE
and-not DIODE
and-not pfetexpand
grow 145
shrink 140
layer pc CONT
and POLY
and-not DIFF
and MET1
grow 145
shrink 140
layer ndic CONT
and DIFF
and NPLUS
and DIODE
and-not POLY
and-not PPLUS
and-not DUALGATE
and-not NAT
grow 145
shrink 140
layer nndic CONT
and DIFF
and NPLUS
and DIODE
and-not POLY
and-not PPLUS
and-not DUALGATE
and NAT
grow 145
shrink 140
layer pdic CONT
and DIFF
and PPLUS
and DIODE
and-not POLY
and-not NPLUS
and-not DUALGATE
grow 145
shrink 140
layer mvndc CONT
and DIFF
and NPLUS
and-not nwelldef
and MET1
and DUALGATE
and-not DIODE
and-not sramexpand
grow 145
shrink 140
layer srammvndc CONT
and DIFF
and NPLUS
and-not nwelldef
and MET1
and DUALGATE
and-not DIODE
and sramexpand
grow 145
shrink 140
layer mvnsc CONT
and DIFF
and NPLUS
and MET1
and DUALGATE
and nwelldef
and-not DIODE
grow 145
shrink 140
layer mvpdc CONT
and DIFF
and PPLUS
and MET1
and DUALGATE
and nwelldef
and-not DIODE
and-not sramexpand
grow 145
shrink 140
layer mvpdc CONT
and DIFF
and PPLUS
and MET1
and DUALGATE
and-not DIODE
and mvpfetexpand
and-not sramexpand
grow 145
shrink 140
layer srammvpdc CONT
and DIFF
and PPLUS
and MET1
and DUALGATE
and nwelldef
and-not DIODE
and sramexpand
grow 145
shrink 140
layer mvpsc CONT
and DIFF
and PPLUS
and-not nwelldef
and MET1
and DUALGATE
and-not DIODE
and-not mvpfetexpand
grow 145
shrink 140
layer mvndic CONT
and DIFF
and NPLUS
and DIODE
and-not POLY
and-not PPLUS
and DUALGATE
and-not NAT
grow 145
shrink 140
layer mvnndic CONT
and DIFF
and NPLUS
and DIODE
and-not POLY
and-not PPLUS
and DUALGATE
and NAT
grow 145
shrink 140
layer mvpdic CONT
and DIFF
and PPLUS
and DIODE
and-not POLY
and-not NPLUS
and DUALGATE
grow 145
shrink 140
layer rm1 MET1
and RESDEF
and MET1RES
layer m1 MET1,MET1TXT
and-not MET1RES
labels MET1
labels MET1TXT port
layer obsm1 M1BLOCK
labels M1BLOCK
layer fillm1 M1FILL
labels M1FILL
layer m2c VIA1
grow 130
shrink 130
layer rm2 MET2
and RESDEF
and MET2RES
layer m2 MET2,MET2TXT
and-not MET2RES
labels MET2
labels MET2TXT port
layer obsm2 M2BLOCK
labels M2BLOCK
layer fillm2 M2FILL
labels M2FILL
#ifdef METALS3 || METALS4 || METALS5 || METALS6
layer rm3 MET3
and RESDEF
and MET3RES
#ifdef METALS3 && MIM
templayer mimarea CAPDEF
and MET3
#endif (METALS3 && MIM)
layer m3 MET3,MET3TXT
and-not MET3RES
labels MET3
labels MET3TXT port
layer obsm3 M3BLOCK
labels M3BLOCK
layer fillm3 M3FILL
labels M3FILL
layer m3c VIA2
#ifdef METALS3 && MIM
and-not CAPM
and-not mimarea
#endif (METALS3 && MIM)
grow 140
shrink 130
#ifdef METALS3 && MIM
layer mimcc VIA2
and MET3
and CAPM
and CAPDEF
grow 260
shrink 250
#endif (METALS3 && MIM)
#endif (METALS3 || METALS4 || METALS5 || METALS6)
#ifdef METALS4 || METALS5 || METALS6
layer rm4 MET4
and RESDEF
and MET4RES
#ifdef METALS4 && MIM
templayer mimarea CAPDEF
and MET3
#endif (METALS4 && MIM)
layer m4 MET4,MET4TXT
and-not MET4RES
labels MET4
labels MET4TXT port
layer obsm4 M4BLOCK
labels M4BLOCK
layer fillm4 M4FILL
labels M4FILL
layer via3 VIA3
#ifdef METALS4 && MIM
and-not CAPM
and-not mimarea
#endif (METALS4 && MIM)
grow 140
shrink 130
#ifdef METALS4 && MIM
layer mimcc VIA3
and MET4
and CAPM
and CAPDEF
grow 260
shrink 250
#endif (METALS4 && MIM)
#endif (METALS4 || METALS5 || METALS6)
#ifdef METALS5 || METALS6
layer rm5 MET5
and RESDEF
and MET5RES
#ifdef METALS5 && MIM
templayer mimarea CAPDEF
and MET4
#endif (METALS5 && MIM)
layer m5 MET5,MET5TXT
and-not MET5RES
labels MET5
labels MET5TXT port
layer obsm5 M5BLOCK
labels M5BLOCK
layer fillm5 M5FILL
labels M5FILL
layer via4 VIA4
#ifdef MIM && METALS5
and-not CAPM
and-not mimarea
#endif (MIM && METALS5)
grow 140
shrink 130
#ifdef METALS5 && MIM
layer mimcc VIA4
and MET5
and CAPM
and CAPDEF
grow 260
shrink 250
#endif (METALS5 && MIM)
#endif (METALS5 || METALS6)
#ifdef METALS6
layer rmtp METTP
and RESDEF
and METTPRES
layer mtp METTP,METTPTXT
and-not METTPRES
labels METTP
labels METTPTXT port
layer obsmtp MTPBLOCK
labels MTPBLOCK
layer fillmtp MTPFILL
labels MTPFILL
#ifdef MIM
templayer mimarea CAPDEF
and MET5
#endif (MIM)
layer viatp VIATP
and METTP
#ifdef MIM
and-not CAPM
and-not mimarea
#endif (MIM)
grow 5
grow 265
shrink 265
#ifdef MIM
layer mimcc VIATP
and METTP
and CAPM
and CAPDEF
grow 260
shrink 250
#endif (MIM)
#endif (METALS6)
#ifdef MIM
layer mimcap CAPM
and CAPDEF
labels CAPM
templayer nolayer CAP_LENGTH
#endif (MIM)
# Find diffusion not covered in
# NPLUS or PPLUS and pull it into
# the next layer up
templayer gentrans DIFF
and-not PPLUS
and-not NPLUS
and POLY
copyup DIFF,POLY
templayer gendiff DIFF
and-not PPLUS
and-not NPLUS
and-not POLY
copyup DIFF
# Handle contacts found by copyup
layer ndic CONT
and MET1
and DIODE
and NPLUS
and-not DUALGATE
and-not NAT
grow 100
shrink 100
layer mvndic CONT
and MET1
and DIODE
and NPLUS
and DUALGATE
and-not NAT
grow 100
shrink 100
layer mvnndic CONT
and MET1
and DIODE
and NPLUS
and DUALGATE
and NAT
grow 100
shrink 100
layer pdic CONT
and MET1
and DIODE
and PPLUS
and-not DUALGATE
grow 100
shrink 100
layer mvpdic CONT
and MET1
and DIODE
and PPLUS
and DUALGATE
grow 100
shrink 100
layer ndc CONT
and ndifcheck
grow 100
shrink 100
layer mvndc CONT
and mvndifcheck
grow 100
shrink 100
layer pdc CONT
and pdifcheck
grow 100
shrink 100
layer mvpdc CONT
and mvpdifcheck
grow 100
shrink 100
layer pc CONT
and polycheck
grow 100
shrink 100
layer nsc CONT
and nsubcheck
grow 100
shrink 100
layer mvnsc CONT
and mvnsubcheck
grow 100
shrink 100
layer psc CONT
and psubcheck
grow 100
shrink 100
layer mvpsc CONT
and mvpsubcheck
grow 100
shrink 100
# Find contacts not covered in
# metal and pull them into the
# next layer up
templayer gencont CONT
and MET1
and-not DIFF
and-not POLY
and-not DIODE
and-not nsubcheck
and-not psubcheck
and-not mvnsubcheck
and-not mvpsubcheck
copyup CONT,MET1
templayer barecont CONT
and-not MET1
and-not nsubcheck
and-not psubcheck
and-not mvnsubcheck
and-not mvpsubcheck
copyup CONT
layer glass GLASS
labels GLASS
templayer cellbound BOUND,PRBOUND
boundary
layer lvstext TTEXT
labels TTEXT text
# layer fillblock FILLOBS,FILLOBS2
layer fillblock FILLOBS2
labels FILLOBS2
# MOS Varactors
layer nvar POLY
and DIFF
and NPLUS
and nwelldef
and-not DUALGATE
layer mvnvar POLY
and DIFF
and NPLUS
and nwelldef
and DUALGATE
layer pvar POLY
and DIFF
and PPLUS
and-not nwelldef
and-not DUALGATE
layer mvpvar POLY
and DIFF
and PPLUS
and-not nwelldef
and DUALGATE
calma DNWELL 12 0
calma NWELL 21 0
calma NWELLTXT 21 10
calma PWELL 204 0
calma PWELLTXT 204 10
calma SUBCUT 23 5
calma DIFF 22 0
calma DIFFFILL 22 4
calma POLY 30 0
calma POLYFILL 30 4
calma POLYTXT 30 10
calma NPLUS 32 0
calma PPLUS 31 0
calma SBLK 49 0
calma GLASS 37 0
calma CONT 33 0
calma MET1 34 0
calma MET1TXT 34 10
calma M1BLOCK 34 5
calma M1FILL 34 4
calma MET2RES 110 11
calma VIA1 35 0
calma MET2 36 0
calma MET2TXT 36 10
calma M2BLOCK 36 5
calma M2FILL 36 4
calma MET2RES 110 12
#ifdef METALS3 || METALS4 || METALS5 || METALS6
calma VIA2 38 0
calma MET3 42 0
calma MET3TXT 42 10
calma M3BLOCK 42 5
calma M3FILL 42 4
calma MET3RES 110 13
#endif (METALS3 || METALS4 || METALS5 || METALS6)
#ifdef METALS4 || METALS5 || METALS6
calma VIA3 40 0
calma MET4 46 0
calma MET4TXT 46 10
calma M4BLOCK 46 5
calma M4FILL 46 4
calma MET4RES 110 14
#endif (METALS4 || METALS5 || METALS6)
#ifdef METALS5 || METALS6
calma VIA4 41 0
calma MET5 81 0
calma MET5TXT 81 10
calma M5BLOCK 81 5
calma M5FILL 81 4
calma MET5RES 110 15
#endif (METALS5 || METALS6)
#ifdef METALS6
calma VIATP 129 0
calma METTP 53 0
calma METTPTXT 53 10
calma MTPBLOCK 53 5
calma METTPRES 110 16
#endif (METALS6)
#ifdef HRPOLY1K
calma HRES 62 0
#endif (HRPOLY1K)
calma EFUSE 80 5
calma PLFUSE 125 5
calma SOURCE 100 8
calma NAT 5 0
#ifdef MIM
calma CAPM 75 0
calma CAP_LENGTH 117 10
#endif (MIM)
calma DIODE 115 5
calma SCHOTTKY 241 0
calma CAPDEF 117 5
calma BJTDEF 118 5
calma BJTDRC 127 5
calma MOSCAP 166 5
calma BOUND 0 0
calma PRBOUND 63 0
calma VTEXT 63 63
calma FILLOBS 111 5
calma FILLOBS2 152 5
calma TTEXT 230 *
calma RESDEF 110 *
calma DUALGATE 55 0
calma SRAMDEF 108 5
calma FET5VDEF 112 1
calma SCRIBE 167 5
calma LATCHUP_ID 137 5
calma IO_ID 119 5
calma ESD_ID 24 5
end
#-----------------------------------------------------
# Digital flow maze router cost parameters
#-----------------------------------------------------
mzrouter
end
#-----------------------------------------------------
# Vendor DRC rules
#-----------------------------------------------------
drc
style drc variants (fast),(full),(routing)
scalefactor 50
cifstyle drc
variants (fast),(full)
#-----------------------------
# NWELL
#-----------------------------
width allnwell 860 "N-well width < %d (NW.1a)"
spacing allnwell allnwell 600 touching_ok "N-well spacing < %d (NW.2a)"
# rnw spacing is to unrelated nwell only.
spacing rnw allnwell 1400 touching_ok "N-well resistor spacing < %d (NW.2b)"
width rnw 2000 "N-well resistor width < %d (NW.1b)"
variants (full)
cifspacing mv_nwell mv_nwell 740 touching_ok "MV N-well spacing < %d (NW.2a)"
variants *
#-----------------------------
# DNWELL (deep nwell)
#-----------------------------
width dnwell 1700 "Deep N-well width < %d (DN.1)"
spacing dnwell dnwell 2500 touching_ok "Deep N-well spacing < %d (DN.2a)"
surround pwell dnwell 2500 absence_ok \
"Deep N-well surround P-well < %d (LPW.3)"
surround nwell dnwell 500 absence_ok \
"Deep N-well surround N-well < %d (NW.5)"
variants (full)
cifwidth pwell_in_dnwell 600 "P-well in deep N-well size < %d (LPW.1)"
cifwidth mvpwell_in_dnwell 740 "HV P-well in deep N-well size < %d (LPW.1)"
cifspacing pwell_in_dnwell pwell_in_dnwell 860 touching_ok \
"P-well in deep N-well spacing < %d (LPW.2b)"
cifspacing mvpwell_in_dnwell mvpwell_in_dnwell 860 touching_ok \
"MV P-well in deep N-well spacing < %d (LPW.2b)"
cifmaxwidth bad_dnwell 0 bend_illegal \
"Both LV and MV devices cannot be in the same deep N-well (DN.11)"
cifmaxwidth bad_nwell 0 bend_illegal \
"Both LV and MV devices cannot be in the same N-well (DV.9)"
cifmaxwidth bad_rnw 0 bend_illegal \
"N-well resistor cannot be in deep N-well (DN.12)"
variants *
spacing dnwell allnwell 3100 surround_ok \
"Deep N-well spacing to N-well < %d (NW.3)"
spacing pwell dnwell 1500 surround_ok \
"Deep N-well spacing to P-well < %d (LPW.11)"
#-----------------------------
# DIFF (diffusion)
#-----------------------------
width alldifflv 220 "Diffusion width < %d (DF.1a)"
width alldiffmv 300 "Diffusion width < %d (DF.1a)"
area alldifflv 202500 220 "Diffusion minimum area < %a (DF.9)"
area alldiffmv 202500 300 "Diffusion minimum area < %a (DF.9)"
spacing alldifflv,nvar,pvar alldifflv,nvar,pvar 280 touching_ok \
"Diffusion spacing < %d (DF.3a)"
spacing alldiffmv,mvnvar,mvpvar alldiffmv,mvnvar,mvpvar 360 touching_ok \
"Diffusion spacing < %d (DF.3a)"
spacing *mvpdiff,mvpvar,*srammvpdiff *mvnsd 360 touching_illegal \
"Diffusion spacing to tap < %d (DF.3a)"
spacing *mvndiff,mvnvar,*srammvndiff *mvpsd 360 touching_illegal \
"Diffusion spacing to tap < %d (DF.3a)"
# Low voltage tap to high voltage diffusion has to clear DUALGATE-to-COMP spacing
spacing *mvpdiff,mvpvar,*srammvpdiff *nsd 480 touching_illegal \
"5/6V Diffusion spacing to 3.3V tap < %d (DV.6 + DV.3)"
spacing *mvndiff,mvnvar,*srammvndiff *psd 480 touching_illegal \
"5/6V Diffusion spacing to 3.3V tap < %d (DV.6 + DV.3)"
spacing (*ndiff,*ndiode,nfet,nnfet,ncap)/a allnwell 430 touching_illegal \
"N-Diffusion spacing to N-well < %d (DF.8)"
spacing (*mvndiff,*mvndiode,hvnfet,mvnfet,mvncap,mvnnfet)/a allnwell 600 touching_illegal \
"N-Diffusion spacing to N-well < %d (DF.8)"
spacing *srammvndiff,srammvnfet allnwell 450 touching_illegal \
"N-Diffusion spacing to N-well in 5V SRAM < %d (S.DF.8_MV)"
spacing *sramndiff,sramnfet allnwell 400 touching_illegal \
"N-Diffusion spacing to N-well in 3.3V SRAM < %d (S.DF.16_LV)"
spacing *psd allnwell 120 touching_illegal \
"P-Ohmic spacing to N-well < %d (DF.5)"
spacing *mvpsd allnwell 160 touching_illegal \
"P-Ohmic spacing to N-well < %d (DF.5)"
# NWELL and DNWELL are interchangeable under devices.
surround *nsd allnwell 120 absence_okay \
"N-well overlap of N-Ohmic < %d (DF.4a)"
surround *mvnsd allnwell 160 absence_okay \
"N-well overlap of N-Ohmic < %d (DF.4a)"
surround *pdiff,*pdiode,pfet,pcap allnwell 430 absence_okay \
"N-well overlap of P-Diffusion < %d (DF.7)"
surround *mvpdiff,*mvpdiode,hvpfet,mvpfet,mvpcap allnwell 600 absence_okay \
"N-well overlap of P-Diffusion < %d (DF.7)"
surround srammvpfet allnwell 450 absence_okay \
"N-well overlap of P-Diffusion in 5V SRAM < %d (S.DF.7_MV)"
surround srampfet allnwell 400 absence_okay \
"N-well overlap of P-Diffusion in 3.3V SRAM < %d (S.DF.4c_LV)"
surround *nsd dnwell 620 absence_okay \
"Deep N-well overlap of N-Ohmic < %d (DF.4b)"
surround *mvnsd dnwell 660 absence_okay \
"Deep N-well overlap of N-Ohmic < %d (DF.4b)"
surround *pdiff,*pdiode,pfet,pcap dnwell 930 absence_okay \
"Deep N-well overlap of P-Diffusion < %d (DF.4e)"
surround *mvpdiff,*mvpdiode,hvpfet,mvpfet,mvpcap dnwell 1100 absence_okay \
"Deep N-well overlap of P-Diffusion < %d (DF.4e)"
variants (full)
# Use CIF-DRC rule to ensure that at least one exists.
cifmaxwidth missing_nwell 0 bend_illegal \
"P-diffusion and N-ohmic must be over N-well or deep N-well"
# Use CIF-DRC rules to ensure where pwell must be inside dnwell
cifmaxwidth pohmic_missing_pwell 0 bend_illegal \
"P-well must surround P-ohmic in deep N-well by 0.12um (DF.5)"
cifmaxwidth mvpohmic_missing_pwell 0 bend_illegal \
"P-well must surround MV P-ohmic in deep N-well by 0.16um (DF.5)"
cifmaxwidth ndiff_missing_pwell 0 bend_illegal \
"P-well must surround N-diffusion inside deep N-well by 0.43um (DF.8)"
cifmaxwidth mvndiff_missing_pwell 0 bend_illegal \
"P-well must surround MV N-diffusion inside deep N-well by 0.60um (DF.8)"
cifarea check_pplus 350000 400 "Minimum PPLUS area >= %a (PP.8a)"
cifarea check_nplus 350000 400 "Minimum NPLUS area >= %a (NP.8a)"
variants *
# surround *psd pwell 120 absence_ok \
# "P-well overlap of P-Ohmic < %d (DF.5)"
# surround *mvpsd pwell 160 absence_ok \
# "MV P-well overlap of MV P-Ohmic < %d (DF.5)"
# NAT requires additional spacing rules
spacing *nndiode,*mvnndiode *psd,*mvpsd 610 touching_illegal \
"NAT Diffusion spacing to TAP diffusion < %d (NAT.5 + NAT.6)"
#-----------------------------
# POLY
#-----------------------------
width allpoly 180 "Poly width < %d (PL.1)"
width fillpoly 5600 "Poly fill width < %d (DPF.1)"
spacing allpoly allpoly 240 touching_ok "Poly spacing < %d (PL.3a)"
spacing allpoly fillpoly 5000 touching_illegal "Poly fill spacing to poly < %d (DPF.5)"
edge4way fillpoly space/poly 2400 ~(fillpoly)/poly 0 0 \
"Lateral spacing between poly fill shapes < %d (DPF.2a)"
spacing fillpoly fillpoly 1100 touching_ok "Poly fill spacing < %d (DPF.2b)"
spacing allpolynonfet alldifflvnonfet 100 corner_ok allfets \
"Poly spacing to diffusion < %d (PL.5a)"
# NOTE: Below, 2nd argument was alldiffmvnonfet, but needs to exclude sram diffusion.
spacing allpolynonfet \
*mvndif,*mvnsd,*mvndiode,mvndiffres,*mvnndiode,*ldndiff,*mvpdif,*mvpsd,*mvpdiode,mvpdiffres,*ldpdiff \
300 corner_ok allfets "Poly spacing to MV diffusion < %d (PL.5a)"
spacing allpolynonfet *srammvndiff 120 corner_ok allfets \
"Poly spacing to MV diffusion in SRAM < %d (S.PL.5a_MV)"
overhang *ndiff,rndiff nfet,nnfet,ncap 230 "N-Diffusion overhang of nmos < %d (DF.6)"
overhang *mvndiff,mvrndiff hvnfet,mvnfet,mvncap,mvnnfet 230 \
"N-Diffusion overhang of nmos < %d (DF.6)"
overhang *srammvndiff srammvnfet 230 \
"N-Diffusion overhang of nmos < %d (DF.6)"
overhang *pdiff,rpdiff pfet,pcap 230 "P-Diffusion overhang of pmos < %d (DF.6)"
overhang *mvpdiff,mvrpdiff hvpfet,mvpfet,mvpcap 230 "P-Diffusion overhang of pmos < %d (DF.6)"
overhang *srammvpdiff srammvpfet 230 "P-Diffusion overhang of pmos < %d (DF.6)"
overhang *poly allfetsnonnat 220 "Poly overhang of transistor < %d (PL.4)"
overhang *poly nnfet,mvnnfet 350 "Poly overhang of NAT transistor < %d (NAT.6)"
angles allfets 45-only "Only 45 degrees allowed on transistors (PL.6)"
#-----------------------------------------------------------------------------
# SBLK - more rules to do here (note PRES refers only to unsalicided resistor)
#-----------------------------------------------------------------------------
spacing allpolysblkres allpolysblkres 400 touching_ok \
"Poly resistor spacing < %d (PRES/LRES.2)"
spacing allpolysblkres allpolynonres 600 touching_ok \
"Poly resistor spacing to unrelated poly < %d (PRES/LRES.4)"
spacing allpolysblkres allactive,allactiveres 600 touching_illegal \
"Poly resistor spacing to diffusion < %d (PRES/LRES.3)"
spacing allactiveres allactiveres 400 touching_ok \
"Diffusion resistor spacing < %d (NDRES.2)"
spacing allactiveres allactive 440 touching_ok \
"Diffusion resistor spacing to unrelated diffusion < %d (NDRES.3)"
spacing allactiveres allpoly 430 touching_ok \
"Diffusion resistor spacing to unrelated poly < %d (NDRES.4)"
#-----------------------------
# CONT
#-----------------------------
# Drawn contact includes 5nm metal1 surround
width (ndc,nsc,pdc,psc,ndic,pdic,pc)/m1 230 \
"Diffusion contact width < %d (CO.1 + 2 * CO.6)"
spacing (ndc,nsc,pdc,psc,ndic,pdic,pc)/m1 \
(ndc,nsc,pdc,psc,ndic,pdic,pc)/m1 240 \
touching_ok "Diffusion contact spacing < %d (CO.2a - 2 * CO.6)"
surround (ndc,nsc,pdc,psc,ndic,pdic,pc)/m1 *m1 55 35 \
directional "Metal1 overlap of contact < %d in one direction (CO.6)"
surround ndc/a *ndiff 65 absence_illegal \
"N-Diffusion overlap of contact < %d (CO.4)"
surround nsc/a *nsd 65 absence_illegal \
"N-Diffusion overlap of contact < %d (CO.4)"
surround pdc/a *pdiff 65 absence_illegal \
"P-Diffusion overlap of contact < %d (CO.4)"
surround psc/a *psd 65 absence_illegal \
"P-Diffusion overlap of contact < %d (CO.4)"
surround ndic/a *ndiode 65 absence_illegal \
"N-Diffusion overlap of contact < %d (CO.4)"
surround pdic/a *pdiode 65 absence_illegal \
"P-Diffusion overlap of contact < %d (CO.4)"
surround pc/a *poly 65 absence_illegal "Poly overlap of contact < %d (CO.3)"
width (mvndc,mvnsc,mvpdc,mvpsc,mvndic,mvnndic,mvpdic)/m1 230 \
"MV Diffusion contact width < %d (CO.1 + 2 * CO.6)"
spacing (mvndc,mvnsc,mvpdc,mvpsc,mvndic,mvnndic,mvpdic)/m1 \
(mvndc,mvnsc,mvpdc,mvpsc,mvndic,mvnndic,mvpdic)/m1 240 touching_ok \
"Diffusion contact spacing < %d (CO.2a - 2 * CO.6)"
surround (mvndc,mvnsc,mvpdc,mvpsc,mvndic,mvnndic,mvpdic)/m1 *m1 55 35 directional \
"Metal1 overlap of contact < %d in one direction (CO.6)"
surround mvndc/a *mvndiff 65 absence_illegal \
"MV N-Diffusion overlap of contact < %d (CO.4)"
surround mvnsc/a *mvnsd 65 absence_illegal \
"MV N-Diffusion overlap of contact < %d (CO.4)"
surround mvpdc/a *mvpdiff 65 absence_illegal \
"MV P-Diffusion overlap of contact < %d (CO.4)"
surround mvpsc/a *mvpsd 65 absence_illegal \
"MV P-Diffusion overlap of contact < %d (CO.4)"
surround mvndic/a *mvndiode 65 absence_illegal \
"MV N-Diffusion overlap of contact < %d (CO.4)"
surround mvnndic/a *mvnndiode 65 absence_illegal \
"MV NAT N-Diffusion overlap of contact < %d (CO.4)"
surround mvpdic/a *mvpdiode 65 absence_illegal \
"MV P-Diffusion overlap of contact < %d (CO.4)"
surround srammvndc *srammvndiff 35 absence_illegal \
"MV N-Diffusion overlap of contact in 5V SRAM < %d (S.CO.4_MV)"
surround srammvpdc/a *srammvpdiff 35 absence_illegal \
"MV P-Diffusion overlap of contact in 5V SRAM < %d (S.CO.4_MV)"
surround sramndc *sramndiff 35 absence_illegal \
"MV N-Diffusion overlap of contact in 3.3V SRAM < %d (S.CO.3_LV)"
surround srampdc/a *srampdiff 35 absence_illegal \
"MV P-Diffusion overlap of contact in 3.3V SRAM < %d (S.CO.3_LV)"
spacing allpdiffcont allndiffcont 240 touching_illegal \
"Diffusion contact spacing < %d (CO.2a - 2 * CO.6)"
spacing allndiffcont allndiffcont 240 touching_ok \
"Diffusion contact spacing < %d (CO.2a - 2 * CO.6)"
spacing allpdiffcont allpdiffcont 240 touching_ok \
"Diffusion contact spacing < %d (CO.2a - 2 * CO.6)"
spacing pc pc 240 touching_ok "Poly contact spacing < %d (CO.2a - 2 * CO.6)"
spacing pc alldiff 165 touching_illegal \
"Poly contact spacing to diffusion < %d (CO.8 - 2 * CO.6)"
spacing allpdiffcont,allndiffcont allpoly 145 touching_illegal \
"Diffusion contact spacing to poly < %d (CO.7 - 2 * CO.6)"
exact_overlap (ndc,pdc,psc,nsc,pc,ndic,pdic)/a
exact_overlap (mvndc,mvpdc,mvpsc,mvnsc,mvndic,mvnndic,mvpdic)/a
exact_overlap (srammvndc,srammvpdc)/a
exact_overlap (sramndc,srampdc)/a
variants *
#-----------------------------
# METAL 1
#-----------------------------
width *m1,rm1 230 "Metal1 width < %d (M1.1)"
spacing allm1,obsm1 allm1,obsm1 230 touching_ok "Metal1 spacing < %d (M1.2a)"
area allm1,obsm1 144400 230 "Metal1 minimum area < %a (M1.3)"
variants (fast),(full)
widespacing allm1,obsm1 10005 allm1,obsm1 300 touching_ok \
"Metal1 > 10um spacing to unrelated m1 < %d (M1.2b)"
variants *
#--------------------------------------------------
# VIA 1
#--------------------------------------------------
width v1/m1 260 "Via1 width < %d (V1.1)"
spacing v1 v1 260 touching_ok "Via1 spacing < %d (V1.2a)"
surround v1/m1 *m1 60 40 directional \
"Metal1 overlap of Via1 < %d in one direction (V1.3)"
surround v1/m2 *m2 10 absence_illegal \
"Metal2 overlap of Via1 < %d (V1.4)"
surround v1/m2 *m2 60 40 directional \
"Metal2 overlap of Via1 < %d in one direction (V1.4i)"
exact_overlap v1/m2
#-----------------------------
# METAL 2
#-----------------------------
width *m2,rm2 280 "Metal2 width < %d (M2.1)"
spacing allm2,obsm2 allm2,obsm2 280 touching_ok "Metal2 spacing < %d (M2.2a)"
area allm2,obsm2 144400 280 "Metal2 minimum area < %a (M2.3)"
variants (fast),(full)
widespacing allm2,obsm2 10005 allm2,obsm2 300 touching_ok \
"Metal2 > 10um spacing to unrelated m2 < %d (M2.2b)"
variants *
#ifdef METALS3 || METALS4 || METALS5 || METALS6
#--------------------------------------------------
# VIA 2
#--------------------------------------------------
width v2/m2 280 "Via2 width < %d (V2.1 + 2 * V2.3)"
spacing v2 v2 240 touching_ok "Via2 spacing < %d (V2.2a - 2 * V2.3)"
surround v2/m2 *m2 50 30 directional \
"Metal2 overlap of Via2 < %d in one direction (V2.3i - V2.3)"
exact_overlap v2/m3
#-----------------------------
# METAL 3
#-----------------------------
#ifdef METALS3
# Metal 3 is the top metal
#ifdef THICKMET3P0
width *m3,rm3 1800 "Thick Metal3 width < %d (MT30.1)"
spacing allm3,obsm3 allm3,obsm3 1800 touching_ok \
"Thick Metal3 spacing < %d (MT30.2)"
surround v2/m3 *m3 110 absence_illegal \
"Thick Metal3 overlap of Via2 < %d (MT30.5 - V2.4)"
surround v2/m3 *m3 240 directional \
"Thick Metal3 overlap of Via2 < %d in one direction (MT30.6 - V2.4)"
#elseif THICKMET0P9 || THICKMET1P1
surround v2/m3 *m3 50 30 directional \
"Metal3 overlap of Via2 < %d in one direction (V2.4i - V2.4)"
width *m3,rm3 440 "Metal3 width < %d (MT.1)"
spacing allm3,obsm3 allm3,obsm3 460 touching_ok "Metal3 spacing < %d (MT.2a)"
area allm3,obsm3 562500 440 "Metal3 minimum area < %a (MT.4)"
variants (fast),(full)
widespacing allm3,obsm3 10005 allm3,obsm3 600 touching_ok \
"Metal3 > %c spacing to unrelated m3 < %d (MT.2b)"
#else (!(THICKMET3P0 || THICKMET0P9 || THICKMET1P1))
surround v2/m3 *m3 50 30 directional \
"Metal3 overlap of Via2 < %d in one direction (V2.4i - V2.4)"
width *m3,rm3 360 "Metal3 width < %d (MT.1)"
spacing allm3,obsm3 allm3,obsm3 380 touching_ok "Metal3 spacing < %d (MT.2a)"
area allm3,obsm3 562500 360 "Metal3 minimum area < %a (MT.4)"
variants (fast),(full)
widespacing allm3,obsm3 10005 allm3,obsm3 500 touching_ok \
"Metal3 > %c spacing to unrelated m3 < %d (MT.2b)"
#endif (!(THICK3UMET || THICKMET1P1 || THICKMET0P9))
#else (!METALS3)
surround v2/m3 *m3 50 30 directional \
"Metal3 overlap of Via2 < %d in one direction (V2.4i - V2.4)"
width *m3,rm3 280 "Metal3 width < %d (M3.1)"
spacing allm3,obsm3 allm3,obsm3 280 touching_ok "Metal3 spacing < %d (M3.2a)"
area allm3,obsm3 144400 280 "Metal3 minimum area < %a (M3.3)"
variants (fast),(full)
widespacing allm3,obsm3 10005 allm3,obsm3 300 touching_ok \
"Metal3 > %c spacing to unrelated m3 < %d (M3.2b)"
#endif (!METALS3)
variants *
#endif (METALS3 || METALS4 || METALS5 || METALS6)
#ifdef METALS4 || METALS5 || METALS6
#--------------------------------------------------------------
# VIA 3 - Requires METAL4, METAL5, or METAL6 Module
#--------------------------------------------------------------
width v3/m3 280 "Via3 width < %d (V3.1 + 2 * V3.4)"
spacing v3 v3 240 touching_ok "Via3 spacing < %d (V3.2a - 2 * V3.4)"
surround v3/m3 *m3 50 30 directional \
"Metal3 overlap of Via3 < %d in one direction (V3.3i - V3.3)"
exact_overlap v3/m4
#-----------------------------
# METAL 4 - METAL4 Module
#-----------------------------
#ifdef METALS4
# Metal 4 is the top metal
#ifdef THICKMET3P0
width *m4,rm4 1800 "Thick Metal4 width < %d (MT30.1)"
spacing allm4,obsm4 allm4,obsm4 1800 touching_ok "Metal4 spacing < %d (MT30.2)"
surround v3/m4 *m4 110 absence_illegal \
"Thick Metal4 overlap of Via3 < %d (MT30.5 - V3.4)"
surround v3/m4 *m4 240 directional \
"Thick Metal4 overlap of Via3 < %d in one direction (MT30.6 - V3.4)"
#elseif THICKMET0P9 || THICKMET1P1
surround v3/m4 *m4 50 30 directional \
"Metal4 overlap of Via3 < %d in one direction (V3.4i - V3.4)"
width *m4,rm4 440 "Metal4 width < %d (MT.1)"
spacing allm4,obsm4 allm4,obsm4 460 touching_ok "Metal4 spacing < %d (MT.2a)"
area allm4,obsm4 562500 440 "Metal4 minimum area < %a (MT.4)"
variants (fast),(full)
widespacing allm4,obsm4 10005 allm4,obsm4 600 touching_ok \
"Metal4 > %c spacing to unrelated m4 < %d (MT.2b)"
#else (!(THICK3UMET || THICKMET1P1 || THICKMET0P9))
surround v3/m4 *m4 50 30 directional \
"Metal4 overlap of Via3 < %d in one direction (V3.4i - V3.4)"
width *m4,rm4 360 "Metal4 width < %d (MT.1)"
spacing allm4,obsm4 allm4,obsm4 380 touching_ok "Metal4 spacing < %d (MT.2a)"
area allm4,obsm4 562500 360 "Metal4 minimum area < %a (MT.4)"
variants (fast),(full)
widespacing allm4,obsm4 10005 allm4,obsm4 500 touching_ok \
"Metal4 > %c spacing to unrelated m4 < %d (MT.2b)"
#endif (!(THICK3UMET || THICKMET1P1 || THICKMET0P9))
#else (!METALS4)
surround v3/m4 *m4 50 30 directional \
"Metal4 overlap of Via3 < %d in one direction (V3.4i - V3.4)"
width *m4,rm4 230 "Metal4 width < %d (M4.1)"
spacing allm4,obsm4 allm4,obsm4 280 touching_ok "Metal4 spacing < %d (M4.2a)"
area allm4,obsm4 144000 230 "Metal4 minimum area < %a (M4.3)"
variants (fast),(full)
widespacing allm4,obsm4 10005 allm4,obsm4 300 touching_ok \
"Metal4 > %c spacing to unrelated m4 < %d (M4.2b)"
#endif (!METALS4)
variants *
#endif (METALS4 || METALS5 || METALS6)
#ifdef METALS5 || METALS6
#------------------------------------------------------
# VIA 4 - Requires METAL5 Module
#------------------------------------------------------
width v4/m4 280 "Via4 width < %d (V4.1 + 2 * V4.4)"
spacing v4 v4 240 touching_ok "Via4 spacing < %d (V4.2a - 2 * V4.4)"
exact_overlap v4/m5
#-----------------------------
# METAL 5 - METAL5 Module
#-----------------------------
#ifdef METALS5
# Metal 5 is the top metal
#ifdef THICKMET3P0
width *m5,rm5 1800 "Metal5 width < %d (MT30.1)"
spacing allm5,obsm5 allm5,obsm5 1800 touching_ok "Metal5 spacing < %d (MT30.2)"
surround v4/m5 *m5 110 absence_illegal \
"Metal5 overlap of Via4 < %d (MT30.5 - V4.4)"
surround v4/m5 *m5 240 directional \
"Metal5 overlap of Via4 < %d in one direction (MT30.6 - V4.4)"
#elseif THICKMET0P9 || THICKMET1P1
surround v4/m4 *m4 50 30 directional \
"Metal4 overlap of Via4 < %d in one direction (V4.3i - V4.3)"
surround v4/m5 *m5 50 30 directional \
"Metal5 overlap of Via4 < %d in one direction (V4.4i - V4.4)"
width *m5,rm5 440 "Metal5 width < %d (MT.1)"
spacing allm5,obsm5 allm5,obsm5 460 touching_ok "Metal5 spacing < %d (MT.2a)"
area allm5,obsm5 526500 440 "Metal5 minimum area < %a (MT.4)"
variants (fast),(full)
widespacing allm5,obsm5 10005 allm5,obsm5 600 touching_ok \
"Metal5 > %c spacing to unrelated m5 < %d (MT.2b)"
#else (!(THICK3UMET || THICKMET1P1 || THICKMET0P9))
surround v4/m4 *m4 50 30 directional \
"Metal4 overlap of Via4 < %d in one direction (V4.3i - V4.3)"
surround v4/m5 *m5 50 30 directional \
"Metal5 overlap of Via4 < %d in one direction (V4.4i - V4.4)"
width *m5,rm5 360 "Metal5 width < %d (MT.1)"
spacing allm5,obsm5 allm5,obsm5 380 touching_ok "Metal5 spacing < %d (MT.2a)"
area allm5,obsm5 562500 360 "Metal5 minimum area < %a (MT.4)"
variants (fast),(full)
widespacing allm5,obsm5 10005 allm5,obsm5 500 touching_ok \
"Metal5 > %c spacing to unrelated m5 < %d (MT.2b)"
#endif (!(THICK3UMET || THICKMET1P1 || THICKMET0P9))
#else (!METALS5)
surround v4/m4 *m4 50 30 directional \
"Metal4 overlap of Via4 < %d in one direction (V4.3i - V4.3)"
surround v4/m5 *m5 50 30 directional \
"Metal5 overlap of Via4 < %d in one direction (V4.4i - V4.4)"
width *m5,rm5 230 "Metal5 width < %d (M5.1)"
spacing allm5,obsm5 allm5,obsm5 280 touching_ok "Metal5 spacing < %d (M5.2a)"
area allm5,obsm5 144000 230 "Metal5 minimum area < %a (M5.3)"
variants (fast),(full)
widespacing allm5,obsm5 10005 allm5,obsm5 300 touching_ok \
"Metal5 > %c spacing to unrelated m5 < %d (M5.2b)"
#endif (!METALS5)
variants *
#endif (METALS5 || METALS6)
#ifdef METALS6
#-----------------------------------------------------------------------------------
# VIA TP - Requires METAL6 Module
#-----------------------------------------------------------------------------------
spacing vtp vtp 340 touching_ok "ViaTP spacing < %d (VT.2a - VT.3)"
width vtp/m5 370 "ViaTP width < %d (VT.1+VT.3)"
surround vtp/m5 *m5 45 directional \
"Metal 5 overlap of ViaTP in one direction < %d (VT.3)"
exact_overlap vtp/m5
#----------------------------------------------------------------------
# METAL TP - Top metal for METAL6 module
#----------------------------------------------------------------------
variants *
# Metal TP is the top metal
#ifdef THICKMET3P0
width allmtp 1800 "Thick Top Metal width < %d (MT30.1)"
spacing allmtp,obsmtp allmtk,obsmtk 1800 touching_ok\
"Thick Top Metal spacing < %d (MT30.2a)"
surround vtp/mtp *mtp 110 absence_illegal \
"Thick Top Metal overlap of ViaTP < %d (MT30.5 - VTP.4)"
surround vtp/mtp *mtp 240 directional \
"Thick Top Metal overlap of ViaTP < %d in one direction (MT30.6 - VTP.4)"
#elseif THICKMET0P9 || THICKMET1P1
surround vtp/mtp *mtp 80 absence_illegal \
"Top Metal overlap of ViaTP < %d (VT.4 - VT.3)"
width allmtp 440 "Top Metal width < %d (MT.1)"
spacing allmtp,obsmtp allmtp,obsmtp 460 touching_ok\
"Top Metal spacing < %d (MT.2a)"
area allmtp 562500 440 "Top Metal minimum area < %a (MT.4)"
variants (fast),(full)
widespacing allmtp,obsmtp 10005 allmtp,obsmtp 600 touching_ok \
"Top Metal > %c spacing to unrelated Top Metal < %d (MT.2b)"
#else (!(THICKMET3P0 || THICKMET1P1 || THICKMET0P9))
surround vtp/mtp *mtp 80 absence_illegal \
"Top Metal overlap of ViaTP < %d (VT.4 - VT.3)"
width allmtp 360 "Top Metal width < %d (MT.1)"
spacing allmtp,obsmtp allmtp,obsmtp 380 touching_ok\
"Top Metal spacing < %d (MT.2a)"
area allmtp 562500 360 "Top Metal minimum area < %a (MT.4)"
variants (fast),(full)
widespacing allmtp,obsmtp 10005 allmtp,obsmtp 500 touching_ok \
"Top Metal > %c spacing to unrelated Top Metal < %d (MT.2b)"
#endif (!(THICKMET3P0 || THICKMET1P1 || THICKMET0P9))
variants *
#endif (METALS6)
#--------------------------------------------------
# NMOS, PMOS
#--------------------------------------------------
# NOTE: The layer width can be used for the smaller of
# (minimum length, minimum width). However, for many
# devices, minimum width is less than minimum length.
extend nnfet *ndiff 400 exclusive "nn Transistor length < %d (DF.2c)"
extend mvnnfet *mvndiff 1200 exclusive "MV nn Transistor length < %d (NAT.4)"
width mvnnfet 400 "MV nn Transistor width < %d (DF.2c)"
extend pfet,pcap *pdiff 280 exclusive "Transistor length < %d (PL.2)"
extend nfet,ncap *ndiff 280 exclusive "Transistor length < %d (PL.2)"
extend srampfet *srampdiff 280 exclusive "Transistor length < %d (PL.2)"
extend sramnfet *sramndiff 280 exclusive "Transistor length < %d (PL.2)"
width pfet,pcap 300 angles "Bent Transistor length < %d (PL.7)"
width nfet,ncap 300 angles "Bent Transistor length < %d (PL.7)"
extend mvpfet,mvpcap *mvpdiff 500 exclusive "MV Transistor length < %d (PL.2)"
extend mvnfet,mvncap *mvndiff 600 exclusive "MV Transistor length < %d (PL.2)"
extend hvpfet *mvpdiff 550 exclusive "6V MV Transistor length < %d (PL.2)"
extend hvnfet *mvndiff 700 exclusive "6V MV Transistor length < %d (PL.2)"
extend srammvpfet *srammvpdiff 500 exclusive "MV Transistor length < %d (PL.2)"
extend srammvnfet *srammvndiff 600 exclusive "MV Transistor length < %d (PL.2)"
width hvpfet,mvpfet,mvpcap 700 angles "Bent MV Transistor length < %d (PL.7)"
width hvnfet,mvnfet,mvncap 700 angles "Bent MV Transistor length < %d (PL.7)"
# The following two rules do not appear to be implemented correctly.
# Previously the distance was set to 330, whereas 320 seems to be the
# closest distance allowed, but not due to NP and PP spacing. Also the
# rule numbers cited are wrong, which casts further suspicion on the
# rule implementation.
edge4way pfet,pcap,hvpfet,mvpfet,mvpcap *poly/a 320 \
~(*nsd,*mvnsd)/a (*pdiff,*mvpdiff)/a 300 \
"n-ohmic spacing to PMOS gate < %d (NP.4b + PP.4c)"
edge4way nfet,ncap,nnfet,mvnnfet,hvnfet,mvnfet,mvncap *poly/a 320 \
~(*psd,*mvpsd)/a (*ndiff,*mvndiff)/a 300 \
"p-ohmic spacing to NMOS gate < %d (PP.4b + NP.4c)"
#--------------------------------------------------
# RPP,RNP
#--------------------------------------------------
width rpp 800 "ppolyres minimum width < %d (PRES.1)"
width rnp 800 "npolyres minimum width < %d (LRES.1)"
spacing rpp rpp 400 touching_ok "ppolyres minimum spacing < %d (PRES.2)"
spacing rnp rnp 400 touching_ok "npolyres minimum spacing < %d (LRES.2)"
spacing rpp pc 215 touching_illegal "rpp spacing to Cont < %d (PRES.7 - CO.6)"
spacing rnp pc 215 touching_illegal "rnp spacing to Cont < %d (LRES.7 - CO.6)"
#ifdef HRPOLY1K
#--------------------------------------------------
# HIRES
#--------------------------------------------------
width hires,mvhires 1000 "hires poly minimum width < %d (HRES.3)"
spacing hires,mvhires hires,mvhires 400 touching_ok \
"hires poly minimum spacing < %d (HRES.2)"
variants (full)
cifmaxwidth res_diff_space 0 bend_illegal \
"High value resistor spacing to diffusion < 0.7um (HRES.5 + HRES.4)"
cifmaxwidth res_poly_space 0 bend_illegal \
"High value resistor spacing to poly < 0.7um (HRES.6 + HRES.4)"
cifmaxwidth res_cont_space_min 0 bend_illegal \
"Unsalicided resistor spacing to poly contact must be 0.22um (PRES/LRES/HRES.7)"
cifmaxwidth res_no_cont 0 bend_illegal \
"Unsalicided resistor spacing to poly contact must be 0.22um (PRES/LRES/HRES.7)"
variants *
#endif (HRPOLY1K)
#--------------------------------------------------
# RDN,RDP (Diffusion resistors)
#--------------------------------------------------
width rdn 300 "N-diffusion resistor width < %d (DF.1b)"
width rdp 300 "P-diffusion resistor width < %d (DF.1b)"
#------------------------------------
# MOS Varactor device rules
#------------------------------------
overhang *nsd nvar 320 \
"N-Ohmic overhang of Varactor < %d (FIXME)"
overhang *mvnsd mvnvar 320 \
"N-Ohmic overhang of Varactor < %d (FIXME)"
width nvar,mvnvar 1000 \
"Varactor length and width < %d (DF.1c)"
overhang *psd pvar 320 \
"P-Ohmic overhang of Varactor < %d (FIXME)"
overhang *mvpsd mvpvar 320 \
"P-Ohmic overhang of Varactor < %d (FIXME)"
width pvar,mvpvar 1000 \
"Varactor length and width < %d (DF.1c)"
#ifdef MIM
#undef MIM
#-------------------------------------------------
# CAPM (FuseTop)
#-------------------------------------------------
width *mimcap 5000 "MiM cap top plate width < %d (MIMTM.8a)"
spacing *mimcap *mimcap 600 touching_ok \
"MiM cap top plate spacing < %d (MIMTM.6)"
surround mimcc mimcap 390 absence_illegal \
"MiM cap must surround MiM cap contact by %d (MIMTM.4-VT.4)"
spacing pad *mimcap 50 touching_illegal "MiM cap cannot overlap pad (MIM1M.X)"
spacing mimcc mimcc 480 touching_ok "MiM cap contact spacing < %d (MIMTM.9 - 2 * VT.3)"
#ifdef METALS3
spacing via1 *mimcap 50 touching_illegal \
"MiM cap cannot overlap via1 (MIMTM.10)"
spacing *mimcap *m2,rm2 1200 touching_ok \
"MiM cap to Metal2 spacing < %d (MIMTM.1)"
spacing *mimcap via2/m3 390 touching_illegal \
"MiM cap spacing to via2 < %d (MIMTM.5-VT.X)"
surround *mimcap m2 600 absence_illegal \
"Bottom plate overlap of MiM cap < %d (MIMTM.3)"
width mimcapc/m3 280 "MiM Contact width < %d (VT.1+VT.3)"
#elseif defined(METALS4)
spacing via2 *mimcap 50 touching_illegal \
"MiM cap cannot overlap via2 (MIMTM.10)"
spacing *mimcap *m3,rm3 1200 touching_ok \
"MiM cap to Metal3 spacing < %d (MIMTM.1)"
spacing *mimcap via3/m4 390 touching_illegal \
"MiM cap spacing to via3 < %d (MIMTM.5)"
surround *mimcap m3 600 absence_illegal \
"Bottom plate overlap of MiM cap < %d (MIMTM.3)"
width mimcapc/m4 280 "MiM Contact width < %d (VT.1+VT.3)"
#elseif defined(METALS5)
spacing via3 *mimcap 50 touching_illegal \
"MiM cap cannot overlap via3 (MIMTM.10)"
spacing *mimcap *m4,rm4 1200 touching_ok \
"MiM cap to Metal4 spacing < %d (MIMTM.1)"
spacing *mimcap via4/m5 390 touching_illegal \
"MiM cap spacing to via4 < %d (MIMTM.5)"
surround *mimcap m4 600 absence_illegal \
"Bottom plate overlap of MiM cap < %d (MIMTM.3)"
width mimcapc/m5 280 "MiM Contact width < %d (VT.1+VT.3)"
#elseif defined(METALS6)
spacing via4 *mimcap 50 touching_illegal \
"MiM cap cannot overlap via4 (MIMTM.10)"
spacing *mimcap *m5,rm5 1200 touching_ok \
"MiM cap to Metal5 spacing < %d (MIMTM.1)"
spacing *mimcap viatp/mtp 390 touching_illegal \
"MiM cap spacing to viaTP < %d (MIMTM.5)"
surround *mimcap m5 600 absence_illegal \
"Bottom plate overlap of MiM cap < %d (MIMTM.3)"
width mimcapc/mtp 280 "MiM Contact width < %d (VT.1+VT.3)"
#endif
variants (full)
cifmaxwidth mim_bottom_plate_space 0 bend_illegal \
"MiM bottom plate to unrelated metal < 1.2um (MIMTM.1)"
cifmaxwidth mim_bot_cont_surround 0 bend_illegal \
"MiM bottom plate surrounds contact < 0.4um (MIMTM.2)"
#define MIM
#endif (MIM)
#----------------------------
# End DRC style
#----------------------------
style empty
scalefactor 50
stepsize 2000
end
#----------------------------
# LEF format definitions
#----------------------------
lef
masterslice pwell Pwell PWELL
masterslice nwell Nwell NWELL
routing m1 Metal1 METAL1 MET1 m1 met1 metal1
routing m2 Metal2 METAL2 MET2 m2 met2 metal2
#ifdef METALS3 || METALS4 || METALS5 || METALS6
routing m3 Metal3 METAL3 MET3 m3 met3 metal3
#endif (METALS3 || METALS4 || METALS5 || METALS6)
#ifdef METALS4 || METALS5 || METALS6
routing m4 Metal4 METAL4 MET4 m4 met4 metal4
#endif (METALS4 || METALS5 || METALS6)
#ifdef METALS5 || METALS6
routing m5 Metal5 METAL5 MET5 m5 met5 metal5
#endif (METALS5 || METALS6)
#ifdef METALS6
routing mtp MetalTop Metal6 METAL6 METTP mtp mettp MET6 m6 met6 metal6
#endif (METALS6)
cut m2c Via1 VIA1 via1 cont2 via12 VIA12
#ifdef METALS3 || METALS4 || METALS5 || METALS6
cut m3c Via2 VIA2 via2 cont3 via23 VIA23
#endif (METALS3 || METALS4 || METALS5 || METALS6)
#ifdef METALS4 || METALS5 || METALS6
cut via3 Via3 VIA3 via3 cont4 via34 VIA34
#endif (METALS4 || METALS5 || METALS6)
#ifdef METALS5 || METALS6
cut via4 Via4 VIA4 via4 cont5 via45 VIA45
#endif (METALS5 || METALS6)
#ifdef METALS6
cut viatp Via5 viatp VIATP VIA5 vtp via5 cont6 via56 VIA56
#endif (METALS6)
obs obsm1 Metal1
obs obsm2 Metal2
#ifdef METALS3 || METALS4 || METALS5 || METALS6
obs obsm3 Metal3
#endif (METALS3 || METALS4 || METALS5 || METALS6)
#ifdef METALS4 || METALS5 || METALS6
obs obsm4 Metal4
#endif (METALS4 || METALS5 || METALS6)
#ifdef METALS5 || METALS6
obs obsm5 Metal5
#endif (METALS5 || METALS6)
#ifdef METALS6
obs obsmtp Metal6
#endif (METALS6)
obs obsv1 Via1
obs obsv2 Via2
end
#-----------------------------------------------------
# Device and Parasitic extraction
#-----------------------------------------------------
extract
style ngspice variants (),(hrhc),(lrhc),(hrlc),(lrlc)
cscale 1
lambda 5.0
units microns
step 7
sidehalo 8
fringeshieldhalo 8
planeorder dwell 0
planeorder well 1
planeorder active 2
planeorder poly 3
planeorder metal1 4
planeorder metal2 5
#ifdef METALS3
planeorder metal3 6
planeorder block 7
planeorder comment 8
#elseif defined(METALS4)
planeorder metal3 6
planeorder metal4 7
planeorder block 8
planeorder comment 9
#elseif defined(METALS5)
planeorder metal3 6
planeorder metal4 7
planeorder metal5 8
planeorder block 9
planeorder comment 10
#elseif defined(METALS6)
planeorder metal3 6
planeorder metal4 7
planeorder metal5 8
planeorder metaltp 9
planeorder block 10
planeorder comment 11
#endif
height dnwell -0.1 0.0
height nwell,pwell 0.0 0.0145
height alldiff 0.0145 0.30
height allpoly 0.32 0.2
height alldiffcont 0.3145 0.9155
height pc 0.52 0.71
height allm1 1.23 0.55
height via 1.78 0.60
height allm2 2.38 0.55
#ifdef METALS3 || METALS4 || METALS5 || METALS6
height via2 2.93 0.60
height allm3 3.53 0.55
#endif
#ifdef METALS4 || METALS5 || METALS6
height via3 4.08 0.60
height allm4 4.68 0.55
#endif
#ifdef METALS5 || METALS6
height via4 5.23 0.60
#endif
#ifdef METALS5
height allm5 5.83 1.0025
#endif
#ifdef METALS6
height allm5 5.83 0.55
#endif
#ifdef METALS6
height viatp 6.38 0.9
height allmtp 7.28 1.0025
#endif
# Antenna check parameters
# (to be completed)
model partial
antenna poly sidewall 200 none
antenna allcont surface 10 none
antenna via1 surface 20 none
#ifdef METALS3 || METALS4 || METALS5 || METALS6
antenna via2 surface 20 none
#endif
#ifdef METALS4 || METALS5 || METALS6
antenna via3 surface 20 none
#endif
#ifdef METALS5 || METALS6
antenna via4 surface 20 none
#endif
#ifdef METALS6
antenna viatp surface 20 none
#endif
#ifdef MIM
antenna mimcc surface 20 none
#endif
antenna m1,m2 sidewall 400 none
#ifdef METALS3 || METALS4 || METALS5 || METALS6
antenna m3 sidewall 400 none
#endif
#ifdef METALS4 || METALS5 || METALS6
antenna m4 sidewall 400 none
#endif
#ifdef METALS5 || METALS6
antenna m5 sidewall 400 none
#endif
#ifdef METALS6
antenna mtp sidewall 400 none
#endif
tiedown alldiffnonfet
substrate *ppdiff,*mvppdiff,space/w,pwell well $SUB -dnwell,isosub
# Layer resistance
variants ()
# Resistances are in milliohms per square
# Optional 3rd argument is the corner adjustment fraction
# See document 180MCU_YI-141-EP059-01_10.pdf
resist (nwell,dnwell)/well 1000000
resist (pwell,isosub)/well 3250000
resist (*sramndiff,*ndiff,nsd)/active 6300
resist (*srampdiff,*pdiff,*psd)/active 7000
resist (*srammvndiff,*mvndiff,mvnsd)/active 6300
resist (*srammvpdiff,*mvpdiff,*mvpsd)/active 7000
resist (allpolynonres)/active 7300
resist (rnw)/well 1000000 0.5
resist (rnd)/active 60000 0.5
resist (rpd)/active 185000 0.5
resist (mvrnd)/active 60000 0.5
resist (mvrpd)/active 185000 0.5
resist (rnds)/active 6300 0.5
resist (rpds)/active 7000 0.5
resist (mvrnds)/active 6300 0.5
resist (mvrpds)/active 7000 0.5
resist (rnps)/active 6800 0.5
resist (rpps)/active 7300 0.5
resist (rpp)/active 350000 0.5
resist (rnp)/active 310000 0.5
#ifdef HRPOLY1K
resist (hires,mvhires)/active 1000000 0.5
#endif (HRPOLY1K)
resist (allm1)/metal1 90
resist (allm2)/metal2 90
#ifdef METALS3
#ifdef THICKMET3P0
resist (allm3)/metal3 10
#elseif THICKMET0P9 || THICKMET1P1
resist (allm3)/metal3 40
#else (!(THICKMET3P0 || THICKMET1P1 || THICKMET0P9))
resist (allm3)/metal3 60
#endif (!(THICKMET3P0 || THICKMET1P1 || THICKMET0P9))
#endif (METALS3)
#ifdef METALS4 || METALS5 || METALS6
resist (allm3)/metal3 90
#endif (METALS4 || METALS5 || METALS6)
#ifdef METALS4
#ifdef THICKMET3P0
resist (allm4)/metal4 10
#elseif THICKMET0P9 || THICKMET1P1
resist (allm4)/metal4 40
#else (!(THICKMET3P0 || THICKMET1P1 || THICKMET0P9))
resist (allm4)/metal4 60
#endif (!(THICKMET3P0 || THICKMET1P1 || THICKMET0P9))
#endif (METALS4)
#ifdef METALS5 || METALS6
resist (allm4)/metal4 90
#endif (METALS5 || METALS6)
#ifdef METALS5
#ifdef THICKMET3P0
resist (allm5)/metal5 10
#elseif THICKMET0P9 || THICKMET1P1
resist (allm5)/metal5 40
#else (!(THICKMET3P0 || THICKMET1P1 || THICKMET0P9))
resist (allm5)/metal5 60
#endif (!(THICKMET3P0 || THICKMET1P1 || THICKMET0P9))
#endif (METALS5)
#ifdef METALS6
resist (allm5)/metal5 90
#endif (METALS6)
#ifdef METALS6
#ifdef THICKMET3P0
resist (allmtp)/metaltp 10
#elseif THICKMET0P9 || THICKMET1P1
resist (allmtp)/metaltp 40
#else (!(THICKMET3P0 || THICKMET1P1 || THICKMET0P9))
resist (allmtp)/metaltp 60
#endif (!(THICKMET3P0 || THICKMET1P1 || THICKMET0P9))
#endif (METALS6)
contact ndc,nsc,ndic,nndic 6300
contact pdc,psc,pdic 5200
contact mvndc,mvnsc,mvndic,mvnndic 6300
contact mvpdc,mvpsc,mvpdic 5200
contact pc 8000
contact m2c 4500
#ifdef METALS3 || METALS4 || METALS5 || METALS6
contact m3c 4500
#endif (METALS3 || METALS4 || METALS5 || METALS6)
#ifdef METALS4 || METALS5 || METALS6
contact via3 4500
#endif (METALS4 || METALS5 || METALS6)
#ifdef METALS5 || METALS6
contact via4 4500
#endif (METALS5 || METALS6)
#ifdef MIM
contact mimcc 4500
#endif (MIM)
#ifdef METALS6
contact viatp 4500
#endif (METALS6)
variants (hrhc),(hrlc)
# High-end corner resistances (milliohms per square)
resist (nwell,dnwell)/well 1200000
resist (pwell,isosub)/well 3250000
resist (*sramndiff,*ndiff,nsd)/active 15000
resist (*srampdiff,*pdiff,*psd)/active 15000
resist (*srammvndiff,*mvndiff,mvnsd)/active 15000
resist (*srammvpdiff,*mvpdiff,*mvpsd)/active 15000
resist (allpolynonres)/active 15000
resist (rnw)/well 1200000 0.5
resist (rnd)/active 75000 0.5
resist (rpd)/active 225000 0.5
resist (mvrnd)/active 75000 0.5
resist (mvrpd)/active 225000 0.5
resist (rnds)/active 15000 0.5
resist (rpds)/active 15000 0.5
resist (mvrnds)/active 15000 0.5
resist (mvrpds)/active 15000 0.5
resist (rnps)/active 15000 0.5
resist (rpps)/active 15000 0.5
resist (rpp)/active 420000 0.5
resist (rnp)/active 370000 0.5
#ifdef HRPOLY1K
resist (hires,mvhires)/active 1200000 0.5
#endif (HRPOLY1K)
resist (allm1)/metal1 104
resist (allm2)/metal2 104
#ifdef METALS3
#ifdef THICKMET3P0
resist (allm3)/metal3 15
#elseif THICKMET0P9 || THICKMET1P1
resist (allm3)/metal3 49
#else (!(THICKMET3P0 || THICKMET1P1 || THICKMET0P9))
resist (allm3)/metal3 70
#endif (!(THICKMET3P0 || THICKMET1P1 || THICKMET0P9))
#endif (METALS3)
#ifdef METALS4 || METALS5 || METALS6
resist (allm3)/metal3 104
#endif (METALS4 || METALS5 || METALS6)
#ifdef METALS4
#ifdef THICKMET3P0
resist (allm4)/metal4 14
#elseif THICKMET0P9 || THICKMET1P1
resist (allm4)/metal4 49
#else (!(THICKMET3P0 || THICKMET1P1 || THICKMET0P9))
resist (allm4)/metal4 70
#endif (!(THICKMET3P0 || THICKMET1P1 || THICKMET0P9))
#endif (METALS4)
#ifdef METALS5 || METALS6
resist (allm4)/metal4 104
#endif (METALS5 || METALS6)
#ifdef METALS5
#ifdef THICKMET3P0
resist (allm5)/metal5 14
#elseif THICKMET0P9 || THICKMET1P1
resist (allm5)/metal5 49
#else (!(THICKMET3P0 || THICKMET1P1 || THICKMET0P9))
resist (allm5)/metal5 70
#endif (!(THICKMET3P0 || THICKMET1P1 || THICKMET0P9))
#endif (METALS5)
#ifdef METALS6
resist (allm5)/metal5 104
#endif (METALS6)
#ifdef METALS6
#ifdef THICKMET3P0
resist (allmtp)/metaltp 14
#elseif THICKMET0P9 || THICKMET1P1
resist (allmtp)/metaltp 49
#else (!(THICKMET3P0 || THICKMET1P1 || THICKMET0P9))
resist (allmtp)/metaltp 70
#endif (!(THICKMET3P0 || THICKMET1P1 || THICKMET0P9))
#endif (METALS6)
contact ndc,nsc,ndic,nndic 15000
contact pdc,psc,pdic 15000
contact mvndc,mvnsc,mvndic,mvnndic 15000
contact mvpdc,mvpsc,mvpdic 15000
contact pc 15000
contact m2c 15000
#ifdef METALS3 || METALS4 || METALS5 || METALS6
contact m3c 15000
#endif (METALS3 || METALS4 || METALS5 || METALS6)
#ifdef METALS4 || METALS5 || METALS6
contact via3 15000
#endif (METALS4 || METALS5 || METALS6)
#ifdef METALS5 || METALS6
contact via4 15000
#endif (METALS5 || METALS6)
#ifdef MIM
contact mimcc 15000
#endif (MIM)
#ifdef METALS6
contact viatp 15000
#endif (METALS6)
variants (lrhc),(lrlc)
# Low-end corner resistances (milliohms per square)
resist (nwell,dnwell)/well 800000
resist (pwell,isosub)/well 3250000
resist (*sramndiff,*ndiff,nsd)/active 1000
resist (*srampdiff,*pdiff,*psd)/active 1000
resist (*srammvndiff,*mvndiff,mvnsd)/active 1000
resist (*srammvpdiff,*mvpdiff,*mvpsd)/active 1000
resist (allpolynonres)/active 1000
resist (rnw)/well 8000000 0.5
resist (rnd)/active 45000 0.5
resist (rpd)/active 145000 0.5
resist (mvrnd)/active 45000 0.5
resist (mvrpd)/active 145000 0.5
resist (rnds)/active 1000 0.5
resist (rpds)/active 1000 0.5
resist (mvrnds)/active 1000 0.5
resist (mvrpds)/active 1000 0.5
resist (rnps)/active 1000 0.5
resist (rpps)/active 1000 0.5
resist (rpp)/active 280000 0.5
resist (rnp)/active 250000 0.5
#ifdef HRPOLY1K
resist (hires,mvhires)/active 800000 0.5
#endif (HRPOLY1K)
resist (allm1)/metal1 76
resist (allm2)/metal2 76
#ifdef METALS3
#ifdef THICKMET3P0
resist (allm3)/metal3 6
#elseif THICKMET0P9 || THICKMET1P1
resist (allm3)/metal3 31
#else (!(THICKMET3P0 || THICKMET1P1 || THICKMET0P9))
resist (allm3)/metal3 50
#endif (!(THICKMET3P0 || THICKMET1P1 || THICKMET0P9))
#endif (METALS3)
#ifdef METALS4 || METALS5 || METALS6
resist (allm3)/metal3 76
#endif (METALS4 || METALS5 || METALS6)
#ifdef METALS4
#ifdef THICKMET3P0
resist (allm4)/metal4 6
#elseif THICKMET0P9 || THICKMET1P1
resist (allm4)/metal4 31
#else (!(THICKMET3P0 || THICKMET1P1 || THICKMET0P9))
resist (allm4)/metal4 50
#endif (!(THICKMET3P0 || THICKMET1P1 || THICKMET0P9))
#endif (METALS4)
#ifdef METALS5 || METALS6
resist (allm4)/metal4 76
#endif (METALS5 || METALS6)
#ifdef METALS5
#ifdef THICKMET3P0
resist (allm5)/metal5 6
#elseif THICKMET0P9 || THICKMET1P1
resist (allm5)/metal5 31
#else (!(THICKMET3P0 || THICKMET1P1 || THICKMET0P9))
resist (allm5)/metal5 50
#endif (!(THICKMET3P0 || THICKMET1P1 || THICKMET0P9))
#endif (METALS5)
#ifdef METALS6
resist (allm5)/metal5 76
#endif (METALS6)
#ifdef METALS6
#ifdef THICKMET3P0
resist (allmtp)/metaltp 6
#elseif THICKMET0P9 || THICKMET1P1
resist (allmtp)/metaltp 31
#else (!(THICKMET3P0 || THICKMET1P1 || THICKMET0P9))
resist (allmtp)/metaltp 50
#endif (!(THICKMET3P0 || THICKMET1P1 || THICKMET0P9))
#endif (METALS6)
contact ndc,nsc,ndic,nndic 0
contact pdc,psc,pdic 0
contact mvndc,mvnsc,mvndic,mvnndic 0
contact mvpdc,mvpsc,mvpdic 0
contact pc 0
contact m2c 0
#ifdef METALS3 || METALS4 || METALS5 || METALS6
contact m3c 0
#endif (METALS3 || METALS4 || METALS5 || METALS6)
#ifdef METALS4 || METALS5 || METALS6
contact via3 0
#endif (METALS4 || METALS5 || METALS6)
#ifdef METALS5 || METALS6
contact via4 0
#endif (METALS5 || METALS6)
#ifdef MIM
contact mimcc 0
#endif (MIM)
#ifdef METALS6
contact viatp 0
#endif (METALS6)
variants *
# These types should not be considered as electrical nodes
resist comment None
#-------------------------------------------------------------------------
# Parasitic capacitance values:
#-------------------------------------------------------------------------
# This uses the new "default" definitions that determine the intervening
# planes from the planeorder stack, take care of the reflexive sideoverlap
# definitions, and generally clean up the section and make it more readable.
#
# Also uses "units microns" statement, so all parasitic capacitance values
# are taken directly from the source document PDS_035_03, in units of
# aF/um^2 for area caps and aF/um for perimeter and sidewall caps.
#-------------------------------------------------------------------------
# Remember that device capacitances to substrate are taken care of by the
# models. Thus, active and poly definitions ignore all "fet" types.
# fet types are excluded when computing parasitic capacitance to
# active from layers above them because poly is a shield; fet types are
# included for parasitics from layers above to poly. Resistor types
# should be removed from all parasitic capacitance calculations, or else
# they just create floating caps. Technically, the capacitance probably
# should be split between the two terminals. Unsure of the correct model.
# Because rnw is on the well plane, "defaultareacap" does not work for
# planes above diffusion because rnw cannot be removed from types on the
# well plane. Because of this, use the normal "areacap" to specify cap
# to substrate, and "defaultoverlap" to specify cap to nwell (but not rnw).
#-------------------------------------------------------------------------
variants ()
# Nominal capacitances
#n-well
defaultareacap nwell well 120
#n-active
# Rely on device models to capture *ndiff area cap
# Do not extract parasitics from resistors
# defaultareacap allnactivenonfet active 790
# defaultperimeter allnactivenonfet active 280
#p-active
# Rely on device models to capture *pdiff area cap
# Do not extract parasitics from resistors
# defaultareacap allpactivenonfet active 810
# defaultperimeter allpactivenonfet active 300
#poly
# Do not extract parasitics from resistors
# defaultsidewall allpolynonfet active 22
# defaultareacap allpolynonfet active 105
# defaultperimeter allpolynonfet active 57
defaultsidewall *poly active 11.098 -0.082
defaultareacap *poly active 110.67
defaultperimeter *poly active 50.72
defaultoverlap *poly active nwell,obswell,pwell well 110.67
defaultsideoverlap *poly active nwell,obswell,pwell well 50.72
#metal1
defaultsidewall allm1 metal1 40.512 -0.053
defaultareacap allm1 metal1 29.304
defaultperimeter allm1 metal1 39.431
defaultoverlap allm1 metal1 nwell well 29.304
defaultsideoverlap allm1 metal1 nwell well 39.431
#metal1->active
defaultoverlap allm1 metal1 alllvactivenonfet active 30.502
defaultsideoverlap allm1 metal1 alllvactivenonfet active 43.406
defaultoverlap allm1 metal1 allmvactivenonfet active 39.187
defaultsideoverlap allm1 metal1 allmvactivenonfet active 43.308
#metal1->poly
defaultoverlap allm1 metal1 allpolynonres active 51.434
defaultsideoverlap allm1 metal1 allpolynonres active 46.700
defaultsideoverlap *poly active allm1 metal1 17.946
#metal2
defaultsidewall allm2 metal2 46.736 0.289
defaultareacap allm2 metal2 15.016
defaultperimeter allm2 metal2 33.298
defaultoverlap allm2 metal2 nwell well 15.016
defaultsideoverlap allm2 metal2 nwell well 33.298
#metal2->active
defaultoverlap allm2 metal2 alllvactivenonfet active 17.305
defaultsideoverlap allm2 metal2 alllvactivenonfet active 35.189
defaultoverlap allm2 metal2 allmvactivenonfet active 17.244
defaultsideoverlap allm2 metal2 allmvactivenonfet active 35.153
#metal2->poly
defaultoverlap allm2 metal2 allpolynonres active 19.263
defaultsideoverlap allm2 metal2 allpolynonres active 36.169
defaultsideoverlap *poly active allm2 metal2 8.706
#metal2->metal1
defaultoverlap allm2 metal2 allm1 metal1 59.027
defaultsideoverlap allm2 metal2 allm1 metal1 47.566
defaultsideoverlap allm1 metal1 allm2 metal2 32.048
#ifdef METALS3 || METALS4 || METALS5 || METALS6
#metal3
defaultsidewall allm3 metal3 70.675 0.534
defaultareacap allm3 metal3 10.094
defaultperimeter allm3 metal3 30.021
defaultoverlap allm3 metal3 nwell well 10.094
defaultsideoverlap allm3 metal3 nwell well 30.021
#metal3->active
defaultoverlap allm3 metal3 alllvactivenonfet active 11.079
defaultsideoverlap allm3 metal3 alllvactivenonfet active 31.40
defaultoverlap allm3 metal3 allmvactivenonfet active 11.054
defaultsideoverlap allm3 metal3 allmvactivenonfet active 31.38
#metal3->poly
defaultoverlap allm3 metal3 allpolynonres active 11.850
defaultsideoverlap allm3 metal3 allpolynonres active 31.927
defaultsideoverlap *poly active allm3 metal3 5.895
#metal3->metal1
defaultoverlap allm3 metal3 allm1 metal1 20.238
defaultsideoverlap allm3 metal3 allm1 metal1 36.609
defaultsideoverlap allm1 metal1 allm3 metal3 18.135
#metal3->metal2
defaultoverlap allm3 metal3 allm2 metal2 59.027
defaultsideoverlap allm3 metal3 allm2 metal2 49.011
defaultsideoverlap allm2 metal2 allm3 metal3 36.626
#endif (METALS3 || METALS4 || METALS5 || METALS6)
#ifdef METALS4 || METALS5 || METALS6
#metal4
defaultsidewall allm4 metal4 77.388 0.611
defaultareacap allm4 metal4 7.602
defaultperimeter allm4 metal4 28.153
defaultoverlap allm4 metal4 nwell well 7.602
defaultsideoverlap allm4 metal4 nwell well 28.153
#metal4->active
defaultoverlap allm4 metal4 alllvactivenonfet active 8.148
defaultsideoverlap allm4 metal4 alllvactivenonfet active 29.065
defaultoverlap allm4 metal4 allmvactivenonfet active 8.135
defaultsideoverlap allm4 metal4 allmvactivenonfet active 29.050
#metal4->poly
defaultoverlap allm4 metal4 allpolynonres active 8.557
defaultsideoverlap allm4 metal4 allpolynonres active 29.407
defaultsideoverlap *poly active allm4 metal4 8.557
#metal4->metal1
defaultoverlap allm4 metal4 allm1 metal1 12.212
defaultsideoverlap allm4 metal4 allm1 metal1 32.104
defaultsideoverlap allm1 metal1 allm4 metal4 13.159
#metal4->metal2
defaultoverlap allm4 metal4 allm2 metal2 20.238
defaultsideoverlap allm4 metal4 allm2 metal2 36.563
defaultsideoverlap allm2 metal2 allm4 metal4 22.405
#metal4->metal3
defaultoverlap allm4 metal4 allm3 metal3 59.027
defaultsideoverlap allm4 metal4 allm3 metal3 47.871
defaultsideoverlap allm3 metal3 allm4 metal4 39.964
#endif (METALS4 || METALS5 || METALS6)
#ifdef METALS5
#metal5
defaultsidewall allm5 metal5 114.86 0.025
#endif
#ifdef METALS6
defaultsidewall allm5 metal5 31.121
#endif
#ifdef METALS5 || METALS6
defaultareacap allm5 metal5 5.798
defaultperimeter allm5 metal5 30.386
defaultoverlap allm5 metal5 nwell well 5.798
defaultsideoverlap allm5 metal5 nwell well 30.386
#metal5->active
defaultoverlap allm5 metal5 alllvactivenonfet active 6.110
defaultsideoverlap allm5 metal5 alllvactivenonfet active 31.165
defaultoverlap allm5 metal5 allmvactivenonfet active 6.102
defaultsideoverlap allm5 metal5 allmvactivenonfet active 31.152
#metal5->poly
defaultoverlap allm5 metal5 allpolynonres active 6.337
defaultsideoverlap allm5 metal5 allpolynonres active 31.458
defaultsideoverlap *poly active allm5 metal5 3.365
#metal5->metal1
defaultoverlap allm5 metal5 allm1 metal1 8.142
defaultsideoverlap allm5 metal5 allm1 metal1 33.316
defaultsideoverlap allm1 metal1 allm5 metal5 9.825
#metal5->metal2
defaultoverlap allm5 metal5 allm2 metal2 11.067
defaultsideoverlap allm5 metal5 allm2 metal2 36.591
defaultsideoverlap allm2 metal2 allm5 metal5 15.764
#metal5->metal3
defaultoverlap allm5 metal5 allm3 metal3 17.276
defaultsideoverlap allm5 metal5 allm3 metal3 41.466
defaultsideoverlap allm3 metal3 allm5 metal5 22.988
#metal5->metal4
defaultoverlap allm5 metal5 allm4 metal4 39.351
defaultsideoverlap allm5 metal5 allm4 metal4 52.692
defaultsideoverlap allm4 metal4 allm5 metal5 34.954
#endif (METALS5 || METALS6)
#ifdef METALS6
#metaltp
defaultsidewall allmtp metaltp 54.335
defaultareacap allmtp metaltp 4.8793
defaultperimeter allmtp metaltp 9.5950
defaultoverlap allmtp metaltp nwell well 4.8793
defaultsideoverlap allmtp metaltp nwell well 9.5950
#metaltp->active
defaultoverlap allmtp metaltp alllvactivenonfet active 5.0937
defaultsideoverlap allmtp metaltp alllvactivenonfet active 9.8790
defaultoverlap allmtp metaltp allmvactivenonfet active 5.0937
defaultsideoverlap allmtp metaltp allmvactivenonfet active 9.8790
#metaltp->poly
defaultoverlap allmtp metaltp allpolynonres active 5.2558
defaultsideoverlap allmtp metaltp allpolynonres active 10.128
defaultsideoverlap *poly active allmtp metaltp 16.946
#metaltp->metal1
defaultoverlap allmtp metaltp allm1 metal1 6.4394
defaultsideoverlap allmtp metaltp allm1 metal1 11.765
defaultsideoverlap allm1 metal1 allmtp metaltp XX.XX
#metaltp->metal2
defaultoverlap allmtp metaltp allm2 metal2 8.1418
defaultsideoverlap allmtp metaltp allm2 metal2 13.958
defaultsideoverlap allm2 metal2 allmtp metaltp XX.XX
#metaltp->metal3
defaultoverlap allmtp metaltp allm3 metal3 11.0677
defaultsideoverlap allmtp metaltp allm3 metal3 17.640
defaultsideoverlap allm3 metal3 allmtp metaltp XX.XX
#metaltp->metal4
defaultoverlap allmtp metaltp allm4 metal4 17.2765
defaultsideoverlap allmtp metaltp allm4 metal4 24.286
defaultsideoverlap allm4 metal4 allmtp metaltp XX.XX
#metaltp->metal5
defaultoverlap allmtp metaltp allm5 metal5 39.3519
defaultsideoverlap allmtp metaltp allm5 metal5 39.586
defaultsideoverlap allm5 metal5 allmtp metaltp XX.XX
#endif (METALS6)
#-------------------------------------------------------------------------
# Parasitic capacitance values for maximum corner
#-------------------------------------------------------------------------
variants (hrhc),(lrhc)
# Maximum corner capacitances
#n-well
defaultareacap nwell well 120
#n-active
# Rely on device models to capture *ndiff area cap
# Do not extract parasitics from resistors
# defaultareacap allnactivenonfet active 790
# defaultperimeter allnactivenonfet active 280
#p-active
# Rely on device models to capture *pdiff area cap
# Do not extract parasitics from resistors
# defaultareacap allpactivenonfet active 810
# defaultperimeter allpactivenonfet active 300
#poly
# Do not extract parasitics from resistors
# defaultsidewall allpolynonfet active 22
# defaultareacap allpolynonfet active 105
# defaultperimeter allpolynonfet active 57
defaultsidewall *poly active 10.434 -0.09
defaultareacap *poly active 130.21
defaultperimeter *poly active 53.551
defaultoverlap *poly active nwell,obswell,pwell well 130.21
defaultsideoverlap *poly active nwell,obswell,pwell well 53.551
#metal1
defaultsidewall allm1 metal1 29.146 -0.107
defaultareacap allm1 metal1 33.126
defaultperimeter allm1 metal1 41.362
defaultoverlap allm1 metal1 nwell well 33.126
defaultsideoverlap allm1 metal1 nwell well 41.362
#metal1->active
defaultoverlap allm1 metal1 alllvactivenonfet active 43.987
defaultsideoverlap allm1 metal1 alllvactivenonfet active 45.606
defaultoverlap allm1 metal1 allmvactivenonfet active 43.597
defaultsideoverlap allm1 metal1 allmvactivenonfet active 45.456
#metal1->poly
defaultoverlap allm1 metal1 allpolynonres active 60.319
defaultsideoverlap allm1 metal1 allpolynonres active 49.813
defaultsideoverlap *poly active allm1 metal1 19.203
#metal2
defaultsidewall allm2 metal2 47.311 -0.055
defaultareacap allm2 metal2 16.471
defaultperimeter allm2 metal2 34.914
defaultoverlap allm2 metal2 nwell well 16.471
defaultsideoverlap allm2 metal2 nwell well 34.914
#metal2->active
defaultoverlap allm2 metal2 alllvactivenonfet active 18.777
defaultsideoverlap allm2 metal2 alllvactivenonfet active 36.552
defaultoverlap allm2 metal2 allmvactivenonfet active 18.706
defaultsideoverlap allm2 metal2 allmvactivenonfet active 36.484
#metal2->poly
defaultoverlap allm2 metal2 allpolynonres active 21.231
defaultsideoverlap allm2 metal2 allpolynonres active 37.753
defaultsideoverlap *poly active allm2 metal2 9.032
#metal2->metal1
defaultoverlap allm2 metal2 allm1 metal1 73.630
defaultsideoverlap allm2 metal2 allm1 metal1 53.172
defaultsideoverlap allm1 metal1 allm2 metal2 35.957
#ifdef METALS3 || METALS4 || METALS5 || METALS6
#metal3
defaultsidewall allm3 metal3 52.065 0.011
defaultareacap allm3 metal3 10.961
defaultperimeter allm3 metal3 31.797
defaultoverlap allm3 metal3 nwell well 10.961
defaultsideoverlap allm3 metal3 nwell well 31.797
#metal3->active
defaultoverlap allm3 metal3 alllvactivenonfet active 11.936
defaultsideoverlap allm3 metal3 alllvactivenonfet active 32.182
defaultoverlap allm3 metal3 allmvactivenonfet active 11.907
defaultsideoverlap allm3 metal3 allmvactivenonfet active 32.161
#metal3->poly
defaultoverlap allm3 metal3 allpolynonres active 12.883
defaultsideoverlap allm3 metal3 allpolynonres active 33.123
defaultsideoverlap *poly active allm3 metal3 6.048
#metal3->metal1
defaultoverlap allm3 metal3 allm1 metal1 22.673
defaultsideoverlap allm3 metal3 allm1 metal1 38.387
defaultsideoverlap allm1 metal1 allm3 metal3 19.218
#metal3->metal2
defaultoverlap allm3 metal3 allm2 metal2 73.630
defaultsideoverlap allm3 metal3 allm2 metal2 53.162
defaultsideoverlap allm2 metal2 allm3 metal3 40.062
#endif (METALS3 || METALS4 || METALS5 || METALS6)
#ifdef METALS4 || METALS5 || METALS6
#metal4
defaultsidewall allm4 metal4 64.224 0.022
defaultareacap allm4 metal4 8.213
defaultperimeter allm4 metal4 29.318
defaultoverlap allm4 metal4 nwell well 8.213
defaultsideoverlap allm4 metal4 nwell well 29.318
#metal4->active
defaultoverlap allm4 metal4 alllvactivenonfet active 8.749
defaultsideoverlap allm4 metal4 alllvactivenonfet active 29.951
defaultoverlap allm4 metal4 allmvactivenonfet active 8.733
defaultsideoverlap allm4 metal4 allmvactivenonfet active 29.937
#metal4->poly
defaultoverlap allm4 metal4 allpolynonres active 9.247
defaultsideoverlap allm4 metal4 allpolynonres active 30.173
defaultsideoverlap *poly active allm4 metal4 4.470
#metal4->metal1
defaultoverlap allm4 metal4 allm1 metal1 13.400
defaultsideoverlap allm4 metal4 allm1 metal1 32.864
defaultsideoverlap allm1 metal1 allm4 metal4 13.737
#metal4->metal2
defaultoverlap allm4 metal4 allm2 metal2 22.673
defaultsideoverlap allm4 metal4 allm2 metal2 38.349
defaultsideoverlap allm2 metal2 allm4 metal4 23.678
#metal4->metal3
defaultoverlap allm4 metal4 allm3 metal3 73.63
defaultsideoverlap allm4 metal4 allm3 metal3 51.717
defaultsideoverlap allm3 metal3 allm4 metal4 43.907
#endif (METALS4 || METALS5 || METALS6)
#ifdef METALS5 || METALS6
#metal5
defaultsidewall allm5 metal5 129.73 0.043
defaultareacap allm5 metal5 6.240
defaultperimeter allm5 metal5 32.259
defaultoverlap allm5 metal5 nwell well 6.240
defaultsideoverlap allm5 metal5 nwell well 32.259
#metal5->active
defaultoverlap allm5 metal5 alllvactivenonfet active 6.545
defaultsideoverlap allm5 metal5 alllvactivenonfet active 32.685
defaultoverlap allm5 metal5 allmvactivenonfet active 6.536
defaultsideoverlap allm5 metal5 allmvactivenonfet active 32.665
#metal5->poly
defaultoverlap allm5 metal5 allpolynonres active 6.820
defaultsideoverlap allm5 metal5 allpolynonres active 33.050
defaultsideoverlap *poly active allm5 metal5 3.402
#metal5->metal1
defaultoverlap allm5 metal5 allm1 metal1 8.841
defaultsideoverlap allm5 metal5 allm1 metal1 35.530
defaultsideoverlap allm1 metal1 allm5 metal5 10.263
#metal5->metal2
defaultoverlap allm5 metal5 allm2 metal2 12.108
defaultsideoverlap allm5 metal5 allm2 metal2 38.815
defaultsideoverlap allm2 metal2 allm5 metal5 16.351
#metal5->metal3
defaultoverlap allm5 metal5 allm3 metal3 19.206
defaultsideoverlap allm5 metal5 allm3 metal3 44.329
defaultsideoverlap allm3 metal3 allm5 metal5 23.969
#metal5->metal4
defaultoverlap allm5 metal5 allm4 metal4 46.417
defaultsideoverlap allm5 metal5 allm4 metal4 57.180
defaultsideoverlap allm4 metal4 allm5 metal5 38.202
#endif (METALS5 || METALS6)
#ifdef METALS6
#metaltp
defaultsidewall allmtp metaltp 57.187
defaultareacap allmtp metaltp 5.242
defaultperimeter allmtp metaltp 9.407
defaultoverlap allmtp metaltp nwell well 5.242
#metaltp->active
defaultoverlap allmtp metaltp alllvactivenonfet active 5.450
defaultsideoverlap allmtp metaltp alllvactivenonfet active 9.679
defaultoverlap allmtp metaltp allmvactivenonfet active 5.450
defaultsideoverlap allmtp metaltp allmvactivenonfet active 9.679
#metaltp->poly
defaultoverlap allmtp metaltp allpolynonres active 5.645
defaultsideoverlap allmtp metaltp allpolynonres active 9.925
defaultsideoverlap *poly active allmtp metaltp 16.946
#metaltp->metal1
defaultoverlap allmtp metaltp allm1 metal1 6.962
defaultsideoverlap allmtp metaltp allm1 metal1 11.549
defaultsideoverlap allm1 metal1 allmtp metaltp 16.946
#metaltp->metal2
defaultoverlap allmtp metaltp allm2 metal2 8.841
defaultsideoverlap allmtp metaltp allm2 metal2 13.909
defaultsideoverlap allm2 metal2 allmtp metaltp 16.946
#metaltp->metal3
defaultoverlap allmtp metaltp allm3 metal3 12.211
defaultsideoverlap allmtp metaltp allm3 metal3 17.215
defaultsideoverlap allm3 metal3 allmtp metaltp 16.946
#metaltp->metal4
defaultoverlap allmtp metaltp allm4 metal4 19.207
defaultsideoverlap allmtp metaltp allm4 metal4 24.725
defaultsideoverlap allm4 metal4 allmtp metaltp 16.946
#metaltp->metal5
defaultoverlap allmtp metaltp allm5 metal5 46.418
defaultsideoverlap allmtp metaltp allm5 metal5 41.628
defaultsideoverlap allm5 metal5 allmtp metaltp 16.946
#endif (METALS6)
#-------------------------------------------------------------------------
# Parasitic capacitance values for minimum corner
#-------------------------------------------------------------------------
variants (hrlc),(lrlc)
# Minimum corner capacitances
#n-well
defaultareacap nwell well 120
#n-active
# Rely on device models to capture *ndiff area cap
# Do not extract parasitics from resistors
# defaultareacap allnactivenonfet active 790
# defaultperimeter allnactivenonfet active 280
#p-active
# Rely on device models to capture *pdiff area cap
# Do not extract parasitics from resistors
# defaultareacap allpactivenonfet active 810
# defaultperimeter allpactivenonfet active 300
#poly
# Do not extract parasitics from resistors
# defaultsidewall allpolynonfet active 22
# defaultareacap allpolynonfet active 105
# defaultperimeter allpolynonfet active 57
defaultsidewall *poly active 11.749 -0.074
defaultareacap *poly active 96.239
defaultperimeter *poly active 48.703
defaultoverlap *poly active nwell,obswell,pwell well 96.239
defaultsideoverlap *poly active nwell,obswell,pwell well 48.703
#metal1
defaultsidewall allm1 metal1 34.592 -0.066
defaultareacap allm1 metal1 26.273
defaultperimeter allm1 metal1 38.065
defaultoverlap allm1 metal1 nwell well 26.273
defaultsideoverlap allm1 metal1 nwell well 38.065
#metal1->active
defaultoverlap allm1 metal1 alllvactivenonfet active 35.846
defaultsideoverlap allm1 metal1 alllvactivenonfet active 41.401
defaultoverlap allm1 metal1 allmvactivenonfet active 35.587
defaultsideoverlap allm1 metal1 allmvactivenonfet active 41.319
#metal1->poly
defaultoverlap allm1 metal1 allpolynonres active 44.830
defaultsideoverlap allm1 metal1 allpolynonres active 44.006
defaultsideoverlap *poly active allm1 metal1 16.709
#metal2
defaultsidewall allm2 metal2 45.876 0.308
defaultareacap allm2 metal2 13.797
defaultperimeter allm2 metal2 32.628
defaultoverlap allm2 metal2 nwell well 13.797
#metal2->active
defaultoverlap allm2 metal2 alllvactivenonfet active 16.047
defaultsideoverlap allm2 metal2 alllvactivenonfet active 33.878
defaultoverlap allm2 metal2 allmvactivenonfet active 15.995
defaultsideoverlap allm2 metal2 allmvactivenonfet active 34.723
#metal2->poly
defaultoverlap allm2 metal2 allpolynonres active 17.629
defaultsideoverlap allm2 metal2 allpolynonres active 34.723
defaultsideoverlap *poly active allm2 metal2 8.497
#metal2->metal1
defaultoverlap allm2 metal2 allm1 metal1 49.257
defaultsideoverlap allm2 metal2 allm1 metal1 45.669
defaultsideoverlap allm1 metal1 allm2 metal2 29.508
#ifdef METALS3 || METALS4 || METALS5 || METALS6
#metal3
defaultsidewall allm3 metal3 80.787 0.719
defaultareacap allm3 metal3 9.354
defaultperimeter allm3 metal3 29.055
defaultoverlap allm3 metal3 nwell well 9.354
defaultsideoverlap allm3 metal3 nwell well 29.055
#metal3->active
defaultoverlap allm3 metal3 alllvactivenonfet active 10.337
defaultsideoverlap allm3 metal3 alllvactivenonfet active 30.367
defaultoverlap allm3 metal3 allmvactivenonfet active 10.316
defaultsideoverlap allm3 metal3 allmvactivenonfet active 30.332
#metal3->poly
defaultoverlap allm3 metal3 allpolynonres active 10.971
defaultsideoverlap allm3 metal3 allpolynonres active 30.302
defaultsideoverlap *poly active allm3 metal3 5.744
#metal3->metal1
defaultoverlap allm3 metal3 allm1 metal1 18.275
defaultsideoverlap allm3 metal3 allm1 metal1 34.455
defaultsideoverlap allm1 metal1 allm3 metal3 17.162
#metal3->metal2
defaultoverlap allm3 metal3 allm2 metal2 49.257
defaultsideoverlap allm3 metal3 allm2 metal2 45.649
defaultsideoverlap allm2 metal2 allm3 metal3 33.836
#endif (METALS3 || METALS4 || METALS5 || METALS6)
#ifdef METALS4 || METALS5 || METALS6
#metal4
defaultsidewall allm4 metal4 79.719 0.700
defaultareacap allm4 metal4 7.076
defaultperimeter allm4 metal4 27.123
defaultoverlap allm4 metal4 nwell well 7.076
defaultsideoverlap allm4 metal4 nwell well 27.123
#metal4->active
defaultoverlap allm4 metal4 alllvactivenonfet active 7.625
defaultsideoverlap allm4 metal4 alllvactivenonfet active 28.128
defaultoverlap allm4 metal4 allmvactivenonfet active 7.613
defaultsideoverlap allm4 metal4 allmvactivenonfet active 28.136
#metal4->poly
defaultoverlap allm4 metal4 allpolynonres active 7.964
defaultsideoverlap allm4 metal4 allpolynonres active 28.175
defaultsideoverlap *poly active allm4 metal4 4.342
#metal4->metal1
defaultoverlap allm4 metal4 allm1 metal1 11.218
defaultsideoverlap allm4 metal4 allm1 metal1 30.402
defaultsideoverlap allm1 metal1 allm4 metal4 12.468
#metal4->metal2
defaultoverlap allm4 metal4 allm2 metal2 18.275
defaultsideoverlap allm4 metal4 allm2 metal2 34.947
defaultsideoverlap allm2 metal2 allm4 metal4 21.090
#metal4->metal3
defaultoverlap allm4 metal4 allm3 metal3 49.257
defaultsideoverlap allm4 metal4 allm3 metal3 45.614
defaultsideoverlap allm3 metal3 allm4 metal4 36.938
#endif (METALS4 || METALS5 || METALS6)
#ifdef METALS5 || METALS6
#metal5
defaultsidewall allm5 metal5 92.462 -0.034
defaultareacap allm5 metal5 5.414
defaultperimeter allm5 metal5 29.752
defaultoverlap allm5 metal5 nwell well 5.414
defaultsideoverlap allm5 metal5 nwell well 29.752
#metal5->active
defaultoverlap allm5 metal5 alllvactivenonfet active 5.729
defaultsideoverlap allm5 metal5 alllvactivenonfet active 30.199
defaultoverlap allm5 metal5 allmvactivenonfet active 5.722
defaultsideoverlap allm5 metal5 allmvactivenonfet active 30.189
#metal5->poly
defaultoverlap allm5 metal5 allpolynonres active 5.918
defaultsideoverlap allm5 metal5 allpolynonres active 30.453
defaultsideoverlap *poly active allm5 metal5 3.319
#metal5->metal1
defaultoverlap allm5 metal5 allm1 metal1 7.545
defaultsideoverlap allm5 metal5 allm1 metal1 32.178
defaultsideoverlap allm1 metal1 allm5 metal5 9.413
#metal5->metal2
defaultoverlap allm5 metal5 allm2 metal2 10.192
defaultsideoverlap allm5 metal5 allm2 metal2 34.862
defaultsideoverlap allm2 metal2 allm5 metal5 15.155
#metal5->metal3
defaultoverlap allm5 metal5 allm3 metal3 15.699
defaultsideoverlap allm5 metal5 allm3 metal3 39.754
defaultsideoverlap allm3 metal3 allm5 metal5 22.014
#metal5->metal4
defaultoverlap allm5 metal5 allm4 metal4 34.152
defaultsideoverlap allm5 metal5 allm4 metal4 49.818
defaultsideoverlap allm4 metal4 allm5 metal5 33.358
#endif (METALS5 || METALS6)
#ifdef METALS6
#metaltp
defaultsidewall allmtp metaltp 51.353
defaultareacap allmtp metaltp 4.563
defaultperimeter allmtp metaltp 9.764
defaultoverlap allmtp metaltp nwell well 4.563
defaultsideoverlap allmtp metaltp nwell well 9.764
#metaltp->active
defaultoverlap allmtp metaltp alllvactivenonfet active 4.781
defaultsideoverlap allmtp metaltp alllvactivenonfet active 10.070
defaultoverlap allmtp metaltp allmvactivenonfet active 4.781
defaultsideoverlap allmtp metaltp allmvactivenonfet active 10.070
#metaltp->poly
defaultoverlap allmtp metaltp allpolynonres active 4.917
defaultsideoverlap allmtp metaltp allpolynonres active 10.263
defaultsideoverlap *poly active allmtp metaltp 16.946
#metaltp->metal1
defaultoverlap allmtp metaltp allm1 metal1 5.990
defaultsideoverlap allmtp metaltp allm1 metal1 11.858
defaultsideoverlap allm1 metal1 allmtp metaltp 16.946
#metaltp->metal2
defaultoverlap allmtp metaltp allm2 metal2 7.545
defaultsideoverlap allmtp metaltp allm2 metal2 13.985
defaultsideoverlap allm2 metal2 allmtp metaltp 16.946
#metaltp->metal3
defaultoverlap allmtp metaltp allm3 metal3 10.192
defaultsideoverlap allmtp metaltp allm3 metal3 17.610
defaultsideoverlap allm3 metal3 allmtp metaltp 16.946
#metaltp->metal4
defaultoverlap allmtp metaltp allm4 metal4 15.699
defaultsideoverlap allmtp metaltp allm4 metal4 23.834
defaultsideoverlap allm4 metal4 allmtp metaltp 16.946
#metaltp->metal5
defaultoverlap allmtp metaltp allm5 metal5 34.153
defaultsideoverlap allmtp metaltp allm5 metal5 37.782
defaultsideoverlap allm5 metal5 allmtp metaltp 16.946
#endif (METALS6)
#-------------------------------------------------------------------------
variants *
# Devices:
# All devices except diodes are modeled as subcircuits
# device list:
# nfet_03v3 mosfet
# pfet_03v3 mosfet
# nfet_06v0 mosfet (thick oxide)
# pfet_06v0 mosfet (thick oxide)
# nfet_05v0 mosfet (thick oxide, short gate)*
# pfet_05v0 mosfet (thick oxide, short gate)*
# nfet_06v0_nvt mosfet (native Vt)
# nfet_03v3_dss mosfet (unsalicided drain)
# pfet_03v3_dss mosfet (unsalicided drain)
# nfet_06v0_dss mosfet (unsalicided drain, thick oxide)
# pfet_06v0_dss mosfet (unsalicided drain, thick oxide)
# nfet_10v0_asym LDNMOS (extended drain)
# pfet_10v0_asym LDPMOS (extended drain)
#
# diode_nd2ps_03v3 diode (N+/pwell)
# diode_pd2nw_03v3 diode (P+/nwell)
# diode_nd2ps_06v0 diode (N+/pwell, high voltage)
# diode_pd2nw_06v0 diode (P+/nwell, high voltage)
# diode_nw2pw_03v3 diode (nwell/pwell)
# diode_nw2pw_06v0 diode (nwell/pwell, high voltage)
# diode_dnw2pw diode (pwell/dnwell)
# diode_dnw2ps diode (dnwll/substrate)
# sc_diode diode (Schottky)
#
# pnp_WxL BJT (10x10, 5x5, 0.42x10, 0.42x5 emitter sizes)
# npn_WxL BJT (10x10, 5x5, 0.54x16, 0.54x8, 0.54x4, 0.54x2)
#
# npolyf_u resistor (N+ poly, unsalicided)
# ppolyf_u resistor (P+ poly, unsalicided)
# ppolyf_u_1k resistor (high res resistor)*
# ppolyf_u_1k_6p0 resistor (high res resistor, high voltage)**
# nplus_u resistor (N+ diffusion, unsalicided)
# pplus_u resistor (P+ diffusion, unsalicided)
# npolyf_s resistor (N+ poly, salicided)
# ppolyf_s resistor (P+ poly, salicided)
# nplus_s resistor (N+ diffusion, salicided)
# pplus_s resistor (N+ diffusion, salicided)
# nwell resistor (N-well resistor)
# rm1 resistor (metal1)
# rm2 resistor (metal2)
# rm3 resistor (metal3)
# rm4 resistor (metal4)
# rm5 resistor (metal5)
# tm6k resistor (top metal, 0.6um thick (standard))***
# tm9k resistor (top metal, 0.9um thick)
# tm11k resistor (top metal, 1.1um thick)
# tm30k resistor (top metal, 3.0um thick)
#
# cap_nmos_03v3 mosfet (source-drain tied)
# cap_pmos_03v3 mosfet (source-drain tied)
# cap_nmos_06v0 mosfet (source-drain tied, high voltage)
# cap_pmos_06v0 mosfet (source-drain tied, high voltage)
# cap_nmos_03v3_b mosfet (n-varactor)
# cap_pmos_03v3_b mosfet (p-varactor)
# cap_nmos_06v0_b mosfet (n-varactor, high voltage)
# cap_pmos_06v0_b mosfet (p-varactor, high voltage)
#
# cap_mim_2f0fF capacitor (MiM)**,***
#
# efuse fuse
# *Note that the "5V" and "6V" devices are the same device and have the same
# device model. However, a slightly shorter gate length is allowed when
# operating at 5V. The GF standard cell sets use the 5V length. Magic
# will extract the shortest gate length as a "5V" type and everything else
# as "6V", which should allow for clean LVS when using the standard cells.
#
# **Note that there are multiple mutually exclusive process options for the
# high sheet rho resistor and MiM capacitor. This tech file assumes the
# options 1kOhm/sq for the resistor and 2fF/um for the MiM capacitor.
#
# ***The top metal may be any of metal3 to metaltp, depending on the stackup
device msubcircuit pfet_03v3 pfet pdiff,pdc pdiff,pdc allnwell error \
l=l w=w a1=as p1=ps a2=ad p2=pd
device msubcircuit nfet_03v3 nfet ndiff,ndc ndiff,ndc allpsub error \
l=l w=w a1=as p1=ps a2=ad p2=pd
device msubcircuit pfet_03v3 srampfet srampdiff,srampdc srampdiff,srampdc \
allnwell error l=l w=w a1=as p1=ps a2=ad p2=pd
device msubcircuit nfet_03v3 sramnfet sramndiff,sramndc sramndiff,sramndc \
allpsub error l=l w=w a1=as p1=ps a2=ad p2=pd
device msubcircuit pfet_05v0 srammvpfet srammvpdiff,srammvpdc \
srammvpdiff,srammvpdc allnwell error l=l w=w a1=as p1=ps a2=ad p2=pd
device msubcircuit pfet_06v0 hvpfet mvpdiff,mvpdc mvpdiff,mvpdc allnwell error \
l=l w=w a1=as p1=ps a2=ad p2=pd
device msubcircuit pfet_05v0 mvpfet mvpdiff,mvpdc mvpdiff,mvpdc allnwell error \
l=l w=w a1=as p1=ps a2=ad p2=pd
device msubcircuit nfet_05v0 srammvnfet srammvndiff,srammvndc \
srammvndiff,srammvndc allpsub error l=l w=w a1=as p1=ps a2=ad p2=pd
device msubcircuit nfet_05v0 srammvnfet srammvndiff,srammvndc \
srammvndiff,srammvndc allpsub error l=l w=w a1=as p1=ps a2=ad p2=pd
device msubcircuit nfet_06v0 hvnfet mvndiff,mvndc mvndiff,mvndc allpsub error \
l=l w=w a1=as p1=ps a2=ad p2=pd
device msubcircuit nfet_05v0 mvnfet mvndiff,mvndc mvndiff,mvndc allpsub error \
l=l w=w a1=as p1=ps a2=ad p2=pd
device msubcircuit pfet_03v3_dss pfet pdiffres pdiffres allnwell error \
l=l w=w a1=as p1=ps a2=ad p2=pd l1=s_sab l2=d_sab
device msubcircuit nfet_03v3_dss nfet ndiffres ndiffres allpsub error \
l=l w=w a1=as p1=ps a2=ad p2=pd l1=s_sab l2=d_sab
device msubcircuit pfet_06v0_dss hvpfet,mvpfet mvpdiffres mvpdiffres allnwell error \
l=l w=w a1=as p1=ps a2=ad p2=pd l1=s_sab l2=d_sab
device msubcircuit nfet_06v0_dss hvnfet,mvnfet mvndiffres mvndiffres allpsub error \
l=l w=w a1=as p1=ps a2=ad p2=pd l1=s_sab l2=d_sab
device msubcircuit nfet_06v0_nvt mvnnfet mvndiff,mvndiffres,mvndc \
mvndiff,mvndiffres,mvndc allpsub error \
l=l w=w a1=as p1=ps a2=ad p2=pd
device subcircuit cap_nmos_03v3_b nvaractor *nndiff l=c_length w=c_width
device subcircuit cap_nmos_06v0_b mvnvaractor *mvnndiff l=c_length w=c_width
device subcircuit cap_pmos_03v3_b pvaractor *ppdiff l=c_length w=c_width
device subcircuit cap_pmos_06v0_b mvpvaractor *mvppdiff l=c_length w=c_width
device subcircuit cap_pmos_03v3 pcap pdiff,pdc l=c_length w=c_width
device subcircuit cap_nmos_03v3 ncap ndiff,ndc l=c_length w=c_width
device subcircuit cap_pmos_06v0 mvpcap mvpdiff,mvpdc l=c_length w=c_width
device subcircuit cap_nmos_06v0 mvncap mvndiff,mvndc l=c_length w=c_width
device msubcircuit npn_10p00x10p00 npn *ndiff dnwell space/w error a1>99.0 a1<101.0
device msubcircuit npn_05p00x05p00 npn *ndiff dnwell space/w error a1>24.0 a1<26.0
device msubcircuit npn_00p54x16p00 npn *ndiff dnwell space/w error a1>8.5 a1<8.7
device msubcircuit npn_00p54x08p00 npn *ndiff dnwell space/w error a1>4.2 a1<4.4
device msubcircuit npn_00p54x04p00 npn *ndiff dnwell space/w error a1>2.0 a1<2.2
device msubcircuit npn_00p54x02p00 npn *ndiff dnwell space/w error a1>1.0 a1<1.2
device msubcircuit pnp_10p00x00p42 pnp pwell,space/w *pdiff error a2>4.1 a2<4.3
device msubcircuit pnp_05p00x00p42 pnp pwell,space/w *pdiff error a2>2.0 a2<2.2
device msubcircuit pnp_10p00x10p00 pnp pwell,space/w *pdiff error a2>99.0 a2<101.0
device msubcircuit pnp_05p00x05p00 pnp pwell,space/w *pdiff error a2>24.0 a2<26.0
device msubcircuit nfet_10v0_asym mvnfet *mvndiff *ldndiff allpsub error \
l=l w=w a1=as p1=ps a2=ad p2=pd
device msubcircuit pfet_10v0_asym mvpfet *mvpdiff *ldpdiff allnwell error \
l=l w=w a1=as p1=ps a2=ad p2=pd
device rsubcircuit efuse efuse *poly
device rsubcircuit rm1 rm1 *m1 l=r_length w=r_width
device rsubcircuit rm2 rm2 *m2 l=r_length w=r_width
#ifdef METALS4 || METALS5 || METALS6
device rsubcircuit rm3 rm3 *m3 l=r_length w=r_width
#endif (METALS4 || METALS5 || METALS6)
#ifdef METALS5 || METALS6
device rsubcircuit rm4 rm4 *m4 l=r_length w=r_width
#endif (METALS5 || METALS6)
#ifdef METALS6
device rsubcircuit rm5 rm5 *m5 l=r_length w=r_width
#endif (METALS6)
#ifdef THICKMET3P0
#ifdef METALS3
device rsubcircuit tm30k rm3 *m3 l=r_length w=r_width
#elseif defined (METALS4)
device rsubcircuit tm30k rm4 *m4 l=r_length w=r_width
#elseif defined (METALS5)
device rsubcircuit tm30k rm5 *m5 l=r_length w=r_width
#elseif defined (METALS6)
device rsubcircuit tm30k rmtp *mtp l=r_length w=r_width
#endif
#elseif defined (THICKMET1P1)
#ifdef METALS3
device rsubcircuit tm11k rm3 *m3 l=r_length w=r_width
#elseif defined (METALS4)
device rsubcircuit tm11k rm4 *m4 l=r_length w=r_width
#elseif defined (METALS5)
device rsubcircuit tm11k rm5 *m5 l=r_length w=r_width
#elseif defined (METALS6)
device rsubcircuit tm11k rmtp *mtp l=r_length w=r_width
#endif
#elseif defined (THICKMET0P9)
#ifdef METALS3
device rsubcircuit tm9k rm3 *m3 l=r_length w=r_width
#elseif defined (METALS4)
device rsubcircuit tm9k rm4 *m4 l=r_length w=r_width
#elseif defined (METALS5)
device rsubcircuit tm9k rm5 *m5 l=r_length w=r_width
#elseif defined (METALS6)
device rsubcircuit tm9k rmtp *mtp l=r_length w=r_width
#endif
#else (!(THICKMET3P0 || THICKMET1P1 || THICKMET0P9))
#ifdef METALS3
device rsubcircuit tm6k rm3 *m3 l=r_length w=r_width
#elseif defined (METALS4)
device rsubcircuit tm6k rm4 *m4 l=r_length w=r_width
#elseif defined (METALS5)
device rsubcircuit tm6k rm5 *m5 l=r_length w=r_width
#elseif defined (METALS6)
device rsubcircuit tm6k rmtp *mtp l=r_length w=r_width
#endif
#endif (!(THICKMET3P0 || THICKMET1P1 || THICKMET0P9))
device rsubcircuit ppolyf_s rpps *poly allnwell,allpsub error l=r_length w=r_width
device rsubcircuit npolyf_s rnps *poly allnwell,allpsub error l=r_length w=r_width
device rsubcircuit ppolyf_u rpp *poly allnwell,allpsub error l=r_length w=r_width
device rsubcircuit npolyf_u rnp *poly allnwell,allpsub error l=r_length w=r_width
#ifdef HRPOLY1K
device rsubcircuit ppolyf_u_1k hires *poly allnwell,allpsub error l=r_length w=r_width
device rsubcircuit ppolyf_u_1k_6p0 mvhires *poly allnwell,allpsub error l=r_length w=r_width
#endif (HRPOLY1K)
device rsubcircuit pplus_u rpd *pdiff allnwell error l=r_length w=r_width
device rsubcircuit nplus_u rnd *ndiff allpsub error l=r_length w=r_width
device rsubcircuit pplus_s rpds *pdiff allnwell error l=r_length w=r_width
device rsubcircuit nplus_s rnds *ndiff allpsub error l=r_length w=r_width
device rsubcircuit pplus_u mvpdiffres *mvpdiff allnwell error l=r_length w=r_width
device rsubcircuit nplus_u mvndiffres *mvndiff allpsub error l=r_length w=r_width
device rsubcircuit nwell rnw nwell allpsub error l=r_length w=r_width
# The following absorbs the source/drain resistor into a *_dss FET device
device subcircuit Short mvndiffres *mvndiff hvnfet,mvnfet allpsub error
device subcircuit Short mvpdiffres *mvpdiff hvpfet,mvpfet allnwell error
device subcircuit Short ndiffres *ndiff nfet allpsub error
device subcircuit Short pdiffres *pdiff pfet allnwell error
device pdiode diode_pd2nw_03v3 *pdiode allnwell a=area p=pj
device ndiode diode_nd2ps_03v3 *ndiode allpsub a=area p=pj
device pdiode diode_pd2nw_06v0 *mvpdiode allnwell a=area p=pj
device ndiode diode_nd2ps_06v0 *mvndiode allpsub a=area p=pj
device ndiode diode_nd2ps_06v0_nvt *mvnndiode allpsub a=area p=pj
device pdiode sc_diode *schottky *nsd a=area p=pj
#ifdef MIM
#ifdef METALS6
device csubcircuit cap_mim_2f0_m5m6_noshield *mimcap *m5 l=c_length w=c_width
#endif
#ifdef METALS5
device csubcircuit cap_mim_2f0_m4m5_noshield *mimcap *m4 l=c_length w=c_width
#endif
#ifdef METALS4
device csubcircuit cap_mim_2f0_m3m4_noshield *mimcap *m3 l=c_length w=c_width
#endif
#ifdef METALS3
device csubcircuit cap_mim_2f0_m2m3_noshield *mimcap *m2 l=c_length w=c_width
#endif
#endif (MIM)
end
#-----------------------------------------------------
# Wiring tool definitions
#-----------------------------------------------------
wiring
scalefactor 50
contact v1 200 m1 5 45 m2 0 45
#ifdef METALS3 || METALS4 || METALS5 || METALS6
contact v2 200 m2 0 45 m3 0 45
#endif (METALS3 || METALS4 || METALS5 || METALS6)
#ifdef METALS4 || METALS5 || METALS6
contact v3 200 m3 0 45 m4 0 45
#endif (METALS4 || METALS5 || METALS6)
#ifdef METALS5 || METALS6
contact v4 200 m4 0 45 m5 0 45
#endif (METALS5 || METALS6)
#ifdef METALS6
contact vtp 370 m3 0 45 mtp 80 80
#endif (METALS6)
contact pdc 160 pdiff 70 70 m1 45 0
contact ndc 160 ndiff 70 70 m1 45 0
contact psc 160 ppdiff 70 70 m1 45 0
contact nsc 160 nndiff 70 70 m1 45 0
contact pc 160 poly 70 70 m1 45 0
contact mvpdc 160 mvpdiff 70 70 m1 45 0
contact mvndc 160 mvndiff 70 70 m1 45 0
contact mvpsc 160 mvppdiff 70 70 m1 45 0
contact mvnsc 160 mvnndiff 70 70 m1 45 0
end
#-----------------------------------------------------
# Plain old router. . .
#-----------------------------------------------------
router
end
#------------------------------------------------------------
# Plowing (restored in magic 8.2, need to fill this section)
#------------------------------------------------------------
plowing
end
#-----------------------------------------------------------------
# No special plot layers defined (use default PNM color choices)
#-----------------------------------------------------------------
plot
style pnm
default
draw fillblock no_color_at_all
draw nwell cwell
draw pwell cwell
draw dnwell cwell
end