Added liberty files for a number of the I/O pad cells, mainly to cover the set used
on the caravel chip design, including the sky130_ef_io set. This supports the new
capability of Openlane to do top-level timing analysis.
diff --git a/sky130/Makefile.in b/sky130/Makefile.in
index e742eaf..7a76c97 100644
--- a/sky130/Makefile.in
+++ b/sky130/Makefile.in
@@ -1013,6 +1013,7 @@
-verilog %l/verilog/*.v compile-only rename=sky130_ef_io \
-cdl %l/cdl/*.cdl \
-spice %l/spice/*.spice \
+ -lib %l/lib/*.lib \
-gds %l/gds/*.gds options=custom/scripts/gds_import_setup.tcl \
-lef %l/lef/*.lef exclude=sky130_fd_io__top_xres4v2.lef \
compile-only rename=sky130_ef_io \
