sky130: split LIB into CELL_LIBS and PAD_LIBS, add views for slices Signed-off-by: Leo Moser <leomoser99@gmail.com>
diff --git a/sky130/custom/sky130_fd_io/cdl/sky130_ef_io.cdl b/sky130/custom/sky130_fd_io/cdl/sky130_ef_io.cdl index c0f0d2a..e0e2c6b 100644 --- a/sky130/custom/sky130_fd_io/cdl/sky130_ef_io.cdl +++ b/sky130/custom/sky130_fd_io/cdl/sky130_ef_io.cdl
@@ -324,6 +324,18 @@ .ENDS *---------------------------------------------------------- +* sky130_ef_io__connect_vdda_vddio_and_vssa_vssio_slice_20um +* A 20um-wide padframe filler that connects VDDA and VDDIO as well as +* VSSA and VSSIO +*---------------------------------------------------------- + +.SUBCKT sky130_ef_io__connect_vdda_vddio_and_vssa_vssio_slice_20um ++ AMUXBUS_A AMUXBUS_B ++ VSSA VDDA VDDIO_Q VDDIO VCCD VSSIO VSSD VSSIO_Q +* Bus filler has no active circuitry +.ENDS + +*---------------------------------------------------------- * sky130_ef_io__disconnect_vdda_slice_5um * A 5um-wide padframe filler that doesn't connect VDDA * through it
diff --git a/sky130/custom/sky130_fd_io/gds/sky130_ef_io__connect_vdda_vddio_and_vssa_vssio_slice_20um.gds b/sky130/custom/sky130_fd_io/gds/sky130_ef_io__connect_vdda_vddio_and_vssa_vssio_slice_20um.gds new file mode 100644 index 0000000..ddb8b8e --- /dev/null +++ b/sky130/custom/sky130_fd_io/gds/sky130_ef_io__connect_vdda_vddio_and_vssa_vssio_slice_20um.gds Binary files differ
diff --git a/sky130/custom/sky130_fd_io/lef/sky130_ef_io__connect_vdda_vddio_and_vssa_vssio_slice_20um.lef b/sky130/custom/sky130_fd_io/lef/sky130_ef_io__connect_vdda_vddio_and_vssa_vssio_slice_20um.lef new file mode 100644 index 0000000..225511b --- /dev/null +++ b/sky130/custom/sky130_fd_io/lef/sky130_ef_io__connect_vdda_vddio_and_vssa_vssio_slice_20um.lef
@@ -0,0 +1,191 @@ +VERSION 5.7 ; + NOWIREEXTENSIONATPIN ON ; + DIVIDERCHAR "/" ; + BUSBITCHARS "[]" ; +MACRO sky130_ef_io__connect_vdda_vddio_and_vssa_vssio_slice_20um + CLASS PAD AREAIO ; + FOREIGN sky130_ef_io__connect_vdda_vddio_and_vssa_vssio_slice_20um ; + ORIGIN 0.000 0.000 ; + SIZE 20.000 BY 197.965 ; + PIN AMUXBUS_A + DIRECTION INOUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 0.000 51.090 20.000 54.070 ; + END + END AMUXBUS_A + PIN AMUXBUS_B + DIRECTION INOUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 0.000 46.330 20.000 49.310 ; + END + END AMUXBUS_B + PIN VSSA + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER met5 ; + RECT 0.000 45.700 20.000 54.700 ; + END + PORT + LAYER met4 ; + RECT 0.000 54.370 20.000 54.700 ; + END + PORT + LAYER met4 ; + RECT 0.000 45.700 20.000 46.030 ; + END + PORT + LAYER met5 ; + RECT 0.000 34.800 20.000 38.050 ; + END + PORT + LAYER met4 ; + RECT 0.000 34.700 20.000 38.150 ; + END + PORT + LAYER met3 ; + RECT 0.990 23.910 19.000 38.045 ; + LAYER via3 ; + RECT 1.215 35.125 18.615 37.725 ; + RECT 1.525 24.215 18.525 28.015 ; + END + END VSSA + PIN VDDA + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER met5 ; + RECT 0.000 13.000 20.000 16.250 ; + END + PORT + LAYER met4 ; + RECT 0.000 12.900 20.000 16.350 ; + END + PORT + LAYER met3 ; + RECT 0.990 13.005 19.000 22.290 ; + LAYER via3 ; + RECT 1.525 18.185 18.525 21.985 ; + RECT 1.525 13.320 18.525 15.920 ; + END + END VDDA + PIN VSWITCH + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER met5 ; + RECT 0.000 29.950 20.000 33.200 ; + END + PORT + LAYER met4 ; + RECT 0.000 29.850 20.000 33.300 ; + END + END VSWITCH + PIN VDDIO_Q + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER met5 ; + RECT 0.000 62.150 20.000 66.400 ; + END + PORT + LAYER met4 ; + RECT 0.000 62.050 20.000 66.500 ; + END + END VDDIO_Q + PIN VCCHIB + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER met5 ; + RECT 0.000 0.100 20.000 5.350 ; + END + PORT + LAYER met4 ; + RECT 0.000 0.000 20.000 5.450 ; + END + END VCCHIB + PIN VDDIO + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER met5 ; + RECT 0.000 68.000 20.000 92.950 ; + END + PORT + LAYER met4 ; + RECT 0.000 68.000 20.000 92.965 ; + END + PORT + LAYER met5 ; + RECT 0.000 17.850 20.000 22.300 ; + END + PORT + LAYER met4 ; + RECT 0.000 17.750 20.000 22.400 ; + END + END VDDIO + PIN VCCD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER met5 ; + RECT 0.000 6.950 20.000 11.400 ; + END + PORT + LAYER met4 ; + RECT 0.000 6.850 20.000 11.500 ; + END + END VCCD + PIN VSSIO + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER met5 ; + RECT 0.000 23.900 20.000 28.350 ; + END + PORT + LAYER met4 ; + RECT 0.000 23.800 20.000 28.450 ; + END + PORT + LAYER met5 ; + RECT 0.000 173.750 20.000 197.965 ; + END + END VSSIO + PIN VSSD + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER met5 ; + RECT 0.000 39.650 20.000 44.100 ; + END + PORT + LAYER met4 ; + RECT 0.000 39.550 20.000 44.200 ; + END + END VSSD + PIN VSSIO_Q + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER met5 ; + RECT 0.000 56.300 20.000 60.550 ; + END + PORT + LAYER met4 ; + RECT 0.000 56.200 20.000 60.650 ; + END + END VSSIO_Q + OBS + LAYER met4 ; + RECT 0.000 173.750 20.000 197.965 ; + RECT 0.000 49.610 20.000 50.790 ; + END +END sky130_ef_io__connect_vdda_vddio_and_vssa_vssio_slice_20um +END LIBRARY +
diff --git a/sky130/custom/sky130_fd_io/lib/slices_stubs.lib b/sky130/custom/sky130_fd_io/lib/slices_stubs.lib new file mode 100644 index 0000000..35765ea --- /dev/null +++ b/sky130/custom/sky130_fd_io/lib/slices_stubs.lib
@@ -0,0 +1,240 @@ +/** + * Copyright 2020 The SkyWater PDK Authors + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * https://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + */ +library ("slices_stubs") { + define(three_state_pullup_res,library,string); + define(three_state_pulldn_res,library,string); + define(zstate_leak_threshold_pct,library,string); + define(clk_width,library,string); + define(driver_model,library,string); + define(def_sim_opt,library,string); + define(simulator,library,string); + define(signal_voltage_type,pin,string); + technology("cmos"); + delay_model : "table_lookup"; + revision : "1.0"; + date : "localtime"; + default_leakage_power_density : 0.000000; + default_cell_leakage_power : 0.000000; + default_fanout_load : 0.000000; + default_inout_pin_cap : 0.000000; + default_input_pin_cap : 0.000000; + default_output_pin_cap : 0.000000; + default_max_transition : 1.500000; + bus_naming_style : "%s[%d]"; + in_place_swap_mode : "match_footprint"; + library_features("report_delay_calculation"); + voltage_unit : "1V"; + current_unit : "1mA"; + leakage_power_unit : "1nW"; + pulling_resistance_unit : "1kohm"; + time_unit : "1ns"; + resistance_unit : "1ohm"; + capacitive_load_unit(1.000000, \ + "pf"); + input_threshold_pct_rise : 50.000000; + input_threshold_pct_fall : 50.000000; + output_threshold_pct_rise : 50.000000; + output_threshold_pct_fall : 50.000000; + slew_lower_threshold_pct_fall : 20.000000; + slew_lower_threshold_pct_rise : 20.000000; + slew_upper_threshold_pct_fall : 80.000000; + slew_upper_threshold_pct_rise : 80.000000; + slew_derate_from_library : 1.000000; + three_state_pullup_res : "1"; + three_state_pulldn_res : "1"; + zstate_leak_threshold_pct : "0.1"; + clk_width : "1.00E-05"; + def_sim_opt : "POST=1 PROBE POST_VERSION=2001 STATFL=1 BRIEF=1 LISLVL=1 INGOLD=2 NOMOD NOPAGE NUMDGT=10 MEASDGT=10 AUTOSTOP SYMB=1 ALTCC=1 RUNLVL=5 ACCURATE=1 "; + simulator : "HSPICE -- H-2013.03 64-BIT (Feb 27 2013)"; + voltage_map("VSS",0.000000); + voltage_map("VCCD",1.950000); + voltage_map("VCCHIB",1.950000); + voltage_map("VDDA",5.500000); + voltage_map("VDDIO",5.500000); + voltage_map("VDDIO_Q",5.500000); + voltage_map("VSSA",0.000000); + voltage_map("VSSD",0.000000); + voltage_map("VSSIO",0.000000); + voltage_map("VSSIO_Q",0.000000); + voltage_map("VSWITCH",5.500000); + cell ("sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um") { + is_macro_cell : true; + dont_use : true; + interface_timing : true; + pad_cell : true; + dont_touch : true; + area : 15000.000000; + + /* Power Supply Pins */ + + pg_pin (VDDA) { + voltage_name : VDDA ; + pg_type : primary_power ; + } + + pg_pin (VSWITCH) { + voltage_name : VSWITCH ; + pg_type : primary_power ; + } + + pg_pin (VDDIO) { + voltage_name : VDDIO ; + pg_type : primary_power ; + } + + pg_pin (VDDIO_Q) { + voltage_name : VDDIO_Q ; + pg_type : primary_power ; + } + + pg_pin (VCCD) { + voltage_name : VCCD ; + pg_type : primary_power ; + } + + pg_pin (VCCHIB) { + voltage_name : VCCHIB ; + pg_type : primary_power ; + } + + /* Ground Pins */ + + pg_pin (VSSD) { + voltage_name : VSSD ; + pg_type : primary_ground ; + } + + pg_pin (VSSIO_Q) { + voltage_name : VSSIO_Q ; + pg_type : primary_ground ; + } + + pg_pin (VSSA) { + voltage_name : VSSA ; + pg_type : primary_ground ; + } + + pg_pin (VSSIO) { + voltage_name : VSSIO ; + pg_type : primary_ground ; + } + + /* Analog Pins */ + + pin ("AMUXBUS_A") { + direction : inout; + related_power_pin : VDDIO; + related_ground_pin : VSSD; + always_on : true; + signal_voltage_type : "analog"; + capacitance : 0.070467; + } + + pin ("AMUXBUS_B") { + direction : inout; + related_power_pin : VDDIO; + related_ground_pin : VSSD; + always_on : true; + signal_voltage_type : "analog"; + capacitance : 0.070467; + } + } + + cell ("sky130_ef_io__connect_vdda_vddio_and_vssa_vssio_slice_20um") { + is_macro_cell : true; + dont_use : true; + interface_timing : true; + pad_cell : true; + dont_touch : true; + area : 15000.000000; + + /* Power Supply Pins */ + + pg_pin (VDDA) { + voltage_name : VDDA ; + pg_type : primary_power ; + } + + pg_pin (VSWITCH) { + voltage_name : VSWITCH ; + pg_type : primary_power ; + } + + pg_pin (VDDIO) { + voltage_name : VDDIO ; + pg_type : primary_power ; + } + + pg_pin (VDDIO_Q) { + voltage_name : VDDIO_Q ; + pg_type : primary_power ; + } + + pg_pin (VCCD) { + voltage_name : VCCD ; + pg_type : primary_power ; + } + + pg_pin (VCCHIB) { + voltage_name : VCCHIB ; + pg_type : primary_power ; + } + + /* Ground Pins */ + + pg_pin (VSSD) { + voltage_name : VSSD ; + pg_type : primary_ground ; + } + + pg_pin (VSSIO_Q) { + voltage_name : VSSIO_Q ; + pg_type : primary_ground ; + } + + pg_pin (VSSA) { + voltage_name : VSSA ; + pg_type : primary_ground ; + } + + pg_pin (VSSIO) { + voltage_name : VSSIO ; + pg_type : primary_ground ; + } + + /* Analog Pins */ + + pin ("AMUXBUS_A") { + direction : inout; + related_power_pin : VDDIO; + related_ground_pin : VSSD; + always_on : true; + signal_voltage_type : "analog"; + capacitance : 0.070467; + } + + pin ("AMUXBUS_B") { + direction : inout; + related_power_pin : VDDIO; + related_ground_pin : VSSD; + always_on : true; + signal_voltage_type : "analog"; + capacitance : 0.070467; + } + } +}
diff --git a/sky130/custom/sky130_fd_io/verilog/sky130_ef_io.v b/sky130/custom/sky130_fd_io/verilog/sky130_ef_io.v index 8b7c228..b078c43 100644 --- a/sky130/custom/sky130_fd_io/verilog/sky130_ef_io.v +++ b/sky130/custom/sky130_fd_io/verilog/sky130_ef_io.v
@@ -9,6 +9,28 @@ // Written by Tim Edwards //----------------------------------------------------------------------- +module sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um(VCCHIB, VCCD, VSWITCH, VDDIO); + inout VCCHIB; + inout VCCD; + inout VSWITCH; + inout VDDIO; + + assign VCCHIB = VCCD; + assign VSWITCH = VDDIO; + +endmodule + +module sky130_ef_io__connect_vdda_vddio_and_vssa_vssio_slice_20um(VDDA, VDDIO, VSSA, VSSIO); + inout VDDA; + inout VDDIO; + inout VSSA; + inout VSSIO; + + assign VDDA = VDDIO; + assign VSSA = VSSIO; + +endmodule + module sky130_ef_io__vccd_hvc_pad (AMUXBUS_A, AMUXBUS_B, DRN_HVC, SRC_BDY_HVC, VSSA, VDDA, VSWITCH, VDDIO_Q, VCCHIB, VDDIO, VCCD, VCCD_PAD, VSSIO, VSSD, VSSIO_Q
diff --git a/sky130/librelane/config.tcl b/sky130/librelane/config.tcl index 0d3973c..6f92d9a 100755 --- a/sky130/librelane/config.tcl +++ b/sky130/librelane/config.tcl
@@ -66,14 +66,19 @@ set ::env(CELL_CDLS) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/cdl/$::env(STD_CELL_LIBRARY).cdl" # Pad cells -set ::env(PAD_LEFS) [glob "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(PAD_CELL_LIBRARY)/lef/*.lef"] +set ::env(PAD_LEFS) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lef/sky130_ef_io.lef" set ::env(PAD_GDS) "\ - $::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(PAD_CELL_LIBRARY)/gds/sky130_fd_io.gds \ - $::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(PAD_CELL_LIBRARY)/gds/sky130_ef_io.gds \ + $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/gds/sky130_fd_io.gds\ + $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/gds/sky130_ef_io.gds\ + $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/gds/sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um.gds\ + $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/gds/sky130_ef_io__connect_vdda_vddio_and_vssa_vssio_slice_20um.gds\ " -set ::env(PAD_VERILOG_MODELS) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(PAD_CELL_LIBRARY)/verilog/$::env(PAD_CELL_LIBRARY)__blackbox_pp.v" -set ::env(PAD_SPICE_MODELS) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(PAD_CELL_LIBRARY)/spice/$::env(PAD_CELL_LIBRARY).spice" -set ::env(PAD_CDLS) [glob "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(PAD_CELL_LIBRARY)/cdl/*.cdl"] +set ::env(PAD_VERILOG_MODELS) "\ + $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/verilog/sky130_fd_io__blackbox_pp.v\ + $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/verilog/sky130_ef_io.v\ +" +#set ::env(PAD_SPICE_MODELS) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/spice/$::env(PAD_CELL_LIBRARY).spice" +set ::env(PAD_CDLS) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/cdl/sky130_ef_io.cdl" # magic setup set ::env(MAGIC_MAGICRC) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/magic/TECHNAME.magicrc" @@ -129,27 +134,27 @@ } # Extra PDN configs -set ::env(FP_PDN_RAIL_LAYER) met1 -set ::env(FP_PDN_VERTICAL_LAYER) met4 -set ::env(FP_PDN_HORIZONTAL_LAYER) met5 -set ::env(FP_PDN_RAIL_OFFSET) 0 -set ::env(FP_PDN_VWIDTH) 1.6 -set ::env(FP_PDN_HWIDTH) 1.6 -set ::env(FP_PDN_VSPACING) 1.7 -set ::env(FP_PDN_HSPACING) 1.7 -set ::env(FP_PDN_VOFFSET) 16.32 -set ::env(FP_PDN_VPITCH) 153.6 -set ::env(FP_PDN_HOFFSET) 16.65 -set ::env(FP_PDN_HPITCH) 153.18 +set ::env(PDN_RAIL_LAYER) met1 +set ::env(PDN_VERTICAL_LAYER) met4 +set ::env(PDN_HORIZONTAL_LAYER) met5 +set ::env(PDN_RAIL_OFFSET) 0 +set ::env(PDN_VWIDTH) 1.6 +set ::env(PDN_HWIDTH) 1.6 +set ::env(PDN_VSPACING) 1.7 +set ::env(PDN_HSPACING) 1.7 +set ::env(PDN_VOFFSET) 16.32 +set ::env(PDN_VPITCH) 153.6 +set ::env(PDN_HOFFSET) 16.65 +set ::env(PDN_HPITCH) 153.18 # Core Ring PDN defaults -set ::env(FP_PDN_CORE_RING_VWIDTH) 1.6 -set ::env(FP_PDN_CORE_RING_HWIDTH) 1.6 -set ::env(FP_PDN_CORE_RING_VSPACING) 1.7 -set ::env(FP_PDN_CORE_RING_HSPACING) 1.7 -set ::env(FP_PDN_CORE_RING_VOFFSET) 6 -set ::env(FP_PDN_CORE_RING_HOFFSET) 6 +set ::env(PDN_CORE_RING_VWIDTH) 1.6 +set ::env(PDN_CORE_RING_HWIDTH) 1.6 +set ::env(PDN_CORE_RING_VSPACING) 1.7 +set ::env(PDN_CORE_RING_HSPACING) 1.7 +set ::env(PDN_CORE_RING_VOFFSET) 6 +set ::env(PDN_CORE_RING_HOFFSET) 6 # PDN Macro blockages list set ::env(MACRO_BLOCKAGES_LAYER) "li1 met1 met2 met3 met4"
diff --git a/sky130/librelane/sky130_ef_io/config.tcl b/sky130/librelane/sky130_ef_io/config.tcl index 0a214a1..6fd9c02 100644 --- a/sky130/librelane/sky130_ef_io/config.tcl +++ b/sky130/librelane/sky130_ef_io/config.tcl
@@ -26,13 +26,28 @@ # Technology lib set ::env(PAD_LIBS) [dict create] dict set ::env(PAD_LIBS) "*_tt_025C_1v80" "\ - [glob $::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(PAD_CELL_LIBRARY)/lib/$::env(PAD_CELL_LIBRARY)__*_tt_025C_1v80_3v30*.lib] \ + $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib \ + $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped_pad_tt_025C_1v80_3v30.lib \ + $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vddio_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib \ + $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssio_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib \ + $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_tt_tt_025C_1v80_3v30.lib \ + $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/slices_stubs.lib \ " dict set ::env(PAD_LIBS) "*_ff_n40C_1v95" "\ - [glob $::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(PAD_CELL_LIBRARY)/lib/$::env(PAD_CELL_LIBRARY)__*_ff_n40C_1v95_5v50*.lib] \ + $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped_pad_ff_n40C_1v95_5v50_5v50.lib \ + $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped_pad_ff_n40C_1v95_5v50.lib \ + $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vddio_hvc_clamped_pad_ff_n40C_1v95_5v50_5v50.lib \ + $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssio_hvc_clamped_pad_ff_n40C_1v95_5v50_5v50.lib \ + $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_ff_ff_n40C_1v95_5v50.lib \ + $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/slices_stubs.lib \ " dict set ::env(PAD_LIBS) "*_ss_100C_1v60" "\ - [glob $::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(PAD_CELL_LIBRARY)/lib/$::env(PAD_CELL_LIBRARY)__*_ss_100C_1v60_3v00*.lib] \ + $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped_pad_ss_100C_1v60_3v00_3v00.lib \ + $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped_pad_ss_100C_1v60_3v00.lib \ + $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vddio_hvc_clamped_pad_ss_100C_1v60_3v00_3v00.lib \ + $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssio_hvc_clamped_pad_ss_100C_1v60_3v00_3v00.lib \ + $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_ss_ss_100C_1v60_3v00.lib \ + $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/slices_stubs.lib \ " # Pad bondpad information (if needed) @@ -44,12 +59,11 @@ # Pad io terminals (if needed) set ::env(PAD_PLACE_IO_TERMINALS) "\ - sky130_fd_io__top_gpiov2/PAD\ sky130_ef_io__gpiov2_pad/PAD\ - sky130_ef_io__vccd_lvc_pad/VCCD_PAD\ - sky130_ef_io__vssd_lvc_pad/VSSD_PAD\ - sky130_ef_io__vddio_lvc_pad/VDDIO_PAD\ - sky130_ef_io__vssio_lvc_pad/VSSIO_PAD\ + sky130_ef_io__vccd_lvc_clamped_pad/VCCD_PAD\ + sky130_ef_io__vssd_lvc_clamped_pad/VSSD_PAD\ + sky130_ef_io__vddio_hvc_clamped_pad/VDDIO_PAD\ + sky130_ef_io__vssio_hvc_clamped_pad/VSSIO_PAD\ " # Sealring is added afterwards
diff --git a/sky130/librelane/sky130_fd_sc_hd/config.tcl b/sky130/librelane/sky130_fd_sc_hd/config.tcl index edf96fa..a6739da 100755 --- a/sky130/librelane/sky130_fd_sc_hd/config.tcl +++ b/sky130/librelane/sky130_fd_sc_hd/config.tcl
@@ -31,9 +31,6 @@ set ::env(CTS_ROOT_BUFFER) sky130_fd_sc_hd__clkbuf_16 set ::env(CELL_CLK_PORT) CLK -# Placement defaults -set ::env(PL_LIB) $::env(LIB_TYPICAL) - # Fillcell insertion set ::env(FILL_CELL) "sky130_fd_sc_hd__fill_2 sky130_fd_sc_hd__fill_1" set ::env(DECAP_CELL) "sky130_fd_sc_hd__decap_3"
diff --git a/sky130/librelane/sky130_fd_sc_hdll/config.tcl b/sky130/librelane/sky130_fd_sc_hdll/config.tcl index 3bd0830..dfe3848 100755 --- a/sky130/librelane/sky130_fd_sc_hdll/config.tcl +++ b/sky130/librelane/sky130_fd_sc_hdll/config.tcl
@@ -28,9 +28,6 @@ set ::env(CTS_ROOT_BUFFER) sky130_fd_sc_hdll__clkbuf_16 set ::env(CELL_CLK_PORT) CLK -# Placement defaults -set ::env(PL_LIB) $::env(LIB_TYPICAL) - # Fillcell insertion set ::env(FILL_CELL) "sky130_fd_sc_hdll__fill*" set ::env(DECAP_CELL) "sky130_fd_sc_hdll__decap*"
diff --git a/sky130/librelane/sky130_fd_sc_hs/config.tcl b/sky130/librelane/sky130_fd_sc_hs/config.tcl index 467fc6f..74f561d 100755 --- a/sky130/librelane/sky130_fd_sc_hs/config.tcl +++ b/sky130/librelane/sky130_fd_sc_hs/config.tcl
@@ -31,9 +31,6 @@ set ::env(CTS_ROOT_BUFFER) sky130_fd_sc_hs__clkbuf_16 set ::env(CELL_CLK_PORT) CLK -# Placement defaults -set ::env(PL_LIB) $::env(LIB_TYPICAL) - # Fillcell insertion set ::env(FILL_CELL) "sky130_fd_sc_hs__fill*" set ::env(DECAP_CELL) "sky130_fd_sc_hs__decap_4"
diff --git a/sky130/librelane/sky130_fd_sc_hvl/config.tcl b/sky130/librelane/sky130_fd_sc_hvl/config.tcl index 753090e..665abac 100644 --- a/sky130/librelane/sky130_fd_sc_hvl/config.tcl +++ b/sky130/librelane/sky130_fd_sc_hvl/config.tcl
@@ -61,9 +61,6 @@ set ::env(CTS_ROOT_BUFFER) sky130_fd_sc_hvl__buf_16 set ::env(CELL_CLK_PORT) CLK -# Placement defaults -set ::env(PL_LIB) $::env(LIB_TYPICAL) - # Fillcell insertion set ::env(FILL_CELL) "sky130_fd_sc_hvl__fill*" set ::env(DECAP_CELL) "sky130_fd_sc_hvl__decap*"
diff --git a/sky130/librelane/sky130_fd_sc_ls/config.tcl b/sky130/librelane/sky130_fd_sc_ls/config.tcl index 57baf56..ae39c67 100755 --- a/sky130/librelane/sky130_fd_sc_ls/config.tcl +++ b/sky130/librelane/sky130_fd_sc_ls/config.tcl
@@ -31,9 +31,6 @@ set ::env(CTS_ROOT_BUFFER) sky130_fd_sc_ls__clkbuf_16 set ::env(CELL_CLK_PORT) CLK -# Placement defaults -set ::env(PL_LIB) $::env(LIB_TYPICAL) - # Fillcell insertion set ::env(FILL_CELL) "sky130_fd_sc_ls__fill*" set ::env(DECAP_CELL) "sky130_fd_sc_ls__decap*"
diff --git a/sky130/librelane/sky130_fd_sc_ms/config.tcl b/sky130/librelane/sky130_fd_sc_ms/config.tcl index dd28eda..4bdb802 100755 --- a/sky130/librelane/sky130_fd_sc_ms/config.tcl +++ b/sky130/librelane/sky130_fd_sc_ms/config.tcl
@@ -31,9 +31,6 @@ set ::env(CTS_ROOT_BUFFER) sky130_fd_sc_ms__clkbuf_16 set ::env(CELL_CLK_PORT) CLK -# Placement defaults -set ::env(PL_LIB) $::env(LIB_TYPICAL) - # Fillcell insertion set ::env(FILL_CELL) "sky130_fd_sc_ms__fill*" set ::env(DECAP_CELL) "sky130_fd_sc_ms__decap_4"
diff --git a/sky130/librelane/sky130_osu_sc_t18/config.tcl b/sky130/librelane/sky130_osu_sc_t18/config.tcl index 2d94031..04d1033 100755 --- a/sky130/librelane/sky130_osu_sc_t18/config.tcl +++ b/sky130/librelane/sky130_osu_sc_t18/config.tcl
@@ -57,9 +57,6 @@ set ::env(CTS_ROOT_BUFFER) CLKBUFX1 set ::env(CELL_CLK_PORT) CK -# Placement defaults -set ::env(PL_LIB) $::env(LIB_TYPICAL) - # Fillcell insertion - do decap cell set ::env(FILL_CELL) "FILLX" set ::env(DECAP_CELL) ""