Added netlists for the analog pads introduced (as layout) in the last commit,
and collected the analog pad netlists into a single file. Added scripts to
modify the SkyWater layouts for the low-voltage clamp power and ground pads
in the same was as was previously done for the high-voltage clamp pads, which
is to isolate the connection to VDDIO_Q or VSSIO_Q with a metal 3 resistor
ring so that the "quiet" busses remain separated for LVS. Modified existing
netlists to account for the addition of the two extra isolated pad pins
inside the metal 3 resistor ring.
diff --git a/VERSION b/VERSION
index 82d479a..144afd4 100644
--- a/VERSION
+++ b/VERSION
@@ -1 +1 @@
-1.0.410
+1.0.411
diff --git a/sky130/Makefile.in b/sky130/Makefile.in
index a965766..f3d269c 100644
--- a/sky130/Makefile.in
+++ b/sky130/Makefile.in
@@ -1410,6 +1410,30 @@
./custom/scripts/fix_vssio_overlay_gds.py \
${STAGING_PATH}/${SKY130$*}/libs.ref/${IO_GDS}/sky130_fd_io__overlay_vssio_hvc.gds
+ # Copy the GDS file for the LVC power pad, then run the script that fixes it.
+ cp ${SKYWATER_LIBS_PATH}/sky130_fd_io/latest/cells/top_power_lvc_wpad/sky130_fd_io__top_power_lvc_wpad.gds \
+ ${STAGING_PATH}/${SKY130$*}/libs.ref/${IO_GDS}
+ ./custom/scripts/fix_vddio_lvc_gds.py \
+ ${STAGING_PATH}/${SKY130$*}/libs.ref/${IO_GDS}/sky130_fd_io__top_power_lvc_wpad.gds
+
+ # Copy the GDS file for the LVC power pad overlay, then run the script that fixes it.
+ cp ${SKYWATER_LIBS_PATH}/sky130_fd_io/latest/cells/overlay_vddio_lvc/sky130_fd_io__overlay_vddio_lvc.gds \
+ ${STAGING_PATH}/${SKY130$*}/libs.ref/${IO_GDS}
+ ./custom/scripts/fix_vddio_overlay_lvc.py \
+ ${STAGING_PATH}/${SKY130$*}/libs.ref/${IO_GDS}/sky130_fd_io__overlay_vddio_lvc.gds
+
+ # Copy the GDS file for the LVC ground pad, then run the script that fixes it.
+ cp ${SKYWATER_LIBS_PATH}/sky130_fd_io/latest/cells/top_ground_lvc_wpad/sky130_fd_io__top_ground_lvc_wpad.gds \
+ ${STAGING_PATH}/${SKY130$*}/libs.ref/${IO_GDS}
+ ./custom/scripts/fix_vssio_lvc_gds.py \
+ ${STAGING_PATH}/${SKY130$*}/libs.ref/${IO_GDS}/sky130_fd_io__top_ground_lvc_wpad.gds
+
+ # Copy the GDS file for the LVC ground pad overlay, then run the script that fixes it.
+ cp ${SKYWATER_LIBS_PATH}/sky130_fd_io/latest/cells/overlay_vssio_lvc/sky130_fd_io__overlay_vssio_lvc.gds \
+ ${STAGING_PATH}/${SKY130$*}/libs.ref/${IO_GDS}
+ ./custom/scripts/fix_vssio_overlay_lvc.py \
+ ${STAGING_PATH}/${SKY130$*}/libs.ref/${IO_GDS}/sky130_fd_io__overlay_vssio_lvc.gds
+
# Install SkyWater I/O pad library
${STAGE} -source ${SKYWATER_LIBS_PATH} -target ${STAGING_PATH}/${SKY130$*} \
-cdl %l/latest/cells/*/*.cdl ignore=topography compile-only \
@@ -1426,8 +1450,8 @@
-gds %l/latest/cells/*/*.gds compile-only \
sort=../common/sort_pdkfiles.py \
options=custom/scripts/gds_import_io.tcl \
- no-copy=sky130_fd_io__top_gpiov2.gds,sky130_fd_io__top_ground_hvc_wpad.gds,sky130_fd_io__top_power_hvc_wpadv2.gds,sky130_fd_io__overlay_vssio_hvc.gds,sky130_fd_io__overlay_vddio_hvc.gds \
- include=sky130_fd_io__top_gpiov2.gds,sky130_fd_io__top_ground_hvc_wpad.gds,sky130_fd_io__top_power_hvc_wpadv2.gds,sky130_fd_io__overlay_vssio_hvc.gds,sky130_fd_io__overlay_vddio_hvc.gds \
+ no-copy=sky130_fd_io__top_gpiov2.gds,sky130_fd_io__top_ground_hvc_wpad.gds,sky130_fd_io__top_power_hvc_wpadv2.gds,sky130_fd_io__overlay_vssio_hvc.gds,sky130_fd_io__overlay_vddio_hvc.gds,sky130_fd_io__top_ground_lvc_wpad.gds,sky130_fd_io__top_power_lvc_wpad.gds,sky130_fd_io__overlay_vssio_lvc.gds,sky130_fd_io__overlay_vddio_lvc.gds \
+ include=sky130_fd_io__top_gpiov2.gds,sky130_fd_io__top_ground_hvc_wpad.gds,sky130_fd_io__top_power_hvc_wpadv2.gds,sky130_fd_io__overlay_vssio_hvc.gds,sky130_fd_io__overlay_vddio_hvc.gds,sky130_fd_io__top_ground_lvc_wpad.gds,sky130_fd_io__top_power_lvc_wpad.gds,sky130_fd_io__overlay_vssio_lvc.gds,sky130_fd_io__overlay_vddio_lvc.gds \
-verilog %l/latest/cells/*/*.*.v \
-verilog %l/latest/cells/*/*.v exclude=*.*.v,sky130_ef_io.v \
compile-only filter=custom/scripts/inc_verilog.py \
diff --git a/sky130/custom/scripts/fix_vddio_lvc_gds.py b/sky130/custom/scripts/fix_vddio_lvc_gds.py
new file mode 100755
index 0000000..5da6b8f
--- /dev/null
+++ b/sky130/custom/scripts/fix_vddio_lvc_gds.py
@@ -0,0 +1,72 @@
+#!/usr/bin/env python3
+#
+# fix_vddio_lvc_gds.py ---
+#
+# Special-purpose script that does the work of what ought to be a simple
+# binary diff and patch. Except that no such thing exists as a standard
+# offering on most Linux systems, so instead of adding another OS
+# package requirement, I'm just writing a binary search-and-replace in
+# python.
+#
+# The purpose of the patch is to add metal3 resistor ID markers to the
+# sky130_fd_io__hvc_clampv2 cell. Also add label for PADISOL|R
+# in the isolated metal3 region formed by the resistors, in the
+# sky130_fd_io__top_power_lvc_wpad cell.
+#
+
+import sys
+
+if len(sys.argv) != 2:
+ print('Usage: fix_vddio_pad_gds.py <filename>')
+ sys.exit(1)
+else:
+ file_name = sys.argv[1]
+
+# Metal 3 resistor at (0.505um 61.12um 24.485um 61.56um)
+add_data_1 = b'\x00\x04\x08\x00\x00\x06\x0d\x02\x00\x46\x00\x06\x0e\x02\x00\x0d\x00\x2c\x10\x03\x00\x00\x01\xf9\x00\x00\xee\xc0\x00\x00\x5f\xa5\x00\x00\xee\xc0\x00\x00\x5f\xa5\x00\x00\xf0\x78\x00\x00\x01\xf9\x00\x00\xf0\x78\x00\x00\x01\xf9\x00\x00\xee\xc0\x00\x04\x11\x00'
+
+# Metal 3 resistor at (50.40um 61.12um 74.64um 61.56um)
+add_data_2 = b'\x00\x04\x08\x00\x00\x06\x0d\x02\x00\x46\x00\x06\x0e\x02\x00\x0d\x00\x2c\x10\x03\x00\x00\xc4\xe0\x00\x00\xee\xc0\x00\x01\x23\x90\x00\x00\xee\xc0\x00\x01\x23\x90\x00\x00\xf0\x78\x00\x00\xc4\xe0\x00\x00\xf0\x78\x00\x00\xc4\xe0\x00\x00\xee\xc0\x00\x04\x11\x00'
+
+# Metal 3 resistor at (24.475um 61.56um 24.485um 67.07um)
+add_data_3 = b'\x00\x04\x08\x00\x00\x06\x0d\x02\x00\x46\x00\x06\x0e\x02\x00\x0d\x00\x2c\x10\x03\x00\x00\x5f\x9b\x00\x00\xf0\x78\x00\x00\x5f\xa5\x00\x00\xf0\x78\x00\x00\x5f\xa5\x00\x01\x05\xfe\x00\x00\x5f\x9b\x00\x01\x05\xfe\x00\x00\x5f\x9b\x00\x00\xf0\x78\x00\x04\x11\x00'
+
+# Metal 3 resistor at (0.505um 61.56um 0.515um 67.07um)
+add_data_4 = b'\x00\x04\x08\x00\x00\x06\x0d\x02\x00\x46\x00\x06\x0e\x02\x00\x0d\x00\x2c\x10\x03\x00\x00\x01\xf9\x00\x00\xf0\x78\x00\x00\x02\x03\x00\x00\xf0\x78\x00\x00\x02\x03\x00\x01\x05\xfe\x00\x00\x01\xf9\x00\x01\x05\xfe\x00\x00\x01\xf9\x00\x00\xf0\x78\x00\x04\x11\x00'
+
+# Metal 3 resistor at (0.505um 67.07um 24.485um 67.51um)
+add_data_5 = b'\x00\x04\x08\x00\x00\x06\x0d\x02\x00\x46\x00\x06\x0e\x02\x00\x0d\x00\x2c\x10\x03\x00\x00\x01\xf9\x00\x01\x05\xfe\x00\x00\x5f\xa5\x00\x01\x05\xfe\x00\x00\x5f\xa5\x00\x01\x07\x66\x00\x00\x01\xf9\x00\x01\x07\x66\x00\x00\x01\xf9\x00\x01\x05\xfe\x00\x04\x11\x00'
+
+# Metal 3 resistor at (50.76um 67.07um 74.64um 67.51um)
+add_data_6 = b'\x00\x04\x08\x00\x00\x06\x0d\x02\x00\x46\x00\x06\x0e\x02\x00\x0d\x00\x2c\x10\x03\x00\x00\xc6\x48\x00\x01\x05\xfe\x00\x01\x23\x90\x00\x01\x05\xfe\x00\x01\x23\x90\x00\x01\x07\x66\x00\x00\xc6\x48\x00\x01\x07\x66\x00\x00\xc6\x48\x00\x01\x05\xfe\x00\x04\x11\x00'
+
+# Metal 3 resistor at (50.76um 61.56um 50.77um 67.07um)
+add_data_7 = b'\x00\x04\x08\x00\x00\x06\x0d\x02\x00\x46\x00\x06\x0e\x02\x00\x0d\x00\x2c\x10\x03\x00\x00\xc6\x48\x00\x00\xf0\x78\x00\x00\xc6\x52\x00\x00\xf0\x78\x00\x00\xc6\x52\x00\x01\x05\xfe\x00\x00\xc6\x48\x00\x01\x05\xfe\x00\x00\xc6\x48\x00\x00\xf0\x78\x00\x04\x11\x00'
+
+# Metal 3 resistor at (74.63um 61.56um 74.64um 67.07um)
+add_data_8 = b'\x00\x04\x08\x00\x00\x06\x0d\x02\x00\x46\x00\x06\x0e\x02\x00\x0d\x00\x2c\x10\x03\x00\x01\x23\x86\x00\x00\xf0\x78\x00\x01\x23\x90\x00\x00\xf0\x78\x00\x01\x23\x90\x00\x01\x05\xfe\x00\x01\x23\x86\x00\x01\x05\xfe\x00\x01\x23\x86\x00\x00\xf0\x78\x00\x04\x11\x00'
+
+# PADISOR label at (67.45um 64.22um) size 0.3um on MET3PIN
+add_data_9 = b'\x00\x04\x0c\x00\x00\x06\x0d\x02\x00\x46\x00\x06\x16\x02\x00\x05\x00\x06\x17\x01\x00\x05\x00\x06\x1a\x01\x00\x00\x00\x0c\x1b\x05\x40\x4c\x66\x66\x66\x66\x66\x66\x00\x0c\x10\x03\x00\x01\x07\x7a\x00\x00\xfa\xdc\x00\x0c\x19\x06\x50\x41\x44\x49\x53\x4f\x52\x00\x00\x04\x11\x00'
+
+# PADISOL label at (5.05um 64.22um) size 0.3um on MET3PIN
+add_data_10 = b'\x00\x04\x0c\x00\x00\x06\x0d\x02\x00\x46\x00\x06\x16\x02\x00\x05\x00\x06\x17\x01\x00\x05\x00\x06\x1a\x01\x00\x00\x00\x0c\x1b\x05\x40\x4c\x66\x66\x66\x66\x66\x66\x00\x0c\x10\x03\x00\x00\x13\xba\x00\x00\xfa\xdc\x00\x0c\x19\x06\x50\x41\x44\x49\x53\x4f\x4c\x00\x00\x04\x11\x00'
+
+# Append metal resistors after this data (between 69:16 and 69:44)
+orig_data_1 = b'\x00\x00\x00\x00\x00\x00\xad\x98\x00\x00\x01\x45\x00\x00\x86\x88\x00\x00\x01\x45\x00\x00\x86\x88\x00\x00\x00\x00\x00\x04\x11\x00'
+
+# Append port label after this data (after "P_CORE" label)
+orig_data_2 = b'\x00\x0c\x10\x03\x00\x00\xf5\x0a\x00\x00\x08\x7f\x00\x0a\x19\x06\x50\x5f\x43\x4f\x52\x45\x00\x04\x11\x00'
+
+# This is not efficient, but only needs to be done once.
+
+with open(file_name, 'rb') as ifile:
+ data = ifile.read()
+ data = data.replace(orig_data_1, orig_data_1 + add_data_1 + add_data_2 + add_data_3 + add_data_4 + add_data_5 + add_data_6 + add_data_7 + add_data_8)
+ data = data.replace(orig_data_2, orig_data_2 + add_data_9 + add_data_10)
+
+# Write back into the same file
+with open(file_name, 'wb') as ofile:
+ ofile.write(data)
+
+print("Done!")
diff --git a/sky130/custom/scripts/fix_vddio_overlay_lvc.py b/sky130/custom/scripts/fix_vddio_overlay_lvc.py
new file mode 100755
index 0000000..6888db6
--- /dev/null
+++ b/sky130/custom/scripts/fix_vddio_overlay_lvc.py
@@ -0,0 +1,51 @@
+#!/usr/bin/env python3
+#
+# fix_vddio_overlay_lvc.py ---
+#
+# Special-purpose script that does the work of what ought to be a simple
+# binary diff and patch. Except that no such thing exists as a standard
+# offering on most Linux systems, so instead of adding another OS
+# package requirement, I'm just writing a binary search-and-replace in
+# python.
+#
+# The purpose of the patch is to narrow down the metal 3 area under
+# the vias in this cell to clear the metal3 resistor marker that has
+# been added to the base cell. Since the overlay just duplicates the
+# metal 3 layer, this has no impact on the physical mask geometry.
+#
+
+import sys
+
+if len(sys.argv) != 2:
+ print('Usage: fix_vddio_overlay_lvc.py <filename>')
+ sys.exit(1)
+else:
+ file_name = sys.argv[1]
+
+# Convert this data
+orig_data_0 = b'\x00\x00\xf2\x8a\x00\x00\x02\x58\x00\x01\x03\xe2\x00\x00\x5f\xb4\x00\x01\x03\xe2\x00\x00\x5f\xb4\x00\x00\xf2\x8a\x00\x00\x02\x58\x00\x00\xf2\x8a'
+
+# To this data (move X position 24500 to 24470)
+new_data_0 = b'\x00\x00\xf2\x8a\x00\x00\x02\x58\x00\x01\x03\xe2\x00\x00\x5f\x96\x00\x01\x03\xe2\x00\x00\x5f\x96\x00\x00\xf2\x8a\x00\x00\x02\x58\x00\x00\xf2\x8a'
+
+# Convert this data
+
+# Convert this data
+orig_data_1 = b'\x00\x00\xc6\x43\x00\x00\xf2\x8a\x00\x00\xc6\x43\x00\x01\x03\xe2\x00\x01\x23\x9f\x00\x01\x03\xe2\x00\x01\x23\x9f\x00\x00\xf2\x8a\x00\x00\xc6\x43'
+
+# To this data (move X position 50755 to 50780), (move X position 74655 to 74625)
+new_data_1 = b'\x00\x00\xc6\x5c\x00\x00\xf2\x8a\x00\x00\xc6\x5c\x00\x01\x03\xe2\x00\x01\x23\x81\x00\x01\x03\xe2\x00\x01\x23\x81\x00\x00\xf2\x8a\x00\x00\xc6\x53'
+
+
+# This is not efficient, but only needs to be done once.
+
+with open(file_name, 'rb') as ifile:
+ data = ifile.read()
+ data = data.replace(orig_data_0, new_data_0)
+ data = data.replace(orig_data_1, new_data_1)
+
+# Write back into the same file
+with open(file_name, 'wb') as ofile:
+ ofile.write(data)
+
+print("Done!")
diff --git a/sky130/custom/scripts/fix_vddio_pad_gds.py b/sky130/custom/scripts/fix_vddio_pad_gds.py
index be038a7..0f9d002 100755
--- a/sky130/custom/scripts/fix_vddio_pad_gds.py
+++ b/sky130/custom/scripts/fix_vddio_pad_gds.py
@@ -52,10 +52,10 @@
# PADISOL label at (5.05um 66.22um) size 0.3um on MET3PIN
add_data_10 = b'\x00\x04\x0c\x00\x00\x06\x0d\x02\x00\x46\x00\x06\x16\x02\x00\x05\x00\x06\x17\x01\x00\x05\x00\x06\x1a\x01\x00\x00\x00\x0c\x1b\x05\x40\x4c\x66\x66\x66\x66\x66\x66\x00\x0c\x10\x03\x00\x00\x13\xba\x00\x01\x02\xac\x00\x0c\x19\x06\x50\x41\x44\x49\x53\x4f\x4c\x00\x00\x04\x11\x00'
-# Append metal resistors after this data
+# Append metal resistors after this data (between 70:44 and 69:44)
orig_data_1 = b'\x00\x02\x9d\x33\x00\x00\x2b\x1b\x00\x02\x9d\xfb\x00\x00\x2a\x53\x00\x02\x9d\xfb\x00\x00\x2a\x53\x00\x02\x9d\x33\x00\x04\x11\x00'
-# Append port label after this data
+# Append port label after this data (after "P_CORE" label)
orig_data_2 = b'\x00\x0c\x10\x03\x00\x00\x2d\x1e\x00\x00\x05\x23\x00\x0a\x19\x06\x50\x5f\x43\x4f\x52\x45\x00\x04\x11\x00'
# This is not efficient, but only needs to be done once.
diff --git a/sky130/custom/scripts/fix_vssio_lvc_gds.py b/sky130/custom/scripts/fix_vssio_lvc_gds.py
new file mode 100755
index 0000000..a1bc8d8
--- /dev/null
+++ b/sky130/custom/scripts/fix_vssio_lvc_gds.py
@@ -0,0 +1,67 @@
+#!/usr/bin/env python3
+#
+# fix_vssio_lvc_gds.py ---
+#
+# Special-purpose script that does the work of what ought to be a simple
+# binary diff and patch. Except that no such thing exists as a standard
+# offering on most Linux systems, so instead of adding another OS
+# package requirement, I'm just writing a binary search-and-replace in
+# python.
+#
+# The purpose of the patch is to add metal3 resistor ID markers to the
+# sky130_fd_io__top_ground_lvc_wpad cell. Also add label for PAD_ISO
+# in the isolated metal3 regions formed by the resistors.
+#
+
+import sys
+
+if len(sys.argv) != 2:
+ print('Usage: fix_vssio_lvc_gds.py <filename>')
+ sys.exit(1)
+else:
+ file_name = sys.argv[1]
+
+# Metal 3 resistor at (0.505um 61.12um 24.385um 61.56um)
+add_data_1 = b'\x00\x04\x08\x00\x00\x06\x0d\x02\x00\x46\x00\x06\x0e\x02\x00\x0d\x00\x2c\x10\x03\x00\x00\x01\xf9\x00\x00\xee\xc0\x00\x00\x5f\x41\x00\x00\xee\xc0\x00\x00\x5f\x41\x00\x00\xf0\x78\x00\x00\x01\xf9\x00\x00\xf0\x78\x00\x00\x01\xf9\x00\x00\xee\xc0\x00\x04\x11\x00'
+
+# Metal 3 resistor at (50.76um 61.12um 74.64um 61.56um)
+add_data_2 = b'\x00\x04\x08\x00\x00\x06\x0d\x02\x00\x46\x00\x06\x0e\x02\x00\x0d\x00\x2c\x10\x03\x00\x00\xc6\x48\x00\x00\xee\xc0\x00\x01\x23\x90\x00\x00\xee\xc0\x00\x01\x23\x90\x00\x00\xf0\x78\x00\x00\xc6\x48\x00\x00\xf0\x78\x00\x00\xc6\x48\x00\x00\xee\xc0\x00\x04\x11\x00'
+
+# Metal 3 resistor at (24.375um 55.760um 24.385um 61.120um)
+add_data_3 = b'\x00\x04\x08\x00\x00\x06\x0d\x02\x00\x46\x00\x06\x0e\x02\x00\x0d\x00\x2c\x10\x03\x00\x00\x5f\x37\x00\x00\xd9\xd0\x00\x00\x5f\x41\x00\x00\xd9\xd0\x00\x00\x5f\x41\x00\x00\xee\xc0\x00\x00\x5f\x37\x00\x00\xee\xc0\x00\x00\x5f\x37\x00\x00\xd9\xd0\x00\x04\x11\x00'
+
+# Metal 3 resistor at (0.505um 55.760um 0.515um 61.120um)
+add_data_4 = b'\x00\x04\x08\x00\x00\x06\x0d\x02\x00\x46\x00\x06\x0e\x02\x00\x0d\x00\x2c\x10\x03\x00\x00\x01\xf9\x00\x00\xd9\xd0\x00\x00\x02\x03\x00\x00\xd9\xd0\x00\x00\x02\x03\x00\x00\xee\xc0\x00\x00\x01\xf9\x00\x00\xee\xc0\x00\x00\x01\xf9\x00\x00\xd9\xd0\x00\x04\x11\x00'
+
+# Metal 3 resistor at (0.505um 55.32um 24.385um 55.76um)
+add_data_5 = b'\x00\x04\x08\x00\x00\x06\x0d\x02\x00\x46\x00\x06\x0e\x02\x00\x0d\x00\x2c\x10\x03\x00\x00\x01\xf9\x00\x00\xd8\x18\x00\x00\x5f\x41\x00\x00\xd8\x18\x00\x00\x5f\x41\x00\x00\xd9\xd0\x00\x00\x01\xf9\x00\x00\xd9\xd0\x00\x00\x01\xf9\x00\x00\xd8\x18\x00\x04\x11\x00'
+
+# Metal 3 resistor at (50.76um 55.32um 74.64um 55.76um)
+add_data_6 = b'\x00\x04\x08\x00\x00\x06\x0d\x02\x00\x46\x00\x06\x0e\x02\x00\x0d\x00\x2c\x10\x03\x00\x00\xc6\x48\x00\x00\xd8\x18\x00\x01\x23\x90\x00\x00\xd8\x18\x00\x01\x23\x90\x00\x00\xd9\xd0\x00\x00\xc6\x48\x00\x00\xd9\xd0\x00\x00\xc6\x48\x00\x00\xd8\x18\x00\x04\x11\x00'
+
+# Metal 3 resistor at (50.76um 55.760um 50.77um 61.120um)
+add_data_7 = b'\x00\x04\x08\x00\x00\x06\x0d\x02\x00\x46\x00\x06\x0e\x02\x00\x0d\x00\x2c\x10\x03\x00\x00\xc6\x48\x00\x00\xd9\xd0\x00\x00\xc6\x52\x00\x00\xd9\xd0\x00\x00\xc6\x52\x00\x00\xee\xc0\x00\x00\xc6\x48\x00\x00\xee\xc0\x00\x00\xc6\x48\x00\x00\xd9\xd0\x00\x04\x11\x00'
+
+# Metal 3 resistor at (74.63um 55.760um 74.64um 61.120um)
+add_data_8 = b'\x00\x04\x08\x00\x00\x06\x0d\x02\x00\x46\x00\x06\x0e\x02\x00\x0d\x00\x2c\x10\x03\x00\x01\x23\x86\x00\x00\xd9\xd0\x00\x01\x23\x90\x00\x00\xd9\xd0\x00\x01\x23\x90\x00\x00\xee\xc0\x00\x01\x23\x86\x00\x00\xee\xc0\x00\x01\x23\x86\x00\x00\xd9\xd0\x00\x04\x11\x00'
+
+# PADISOR label at (67.45um 58.34um) size 0.3um on MET3PIN
+add_data_9 = b'\x00\x04\x0c\x00\x00\x06\x0d\x02\x00\x46\x00\x06\x16\x02\x00\x05\x00\x06\x17\x01\x00\x05\x00\x06\x1a\x01\x00\x00\x00\x0c\x1b\x05\x40\x4c\x66\x66\x66\x66\x66\x66\x00\x0c\x10\x03\x00\x01\x07\x7a\x00\x00\xe3\xe4\x00\x0c\x19\x06\x50\x41\x44\x49\x53\x4f\x52\x00\x00\x04\x11\x00'
+
+# PADISOL label at (5.05um 58.34um) size 0.3um on MET3PIN
+add_data_10 = b'\x00\x04\x0c\x00\x00\x06\x0d\x02\x00\x46\x00\x06\x16\x02\x00\x05\x00\x06\x17\x01\x00\x05\x00\x06\x1a\x01\x00\x00\x00\x0c\x1b\x05\x40\x4c\x66\x66\x66\x66\x66\x66\x00\x0c\x10\x03\x00\x00\x13\xba\x00\x00\xe3\xe4\x00\x0c\x19\x06\x50\x41\x44\x49\x53\x4f\x4c\x00\x00\x04\x11\x00'
+
+# Append after this data
+orig_data = b'\x00\x00\x61\x8f\x00\x01\x12\xc4\x00\x03\x05\x70\x00\x01\x0b\xda\x00\x03\x05\x70\x00\x01\x0b\xda\x00\x00\x61\x8f\x00\x04\x11\x00'
+
+# This is not efficient, but only needs to be done once.
+
+with open(file_name, 'rb') as ifile:
+ data = ifile.read()
+ data = data.replace(orig_data, orig_data + add_data_1 + add_data_2 + add_data_3 + add_data_4 + add_data_5 + add_data_6 + add_data_7 + add_data_8 + add_data_9 + add_data_10)
+
+# Write back into the same file
+with open(file_name, 'wb') as ofile:
+ ofile.write(data)
+
+print("Done!")
diff --git a/sky130/custom/scripts/fix_vssio_overlay_lvc.py b/sky130/custom/scripts/fix_vssio_overlay_lvc.py
new file mode 100755
index 0000000..036fb19
--- /dev/null
+++ b/sky130/custom/scripts/fix_vssio_overlay_lvc.py
@@ -0,0 +1,48 @@
+#!/usr/bin/env python3
+#
+# fix_vssio_overlay_lvc.py ---
+#
+# Special-purpose script that does the work of what ought to be a simple
+# binary diff and patch. Except that no such thing exists as a standard
+# offering on most Linux systems, so instead of adding another OS
+# package requirement, I'm just writing a binary search-and-replace in
+# python.
+#
+# The purpose of the patch is to narrow down the metal 3 area under
+# the vias in this cell to clear the metal3 resistor marker that has
+# been added to the base cell. Since the overlay just duplicates the
+# metal 3 layer, this has no impact on the physical mask geometry.
+#
+
+import sys
+
+if len(sys.argv) != 2:
+ print('Usage: fix_vssio_overlay_lvc.py <filename>')
+ sys.exit(1)
+else:
+ file_name = sys.argv[1]
+
+# Convert this data
+orig_data_0 = b'\x00\x00\x01\xf4\x00\x00\xdb\xb0\x00\x00\x01\xf4\x00\x00\xed\x08\x00\x00\x5f\x50\x00\x00\xed\x08\x00\x00\x5f\x50\x00\x00\xdb\xb0\x00\x00\x01\xf4'
+
+# To this data (move X position 24400 to 24370), (move X position 500 to 520)
+new_data_0 = b'\x00\x00\x02\x08\x00\x00\xdb\xb0\x00\x00\x02\x08\x00\x00\xed\x08\x00\x00\x5f\x32\x00\x00\xed\x08\x00\x00\x5f\x32\x00\x00\xdb\xb0\x00\x00\x02\x08'
+
+# Convert this data
+orig_data_1 = b'\x00\x00\xc6\x43\x00\x00\xdb\xb0\x00\x00\xc6\x43\x00\x00\xed\x08\x00\x01\x22\x32\x00\x00\xed\x08\x00\x01\x22\x32\x00\x00\xdb\xb0\x00\x00\xc6\x43'
+
+# To this data (move X position 50755 to 50775)
+new_data_1 = b'\x00\x00\xc6\x57\x00\x00\xdb\xb0\x00\x00\xc6\x57\x00\x00\xed\x08\x00\x01\x22\x32\x00\x00\xed\x08\x00\x01\x22\x32\x00\x00\xdb\xb0\x00\x00\xc6\x57'
+
+# This is not efficient, but only needs to be done once.
+
+with open(file_name, 'rb') as ifile:
+ data = ifile.read()
+ data = data.replace(orig_data_0, new_data_0)
+ data = data.replace(orig_data_1, new_data_1)
+
+# Write back into the same file
+with open(file_name, 'wb') as ofile:
+ ofile.write(data)
+
+print("Done!")
diff --git a/sky130/custom/sky130_fd_io/cdl/sky130_ef_io.cdl b/sky130/custom/sky130_fd_io/cdl/sky130_ef_io.cdl
index b20e56e..ba4edfb 100644
--- a/sky130/custom/sky130_fd_io/cdl/sky130_ef_io.cdl
+++ b/sky130/custom/sky130_fd_io/cdl/sky130_ef_io.cdl
@@ -33,7 +33,7 @@
* Instantiate the underlying power pad (connects P_PAD to VCCD)
Xsky130_fd_io__top_power_lvc_base
+ AMUXBUS_A AMUXBUS_B BDY2_B2B DRN_LVC1 DRN_LVC2 BDY2_B2B
-+ VCCD VCCD_PAD
++ PADISOL PADISOR VCCD VCCD_PAD
+ SRC_BDY_LVC1 SRC_BDY_LVC2 VCCD VCCHIB VDDA VDDIO VDDIO_Q
+ VSSA VSSD VSSIO VSSIO_Q VSWITCH
+ sky130_fd_io__top_power_lvc_wpad
@@ -54,7 +54,7 @@
* Instantiate the underlying power pad (connects P_PAD to VDDA)
Xsky130_fd_io__top_power_lvc_base
+ AMUXBUS_A AMUXBUS_B BDY2_B2B DRN_LVC1 DRN_LVC2 BDY2_B2B
-+ VDDA VDDA_PAD
++ PADISOL PADISOR VDDA VDDA_PAD
+ SRC_BDY_LVC1 SRC_BDY_LVC2 VCCD VCCHIB VDDA VDDIO VDDIO_Q
+ VSSA VSSD VSSIO VSSIO_Q VSWITCH
+ sky130_fd_io__top_power_lvc_wpad
@@ -94,7 +94,7 @@
* Instantiate the underlying power pad (connects P_PAD and VDDIO_Q to VDDIO)
Xsky130_fd_io__top_power_lvc_base
+ AMUXBUS_A AMUXBUS_B BDY2_B2B DRN_LVC1 DRN_LVC2 BDY2_B2B
-+ VDDIO VDDIO_PAD
++ PADISOL PADISOR VDDIO VDDIO_PAD
+ SRC_BDY_LVC1 SRC_BDY_LVC2 VCCD VCCHIB VDDA VDDIO VDDIO_Q
+ VSSA VSSD VSSIO VSSIO_Q VSWITCH
+ sky130_fd_io__top_power_lvc_wpad
@@ -134,7 +134,7 @@
* Instantiate the underlying ground pad (connects G_PAD to VSSD)
Xsky130_fd_io__top_ground_lvc_base
+ AMUXBUS_A AMUXBUS_B BDY2_B2B DRN_LVC1 DRN_LVC2
-+ VSSD VSSD_PAD
++ VSSD VSSD_PAD PADISOL PADISOR
+ BDY2_B2B SRC_BDY_LVC1 SRC_BDY_LVC2 VCCD VCCHIB VDDA VDDIO VDDIO_Q
+ VSSA VSSD VSSIO VSSIO_Q VSWITCH
+ sky130_fd_io__top_ground_lvc_wpad
@@ -174,7 +174,7 @@
* Instantiate the underlying ground pad (connects G_PAD and VSSIO_Q to VSSIO)
Xsky130_fd_io__top_ground_lvc_base
+ AMUXBUS_A AMUXBUS_B BDY2_B2B DRN_LVC1 DRN_LVC2
-+ VSSIO VSSIO_PAD
++ VSSIO VSSIO_PAD PADISOL PADISOR
+ BDY2_B2B SRC_BDY_LVC1 SRC_BDY_LVC2 VCCD VCCHIB VDDA VDDIO VDDIO_Q
+ VSSA VSSD VSSIO VSSIO_Q VSWITCH
+ sky130_fd_io__top_ground_lvc_wpad
@@ -214,7 +214,7 @@
* Instantiate the underlying ground pad (connects G_PAD to VSSA)
Xsky130_fd_io__top_ground_lvc_base
+ AMUXBUS_A AMUXBUS_B BDY2_B2B DRN_LVC1 DRN_LVC2
-+ VSSA VSSA_PAD
++ VSSA VSSA_PAD PADISOL PADISOR
+ BDY2_B2B SRC_BDY_LVC1 SRC_BDY_LVC2 VCCD VCCHIB VDDA VDDIO VDDIO_Q
+ VSSA VSSD VSSIO VSSIO_Q VSWITCH
+ sky130_fd_io__top_ground_lvc_wpad
@@ -489,7 +489,7 @@
* Instantiate the underlying power pad (connects P_PAD to VCCD)
Xsky130_fd_io__top_power_lvc_base
+ AMUXBUS_A AMUXBUS_B VSSA VCCD VCCD VSSA
-+ VCCD VCCD_PAD
++ PADISOL PADISOR VCCD VCCD_PAD
+ VSSIO VSSD VCCD VCCHIB VDDA VDDIO VDDIO_Q
+ VSSA VSSD VSSIO VSSIO_Q VSWITCH
+ sky130_fd_io__top_power_lvc_wpad
@@ -510,7 +510,7 @@
* Instantiate the underlying ground pad (connects G_PAD to VSSD)
Xsky130_fd_io__top_ground_lvc_base
+ AMUXBUS_A AMUXBUS_B VSSA VCCD VCCD
-+ VSSD VSSD_PAD
++ VSSD VSSD_PAD PADISOL PADISOR
+ VSSA VSSIO VSSD VCCD VCCHIB VDDA VDDIO VDDIO_Q
+ VSSA VSSD VSSIO VSSIO_Q VSWITCH
+ sky130_fd_io__top_ground_lvc_wpad
@@ -532,7 +532,7 @@
* Instantiate the underlying power pad (connects P_PAD to VCCD)
Xsky130_fd_io__top_power_lvc_base
+ AMUXBUS_A AMUXBUS_B VSSIO VCCD1 VCCD1 VSSIO
-+ VCCD1 VCCD_PAD
++ PADISOL PADISOR VCCD1 VCCD_PAD
+ VSSD1 VSSD1 VCCD VCCHIB VDDA VDDIO VDDIO_Q
+ VSSA VSSD VSSIO VSSIO_Q VSWITCH
+ sky130_fd_io__top_power_lvc_wpad
@@ -554,7 +554,7 @@
* Instantiate the underlying ground pad (connects G_PAD to VSSD)
Xsky130_fd_io__top_ground_lvc_base
+ AMUXBUS_A AMUXBUS_B VSSIO VCCD1 VCCD1
-+ VSSD1 VSSD_PAD
++ VSSD1 VSSD_PAD PADISOL PADISOR
+ VSSIO VSSD1 VSSD1 VCCD VCCHIB VDDA VDDIO VDDIO_Q
+ VSSA VSSD VSSIO VSSIO_Q VSWITCH
+ sky130_fd_io__top_ground_lvc_wpad
@@ -575,7 +575,7 @@
* Instantiate the underlying power pad (connects P_PAD to VCCD)
Xsky130_fd_io__top_power_lvc_base
+ AMUXBUS_A AMUXBUS_B VSSA VCCD VCCD VSSA
-+ VCCD VCCD_PAD
++ PADISOL PADISOR VCCD VCCD_PAD
+ VSSIO VSSD VCCD VCCHIB VDDA VDDIO VDDIO_Q
+ VSSA VSSD VSSIO VSSIO_Q VSWITCH
+ sky130_fd_io__top_power_lvc_wpad
@@ -596,7 +596,7 @@
* Instantiate the underlying ground pad (connects G_PAD to VSSD)
Xsky130_fd_io__top_ground_lvc_base
+ AMUXBUS_A AMUXBUS_B VSSA VCCD VCCD
-+ VSSD VSSD_PAD
++ VSSD VSSD_PAD PADISOL PADISOR
+ VSSA VSSIO VSSD VCCD VCCHIB VDDA VDDIO VDDIO_Q
+ VSSA VSSD VSSIO VSSIO_Q VSWITCH
+ sky130_fd_io__top_ground_lvc_wpad
@@ -625,3 +625,47 @@
.ENDS
*--------------------------------------------------------------------------
+* sky130_ef_io__vddio_lvc_clamped_pad
+* sky130_ef_io__vddio_lvc_pad with LV clamp connections to VDDIO and VSSIO,
+* for use with 1.8V VDDIO. The back-to-back diodes are both shorted to
+* VSSIO.
+*--------------------------------------------------------------------------
+
+.SUBCKT sky130_ef_io__vddio_lvc_clamped_pad
++ AMUXBUS_A AMUXBUS_B VDDIO_PAD
++ VSSA VDDA VSWITCH VDDIO_Q VCCHIB VDDIO VCCD
++ VSSIO VSSD VSSIO_Q
+
+* Instantiate the underlying power pad (connects P_PAD to VCCIO)
+Xsky130_fd_io__top_power_lvc_base
++ AMUXBUS_A AMUXBUS_B VSSIO VDDIO VDDIO VSSIO
++ VDDIO_Q VDDIO_Q VDDIO VDDIO_PAD
++ VSSIO VSSIO VCCD VCCHIB VDDA VDDIO VDDIO_Q
++ VSSA VSSD VSSIO VSSIO_Q VSWITCH
++ sky130_fd_io__top_power_lvc_wpad
+
+.ENDS
+
+*--------------------------------------------------------------------------
+* sky130_ef_io__vssio_lvc_clamped_pad
+* sky130_ef_io__vssio_lvc_pad with LV clamp connections to VDDIO and VSSIO,
+* for use with 1.8V VDDIO. The back-to-back diodes are both shorted to
+* VSSIO.
+*--------------------------------------------------------------------------
+
+.SUBCKT sky130_ef_io__vssio_lvc_clamped_pad
++ AMUXBUS_A AMUXBUS_B VSSIO_PAD
++ VSSA VDDA VSWITCH VDDIO_Q VCCHIB VDDIO VCCD
++ VSSIO VSSD VSSIO_Q
+
+* Instantiate the underlying ground pad (connects G_PAD to VSSIO)
+Xsky130_fd_io__top_ground_lvc_base
++ AMUXBUS_A AMUXBUS_B VSSIO VDDIO VDDIO
++ VSSIO VSSIO_PAD VSSIO VSSIO_Q VSSIO_Q
++ VSSIO VSSIO VCCD VCCHIB VDDA VDDIO VDDIO_Q
++ VSSA VSSD VSSIO VSSIO_Q VSWITCH
++ sky130_fd_io__top_ground_lvc_wpad
+
+.ENDS
+
+*--------------------------------------------------------------------------
diff --git a/sky130/custom/sky130_fd_io/gds/sky130_ef_io__analog.gds b/sky130/custom/sky130_fd_io/gds/sky130_ef_io__analog.gds
index 83f1fb1..d37d552 100644
--- a/sky130/custom/sky130_fd_io/gds/sky130_ef_io__analog.gds
+++ b/sky130/custom/sky130_fd_io/gds/sky130_ef_io__analog.gds
Binary files differ
diff --git a/sky130/custom/sky130_fd_io/spice/sky130_ef_io__analog.spice b/sky130/custom/sky130_fd_io/spice/sky130_ef_io__analog.spice
new file mode 100644
index 0000000..22e944a
--- /dev/null
+++ b/sky130/custom/sky130_fd_io/spice/sky130_ef_io__analog.spice
@@ -0,0 +1,66 @@
+* NGSPICE file created from sky130_ef_io__analog --- technology: sky130A
+* Library of analog pads for sky130
+*---------------------------------------------------------------------------
+
+*---------------------------------------------------------------------------
+* sky130_ef_io__analog_noesd_pad:
+*---------------------------------------------------------------------------
+* Simple pad, straight through, no ESD protection.
+*---------------------------------------------------------------------------
+
+.subckt sky130_ef_io__analog_noesd_pad P_CORE VSSA VSSD AMUXBUS_B AMUXBUS_A
++ VDDIO_Q VDDIO VSWITCH VSSIO VDDA VCCD VCCHIB VSSIO_Q P_PAD
+
+R0 P_PAD P_CORE sky130_fd_pr__res_generic_m5 w=253 l=0.1
+.ends
+
+*---------------------------------------------------------------------------
+* sky130_ef_io__analog_pad:
+*---------------------------------------------------------------------------
+* Simple pad, straight through, with ESD diodes (5 each P and N).
+*---------------------------------------------------------------------------
+
+.subckt sky130_ef_io__analog_pad P_CORE VSSA VSSD AMUXBUS_B AMUXBUS_A VDDIO_Q VDDIO
++ VSWITCH VSSIO VDDA VCCD VCCHIB VSSIO_Q P_PAD
+R0 P_PAD P_CORE sky130_fd_pr__res_generic_m5 w=253 l=0.1
+
+D0 VSSIO P_CORE sky130_fd_pr__diode_pw2nd_11v0 pj=1.02e+08 area=5e+13
+D1 VSSIO P_CORE sky130_fd_pr__diode_pw2nd_11v0 pj=1.02e+08 area=5e+13
+D2 VSSIO P_CORE sky130_fd_pr__diode_pw2nd_11v0 pj=1.02e+08 area=5e+13
+D3 VSSIO P_CORE sky130_fd_pr__diode_pw2nd_11v0 pj=1.02e+08 area=5e+13
+D4 VSSIO P_CORE sky130_fd_pr__diode_pw2nd_11v0 pj=1.02e+08 area=5e+13
+
+D5 P_CORE VDDIO sky130_fd_pr__diode_pd2nw_11v0 pj=1.02e+08 area=5e+13
+D6 P_CORE VDDIO sky130_fd_pr__diode_pd2nw_11v0 pj=1.02e+08 area=5e+13
+D7 P_CORE VDDIO sky130_fd_pr__diode_pd2nw_11v0 pj=1.02e+08 area=5e+13
+D8 P_CORE VDDIO sky130_fd_pr__diode_pd2nw_11v0 pj=1.02e+08 area=5e+13
+D9 P_CORE VDDIO sky130_fd_pr__diode_pd2nw_11v0 pj=1.02e+08 area=5e+13
+.ends
+
+*---------------------------------------------------------------------------
+* sky130_ef_io__analog_minesd_pad:
+*---------------------------------------------------------------------------
+* Simple pad, straight through, with ESD diodes (1 each P and N).
+*---------------------------------------------------------------------------
+
+.subckt sky130_ef_io__analog_minesd_pad P_CORE VSSA VSSD AMUXBUS_B AMUXBUS_A VDDIO_Q VDDIO
++ VSWITCH VSSIO VDDA VCCD VCCHIB VSSIO_Q P_PAD
+R0 P_PAD P_CORE sky130_fd_pr__res_generic_m5 w=253 l=0.1
+
+D0 VSSIO P_CORE sky130_fd_pr__diode_pw2nd_11v0 pj=1.02e+08 area=5e+13
+D1 P_CORE VDDIO sky130_fd_pr__diode_pd2nw_11v0 pj=1.02e+08 area=5e+13
+.ends
+
+*---------------------------------------------------------------------------
+* sky130_ef_io__analog_minesd_pad_short:
+*---------------------------------------------------------------------------
+* Simple pad, straight through, with ESD diodes (1 each P and N).
+* All busses except for VDDIO and VSSIO removed
+*---------------------------------------------------------------------------
+
+.subckt sky130_ef_io__analog_minesd_pad_short P_CORE VDDIO VSSIO P_PAD
+R0 P_PAD P_CORE sky130_fd_pr__res_generic_m5 w=253 l=0.1
+
+D0 VSSIO P_CORE sky130_fd_pr__diode_pw2nd_11v0 pj=1.02e+08 area=5e+13
+D1 P_CORE VDDIO sky130_fd_pr__diode_pd2nw_11v0 pj=1.02e+08 area=5e+13
+.ends
diff --git a/sky130/custom/sky130_fd_io/spice/sky130_ef_io__analog_noesd_pad.spice b/sky130/custom/sky130_fd_io/spice/sky130_ef_io__analog_noesd_pad.spice
deleted file mode 100644
index e235ead..0000000
--- a/sky130/custom/sky130_fd_io/spice/sky130_ef_io__analog_noesd_pad.spice
+++ /dev/null
@@ -1,40 +0,0 @@
-* NGSPICE file created from sky130_ef_io__analog_noesd_pad.ext - technology: sky130A
-
-.subckt sky130_fd_io__pad_esd VSUBS m4_960_20297# m5_1354_20528#
-R0 m4_960_20297# m5_1354_20528# sky130_fd_pr__res_generic_m5 w=2.5284e+08u l=100000u
-.ends
-
-.subckt sky130_fd_io__com_busses_esd VSUBS sky130_fd_io__com_bus_hookup_0/VCCD sky130_fd_io__com_bus_hookup_0/VSWITCH
-+ sky130_fd_io__com_bus_hookup_0/AMUXBUS_A sky130_fd_io__com_bus_hookup_0/VSSIO sky130_fd_io__com_bus_hookup_0/AMUXBUS_B
-+ sky130_fd_io__com_bus_hookup_0/VDDA sky130_fd_io__com_bus_hookup_0/VDDIO sky130_fd_io__com_bus_hookup_0/VSSIO_Q
-+ sky130_fd_io__pad_esd_0/m5_1354_20528# sky130_fd_io__pad_esd_0/m4_960_20297# sky130_fd_io__com_bus_hookup_0/VDDIO_Q
-+ sky130_fd_io__com_bus_hookup_0/VSSA sky130_fd_io__com_bus_hookup_0/VSSD sky130_fd_io__com_bus_hookup_0/VCCHIB
-Xsky130_fd_io__pad_esd_0 VSUBS sky130_fd_io__pad_esd_0/m4_960_20297# sky130_fd_io__pad_esd_0/m5_1354_20528#
-+ sky130_fd_io__pad_esd
-.ends
-
-.subckt sky130_fd_io__simple_pad_and_busses VSUBS sky130_fd_io__com_busses_esd_0/sky130_fd_io__com_bus_hookup_0/VSWITCH
-+ sky130_fd_io__com_busses_esd_0/sky130_fd_io__com_bus_hookup_0/VDDA sky130_fd_io__com_busses_esd_0/sky130_fd_io__com_bus_hookup_0/VSSIO
-+ sky130_fd_io__com_busses_esd_0/sky130_fd_io__com_bus_hookup_0/VCCHIB sky130_fd_io__com_busses_esd_0/sky130_fd_io__com_bus_hookup_0/VDDIO
-+ m3_99_16575# sky130_fd_io__com_busses_esd_0/sky130_fd_io__com_bus_hookup_0/VSSIO_Q
-+ sky130_fd_io__com_busses_esd_0/sky130_fd_io__com_bus_hookup_0/AMUXBUS_A sky130_fd_io__com_busses_esd_0/sky130_fd_io__pad_esd_0/m5_1354_20528#
-+ sky130_fd_io__com_busses_esd_0/sky130_fd_io__com_bus_hookup_0/AMUXBUS_B sky130_fd_io__com_busses_esd_0/sky130_fd_io__com_bus_hookup_0/VSSA
-+ sky130_fd_io__com_busses_esd_0/sky130_fd_io__com_bus_hookup_0/VDDIO_Q sky130_fd_io__com_busses_esd_0/sky130_fd_io__com_bus_hookup_0/VSSD
-+ w_818_9944# sky130_fd_io__com_busses_esd_0/sky130_fd_io__com_bus_hookup_0/VCCD
-Xsky130_fd_io__com_busses_esd_0 VSUBS sky130_fd_io__com_busses_esd_0/sky130_fd_io__com_bus_hookup_0/VCCD
-+ sky130_fd_io__com_busses_esd_0/sky130_fd_io__com_bus_hookup_0/VSWITCH sky130_fd_io__com_busses_esd_0/sky130_fd_io__com_bus_hookup_0/AMUXBUS_A
-+ sky130_fd_io__com_busses_esd_0/sky130_fd_io__com_bus_hookup_0/VSSIO sky130_fd_io__com_busses_esd_0/sky130_fd_io__com_bus_hookup_0/AMUXBUS_B
-+ sky130_fd_io__com_busses_esd_0/sky130_fd_io__com_bus_hookup_0/VDDA sky130_fd_io__com_busses_esd_0/sky130_fd_io__com_bus_hookup_0/VDDIO
-+ sky130_fd_io__com_busses_esd_0/sky130_fd_io__com_bus_hookup_0/VSSIO_Q sky130_fd_io__com_busses_esd_0/sky130_fd_io__pad_esd_0/m5_1354_20528#
-+ m3_99_16575# sky130_fd_io__com_busses_esd_0/sky130_fd_io__com_bus_hookup_0/VDDIO_Q
-+ sky130_fd_io__com_busses_esd_0/sky130_fd_io__com_bus_hookup_0/VSSA sky130_fd_io__com_busses_esd_0/sky130_fd_io__com_bus_hookup_0/VSSD
-+ sky130_fd_io__com_busses_esd_0/sky130_fd_io__com_bus_hookup_0/VCCHIB sky130_fd_io__com_busses_esd
-.ends
-
-.subckt sky130_ef_io__analog_noesd_pad P_CORE VSSA VSSD AMUXBUS_B AMUXBUS_A VDDIO_Q VDDIO
-+ VSWITCH VSSIO VDDA VCCD VCCHIB VSSIO_Q P_PAD
-Xsky130_fd_io__simple_pad_and_busses_0 sky130_fd_io__simple_pad_and_busses_0/VSUBS
-+ VSWITCH VDDA VSSIO VCCHIB VDDIO P_CORE VSSIO_Q AMUXBUS_A P_PAD AMUXBUS_B VSSA VDDIO_Q
-+ VSSD sky130_fd_io__simple_pad_and_busses_0/VSUBS VCCD sky130_fd_io__simple_pad_and_busses
-.ends
-
diff --git a/sky130/custom/sky130_fd_io/spice/sky130_ef_io__analog_pad.spice b/sky130/custom/sky130_fd_io/spice/sky130_ef_io__analog_pad.spice
deleted file mode 100644
index 9156cf5..0000000
--- a/sky130/custom/sky130_fd_io/spice/sky130_ef_io__analog_pad.spice
+++ /dev/null
@@ -1,62 +0,0 @@
-* NGSPICE file created from sky130_ef_io__analog_pad.ext - technology: sky130A
-
-.subckt sky130_fd_io__pad_esd m4_960_20017# m5_1354_20500#
-R0 m4_960_20017# m5_1354_20500# sky130_fd_pr__res_generic_m5 w=253 l=0.1
-.ends
-
-.subckt sky130_fd_io__com_busses_esd sky130_fd_io__com_bus_hookup_0/VCCHIB sky130_fd_io__com_bus_hookup_0/VSSD
-+ sky130_fd_io__pad_esd_0/m5_1354_20500# sky130_fd_io__com_bus_hookup_0/VSSA sky130_fd_io__com_bus_hookup_0/VDDIO_Q
-+ sky130_fd_io__com_bus_hookup_0/VSSIO_Q sky130_fd_io__com_bus_hookup_0/VDDA sky130_fd_io__pad_esd_0/m4_960_20017#
-+ sky130_fd_io__com_bus_hookup_0/AMUXBUS_B sky130_fd_io__com_bus_hookup_0/VSSIO sky130_fd_io__com_bus_hookup_0/AMUXBUS_A
-+ sky130_fd_io__com_bus_hookup_0/VDDIO sky130_fd_io__com_bus_hookup_0/VSWITCH sky130_fd_io__com_bus_hookup_0/VCCD
-Xsky130_fd_io__pad_esd_0 sky130_fd_io__pad_esd_0/m4_960_20017# sky130_fd_io__pad_esd_0/m5_1354_20500#
-+ sky130_fd_io__pad_esd
-.ends
-
-.subckt sky130_ef_io__esd_pdiode_11v0_array a_n1540_n5136# a_1132_n5000# a_516_n5000#
-+ a_n1332_n5000# a_n716_n5000# a_n100_n5000#
-D0 a_n716_n5000# a_n716_n5000# sky130_fd_pr__diode_pw2nd_11v0 pj=1.02e+08 area=5e+13
-D1 a_n1332_n5000# a_n1332_n5000# sky130_fd_pr__diode_pw2nd_11v0 pj=1.02e+08 area=5e+13
-D2 a_n100_n5000# a_n100_n5000# sky130_fd_pr__diode_pw2nd_11v0 pj=1.02e+08 area=5e+13
-D3 a_1132_n5000# a_1132_n5000# sky130_fd_pr__diode_pw2nd_11v0 pj=1.02e+08 area=5e+13
-D4 a_516_n5000# a_516_n5000# sky130_fd_pr__diode_pw2nd_11v0 pj=1.02e+08 area=5e+13
-.ends
-
-.subckt sky130_ef_io__esd_ndiode_11v0_array a_964_n5000# a_n1164_n5000# a_432_n5000#
-+ a_n632_n5000# a_n100_n5000# w_n1396_n5168#
-D0 a_432_n5000# w_n1396_n5168# sky130_fd_pr__diode_pd2nw_11v0 pj=1.02e+08 area=5e+13
-D1 a_n100_n5000# w_n1396_n5168# sky130_fd_pr__diode_pd2nw_11v0 pj=1.02e+08 area=5e+13
-D2 a_n632_n5000# w_n1396_n5168# sky130_fd_pr__diode_pd2nw_11v0 pj=1.02e+08 area=5e+13
-D3 a_964_n5000# w_n1396_n5168# sky130_fd_pr__diode_pd2nw_11v0 pj=1.02e+08 area=5e+13
-D4 a_n1164_n5000# w_n1396_n5168# sky130_fd_pr__diode_pd2nw_11v0 pj=1.02e+08 area=5e+13
-.ends
-
-.subckt sky130_ef_io__esd_pad_and_busses sky130_fd_io__com_busses_esd_0/sky130_fd_io__com_bus_hookup_0/VCCD
-+ m1_2509_27880# sky130_fd_io__com_busses_esd_0/sky130_fd_io__pad_esd_0/m5_1354_20500#
-+ sky130_fd_io__com_busses_esd_0/sky130_fd_io__com_bus_hookup_0/VSSD sky130_fd_io__com_busses_esd_0/sky130_fd_io__com_bus_hookup_0/VDDIO_Q
-+ sky130_fd_io__com_busses_esd_0/sky130_fd_io__com_bus_hookup_0/VSSA sky130_fd_io__com_busses_esd_0/sky130_fd_io__com_bus_hookup_0/AMUXBUS_B
-+ sky130_fd_io__com_busses_esd_0/sky130_fd_io__com_bus_hookup_0/AMUXBUS_A sky130_fd_io__com_busses_esd_0/sky130_fd_io__com_bus_hookup_0/VSSIO_Q
-+ sky130_fd_io__com_busses_esd_0/sky130_fd_io__com_bus_hookup_0/VDDIO sky130_fd_io__com_busses_esd_0/sky130_fd_io__com_bus_hookup_0/VCCHIB
-+ sky130_fd_io__com_busses_esd_0/sky130_fd_io__com_bus_hookup_0/VSSIO sky130_fd_io__com_busses_esd_0/sky130_fd_io__com_bus_hookup_0/VDDA
-+ sky130_fd_io__com_busses_esd_0/sky130_fd_io__com_bus_hookup_0/VSWITCH
-Xsky130_fd_io__com_busses_esd_0 sky130_fd_io__com_busses_esd_0/sky130_fd_io__com_bus_hookup_0/VCCHIB
-+ sky130_fd_io__com_busses_esd_0/sky130_fd_io__com_bus_hookup_0/VSSD sky130_fd_io__com_busses_esd_0/sky130_fd_io__pad_esd_0/m5_1354_20500#
-+ sky130_fd_io__com_busses_esd_0/sky130_fd_io__com_bus_hookup_0/VSSA sky130_fd_io__com_busses_esd_0/sky130_fd_io__com_bus_hookup_0/VDDIO_Q
-+ sky130_fd_io__com_busses_esd_0/sky130_fd_io__com_bus_hookup_0/VSSIO_Q sky130_fd_io__com_busses_esd_0/sky130_fd_io__com_bus_hookup_0/VDDA
-+ m1_2509_27880# sky130_fd_io__com_busses_esd_0/sky130_fd_io__com_bus_hookup_0/AMUXBUS_B
-+ sky130_fd_io__com_busses_esd_0/sky130_fd_io__com_bus_hookup_0/VSSIO sky130_fd_io__com_busses_esd_0/sky130_fd_io__com_bus_hookup_0/AMUXBUS_A
-+ sky130_fd_io__com_busses_esd_0/sky130_fd_io__com_bus_hookup_0/VDDIO sky130_fd_io__com_busses_esd_0/sky130_fd_io__com_bus_hookup_0/VSWITCH
-+ sky130_fd_io__com_busses_esd_0/sky130_fd_io__com_bus_hookup_0/VCCD sky130_fd_io__com_busses_esd
-Xsky130_ef_io__esd_vssio sky130_fd_io__com_busses_esd_0/sky130_fd_io__com_bus_hookup_0/VSSIO
-+ m1_2509_27880# m1_2509_27880# m1_2509_27880# m1_2509_27880# m1_2509_27880# sky130_ef_io__esd_pdiode_11v0_array
-Xsky130_ef_io__esd_vddio m1_2509_27880# m1_2509_27880# m1_2509_27880# m1_2509_27880#
-+ m1_2509_27880# sky130_fd_io__com_busses_esd_0/sky130_fd_io__com_bus_hookup_0/VDDIO
-+ sky130_ef_io__esd_ndiode_11v0_array
-.ends
-
-.subckt sky130_ef_io__analog_pad P_CORE VSSA VSSD AMUXBUS_B AMUXBUS_A VDDIO_Q VDDIO
-+ VSWITCH VSSIO VDDA VCCD VCCHIB VSSIO_Q P_PAD
-Xsky130_ef_io__esd_pad_and_busses_0 VCCD P_CORE P_PAD VSSD VDDIO_Q VSSA AMUXBUS_B
-+ AMUXBUS_A VSSIO_Q VDDIO VCCHIB VSSIO VDDA VSWITCH sky130_ef_io__esd_pad_and_busses
-.ends
-
diff --git a/sky130/custom/sky130_fd_io/spice/sky130_fd_io.spice b/sky130/custom/sky130_fd_io/spice/sky130_fd_io.spice
index 39b4f25..29c75fd 100644
--- a/sky130/custom/sky130_fd_io/spice/sky130_fd_io.spice
+++ b/sky130/custom/sky130_fd_io/spice/sky130_fd_io.spice
@@ -7725,16 +7725,18 @@
* SPDX-License-Identifier: Apache-2.0
.SUBCKT sky130_fd_io__top_ground_lvc_wpad AMUXBUS_A AMUXBUS_B BDY2_B2B DRN_LVC1
-+ DRN_LVC2 G_CORE G_PAD OGC_LVC SRC_BDY_LVC1 SRC_BDY_LVC2 VCCD VCCHIB VDDA VDDIO
-+ VDDIO_Q VSSA VSSD VSSIO VSSIO_Q VSWITCH
++ DRN_LVC2 G_CORE G_PAD OGC_LVC PADISOL PADISOR SRC_BDY_LVC1 SRC_BDY_LVC2 VCCD
++ VCCHIB VDDA VDDIO VDDIO_Q VSSA VSSD VSSIO VSSIO_Q VSWITCH
*.PININFO AMUXBUS_A:B AMUXBUS_B:B BDY2_B2B:B DRN_LVC1:B DRN_LVC2:B
-*.PININFO G_CORE:B G_PAD:B OGC_LVC:B SRC_BDY_LVC1:B SRC_BDY_LVC2:B
-*.PININFO VCCD:B VCCHIB:B VDDA:B VDDIO:B VDDIO_Q:B VSSA:B VSSD:B
-*.PININFO VSSIO:B VSSIO_Q:B VSWITCH:B
+*.PININFO G_CORE:B G_PAD:B OGC_LVC:B PADISOL:B PADISOR:B SRC_BDY_LVC1:B
+*.PININFO SRC_BDY_LVC2:B VCCD:B VCCHIB:B VDDA:B VDDIO:B VDDIO_Q:B VSSA:B
+*.PININFO VSSD:B VSSIO:B VSSIO_Q:B VSWITCH:B
Xesd_q0 BDY2_B2B SRC_BDY_LVC1 VSSD sky130_fd_io__gnd2gnd_120x2_lv_isosub
xI54 SRC_BDY_LVC2 VDDIO sky130_fd_io__condiode
xI50 SRC_BDY_LVC1 VDDIO sky130_fd_io__condiode
RI21 G_PAD G_CORE sky130_fd_pr__res_generic_m5 w=2.5385e+08u l=100000u
+RIL G_CORE PADISOL sky130_fd_pr__res_generic_m3 w=11.825 l=0.01
+RIR G_CORE PADISOR sky130_fd_pr__res_generic_m3 w=11.825 l=0.01
Xpre_p1_q0 g_nclamp_lvc1 g_pdpre_lvc1 DRN_LVC1 DRN_LVC1 sky130_fd_pr__pfet_01v8
+ m=20 w=7.0 l=0.18 mult=1 sa=0.265 sb=0.265 sd=0.28 topography=normal area=0.063
+ perim=1.14
@@ -7795,16 +7797,18 @@
* SPDX-License-Identifier: Apache-2.0
.SUBCKT sky130_fd_io__top_power_lvc_wpad AMUXBUS_A AMUXBUS_B BDY2_B2B DRN_LVC1
-+ DRN_LVC2 OGC_LVC P_CORE P_PAD SRC_BDY_LVC1 SRC_BDY_LVC2 VCCD VCCHIB VDDA VDDIO
-+ VDDIO_Q VSSA VSSD VSSIO VSSIO_Q VSWITCH
++ DRN_LVC2 OGC_LVC PADISOL PADISOR P_CORE P_PAD SRC_BDY_LVC1 SRC_BDY_LVC2 VCCD
++ VCCHIB VDDA VDDIO VDDIO_Q VSSA VSSD VSSIO VSSIO_Q VSWITCH
*.PININFO AMUXBUS_A:B AMUXBUS_B:B BDY2_B2B:B DRN_LVC1:B DRN_LVC2:B
-*.PININFO OGC_LVC:B P_CORE:B P_PAD:B SRC_BDY_LVC1:B SRC_BDY_LVC2:B
-*.PININFO VCCD:B VCCHIB:B VDDA:B VDDIO:B VDDIO_Q:B VSSA:B VSSD:B
-*.PININFO VSSIO:B VSSIO_Q:B VSWITCH:B
+*.PININFO OGC_LVC:B PADISOL:B PADISOR:B P_CORE:B P_PAD:B SRC_BDY_LVC1:B
+*.PININFO SRC_BDY_LVC2:B VCCD:B VCCHIB:B VDDA:B VDDIO:B VDDIO_Q:B
+*.PININFO VSSA:B VSSD:B VSSIO:B VSSIO_Q:B VSWITCH:B
Xesd_q0 BDY2_B2B SRC_BDY_LVC1 VSSD sky130_fd_io__gnd2gnd_120x2_lv_isosub
xI54 SRC_BDY_LVC2 VDDIO sky130_fd_io__condiode
xI50 SRC_BDY_LVC1 VDDIO sky130_fd_io__condiode
RI21 P_PAD P_CORE sky130_fd_pr__res_generic_m5 w=2.5385e+08u l=100000u
+RIL P_CORE PADISOL sky130_fd_pr__res_generic_m3 w=11.825 l=0.01
+RIR P_CORE PADISOR sky130_fd_pr__res_generic_m3 w=11.825 l=0.01
Xpre_p1_q0 g_nclamp_lvc1 g_pdpre_lvc1 DRN_LVC1 DRN_LVC1 sky130_fd_pr__pfet_01v8
+ m=20 w=7.0 l=0.18 mult=1 sa=0.265 sb=0.265 sd=0.28 topography=normal area=0.063
+ perim=1.14
