gf180mcu: add gf180mcu_re_efuse, update LibreLane configs - Add gf180mcu_re_efuse - Update LibreLane configs - Add latch maps (gf180mcu_fd_sc_mcu7t5v0/mcu9t5v0) - Add pad configs (gf180mcu_fd_io/gf180mcu_ocd_io) - Add scl config (gf180mcu_as_sc_mcu7t3v3) - Add blackbox views - Add `SYNTH_CLOCKGATE_*` variables for clock gating - Make use of the new KLayout DRC setup - Update JSON manifest Signed-off-by: Leo Moser <leomoser99@gmail.com>
diff --git a/gf180mcu/Makefile.in b/gf180mcu/Makefile.in index e623470..11b48bc 100644 --- a/gf180mcu/Makefile.in +++ b/gf180mcu/Makefile.in
@@ -146,13 +146,13 @@ # library repositories must be subdirectories of this path. GF180MCU_PR_PATH = @GF180MCU_FD_PR_PATH@ GF180MCU_PV_PATH = @GF180MCU_FD_PV_PATH@ -GF180MCU_WS_KLAYOUT_PATH = @GF180MCU_WS_KLAYOUT_PATH@ GF180MCU_IO_PATH = @GF180MCU_FD_IO_PATH@ GF180MCU_SC_7T5V0_PATH = @GF180MCU_FD_SC_MCU7T5V0_PATH@ GF180MCU_SC_9T5V0_PATH = @GF180MCU_FD_SC_MCU9T5V0_PATH@ GF180MCU_SRAM_PATH = @GF180MCU_FD_IP_SRAM_PATH@ GF180MCU_OSU_SC_PATH = @GF180MCU_OSU_SC_PATH@ GF180MCU_AS_SC_PATH = @GF180MCU_AS_SC_PATH@ +GF180MCU_RE_EFUSE_PATH = @GF180MCU_RE_EFUSE_PATH@ GF180MCU_OCD_IO_PATH = @GF180MCU_OCD_IO_PATH@ GF180MCU_OCD_ALPHA_PATH = @GF180MCU_OCD_ALPHA_PATH@ GF180MCU_OCD_SRAM_PATH = @GF180MCU_OCD_IP_SRAM_PATH@ @@ -168,25 +168,24 @@ endif # Path to GF180MCU library sources -PDK_URL = https://github.com/google OSU_URL = https://github.com/stineje OCD_URL = https://github.com/RTimothyEdwards AVALON_URL = https://github.com/AvalonSemiconductors +EGORXE_URL = https://github.com/egorxe FOSSI_URL = https://github.com/fossi-foundation -WAFERSPACE_URL = https://github.com/wafer-space # Names of library repositories # NOTE: Switching PDK_LIB_PR and PDK_LIB_SC_7T5V0 to Efabless versions # having "quick fixes" under development. PDK_LIB_PR = ${FOSSI_URL}/globalfoundries-pdk-libs-gf180mcu_fd_pr PDK_LIB_PV = ${FOSSI_URL}/globalfoundries-pdk-libs-gf180mcu_fd_pv -PDK_LIB_WS_KLAYOUT = ${WAFERSPACE_URL}/gf180mcu PDK_LIB_IO = ${FOSSI_URL}/globalfoundries-pdk-libs-gf180mcu_fd_io PDK_LIB_SC_7T5V0 = ${FOSSI_URL}/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 PDK_LIB_SC_9T5V0 = ${FOSSI_URL}/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 -PDK_LIB_SRAM = ${PDK_URL}/globalfoundries-pdk-ip-gf180mcu_fd_ip_sram +PDK_LIB_SRAM = ${FOSSI_URL}/globalfoundries-pdk-ip-gf180mcu_fd_ip_sram PDK_LIB_OSU_SC = ${OSU_URL}/globalfoundries-pdk-libs-gf180mcu_osu_sc PDK_LIB_AS_SC = ${AVALON_URL}/gf180mcu_as_sc_mcu7t3v3 +PDK_LIB_RE_EFUSE = ${EGORXE_URL}/gf180mcu_re_efuse PDK_LIB_OCD_IO = ${OCD_URL}/gf180mcu_ocd_io PDK_LIB_OCD_SRAM = ${OCD_URL}/gf180mcu_ocd_ip_sram PDK_LIB_OCD_ALPHA =${OCD_URL}/gf180mcu_ocd_alpha @@ -258,11 +257,6 @@ else COMMIT_DEFS += -DFD_PV_COMMIT=$(shell cd ${GF180MCU_PV_PATH} ; git rev-parse HEAD) endif -ifeq (${GF180MCU_WS_KLAYOUT_PATH},) - COMMIT_DEFS += -DWS_KLAYOUT_COMMIT="unknown" -else - COMMIT_DEFS += -DWS_KLAYOUT_COMMIT=$(shell cd ${GF180MCU_WS_KLAYOUT_PATH} ; git rev-parse HEAD) -endif ifeq (${GF180MCU_IO_PATH},) COMMIT_DEFS += -DFD_IO_COMMIT="unknown" else @@ -288,6 +282,11 @@ else COMMIT_DEFS += -DAS_SC_MCU7T3V3_COMMIT=$(shell cd ${GF180MCU_AS_SC_PATH} ; git rev-parse HEAD) endif +ifeq (${GF180MCU_RE_EFUSE_PATH},) + COMMIT_DEFS += -DRE_EFUSE_COMMIT="unknown" +else + COMMIT_DEFS += -DRE_EFUSE_COMMIT=$(shell cd ${GF180MCU_RE_EFUSE_PATH} ; git rev-parse HEAD) +endif ifeq (${GF180MCU_OCD_IO_PATH},) COMMIT_DEFS += -DOCD_IO_COMMIT="unknown" else @@ -426,7 +425,7 @@ # LibreLane has a number of files that are common to all digital # standard cell libraries, so these are collected in one definition # here: -LIBRELANE_COMMON = config.tcl tracks.info no_synth.cells drc_exclude.cells +LIBRELANE_COMMON = config.tcl tracks.info no_synth.cells drc_exclude.cells pnr_exclude.cells synth_exclude.cells latch_map.v mux2_map.v # Where cpp syntax is followed, this is equivalent to cpp, but it does not # mangle non-C source files under the belief that they are actually C code. @@ -511,7 +510,7 @@ ../common/save_commit_refs.py ${COMMIT_DEFS} ${TECH}.json # Handle prerequisites -prerequisites: pr-repo pv-repo klayout-repo io-repo sc-7t-repo sc-9t-repo sram-repo ocd-sram-repo osu-sc-repo avalon-sc-repo ocd-io-repo ocd-alpha-repo +prerequisites: pr-repo pv-repo io-repo sc-7t-repo sc-9t-repo sram-repo ocd-sram-repo osu-sc-repo avalon-sc-repo re-efuse-repo ocd-io-repo ocd-alpha-repo pr-repo: if test "x${REFERENCE_JSON}" != "x"; then \ @@ -539,19 +538,6 @@ fi ; \ fi -klayout-repo: - if test "x${REFERENCE_JSON}" != "x"; then \ - WS_KLAYOUT_COMMIT=`cat ${REFERENCE_JSON} | grep gf180mcu_klayout | grep -v COMMIT | cut -d'"' -f4` ; \ - fi ; \ - if test "x${GF180MCU_WS_KLAYOUT_PATH}" != "x" ; then \ - if test -d "${GF180MCU_WS_KLAYOUT_PATH}" ; then \ - echo "Using existing installation of klayout libraries from ${GF180MCU_WS_KLAYOUT_PATH}" ; \ - else \ - echo "Downloading klayout library from ${GF180MCU_WS_KLAYOUT_PATH}" ; \ - ../scripts/download.sh ${PDK_LIB_WS_KLAYOUT} ${GF180MCU_WS_KLAYOUT_PATH} $${WS_KLAYOUT_COMMIT}; \ - fi ; \ - fi - io-repo: if test "x${REFERENCE_JSON}" != "x"; then \ FD_IO_COMMIT=`cat ${REFERENCE_JSON} | grep gf180mcu_fd_io | grep -v COMMIT | cut -d'"' -f4` ; \ @@ -643,6 +629,19 @@ fi ; \ fi +re-efuse-repo: + if test "x${REFERENCE_JSON}" != "x"; then \ + RE_EFUSE_COMMIT=`cat ${REFERENCE_JSON} | grep gf180mcu_re_efuse | grep -v COMMIT | cut -d'"' -f4` ; \ + fi ; \ + if test "x${GF180MCU_RE_EFUSE_PATH}" != "x" ; then \ + if test -d "${GF180MCU_RE_EFUSE_PATH}" ; then \ + echo "Using existing installation of eFuse non-volatile memory macros library from ${GF180MCU_RE_EFUSE_PATH}" ; \ + else \ + echo "Downloading eFuse non-volatile memory macros library from ${GF180MCU_RE_EFUSE_PATH}" ; \ + ../scripts/download.sh ${PDK_LIB_RE_EFUSE} ${GF180MCU_RE_EFUSE_PATH} $${RE_EFUSE_COMMIT} ; \ + fi ; \ + fi + ocd-io-repo: if test "x${REFERENCE_JSON}" != "x"; then \ OCD_IO_COMMIT=`cat ${REFERENCE_JSON} | grep gf180mcu_ocd_io | grep -v COMMIT | cut -d'"' -f4` ; \ @@ -671,7 +670,7 @@ # Update prerequisites -update: update-pr-repo update-pv-repo update-klayout-repo update-io-repo update-sc-7t-repo update-sc-9t-repo update-sram-repo update-ocd-sram-repo update-osu-sc-repo update-avalon-sc-repo update-ocd-io-repo +update: update-pr-repo update-pv-repo update-io-repo update-sc-7t-repo update-sc-9t-repo update-sram-repo update-ocd-sram-repo update-osu-sc-repo update-avalon-sc-repo update-re-efuse-repo update-ocd-io-repo update-pr-repo: if test "x${GF180MCU_PR_PATH}" != "x" ; then \ @@ -685,12 +684,6 @@ ../scripts/update.sh ${GF180MCU_PV_PATH} ; \ fi -update-klayout-repo: - if test "x${GF180MCU_WS_KLAYOUT_PATH}" != "x" ; then \ - echo "Updating GF180MCU klayout libraries from ${PDK_LIB_WS_KLAYOUT}" ; \ - ../scripts/update.sh ${GF180MCU_WS_KLAYOUT_PATH} ; \ - fi - update-io-repo: if test "x${GF180MCU_IO_PATH}" != "x" ; then \ echo "Updating GF180MCU I/O library from ${PDK_LIB_IO}" ; \ @@ -733,6 +726,12 @@ ../scripts/update.sh ${GF180MCU_AS_SC_PATH} ; \ fi +update-re-efuse-repo: + if test "x${GF180MCU_RE_EFUSE_PATH}" != "x" ; then \ + echo "Updating GF180MCU Avalon Semiconductors 3.3V standard cell library from ${PDK_LIB_RE_EFUSE}" ; \ + ../scripts/update.sh ${GF180MCU_RE_EFUSE_PATH} ; \ + fi + update-ocd-io-repo: if test "x${GF180MCU_OCD_IO_PATH}" != "x" ; then \ echo "Updating GF180MCU Open Circuit Design dual-voltage I/O library from ${PDK_LIB_OCD_IO}" ; \ @@ -818,20 +817,38 @@ mkdir -p ${IRSIMTOP_STAGING_$*} mkdir -p ${IRSIM_STAGING_$*} -klayout-%: ${GF180MCU_WS_KLAYOUT_PATH} ${GF180MCU_PR_PATH} +klayout-%: ${GF180MCU_PV_PATH} ${GF180MCU_PR_PATH} mkdir -p ${KLAYOUTTOP_STAGING_$*} mkdir -p ${KLAYOUT_STAGING_$*} - rm -rf ${KLAYOUT_STAGING_$*}/drc - rm -rf ${KLAYOUT_STAGING_$*}/lvs rm -rf ${KLAYOUT_STAGING_$*}/tech - rm -rf ${KLAYOUT_STAGING_$*}/pymacros mkdir ${KLAYOUT_STAGING_$*}/tech + mkdir ${KLAYOUT_STAGING_$*}/tech/drc + mkdir ${KLAYOUT_STAGING_$*}/tech/lvs + mkdir ${KLAYOUT_STAGING_$*}/tech/macros + mkdir ${KLAYOUT_STAGING_$*}/tech/pymacros + mkdir ${KLAYOUT_STAGING_$*}/tech/pymacros/cells + mkdir ${KLAYOUT_STAGING_$*}/tech/pymacros/klayout_api_cells + mkdir ${KLAYOUT_STAGING_$*}/tech/pymacros/sealring_cells + mkdir ${KLAYOUT_STAGING_$*}/tech/scripts - # This is a pre-built library; just copy the entire thing. - # NOTE: there is only one directory gf180mcuD in the repository. - # Copy the contents from this into all targets. - cp -rp ${GF180MCU_WS_KLAYOUT_PATH}/gf180mcuD/libs.tech/klayout/tech \ - ${KLAYOUT_STAGING_$*} + cp -rp ${GF180MCU_PV_PATH}/klayout/drc/* \ + ${KLAYOUT_STAGING_$*}/tech/drc + cp -rp ${GF180MCU_PV_PATH}/klayout/lvs/* \ + ${KLAYOUT_STAGING_$*}/tech/lvs + cp -rp ${GF180MCU_PR_PATH}/rules/klayout/macros/* \ + ${KLAYOUT_STAGING_$*}/tech/macros + cp -rp ${GF180MCU_PR_PATH}/cells/klayout/pymacros/cells/* \ + ${KLAYOUT_STAGING_$*}/tech/pymacros/cells + cp -rp ${GF180MCU_PR_PATH}/cells/klayout/pymacros/klayout_api_cells/* \ + ${KLAYOUT_STAGING_$*}/tech/pymacros/klayout_api_cells + cp -rp ${GF180MCU_PR_PATH}/cells/klayout/pymacros/sealring_cells/* \ + ${KLAYOUT_STAGING_$*}/tech/pymacros/sealring_cells + cp -rp ${GF180MCU_PR_PATH}/tech/klayout/* \ + ${KLAYOUT_STAGING_$*}/tech + cp -rp ${GF180MCU_PR_PATH}/cells/klayout/pymacros/*.lym \ + ${KLAYOUT_STAGING_$*}/tech/pymacros + cp -rp ${GF180MCU_PR_PATH}/cells/klayout/scripts/* \ + ${KLAYOUT_STAGING_$*}/tech/scripts xcircuit-%: rm -rf ${XCIRCUIT_STAGING_$*} @@ -849,19 +866,44 @@ ./custom/scripts/fix_xschemrc.py ${XSCHEM_STAGING_$*}/xschemrc \ ${GF180MCU$*} 2>&1 | tee -a ${GF180MCU$*}_make.log || true -librelane-%: librelane/config.tcl librelane/gf180mcu_fd_sc_mcu7t5v0/config.tcl librelane/gf180mcu_fd_sc_mcu9t5v0/config.tcl +librelane-%: librelane/config.tcl librelane/gf180mcu_fd_sc_mcu7t5v0/config.tcl librelane/gf180mcu_fd_sc_mcu9t5v0/config.tcl librelane/gf180mcu_as_sc_mcu7t3v3/config.tcl librelane/gf180mcu_osu_sc_gp9t3v3/config.tcl librelane/gf180mcu_osu_sc_gp12t3v3/config.tcl librelane/gf180mcu_fd_io/config.tcl librelane/gf180mcu_ocd_io/config.tcl mkdir -p ${LIBRELANETOP_STAGING_$*} mkdir -p ${LIBRELANE_STAGING_$*} rm -rf ${LIBRELANE_STAGING_$*}/gf180mcu_fd_sc_mcu7t5v0 rm -rf ${LIBRELANE_STAGING_$*}/gf180mcu_fd_sc_mcu9t5v0 + rm -rf ${LIBRELANE_STAGING_$*}/gf180mcu_as_sc_mcu7t3v3 + rm -rf ${LIBRELANE_STAGING_$*}/gf180mcu_osu_sc_gp9t3v3 + rm -rf ${LIBRELANE_STAGING_$*}/gf180mcu_osu_sc_gp12t3v3 + rm -rf ${LIBRELANE_STAGING_$*}/gf180mcu_fd_io + rm -rf ${LIBRELANE_STAGING_$*}/gf180mcu_ocd_io mkdir ${LIBRELANE_STAGING_$*}/gf180mcu_fd_sc_mcu7t5v0 mkdir ${LIBRELANE_STAGING_$*}/gf180mcu_fd_sc_mcu9t5v0 + mkdir ${LIBRELANE_STAGING_$*}/gf180mcu_as_sc_mcu7t3v3 + mkdir ${LIBRELANE_STAGING_$*}/gf180mcu_osu_sc_gp9t3v3 + mkdir ${LIBRELANE_STAGING_$*}/gf180mcu_osu_sc_gp12t3v3 + mkdir ${LIBRELANE_STAGING_$*}/gf180mcu_fd_io + mkdir ${LIBRELANE_STAGING_$*}/gf180mcu_ocd_io for file in ${LIBRELANE_COMMON} ; do \ rm -f ${LIBRELANE_STAGING_$*}/gf180mcu_fd_sc_mcu7t5v0/$$file ; \ done for file in ${LIBRELANE_COMMON} ; do \ rm -f ${LIBRELANE_STAGING_$*}/gf180mcu_fd_sc_mcu9t5v0/$$file ; \ done + for file in ${LIBRELANE_COMMON} ; do \ + rm -f ${LIBRELANE_STAGING_$*}/gf180mcu_as_sc_mcu7t3v3/$$file ; \ + done + for file in ${LIBRELANE_COMMON} ; do \ + rm -f ${LIBRELANE_STAGING_$*}/gf180mcu_osu_sc_gp9t3v3/$$file ; \ + done + for file in ${LIBRELANE_COMMON} ; do \ + rm -f ${LIBRELANE_STAGING_$*}/gf180mcu_osu_sc_gp12t3v3/$$file ; \ + done + for file in ${LIBRELANE_COMMON} ; do \ + rm -f ${LIBRELANE_STAGING_$*}/gf180mcu_ocd_io/$$file ; \ + done + for file in ${LIBRELANE_COMMON} ; do \ + rm -f ${LIBRELANE_STAGING_$*}/gf180mcu_ocd_io/$$file ; \ + done ${CPP} ${GF180MCU$*_DEFS} librelane/config.tcl ${LIBRELANE_STAGING_$*}/config.tcl for file in ${LIBRELANE_COMMON} ; do \ @@ -872,6 +914,24 @@ ${CPP} -quiet ${GF180MCU$*_DEFS} librelane/gf180mcu_fd_sc_mcu9t5v0/$$file \ ${LIBRELANE_STAGING_$*}/gf180mcu_fd_sc_mcu9t5v0/$$file ; \ done + for file in ${LIBRELANE_COMMON} ; do \ + ${CPP} -quiet ${GF180MCU$*_DEFS} librelane/gf180mcu_as_sc_mcu7t3v3/$$file \ + ${LIBRELANE_STAGING_$*}/gf180mcu_as_sc_mcu7t3v3/$$file ; \ + done + for file in ${LIBRELANE_COMMON} ; do \ + ${CPP} -quiet ${GF180MCU$*_DEFS} librelane/gf180mcu_osu_sc_gp9t3v3/$$file \ + ${LIBRELANE_STAGING_$*}/gf180mcu_osu_sc_gp9t3v3/$$file ; \ + done + for file in ${LIBRELANE_COMMON} ; do \ + ${CPP} -quiet ${GF180MCU$*_DEFS} librelane/gf180mcu_osu_sc_gp12t3v3/$$file \ + ${LIBRELANE_STAGING_$*}/gf180mcu_osu_sc_gp12t3v3/$$file ; \ + done + + ${CPP} -quiet ${GF180MCU$*_DEFS} librelane/gf180mcu_fd_io/config.tcl \ + ${LIBRELANE_STAGING_$*}/gf180mcu_fd_io/config.tcl + + ${CPP} -quiet ${GF180MCU$*_DEFS} librelane/gf180mcu_ocd_io/config.tcl \ + ${LIBRELANE_STAGING_$*}/gf180mcu_ocd_io/config.tcl rm -f ${LIBRELANE_STAGING_$*}/rules.openrcx.gf180mcu$*.min.* rm -f ${LIBRELANE_STAGING_$*}/rules.openrcx.gf180mcu$*.nom.* @@ -902,13 +962,13 @@ ${LIBRELANE_STAGING_$*}/rules.openrcx.gf180mcu$*.max ;\ fi -vendor-A: primitive-build-A digital-7t5v0-build-A digital-9t5v0-build-A io-build-A ocd-io-build-A ocd-alpha-build-A sram-build-A ocd-sram-build-A digital-osu-build-A digital-avalon-build-A +vendor-A: primitive-build-A digital-7t5v0-build-A digital-9t5v0-build-A io-build-A ocd-io-build-A ocd-alpha-build-A sram-build-A ocd-sram-build-A digital-osu-build-A digital-avalon-build-A digital-efuse-build-A -vendor-B: primitive-build-B digital-7t5v0-build-B digital-9t5v0-build-B io-build-B ocd-io-build-B ocd-alpha-build-B sram-build-B ocd-sram-build-B digital-osu-build-B digital-avalon-build-B +vendor-B: primitive-build-B digital-7t5v0-build-B digital-9t5v0-build-B io-build-B ocd-io-build-B ocd-alpha-build-B sram-build-B ocd-sram-build-B digital-osu-build-B digital-avalon-build-B digital-efuse-build-B -vendor-C: primitive-build-C digital-7t5v0-build-C digital-9t5v0-build-C io-build-C ocd-io-build-C ocd-alpha-build-C sram-build-C ocd-sram-build-C digital-osu-build-C digital-avalon-build-C +vendor-C: primitive-build-C digital-7t5v0-build-C digital-9t5v0-build-C io-build-C ocd-io-build-C ocd-alpha-build-C sram-build-C ocd-sram-build-C digital-osu-build-C digital-avalon-build-C digital-efuse-build-C -vendor-D: primitive-build-D digital-7t5v0-build-D digital-9t5v0-build-D io-build-D ocd-io-build-D ocd-alpha-build-D sram-build-D ocd-sram-build-D digital-osu-build-D digital-avalon-build-D +vendor-D: primitive-build-D digital-7t5v0-build-D digital-9t5v0-build-D io-build-D ocd-io-build-D ocd-alpha-build-D sram-build-D ocd-sram-build-D digital-osu-build-D digital-avalon-build-D digital-efuse-build-D primitive-build-%: if test "x${GF180MCU_PR_PATH}" != "x" ; then \ @@ -990,6 +1050,14 @@ fi ;\ fi +digital-efuse-build-%: + if test "x${GF180MCU_RE_EFUSE_PATH}" != "x" ; then \ + if test -d ${GF180MCU_RE_EFUSE_PATH} ; then \ + echo "Building eFuse non-volatile memory macros libraries" ;\ + make digital-efuse-$* ;\ + fi ;\ + fi + primitive-%: # Install tech LEF and primitive devices from vendor files ${STAGE} -source ${GF180MCU_PR_PATH} \ @@ -1315,18 +1383,42 @@ mkdir -p ${STAGING_PATH}/${GF180MCU$*}/libs.ref/gf180mcu_as_sc_mcu7t3v3/spice cp -rp ${AVALON_REF_SOURCE}/spice ${STAGING_PATH}/${GF180MCU$*}/libs.ref/gf180mcu_as_sc_mcu7t3v3 - # This library is done the right way and has its own librelane setup. - mkdir -p ${LIBRELANETOP_STAGING_$*} - mkdir -p ${LIBRELANE_STAGING_$*} - rm -rf ${LIBRELANE_STAGING_$*}/gf180mcu_as_sc_mcu7t3v3 - mkdir ${LIBRELANE_STAGING_$*}/gf180mcu_as_sc_mcu7t3v3 - cp -rp ${AVALON_TECH_SOURCE}/librelane/gf180mcu_as_sc_mcu7t3v3 ${LIBRELANE_STAGING_$*} +digital-efuse-%: + # Install eFuse non-volatile memory macros from vendor files + # NOTE: The repository is in open_pdks format and mainly just needs to + # be copied, not built. + rm -rf ${STAGING_PATH}/${GF180MCU$*}/libs.ref/gf180mcu_re_efuse/lib + mkdir -p ${STAGING_PATH}/${GF180MCU$*}/libs.ref/gf180mcu_re_efuse/lib + cp -rp ${GF180MCU_RE_EFUSE_PATH}/lib ${STAGING_PATH}/${GF180MCU$*}/libs.ref/gf180mcu_re_efuse + + rm -rf ${STAGING_PATH}/${GF180MCU$*}/libs.ref/gf180mcu_re_efuse/gds + mkdir ${STAGING_PATH}/${GF180MCU$*}/libs.ref/gf180mcu_re_efuse/gds + cp -rp ${GF180MCU_RE_EFUSE_PATH}/gds ${STAGING_PATH}/${GF180MCU$*}/libs.ref/gf180mcu_re_efuse + + rm -rf ${STAGING_PATH}/${GF180MCU$*}/libs.ref/gf180mcu_re_efuse/lef + mkdir ${STAGING_PATH}/${GF180MCU$*}/libs.ref/gf180mcu_re_efuse/lef + cp -rp ${GF180MCU_RE_EFUSE_PATH}/lef ${STAGING_PATH}/${GF180MCU$*}/libs.ref/gf180mcu_re_efuse + + rm -rf ${STAGING_PATH}/${GF180MCU$*}/libs.ref/gf180mcu_re_efuse/spice + mkdir ${STAGING_PATH}/${GF180MCU$*}/libs.ref/gf180mcu_re_efuse/spice + cp -rp ${GF180MCU_RE_EFUSE_PATH}/spice ${STAGING_PATH}/${GF180MCU$*}/libs.ref/gf180mcu_re_efuse + + rm -rf ${STAGING_PATH}/${GF180MCU$*}/libs.ref/gf180mcu_re_efuse/verilog + mkdir ${STAGING_PATH}/${GF180MCU$*}/libs.ref/gf180mcu_re_efuse/verilog + cp -rp ${GF180MCU_RE_EFUSE_PATH}/verilog ${STAGING_PATH}/${GF180MCU$*}/libs.ref/gf180mcu_re_efuse + + cp ${GF180MCU_RE_EFUSE_PATH}/README.md ${STAGING_PATH}/${GF180MCU$*}/libs.ref/gf180mcu_re_efuse/ + cp ${GF180MCU_RE_EFUSE_PATH}/LICENSE ${STAGING_PATH}/${GF180MCU$*}/libs.ref/gf180mcu_re_efuse/ io-%: # Install custom additions to the I/O pad library ${STAGE} -source ./custom -target ${STAGING_PATH}/${GF180MCU$*} \ - -verilog %l/verilog/*.v compile-only rename=gf180mcu_ef_io \ - -spice %l/spice/*.spice compile-only rename=gf180mcu_ef_io \ + -verilog %l/verilog/gf180mcu_ef_io__bi_t.v compile-only rename=gf180mcu_ef_io \ + -verilog %l/verilog/gf180mcu_ef_io__bi_t__blackbox.v \ + compile-only rename=gf180mcu_ef_io__blackbox \ + -verilog %l/verilog/gf180mcu_ef_io__bi_t__blackbox_pp.v \ + compile-only rename=gf180mcu_ef_io__blackbox_pp \ + -spice %l/spice/gf180mcu_ef_io__bi_t.spice compile-only rename=gf180mcu_ef_io \ -gds %l/gds/*_${$*_STACK}.gds compile-only \ rename=gf180mcu_ef_io \ options=custom/scripts/gds_import_io.tcl \ @@ -1398,10 +1490,11 @@ filter=custom/scripts/fix_io_cor_gds.py \ -lef cells/*/*_${$*_STACK}.lef \ annotate lefopts=-hide \ - filter=custom/scripts/fix_io_lef.py \ -xschem cells/*/*.sym \ filter=custom/scripts/make_primitive.py \ - -verilog cells/*/*.v compile-only \ + -verilog cells/*/*.v exclude=*__blackbox*.v compile-only \ + -verilog cells/*/*__blackbox.v compile-only rename=gf180mcu_fd_io__blackbox \ + -verilog cells/*/*__blackbox_pp.v compile-only rename=gf180mcu_fd_io__blackbox_pp \ -library general gf180mcu_fd_io 2>&1 | tee -a ${GF180MCU$*}_make.log ocd-io-%: @@ -1450,7 +1543,9 @@ -lef cells/*/*_${$*_STACK}.lef compile-only \ -xschem cells/*/*.sym \ filter=custom/scripts/make_primitive.py \ - -verilog cells/*/*.v compile-only \ + -verilog cells/*/*.v exclude=*__blackbox*.v compile-only \ + -verilog cells/*/*__blackbox.v rename=gf180mcu_ocd_io__blackbox.v compile-only \ + -verilog cells/*/*__blackbox_pp.v rename=gf180mcu_ocd_io__blackbox_pp.v compile-only \ -library general gf180mcu_ocd_io 2>&1 | tee -a ${GF180MCU$*}_make.log ocd-alpha-%: @@ -1488,7 +1583,9 @@ options=custom/scripts/gds_import_sram.tcl \ filter=custom/scripts/fix_sram_gds.py \ -lef cells/*/*.lef annotate lefopts="-hide 5um" \ - -verilog cells/*/*.v \ + -verilog cells/*/*.v exclude=*__blackbox*.v \ + -verilog cells/*/*__blackbox.v \ + -verilog cells/*/*__blackbox_pp.v \ -library general gf180mcu_fd_ip_sram 2>&1 | tee -a ${GF180MCU$*}_make.log # Remove "BL" labels from the rarray4_* cells, otherwise extraction # of the SRAMs without using "extract unique" will fail. @@ -1504,7 +1601,9 @@ -gds cells/*/*.gds \ options=custom/scripts/gds_import_ocd_sram.tcl \ -lef cells/*/*.lef \ - -verilog cells/*/*.v \ + -verilog cells/*/*.v exclude=*__blackbox*.v \ + -verilog cells/*/*__blackbox.v \ + -verilog cells/*/*__blackbox_pp.v \ -library general gf180mcu_ocd_ip_sram 2>&1 | tee -a ${GF180MCU$*}_make.log install: $(foreach var, ${VARIANTS}, install-$(var))
diff --git a/gf180mcu/custom/gf180mcu_fd_io/verilog/gf180mcu_ef_io__bi_t__blackbox.v b/gf180mcu/custom/gf180mcu_fd_io/verilog/gf180mcu_ef_io__bi_t__blackbox.v new file mode 100644 index 0000000..1d0eb6b --- /dev/null +++ b/gf180mcu/custom/gf180mcu_fd_io/verilog/gf180mcu_ef_io__bi_t__blackbox.v
@@ -0,0 +1,31 @@ +/* + * Copyright 2022 GlobalFoundries PDK Authors + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http:www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +(* blackbox *) +module gf180mcu_ef_io__bi_t (CS, SL, IE, OE, PU, PD, A, ANA, PDRV0, PDRV1, PAD, Y); + input CS; + input SL; + input IE; + input OE; + input PU; + input PD; + input A; + inout ANA; + input PDRV0; + input PDRV1; + inout PAD; + output Y; +endmodule
diff --git a/gf180mcu/custom/gf180mcu_fd_io/verilog/gf180mcu_ef_io__bi_t__blackbox_pp.v b/gf180mcu/custom/gf180mcu_fd_io/verilog/gf180mcu_ef_io__bi_t__blackbox_pp.v new file mode 100644 index 0000000..3b767c1 --- /dev/null +++ b/gf180mcu/custom/gf180mcu_fd_io/verilog/gf180mcu_ef_io__bi_t__blackbox_pp.v
@@ -0,0 +1,35 @@ +/* + * Copyright 2022 GlobalFoundries PDK Authors + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http:www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +(* blackbox *) +module gf180mcu_ef_io__bi_t (CS, SL, IE, OE, PU, PD, A, ANA, PDRV0, PDRV1, PAD, Y, DVDD, DVSS, VDD, VSS); + input CS; + input SL; + input IE; + input OE; + input PU; + input PD; + input A; + inout ANA; + input PDRV0; + input PDRV1; + inout PAD; + output Y; + inout DVDD; + inout DVSS; + inout VDD; + inout VSS; +endmodule
diff --git a/gf180mcu/custom/scripts/fix_io_lef.py b/gf180mcu/custom/scripts/fix_io_lef.py deleted file mode 100755 index 402e214..0000000 --- a/gf180mcu/custom/scripts/fix_io_lef.py +++ /dev/null
@@ -1,134 +0,0 @@ -#!/usr/bin/env python3 -# -# fix_io_lef --- -# -# This script fixes the issue where the LEF macros of the I/O cells -# are missing ports in the position of the wirebond pads, or the ports -# do not include the entire pad area. This script inserts an extra -# port rectangle at the position of the pad on all top-level I/O cells -# -# This script is a filter to be run by setting the name of this script as -# the value to "filter=" for the model install in the gf180mcu Makefile. - -import re -import os -import sys - -def filter(inname, outname): - - # Read input. Note that there is only one LEF file for the I/O library. - try: - with open(inname, 'r') as inFile: - ltext = inFile.read() - llines = ltext.splitlines() - except: - print('fix_io_lef.py: failed to open ' + inname + ' for reading.', file=sys.stderr) - return 1 - - # Map the input file name to the metal layer of the pad. - # The file names end in _3lm.lef, _4lm.lef, and _5lm.lef, so pick up the - # 7th character from the end. - mlayer = 'Metal' + inname[-7] - - # The following macros need pad ports - fixmacros = ['GF_NI_ASIG_5P0', 'GF_NI_BI_24T', 'GF_NI_BI_T', 'GF_NI_DVDD', - 'GF_NI_DVSS', 'GF_NI_IN_C', 'GF_NI_IN_S'] - - # Pin name for the pad port corresponding to each of the above macros - fixpins = ['ASIG5V', 'PAD', 'PAD', 'DVDD', 'DVSS', 'PAD', 'PAD'] - - # Process input with regexp - - fixedlines = [] - modified = False - - macrorex = re.compile(r'[ \t]*MACRO[ \t]+([^ \t\n]+)') - pinrex = re.compile(r'[ \t]*PIN[ \t]+([^ \t\n]+)') - userex = re.compile(r'[ \t]*USE[ \t]+([^ \t\n]+)') - endrex = re.compile(r'[ \t]*END[ \t]+([^ \t\n]+)') - - macroidx = -1 - pinidx = -1 - pin = None - for line in llines: - fixedlines.append(line) - - # Check for macro end - if macroidx >= 0: - ematch = endrex.match(line) - if ematch: - macroidx = -1 - pinidx = -1 - - # Check for 'MACRO' record, and get name of the macro. - mmatch = macrorex.match(line) - if mmatch: - macroname = mmatch.group(1) - if macroname in fixmacros: - macroidx = fixmacros.index(macroname) - - # Check for pin - if macroidx >= 0: - pmatch = pinrex.match(line) - if pmatch: - if pmatch.group(1) == fixpins[macroidx]: - pinidx = macroidx - - if pinidx >= 0: - umatch = userex.match(line) - if umatch: - # Add the extra port - fixedlines.append(' PORT') - fixedlines.append(' LAYER ' + mlayer + ' ;') - fixedlines.append(' RECT 7.5 2.0 67.5 62.0 ;') - fixedlines.append(' END') - pinidx = -1 - modified = True - - # Write output - if outname == None: - for i in fixedlines: - print(i) - else: - # If the output is a symbolic link but no modifications have been made, - # then leave it alone. If it was modified, then remove the symbolic - # link before writing. - if os.path.islink(outname): - if not modified: - return 0 - else: - os.unlink(outname) - try: - with open(outname, 'w') as outFile: - for i in fixedlines: - print(i, file=outFile) - except: - print('fix_io_lef.py: failed to open ' + outname + ' for writing.', file=sys.stderr) - return 1 - - -if __name__ == '__main__': - - # This script expects to get one or two arguments. One argument is - # mandatory and is the input file. The other argument is optional and - # is the output file. The output file and input file may be the same - # name, in which case the original input is overwritten. - - options = [] - arguments = [] - for item in sys.argv[1:]: - if item.find('-', 0) == 0: - options.append(item[1:]) - else: - arguments.append(item) - - if len(arguments) > 0: - infilename = arguments[0] - - if len(arguments) > 1: - outfilename = arguments[1] - else: - outfilename = None - - result = filter(infilename, outfilename) - sys.exit(result)
diff --git a/gf180mcu/gf180mcu.json b/gf180mcu/gf180mcu.json index f169a41..122f3da 100644 --- a/gf180mcu/gf180mcu.json +++ b/gf180mcu/gf180mcu.json
@@ -43,49 +43,50 @@ "description": "DESCRIPTION OPTION1 OPTION2 OPTION3 OPTION4 OPTION5", "options": [ #ifdef THICKMET3P0 - "THICKMET", + "THICKMET", #endif #ifdef MIM #undef MIM - "MIM_2P0", + "MIM_2P0", #endif #ifdef HRES1K - "HIRES_POLY_1K", + "HIRES_POLY_1K", #endif #ifdef METALS3 - "METAL3" + "METAL3" #elseif defined (METALS4) - "METAL4" + "METAL4" #elseif defined (METALS5) - "METAL5" + "METAL5" #elseif defined (METALS6) - "METAL6" + "METAL6" #endif ], "stdcells": { "gf180mcu_fd_sc_mcu9t5v0": "FD_SC_MCU9T5V0_COMMIT", "gf180mcu_fd_sc_mcu7t5v0": "FD_SC_MCU7T5V0_COMMIT", "gf180mcu_osu_sc_gf12t3v3": "OSU_SC_COMMIT", - "gf180mcu_osu_sc_gf9t3v3": "OSU_SC_COMMIT" + "gf180mcu_osu_sc_gf9t3v3": "OSU_SC_COMMIT", "gf180mcu_as_sc_mcu7t3v3": "AS_SC_MCU7T3V3_COMMIT" }, "iocells": { - "gf180mcu_fd_io": "FD_IO_COMMIT" + "gf180mcu_fd_io": "FD_IO_COMMIT", "gf180mcu_ocd_io": "OCD_IO_COMMIT" }, "primitive": { "gf180mcu_fd_pr": "FD_PR_COMMIT" }, "verification": { - "gf180mcu_fd_pv": "FD_PV_COMMIT" + "gf180mcu_fd_pv": "FD_PV_COMMIT", "gf180mcu_ws_klayout": "WS_KLAYOUT_COMMIT" }, "memory": { - "gf180mcu_fd_ip_sram": "FD_IP_SRAM_COMMIT" - "gf180mcu_ocd_ip_sram": "OCD_IP_SRAM_COMMIT" + "gf180mcu_fd_ip_sram": "FD_IP_SRAM_COMMIT", + "gf180mcu_ocd_ip_sram": "OCD_IP_SRAM_COMMIT", + "gf180mcu_re_efuse": "RE_EFUSE_COMMIT" }, "other": { - "gf180mcu_ocd_alpha": "OCD_ALPHA_COMMIT" + "gf180mcu_ocd_alpha": "OCD_ALPHA_COMMIT" }, "build": { "open_pdks": "OPEN_PDKS_VERSION", @@ -96,20 +97,20 @@ "magic": "MAGIC_COMMIT" }, "reference": { - "open_pdks": "9bd3b0328c7c742bbb87082f659cff3a11a6a5ff", + "open_pdks": "b2b2a17cfab106ea0f2621df8f7d441cfc7dee78", "magic": "d0e38df6bf11fcc424a7352006152fca02cb9b2a", "gf180mcu_pdk": "a897aa30369d3bcec87d9d50ce9b01f320f854ef", - "gf180mcu_fd_pr": "0ca9d87b1b4c4e5a71e69c25b74bb29a800470a6", - "gf180mcu_fd_pv": "c9e23a62ce171352640f8341feec71fe13f1c132", - "gf180mcu_ws_klayout": "7636804aa430fed842535e3d660f94de8ac4754c", - "gf180mcu_fd_io": "545621fdbac44f55344834e6c03486310c0862d7", + "gf180mcu_fd_pr": "3c646e3b2b410c6560c78acff8d6a11eab942f97", + "gf180mcu_fd_pv": "566d363c07cbde3dee149b4450b43dc7dfa91f3d", + "gf180mcu_fd_io": "ddf40b1a7c1a556b0f312ec9850ce4efb4c3f171", "gf180mcu_fd_sc_mcu7t5v0": "5641d172662a7d9086e5b99c5d54506c05e65cee", "gf180mcu_fd_sc_mcu9t5v0": "e0e80f5a6522f10b82165d3aeab9b8ee28e89849", - "gf180mcu_fd_ip_sram": "9c411928870ce15226228fa52ddb6ecc0ea4ffbe", - "gf180mcu_as_sc_mcu7t3v3": "94449964567d710e3dab608f1a932f87c718d4f3", - "gf180mcu_ocd_io": "a559ee0bbc5744fdb64a9f75d3ab9415a5315e09", + "gf180mcu_fd_ip_sram": "b98653230f05be17867c70870ecacfa6a6bca7ff", + "gf180mcu_as_sc_mcu7t3v3": "fd4991d0b9a4ac48eecfc74d6c6402d11778cee8", + "gf180mcu_re_efuse": "9941e38e7670a12f3f3a744bea4f9d2f04e6a669", + "gf180mcu_ocd_io": "53582c591ff7f2ca2529889e8e869f38ff4da39e", "gf180mcu_ocd_alpha": "0597ebd5732987dbcd149e02c38525c1c5bf2a58", - "gf180mcu_ocd_ip_sram": "2c2a6019df7f2404cc0794dd3b2302d85d917688", + "gf180mcu_ocd_ip_sram": "145d144b0158999e33826a7b3777fc3531f43977", "gf180mcu_osu_sc_gf12t3v3": "aa2fa8cd1bcb8fe98669acd05c0b0c65879268b3", "gf180mcu_osu_sc_gf9t3v3": "aa2fa8cd1bcb8fe98669acd05c0b0c65879268b3" }
diff --git a/gf180mcu/librelane/config.tcl b/gf180mcu/librelane/config.tcl index 3c5121f..324cec4 100644 --- a/gf180mcu/librelane/config.tcl +++ b/gf180mcu/librelane/config.tcl
@@ -7,37 +7,69 @@ set ::env(VDD_PIN_VOLTAGE) "5.00" set ::env(GND_PIN_VOLTAGE) "0.00" -set ::env(STD_CELL_POWER_PINS) "VDD VNW" -set ::env(STD_CELL_GROUND_PINS) "VSS VPW" +set ::env(SCL_POWER_PINS) "VDD VNW" +set ::env(SCL_GROUND_PINS) "VSS VPW" if { ![info exist ::env(STD_CELL_LIBRARY)] } { set ::env(STD_CELL_LIBRARY) gf180mcu_fd_sc_mcu7t5v0 } -if { ![info exist ::env(STD_CELL_LIBRARY_OPT)] } { - set ::env(STD_CELL_LIBRARY_OPT) gf180mcu_fd_sc_mcu7t5v0 + +if { ![info exist ::env(PAD_CELL_LIBRARY)] } { + set ::env(PAD_CELL_LIBRARY) gf180mcu_fd_io } -# Lib Files -set ::env(LIB_SYNTH) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/lib/$::env(STD_CELL_LIBRARY)__tt_025C_5v00.lib" -set ::env(LIB_FASTEST) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/lib/$::env(STD_CELL_LIBRARY)__ff_n40C_5v50.lib" -set ::env(LIB_SLOWEST) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/lib/$::env(STD_CELL_LIBRARY)__ss_125C_4v50.lib" +# Technology lib +set ::env(CELL_LIBS) [dict create] +dict set ::env(CELL_LIBS) *_tt_025C_5v00 "\ + $::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/lib/$::env(STD_CELL_LIBRARY)__tt_025C_5v00.lib\ +" +dict set ::env(CELL_LIBS) *_ff_n40C_5v50 "\ + $::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/lib/$::env(STD_CELL_LIBRARY)__ff_n40C_5v50.lib\ +" +dict set ::env(CELL_LIBS) *_ss_125C_4v50 "\ + $::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/lib/$::env(STD_CELL_LIBRARY)__ss_125C_4v50.lib\ +" -set ::env(LIB_TYPICAL) $::env(LIB_SYNTH) +# Corners +set ::env(STA_CORNERS) "\ +nom_tt_025C_5v00 \ +nom_ss_125C_4v50 \ +nom_ff_n40C_5v50 \ +min_tt_025C_5v00 \ +min_ss_125C_4v50 \ +min_ff_n40C_5v50 \ +max_tt_025C_5v00 \ +max_ss_125C_4v50 \ +max_ff_n40C_5v50 \ +" + +set ::env(DEFAULT_CORNER) "nom_tt_025C_5v00" + +set ::env(TIMING_VIOLATION_CORNERS) "*tt*" # Technology LEF -set ::env(TECH_LEF) [glob "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/techlef/*__nom.tlef"] -set ::env(TECH_LEF_MIN) [glob "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/techlef/*__min.tlef"] -set ::env(TECH_LEF_MAX) [glob "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/techlef/*__max.tlef"] -set ::env(CELLS_LEF) [glob "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/lef/*.lef"] -set ::env(GDS_FILES) [glob "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/gds/*.gds"] -set ::env(STD_CELL_LIBRARY_CDL) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/cdl/$::env(STD_CELL_LIBRARY).cdl" -set ::env(GPIO_PADS_LEF) "\ - $::env(PDK_ROOT)/$::env(PDK)/libs.ref/gf180mcu_io/lef/GF018green_ipio_5p0c_75_5lm.lef -" -set ::env(GPIO_PADS_VERILOG) "\ - $::env(PDK_ROOT)/$::env(PDK)/libs.ref/gf180mcu_io/verilog/GF018green_ipio_5p0c_75_5lm.v -" +set ::env(TECH_LEFS) [dict create] +dict set ::env(TECH_LEFS) nom_* [glob "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/techlef/*__nom.tlef"] +dict set ::env(TECH_LEFS) min_* [glob "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/techlef/*__min.tlef"] +dict set ::env(TECH_LEFS) max_* [glob "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/techlef/*__max.tlef"] +# Standard cells +set ::env(CELL_LEFS) [glob "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/lef/*.lef"] +set ::env(CELL_GDS) [glob "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/gds/*.gds"] +set ::env(CELL_VERILOG_MODELS) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/verilog/$::env(STD_CELL_LIBRARY).v" +set ::env(CELL_SPICE_MODELS) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/spice/$::env(STD_CELL_LIBRARY).spice" +set ::env(CELL_CDLS) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/cdl/$::env(STD_CELL_LIBRARY).cdl" + +# Pad cells +set ::env(PAD_LEFS) [glob "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(PAD_CELL_LIBRARY)/lef/*.lef"] +# The foundry library must be read in before the ef library because of ghost cells (references) +set ::env(PAD_GDS) "\ + $::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(PAD_CELL_LIBRARY)/gds/gf180mcu_fd_io.gds\ + $::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(PAD_CELL_LIBRARY)/gds/gf180mcu_ef_io.gds\ +" +set ::env(PAD_VERILOG_MODELS) [glob "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(PAD_CELL_LIBRARY)/verilog/*__blackbox_pp.v"] +set ::env(PAD_SPICE_MODELS) [glob "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(PAD_CELL_LIBRARY)/spice/*.spice"] +set ::env(PAD_CDLS) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(PAD_CELL_LIBRARY)/cdl/$::env(PAD_CELL_LIBRARY).cdl" # Latch mapping set ::env(SYNTH_LATCH_MAP) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/librelane/$::env(STD_CELL_LIBRARY)/latch_map.v" @@ -55,50 +87,49 @@ set ::env(CARRY_SELECT_ADDER_MAP) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/librelane/$::env(STD_CELL_LIBRARY)/csa_map.v" # Default No Synth List -set ::env(NO_SYNTH_CELL_LIST) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/librelane/$::env(STD_CELL_LIBRARY)/no_synth.cells" +set ::env(SYNTH_EXCLUDED_CELL_FILE) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/librelane/$::env(STD_CELL_LIBRARY)/synth_exclude.cells" # Default DRC Exclude List -set ::env(DRC_EXCLUDE_CELL_LIST) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/librelane/$::env(STD_CELL_LIBRARY)/drc_exclude.cells" - -# DRC Exclude List for Optimization library -set ::env(DRC_EXCLUDE_CELL_LIST_OPT) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/librelane/$::env(STD_CELL_LIBRARY_OPT)/drc_exclude.cells" +set ::env(PNR_EXCLUDED_CELL_FILE) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/librelane/$::env(STD_CELL_LIBRARY)/pnr_exclude.cells" # Open-RCX Rules File set ::env(RCX_RULES) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/librelane/rcx_rules.info" # Floorplanning -## Layer Info -set ::env(FP_IO_HLAYER) "Metal3" -set ::env(FP_IO_VLAYER) "Metal2" -set ::env(FP_PDN_RAIL_LAYER) "Metal1" -set ::env(FP_PDN_VERTICAL_LAYER) "Metal4" -set ::env(FP_PDN_HORIZONTAL_LAYER) "Metal5" + +# I/O Layer info +set ::env(IO_PIN_H_LAYER) "Metal3" +set ::env(IO_PIN_V_LAYER) "Metal2" + +# PDN Macro blockages list set ::env(MACRO_BLOCKAGES_LAYER) "Metal1 Metal2 Metal3 Metal4 Metal5" -set ::env(DATA_WIRE_RC_LAYER) "Metal2" -set ::env(CLOCK_WIRE_RC_LAYER) "Metal4" ## Tap Cell Dist set ::env(FP_TAPCELL_DIST) 20 -## Extra PDN configs +# Extra PDN configs +set ::env(PDN_RAIL_LAYER) "Metal1" +set ::env(PDN_RAIL_OFFSET) 0 -set ::env(FP_PDN_RAIL_OFFSET) 0 -set ::env(FP_PDN_VWIDTH) 1.6 -set ::env(FP_PDN_HWIDTH) 1.6 -set ::env(FP_PDN_VSPACING) 1.7 -set ::env(FP_PDN_HSPACING) 1.7 -set ::env(FP_PDN_VOFFSET) 16.32 -set ::env(FP_PDN_VPITCH) 153.6 -set ::env(FP_PDN_HOFFSET) 16.65 -set ::env(FP_PDN_HPITCH) 153.18 +set ::env(PDN_VERTICAL_LAYER) "Metal4" +set ::env(PDN_HORIZONTAL_LAYER) "Metal5" + +set ::env(PDN_VWIDTH) 1.6 +set ::env(PDN_HWIDTH) 1.6 +set ::env(PDN_VSPACING) 1.7 +set ::env(PDN_HSPACING) 1.7 +set ::env(PDN_VOFFSET) 16.32 +set ::env(PDN_VPITCH) 153.6 +set ::env(PDN_HOFFSET) 16.65 +set ::env(PDN_HPITCH) 153.18 ## Core Ring PDN defaults -set ::env(FP_PDN_CORE_RING_VWIDTH) 1.6 -set ::env(FP_PDN_CORE_RING_HWIDTH) 1.6 -set ::env(FP_PDN_CORE_RING_VSPACING) 1.7 -set ::env(FP_PDN_CORE_RING_HSPACING) 1.7 -set ::env(FP_PDN_CORE_RING_VOFFSET) 6 -set ::env(FP_PDN_CORE_RING_HOFFSET) 6 +set ::env(PDN_CORE_RING_VWIDTH) 1.6 +set ::env(PDN_CORE_RING_HWIDTH) 1.6 +set ::env(PDN_CORE_RING_VSPACING) 1.7 +set ::env(PDN_CORE_RING_HSPACING) 1.7 +set ::env(PDN_CORE_RING_VOFFSET) 6 +set ::env(PDN_CORE_RING_HOFFSET) 6 # Timing set ::env(RCX_RULES) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/librelane/rules.openrcx.$::env(PDK).nom" @@ -113,33 +144,81 @@ set ::env(GRT_LAYER_ADJUSTMENTS) "0,0,0,0,0" ## Tracks info -set ::env(TRACKS_INFO_FILE) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/librelane/$::env(STD_CELL_LIBRARY)/tracks.info" +set ::env(FP_TRACKS_INFO) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/librelane/$::env(STD_CELL_LIBRARY)/tracks.info" # Signoff ## Magic -set ::env(MAGIC_MAGICRC) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/magic/$::env(PDK).magicrc" -set ::env(MAGIC_TECH_FILE) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/magic/$::env(PDK).tech" +set ::env(MAGICRC) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/magic/$::env(PDK).magicrc" +set ::env(MAGIC_TECH) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/magic/$::env(PDK).tech" ## Klayout set ::env(KLAYOUT_TECH) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/klayout/tech/gf180mcu.lyt" set ::env(KLAYOUT_PROPERTIES) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/klayout/tech/gf180mcu.lyp" -set ::env(KLAYOUT_DRC_TECH_SCRIPT) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/klayout/drc/gf180mcu.drc" set ::env(KLAYOUT_DEF_LAYER_MAP) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/klayout/tech/gf180mcu.map" +set ::env(KLAYOUT_DRC_RUNSET) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/klayout/tech/drc/gf180mcu.drc" +set ::env(KLAYOUT_DRC_OPTIONS) [dict create] +dict set ::env(KLAYOUT_DRC_OPTIONS) variant $::env(PDK) +dict set ::env(KLAYOUT_DRC_OPTIONS) decks "all,-antenna,-density" + +set ::env(KLAYOUT_DENSITY_RUNSET) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/klayout/tech/drc/gf180mcu.drc" +set ::env(KLAYOUT_DENSITY_OPTIONS) [dict create] +dict set ::env(KLAYOUT_DRC_OPTIONS) variant $::env(PDK) +dict set ::env(KLAYOUT_DENSITY_OPTIONS) decks "density" + +set ::env(KLAYOUT_ANTENNA_RUNSET) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/klayout/tech/drc/gf180mcu.drc" +set ::env(KLAYOUT_ANTENNA_OPTIONS) [dict create] +dict set ::env(KLAYOUT_DRC_OPTIONS) variant $::env(PDK) +dict set ::env(KLAYOUT_ANTENNA_OPTIONS) decks "antenna" + +set ::env(KLAYOUT_FILLER_SCRIPT) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/klayout/tech/scripts/fill_all.rb" +set ::env(KLAYOUT_FILLER_OPTIONS) [dict create] + +set ::env(KLAYOUT_LVS_SCRIPT) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/klayout/tech/lvs/gf180mcu.lvs" +set ::env(KLAYOUT_LVS_OPTIONS) [dict create run_mode deep] + +set ::env(KLAYOUT_SEALRING_SCRIPT) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/klayout/tech/scripts/sealring.py" + ## Netgen -set ::env(NETGEN_SETUP_FILE) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/netgen/$::env(PDK)_setup.tcl" +set ::env(NETGEN_SETUP) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/netgen/$::env(PDK)_setup.tcl" -# # Temporary Override(s) Because OpenROAD can't read techlefs properly -# # Layer RC Values -# set ::env(LAYERS_RC) "\ -# Metal1 0.090000 0.0000394,\ -# Metal2 0.090000 0.0000394,\ -# Metal3 0.090000 0.0000394,\ -# Metal4 0.090000 0.0000394,\ -# Metal5 0.090000 0.0000394" +# Used for parasitics estimation, IR drop analysis, etc +set ::env(LAYERS_RC) [dict create] -# set ::env(VIAS_RC) "\ -# Via1 4.500,\ -# Via2 4.500,\ -# Via3 4.500,\ -# Via4 4.500" +# RC fit from OpenROAD +# https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/master/flow/platforms/gf180/setRC.tcl +dict set ::env(LAYERS_RC) "*" Metal2 res 3.85861E-04 +dict set ::env(LAYERS_RC) "*" Metal2 cap 1.35357E-04 +dict set ::env(LAYERS_RC) "*" Metal3 res 2.06673E-04 +dict set ::env(LAYERS_RC) "*" Metal3 cap 1.46141E-04 +dict set ::env(LAYERS_RC) "*" Metal4 res 1.68609E-04 +dict set ::env(LAYERS_RC) "*" Metal4 cap 1.50688E-04 +dict set ::env(LAYERS_RC) "*" Metal5 res 7.92778E-05 +dict set ::env(LAYERS_RC) "*" Metal5 cap 1.55595E-04 + +set ::env(VIAS_R) [dict create] + +# Best case (and used for nom) +dict set ::env(VIAS_R) "*" Via1 res 4.23 +dict set ::env(VIAS_R) "*" Via2 res 4.23 +dict set ::env(VIAS_R) "*" Via3 res 4.23 +dict set ::env(VIAS_R) "*" Via4 res 4.23 + +# Worst case (last one wins) +dict set ::env(VIAS_R) "max_*" Via1 res 16.845 +dict set ::env(VIAS_R) "max_*" Via2 res 16.845 +dict set ::env(VIAS_R) "max_*" Via3 res 16.845 +dict set ::env(VIAS_R) "max_*" Via4 res 16.845 + +set ::env(SIGNAL_WIRE_RC_LAYERS) "Metal2 Metal3 Metal4" +set ::env(CLOCK_WIRE_RC_LAYERS) "Metal2 Metal3 Metal4" + +# Base SDC + +# in ns +set ::env(CLOCK_UNCERTAINTY_CONSTRAINT) 0.25 +set ::env(CLOCK_TRANSITION_CONSTRAINT) 0.15 + +# Percentage +set ::env(TIME_DERATING_CONSTRAINT) 5 +set ::env(IO_DELAY_CONSTRAINT) 20
diff --git a/gf180mcu/librelane/gf180mcu_as_sc_mcu7t3v3/config.tcl b/gf180mcu/librelane/gf180mcu_as_sc_mcu7t3v3/config.tcl new file mode 100644 index 0000000..52f4d8c --- /dev/null +++ b/gf180mcu/librelane/gf180mcu_as_sc_mcu7t3v3/config.tcl
@@ -0,0 +1,73 @@ +set current_folder [file dirname [file normalize [info script]]] +# Technology lib + +set ::env(CELL_LIBS) [dict create] +dict set ::env(CELL_LIBS) *_tt_025C_3v30 "\ + $::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/lib/$::env(STD_CELL_LIBRARY)__tt_025C_3v30.lib\ +" +dict set ::env(CELL_LIBS) *_ff_n40C_3v60 "\ + $::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/lib/$::env(STD_CELL_LIBRARY)__ff_n40C_3v60.lib\ +" +dict set ::env(CELL_LIBS) *_ss_125C_3v00 "\ + $::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/lib/$::env(STD_CELL_LIBRARY)__ss_125C_3v00.lib\ +" + +set ::env(STA_CORNERS) "\ + nom_tt_025C_3v30 \ + min_tt_025C_3v30 \ + max_tt_025C_3v30 \ + nom_ff_n40C_3v60 \ + min_ff_n40C_3v60 \ + max_ff_n40C_3v60 \ + nom_ss_125C_3v00 \ + min_ss_125C_3v00 \ + max_ss_125C_3v00 \ +" +set ::env(DEFAULT_CORNER) "nom_tt_025C_3v30" + +# MUX2 mapping +set ::env(SYNTH_MUX_MAP) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/librelane/$::env(STD_CELL_LIBRARY)/mux2_map.v" + +# Placement site for core cells +# This can be found in the technology lef +set ::env(PLACE_SITE) "unithd" + +# welltap and endcap cell +set ::env(WELLTAP_CELL) "$::env(STD_CELL_LIBRARY)__tap_2" +set ::env(ENDCAP_CELL) "$::env(STD_CELL_LIBRARY)__tap_2" + +# defaults (can be overridden by designs): +set ::env(SYNTH_DRIVING_CELL) "$::env(STD_CELL_LIBRARY)__inv_2/Y" +set ::env(SYNTH_CLK_DRIVING_CELL) "$::env(STD_CELL_LIBRARY)__inv_4/Y" + +# update these +set ::env(OUTPUT_CAP_LOAD) "72.91" ; # femtofarad from pin I in liberty file +set ::env(SYNTH_BUFFER_CELL) "$::env(STD_CELL_LIBRARY)__buff_2/A/Y" +set ::env(SYNTH_TIEHI_CELL) "$::env(STD_CELL_LIBRARY)__tieh_4/ONE" +set ::env(SYNTH_TIELO_CELL) "$::env(STD_CELL_LIBRARY)__tiel_4/ZERO" + +# Fillcell insertion +set ::env(FILL_CELLS) "$::env(STD_CELL_LIBRARY)__fill_*" +set ::env(DECAP_CELLS) "$::env(STD_CELL_LIBRARY)__fillcap_*" + +# Diode Insertion +# A fake diode has to be created, for now don't use any strategy that uses fake diode +# set ::env(FAKEDIODE_CELL) "" +set ::env(DIODE_CELL) "$::env(STD_CELL_LIBRARY)__diode_2/DIODE" + +set ::env(CELL_PAD_EXCLUDE) "$::env(STD_CELL_LIBRARY)__tap_2 $::env(STD_CELL_LIBRARY)__fill_*" + +# TritonCTS configurations +set ::env(CTS_ROOT_BUFFER) "$::env(STD_CELL_LIBRARY)__clkbuff_12" +set ::env(CTS_CLK_BUFFER_LIST) "$::env(STD_CELL_LIBRARY)__clkbuff_4 $::env(STD_CELL_LIBRARY)__clkbuff_8 $::env(STD_CELL_LIBRARY)__clkbuff_12" + +set ::env(FP_PDN_RAIL_WIDTH) 0.6 + +set ::env(MAX_TRANSITION_CONSTRAINT) 1.5 +set ::env(MAX_FANOUT_CONSTRAINT) 9 +set ::env(MAX_CAPACITANCE_CONSTRAINT) 0.2 + +set ::env(GPL_CELL_PADDING) {0} +set ::env(DPL_CELL_PADDING) {0} + +set ::env(TRISTATE_CELLS) "$::env(STD_CELL_LIBRARY)__invz*"
diff --git a/gf180mcu/librelane/gf180mcu_osu_sc_gp9t3v3/drc_exclude.cells b/gf180mcu/librelane/gf180mcu_as_sc_mcu7t3v3/drc_exclude.cells similarity index 100% copy from gf180mcu/librelane/gf180mcu_osu_sc_gp9t3v3/drc_exclude.cells copy to gf180mcu/librelane/gf180mcu_as_sc_mcu7t3v3/drc_exclude.cells
diff --git a/gf180mcu/librelane/gf180mcu_as_sc_mcu7t3v3/mux2_map.v b/gf180mcu/librelane/gf180mcu_as_sc_mcu7t3v3/mux2_map.v new file mode 100644 index 0000000..2d4f5b3 --- /dev/null +++ b/gf180mcu/librelane/gf180mcu_as_sc_mcu7t3v3/mux2_map.v
@@ -0,0 +1,13 @@ +module \$_MUX_ ( + output Y, + input A, + input B, + input S + ); + gf180mcu_as_sc_mcu7t3v3__mux2_2 _TECHMAP_MUX ( + .Y(Y), + .A(A), + .B(B), + .S(S) + ); +endmodule
diff --git a/gf180mcu/librelane/gf180mcu_osu_sc_gp9t3v3/drc_exclude.cells b/gf180mcu/librelane/gf180mcu_as_sc_mcu7t3v3/pnr_exclude.cells similarity index 100% copy from gf180mcu/librelane/gf180mcu_osu_sc_gp9t3v3/drc_exclude.cells copy to gf180mcu/librelane/gf180mcu_as_sc_mcu7t3v3/pnr_exclude.cells
diff --git a/gf180mcu/librelane/gf180mcu_as_sc_mcu7t3v3/synth_exclude.cells b/gf180mcu/librelane/gf180mcu_as_sc_mcu7t3v3/synth_exclude.cells new file mode 100644 index 0000000..c85daa5 --- /dev/null +++ b/gf180mcu/librelane/gf180mcu_as_sc_mcu7t3v3/synth_exclude.cells
@@ -0,0 +1,5 @@ +gf180mcu_as_sc_mcu7t3v3__diode_2 +gf180mcu_as_sc_mcu7t3v3__clkbuff_4 +gf180mcu_as_sc_mcu7t3v3__clkbuff_8 +gf180mcu_as_sc_mcu7t3v3__clkbuff_12 +gf180mcu_as_sc_mcu7t3v3__hcf_7
diff --git a/gf180mcu/librelane/gf180mcu_as_sc_mcu7t3v3/tracks.info b/gf180mcu/librelane/gf180mcu_as_sc_mcu7t3v3/tracks.info new file mode 100644 index 0000000..16f592e --- /dev/null +++ b/gf180mcu/librelane/gf180mcu_as_sc_mcu7t3v3/tracks.info
@@ -0,0 +1,10 @@ +Metal1 X 0.28 0.56 +Metal1 Y 0.28 0.56 +Metal2 X 0.28 0.56 +Metal2 Y 0.28 0.56 +Metal3 X 0.28 0.56 +Metal3 Y 0.28 0.56 +Metal4 X 0.28 0.56 +Metal4 Y 0.28 0.56 +Metal5 X 0.45 0.90 +Metal5 Y 0.45 0.90
diff --git a/gf180mcu/librelane/gf180mcu_fd_io/config.tcl b/gf180mcu/librelane/gf180mcu_fd_io/config.tcl new file mode 100644 index 0000000..ccc332f --- /dev/null +++ b/gf180mcu/librelane/gf180mcu_fd_io/config.tcl
@@ -0,0 +1,57 @@ +set current_folder [file dirname [file normalize [info script]]] + +# Pad IO sites +set ::env(PAD_SITE_NAME) "GF_IO_Site" +set ::env(PAD_CORNER_SITE_NAME) "GF_COR_Site" + +# Create fake pad sites +# Note: This is needed if site definition are not in LEF +set ::env(PAD_FAKE_SITES) [dict create] +dict set ::env(PAD_FAKE_SITES) "GF_IO_Site" "0.1, 355" +dict set ::env(PAD_FAKE_SITES) "GF_COR_Site" "355, 355" + +# Technology lib +set ::env(PAD_LIBS) [dict create] +dict set ::env(PAD_LIBS) *_tt_025C_5v00 "\ + [glob $::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(PAD_CELL_LIBRARY)/lib/*__tt_025C_5v00.lib]\ +" +dict set ::env(PAD_LIBS) *_ff_n40C_5v50 "\ + [glob $::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(PAD_CELL_LIBRARY)/lib/*__ff_n40C_5v50.lib]\ +" +dict set ::env(PAD_LIBS) *_ss_125C_4v50 "\ + [glob $::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(PAD_CELL_LIBRARY)/lib/*__ss_125C_4v50.lib]\ +" + +# These corners are for 3.3V SCL libraries +dict set ::env(PAD_LIBS) *_tt_025C_3v30 "\ + [glob $::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(PAD_CELL_LIBRARY)/lib/*__tt_025C_3v30.lib]\ +" +dict set ::env(PAD_LIBS) *_ff_n40C_3v60 "\ + [glob $::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(PAD_CELL_LIBRARY)/lib/*__ff_n40C_3v63.lib]\ +" +dict set ::env(PAD_LIBS) *_ss_125C_3v00 "\ + [glob $::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(PAD_CELL_LIBRARY)/lib/*__ss_125C_2v97.lib]\ +" + +# Pad cells +set ::env(PAD_CORNER) "$::env(PAD_CELL_LIBRARY)__cor" +set ::env(PAD_FILLERS) "\ + $::env(PAD_CELL_LIBRARY)__fill10\ + $::env(PAD_CELL_LIBRARY)__fill5\ + $::env(PAD_CELL_LIBRARY)__fill1\ + $::env(PAD_CELL_LIBRARY)__fillnc\ +" + +# Pad io terminals (if needed) +set ::env(PAD_PLACE_IO_TERMINALS) "\ + $::env(PAD_CELL_LIBRARY)__asig_5p0/ASIG5V\ + $::env(PAD_CELL_LIBRARY)__bi_24t/PAD\ + $::env(PAD_CELL_LIBRARY)__bi_t/PAD\ + $::env(PAD_CELL_LIBRARY)__in_c/PAD\ + $::env(PAD_CELL_LIBRARY)__in_s/PAD\ + $::env(PAD_CELL_LIBRARY)__dvss/DVSS\ + $::env(PAD_CELL_LIBRARY)__dvdd/DVDD\ +" + +# Pad sites to edge offset +set ::env(PAD_EDGE_SPACING) "26"
diff --git a/gf180mcu/librelane/gf180mcu_fd_sc_mcu7t5v0/config.tcl b/gf180mcu/librelane/gf180mcu_fd_sc_mcu7t5v0/config.tcl index 28b84ad..1402701 100644 --- a/gf180mcu/librelane/gf180mcu_fd_sc_mcu7t5v0/config.tcl +++ b/gf180mcu/librelane/gf180mcu_fd_sc_mcu7t5v0/config.tcl
@@ -3,47 +3,35 @@ # Placement site for core cells # This can be found in the technology lef set ::env(PLACE_SITE) "GF018hv5v_mcu_sc7" -set ::env(PLACE_SITE_WIDTH) 0.56 -set ::env(PLACE_SITE_HEIGHT) 3.92 # welltap and endcap cell -set ::env(FP_WELLTAP_CELL) "$::env(STD_CELL_LIBRARY)__filltie" -set ::env(FP_ENDCAP_CELL) "$::env(STD_CELL_LIBRARY)__endcap" +set ::env(WELLTAP_CELL) "$::env(STD_CELL_LIBRARY)__filltie" +set ::env(ENDCAP_CELL) "$::env(STD_CELL_LIBRARY)__endcap" # defaults (can be overridden by designs): -set ::env(SYNTH_DRIVING_CELL) "$::env(STD_CELL_LIBRARY)__inv_1" -set ::env(SYNTH_DRIVING_CELL_PIN) "ZN" -set ::env(SYNTH_CLK_DRIVING_CELL) "$::env(STD_CELL_LIBRARY)__inv_4" -set ::env(SYNTH_CLK_DRIVING_CELL_PIN) "ZN" +set ::env(SYNTH_DRIVING_CELL) "$::env(STD_CELL_LIBRARY)__inv_1/ZN" +set ::env(SYNTH_CLK_DRIVING_CELL) "$::env(STD_CELL_LIBRARY)__inv_4/ZN" # update these set ::env(OUTPUT_CAP_LOAD) "72.91" ; # femtofarad from pin I in liberty file -set ::env(SYNTH_MIN_BUF_PORT) "$::env(STD_CELL_LIBRARY)__buf_1 I Z" -set ::env(SYNTH_TIEHI_PORT) "$::env(STD_CELL_LIBRARY)__tieh Z" -set ::env(SYNTH_TIELO_PORT) "$::env(STD_CELL_LIBRARY)__tiel ZN" - -# Placement defaults -set ::env(PL_LIB) $::env(LIB_TYPICAL) +set ::env(SYNTH_BUFFER_CELL) "$::env(STD_CELL_LIBRARY)__buf_1/I/Z" +set ::env(SYNTH_TIEHI_CELL) "$::env(STD_CELL_LIBRARY)__tieh/Z" +set ::env(SYNTH_TIELO_CELL) "$::env(STD_CELL_LIBRARY)__tiel/ZN" # Fillcell insertion -set ::env(FILL_CELL) "$::env(STD_CELL_LIBRARY)__fill_*" -set ::env(DECAP_CELL) "$::env(STD_CELL_LIBRARY)__fillcap_*" +set ::env(FILL_CELLS) "$::env(STD_CELL_LIBRARY)__fill_*" +set ::env(DECAP_CELLS) "$::env(STD_CELL_LIBRARY)__fillcap_*" # Diode Insertion -# A fake diode has to be created, for now don't use any strategy that uses fake diode -# set ::env(FAKEDIODE_CELL) "" -set ::env(DIODE_CELL) "$::env(STD_CELL_LIBRARY)__antenna" -set ::env(DIODE_CELL_PIN) "I" -set ::env(DIODE_INSERTION_STRATEGY) {4} +set ::env(DIODE_CELL) "$::env(STD_CELL_LIBRARY)__antenna/I" set ::env(CELL_PAD_EXCLUDE) "$::env(STD_CELL_LIBRARY)__filltie $::env(STD_CELL_LIBRARY)__fill_* $::env(STD_CELL_LIBRARY)__endcap" # TritonCTS configurations set ::env(CTS_ROOT_BUFFER) "$::env(STD_CELL_LIBRARY)__clkbuf_16" -set ::env(CTS_CLK_BUFFER_LIST) "$::env(STD_CELL_LIBRARY)__clkbuf_2 $::env(STD_CELL_LIBRARY)__clkbuf_4 $::env(STD_CELL_LIBRARY)__clkbuf_8" -set ::env(CTS_MAX_CAP) 0.5 +set ::env(CTS_CLK_BUFFERS) "$::env(STD_CELL_LIBRARY)__clkbuf_2 $::env(STD_CELL_LIBRARY)__clkbuf_4 $::env(STD_CELL_LIBRARY)__clkbuf_8" -set ::env(FP_PDN_RAIL_WIDTH) 0.6 +set ::env(PDN_RAIL_WIDTH) 0.6 # The library maximum transition is 8.9ns; setting it to lower value set ::env(MAX_TRANSITION_CONSTRAINT) 3 @@ -53,4 +41,7 @@ set ::env(GPL_CELL_PADDING) {0} set ::env(DPL_CELL_PADDING) {0} -set ::env(TRISTATE_CELL_PREFIX) "$::env(STD_CELL_LIBRARY)__bufz" +set ::env(TRISTATE_CELLS) "$::env(STD_CELL_LIBRARY)__bufz*" + +set ::env(SYNTH_CLOCKGATE_POSEDGE_ICG) "$::env(STD_CELL_LIBRARY)__icgtp_1/E/CLK/Q" +set ::env(SYNTH_CLOCKGATE_NEGEDGE_ICG) "$::env(STD_CELL_LIBRARY)__icgtn_1/E/CLKN/Q"
diff --git a/gf180mcu/librelane/gf180mcu_fd_sc_mcu7t5v0/latch_map.v b/gf180mcu/librelane/gf180mcu_fd_sc_mcu7t5v0/latch_map.v new file mode 100644 index 0000000..a5c4336 --- /dev/null +++ b/gf180mcu/librelane/gf180mcu_fd_sc_mcu7t5v0/latch_map.v
@@ -0,0 +1,31 @@ +// positive D-latch +module \$_DLATCH_P_ (input E, input D, output Q); + gf180mcu_fd_sc_mcu7t5v0__latq_1 _TECHMAP_REPLACE_ ( + .E (E), + .D (D), + .Q (Q) + ); +endmodule + +// positive D-latch, active low reset +module \$_DLATCH_PN0_ (input E, input R, input D, output Q); + gf180mcu_fd_sc_mcu7t5v0__latrnq_1 _TECHMAP_REPLACE_ ( + .E (E), + .D (D), + .RN (R), + .Q (Q) + ); +endmodule + +// positive D-latch, active low set/reset +//gf180mcu_fd_sc_mcu7t5v0__latrsnq_1 ( E, D, RN, SETN, Q); + +// positive D-latch, active low set +module \$_DLATCH_PN1_ (input E, input R, input D, output Q); + gf180mcu_fd_sc_mcu7t5v0__latsnq_1 _TECHMAP_REPLACE_ ( + .E (E), + .D (D), + .SETN (R), + .Q (Q) + ); +endmodule
diff --git a/gf180mcu/librelane/gf180mcu_fd_sc_mcu7t5v0/drc_exclude.cells b/gf180mcu/librelane/gf180mcu_fd_sc_mcu7t5v0/pnr_exclude.cells similarity index 100% rename from gf180mcu/librelane/gf180mcu_fd_sc_mcu7t5v0/drc_exclude.cells rename to gf180mcu/librelane/gf180mcu_fd_sc_mcu7t5v0/pnr_exclude.cells
diff --git a/gf180mcu/librelane/gf180mcu_fd_sc_mcu7t5v0/no_synth.cells b/gf180mcu/librelane/gf180mcu_fd_sc_mcu7t5v0/synth_exclude.cells similarity index 100% rename from gf180mcu/librelane/gf180mcu_fd_sc_mcu7t5v0/no_synth.cells rename to gf180mcu/librelane/gf180mcu_fd_sc_mcu7t5v0/synth_exclude.cells
diff --git a/gf180mcu/librelane/gf180mcu_fd_sc_mcu9t5v0/config.tcl b/gf180mcu/librelane/gf180mcu_fd_sc_mcu9t5v0/config.tcl index 922a51f..6eb3100 100644 --- a/gf180mcu/librelane/gf180mcu_fd_sc_mcu9t5v0/config.tcl +++ b/gf180mcu/librelane/gf180mcu_fd_sc_mcu9t5v0/config.tcl
@@ -3,45 +3,35 @@ # Placement site for core cells # This can be found in the technology lef set ::env(PLACE_SITE) "GF018hv5v_green_sc9" -set ::env(PLACE_SITE_WIDTH) 0.56 -set ::env(PLACE_SITE_HEIGHT) 3.92 # welltap and endcap cell set ::env(FP_WELLTAP_CELL) "$::env(STD_CELL_LIBRARY)__filltie" set ::env(FP_ENDCAP_CELL) "$::env(STD_CELL_LIBRARY)__endcap" # defaults (can be overridden by designs): -set ::env(SYNTH_DRIVING_CELL) "$::env(STD_CELL_LIBRARY)__inv_1" -set ::env(SYNTH_DRIVING_CELL_PIN) "ZN" -set ::env(SYNTH_CLK_DRIVING_CELL) "$::env(STD_CELL_LIBRARY)__inv_4" -set ::env(SYNTH_CLK_DRIVING_CELL_PIN) "ZN" +set ::env(SYNTH_DRIVING_CELL) "$::env(STD_CELL_LIBRARY)__inv_1/ZN" +set ::env(SYNTH_CLK_DRIVING_CELL) "$::env(STD_CELL_LIBRARY)__inv_4/ZN" # update these set ::env(OUTPUT_CAP_LOAD) "72.91" ; # femtofarad from pin I in liberty file -set ::env(SYNTH_MIN_BUF_PORT) "$::env(STD_CELL_LIBRARY)__buf_1 I Z" -set ::env(SYNTH_TIEHI_PORT) "$::env(STD_CELL_LIBRARY)__tieh Z" -set ::env(SYNTH_TIELO_PORT) "$::env(STD_CELL_LIBRARY)__tiel ZN" - -# Placement defaults -set ::env(PL_LIB) $::env(LIB_TYPICAL) +set ::env(SYNTH_BUFFER_CELL) "$::env(STD_CELL_LIBRARY)__buf_1/I/Z" +set ::env(SYNTH_TIEHI_CELL) "$::env(STD_CELL_LIBRARY)__tieh/Z" +set ::env(SYNTH_TIELO_CELL) "$::env(STD_CELL_LIBRARY)__tiel/ZN" # Fillcell insertion -set ::env(FILL_CELL) "$::env(STD_CELL_LIBRARY)__fill_*" -set ::env(DECAP_CELL) "$::env(STD_CELL_LIBRARY)__fillcap_*" +set ::env(FILL_CELLS) "$::env(STD_CELL_LIBRARY)__fill_*" +set ::env(DECAP_CELLS) "$::env(STD_CELL_LIBRARY)__fillcap_*" # Diode Insertion # A fake diode has to be created, for now don't use any strategy that uses fake diode # set ::env(FAKEDIODE_CELL) "" -set ::env(DIODE_CELL) "$::env(STD_CELL_LIBRARY)__antenna" -set ::env(DIODE_CELL_PIN) "I" -set ::env(DIODE_INSERTION_STRATEGY) {4} +set ::env(DIODE_CELL) "$::env(STD_CELL_LIBRARY)__antenna/I" set ::env(CELL_PAD_EXCLUDE) "$::env(STD_CELL_LIBRARY)__filltie $::env(STD_CELL_LIBRARY)__fill_* $::env(STD_CELL_LIBRARY)__endcap" # TritonCTS configurations set ::env(CTS_ROOT_BUFFER) "$::env(STD_CELL_LIBRARY)__clkbuf_16" -set ::env(CTS_CLK_BUFFER_LIST) "$::env(STD_CELL_LIBRARY)__clkbuf_2 $::env(STD_CELL_LIBRARY)__clkbuf_4 $::env(STD_CELL_LIBRARY)__clkbuf_8" -set ::env(CTS_MAX_CAP) 0.5 +set ::env(CTS_CLK_BUFFERS) "$::env(STD_CELL_LIBRARY)__clkbuf_2 $::env(STD_CELL_LIBRARY)__clkbuf_4 $::env(STD_CELL_LIBRARY)__clkbuf_8" set ::env(FP_PDN_RAIL_WIDTH) 0.6 @@ -53,4 +43,7 @@ set ::env(GPL_CELL_PADDING) {0} set ::env(DPL_CELL_PADDING) {0} -set ::env(TRISTATE_CELL_PREFIX) "$::env(STD_CELL_LIBRARY)__bufz" +set ::env(TRISTATE_CELLS) "$::env(STD_CELL_LIBRARY)__bufz*" + +set ::env(SYNTH_CLOCKGATE_POSEDGE_ICG) "$::env(STD_CELL_LIBRARY)__icgtp_1/E/CLK/Q" +set ::env(SYNTH_CLOCKGATE_NEGEDGE_ICG) "$::env(STD_CELL_LIBRARY)__icgtn_1/E/CLKN/Q"
diff --git a/gf180mcu/librelane/gf180mcu_fd_sc_mcu9t5v0/latch_map.v b/gf180mcu/librelane/gf180mcu_fd_sc_mcu9t5v0/latch_map.v new file mode 100644 index 0000000..33e84f5 --- /dev/null +++ b/gf180mcu/librelane/gf180mcu_fd_sc_mcu9t5v0/latch_map.v
@@ -0,0 +1,31 @@ +// positive D-latch +module \$_DLATCH_P_ (input E, input D, output Q); + gf180mcu_fd_sc_mcu9t5v0__latq_1 _TECHMAP_REPLACE_ ( + .E (E), + .D (D), + .Q (Q) + ); +endmodule + +// positive D-latch, active low reset +module \$_DLATCH_PN0_ (input E, input R, input D, output Q); + gf180mcu_fd_sc_mcu9t5v0__latrnq_1 _TECHMAP_REPLACE_ ( + .E (E), + .D (D), + .RN (R), + .Q (Q) + ); +endmodule + +// positive D-latch, active low set/reset +//gf180mcu_fd_sc_mcu9t5v0__latrsnq_1 ( E, D, RN, SETN, Q); + +// positive D-latch, active low set +module \$_DLATCH_PN1_ (input E, input R, input D, output Q); + gf180mcu_fd_sc_mcu9t5v0__latsnq_1 _TECHMAP_REPLACE_ ( + .E (E), + .D (D), + .SETN (R), + .Q (Q) + ); +endmodule
diff --git a/gf180mcu/librelane/gf180mcu_fd_sc_mcu9t5v0/no_synth.cells b/gf180mcu/librelane/gf180mcu_fd_sc_mcu9t5v0/no_synth.cells deleted file mode 100644 index c096d02..0000000 --- a/gf180mcu/librelane/gf180mcu_fd_sc_mcu9t5v0/no_synth.cells +++ /dev/null
@@ -1,12 +0,0 @@ -SDFFSNQ_X4 -SDFFQ_X1 -SDFFQ_X2 -SDFFQ_X4 -SDFFRNQ_X1 -SDFFRNQ_X2 -SDFFRNQ_X4 -SDFFRSNQ_X1 -SDFFRSNQ_X2 -SDFFRSNQ_X4 -SDFFSNQ_X1 -SDFFSNQ_X2 \ No newline at end of file
diff --git a/gf180mcu/librelane/gf180mcu_osu_sc_gp12t3v3/drc_exclude.cells b/gf180mcu/librelane/gf180mcu_fd_sc_mcu9t5v0/pnr_exclude.cells similarity index 100% copy from gf180mcu/librelane/gf180mcu_osu_sc_gp12t3v3/drc_exclude.cells copy to gf180mcu/librelane/gf180mcu_fd_sc_mcu9t5v0/pnr_exclude.cells
diff --git a/gf180mcu/librelane/gf180mcu_fd_sc_mcu9t5v0/synth_exclude.cells b/gf180mcu/librelane/gf180mcu_fd_sc_mcu9t5v0/synth_exclude.cells new file mode 100644 index 0000000..52ed702 --- /dev/null +++ b/gf180mcu/librelane/gf180mcu_fd_sc_mcu9t5v0/synth_exclude.cells
@@ -0,0 +1,12 @@ +gf180mcu_fd_sc_mcu9t5v0__sdffq_1 +gf180mcu_fd_sc_mcu9t5v0__sdffq_2 +gf180mcu_fd_sc_mcu9t5v0__sdffq_4 +gf180mcu_fd_sc_mcu9t5v0__sdffrnq_1 +gf180mcu_fd_sc_mcu9t5v0__sdffrnq_2 +gf180mcu_fd_sc_mcu9t5v0__sdffrnq_4 +gf180mcu_fd_sc_mcu9t5v0__sdffrsnq_1 +gf180mcu_fd_sc_mcu9t5v0__sdffrsnq_2 +gf180mcu_fd_sc_mcu9t5v0__sdffrsnq_4 +gf180mcu_fd_sc_mcu9t5v0__sdffsnq_1 +gf180mcu_fd_sc_mcu9t5v0__sdffsnq_2 +gf180mcu_fd_sc_mcu9t5v0__sdffsnq_4
diff --git a/gf180mcu/librelane/gf180mcu_ocd_io/config.tcl b/gf180mcu/librelane/gf180mcu_ocd_io/config.tcl new file mode 100644 index 0000000..d1c2af9 --- /dev/null +++ b/gf180mcu/librelane/gf180mcu_ocd_io/config.tcl
@@ -0,0 +1,65 @@ +set current_folder [file dirname [file normalize [info script]]] + +# Pad IO sites +set ::env(PAD_SITE_NAME) "GF_IO_Site" +set ::env(PAD_CORNER_SITE_NAME) "GF_COR_Site" + +# Create fake pad sites +# Note: This is needed if site definition are not in LEF +set ::env(PAD_FAKE_SITES) [dict create] +dict set ::env(PAD_FAKE_SITES) "GF_IO_Site" "0.1, 355" +dict set ::env(PAD_FAKE_SITES) "GF_COR_Site" "355, 355" + +# Technology lib +set ::env(PAD_LIBS) [dict create] +dict set ::env(PAD_LIBS) *_tt_025C_5v00 "\ + [glob $::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(PAD_CELL_LIBRARY)/lib/*__tt_025C_5v00.lib]\ +" +dict set ::env(PAD_LIBS) *_ff_n40C_5v50 "\ + [glob $::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(PAD_CELL_LIBRARY)/lib/*__ff_n40C_5v50.lib]\ +" +dict set ::env(PAD_LIBS) *_ss_125C_4v50 "\ + [glob $::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(PAD_CELL_LIBRARY)/lib/*__ss_125C_4v50.lib]\ +" + +# These corners are for 3.3V SCL libraries +dict set ::env(PAD_LIBS) *_tt_025C_3v30 "\ + [glob $::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(PAD_CELL_LIBRARY)/lib/*__tt_025C_3v30.lib]\ +" +dict set ::env(PAD_LIBS) *_ff_n40C_3v60 "\ + [glob $::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(PAD_CELL_LIBRARY)/lib/*__ff_n40C_3v63.lib]\ +" +dict set ::env(PAD_LIBS) *_ss_125C_3v00 "\ + [glob $::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(PAD_CELL_LIBRARY)/lib/*__ss_125C_2v97.lib]\ +" + +# Override +set ::env(PAD_GDS) "\ + $::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(PAD_CELL_LIBRARY)/gds/$::env(PAD_CELL_LIBRARY).gds\ +" +set ::env(PAD_CDLS) "" + +# Pad cells +set ::env(PAD_CORNER) "$::env(PAD_CELL_LIBRARY)__cor" +set ::env(PAD_FILLERS) "\ + $::env(PAD_CELL_LIBRARY)__fill10\ + $::env(PAD_CELL_LIBRARY)__fill5\ + $::env(PAD_CELL_LIBRARY)__fill1\ + $::env(PAD_CELL_LIBRARY)__fillnc\ +" + +# Pad io terminals (if needed) +set ::env(PAD_PLACE_IO_TERMINALS) "\ + $::env(PAD_CELL_LIBRARY)__asig_5p0/ASIG5V\ + $::env(PAD_CELL_LIBRARY)__bi_24t/PAD\ + $::env(PAD_CELL_LIBRARY)__bi_t/PAD\ + $::env(PAD_CELL_LIBRARY)__in_c/PAD\ + $::env(PAD_CELL_LIBRARY)__in_s/PAD\ + $::env(PAD_CELL_LIBRARY)__dvss/DVSS\ + $::env(PAD_CELL_LIBRARY)__dvdd/DVDD\ + $::env(PAD_CELL_LIBRARY)__vss/VSS\ + $::env(PAD_CELL_LIBRARY)__vdd/VDD\ +" + +# Pad sites to edge offset +set ::env(PAD_EDGE_SPACING) "26"
diff --git a/gf180mcu/librelane/gf180mcu_osu_sc_gp12t3v3/config.tcl b/gf180mcu/librelane/gf180mcu_osu_sc_gp12t3v3/config.tcl index a5a893e..12c1f79 100644 --- a/gf180mcu/librelane/gf180mcu_osu_sc_gp12t3v3/config.tcl +++ b/gf180mcu/librelane/gf180mcu_osu_sc_gp12t3v3/config.tcl
@@ -6,54 +6,54 @@ set ::env(VDD_PIN_VOLTAGE) "3.30" -set ::env(STD_CELL_POWER_PINS) "VDD" -set ::env(STD_CELL_GROUND_PINS) "VSS" +set ::env(SCL_POWER_PINS) "VDD" +set ::env(SCL_GROUND_PINS) "VSS" -# Lib Files (override gf180mcu defaults) -set ::env(LIB_SYNTH) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/lib/$::env(STD_CELL_LIBRARY)__tt_025C_3v30.lib" -set ::env(LIB_FASTEST) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/lib/$::env(STD_CELL_LIBRARY)__tt_025C_3v30.lib" -set ::env(LIB_SLOWEST) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/lib/$::env(STD_CELL_LIBRARY)__tt_025C_3v30.lib" -set ::env(LIB_TYPICAL) $::env(LIB_SYNTH) +# Technology lib +set ::env(LIB) [dict create] +dict set ::env(LIB) *_tt_025C_3v30 "\ + $::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/lib/$::env(STD_CELL_LIBRARY)__tt_025C_3v30.lib\ +" + +# Corners +set ::env(STA_CORNERS) "\ + nom_tt_025C_3v30 \ +" + +set ::env(DEFAULT_CORNER) "nom_tt_025C_3v30" # Technology LEF (override gf180mcu defaults) -set ::env(TECH_LEF_MIN) $::env(TECH_LEF) -set ::env(TECH_LEF_MAX) $::env(TECH_LEF) +set ::env(TECH_LEFS) [dict create] +dict set ::env(TECH_LEFS) nom_* [glob "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/techlef/*__nom.tlef"] + +set ::env(CELL_CDLS) "" # Placement site for core cells # This can be found in the technology lef set ::env(PLACE_SITE) "gf180mcu_osu_sc_gp12t3v3" -set ::env(PLACE_SITE_WIDTH) 0.10 -set ::env(PLACE_SITE_HEIGHT) 6.35 # welltap and endcap cell # set ::env(FP_WELLTAP_CELL) "$::env(STD_CELL_LIBRARY)__filltie" # set ::env(FP_ENDCAP_CELL) "$::env(STD_CELL_LIBRARY)__endcap" -set ::env(FP_WELLTAP_CELL) "" -set ::env(FP_ENDCAP_CELL) "" +set ::env(WELLTAP_CELL) "$::env(STD_CELL_LIBRARY)__fill_1" +set ::env(ENDCAP_CELL) "$::env(STD_CELL_LIBRARY)__fill_1" # defaults (can be overridden by designs): -set ::env(SYNTH_DRIVING_CELL) "$::env(STD_CELL_LIBRARY)__inv_1" -set ::env(SYNTH_DRIVING_CELL_PIN) "Y" -set ::env(SYNTH_CLK_DRIVING_CELL) "$::env(STD_CELL_LIBRARY)__clkinv_4" -set ::env(SYNTH_CLK_DRIVING_CELL_PIN) "Y" +set ::env(SYNTH_DRIVING_CELL) "$::env(STD_CELL_LIBRARY)__inv_1/Y" +set ::env(SYNTH_CLK_DRIVING_CELL) "$::env(STD_CELL_LIBRARY)__clkinv_4/Y" # update these set ::env(OUTPUT_CAP_LOAD) "4.046" ; # femtofarad from pin A in liberty file -set ::env(SYNTH_MIN_BUF_PORT) "$::env(STD_CELL_LIBRARY)__buf_1 A Y" -set ::env(SYNTH_TIEHI_PORT) "$::env(STD_CELL_LIBRARY)__tieh Y" -set ::env(SYNTH_TIELO_PORT) "$::env(STD_CELL_LIBRARY)__tiel Y" - -# Placement defaults -set ::env(PL_LIB) $::env(LIB_TYPICAL) +set ::env(SYNTH_BUFFER_CELL) "$::env(STD_CELL_LIBRARY)__buf_1/A/Y" +set ::env(SYNTH_TIEHI_CELL) "$::env(STD_CELL_LIBRARY)__tieh/Y" +set ::env(SYNTH_TIELO_CELL) "$::env(STD_CELL_LIBRARY)__tiel/Y" # Fillcell insertion -set ::env(FILL_CELL) "$::env(STD_CELL_LIBRARY)__fill_*" -set ::env(DECAP_CELL) "$::env(STD_CELL_LIBRARY)__decap_*" +set ::env(FILL_CELLS) "$::env(STD_CELL_LIBRARY)__fill_*" +set ::env(DECAP_CELLS) "$::env(STD_CELL_LIBRARY)__decap_*" # Diode Insertion -set ::env(DIODE_CELL) "$::env(STD_CELL_LIBRARY)__ant" -set ::env(DIODE_CELL_PIN) "A" -set ::env(DIODE_INSERTION_STRATEGY) {4} +set ::env(DIODE_CELL) "$::env(STD_CELL_LIBRARY)__ant/A" # set ::env(CELL_PAD_EXCLUDE) "$::env(STD_CELL_LIBRARY)__filltie $::env(STD_CELL_LIBRARY)__fill_* $::env(STD_CELL_LIBRARY)__endcap" set ::env(CELL_PAD_EXCLUDE) "" @@ -61,7 +61,6 @@ # TritonCTS configurations set ::env(CTS_ROOT_BUFFER) "$::env(STD_CELL_LIBRARY)__clkbuf_16" set ::env(CTS_CLK_BUFFER_LIST) "$::env(STD_CELL_LIBRARY)__clkbuf_2 $::env(STD_CELL_LIBRARY)__clkbuf_4 $::env(STD_CELL_LIBRARY)__clkbuf_8" -set ::env(CTS_MAX_CAP) 0.5 set ::env(FP_PDN_RAIL_WIDTH) 0.6 @@ -73,4 +72,4 @@ set ::env(GPL_CELL_PADDING) {0} set ::env(DPL_CELL_PADDING) {0} -set ::env(TRISTATE_CELL_PREFIX) "$::env(STD_CELL_LIBRARY)__tbuf" +set ::env(TRISTATE_CELLS) "$::env(STD_CELL_LIBRARY)__tbuf*"
diff --git a/gf180mcu/librelane/gf180mcu_osu_sc_gp12t3v3/no_synth.cells b/gf180mcu/librelane/gf180mcu_osu_sc_gp12t3v3/no_synth.cells deleted file mode 100644 index e69de29..0000000 --- a/gf180mcu/librelane/gf180mcu_osu_sc_gp12t3v3/no_synth.cells +++ /dev/null
diff --git a/gf180mcu/librelane/gf180mcu_osu_sc_gp12t3v3/drc_exclude.cells b/gf180mcu/librelane/gf180mcu_osu_sc_gp12t3v3/pnr_exclude.cells similarity index 100% rename from gf180mcu/librelane/gf180mcu_osu_sc_gp12t3v3/drc_exclude.cells rename to gf180mcu/librelane/gf180mcu_osu_sc_gp12t3v3/pnr_exclude.cells
diff --git a/gf180mcu/librelane/gf180mcu_osu_sc_gp12t3v3/drc_exclude.cells b/gf180mcu/librelane/gf180mcu_osu_sc_gp12t3v3/synth_exclude.cells.cells similarity index 100% copy from gf180mcu/librelane/gf180mcu_osu_sc_gp12t3v3/drc_exclude.cells copy to gf180mcu/librelane/gf180mcu_osu_sc_gp12t3v3/synth_exclude.cells.cells
diff --git a/gf180mcu/librelane/gf180mcu_osu_sc_gp9t3v3/config.tcl b/gf180mcu/librelane/gf180mcu_osu_sc_gp9t3v3/config.tcl index d0e8267..c838819 100644 --- a/gf180mcu/librelane/gf180mcu_osu_sc_gp9t3v3/config.tcl +++ b/gf180mcu/librelane/gf180mcu_osu_sc_gp9t3v3/config.tcl
@@ -2,58 +2,57 @@ # Standard cell library (override gf180mcu default) set ::env(STD_CELL_LIBRARY) gf180mcu_osu_sc_gp9t3v3 -set ::env(STD_CELL_LIBRARY_OPT) gf180mcu_osu_sc_gp9t3v3 set ::env(VDD_PIN_VOLTAGE) "3.30" -set ::env(STD_CELL_POWER_PINS) "VDD" -set ::env(STD_CELL_GROUND_PINS) "VSS" +set ::env(SCL_POWER_PINS) "VDD" +set ::env(SCL_GROUND_PINS) "VSS" -# Lib Files (override gf180mcu defaults) -set ::env(LIB_SYNTH) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/lib/$::env(STD_CELL_LIBRARY)__tt_025C_3v30.lib" -set ::env(LIB_FASTEST) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/lib/$::env(STD_CELL_LIBRARY)__tt_025C_3v30.lib" -set ::env(LIB_SLOWEST) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/lib/$::env(STD_CELL_LIBRARY)__tt_025C_3v30.lib" -set ::env(LIB_TYPICAL) $::env(LIB_SYNTH) +# Technology lib +set ::env(LIB) [dict create] +dict set ::env(LIB) *_tt_025C_3v30 "\ + $::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/lib/$::env(STD_CELL_LIBRARY)__tt_025C_3v30.lib\ +" + +# Corners +set ::env(STA_CORNERS) "\ + nom_tt_025C_3v30 \ +" + +set ::env(DEFAULT_CORNER) "nom_tt_025C_3v30" # Technology LEF (override gf180mcu defaults) -set ::env(TECH_LEF_MIN) $::env(TECH_LEF) -set ::env(TECH_LEF_MAX) $::env(TECH_LEF) +set ::env(TECH_LEFS) [dict create] +dict set ::env(TECH_LEFS) nom_* [glob "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/techlef/*__nom.tlef"] + +set ::env(CELL_CDLS) "" # Placement site for core cells # This can be found in the technology lef set ::env(PLACE_SITE) "gf180mcu_osu_sc_gp9t3v3" -set ::env(PLACE_SITE_WIDTH) 0.10 -set ::env(PLACE_SITE_HEIGHT) 6.35 # welltap and endcap cell # set ::env(FP_WELLTAP_CELL) "$::env(STD_CELL_LIBRARY)__filltie" # set ::env(FP_ENDCAP_CELL) "$::env(STD_CELL_LIBRARY)__endcap" -set ::env(FP_WELLTAP_CELL) "" -set ::env(FP_ENDCAP_CELL) "" +set ::env(FP_WELLTAP_CELL) "$::env(STD_CELL_LIBRARY)__fill_1" +set ::env(FP_ENDCAP_CELL) "$::env(STD_CELL_LIBRARY)__fill_1" # defaults (can be overridden by designs): -set ::env(SYNTH_DRIVING_CELL) "$::env(STD_CELL_LIBRARY)__inv_1" -set ::env(SYNTH_DRIVING_CELL_PIN) "Y" -set ::env(SYNTH_CLK_DRIVING_CELL) "$::env(STD_CELL_LIBRARY)__clkinv_4" -set ::env(SYNTH_CLK_DRIVING_CELL_PIN) "Y" +set ::env(SYNTH_DRIVING_CELL) "$::env(STD_CELL_LIBRARY)__inv_1/Y" +set ::env(SYNTH_CLK_DRIVING_CELL) "$::env(STD_CELL_LIBRARY)__clkinv_4/Y" # update these set ::env(OUTPUT_CAP_LOAD) "4.046" ; # femtofarad from pin A in liberty file -set ::env(SYNTH_MIN_BUF_PORT) "$::env(STD_CELL_LIBRARY)__buf_1 A Y" -set ::env(SYNTH_TIEHI_PORT) "$::env(STD_CELL_LIBRARY)__tieh Y" -set ::env(SYNTH_TIELO_PORT) "$::env(STD_CELL_LIBRARY)__tiel Y" - -# Placement defaults -set ::env(PL_LIB) $::env(LIB_TYPICAL) +set ::env(SYNTH_BUFFER_CELL) "$::env(STD_CELL_LIBRARY)__buf_1/A/Y" +set ::env(SYNTH_TIEHI_CELL) "$::env(STD_CELL_LIBRARY)__tieh/Y" +set ::env(SYNTH_TIELO_CELL) "$::env(STD_CELL_LIBRARY)__tiel/Y" # Fillcell insertion -set ::env(FILL_CELL) "$::env(STD_CELL_LIBRARY)__fill_*" -set ::env(DECAP_CELL) "$::env(STD_CELL_LIBRARY)__decap_*" +set ::env(FILL_CELLS) "$::env(STD_CELL_LIBRARY)__fill_*" +set ::env(DECAP_CELLS) "$::env(STD_CELL_LIBRARY)__decap_*" # Diode Insertion -set ::env(DIODE_CELL) "$::env(STD_CELL_LIBRARY)__ant" -set ::env(DIODE_CELL_PIN) "A" -set ::env(DIODE_INSERTION_STRATEGY) {4} +set ::env(DIODE_CELL) "$::env(STD_CELL_LIBRARY)__ant/A" # set ::env(CELL_PAD_EXCLUDE) "$::env(STD_CELL_LIBRARY)__filltie $::env(STD_CELL_LIBRARY)__fill_* $::env(STD_CELL_LIBRARY)__endcap" set ::env(CELL_PAD_EXCLUDE) "" @@ -61,7 +60,6 @@ # TritonCTS configurations set ::env(CTS_ROOT_BUFFER) "$::env(STD_CELL_LIBRARY)__clkbuf_16" set ::env(CTS_CLK_BUFFER_LIST) "$::env(STD_CELL_LIBRARY)__clkbuf_2 $::env(STD_CELL_LIBRARY)__clkbuf_4 $::env(STD_CELL_LIBRARY)__clkbuf_8" -set ::env(CTS_MAX_CAP) 0.5 set ::env(FP_PDN_RAIL_WIDTH) 0.6 @@ -73,4 +71,4 @@ set ::env(GPL_CELL_PADDING) {0} set ::env(DPL_CELL_PADDING) {0} -set ::env(TRISTATE_CELL_PREFIX) "$::env(STD_CELL_LIBRARY)__tbuf" +set ::env(TRISTATE_CELLS) "$::env(STD_CELL_LIBRARY)__tbuf*"
diff --git a/gf180mcu/librelane/gf180mcu_osu_sc_gp9t3v3/no_synth.cells b/gf180mcu/librelane/gf180mcu_osu_sc_gp9t3v3/no_synth.cells deleted file mode 100644 index e69de29..0000000 --- a/gf180mcu/librelane/gf180mcu_osu_sc_gp9t3v3/no_synth.cells +++ /dev/null
diff --git a/gf180mcu/librelane/gf180mcu_osu_sc_gp9t3v3/drc_exclude.cells b/gf180mcu/librelane/gf180mcu_osu_sc_gp9t3v3/pnr_exclude.cells similarity index 100% rename from gf180mcu/librelane/gf180mcu_osu_sc_gp9t3v3/drc_exclude.cells rename to gf180mcu/librelane/gf180mcu_osu_sc_gp9t3v3/pnr_exclude.cells
diff --git a/gf180mcu/librelane/gf180mcu_osu_sc_gp9t3v3/drc_exclude.cells b/gf180mcu/librelane/gf180mcu_osu_sc_gp9t3v3/synth_exclude.cells similarity index 100% copy from gf180mcu/librelane/gf180mcu_osu_sc_gp9t3v3/drc_exclude.cells copy to gf180mcu/librelane/gf180mcu_osu_sc_gp9t3v3/synth_exclude.cells
diff --git a/scripts/configure b/scripts/configure index 97d4d32..8146699 100755 --- a/scripts/configure +++ b/scripts/configure
@@ -618,13 +618,13 @@ GF180MCU_OCD_IP_SRAM_PATH GF180MCU_OCD_IO_PATH GF180MCU_AS_SC_PATH +GF180MCU_RE_EFUSE_PATH GF180MCU_OSU_SC_PATH GF180MCU_OCD_ALPHA_PATH GF180MCU_FD_IP_SRAM_PATH GF180MCU_FD_SC_MCU9T5V0_PATH GF180MCU_FD_SC_MCU7T5V0_PATH GF180MCU_FD_IO_PATH -GF180MCU_WS_KLAYOUT_PATH GF180MCU_FD_PV_PATH GF180MCU_FD_PR_PATH SKY130_OSU_T18_PATH @@ -750,7 +750,6 @@ enable_osu_t18_sky130 enable_primitive_gf180mcu enable_verification_gf180mcu -enable_klayout_gf180mcu enable_io_gf180mcu enable_sc_7t5v0_gf180mcu enable_sc_9t5v0_gf180mcu @@ -758,6 +757,7 @@ enable_alpha_gf180mcu enable_osu_sc_gf180mcu enable_avalon_sc_gf180mcu +enable_re_efuse_gf180mcu enable_ocd_io_gf180mcu enable_ocd_sram_gf180mcu with_reference @@ -1484,9 +1484,6 @@ --enable-verification-gf180mcu[=path] Install gf180mcu_fd_pv. If path is omitted, the repository will be downloaded. [default=enabled] - --enable-klayout-gf180mcu[=path] - Install gf180mcu_ws_klayout. If path is omitted, the repository - will be downloaded. [default=enabled] --enable-io-gf180mcu[=path] Install gf180mcu_fd_io. If path is omitted, the repository will be downloaded. [default=enabled] @@ -1508,6 +1505,9 @@ --enable-avalon-sc-gf180mcu[=path] Install gf180mcu_as_sc. If path is omitted, the repository will be downloaded. [default=enabled] + --enable-re-efuse-gf180mcu[=path] + Install gf180mcu_re_efuse. If path is omitted, the repository + will be downloaded. [default=enabled] --enable-ocd-io-gf180mcu[=path] Install gf180mcu_ocd_io. If path is omitted, the repository will be downloaded. [default=enabled] @@ -3799,50 +3799,6 @@ # echo target targetvar flag location - GF180MCU_WS_KLAYOUT_PATH="" - - # Check whether --enable-klayout-gf180mcu was given. -if test ${enable_klayout_gf180mcu+y} -then : - enableval=$enable_klayout_gf180mcu; - if test "$enableval" == "yes" -o "$enableval" == "YES"; then - { printf "%s\n" "$as_me:${as_lineno-$LINENO}: Package 'gf180mcu_ws_klayout' will be installed automatically during make." >&5 -printf "%s\n" "$as_me: Package 'gf180mcu_ws_klayout' will be installed automatically during make." >&6;} - export GF180MCU_WS_KLAYOUT_PATH=../sources/gf180mcu_ws_klayout - elif test "$enableval" == "no" -o "$enableval" == "NO"; then - { printf "%s\n" "$as_me:${as_lineno-$LINENO}: Disabling package 'gf180mcu_ws_klayout'" >&5 -printf "%s\n" "$as_me: Disabling package 'gf180mcu_ws_klayout'" >&6;} - export GF180MCU_WS_KLAYOUT_PATH="" - else - GF180MCU_WS_KLAYOUT_PATH=$enableval - { printf "%s\n" "$as_me:${as_lineno-$LINENO}: Enabling package 'gf180mcu_ws_klayout' at $GF180MCU_WS_KLAYOUT_PATH" >&5 -printf "%s\n" "$as_me: Enabling package 'gf180mcu_ws_klayout' at $GF180MCU_WS_KLAYOUT_PATH" >&6;} - fi - GF180MCU_WS_KLAYOUT_PATH=`realpath $GF180MCU_WS_KLAYOUT_PATH` - -else case e in #( - e) - { printf "%s\n" "$as_me:${as_lineno-$LINENO}: Package 'gf180mcu_ws_klayout' will be installed automatically during make." >&5 -printf "%s\n" "$as_me: Package 'gf180mcu_ws_klayout' will be installed automatically during make." >&6;} - GF180MCU_WS_KLAYOUT_PATH=../sources/gf180mcu_ws_klayout - - ;; -esac -fi - - - - - - - - - - - - - # echo target targetvar flag location - GF180MCU_FD_IO_PATH="" # Check whether --enable-io-gf180mcu was given. @@ -4153,6 +4109,50 @@ # echo target targetvar flag location + GF180MCU_RE_EFUSE_PATH="" + + # Check whether --enable-re-efuse-gf180mcu was given. +if test ${enable_re_efuse_gf180mcu+y} +then : + enableval=$enable_re_efuse_gf180mcu; + if test "$enableval" == "yes" -o "$enableval" == "YES"; then + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: Package 'gf180mcu_re_efuse' will be installed automatically during make." >&5 +printf "%s\n" "$as_me: Package 'gf180mcu_re_efuse' will be installed automatically during make." >&6;} + export GF180MCU_RE_EFUSE_PATH=../sources/gf180mcu_re_efuse + elif test "$enableval" == "no" -o "$enableval" == "NO"; then + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: Disabling package 'gf180mcu_re_efuse'" >&5 +printf "%s\n" "$as_me: Disabling package 'gf180mcu_re_efuse'" >&6;} + export GF180MCU_RE_EFUSE_PATH="" + else + GF180MCU_RE_EFUSE_PATH=$enableval + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: Enabling package 'gf180mcu_re_efuse' at $GF180MCU_RE_EFUSE_PATH" >&5 +printf "%s\n" "$as_me: Enabling package 'gf180mcu_re_efuse' at $GF180MCU_RE_EFUSE_PATH" >&6;} + fi + GF180MCU_RE_EFUSE_PATH=`realpath $GF180MCU_RE_EFUSE_PATH` + +else case e in #( + e) + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: Package 'gf180mcu_re_efuse' will be installed automatically during make." >&5 +printf "%s\n" "$as_me: Package 'gf180mcu_re_efuse' will be installed automatically during make." >&6;} + GF180MCU_RE_EFUSE_PATH=../sources/gf180mcu_re_efuse + + ;; +esac +fi + + + + + + + + + + + + + # echo target targetvar flag location + GF180MCU_OCD_IO_PATH="" # Check whether --enable-ocd-io-gf180mcu was given.
diff --git a/scripts/configure.ac b/scripts/configure.ac index d5c11a9..5e87368 100755 --- a/scripts/configure.ac +++ b/scripts/configure.ac
@@ -255,7 +255,6 @@ # GlobalFoundries gf180mcu essential M4_GEN_INSTALLATION(gf180mcu_fd_pr, primitive-gf180mcu, ../sources) M4_GEN_INSTALLATION(gf180mcu_fd_pv, verification-gf180mcu, ../sources) -M4_GEN_INSTALLATION(gf180mcu_ws_klayout, klayout-gf180mcu, ../sources) M4_GEN_INSTALLATION(gf180mcu_fd_io, io-gf180mcu, ../sources) M4_GEN_INSTALLATION(gf180mcu_fd_sc_mcu7t5v0, sc-7t5v0-gf180mcu, ../sources) M4_GEN_INSTALLATION(gf180mcu_fd_sc_mcu9t5v0, sc-9t5v0-gf180mcu, ../sources) @@ -265,6 +264,7 @@ # GlobalFoundries gf180mcu optional M4_GEN_INSTALLATION(gf180mcu_osu_sc, osu-sc-gf180mcu, ../sources) M4_GEN_INSTALLATION(gf180mcu_as_sc, avalon-sc-gf180mcu, ../sources) +M4_GEN_INSTALLATION(gf180mcu_re_efuse, re-efuse-gf180mcu, ../sources) M4_GEN_INSTALLATION(gf180mcu_ocd_io, ocd-io-gf180mcu, ../sources) M4_GEN_INSTALLATION(gf180mcu_ocd_ip_sram, ocd-sram-gf180mcu, ../sources)