Fix `LEF` views of EF cells
* Correctly set the `CLASS` property to `CLASS CORE SPACER` instead of `CLASS BLOCK`
* Set missing `SYMMETRY` property to `X Y R90` to match `fd_sc_hd` fill cells
* Set missing `SITE` property to `unithd`
* Created missing `sky130_ef_sc_hd__fill_4.v`
* Remove `fakediode`: Maintaining it is no longer worth it
diff --git a/sky130/custom/sky130_fd_sc_hd/gds/sky130_ef_sc_hd__fakediode_2.gds b/sky130/custom/sky130_fd_sc_hd/gds/sky130_ef_sc_hd__fakediode_2.gds
deleted file mode 100644
index 1f7642f..0000000
--- a/sky130/custom/sky130_fd_sc_hd/gds/sky130_ef_sc_hd__fakediode_2.gds
+++ /dev/null
Binary files differ
diff --git a/sky130/custom/sky130_fd_sc_hd/lef/sky130_ef_sc_hd__decap_12.lef b/sky130/custom/sky130_fd_sc_hd/lef/sky130_ef_sc_hd__decap_12.lef
index 1667567..bb9215b 100644
--- a/sky130/custom/sky130_fd_sc_hd/lef/sky130_ef_sc_hd__decap_12.lef
+++ b/sky130/custom/sky130_fd_sc_hd/lef/sky130_ef_sc_hd__decap_12.lef
@@ -3,17 +3,12 @@
DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
MACRO sky130_ef_sc_hd__decap_12
- CLASS BLOCK ;
+ CLASS CORE SPACER ;
FOREIGN sky130_ef_sc_hd__decap_12 ;
ORIGIN 0.000 0.000 ;
SIZE 5.520 BY 2.720 ;
- PIN VGND
- USE GROUND ;
- PORT
- LAYER met1 ;
- RECT 0.000 -0.240 5.520 0.240 ;
- END
- END VGND
+ SYMMETRY X Y R90 ;
+ SITE unithd ;
PIN VPWR
USE POWER ;
PORT
@@ -21,6 +16,13 @@
RECT 0.000 2.480 5.520 2.960 ;
END
END VPWR
+ PIN VGND
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000 -0.240 5.520 0.240 ;
+ END
+ END VGND
PIN VPB
DIRECTION INOUT ;
USE POWER ;
diff --git a/sky130/custom/sky130_fd_sc_hd/lef/sky130_ef_sc_hd__fakediode_2.lef b/sky130/custom/sky130_fd_sc_hd/lef/sky130_ef_sc_hd__fakediode_2.lef
deleted file mode 100644
index 5639f2b..0000000
--- a/sky130/custom/sky130_fd_sc_hd/lef/sky130_ef_sc_hd__fakediode_2.lef
+++ /dev/null
@@ -1,59 +0,0 @@
-VERSION 5.7 ;
- NOWIREEXTENSIONATPIN ON ;
- DIVIDERCHAR "/" ;
- BUSBITCHARS "[]" ;
-MACRO sky130_ef_sc_hd__fakediode_2
- CLASS BLOCK ;
- FOREIGN sky130_ef_sc_hd__fakediode_2 ;
- ORIGIN 0.000 0.000 ;
- SIZE 0.920 BY 2.720 ;
- PIN DIODE
- PORT
- LAYER li1 ;
- RECT 0.085 0.255 0.835 2.465 ;
- END
- END DIODE
- PIN VGND
- USE GROUND ;
- PORT
- LAYER met1 ;
- RECT 0.000 -0.240 0.920 0.240 ;
- END
- END VGND
- PIN VPWR
- USE POWER ;
- PORT
- LAYER met1 ;
- RECT 0.000 2.480 0.920 2.960 ;
- END
- END VPWR
- PIN VPB
- DIRECTION INOUT ;
- USE POWER ;
- PORT
- LAYER nwell ;
- RECT -0.190 1.305 1.110 2.910 ;
- END
- END VPB
- PIN VNB
- DIRECTION INOUT ;
- USE GROUND ;
- PORT
- LAYER pwell ;
- RECT 0.025 0.065 0.915 1.015 ;
- RECT 0.145 -0.085 0.315 0.065 ;
- END
- END VNB
- OBS
- LAYER li1 ;
- RECT 0.000 2.635 0.920 2.805 ;
- RECT 0.000 -0.085 0.920 0.085 ;
- LAYER mcon ;
- RECT 0.145 2.635 0.315 2.805 ;
- RECT 0.605 2.635 0.775 2.805 ;
- RECT 0.145 -0.085 0.315 0.085 ;
- RECT 0.605 -0.085 0.775 0.085 ;
- END
-END sky130_ef_sc_hd__fakediode_2
-END LIBRARY
-
diff --git a/sky130/custom/sky130_fd_sc_hd/lef/sky130_ef_sc_hd__fill_12.lef b/sky130/custom/sky130_fd_sc_hd/lef/sky130_ef_sc_hd__fill_12.lef
index e96e434..e171847 100644
--- a/sky130/custom/sky130_fd_sc_hd/lef/sky130_ef_sc_hd__fill_12.lef
+++ b/sky130/custom/sky130_fd_sc_hd/lef/sky130_ef_sc_hd__fill_12.lef
@@ -3,10 +3,12 @@
DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
MACRO sky130_ef_sc_hd__fill_12
- CLASS BLOCK ;
+ CLASS CORE SPACER ;
FOREIGN sky130_ef_sc_hd__fill_12 ;
ORIGIN 0.000 0.000 ;
SIZE 5.520 BY 2.720 ;
+ SYMMETRY X Y R90 ;
+ SITE unithd ;
PIN VPWR
USE POWER ;
PORT
diff --git a/sky130/custom/sky130_fd_sc_hd/lef/sky130_ef_sc_hd__fill_4.lef b/sky130/custom/sky130_fd_sc_hd/lef/sky130_ef_sc_hd__fill_4.lef
index 7233a72..490d182 100644
--- a/sky130/custom/sky130_fd_sc_hd/lef/sky130_ef_sc_hd__fill_4.lef
+++ b/sky130/custom/sky130_fd_sc_hd/lef/sky130_ef_sc_hd__fill_4.lef
@@ -3,17 +3,12 @@
DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
MACRO sky130_ef_sc_hd__fill_4
- CLASS BLOCK ;
+ CLASS CORE SPACER ;
FOREIGN sky130_ef_sc_hd__fill_4 ;
ORIGIN 0.000 0.000 ;
SIZE 1.840 BY 2.720 ;
- PIN VGND
- USE GROUND ;
- PORT
- LAYER met1 ;
- RECT 0.000 -0.240 1.840 0.240 ;
- END
- END VGND
+ SYMMETRY X Y R90 ;
+ SITE unithd ;
PIN VPWR
USE POWER ;
PORT
@@ -21,6 +16,13 @@
RECT 0.000 2.480 1.840 2.960 ;
END
END VPWR
+ PIN VGND
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000 -0.240 1.840 0.240 ;
+ END
+ END VGND
PIN VPB
DIRECTION INOUT ;
USE POWER ;
diff --git a/sky130/custom/sky130_fd_sc_hd/lef/sky130_ef_sc_hd__fill_8.lef b/sky130/custom/sky130_fd_sc_hd/lef/sky130_ef_sc_hd__fill_8.lef
index 7ab7413..d3d95f4 100644
--- a/sky130/custom/sky130_fd_sc_hd/lef/sky130_ef_sc_hd__fill_8.lef
+++ b/sky130/custom/sky130_fd_sc_hd/lef/sky130_ef_sc_hd__fill_8.lef
@@ -3,17 +3,12 @@
DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
MACRO sky130_ef_sc_hd__fill_8
- CLASS BLOCK ;
+ CLASS CORE SPACER ;
FOREIGN sky130_ef_sc_hd__fill_8 ;
ORIGIN 0.000 0.000 ;
SIZE 3.680 BY 2.720 ;
- PIN VGND
- USE GROUND ;
- PORT
- LAYER met1 ;
- RECT 0.000 -0.240 3.680 0.240 ;
- END
- END VGND
+ SYMMETRY X Y R90 ;
+ SITE unithd ;
PIN VPWR
USE POWER ;
PORT
@@ -21,6 +16,13 @@
RECT 0.000 2.480 3.680 2.960 ;
END
END VPWR
+ PIN VGND
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000 -0.240 3.680 0.240 ;
+ END
+ END VGND
PIN VPB
DIRECTION INOUT ;
USE POWER ;
diff --git a/sky130/custom/sky130_fd_sc_hd/verilog/sky130_ef_sc_hd__fakediode_2.v b/sky130/custom/sky130_fd_sc_hd/verilog/sky130_ef_sc_hd__fakediode_2.v
deleted file mode 100644
index f510454..0000000
--- a/sky130/custom/sky130_fd_sc_hd/verilog/sky130_ef_sc_hd__fakediode_2.v
+++ /dev/null
@@ -1,87 +0,0 @@
-/**
- * Copyright 2020 The SkyWater PDK Authors
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * https://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-`ifndef SKY130_EF_SC_HD__FAKEDIODE_2_V
-`define SKY130_EF_SC_HD__FAKEDIODE_2_V
-
-/**
- * fakediode: Antenna tie-down diode with no connection between the DIODE
- * pin and the diode. This is just the sky130_fd_sc_hd__diode_2 cell with
- * the contacts removed between the diode and the pin. It is used by the
- * openlane synthesis flow to preemptively put antenna tie-downs close to
- * every pin without making a connection. If the net needs an antenna
- * tiedown, the fakediode cell can be replaced by the real diode cell.
- *
- * Verilog wrapper for diode with size of 2 units. Because the diode
- * has no function in verilog, there is no difference between the verilog
- * definitions of the diode and fake diode other than the cell name.
- *
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_ef_sc_hd__fakediode_2 (
- DIODE,
- VPWR ,
- VGND ,
- VPB ,
- VNB
-);
-
- // Module ports
- input DIODE;
- input VPWR ;
- input VGND ;
- input VPB ;
- input VNB ;
- // No contents.
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_ef_sc_hd__fakediode_2 (
- DIODE
-);
-
- // Module ports
- input DIODE;
-
- // Voltage supply signals
- supply1 VPWR;
- supply0 VGND;
- supply1 VPB ;
- supply0 VNB ;
- // No contents.
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif // SKY130_EF_SC_HD__FAKEDIODE_2_V
diff --git a/sky130/custom/sky130_fd_sc_hd/verilog/sky130_ef_sc_hd__fill_4.v b/sky130/custom/sky130_fd_sc_hd/verilog/sky130_ef_sc_hd__fill_4.v
new file mode 100644
index 0000000..e66b3e5
--- /dev/null
+++ b/sky130/custom/sky130_fd_sc_hd/verilog/sky130_ef_sc_hd__fill_4.v
@@ -0,0 +1,73 @@
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_EF_SC_HD__FILL_4_V
+`define SKY130_EF_SC_HD__FILL_4_V
+
+/**
+ * fill: Fill cell.
+ *
+ * Verilog wrapper for fill with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_ef_sc_hd__fill_4 (
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ // No contents.
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_ef_sc_hd__fill_4 ();
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+ // No contents.
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_EF_SC_HD__FILL_4_V
