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foss-eda-tools/third_party/opencircuitdesign.com/open_pdks/113790763459c342915a52c1852849e935f7eb63^!/.
commit
113790763459c342915a52c1852849e935f7eb63
[log]
author
Iztok Jeras <iztok.jeras@gmail.com>
Tue May 19 02:25:14 2026 +0200
committer
R. Timothy Edwards <tim@opencircuitdesign.com>
Thu May 28 13:49:47 2026 -0400
tree
f77e464117fb743b29d87ea29a334690d8bbf41b
parent
dedd0014ffc585d9fb6c1a237ff79ab0249e8e4b [diff]
sky130: consolidating (minimizing differences) config.tcl files by using the STD_CELL_LIBRARY variable to construct cell names, no functional change

diff --git a/sky130/librelane/sky130_fd_sc_hd/config.tcl b/sky130/librelane/sky130_fd_sc_hd/config.tcl
index ea952d9..6954ed1 100755
--- a/sky130/librelane/sky130_fd_sc_hd/config.tcl
+++ b/sky130/librelane/sky130_fd_sc_hd/config.tcl

@@ -12,38 +12,40 @@
 set ::env(PLACE_SITE) "unithd"
 
 # welltap and endcap cells
-set ::env(WELLTAP_CELL) "sky130_fd_sc_hd__tapvpwrvgnd_1"
-set ::env(ENDCAP_CELL) "sky130_fd_sc_hd__decap_3"
+set ::env(WELLTAP_CELL) "$::env(STD_CELL_LIBRARY)__tapvpwrvgnd_1"
+set ::env(ENDCAP_CELL) "$::env(STD_CELL_LIBRARY)__decap_3"
 
 # defaults (can be overridden by designs):
-set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hd__inv_2/Y"
+set ::env(SYNTH_DRIVING_CELL) "$::env(STD_CELL_LIBRARY)__inv_2/Y"
 #capacitance : 0.017653;
-#set ::env(SYNTH_CLK_DRIVING_CELL) "sky130_fd_sc_hd__clkinv_2/Y"
+#set ::env(SYNTH_CLK_DRIVING_CELL) "$::env(STD_CELL_LIBRARY)__clkinv_2/Y"
 # update these
 set ::env(OUTPUT_CAP_LOAD) "33.442" ; # femtofarad __inv_16 pin A cap (https://github.com/google/skywater-pdk-libs-sky130_fd_sc_hd/blob/main/cells/inv/sky130_fd_sc_hd__inv_16__tt_025C_1v80.lib.json)
-set ::env(SYNTH_BUFFER_CELL) "sky130_fd_sc_hd__buf_2/A/X"
-set ::env(SYNTH_TIEHI_CELL) "sky130_fd_sc_hd__conb_1/HI"
-set ::env(SYNTH_TIELO_CELL) "sky130_fd_sc_hd__conb_1/LO"
+set ::env(SYNTH_BUFFER_CELL) "$::env(STD_CELL_LIBRARY)__buf_2/A/X"
+set ::env(SYNTH_TIEHI_CELL) "$::env(STD_CELL_LIBRARY)__conb_1/HI"
+set ::env(SYNTH_TIELO_CELL) "$::env(STD_CELL_LIBRARY)__conb_1/LO"
 
 # cts defaults
-set ::env(CTS_ROOT_BUFFER) sky130_fd_sc_hd__clkbuf_16
+set ::env(CTS_ROOT_BUFFER) "$::env(STD_CELL_LIBRARY)__clkbuf_16"
 
 # fill/decap cell insertion
-set ::env(FILL_CELLS) "sky130_fd_sc_hd__fill_2 sky130_fd_sc_hd__fill_1"
-set ::env(DECAP_CELLS) "sky130_fd_sc_hd__decap_3"
+set ::env(FILL_CELLS) "$::env(STD_CELL_LIBRARY)__fill_2 $::env(STD_CELL_LIBRARY)__fill_1"
+set ::env(DECAP_CELLS) "$::env(STD_CELL_LIBRARY)__decap_3"
 
 # diode insertion
-set ::env(DIODE_CELL) "sky130_fd_sc_hd__diode_2/DIODE"
+set ::env(DIODE_CELL) "$::env(STD_CELL_LIBRARY)__diode_2/DIODE"
 
 set ::env(GPL_CELL_PADDING) {0}
 set ::env(DPL_CELL_PADDING) {0}
-set ::env(CELL_PAD_EXCLUDE) "sky130_fd_sc_hd__tap* sky130_fd_sc_hd__decap* sky130_ef_sc_hd__decap* sky130_fd_sc_hd__fill*"
+set ::env(CELL_PAD_EXCLUDE) "$::env(STD_CELL_LIBRARY)__tap* $::env(STD_CELL_LIBRARY)__decap* $::env(STD_CELL_LIBRARY)__fill*"
 
 # Clk Buffers info CTS data
-set ::env(CTS_CLK_BUFFERS) "sky130_fd_sc_hd__clkbuf_8 sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_2"
-set ::env(PDN_RAIL_WIDTH) 0.48
+set ::env(CTS_CLK_BUFFERS) "$::env(STD_CELL_LIBRARY)__clkbuf_8 $::env(STD_CELL_LIBRARY)__clkbuf_4 $::env(STD_CELL_LIBRARY)__clkbuf_2"
+
 set ::env(MAX_TRANSITION_CONSTRAINT) 0.75
 set ::env(MAX_FANOUT_CONSTRAINT) 10
 set ::env(MAX_CAPACITANCE_CONSTRAINT) 0.2
 
+set ::env(PDN_RAIL_WIDTH) 0.48
+
 set ::env(TRISTATE_CELLS) "$::env(STD_CELL_LIBRARY)__ebuf*"

diff --git a/sky130/librelane/sky130_fd_sc_hdll/config.tcl b/sky130/librelane/sky130_fd_sc_hdll/config.tcl
index a942745..94d6a69 100755
--- a/sky130/librelane/sky130_fd_sc_hdll/config.tcl
+++ b/sky130/librelane/sky130_fd_sc_hdll/config.tcl

@@ -9,38 +9,40 @@
 set ::env(PLACE_SITE) "unithd"
 
 # welltap and endcap cells
-set ::env(WELLTAP_CELL) "sky130_fd_sc_hdll__tapvpwrvgnd_1"
-set ::env(ENDCAP_CELL) "sky130_fd_sc_hdll__decap_3"
+set ::env(WELLTAP_CELL) "$::env(STD_CELL_LIBRARY)__tapvpwrvgnd_1"
+set ::env(ENDCAP_CELL) "$::env(STD_CELL_LIBRARY)__decap_3"
 
 # defaults (can be overridden by designs):
-set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hdll__inv_2/Y"
+set ::env(SYNTH_DRIVING_CELL) "$::env(STD_CELL_LIBRARY)__inv_2/Y"
 #capacitance : 0.017653;
-#set ::env(SYNTH_CLK_DRIVING_CELL) "sky130_fd_sc_hdll__clkinv_2/Y"
+#set ::env(SYNTH_CLK_DRIVING_CELL) "$::env(STD_CELL_LIBRARY)__clkinv_2/Y"
 # update these
 set ::env(OUTPUT_CAP_LOAD) "33.468" ; # femtofarad _inv_16 pin A cap (https://github.com/google/skywater-pdk-libs-sky130_fd_sc_hdll/blob/main/cells/inv/sky130_fd_sc_hdll__inv_16__tt_025C_1v80.lib.json)
-set ::env(SYNTH_BUFFER_CELL) "sky130_fd_sc_hdll__buf_2/A/X"
-set ::env(SYNTH_TIEHI_CELL) "sky130_fd_sc_hdll__conb_1/HI"
-set ::env(SYNTH_TIELO_CELL) "sky130_fd_sc_hdll__conb_1/LO"
+set ::env(SYNTH_BUFFER_CELL) "$::env(STD_CELL_LIBRARY)__buf_2/A/X"
+set ::env(SYNTH_TIEHI_CELL) "$::env(STD_CELL_LIBRARY)__conb_1/HI"
+set ::env(SYNTH_TIELO_CELL) "$::env(STD_CELL_LIBRARY)__conb_1/LO"
 
 # cts defaults
-set ::env(CTS_ROOT_BUFFER) sky130_fd_sc_hdll__clkbuf_16
+set ::env(CTS_ROOT_BUFFER) "$::env(STD_CELL_LIBRARY)__clkbuf_16"
 
 # fill/decap cell insertion
-set ::env(FILL_CELLS) "sky130_fd_sc_hdll__fill*"
-set ::env(DECAP_CELLS) "sky130_fd_sc_hdll__decap*"
+set ::env(FILL_CELLS) "$::env(STD_CELL_LIBRARY)__fill*"
+set ::env(DECAP_CELLS) "$::env(STD_CELL_LIBRARY)__decap*"
 
 # diode insertion
-set ::env(DIODE_CELL) "sky130_fd_sc_hdll__diode_2/DIODE"
+set ::env(DIODE_CELL) "$::env(STD_CELL_LIBRARY)__diode_2/DIODE"
 
 set ::env(GPL_CELL_PADDING) {0}
 set ::env(DPL_CELL_PADDING) {0}
 set ::env(CELL_PAD_EXCLUDE) "$::env(STD_CELL_LIBRARY)__tap* $::env(STD_CELL_LIBRARY)__decap* $::env(STD_CELL_LIBRARY)__fill*"
 
 # Clk Buffers info CTS data
-set ::env(CTS_CLK_BUFFERS) "sky130_fd_sc_hdll__clkbuf_8 sky130_fd_sc_hdll__clkbuf_4 sky130_fd_sc_hdll__clkbuf_2"
-set ::env(PDN_RAIL_WIDTH) 0.48
+set ::env(CTS_CLK_BUFFERS) "$::env(STD_CELL_LIBRARY)__clkbuf_8 $::env(STD_CELL_LIBRARY)__clkbuf_4 $::env(STD_CELL_LIBRARY)__clkbuf_2"
+
 set ::env(MAX_TRANSITION_CONSTRAINT) 0.75
 set ::env(MAX_FANOUT_CONSTRAINT) 10
 set ::env(MAX_CAPACITANCE_CONSTRAINT) 0.2
 
+set ::env(PDN_RAIL_WIDTH) 0.48
+
 set ::env(TRISTATE_CELLS) "$::env(STD_CELL_LIBRARY)__ebuf*"

diff --git a/sky130/librelane/sky130_fd_sc_hs/config.tcl b/sky130/librelane/sky130_fd_sc_hs/config.tcl
index d90d6f1..f4df1cd 100755
--- a/sky130/librelane/sky130_fd_sc_hs/config.tcl
+++ b/sky130/librelane/sky130_fd_sc_hs/config.tcl

@@ -12,37 +12,40 @@
 set ::env(PLACE_SITE) "unit"
 
 # welltap and endcap cells
-set ::env(WELLTAP_CELL) "sky130_fd_sc_hs__tapvpwrvgnd_1"
-set ::env(ENDCAP_CELL) "sky130_fd_sc_hs__decap_4"
+set ::env(WELLTAP_CELL) "$::env(STD_CELL_LIBRARY)__tapvpwrvgnd_1"
+set ::env(ENDCAP_CELL) "$::env(STD_CELL_LIBRARY)__decap_4"
 
 # defaults (can be overridden by designs):
-set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hs__inv_2/Y"
+set ::env(SYNTH_DRIVING_CELL) "$::env(STD_CELL_LIBRARY)__inv_2/Y"
 #capacitance : 0.02104;
-#set ::env(SYNTH_CLK_DRIVING_CELL) "sky130_fd_sc_hs__clkinv_2/Y"
+#set ::env(SYNTH_CLK_DRIVING_CELL) "$::env(STD_CELL_LIBRARY)__clkinv_2/Y"
 # update these
 set ::env(OUTPUT_CAP_LOAD) "43.39" ; # femtofarad _inv_16 pin A cap (https://github.com/google/skywater-pdk-libs-sky130_fd_sc_hs/blob/main/cells/inv/sky130_fd_sc_hs__inv_16__tt_025C_1v68.lib.json)
-set ::env(SYNTH_BUFFER_CELL) "sky130_fd_sc_hs__buf_2/A/X"
-set ::env(SYNTH_TIEHI_CELL) "sky130_fd_sc_hs__conb_1/HI"
-set ::env(SYNTH_TIELO_CELL) "sky130_fd_sc_hs__conb_1/LO"
+set ::env(SYNTH_BUFFER_CELL) "$::env(STD_CELL_LIBRARY)__buf_2/A/X"
+set ::env(SYNTH_TIEHI_CELL) "$::env(STD_CELL_LIBRARY)__conb_1/HI"
+set ::env(SYNTH_TIELO_CELL) "$::env(STD_CELL_LIBRARY)__conb_1/LO"
 
 # cts defaults
-set ::env(CTS_ROOT_BUFFER) sky130_fd_sc_hs__clkbuf_16
+set ::env(CTS_ROOT_BUFFER) "$::env(STD_CELL_LIBRARY)__clkbuf_16"
 
 # fill/decap cell insertion
-set ::env(FILL_CELLS) "sky130_fd_sc_hs__fill*"
-set ::env(DECAP_CELLS) "sky130_fd_sc_hs__decap_4"
+set ::env(FILL_CELLS) "$::env(STD_CELL_LIBRARY)__fill*"
+set ::env(DECAP_CELLS) "$::env(STD_CELL_LIBRARY)__decap_4"
 
 # diode insertion
-set ::env(DIODE_CELL) "sky130_fd_sc_hs__diode_2/DIODE"
+set ::env(DIODE_CELL) "$::env(STD_CELL_LIBRARY)__diode_2/DIODE"
 
 set ::env(GPL_CELL_PADDING) {0}
 set ::env(DPL_CELL_PADDING) {0}
-set ::env(CELL_PAD_EXCLUDE) "sky130_fd_sc_hs__tap* sky130_fd_sc_hs__decap* sky130_fd_sc_hs__fill*"
+set ::env(CELL_PAD_EXCLUDE) "$::env(STD_CELL_LIBRARY)__tap* $::env(STD_CELL_LIBRARY)__decap* $::env(STD_CELL_LIBRARY)__fill*"
 
-set ::env(CTS_CLK_BUFFERS) "sky130_fd_sc_hs__clkbuf_8 sky130_fd_sc_hs__clkbuf_4 sky130_fd_sc_hs__clkbuf_2"
+# Clk Buffers info CTS data
+set ::env(CTS_CLK_BUFFERS) "$::env(STD_CELL_LIBRARY)__clkbuf_8 $::env(STD_CELL_LIBRARY)__clkbuf_4 $::env(STD_CELL_LIBRARY)__clkbuf_2"
+
 set ::env(MAX_TRANSITION_CONSTRAINT) 0.75
 set ::env(MAX_FANOUT_CONSTRAINT) 10
 set ::env(MAX_CAPACITANCE_CONSTRAINT) 0.2
+
 set ::env(PDN_RAIL_WIDTH) 0.48
 
 set ::env(TRISTATE_CELLS) "$::env(STD_CELL_LIBRARY)__ebuf*"

diff --git a/sky130/librelane/sky130_fd_sc_hvl/config.tcl b/sky130/librelane/sky130_fd_sc_hvl/config.tcl
index 346ecd0..7f30176 100644
--- a/sky130/librelane/sky130_fd_sc_hvl/config.tcl
+++ b/sky130/librelane/sky130_fd_sc_hvl/config.tcl

@@ -39,34 +39,36 @@
 
 # welltap and endcap cells
 #set ::env(WELLTAP_CELL) ""
-set ::env(ENDCAP_CELL) "sky130_fd_sc_hvl__decap_4"
+set ::env(ENDCAP_CELL) "$::env(STD_CELL_LIBRARY)__decap_4"
 
 # defaults (can be overridden by designs):
-set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hvl__inv_2/Y"
+set ::env(SYNTH_DRIVING_CELL) "$::env(STD_CELL_LIBRARY)__inv_2/Y"
 #capacitance : 0.017653;
 # update these
 set ::env(OUTPUT_CAP_LOAD) "70.77" ; # femtofarad __inv_16 pin A cap (https://github.com/google/skywater-pdk-libs-sky130_fd_sc_hvl/blob/main/cells/inv/sky130_fd_sc_hvl__inv_16__tt_025C_3v30.lib.json)
-set ::env(SYNTH_BUFFER_CELL) "sky130_fd_sc_hvl__buf_1/A/X"
-set ::env(SYNTH_TIEHI_CELL) "sky130_fd_sc_hvl__conb_1/HI"
-set ::env(SYNTH_TIELO_CELL) "sky130_fd_sc_hvl__conb_1/LO"
+set ::env(SYNTH_BUFFER_CELL) "$::env(STD_CELL_LIBRARY)__buf_1/A/X"
+set ::env(SYNTH_TIEHI_CELL) "$::env(STD_CELL_LIBRARY)__conb_1/HI"
+set ::env(SYNTH_TIELO_CELL) "$::env(STD_CELL_LIBRARY)__conb_1/LO"
 
 # cts defaults
-set ::env(CTS_ROOT_BUFFER) sky130_fd_sc_hvl__buf_16
+set ::env(CTS_ROOT_BUFFER) "$::env(STD_CELL_LIBRARY)__buf_16"
 
 # fill/decap cell insertion
-set ::env(FILL_CELLS) "sky130_fd_sc_hvl__fill*"
-set ::env(DECAP_CELLS) "sky130_fd_sc_hvl__decap*"
+set ::env(FILL_CELLS) "$::env(STD_CELL_LIBRARY)__fill*"
+set ::env(DECAP_CELLS) "$::env(STD_CELL_LIBRARY)__decap*"
 
 # diode insertion
-set ::env(DIODE_CELL) "sky130_fd_sc_hvl__diode_2/DIODE"
+set ::env(DIODE_CELL) "$::env(STD_CELL_LIBRARY)__diode_2/DIODE"
 
 set ::env(GPL_CELL_PADDING) {0}
 set ::env(DPL_CELL_PADDING) {0}
-set ::env(CELL_PAD_EXCLUDE) "sky130_fd_sc_hvl__tap* sky130_fd_sc_hvl__decap* sky130_fd_sc_hvl__fill*"
+set ::env(CELL_PAD_EXCLUDE) "$::env(STD_CELL_LIBRARY)__tap* $::env(STD_CELL_LIBRARY)__decap* $::env(STD_CELL_LIBRARY)__fill*"
 
 # Clk Buffers info CTS data
-set ::env(CTS_CLK_BUFFERS) "sky130_fd_sc_hvl__buf_8 sky130_fd_sc_hvl__buf_4 sky130_fd_sc_hvl__buf_2"
+set ::env(CTS_CLK_BUFFERS) "$::env(STD_CELL_LIBRARY)__buf_8 $::env(STD_CELL_LIBRARY)__buf_4 $::env(STD_CELL_LIBRARY)__buf_2"
+
 set ::env(MAX_TRANSITION_CONSTRAINT) 0.75
 set ::env(MAX_FANOUT_CONSTRAINT) 10
 set ::env(MAX_CAPACITANCE_CONSTRAINT) 0.2
+
 set ::env(PDN_RAIL_WIDTH) 0.51

diff --git a/sky130/librelane/sky130_fd_sc_ls/config.tcl b/sky130/librelane/sky130_fd_sc_ls/config.tcl
index d175b7f..8a9036e 100755
--- a/sky130/librelane/sky130_fd_sc_ls/config.tcl
+++ b/sky130/librelane/sky130_fd_sc_ls/config.tcl

@@ -12,38 +12,40 @@
 set ::env(PLACE_SITE) "unit"
 
 # welltap and endcap cells
-set ::env(WELLTAP_CELL) "sky130_fd_sc_ls__tapvpwrvgnd_1"
-set ::env(ENDCAP_CELL) "sky130_fd_sc_ls__decap_4"
+set ::env(WELLTAP_CELL) "$::env(STD_CELL_LIBRARY)__tapvpwrvgnd_1"
+set ::env(ENDCAP_CELL) "$::env(STD_CELL_LIBRARY)__decap_4"
 
 # defaults (can be overridden by designs):
-set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_ls__inv_2/Y"
+set ::env(SYNTH_DRIVING_CELL) "$::env(STD_CELL_LIBRARY)__inv_2/Y"
 #capacitance : 0.017653;
-#set ::env(SYNTH_CLK_DRIVING_CELL) "sky130_fd_sc_ls__clkinv_2/Y"
+#set ::env(SYNTH_CLK_DRIVING_CELL) "$::env(STD_CELL_LIBRARY)__clkinv_2/Y"
 # update these
 set ::env(OUTPUT_CAP_LOAD) "46.690" ; # femtofarad _inv_16 pin A cap (https://github.com/google/skywater-pdk-libs-sky130_fd_sc_ls/blob/main/cells/inv/sky130_fd_sc_ls__inv_16__tt_100C_1v80.lib.json)
-set ::env(SYNTH_BUFFER_CELL) "sky130_fd_sc_ls__buf_2/A/X"
-set ::env(SYNTH_TIEHI_CELL) "sky130_fd_sc_ls__conb_1/HI"
-set ::env(SYNTH_TIELO_CELL) "sky130_fd_sc_ls__conb_1/LO"
+set ::env(SYNTH_BUFFER_CELL) "$::env(STD_CELL_LIBRARY)__buf_2/A/X"
+set ::env(SYNTH_TIEHI_CELL) "$::env(STD_CELL_LIBRARY)__conb_1/HI"
+set ::env(SYNTH_TIELO_CELL) "$::env(STD_CELL_LIBRARY)__conb_1/LO"
 
 # cts defaults
-set ::env(CTS_ROOT_BUFFER) sky130_fd_sc_ls__clkbuf_16
+set ::env(CTS_ROOT_BUFFER) "$::env(STD_CELL_LIBRARY)__clkbuf_16"
 
 # fill/decap cell insertion
-set ::env(FILL_CELLS) "sky130_fd_sc_ls__fill*"
-set ::env(DECAP_CELLS) "sky130_fd_sc_ls__decap*"
+set ::env(FILL_CELLS) "$::env(STD_CELL_LIBRARY)__fill*"
+set ::env(DECAP_CELLS) "$::env(STD_CELL_LIBRARY)__decap*"
 
 # diode insertion
-set ::env(DIODE_CELL) "sky130_fd_sc_ls__diode_2/DIODE"
+set ::env(DIODE_CELL) "$::env(STD_CELL_LIBRARY)__diode_2/DIODE"
 
 set ::env(GPL_CELL_PADDING) {0}
 set ::env(DPL_CELL_PADDING) {0}
 set ::env(CELL_PAD_EXCLUDE) "$::env(STD_CELL_LIBRARY)__tap* $::env(STD_CELL_LIBRARY)__decap* $::env(STD_CELL_LIBRARY)__fill*"
 
 # Clk Buffers info CTS data
-set ::env(CTS_CLK_BUFFERS) "sky130_fd_sc_ls__clkbuf_8 sky130_fd_sc_ls__clkbuf_4 sky130_fd_sc_ls__clkbuf_2"
+set ::env(CTS_CLK_BUFFERS) "$::env(STD_CELL_LIBRARY)__clkbuf_8 $::env(STD_CELL_LIBRARY)__clkbuf_4 $::env(STD_CELL_LIBRARY)__clkbuf_2"
+
 set ::env(MAX_TRANSITION_CONSTRAINT) 0.75
 set ::env(MAX_FANOUT_CONSTRAINT) 10
 set ::env(MAX_CAPACITANCE_CONSTRAINT) 0.2
+
 set ::env(PDN_RAIL_WIDTH) 0.48
 
 set ::env(TRISTATE_CELLS) "$::env(STD_CELL_LIBRARY)__ebuf*"

diff --git a/sky130/librelane/sky130_fd_sc_ms/config.tcl b/sky130/librelane/sky130_fd_sc_ms/config.tcl
index 65d9cfe..c8abca4 100755
--- a/sky130/librelane/sky130_fd_sc_ms/config.tcl
+++ b/sky130/librelane/sky130_fd_sc_ms/config.tcl

@@ -12,38 +12,40 @@
 set ::env(PLACE_SITE) "unit"
 
 # welltap and endcap cells
-set ::env(WELLTAP_CELL) "sky130_fd_sc_ms__tapvpwrvgnd_1"
-set ::env(ENDCAP_CELL) "sky130_fd_sc_ms__decap_4"
+set ::env(WELLTAP_CELL) "$::env(STD_CELL_LIBRARY)__tapvpwrvgnd_1"
+set ::env(ENDCAP_CELL) "$::env(STD_CELL_LIBRARY)__decap_4"
 
 # defaults (can be overridden by designs):
-set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_ms__inv_2/Y"
+set ::env(SYNTH_DRIVING_CELL) "$::env(STD_CELL_LIBRARY)__inv_2/Y"
 #capacitance : 0.017653;
-#set ::env(SYNTH_CLK_DRIVING_CELL) "sky130_fd_sc_ms__clkinv_2/Y"
+#set ::env(SYNTH_CLK_DRIVING_CELL) "$::env(STD_CELL_LIBRARY)__clkinv_2/Y"
 # update these
 set ::env(OUTPUT_CAP_LOAD) "22.66" ; # femtofarad _inv_8 pin A cap
-set ::env(SYNTH_BUFFER_CELL) "sky130_fd_sc_ms__buf_2/A/X"
-set ::env(SYNTH_TIEHI_CELL) "sky130_fd_sc_ms__conb_1/HI"
-set ::env(SYNTH_TIELO_CELL) "sky130_fd_sc_ms__conb_1/LO"
+set ::env(SYNTH_BUFFER_CELL) "$::env(STD_CELL_LIBRARY)__buf_2/A/X"
+set ::env(SYNTH_TIEHI_CELL) "$::env(STD_CELL_LIBRARY)__conb_1/HI"
+set ::env(SYNTH_TIELO_CELL) "$::env(STD_CELL_LIBRARY)__conb_1/LO"
 
 # cts defaults
-set ::env(CTS_ROOT_BUFFER) sky130_fd_sc_ms__clkbuf_16
+set ::env(CTS_ROOT_BUFFER) "$::env(STD_CELL_LIBRARY)__clkbuf_16"
 
 # fill/decap cell insertion
-set ::env(FILL_CELLS) "sky130_fd_sc_ms__fill*"
-set ::env(DECAP_CELLS) "sky130_fd_sc_ms__decap_4"
+set ::env(FILL_CELLS) "$::env(STD_CELL_LIBRARY)__fill*"
+set ::env(DECAP_CELLS) "$::env(STD_CELL_LIBRARY)__decap_4"
 
 # diode insertion
-set ::env(DIODE_CELL) "sky130_fd_sc_ms__diode_2/DIODE"
+set ::env(DIODE_CELL) "$::env(STD_CELL_LIBRARY)__diode_2/DIODE"
 
 set ::env(GPL_CELL_PADDING) {0}
 set ::env(DPL_CELL_PADDING) {0}
 set ::env(CELL_PAD_EXCLUDE) "$::env(STD_CELL_LIBRARY)__tap* $::env(STD_CELL_LIBRARY)__decap* $::env(STD_CELL_LIBRARY)__fill*"
 
 # Clk Buffers info CTS data
-set ::env(CTS_CLK_BUFFERS) "sky130_fd_sc_ms__clkbuf_8 sky130_fd_sc_ms__clkbuf_4 sky130_fd_sc_ms__clkbuf_2"
+set ::env(CTS_CLK_BUFFERS) "$::env(STD_CELL_LIBRARY)__clkbuf_8 $::env(STD_CELL_LIBRARY)__clkbuf_4 $::env(STD_CELL_LIBRARY)__clkbuf_2"
+
 set ::env(MAX_TRANSITION_CONSTRAINT) 0.75
 set ::env(MAX_FANOUT_CONSTRAINT) 10
 set ::env(MAX_CAPACITANCE_CONSTRAINT) 0.2
+
 set ::env(PDN_RAIL_WIDTH) 0.48
 
 set ::env(TRISTATE_CELLS) "$::env(STD_CELL_LIBRARY)__ebuf*"