Low_Power/Back_End/virtuoso/LowPowerOpenCellLibrary/LS_HL_X1/functional/verilog.v

// Created by ihdl
module LS_HL_X1 (A, Z);
  input A;
  output Z;

  buf(Z, A);

  specify
    (A => Z) = (0.1, 0.1);
  endspecify

endmodule