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foss-eda-tools
/
third_party
/
freepdk45
/
954b16e2fcd52994e9d3c8b5af35b5f91d261889
/
.
/
Low_Power
/
Back_End
/
virtuoso
/
LowPowerOpenCellLibrary
/
ISO_FENCE0_X4
/
functional
/
verilog.v
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// Created by ihdl
module
ISO_FENCE0_X4
(
A
,
EN
,
Z
);
input A
;
input EN
;
output Z
;
not
(
Z
,
i_4
);
or
(
i_4
,
A
,
EN
);
specify
(
A
=>
Z
)
=
(
0.1
,
0.1
);
(
EN
=>
Z
)
=
(
0.1
,
0.1
);
endspecify
endmodule