Low_Power/Back_End/virtuoso/LowPowerOpenCellLibrary/HEADER_OE_X1/functional/verilog.v

// Created by ihdl
module HEADER_OE_X1 (SLEEP, SLEEPOUT);
  input SLEEP;
  output SLEEPOUT;

  buf(SLEEPOUT, SLEEP);

  specify
    (SLEEP => SLEEPOUT) = (0.1, 0.1);
  endspecify

endmodule