| * |
| * ****************************************************************************** |
| * * * |
| * * Copyright (C) 2004-2010, Nangate Inc. * |
| * * All rights reserved. * |
| * * * |
| * * Nangate and the Nangate logo are trademarks of Nangate Inc. * |
| * * * |
| * * All trademarks, logos, software marks, and trade names (collectively the * |
| * * "Marks") in this program are proprietary to Nangate or other respective * |
| * * owners that have granted Nangate the right and license to use such Marks. * |
| * * You are not permitted to use the Marks without the prior written consent * |
| * * of Nangate or such third party that may own the Marks. * |
| * * * |
| * * This file has been provided pursuant to a License Agreement containing * |
| * * restrictions on its use. This file contains valuable trade secrets and * |
| * * proprietary information of Nangate Inc., and is protected by U.S. and * |
| * * international laws and/or treaties. * |
| * * * |
| * * The copyright notice(s) in this file does not indicate actual or intended * |
| * * publication of this file. * |
| * * * |
| * * buildcell, v2010.08-HR32-SP3-2010-08-05 - build 1009061800 * |
| * * * |
| * ****************************************************************************** |
| * |
| * |
| * Running on brazil06.nangate.com.br for user Giancarlo Franciscatto (gfr). |
| * Local time is now Fri, 3 Dec 2010, 19:19:07. |
| * Main process id is 28033. |
| * |
| ******************************************************************************** |
| * * |
| * Cellname: XOR2_X2. * |
| * * |
| * Technology: NCSU FreePDK 45nm. * |
| * Format: Cdl. * |
| * * |
| * Written on brazil06.nangate.com.br for user Giancarlo Franciscatto (gfr) * |
| * at 19:19:07 on Fri, 3 Dec 2010. * |
| * * |
| ******************************************************************************** |
| .SUBCKT XOR2_X2 A B Z VDD VSS |
| *.PININFO A:I B:I Z:O VDD:P VSS:G |
| *.EQN Z=(A ^ B) |
| M_i_0 net_000 A VSS VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_7 VSS B net_000 VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_13 Z net_000 VSS VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_19 net_001 A Z VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_24 VSS B net_001 VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_24_4 VSS B net_001b VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_19_23 net_001b A Z VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_13_35 Z net_000 VSS VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_30 net_002 A net_000 VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_35 VDD B net_002 VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_41 net_003 net_000 VDD VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_47 Z A net_003 VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_53 net_003 B Z VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_53_18 net_003 B Z VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_47_27 Z A net_003 VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_41_29 net_003 net_000 VDD VDD PMOS_VTL W=0.630000U L=0.050000U |
| .ENDS |
| |
| ******************************************************************************** |
| * |
| * END |
| * |
| ******************************************************************************** |
