blob: f9a9e3259099165052aec781edbf378fafe40ac1 [file] [log] [blame]
*
* ******************************************************************************
* * *
* * Copyright (C) 2004-2010, Nangate Inc. *
* * All rights reserved. *
* * *
* * Nangate and the Nangate logo are trademarks of Nangate Inc. *
* * *
* * All trademarks, logos, software marks, and trade names (collectively the *
* * "Marks") in this program are proprietary to Nangate or other respective *
* * owners that have granted Nangate the right and license to use such Marks. *
* * You are not permitted to use the Marks without the prior written consent *
* * of Nangate or such third party that may own the Marks. *
* * *
* * This file has been provided pursuant to a License Agreement containing *
* * restrictions on its use. This file contains valuable trade secrets and *
* * proprietary information of Nangate Inc., and is protected by U.S. and *
* * international laws and/or treaties. *
* * *
* * The copyright notice(s) in this file does not indicate actual or intended *
* * publication of this file. *
* * *
* * buildcell, v2010.08-HR32-SP3-2010-08-05 - build 1009061800 *
* * *
* ******************************************************************************
*
*
* Running on brazil06.nangate.com.br for user Giancarlo Franciscatto (gfr).
* Local time is now Fri, 3 Dec 2010, 19:19:40.
* Main process id is 28006.
*
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* *
* Cellname: XNOR2_X1. *
* *
* Technology: NCSU FreePDK 45nm. *
* Format: Cdl. *
* *
* Written on brazil06.nangate.com.br for user Giancarlo Franciscatto (gfr) *
* at 19:19:40 on Fri, 3 Dec 2010. *
* *
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.SUBCKT XNOR2_X1 A B ZN VDD VSS
*.PININFO A:I B:I ZN:O VDD:P VSS:G
*.EQN ZN=!(A ^ B)
M_i_0 net_001 A net_000 VSS NMOS_VTL W=0.210000U L=0.050000U
M_i_5 VSS B net_001 VSS NMOS_VTL W=0.210000U L=0.050000U
M_i_11 net_002 net_000 VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_17 ZN A net_002 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_23 net_002 B ZN VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_29 net_000 A VDD VDD PMOS_VTL W=0.315000U L=0.050000U
M_i_36 VDD B net_000 VDD PMOS_VTL W=0.315000U L=0.050000U
M_i_42 ZN net_000 VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_48 net_003 A ZN VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_53 VDD B net_003 VDD PMOS_VTL W=0.630000U L=0.050000U
.ENDS
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*
* END
*
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