| * |
| * ****************************************************************************** |
| * * * |
| * * Copyright (C) 2004-2010, Nangate Inc. * |
| * * All rights reserved. * |
| * * * |
| * * Nangate and the Nangate logo are trademarks of Nangate Inc. * |
| * * * |
| * * All trademarks, logos, software marks, and trade names (collectively the * |
| * * "Marks") in this program are proprietary to Nangate or other respective * |
| * * owners that have granted Nangate the right and license to use such Marks. * |
| * * You are not permitted to use the Marks without the prior written consent * |
| * * of Nangate or such third party that may own the Marks. * |
| * * * |
| * * This file has been provided pursuant to a License Agreement containing * |
| * * restrictions on its use. This file contains valuable trade secrets and * |
| * * proprietary information of Nangate Inc., and is protected by U.S. and * |
| * * international laws and/or treaties. * |
| * * * |
| * * The copyright notice(s) in this file does not indicate actual or intended * |
| * * publication of this file. * |
| * * * |
| * * buildcell, v2010.08-HR32-SP3-2010-08-05 - build 1009061800 * |
| * * * |
| * ****************************************************************************** |
| * |
| * |
| * Running on brazil06.nangate.com.br for user Giancarlo Franciscatto (gfr). |
| * Local time is now Fri, 3 Dec 2010, 18:55:24. |
| * Main process id is 28034. |
| * |
| ******************************************************************************** |
| * * |
| * Cellname: SDFF_X1. * |
| * * |
| * Technology: NCSU FreePDK 45nm. * |
| * Format: Cdl. * |
| * * |
| * Written on brazil06.nangate.com.br for user Giancarlo Franciscatto (gfr) * |
| * at 18:55:24 on Fri, 3 Dec 2010. * |
| * * |
| ******************************************************************************** |
| .SUBCKT SDFF_X1 D SE SI CK Q QN VDD VSS |
| *.PININFO D:I SE:I SI:I CK:I Q:O QN:O VDD:P VSS:G |
| M_i_7 QN net_000 VSS VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_0 VSS net_002 Q VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_13 VSS net_002 net_000 VSS NMOS_VTL W=0.210000U L=0.050000U |
| M_i_20 net_001 net_000 VSS VSS NMOS_VTL W=0.090000U L=0.050000U |
| M_i_24 net_002 net_009 net_001 VSS NMOS_VTL W=0.090000U L=0.050000U |
| M_i_30 net_003 net_004 net_002 VSS NMOS_VTL W=0.210000U L=0.050000U |
| M_i_34 VSS net_007 net_003 VSS NMOS_VTL W=0.210000U L=0.050000U |
| M_i_40 net_004 net_009 VSS VSS NMOS_VTL W=0.210000U L=0.050000U |
| M_i_75 net_009 CK VSS VSS NMOS_VTL W=0.210000U L=0.050000U |
| M_i_54 net_006 net_005 VSS VSS NMOS_VTL W=0.090000U L=0.050000U |
| M_i_58 net_007 net_004 net_006 VSS NMOS_VTL W=0.090000U L=0.050000U |
| M_i_64 net_008 net_009 net_007 VSS NMOS_VTL W=0.210000U L=0.050000U |
| M_i_69 VSS net_011 net_008 VSS NMOS_VTL W=0.210000U L=0.050000U |
| M_i_47 VSS net_007 net_005 VSS NMOS_VTL W=0.210000U L=0.050000U |
| M_i_96 VSS SI net_012 VSS NMOS_VTL W=0.210000U L=0.050000U |
| M_i_92 net_012 SE net_011 VSS NMOS_VTL W=0.210000U L=0.050000U |
| M_i_86 net_011 net_013 net_010 VSS NMOS_VTL W=0.275000U L=0.050000U |
| M_i_81 net_010 D VSS VSS NMOS_VTL W=0.275000U L=0.050000U |
| M_i_102 net_013 SE VSS VSS NMOS_VTL W=0.210000U L=0.050000U |
| M_i_115 QN net_000 VDD VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_108 VDD net_002 Q VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_121 VDD net_002 net_000 VDD PMOS_VTL W=0.315000U L=0.050000U |
| M_i_128 net_014 net_000 VDD VDD PMOS_VTL W=0.090000U L=0.050000U |
| M_i_132 net_002 net_004 net_014 VDD PMOS_VTL W=0.090000U L=0.050000U |
| M_i_138 net_015 net_009 net_002 VDD PMOS_VTL W=0.315000U L=0.050000U |
| M_i_143 VDD net_007 net_015 VDD PMOS_VTL W=0.315000U L=0.050000U |
| M_i_149 net_004 net_009 VDD VDD PMOS_VTL W=0.315000U L=0.050000U |
| M_i_182 net_009 CK VDD VDD PMOS_VTL W=0.315000U L=0.050000U |
| M_i_162 net_016 net_005 VDD VDD PMOS_VTL W=0.090000U L=0.050000U |
| M_i_166 net_007 net_009 net_016 VDD PMOS_VTL W=0.090000U L=0.050000U |
| M_i_172 net_017 net_004 net_007 VDD PMOS_VTL W=0.315000U L=0.050000U |
| M_i_176 VDD net_011 net_017 VDD PMOS_VTL W=0.315000U L=0.050000U |
| M_i_155 VDD net_007 net_005 VDD PMOS_VTL W=0.315000U L=0.050000U |
| M_i_189 net_018 SI VDD VDD PMOS_VTL W=0.315000U L=0.050000U |
| M_i_194 net_011 net_013 net_018 VDD PMOS_VTL W=0.315000U L=0.050000U |
| M_i_200 net_019 SE net_011 VDD PMOS_VTL W=0.420000U L=0.050000U |
| M_i_204 VDD D net_019 VDD PMOS_VTL W=0.420000U L=0.050000U |
| M_i_210 net_013 SE VDD VDD PMOS_VTL W=0.315000U L=0.050000U |
| .ENDS |
| |
| ******************************************************************************** |
| * |
| * END |
| * |
| ******************************************************************************** |
