blob: 24c0f40ac56dcc958dd3171183344b146236cc8e [file] [log] [blame]
*
* ******************************************************************************
* * *
* * Copyright (C) 2004-2010, Nangate Inc. *
* * All rights reserved. *
* * *
* * Nangate and the Nangate logo are trademarks of Nangate Inc. *
* * *
* * All trademarks, logos, software marks, and trade names (collectively the *
* * "Marks") in this program are proprietary to Nangate or other respective *
* * owners that have granted Nangate the right and license to use such Marks. *
* * You are not permitted to use the Marks without the prior written consent *
* * of Nangate or such third party that may own the Marks. *
* * *
* * This file has been provided pursuant to a License Agreement containing *
* * restrictions on its use. This file contains valuable trade secrets and *
* * proprietary information of Nangate Inc., and is protected by U.S. and *
* * international laws and/or treaties. *
* * *
* * The copyright notice(s) in this file does not indicate actual or intended *
* * publication of this file. *
* * *
* * buildcell, v2010.08-HR32-SP3-2010-08-05 - build 1009061800 *
* * *
* ******************************************************************************
*
*
* Running on brazil06.nangate.com.br for user Giancarlo Franciscatto (gfr).
* Local time is now Fri, 3 Dec 2010, 19:08:17.
* Main process id is 28034.
*
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* *
* Cellname: OR4_X1. *
* *
* Technology: NCSU FreePDK 45nm. *
* Format: Cdl. *
* *
* Written on brazil06.nangate.com.br for user Giancarlo Franciscatto (gfr) *
* at 19:08:17 on Fri, 3 Dec 2010. *
* *
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.SUBCKT OR4_X1 A1 A2 A3 A4 ZN VDD VSS
*.PININFO A1:I A2:I A3:I A4:I ZN:O VDD:P VSS:G
*.EQN ZN=(((A1 + A2) + A3) + A4)
M_i_2 ZN_neg A1 VSS VSS NMOS_VTL W=0.210000U L=0.050000U
M_i_3 VSS A2 ZN_neg VSS NMOS_VTL W=0.210000U L=0.050000U
M_i_4 ZN_neg A3 VSS VSS NMOS_VTL W=0.210000U L=0.050000U
M_i_5 VSS A4 ZN_neg VSS NMOS_VTL W=0.210000U L=0.050000U
M_i_0 ZN ZN_neg VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_6 net_0 A1 ZN_neg VDD PMOS_VTL W=0.315000U L=0.050000U
M_i_7 net_1 A2 net_0 VDD PMOS_VTL W=0.315000U L=0.050000U
M_i_8 net_2 A3 net_1 VDD PMOS_VTL W=0.315000U L=0.050000U
M_i_9 VDD A4 net_2 VDD PMOS_VTL W=0.315000U L=0.050000U
M_i_1 ZN ZN_neg VDD VDD PMOS_VTL W=0.630000U L=0.050000U
.ENDS
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*
* END
*
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