blob: 558b4b4087136e2fe8fe1603ce5139d05a26393a [file] [log] [blame]
*
* ******************************************************************************
* * *
* * Copyright (C) 2004-2010, Nangate Inc. *
* * All rights reserved. *
* * *
* * Nangate and the Nangate logo are trademarks of Nangate Inc. *
* * *
* * All trademarks, logos, software marks, and trade names (collectively the *
* * "Marks") in this program are proprietary to Nangate or other respective *
* * owners that have granted Nangate the right and license to use such Marks. *
* * You are not permitted to use the Marks without the prior written consent *
* * of Nangate or such third party that may own the Marks. *
* * *
* * This file has been provided pursuant to a License Agreement containing *
* * restrictions on its use. This file contains valuable trade secrets and *
* * proprietary information of Nangate Inc., and is protected by U.S. and *
* * international laws and/or treaties. *
* * *
* * The copyright notice(s) in this file does not indicate actual or intended *
* * publication of this file. *
* * *
* * buildcell, v2010.08-HR32-SP3-2010-08-05 - build 1009061800 *
* * *
* ******************************************************************************
*
*
* Running on brazil06.nangate.com.br for user Giancarlo Franciscatto (gfr).
* Local time is now Fri, 3 Dec 2010, 18:59:00.
* Main process id is 28006.
*
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* *
* Cellname: DLH_X1. *
* *
* Technology: NCSU FreePDK 45nm. *
* Format: Cdl. *
* *
* Written on brazil06.nangate.com.br for user Giancarlo Franciscatto (gfr) *
* at 18:59:00 on Fri, 3 Dec 2010. *
* *
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.SUBCKT DLH_X1 D G Q VDD VSS
*.PININFO D:I G:I Q:O VDD:P VSS:G
M_i_0 VSS G net_000 VSS NMOS_VTL W=0.210000U L=0.050000U
M_i_41_11 Q net_003 VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_7 net_001 net_000 VSS VSS NMOS_VTL W=0.210000U L=0.050000U
M_i_13 net_002 D VSS VSS NMOS_VTL W=0.210000U L=0.050000U
M_i_18 net_003 net_001 net_002 VSS NMOS_VTL W=0.210000U L=0.050000U
M_i_24 net_004 net_000 net_003 VSS NMOS_VTL W=0.090000U L=0.050000U
M_i_28 VSS net_005 net_004 VSS NMOS_VTL W=0.090000U L=0.050000U
M_i_34 VSS net_003 net_005 VSS NMOS_VTL W=0.090000U L=0.050000U
M_i_48 VDD G net_000 VDD PMOS_VTL W=0.315000U L=0.050000U
M_i_89_4 Q net_003 VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_55 net_001 net_000 VDD VDD PMOS_VTL W=0.315000U L=0.050000U
M_i_61 net_006 D VDD VDD PMOS_VTL W=0.315000U L=0.050000U
M_i_66 net_003 net_000 net_006 VDD PMOS_VTL W=0.315000U L=0.050000U
M_i_72 net_007 net_001 net_003 VDD PMOS_VTL W=0.090000U L=0.050000U
M_i_76 VDD net_005 net_007 VDD PMOS_VTL W=0.090000U L=0.050000U
M_i_82 VDD net_003 net_005 VDD PMOS_VTL W=0.090000U L=0.050000U
.ENDS
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*
* END
*
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