| * |
| * ****************************************************************************** |
| * * * |
| * * Copyright (C) 2004-2010, Nangate Inc. * |
| * * All rights reserved. * |
| * * * |
| * * Nangate and the Nangate logo are trademarks of Nangate Inc. * |
| * * * |
| * * All trademarks, logos, software marks, and trade names (collectively the * |
| * * "Marks") in this program are proprietary to Nangate or other respective * |
| * * owners that have granted Nangate the right and license to use such Marks. * |
| * * You are not permitted to use the Marks without the prior written consent * |
| * * of Nangate or such third party that may own the Marks. * |
| * * * |
| * * This file has been provided pursuant to a License Agreement containing * |
| * * restrictions on its use. This file contains valuable trade secrets and * |
| * * proprietary information of Nangate Inc., and is protected by U.S. and * |
| * * international laws and/or treaties. * |
| * * * |
| * * The copyright notice(s) in this file does not indicate actual or intended * |
| * * publication of this file. * |
| * * * |
| * * buildcell, v2010.08-HR32-SP3-2010-08-05 - build 1009061800 * |
| * * * |
| * ****************************************************************************** |
| * |
| * |
| * Running on brazil06.nangate.com.br for user Giancarlo Franciscatto (gfr). |
| * Local time is now Fri, 3 Dec 2010, 19:31:56. |
| * Main process id is 28006. |
| * |
| ******************************************************************************** |
| * * |
| * Cellname: BUF_X32. * |
| * * |
| * Technology: NCSU FreePDK 45nm. * |
| * Format: Cdl. * |
| * * |
| * Written on brazil06.nangate.com.br for user Giancarlo Franciscatto (gfr) * |
| * at 19:31:56 on Fri, 3 Dec 2010. * |
| * * |
| ******************************************************************************** |
| .SUBCKT BUF_X32 A Z VDD VSS |
| *.PININFO A:I Z:O VDD:P VSS:G |
| *.EQN Z=A |
| M_i_2_0 Z_neg A VSS VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_2_1 VSS A Z_neg VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_2_2 Z_neg A VSS VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_2_3 VSS A Z_neg VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_2_4 Z_neg A VSS VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_2_5 VSS A Z_neg VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_2_6 Z_neg A VSS VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_2_7 VSS A Z_neg VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_2_8 Z_neg A VSS VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_2_9 VSS A Z_neg VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_2_10 Z_neg A VSS VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_2_11 VSS A Z_neg VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_2_12 Z_neg A VSS VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_2_13 VSS A Z_neg VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_2_14 Z_neg A VSS VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_2_15 VSS A Z_neg VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_0_0 Z Z_neg VSS VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_0_1 VSS Z_neg Z VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_0_2 Z Z_neg VSS VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_0_3 VSS Z_neg Z VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_0_4 Z Z_neg VSS VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_0_5 VSS Z_neg Z VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_0_6 Z Z_neg VSS VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_0_7 VSS Z_neg Z VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_0_8 Z Z_neg VSS VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_0_9 VSS Z_neg Z VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_0_10 Z Z_neg VSS VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_0_11 VSS Z_neg Z VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_0_12 Z Z_neg VSS VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_0_13 VSS Z_neg Z VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_0_14 Z Z_neg VSS VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_0_15 VSS Z_neg Z VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_0_16 Z Z_neg VSS VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_0_17 VSS Z_neg Z VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_0_18 Z Z_neg VSS VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_0_19 VSS Z_neg Z VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_0_20 Z Z_neg VSS VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_0_21 VSS Z_neg Z VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_0_22 Z Z_neg VSS VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_0_23 VSS Z_neg Z VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_0_24 Z Z_neg VSS VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_0_25 VSS Z_neg Z VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_0_26 Z Z_neg VSS VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_0_27 VSS Z_neg Z VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_0_28 Z Z_neg VSS VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_0_29 VSS Z_neg Z VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_0_30 Z Z_neg VSS VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_0_31 VSS Z_neg Z VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_3_0 Z_neg A VDD VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_3_1 VDD A Z_neg VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_3_2 Z_neg A VDD VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_3_3 VDD A Z_neg VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_3_4 Z_neg A VDD VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_3_5 VDD A Z_neg VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_3_6 Z_neg A VDD VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_3_7 VDD A Z_neg VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_3_8 Z_neg A VDD VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_3_9 VDD A Z_neg VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_3_10 Z_neg A VDD VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_3_11 VDD A Z_neg VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_3_12 Z_neg A VDD VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_3_13 VDD A Z_neg VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_3_14 Z_neg A VDD VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_3_15 VDD A Z_neg VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_1_0 Z Z_neg VDD VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_1_1 VDD Z_neg Z VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_1_2 Z Z_neg VDD VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_1_3 VDD Z_neg Z VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_1_4 Z Z_neg VDD VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_1_5 VDD Z_neg Z VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_1_6 Z Z_neg VDD VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_1_7 VDD Z_neg Z VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_1_8 Z Z_neg VDD VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_1_9 VDD Z_neg Z VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_1_10 Z Z_neg VDD VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_1_11 VDD Z_neg Z VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_1_12 Z Z_neg VDD VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_1_13 VDD Z_neg Z VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_1_14 Z Z_neg VDD VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_1_15 VDD Z_neg Z VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_1_16 Z Z_neg VDD VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_1_17 VDD Z_neg Z VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_1_18 Z Z_neg VDD VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_1_19 VDD Z_neg Z VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_1_20 Z Z_neg VDD VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_1_21 VDD Z_neg Z VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_1_22 Z Z_neg VDD VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_1_23 VDD Z_neg Z VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_1_24 Z Z_neg VDD VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_1_25 VDD Z_neg Z VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_1_26 Z Z_neg VDD VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_1_27 VDD Z_neg Z VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_1_28 Z Z_neg VDD VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_1_29 VDD Z_neg Z VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_1_30 Z Z_neg VDD VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_1_31 VDD Z_neg Z VDD PMOS_VTL W=0.630000U L=0.050000U |
| .ENDS |
| |
| ******************************************************************************** |
| * |
| * END |
| * |
| ******************************************************************************** |
