| //*****************************************************************************/ |
| // */ |
| // Generated by HHNEC Design Service Department */ |
| // Created: Nov.22,2012 by Library Group */ |
| // Process Name: EF130 0.13um 1.8v Process */ |
| // Revision :V0.1 */ |
| // Revision History: */ |
| // 1. modify following specify blocks: dlrbn dlrbp dlrtn dlrtp */ |
| // */ |
| //*****************************************************************************/ |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a2111o_0 ( X , A1 , A2 , B1 , C1 , D1 ); |
| output X ; |
| input A1 , A2 , B1 , C1 , D1 ; |
| |
| wire X , A1 , A2 , B1 ; |
| wire C1 , D1 , csi_opt_273 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 +=> X) = (0:0:0,0:0:0); |
| (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!C1&!D1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!C1&!D1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!C1&!D1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!B1&!D1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B1&!D1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B1&!D1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!B1&!C1)) (D1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B1&!C1)) (D1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B1&!C1)) (D1 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and ( csi_opt_273 , A1 , A2 ) ; |
| or #0.001 ( X , C1 , B1 , csi_opt_273 , D1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a2111o_1 ( X , A1 , A2 , B1 , C1 , D1 ); |
| output X ; |
| input A1 , A2 , B1 , C1 , D1 ; |
| |
| wire X , A1 , A2 , B1 ; |
| wire C1 , D1 , csi_opt_273 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 +=> X) = (0:0:0,0:0:0); |
| (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!C1&!D1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!C1&!D1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!C1&!D1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!B1&!D1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B1&!D1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B1&!D1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!B1&!C1)) (D1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B1&!C1)) (D1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B1&!C1)) (D1 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and ( csi_opt_273 , A1 , A2 ) ; |
| or #0.001 ( X , C1 , B1 , csi_opt_273 , D1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a2111o_2 ( X , A1 , A2 , B1 , C1 , D1 ); |
| output X ; |
| input A1 , A2 , B1 , C1 , D1 ; |
| |
| wire X , A1 , A2 , B1 ; |
| wire C1 , D1 , csi_opt_273 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 +=> X) = (0:0:0,0:0:0); |
| (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!C1&!D1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!C1&!D1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!C1&!D1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!B1&!D1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B1&!D1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B1&!D1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!B1&!C1)) (D1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B1&!C1)) (D1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B1&!C1)) (D1 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and ( csi_opt_273 , A1 , A2 ) ; |
| or #0.001 ( X , C1 , B1 , csi_opt_273 , D1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a2111o_4 ( X , A1 , A2 , B1 , C1 , D1 ); |
| output X ; |
| input A1 , A2 , B1 , C1 , D1 ; |
| |
| wire X , A1 , A2 , B1 ; |
| wire C1 , D1 , csi_opt_273 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 +=> X) = (0:0:0,0:0:0); |
| (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!C1&!D1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!C1&!D1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!C1&!D1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!B1&!D1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B1&!D1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B1&!D1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!B1&!C1)) (D1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B1&!C1)) (D1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B1&!C1)) (D1 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and ( csi_opt_273 , A1 , A2 ) ; |
| or #0.001 ( X , C1 , B1 , csi_opt_273 , D1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a2111oi_0 ( Y , A1 , A2 , B1 , C1 , D1 ); |
| output Y ; |
| input A1 , A2 , B1 , C1 , D1 ; |
| |
| wire Y , A1 , A2 , B1 ; |
| wire C1 , D1 , csi_opt_274 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 -=> Y) = (0:0:0,0:0:0); |
| (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!C1&!D1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!C1&!D1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!C1&!D1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!B1&!D1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B1&!D1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B1&!D1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!B1&!C1)) (D1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B1&!C1)) (D1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B1&!C1)) (D1 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and ( csi_opt_274 , A1 , A2 ) ; |
| nor #0.001 ( Y , B1 , C1 , D1 , csi_opt_274 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a2111oi_1 ( Y , A1 , A2 , B1 , C1 , D1 ); |
| output Y ; |
| input A1 , A2 , B1 , C1 , D1 ; |
| |
| wire Y , A1 , A2 , B1 ; |
| wire C1 , D1 , csi_opt_274 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 -=> Y) = (0:0:0,0:0:0); |
| (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!C1&!D1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!C1&!D1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!C1&!D1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!B1&!D1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B1&!D1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B1&!D1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!B1&!C1)) (D1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B1&!C1)) (D1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B1&!C1)) (D1 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and ( csi_opt_274 , A1 , A2 ) ; |
| nor #0.001 ( Y , B1 , C1 , D1 , csi_opt_274 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a2111oi_2 ( Y , A1 , A2 , B1 , C1 , D1 ); |
| output Y ; |
| input A1 , A2 , B1 , C1 , D1 ; |
| |
| wire Y , A1 , A2 , B1 ; |
| wire C1 , D1 , csi_opt_274 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 -=> Y) = (0:0:0,0:0:0); |
| (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!C1&!D1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!C1&!D1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!C1&!D1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!B1&!D1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B1&!D1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B1&!D1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!B1&!C1)) (D1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B1&!C1)) (D1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B1&!C1)) (D1 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and ( csi_opt_274 , A1 , A2 ) ; |
| nor #0.001 ( Y , B1 , C1 , D1 , csi_opt_274 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a2111oi_4 ( Y , A1 , A2 , B1 , C1 , D1 ); |
| output Y ; |
| input A1 , A2 , B1 , C1 , D1 ; |
| |
| wire Y , A1 , A2 , B1 ; |
| wire C1 , D1 , csi_opt_274 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 -=> Y) = (0:0:0,0:0:0); |
| (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!C1&!D1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!C1&!D1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!C1&!D1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!B1&!D1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B1&!D1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B1&!D1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!B1&!C1)) (D1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B1&!C1)) (D1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B1&!C1)) (D1 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and ( csi_opt_274 , A1 , A2 ) ; |
| nor #0.001 ( Y , B1 , C1 , D1 , csi_opt_274 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a211o_0 ( X , A1 , A2 , B1 , C1 ); |
| output X ; |
| input A1 , A2 , B1 , C1 ; |
| |
| wire X , A1 , A2 , B1 ; |
| wire C1 , csi_opt_273 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 +=> X) = (0:0:0,0:0:0); |
| (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and ( csi_opt_273 , A1 , A2 ) ; |
| or #0.001 ( X , csi_opt_273 , C1 , B1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a211o_1 ( X , A1 , A2 , B1 , C1 ); |
| output X ; |
| input A1 , A2 , B1 , C1 ; |
| |
| wire X , A1 , A2 , B1 ; |
| wire C1 , csi_opt_273 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 +=> X) = (0:0:0,0:0:0); |
| (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and ( csi_opt_273 , A1 , A2 ) ; |
| or #0.001 ( X , csi_opt_273 , C1 , B1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a211o_2 ( X , A1 , A2 , B1 , C1 ); |
| output X ; |
| input A1 , A2 , B1 , C1 ; |
| |
| wire X , A1 , A2 , B1 ; |
| wire C1 , csi_opt_273 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 +=> X) = (0:0:0,0:0:0); |
| (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and ( csi_opt_273 , A1 , A2 ) ; |
| or #0.001 ( X , csi_opt_273 , C1 , B1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a211o_4 ( X , A1 , A2 , B1 , C1 ); |
| output X ; |
| input A1 , A2 , B1 , C1 ; |
| |
| wire X , A1 , A2 , B1 ; |
| wire C1 , csi_opt_273 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 +=> X) = (0:0:0,0:0:0); |
| (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and ( csi_opt_273 , A1 , A2 ) ; |
| or #0.001 ( X , csi_opt_273 , C1 , B1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a211oi_0 ( Y , A1 , A2 , B1 , C1 ); |
| output Y ; |
| input A1 , A2 , B1 , C1 ; |
| |
| wire Y , A1 , A2 , B1 ; |
| wire C1 , csi_opt_274 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 -=> Y) = (0:0:0,0:0:0); |
| (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and ( csi_opt_274 , A1 , A2 ) ; |
| nor #0.001 ( Y , csi_opt_274 , B1 , C1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a211oi_1 ( Y , A1 , A2 , B1 , C1 ); |
| output Y ; |
| input A1 , A2 , B1 , C1 ; |
| |
| wire Y , A1 , A2 , B1 ; |
| wire C1 , csi_opt_274 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 -=> Y) = (0:0:0,0:0:0); |
| (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and ( csi_opt_274 , A1 , A2 ) ; |
| nor #0.001 ( Y , csi_opt_274 , B1 , C1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a211oi_2 ( Y , A1 , A2 , B1 , C1 ); |
| output Y ; |
| input A1 , A2 , B1 , C1 ; |
| |
| wire Y , A1 , A2 , B1 ; |
| wire C1 , csi_opt_274 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 -=> Y) = (0:0:0,0:0:0); |
| (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and ( csi_opt_274 , A1 , A2 ) ; |
| nor #0.001 ( Y , csi_opt_274 , B1 , C1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a211oi_4 ( Y , A1 , A2 , B1 , C1 ); |
| output Y ; |
| input A1 , A2 , B1 , C1 ; |
| |
| wire Y , A1 , A2 , B1 ; |
| wire C1 , csi_opt_274 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 -=> Y) = (0:0:0,0:0:0); |
| (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and ( csi_opt_274 , A1 , A2 ) ; |
| nor #0.001 ( Y , csi_opt_274 , B1 , C1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a21bo_0 ( X , A1 , A2 , B1N ); |
| output X ; |
| input A1 , A2 , B1N ; |
| |
| wire X , A1 , A2 , B1N ; |
| wire csi_opt_289 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 +=> X) = (0:0:0,0:0:0); |
| (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2)) (B1N -=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2)) (B1N -=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2)) (B1N -=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nand ( csi_opt_289 , A2 , A1 ) ; |
| nand #0.001 ( X , B1N , csi_opt_289 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a21bo_1 ( X , A1 , A2 , B1N ); |
| output X ; |
| input A1 , A2 , B1N ; |
| |
| wire X , A1 , A2 , B1N ; |
| wire csi_opt_289 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 +=> X) = (0:0:0,0:0:0); |
| (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2)) (B1N -=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2)) (B1N -=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2)) (B1N -=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nand ( csi_opt_289 , A2 , A1 ) ; |
| nand #0.001 ( X , B1N , csi_opt_289 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a21bo_2 ( X , A1 , A2 , B1N ); |
| output X ; |
| input A1 , A2 , B1N ; |
| |
| wire X , A1 , A2 , B1N ; |
| wire csi_opt_289 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 +=> X) = (0:0:0,0:0:0); |
| (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2)) (B1N -=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2)) (B1N -=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2)) (B1N -=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nand ( csi_opt_289 , A2 , A1 ) ; |
| nand #0.001 ( X , B1N , csi_opt_289 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a21bo_4 ( X , A1 , A2 , B1N ); |
| output X ; |
| input A1 , A2 , B1N ; |
| |
| wire X , A1 , A2 , B1N ; |
| wire csi_opt_289 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 +=> X) = (0:0:0,0:0:0); |
| (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2)) (B1N -=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2)) (B1N -=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2)) (B1N -=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nand ( csi_opt_289 , A2 , A1 ) ; |
| nand #0.001 ( X , B1N , csi_opt_289 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a21boi_0 (Y,A1,A2,B1N); |
| output Y; |
| input A1,A2,B1N; |
| wire b; |
| not (b,B1N); |
| and ( csi_opt_273 , A1 , A2 ) ; |
| nor #0.001 ( Y , b , csi_opt_273 ) ; |
| // modification by B1NB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 -=> Y) = (0:0:0,0:0:0); |
| (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2)) (B1N +=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2)) (B1N +=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2)) (B1N +=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a21boi_1 (Y,A1,A2,B1N); |
| output Y; |
| input A1,A2,B1N; |
| wire b; |
| not (b,B1N); |
| and ( csi_opt_273 , A1 , A2 ) ; |
| nor #0.001 ( Y , b , csi_opt_273 ) ; |
| // modification by B1NB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 -=> Y) = (0:0:0,0:0:0); |
| (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2)) (B1N +=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2)) (B1N +=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2)) (B1N +=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a21boi_2 (Y,A1,A2,B1N); |
| output Y; |
| input A1,A2,B1N; |
| wire b; |
| not (b,B1N); |
| and ( csi_opt_273 , A1 , A2 ) ; |
| nor #0.001 ( Y , b , csi_opt_273 ) ; |
| // modification by B1NB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 -=> Y) = (0:0:0,0:0:0); |
| (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2)) (B1N +=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2)) (B1N +=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2)) (B1N +=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a21boi_4 (Y,A1,A2,B1N); |
| output Y; |
| input A1,A2,B1N; |
| wire b; |
| not (b,B1N); |
| and ( csi_opt_273 , A1 , A2 ) ; |
| nor #0.001 ( Y , b , csi_opt_273 ) ; |
| // modification by B1NB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 -=> Y) = (0:0:0,0:0:0); |
| (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2)) (B1N +=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2)) (B1N +=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2)) (B1N +=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a21o_0 ( X , A1 , A2 , B1 ); |
| output X ; |
| input A1 , A2 , B1 ; |
| |
| wire X , A1 , A2 , B1 ; |
| wire csi_opt_273 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 +=> X) = (0:0:0,0:0:0); |
| (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2)) (B1 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and ( csi_opt_273 , A1 , A2 ) ; |
| or #0.001 ( X , csi_opt_273 , B1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a21o_1 ( X , A1 , A2 , B1 ); |
| output X ; |
| input A1 , A2 , B1 ; |
| |
| wire X , A1 , A2 , B1 ; |
| wire csi_opt_273 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 +=> X) = (0:0:0,0:0:0); |
| (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2)) (B1 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and ( csi_opt_273 , A1 , A2 ) ; |
| or #0.001 ( X , csi_opt_273 , B1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a21o_2 ( X , A1 , A2 , B1 ); |
| output X ; |
| input A1 , A2 , B1 ; |
| |
| wire X , A1 , A2 , B1 ; |
| wire csi_opt_273 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 +=> X) = (0:0:0,0:0:0); |
| (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2)) (B1 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and ( csi_opt_273 , A1 , A2 ) ; |
| or #0.001 ( X , csi_opt_273 , B1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a21o_4 ( X , A1 , A2 , B1 ); |
| output X ; |
| input A1 , A2 , B1 ; |
| |
| wire X , A1 , A2 , B1 ; |
| wire csi_opt_273 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 +=> X) = (0:0:0,0:0:0); |
| (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2)) (B1 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and ( csi_opt_273 , A1 , A2 ) ; |
| or #0.001 ( X , csi_opt_273 , B1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a21oi_0 ( Y , A1 , A2 , B1 ); |
| output Y ; |
| input A1 , A2 , B1 ; |
| |
| wire Y , A1 , A2 , B1 ; |
| wire csi_opt_273 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 -=> Y) = (0:0:0,0:0:0); |
| (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and ( csi_opt_273 , A1 , A2 ) ; |
| nor #0.001 ( Y , B1 , csi_opt_273 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a21oi_1 ( Y , A1 , A2 , B1 ); |
| output Y ; |
| input A1 , A2 , B1 ; |
| |
| wire Y , A1 , A2 , B1 ; |
| wire csi_opt_273 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 -=> Y) = (0:0:0,0:0:0); |
| (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and ( csi_opt_273 , A1 , A2 ) ; |
| nor #0.001 ( Y , B1 , csi_opt_273 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a21oi_2 ( Y , A1 , A2 , B1 ); |
| output Y ; |
| input A1 , A2 , B1 ; |
| |
| wire Y , A1 , A2 , B1 ; |
| wire csi_opt_273 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 -=> Y) = (0:0:0,0:0:0); |
| (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and ( csi_opt_273 , A1 , A2 ) ; |
| nor #0.001 ( Y , B1 , csi_opt_273 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a21oi_4 ( Y , A1 , A2 , B1 ); |
| output Y ; |
| input A1 , A2 , B1 ; |
| |
| wire Y , A1 , A2 , B1 ; |
| wire csi_opt_273 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 -=> Y) = (0:0:0,0:0:0); |
| (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and ( csi_opt_273 , A1 , A2 ) ; |
| nor #0.001 ( Y , B1 , csi_opt_273 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a221o_0 ( X , A1 , A2 , B1 , B2 , C1 ); |
| output X ; |
| input A1 , A2 , B1 , B2 , C1 ; |
| |
| wire X , A1 , A2 , B1 ; |
| wire B2 , C1 , csi_opt_273, csi_opt_274 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((A2&!B1&!B2&!C1)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((A2&!B1&B2&!C1)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((A2&B1&!B2&!C1)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!B1&!B2&!C1)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!B1&B2&!C1)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&B1&!B2&!C1)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&B2&!C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&B2&!C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&B2&!C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&B1&!C1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&B1&!C1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&B1&!C1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!B1&!B2)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!B1&B2)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&B1&!B2)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B1&!B2)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B1&B2)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&B1&!B2)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B1&!B2)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B1&B2)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&B1&!B2)) (C1 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and ( csi_opt_273 , B1 , B2 ) ; |
| and ( csi_opt_274 , A1 , A2 ) ; |
| or #0.001 ( X , csi_opt_274 , csi_opt_273 , C1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a221o_1 ( X , A1 , A2 , B1 , B2 , C1 ); |
| output X ; |
| input A1 , A2 , B1 , B2 , C1 ; |
| |
| wire X , A1 , A2 , B1 ; |
| wire B2 , C1 , csi_opt_273, csi_opt_274 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((A2&!B1&!B2&!C1)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((A2&!B1&B2&!C1)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((A2&B1&!B2&!C1)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!B1&!B2&!C1)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!B1&B2&!C1)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&B1&!B2&!C1)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&B2&!C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&B2&!C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&B2&!C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&B1&!C1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&B1&!C1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&B1&!C1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!B1&!B2)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!B1&B2)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&B1&!B2)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B1&!B2)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B1&B2)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&B1&!B2)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B1&!B2)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B1&B2)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&B1&!B2)) (C1 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and ( csi_opt_273 , B1 , B2 ) ; |
| and ( csi_opt_274 , A1 , A2 ) ; |
| or #0.001 ( X , csi_opt_274 , csi_opt_273 , C1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a221o_2 ( X , A1 , A2 , B1 , B2 , C1 ); |
| output X ; |
| input A1 , A2 , B1 , B2 , C1 ; |
| |
| wire X , A1 , A2 , B1 ; |
| wire B2 , C1 , csi_opt_273, csi_opt_274 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((A2&!B1&!B2&!C1)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((A2&!B1&B2&!C1)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((A2&B1&!B2&!C1)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!B1&!B2&!C1)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!B1&B2&!C1)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&B1&!B2&!C1)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&B2&!C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&B2&!C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&B2&!C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&B1&!C1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&B1&!C1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&B1&!C1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!B1&!B2)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!B1&B2)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&B1&!B2)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B1&!B2)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B1&B2)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&B1&!B2)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B1&!B2)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B1&B2)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&B1&!B2)) (C1 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and ( csi_opt_273 , B1 , B2 ) ; |
| and ( csi_opt_274 , A1 , A2 ) ; |
| or #0.001 ( X , csi_opt_274 , csi_opt_273 , C1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a221o_4 ( X , A1 , A2 , B1 , B2 , C1 ); |
| output X ; |
| input A1 , A2 , B1 , B2 , C1 ; |
| |
| wire X , A1 , A2 , B1 ; |
| wire B2 , C1 , csi_opt_273, csi_opt_274 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((A2&!B1&!B2&!C1)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((A2&!B1&B2&!C1)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((A2&B1&!B2&!C1)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!B1&!B2&!C1)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!B1&B2&!C1)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&B1&!B2&!C1)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&B2&!C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&B2&!C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&B2&!C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&B1&!C1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&B1&!C1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&B1&!C1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!B1&!B2)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!B1&B2)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&B1&!B2)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B1&!B2)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B1&B2)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&B1&!B2)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B1&!B2)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B1&B2)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&B1&!B2)) (C1 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and ( csi_opt_273 , B1 , B2 ) ; |
| and ( csi_opt_274 , A1 , A2 ) ; |
| or #0.001 ( X , csi_opt_274 , csi_opt_273 , C1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a221oi_0 ( Y , A1 , A2 , B1 , B2 , C1 ); |
| output Y ; |
| input A1 , A2 , B1 , B2 , C1 ; |
| |
| wire Y , A1 , A2 , B1 ; |
| wire B2 , C1 , csi_opt_275, csi_opt_276 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((A2&!B1&!B2&!C1)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((A2&!B1&B2&!C1)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((A2&B1&!B2&!C1)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!B1&!B2&!C1)) (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!B1&B2&!C1)) (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&B1&!B2&!C1)) (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&B2&!C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&B2&!C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&B2&!C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&B1&!C1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&B1&!C1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&B1&!C1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!B1&!B2)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!B1&B2)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&B1&!B2)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B1&!B2)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B1&B2)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&B1&!B2)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B1&!B2)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B1&B2)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&B1&!B2)) (C1 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and ( csi_opt_275 , B1 , B2 ) ; |
| and ( csi_opt_276 , A1 , A2 ) ; |
| nor #0.001 ( Y , csi_opt_275 , C1 , csi_opt_276 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a221oi_1 ( Y , A1 , A2 , B1 , B2 , C1 ); |
| output Y ; |
| input A1 , A2 , B1 , B2 , C1 ; |
| |
| wire Y , A1 , A2 , B1 ; |
| wire B2 , C1 , csi_opt_275, csi_opt_276 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((A2&!B1&!B2&!C1)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((A2&!B1&B2&!C1)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((A2&B1&!B2&!C1)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!B1&!B2&!C1)) (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!B1&B2&!C1)) (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&B1&!B2&!C1)) (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&B2&!C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&B2&!C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&B2&!C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&B1&!C1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&B1&!C1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&B1&!C1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!B1&!B2)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!B1&B2)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&B1&!B2)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B1&!B2)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B1&B2)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&B1&!B2)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B1&!B2)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B1&B2)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&B1&!B2)) (C1 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and ( csi_opt_275 , B1 , B2 ) ; |
| and ( csi_opt_276 , A1 , A2 ) ; |
| nor #0.001 ( Y , csi_opt_275 , C1 , csi_opt_276 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a221oi_2 ( Y , A1 , A2 , B1 , B2 , C1 ); |
| output Y ; |
| input A1 , A2 , B1 , B2 , C1 ; |
| |
| wire Y , A1 , A2 , B1 ; |
| wire B2 , C1 , csi_opt_275, csi_opt_276 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((A2&!B1&!B2&!C1)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((A2&!B1&B2&!C1)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((A2&B1&!B2&!C1)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!B1&!B2&!C1)) (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!B1&B2&!C1)) (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&B1&!B2&!C1)) (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&B2&!C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&B2&!C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&B2&!C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&B1&!C1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&B1&!C1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&B1&!C1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!B1&!B2)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!B1&B2)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&B1&!B2)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B1&!B2)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B1&B2)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&B1&!B2)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B1&!B2)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B1&B2)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&B1&!B2)) (C1 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and ( csi_opt_275 , B1 , B2 ) ; |
| and ( csi_opt_276 , A1 , A2 ) ; |
| nor #0.001 ( Y , csi_opt_275 , C1 , csi_opt_276 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a221oi_4 ( Y , A1 , A2 , B1 , B2 , C1 ); |
| output Y ; |
| input A1 , A2 , B1 , B2 , C1 ; |
| |
| wire Y , A1 , A2 , B1 ; |
| wire B2 , C1 , csi_opt_275, csi_opt_276 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((A2&!B1&!B2&!C1)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((A2&!B1&B2&!C1)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((A2&B1&!B2&!C1)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!B1&!B2&!C1)) (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!B1&B2&!C1)) (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&B1&!B2&!C1)) (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&B2&!C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&B2&!C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&B2&!C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&B1&!C1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&B1&!C1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&B1&!C1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!B1&!B2)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!B1&B2)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&B1&!B2)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B1&!B2)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B1&B2)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&B1&!B2)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B1&!B2)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B1&B2)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&B1&!B2)) (C1 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and ( csi_opt_275 , B1 , B2 ) ; |
| and ( csi_opt_276 , A1 , A2 ) ; |
| nor #0.001 ( Y , csi_opt_275 , C1 , csi_opt_276 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a22o_0 ( X , A1 , A2 , B1 , B2 ); |
| output X ; |
| input A1 , A2 , B1 , B2 ; |
| |
| wire X , A1 , A2 , B1 ; |
| wire B2 , csi_opt_273, csi_opt_274 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((A2&!B1&!B2)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((A2&!B1&B2)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((A2&B1&!B2)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!B1&!B2)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!B1&B2)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&B1&!B2)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and ( csi_opt_273 , B1 , B2 ) ; |
| and ( csi_opt_274 , A1 , A2 ) ; |
| or #0.001 ( X , csi_opt_274 , csi_opt_273 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a22o_1 ( X , A1 , A2 , B1 , B2 ); |
| output X ; |
| input A1 , A2 , B1 , B2 ; |
| |
| wire X , A1 , A2 , B1 ; |
| wire B2 , csi_opt_273, csi_opt_274 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((A2&!B1&!B2)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((A2&!B1&B2)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((A2&B1&!B2)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!B1&!B2)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!B1&B2)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&B1&!B2)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and ( csi_opt_273 , B1 , B2 ) ; |
| and ( csi_opt_274 , A1 , A2 ) ; |
| or #0.001 ( X , csi_opt_274 , csi_opt_273 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a22o_2 ( X , A1 , A2 , B1 , B2 ); |
| output X ; |
| input A1 , A2 , B1 , B2 ; |
| |
| wire X , A1 , A2 , B1 ; |
| wire B2 , csi_opt_273, csi_opt_274 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((A2&!B1&!B2)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((A2&!B1&B2)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((A2&B1&!B2)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!B1&!B2)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!B1&B2)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&B1&!B2)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and ( csi_opt_273 , B1 , B2 ) ; |
| and ( csi_opt_274 , A1 , A2 ) ; |
| or #0.001 ( X , csi_opt_274 , csi_opt_273 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a22o_4 ( X , A1 , A2 , B1 , B2 ); |
| output X ; |
| input A1 , A2 , B1 , B2 ; |
| |
| wire X , A1 , A2 , B1 ; |
| wire B2 , csi_opt_273, csi_opt_274 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((A2&!B1&!B2)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((A2&!B1&B2)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((A2&B1&!B2)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!B1&!B2)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!B1&B2)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&B1&!B2)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and ( csi_opt_273 , B1 , B2 ) ; |
| and ( csi_opt_274 , A1 , A2 ) ; |
| or #0.001 ( X , csi_opt_274 , csi_opt_273 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a22oi_0 ( Y , A1 , A2 , B1 , B2 ); |
| output Y ; |
| input A1 , A2 , B1 , B2 ; |
| |
| wire Y , A1 , A2 , B1 ; |
| wire B2 , csi_opt_298, csi_opt_296 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((A2&!B1&!B2)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((A2&!B1&B2)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((A2&B1&!B2)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!B1&!B2)) (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!B1&B2)) (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&B1&!B2)) (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nand ( csi_opt_298 , A2 , A1 ) ; |
| nand ( csi_opt_296 , B2 , B1 ) ; |
| and #0.001 ( Y , csi_opt_298 , csi_opt_296 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a22oi_1 ( Y , A1 , A2 , B1 , B2 ); |
| output Y ; |
| input A1 , A2 , B1 , B2 ; |
| |
| wire Y , A1 , A2 , B1 ; |
| wire B2 , csi_opt_298, csi_opt_296 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((A2&!B1&!B2)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((A2&!B1&B2)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((A2&B1&!B2)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!B1&!B2)) (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!B1&B2)) (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&B1&!B2)) (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nand ( csi_opt_298 , A2 , A1 ) ; |
| nand ( csi_opt_296 , B2 , B1 ) ; |
| and #0.001 ( Y , csi_opt_298 , csi_opt_296 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a22oi_2 ( Y , A1 , A2 , B1 , B2 ); |
| output Y ; |
| input A1 , A2 , B1 , B2 ; |
| |
| wire Y , A1 , A2 , B1 ; |
| wire B2 , csi_opt_298, csi_opt_296 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((A2&!B1&!B2)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((A2&!B1&B2)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((A2&B1&!B2)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!B1&!B2)) (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!B1&B2)) (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&B1&!B2)) (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nand ( csi_opt_298 , A2 , A1 ) ; |
| nand ( csi_opt_296 , B2 , B1 ) ; |
| and #0.001 ( Y , csi_opt_298 , csi_opt_296 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a22oi_4 ( Y , A1 , A2 , B1 , B2 ); |
| output Y ; |
| input A1 , A2 , B1 , B2 ; |
| |
| wire Y , A1 , A2 , B1 ; |
| wire B2 , csi_opt_298, csi_opt_296 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((A2&!B1&!B2)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((A2&!B1&B2)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((A2&B1&!B2)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!B1&!B2)) (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!B1&B2)) (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&B1&!B2)) (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nand ( csi_opt_298 , A2 , A1 ) ; |
| nand ( csi_opt_296 , B2 , B1 ) ; |
| and #0.001 ( Y , csi_opt_298 , csi_opt_296 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a2bb2o_0 ( X , A1N , A2N , B1 , B2 ); |
| output X ; |
| input A1N , A2N , B1 , B2 ; |
| |
| wire X , A1N , A2N , B1 ; |
| wire B2 , csi_opt_273, csi_opt_274 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((!A2N&!B1&!B2)) (A1N -=> X) = (0:0:0,0:0:0); |
| if ((!A2N&!B1&B2)) (A1N -=> X) = (0:0:0,0:0:0); |
| if ((!A2N&B1&!B2)) (A1N -=> X) = (0:0:0,0:0:0); |
| if ((!A1N&!B1&!B2)) (A2N -=> X) = (0:0:0,0:0:0); |
| if ((!A1N&!B1&B2)) (A2N -=> X) = (0:0:0,0:0:0); |
| if ((!A1N&B1&!B2)) (A2N -=> X) = (0:0:0,0:0:0); |
| if ((!A1N&A2N&B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1N&!A2N&B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1N&A2N&B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1N&A2N&B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((A1N&!A2N&B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((A1N&A2N&B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and ( csi_opt_273 , B1 , B2 ) ; |
| nor ( csi_opt_274 , A1N , A2N ) ; |
| or #0.001 ( X , csi_opt_274 , csi_opt_273 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a2bb2o_1 ( X , A1N , A2N , B1 , B2 ); |
| output X ; |
| input A1N , A2N , B1 , B2 ; |
| |
| wire X , A1N , A2N , B1 ; |
| wire B2 , csi_opt_273, csi_opt_274 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((!A2N&!B1&!B2)) (A1N -=> X) = (0:0:0,0:0:0); |
| if ((!A2N&!B1&B2)) (A1N -=> X) = (0:0:0,0:0:0); |
| if ((!A2N&B1&!B2)) (A1N -=> X) = (0:0:0,0:0:0); |
| if ((!A1N&!B1&!B2)) (A2N -=> X) = (0:0:0,0:0:0); |
| if ((!A1N&!B1&B2)) (A2N -=> X) = (0:0:0,0:0:0); |
| if ((!A1N&B1&!B2)) (A2N -=> X) = (0:0:0,0:0:0); |
| if ((!A1N&A2N&B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1N&!A2N&B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1N&A2N&B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1N&A2N&B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((A1N&!A2N&B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((A1N&A2N&B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and ( csi_opt_273 , B1 , B2 ) ; |
| nor ( csi_opt_274 , A1N , A2N ) ; |
| or #0.001 ( X , csi_opt_274 , csi_opt_273 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a2bb2o_2 ( X , A1N , A2N , B1 , B2 ); |
| output X ; |
| input A1N , A2N , B1 , B2 ; |
| |
| wire X , A1N , A2N , B1 ; |
| wire B2 , csi_opt_273, csi_opt_274 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((!A2N&!B1&!B2)) (A1N -=> X) = (0:0:0,0:0:0); |
| if ((!A2N&!B1&B2)) (A1N -=> X) = (0:0:0,0:0:0); |
| if ((!A2N&B1&!B2)) (A1N -=> X) = (0:0:0,0:0:0); |
| if ((!A1N&!B1&!B2)) (A2N -=> X) = (0:0:0,0:0:0); |
| if ((!A1N&!B1&B2)) (A2N -=> X) = (0:0:0,0:0:0); |
| if ((!A1N&B1&!B2)) (A2N -=> X) = (0:0:0,0:0:0); |
| if ((!A1N&A2N&B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1N&!A2N&B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1N&A2N&B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1N&A2N&B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((A1N&!A2N&B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((A1N&A2N&B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and ( csi_opt_273 , B1 , B2 ) ; |
| nor ( csi_opt_274 , A1N , A2N ) ; |
| or #0.001 ( X , csi_opt_274 , csi_opt_273 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a2bb2o_4 ( X , A1N , A2N , B1 , B2 ); |
| output X ; |
| input A1N , A2N , B1 , B2 ; |
| |
| wire X , A1N , A2N , B1 ; |
| wire B2 , csi_opt_273, csi_opt_274 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((!A2N&!B1&!B2)) (A1N -=> X) = (0:0:0,0:0:0); |
| if ((!A2N&!B1&B2)) (A1N -=> X) = (0:0:0,0:0:0); |
| if ((!A2N&B1&!B2)) (A1N -=> X) = (0:0:0,0:0:0); |
| if ((!A1N&!B1&!B2)) (A2N -=> X) = (0:0:0,0:0:0); |
| if ((!A1N&!B1&B2)) (A2N -=> X) = (0:0:0,0:0:0); |
| if ((!A1N&B1&!B2)) (A2N -=> X) = (0:0:0,0:0:0); |
| if ((!A1N&A2N&B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1N&!A2N&B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1N&A2N&B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1N&A2N&B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((A1N&!A2N&B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((A1N&A2N&B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and ( csi_opt_273 , B1 , B2 ) ; |
| nor ( csi_opt_274 , A1N , A2N ) ; |
| or #0.001 ( X , csi_opt_274 , csi_opt_273 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a2bb2oi_0 ( Y , A1N , A2N , B1 , B2 ); |
| output Y ; |
| input A1N , A2N , B1 , B2 ; |
| |
| wire Y , A1N , A2N , B1 ; |
| wire B2 , csi_opt_273, csi_opt_274 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((!A2N&!B1&!B2)) (A1N +=> Y) = (0:0:0,0:0:0); |
| if ((!A2N&!B1&B2)) (A1N +=> Y) = (0:0:0,0:0:0); |
| if ((!A2N&B1&!B2)) (A1N +=> Y) = (0:0:0,0:0:0); |
| if ((!A1N&!B1&!B2)) (A2N +=> Y) = (0:0:0,0:0:0); |
| if ((!A1N&!B1&B2)) (A2N +=> Y) = (0:0:0,0:0:0); |
| if ((!A1N&B1&!B2)) (A2N +=> Y) = (0:0:0,0:0:0); |
| if ((!A1N&A2N&B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1N&!A2N&B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1N&A2N&B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1N&A2N&B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1N&!A2N&B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1N&A2N&B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and ( csi_opt_273 , B1 , B2 ) ; |
| nor ( csi_opt_274 , A1N , A2N ) ; |
| nor #0.001 ( Y , csi_opt_274 , csi_opt_273 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a2bb2oi_1 ( Y , A1N , A2N , B1 , B2 ); |
| output Y ; |
| input A1N , A2N , B1 , B2 ; |
| |
| wire Y , A1N , A2N , B1 ; |
| wire B2 , csi_opt_273, csi_opt_274 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((!A2N&!B1&!B2)) (A1N +=> Y) = (0:0:0,0:0:0); |
| if ((!A2N&!B1&B2)) (A1N +=> Y) = (0:0:0,0:0:0); |
| if ((!A2N&B1&!B2)) (A1N +=> Y) = (0:0:0,0:0:0); |
| if ((!A1N&!B1&!B2)) (A2N +=> Y) = (0:0:0,0:0:0); |
| if ((!A1N&!B1&B2)) (A2N +=> Y) = (0:0:0,0:0:0); |
| if ((!A1N&B1&!B2)) (A2N +=> Y) = (0:0:0,0:0:0); |
| if ((!A1N&A2N&B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1N&!A2N&B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1N&A2N&B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1N&A2N&B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1N&!A2N&B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1N&A2N&B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and ( csi_opt_273 , B1 , B2 ) ; |
| nor ( csi_opt_274 , A1N , A2N ) ; |
| nor #0.001 ( Y , csi_opt_274 , csi_opt_273 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a2bb2oi_2 ( Y , A1N , A2N , B1 , B2 ); |
| output Y ; |
| input A1N , A2N , B1 , B2 ; |
| |
| wire Y , A1N , A2N , B1 ; |
| wire B2 , csi_opt_273, csi_opt_274 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((!A2N&!B1&!B2)) (A1N +=> Y) = (0:0:0,0:0:0); |
| if ((!A2N&!B1&B2)) (A1N +=> Y) = (0:0:0,0:0:0); |
| if ((!A2N&B1&!B2)) (A1N +=> Y) = (0:0:0,0:0:0); |
| if ((!A1N&!B1&!B2)) (A2N +=> Y) = (0:0:0,0:0:0); |
| if ((!A1N&!B1&B2)) (A2N +=> Y) = (0:0:0,0:0:0); |
| if ((!A1N&B1&!B2)) (A2N +=> Y) = (0:0:0,0:0:0); |
| if ((!A1N&A2N&B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1N&!A2N&B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1N&A2N&B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1N&A2N&B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1N&!A2N&B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1N&A2N&B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and ( csi_opt_273 , B1 , B2 ) ; |
| nor ( csi_opt_274 , A1N , A2N ) ; |
| nor #0.001 ( Y , csi_opt_274 , csi_opt_273 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a2bb2oi_4 ( Y , A1N , A2N , B1 , B2 ); |
| output Y ; |
| input A1N , A2N , B1 , B2 ; |
| |
| wire Y , A1N , A2N , B1 ; |
| wire B2 , csi_opt_273, csi_opt_274 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((!A2N&!B1&!B2)) (A1N +=> Y) = (0:0:0,0:0:0); |
| if ((!A2N&!B1&B2)) (A1N +=> Y) = (0:0:0,0:0:0); |
| if ((!A2N&B1&!B2)) (A1N +=> Y) = (0:0:0,0:0:0); |
| if ((!A1N&!B1&!B2)) (A2N +=> Y) = (0:0:0,0:0:0); |
| if ((!A1N&!B1&B2)) (A2N +=> Y) = (0:0:0,0:0:0); |
| if ((!A1N&B1&!B2)) (A2N +=> Y) = (0:0:0,0:0:0); |
| if ((!A1N&A2N&B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1N&!A2N&B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1N&A2N&B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1N&A2N&B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1N&!A2N&B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1N&A2N&B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and ( csi_opt_273 , B1 , B2 ) ; |
| nor ( csi_opt_274 , A1N , A2N ) ; |
| nor #0.001 ( Y , csi_opt_274 , csi_opt_273 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a311o_0 ( X , A1 , A2 , A3 , B1 , C1 ); |
| output X ; |
| input A1 , A2 , A3 , B1 , C1 ; |
| |
| wire X , A1 , A2 , A3 ; |
| wire B1 , C1 , csi_opt_273 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 +=> X) = (0:0:0,0:0:0); |
| (A2 +=> X) = (0:0:0,0:0:0); |
| (A3 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!A3&!C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&!C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&!C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&!C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&!C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&!C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&!C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!A3&!B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&!B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&!B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&!B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&!B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&!B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&!B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and ( csi_opt_273 , A3 , A1 , A2 ) ; |
| or #0.001 ( X , csi_opt_273 , C1 , B1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a311o_1 ( X , A1 , A2 , A3 , B1 , C1 ); |
| output X ; |
| input A1 , A2 , A3 , B1 , C1 ; |
| |
| wire X , A1 , A2 , A3 ; |
| wire B1 , C1 , csi_opt_273 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 +=> X) = (0:0:0,0:0:0); |
| (A2 +=> X) = (0:0:0,0:0:0); |
| (A3 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!A3&!C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&!C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&!C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&!C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&!C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&!C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&!C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!A3&!B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&!B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&!B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&!B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&!B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&!B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&!B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and ( csi_opt_273 , A3 , A1 , A2 ) ; |
| or #0.001 ( X , csi_opt_273 , C1 , B1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a311o_2 ( X , A1 , A2 , A3 , B1 , C1 ); |
| output X ; |
| input A1 , A2 , A3 , B1 , C1 ; |
| |
| wire X , A1 , A2 , A3 ; |
| wire B1 , C1 , csi_opt_273 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 +=> X) = (0:0:0,0:0:0); |
| (A2 +=> X) = (0:0:0,0:0:0); |
| (A3 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!A3&!C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&!C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&!C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&!C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&!C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&!C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&!C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!A3&!B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&!B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&!B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&!B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&!B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&!B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&!B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and ( csi_opt_273 , A3 , A1 , A2 ) ; |
| or #0.001 ( X , csi_opt_273 , C1 , B1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a311o_4 ( X , A1 , A2 , A3 , B1 , C1 ); |
| output X ; |
| input A1 , A2 , A3 , B1 , C1 ; |
| |
| wire X , A1 , A2 , A3 ; |
| wire B1 , C1 , csi_opt_273 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 +=> X) = (0:0:0,0:0:0); |
| (A2 +=> X) = (0:0:0,0:0:0); |
| (A3 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!A3&!C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&!C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&!C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&!C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&!C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&!C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&!C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!A3&!B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&!B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&!B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&!B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&!B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&!B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&!B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and ( csi_opt_273 , A3 , A1 , A2 ) ; |
| or #0.001 ( X , csi_opt_273 , C1 , B1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a311oi_0 ( Y , A1 , A2 , A3 , B1 , C1 ); |
| output Y ; |
| input A1 , A2 , A3 , B1 , C1 ; |
| |
| wire Y , A1 , A2 , A3 ; |
| wire B1 , C1 , csi_opt_275 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 -=> Y) = (0:0:0,0:0:0); |
| (A2 -=> Y) = (0:0:0,0:0:0); |
| (A3 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!A3&!C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&!C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&!C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&!C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&!C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&!C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&!C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!A3&!B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&!B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&!B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&!B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&!B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&!B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&!B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and ( csi_opt_275 , A3 , A1 , A2 ) ; |
| nor #0.001 ( Y , csi_opt_275 , B1 , C1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a311oi_1 ( Y , A1 , A2 , A3 , B1 , C1 ); |
| output Y ; |
| input A1 , A2 , A3 , B1 , C1 ; |
| |
| wire Y , A1 , A2 , A3 ; |
| wire B1 , C1 , csi_opt_275 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 -=> Y) = (0:0:0,0:0:0); |
| (A2 -=> Y) = (0:0:0,0:0:0); |
| (A3 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!A3&!C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&!C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&!C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&!C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&!C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&!C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&!C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!A3&!B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&!B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&!B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&!B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&!B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&!B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&!B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and ( csi_opt_275 , A3 , A1 , A2 ) ; |
| nor #0.001 ( Y , csi_opt_275 , B1 , C1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a311oi_2 ( Y , A1 , A2 , A3 , B1 , C1 ); |
| output Y ; |
| input A1 , A2 , A3 , B1 , C1 ; |
| |
| wire Y , A1 , A2 , A3 ; |
| wire B1 , C1 , csi_opt_275 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 -=> Y) = (0:0:0,0:0:0); |
| (A2 -=> Y) = (0:0:0,0:0:0); |
| (A3 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!A3&!C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&!C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&!C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&!C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&!C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&!C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&!C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!A3&!B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&!B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&!B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&!B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&!B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&!B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&!B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and ( csi_opt_275 , A3 , A1 , A2 ) ; |
| nor #0.001 ( Y , csi_opt_275 , B1 , C1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a311oi_4 ( Y , A1 , A2 , A3 , B1 , C1 ); |
| output Y ; |
| input A1 , A2 , A3 , B1 , C1 ; |
| |
| wire Y , A1 , A2 , A3 ; |
| wire B1 , C1 , csi_opt_275 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 -=> Y) = (0:0:0,0:0:0); |
| (A2 -=> Y) = (0:0:0,0:0:0); |
| (A3 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!A3&!C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&!C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&!C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&!C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&!C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&!C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&!C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!A3&!B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&!B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&!B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&!B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&!B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&!B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&!B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and ( csi_opt_275 , A3 , A1 , A2 ) ; |
| nor #0.001 ( Y , csi_opt_275 , B1 , C1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a31o_0 ( X , A1 , A2 , A3 , B1 ); |
| output X ; |
| input A1 , A2 , A3 , B1 ; |
| |
| wire X , A1 , A2 , A3 ; |
| wire B1 , csi_opt_273 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 +=> X) = (0:0:0,0:0:0); |
| (A2 +=> X) = (0:0:0,0:0:0); |
| (A3 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!A3)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3)) (B1 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and ( csi_opt_273 , A3 , A1 , A2 ) ; |
| or #0.001 ( X , csi_opt_273 , B1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a31o_1 ( X , A1 , A2 , A3 , B1 ); |
| output X ; |
| input A1 , A2 , A3 , B1 ; |
| |
| wire X , A1 , A2 , A3 ; |
| wire B1 , csi_opt_273 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 +=> X) = (0:0:0,0:0:0); |
| (A2 +=> X) = (0:0:0,0:0:0); |
| (A3 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!A3)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3)) (B1 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and ( csi_opt_273 , A3 , A1 , A2 ) ; |
| or #0.001 ( X , csi_opt_273 , B1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a31o_2 ( X , A1 , A2 , A3 , B1 ); |
| output X ; |
| input A1 , A2 , A3 , B1 ; |
| |
| wire X , A1 , A2 , A3 ; |
| wire B1 , csi_opt_273 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 +=> X) = (0:0:0,0:0:0); |
| (A2 +=> X) = (0:0:0,0:0:0); |
| (A3 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!A3)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3)) (B1 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and ( csi_opt_273 , A3 , A1 , A2 ) ; |
| or #0.001 ( X , csi_opt_273 , B1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a31o_4 ( X , A1 , A2 , A3 , B1 ); |
| output X ; |
| input A1 , A2 , A3 , B1 ; |
| |
| wire X , A1 , A2 , A3 ; |
| wire B1 , csi_opt_273 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 +=> X) = (0:0:0,0:0:0); |
| (A2 +=> X) = (0:0:0,0:0:0); |
| (A3 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!A3)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3)) (B1 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and ( csi_opt_273 , A3 , A1 , A2 ) ; |
| or #0.001 ( X , csi_opt_273 , B1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a31oi_0 ( Y , A1 , A2 , A3 , B1 ); |
| output Y ; |
| input A1 , A2 , A3 , B1 ; |
| |
| wire Y , A1 , A2 , A3 ; |
| wire B1 , csi_opt_273 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 -=> Y) = (0:0:0,0:0:0); |
| (A2 -=> Y) = (0:0:0,0:0:0); |
| (A3 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!A3)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3)) (B1 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and ( csi_opt_273 , A3 , A1 , A2 ) ; |
| nor #0.001 ( Y , B1 , csi_opt_273 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a31oi_1 ( Y , A1 , A2 , A3 , B1 ); |
| output Y ; |
| input A1 , A2 , A3 , B1 ; |
| |
| wire Y , A1 , A2 , A3 ; |
| wire B1 , csi_opt_273 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 -=> Y) = (0:0:0,0:0:0); |
| (A2 -=> Y) = (0:0:0,0:0:0); |
| (A3 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!A3)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3)) (B1 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and ( csi_opt_273 , A3 , A1 , A2 ) ; |
| nor #0.001 ( Y , B1 , csi_opt_273 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a31oi_2 ( Y , A1 , A2 , A3 , B1 ); |
| output Y ; |
| input A1 , A2 , A3 , B1 ; |
| |
| wire Y , A1 , A2 , A3 ; |
| wire B1 , csi_opt_273 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 -=> Y) = (0:0:0,0:0:0); |
| (A2 -=> Y) = (0:0:0,0:0:0); |
| (A3 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!A3)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3)) (B1 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and ( csi_opt_273 , A3 , A1 , A2 ) ; |
| nor #0.001 ( Y , B1 , csi_opt_273 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a31oi_4 ( Y , A1 , A2 , A3 , B1 ); |
| output Y ; |
| input A1 , A2 , A3 , B1 ; |
| |
| wire Y , A1 , A2 , A3 ; |
| wire B1 , csi_opt_273 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 -=> Y) = (0:0:0,0:0:0); |
| (A2 -=> Y) = (0:0:0,0:0:0); |
| (A3 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!A3)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3)) (B1 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and ( csi_opt_273 , A3 , A1 , A2 ) ; |
| nor #0.001 ( Y , B1 , csi_opt_273 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a32o_0 ( X , A1 , A2 , A3 , B1 , B2 ); |
| output X ; |
| input A1 , A2 , A3 , B1 , B2 ; |
| |
| wire X , A1 , A2 , A3 ; |
| wire B1 , B2 , csi_opt_273, csi_opt_274 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((A2&A3&!B1&!B2)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((A2&A3&!B1&B2)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((A2&A3&B1&!B2)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A3&!B1&!B2)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A3&!B1&B2)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A3&B1&!B2)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!B1&!B2)) (A3 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!B1&B2)) (A3 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&B1&!B2)) (A3 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!A3&B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!A3&B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and ( csi_opt_273 , A3 , A1 , A2 ) ; |
| and ( csi_opt_274 , B1 , B2 ) ; |
| or #0.001 ( X , csi_opt_274 , csi_opt_273 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a32o_1 ( X , A1 , A2 , A3 , B1 , B2 ); |
| output X ; |
| input A1 , A2 , A3 , B1 , B2 ; |
| |
| wire X , A1 , A2 , A3 ; |
| wire B1 , B2 , csi_opt_273, csi_opt_274 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((A2&A3&!B1&!B2)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((A2&A3&!B1&B2)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((A2&A3&B1&!B2)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A3&!B1&!B2)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A3&!B1&B2)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A3&B1&!B2)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!B1&!B2)) (A3 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!B1&B2)) (A3 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&B1&!B2)) (A3 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!A3&B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!A3&B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and ( csi_opt_273 , A3 , A1 , A2 ) ; |
| and ( csi_opt_274 , B1 , B2 ) ; |
| or #0.001 ( X , csi_opt_274 , csi_opt_273 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a32o_2 ( X , A1 , A2 , A3 , B1 , B2 ); |
| output X ; |
| input A1 , A2 , A3 , B1 , B2 ; |
| |
| wire X , A1 , A2 , A3 ; |
| wire B1 , B2 , csi_opt_273, csi_opt_274 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((A2&A3&!B1&!B2)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((A2&A3&!B1&B2)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((A2&A3&B1&!B2)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A3&!B1&!B2)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A3&!B1&B2)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A3&B1&!B2)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!B1&!B2)) (A3 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!B1&B2)) (A3 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&B1&!B2)) (A3 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!A3&B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!A3&B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and ( csi_opt_273 , A3 , A1 , A2 ) ; |
| and ( csi_opt_274 , B1 , B2 ) ; |
| or #0.001 ( X , csi_opt_274 , csi_opt_273 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a32o_4 ( X , A1 , A2 , A3 , B1 , B2 ); |
| output X ; |
| input A1 , A2 , A3 , B1 , B2 ; |
| |
| wire X , A1 , A2 , A3 ; |
| wire B1 , B2 , csi_opt_273, csi_opt_274 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((A2&A3&!B1&!B2)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((A2&A3&!B1&B2)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((A2&A3&B1&!B2)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A3&!B1&!B2)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A3&!B1&B2)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A3&B1&!B2)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!B1&!B2)) (A3 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!B1&B2)) (A3 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&B1&!B2)) (A3 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!A3&B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!A3&B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and ( csi_opt_273 , A3 , A1 , A2 ) ; |
| and ( csi_opt_274 , B1 , B2 ) ; |
| or #0.001 ( X , csi_opt_274 , csi_opt_273 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a32oi_0 ( Y , A1 , A2 , A3 , B1 , B2 ); |
| output Y ; |
| input A1 , A2 , A3 , B1 , B2 ; |
| |
| wire Y , A1 , A2 , A3 ; |
| wire B1 , B2 , csi_opt_304, csi_opt_302 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((A2&A3&!B1&!B2)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((A2&A3&!B1&B2)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((A2&A3&B1&!B2)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A3&!B1&!B2)) (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A3&!B1&B2)) (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A3&B1&!B2)) (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!B1&!B2)) (A3 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!B1&B2)) (A3 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&B1&!B2)) (A3 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!A3&B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!A3&B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nand ( csi_opt_304 , A2 , A1 , A3 ) ; |
| nand ( csi_opt_302 , B2 , B1 ) ; |
| and #0.001 ( Y , csi_opt_304 , csi_opt_302 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a32oi_1 ( Y , A1 , A2 , A3 , B1 , B2 ); |
| output Y ; |
| input A1 , A2 , A3 , B1 , B2 ; |
| |
| wire Y , A1 , A2 , A3 ; |
| wire B1 , B2 , csi_opt_304, csi_opt_302 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((A2&A3&!B1&!B2)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((A2&A3&!B1&B2)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((A2&A3&B1&!B2)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A3&!B1&!B2)) (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A3&!B1&B2)) (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A3&B1&!B2)) (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!B1&!B2)) (A3 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!B1&B2)) (A3 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&B1&!B2)) (A3 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!A3&B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!A3&B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nand ( csi_opt_304 , A2 , A1 , A3 ) ; |
| nand ( csi_opt_302 , B2 , B1 ) ; |
| and #0.001 ( Y , csi_opt_304 , csi_opt_302 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a32oi_2 ( Y , A1 , A2 , A3 , B1 , B2 ); |
| output Y ; |
| input A1 , A2 , A3 , B1 , B2 ; |
| |
| wire Y , A1 , A2 , A3 ; |
| wire B1 , B2 , csi_opt_304, csi_opt_302 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((A2&A3&!B1&!B2)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((A2&A3&!B1&B2)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((A2&A3&B1&!B2)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A3&!B1&!B2)) (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A3&!B1&B2)) (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A3&B1&!B2)) (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!B1&!B2)) (A3 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!B1&B2)) (A3 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&B1&!B2)) (A3 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!A3&B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!A3&B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nand ( csi_opt_304 , A2 , A1 , A3 ) ; |
| nand ( csi_opt_302 , B2 , B1 ) ; |
| and #0.001 ( Y , csi_opt_304 , csi_opt_302 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a32oi_4 ( Y , A1 , A2 , A3 , B1 , B2 ); |
| output Y ; |
| input A1 , A2 , A3 , B1 , B2 ; |
| |
| wire Y , A1 , A2 , A3 ; |
| wire B1 , B2 , csi_opt_304, csi_opt_302 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((A2&A3&!B1&!B2)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((A2&A3&!B1&B2)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((A2&A3&B1&!B2)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A3&!B1&!B2)) (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A3&!B1&B2)) (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A3&B1&!B2)) (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!B1&!B2)) (A3 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!B1&B2)) (A3 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&B1&!B2)) (A3 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!A3&B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!A3&B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nand ( csi_opt_304 , A2 , A1 , A3 ) ; |
| nand ( csi_opt_302 , B2 , B1 ) ; |
| and #0.001 ( Y , csi_opt_304 , csi_opt_302 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a41o_0 ( X , A1 , A2 , A3 , A4 , B1 ); |
| output X ; |
| input A1 , A2 , A3 , A4 , B1 ; |
| |
| wire X , A1 , A2 , A3 ; |
| wire A4 , B1 , csi_opt_273 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 +=> X) = (0:0:0,0:0:0); |
| (A2 +=> X) = (0:0:0,0:0:0); |
| (A3 +=> X) = (0:0:0,0:0:0); |
| (A4 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!A3&A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and ( csi_opt_273 , A1 , A2 , A3 , A4 ) ; |
| or #0.001 ( X , csi_opt_273 , B1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a41o_1 ( X , A1 , A2 , A3 , A4 , B1 ); |
| output X ; |
| input A1 , A2 , A3 , A4 , B1 ; |
| |
| wire X , A1 , A2 , A3 ; |
| wire A4 , B1 , csi_opt_273 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 +=> X) = (0:0:0,0:0:0); |
| (A2 +=> X) = (0:0:0,0:0:0); |
| (A3 +=> X) = (0:0:0,0:0:0); |
| (A4 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!A3&A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and ( csi_opt_273 , A1 , A2 , A3 , A4 ) ; |
| or #0.001 ( X , csi_opt_273 , B1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a41o_2 ( X , A1 , A2 , A3 , A4 , B1 ); |
| output X ; |
| input A1 , A2 , A3 , A4 , B1 ; |
| |
| wire X , A1 , A2 , A3 ; |
| wire A4 , B1 , csi_opt_273 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 +=> X) = (0:0:0,0:0:0); |
| (A2 +=> X) = (0:0:0,0:0:0); |
| (A3 +=> X) = (0:0:0,0:0:0); |
| (A4 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!A3&A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and ( csi_opt_273 , A1 , A2 , A3 , A4 ) ; |
| or #0.001 ( X , csi_opt_273 , B1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a41o_4 ( X , A1 , A2 , A3 , A4 , B1 ); |
| output X ; |
| input A1 , A2 , A3 , A4 , B1 ; |
| |
| wire X , A1 , A2 , A3 ; |
| wire A4 , B1 , csi_opt_273 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 +=> X) = (0:0:0,0:0:0); |
| (A2 +=> X) = (0:0:0,0:0:0); |
| (A3 +=> X) = (0:0:0,0:0:0); |
| (A4 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!A3&A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and ( csi_opt_273 , A1 , A2 , A3 , A4 ) ; |
| or #0.001 ( X , csi_opt_273 , B1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a41oi_0 ( Y , A1 , A2 , A3 , A4 , B1 ); |
| output Y ; |
| input A1 , A2 , A3 , A4 , B1 ; |
| |
| wire Y , A1 , A2 , A3 ; |
| wire A4 , B1 , csi_opt_273 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 -=> Y) = (0:0:0,0:0:0); |
| (A2 -=> Y) = (0:0:0,0:0:0); |
| (A3 -=> Y) = (0:0:0,0:0:0); |
| (A4 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!A3&!A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!A3&A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&!A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&!A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&!A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&!A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&!A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&!A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&A3&!A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and ( csi_opt_273 , A1 , A2 , A3 , A4 ) ; |
| nor #0.001 ( Y , B1 , csi_opt_273 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a41oi_1 ( Y , A1 , A2 , A3 , A4 , B1 ); |
| output Y ; |
| input A1 , A2 , A3 , A4 , B1 ; |
| |
| wire Y , A1 , A2 , A3 ; |
| wire A4 , B1 , csi_opt_273 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 -=> Y) = (0:0:0,0:0:0); |
| (A2 -=> Y) = (0:0:0,0:0:0); |
| (A3 -=> Y) = (0:0:0,0:0:0); |
| (A4 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!A3&!A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!A3&A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&!A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&!A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&!A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&!A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&!A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&!A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&A3&!A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and ( csi_opt_273 , A1 , A2 , A3 , A4 ) ; |
| nor #0.001 ( Y , B1 , csi_opt_273 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a41oi_2 ( Y , A1 , A2 , A3 , A4 , B1 ); |
| output Y ; |
| input A1 , A2 , A3 , A4 , B1 ; |
| |
| wire Y , A1 , A2 , A3 ; |
| wire A4 , B1 , csi_opt_273 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 -=> Y) = (0:0:0,0:0:0); |
| (A2 -=> Y) = (0:0:0,0:0:0); |
| (A3 -=> Y) = (0:0:0,0:0:0); |
| (A4 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!A3&!A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!A3&A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&!A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&!A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&!A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&!A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&!A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&!A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&A3&!A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and ( csi_opt_273 , A1 , A2 , A3 , A4 ) ; |
| nor #0.001 ( Y , B1 , csi_opt_273 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_a41oi_4 ( Y , A1 , A2 , A3 , A4 , B1 ); |
| output Y ; |
| input A1 , A2 , A3 , A4 , B1 ; |
| |
| wire Y , A1 , A2 , A3 ; |
| wire A4 , B1 , csi_opt_273 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 -=> Y) = (0:0:0,0:0:0); |
| (A2 -=> Y) = (0:0:0,0:0:0); |
| (A3 -=> Y) = (0:0:0,0:0:0); |
| (A4 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!A3&!A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!A3&A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&!A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&!A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&!A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&!A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&!A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&!A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&A3&!A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and ( csi_opt_273 , A1 , A2 , A3 , A4 ) ; |
| nor #0.001 ( Y , B1 , csi_opt_273 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_and2_0 ( X , A , B ); |
| output X ; |
| input A , B ; |
| |
| wire X , A , B ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X) = (0:0:0,0:0:0); |
| (B +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and #0.001 ( X , A , B ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_and2_1 ( X , A , B ); |
| output X ; |
| input A , B ; |
| |
| wire X , A , B ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X) = (0:0:0,0:0:0); |
| (B +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and #0.001 ( X , A , B ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_and2_2 ( X , A , B ); |
| output X ; |
| input A , B ; |
| |
| wire X , A , B ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X) = (0:0:0,0:0:0); |
| (B +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and #0.001 ( X , A , B ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_and2_4 ( X , A , B ); |
| output X ; |
| input A , B ; |
| |
| wire X , A , B ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X) = (0:0:0,0:0:0); |
| (B +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and #0.001 ( X , A , B ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_and2b_1 ( X , AN , B ); |
| output X ; |
| input AN , B ; |
| |
| wire X , AN , B , csi_opt_276 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (AN -=> X) = (0:0:0,0:0:0); |
| (B +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| not ( csi_opt_276 , AN ) ; |
| and #0.001 ( X , csi_opt_276 , B ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_and2b_2 ( X , AN , B ); |
| output X ; |
| input AN , B ; |
| |
| wire X , AN , B , csi_opt_276 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (AN -=> X) = (0:0:0,0:0:0); |
| (B +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| not ( csi_opt_276 , AN ) ; |
| and #0.001 ( X , csi_opt_276 , B ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_and2b_4 ( X , AN , B ); |
| output X ; |
| input AN , B ; |
| |
| wire X , AN , B , csi_opt_276 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (AN -=> X) = (0:0:0,0:0:0); |
| (B +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| not ( csi_opt_276 , AN ) ; |
| and #0.001 ( X , csi_opt_276 , B ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_and3_0 ( X , A , B , C ); |
| output X ; |
| input A , B , C ; |
| |
| wire X , A , B , C ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X) = (0:0:0,0:0:0); |
| (B +=> X) = (0:0:0,0:0:0); |
| (C +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and #0.001 ( X , C , A , B ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_and3_1 ( X , A , B , C ); |
| output X ; |
| input A , B , C ; |
| |
| wire X , A , B , C ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X) = (0:0:0,0:0:0); |
| (B +=> X) = (0:0:0,0:0:0); |
| (C +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and #0.001 ( X , C , A , B ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_and3_2 ( X , A , B , C ); |
| output X ; |
| input A , B , C ; |
| |
| wire X , A , B , C ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X) = (0:0:0,0:0:0); |
| (B +=> X) = (0:0:0,0:0:0); |
| (C +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and #0.001 ( X , C , A , B ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_and3_4 ( X , A , B , C ); |
| output X ; |
| input A , B , C ; |
| |
| wire X , A , B , C ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X) = (0:0:0,0:0:0); |
| (B +=> X) = (0:0:0,0:0:0); |
| (C +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and #0.001 ( X , C , A , B ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_and3b_1 ( X , AN , B , C ); |
| output X ; |
| input AN , B , C ; |
| |
| wire X , AN , B , C ; |
| wire csi_opt_280 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (AN -=> X) = (0:0:0,0:0:0); |
| (B +=> X) = (0:0:0,0:0:0); |
| (C +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| not ( csi_opt_280 , AN ) ; |
| and #0.001 ( X , C , csi_opt_280 , B ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_and3b_2 ( X , AN , B , C ); |
| output X ; |
| input AN , B , C ; |
| |
| wire X , AN , B , C ; |
| wire csi_opt_280 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (AN -=> X) = (0:0:0,0:0:0); |
| (B +=> X) = (0:0:0,0:0:0); |
| (C +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| not ( csi_opt_280 , AN ) ; |
| and #0.001 ( X , C , csi_opt_280 , B ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_and3b_4 ( X , AN , B , C ); |
| output X ; |
| input AN , B , C ; |
| |
| wire X , AN , B , C ; |
| wire csi_opt_280 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (AN -=> X) = (0:0:0,0:0:0); |
| (B +=> X) = (0:0:0,0:0:0); |
| (C +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| not ( csi_opt_280 , AN ) ; |
| and #0.001 ( X , C , csi_opt_280 , B ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_and4_0 ( X , A , B , C , D ); |
| output X ; |
| input A , B , C , D ; |
| |
| wire X , A , B , C ; |
| wire D ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X) = (0:0:0,0:0:0); |
| (B +=> X) = (0:0:0,0:0:0); |
| (C +=> X) = (0:0:0,0:0:0); |
| (D +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and #0.001 ( X , A , B , C , D ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_and4_1 ( X , A , B , C , D ); |
| output X ; |
| input A , B , C , D ; |
| |
| wire X , A , B , C ; |
| wire D ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X) = (0:0:0,0:0:0); |
| (B +=> X) = (0:0:0,0:0:0); |
| (C +=> X) = (0:0:0,0:0:0); |
| (D +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and #0.001 ( X , A , B , C , D ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_and4_2 ( X , A , B , C , D ); |
| output X ; |
| input A , B , C , D ; |
| |
| wire X , A , B , C ; |
| wire D ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X) = (0:0:0,0:0:0); |
| (B +=> X) = (0:0:0,0:0:0); |
| (C +=> X) = (0:0:0,0:0:0); |
| (D +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and #0.001 ( X , A , B , C , D ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_and4_4 ( X , A , B , C , D ); |
| output X ; |
| input A , B , C , D ; |
| |
| wire X , A , B , C ; |
| wire D ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X) = (0:0:0,0:0:0); |
| (B +=> X) = (0:0:0,0:0:0); |
| (C +=> X) = (0:0:0,0:0:0); |
| (D +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and #0.001 ( X , A , B , C , D ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_and4b_1 ( X , AN , B , C , D ); |
| output X ; |
| input AN , B , C , D ; |
| |
| wire X , AN , B , C ; |
| wire D , csi_opt_284 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (AN -=> X) = (0:0:0,0:0:0); |
| (B +=> X) = (0:0:0,0:0:0); |
| (C +=> X) = (0:0:0,0:0:0); |
| (D +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| not ( csi_opt_284 , AN ) ; |
| and #0.001 ( X , csi_opt_284 , B , C , D ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_and4b_2 ( X , AN , B , C , D ); |
| output X ; |
| input AN , B , C , D ; |
| |
| wire X , AN , B , C ; |
| wire D , csi_opt_284 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (AN -=> X) = (0:0:0,0:0:0); |
| (B +=> X) = (0:0:0,0:0:0); |
| (C +=> X) = (0:0:0,0:0:0); |
| (D +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| not ( csi_opt_284 , AN ) ; |
| and #0.001 ( X , csi_opt_284 , B , C , D ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_and4b_4 ( X , AN , B , C , D ); |
| output X ; |
| input AN , B , C , D ; |
| |
| wire X , AN , B , C ; |
| wire D , csi_opt_284 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (AN -=> X) = (0:0:0,0:0:0); |
| (B +=> X) = (0:0:0,0:0:0); |
| (C +=> X) = (0:0:0,0:0:0); |
| (D +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| not ( csi_opt_284 , AN ) ; |
| and #0.001 ( X , csi_opt_284 , B , C , D ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_and4bb_1 ( X , AN , BN , C , D ); |
| output X ; |
| input AN , BN , C , D ; |
| |
| wire X , AN , BN , C ; |
| wire D , csi_opt_278 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (AN -=> X) = (0:0:0,0:0:0); |
| (BN -=> X) = (0:0:0,0:0:0); |
| (C +=> X) = (0:0:0,0:0:0); |
| (D +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nor ( csi_opt_278 , AN , BN ) ; |
| and #0.001 ( X , csi_opt_278 , C , D ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_and4bb_2 ( X , AN , BN , C , D ); |
| output X ; |
| input AN , BN , C , D ; |
| |
| wire X , AN , BN , C ; |
| wire D , csi_opt_278 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (AN -=> X) = (0:0:0,0:0:0); |
| (BN -=> X) = (0:0:0,0:0:0); |
| (C +=> X) = (0:0:0,0:0:0); |
| (D +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nor ( csi_opt_278 , AN , BN ) ; |
| and #0.001 ( X , csi_opt_278 , C , D ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_and4bb_4 ( X , AN , BN , C , D ); |
| output X ; |
| input AN , BN , C , D ; |
| |
| wire X , AN , BN , C ; |
| wire D , csi_opt_278 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (AN -=> X) = (0:0:0,0:0:0); |
| (BN -=> X) = (0:0:0,0:0:0); |
| (C +=> X) = (0:0:0,0:0:0); |
| (D +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nor ( csi_opt_278 , AN , BN ) ; |
| and #0.001 ( X , csi_opt_278 , C , D ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_buf_0 ( X , A ); |
| output X ; |
| input A ; |
| |
| wire X , A ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X ) = (0:0:0,0:0:0); // delays are tris,tfall |
| endspecify |
| `endif |
| |
| buf #0.001 ( X , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_buf_1 ( X , A ); |
| output X ; |
| input A ; |
| |
| wire X , A ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X ) = (0:0:0,0:0:0); // delays are tris,tfall |
| endspecify |
| `endif |
| |
| buf #0.001 ( X , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_buf_16 ( X , A ); |
| output X ; |
| input A ; |
| |
| wire X , A ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X ) = (0:0:0,0:0:0); // delays are tris,tfall |
| endspecify |
| `endif |
| |
| buf #0.001 ( X , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_buf_2 ( X , A ); |
| output X ; |
| input A ; |
| |
| wire X , A ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X ) = (0:0:0,0:0:0); // delays are tris,tfall |
| endspecify |
| `endif |
| |
| buf #0.001 ( X , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_buf_4 ( X , A ); |
| output X ; |
| input A ; |
| |
| wire X , A ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X ) = (0:0:0,0:0:0); // delays are tris,tfall |
| endspecify |
| `endif |
| |
| buf #0.001 ( X , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_buf_8 ( X , A ); |
| output X ; |
| input A ; |
| |
| wire X , A ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X ) = (0:0:0,0:0:0); // delays are tris,tfall |
| endspecify |
| `endif |
| |
| buf #0.001 ( X , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_bufbuf_16 ( X , A ); |
| output X ; |
| input A ; |
| |
| wire X , A ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X ) = (0:0:0,0:0:0); // delays are tris,tfall |
| endspecify |
| `endif |
| |
| buf #0.001 ( X , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_bufbuf_8 ( X , A ); |
| output X ; |
| input A ; |
| |
| wire X , A ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X ) = (0:0:0,0:0:0); // delays are tris,tfall |
| endspecify |
| `endif |
| |
| buf #0.001 ( X , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_bufinv_16 ( Y , A ); |
| output Y ; |
| input A ; |
| |
| wire Y , A ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A -=> Y ) = (0:0:0,0:0:0); // delays are tris,tfall |
| endspecify |
| `endif |
| |
| not #0.001 ( Y , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_bufinv_8 ( Y , A ); |
| output Y ; |
| input A ; |
| |
| wire Y , A ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A -=> Y ) = (0:0:0,0:0:0); // delays are tris,tfall |
| endspecify |
| `endif |
| |
| not #0.001 ( Y , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_buflp_0 ( X , A ); |
| output X ; |
| input A ; |
| |
| wire X , A ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X ) = (0:0:0,0:0:0); // delays are tris,tfall |
| endspecify |
| `endif |
| |
| buf #0.001 ( X , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_buflp_1 ( X , A ); |
| output X ; |
| input A ; |
| |
| wire X , A ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X ) = (0:0:0,0:0:0); // delays are tris,tfall |
| endspecify |
| `endif |
| |
| buf #0.001 ( X , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_buflp_2 ( X , A ); |
| output X ; |
| input A ; |
| |
| wire X , A ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X ) = (0:0:0,0:0:0); // delays are tris,tfall |
| endspecify |
| `endif |
| |
| buf #0.001 ( X , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_buflp_4 ( X , A ); |
| output X ; |
| input A ; |
| |
| wire X , A ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X ) = (0:0:0,0:0:0); // delays are tris,tfall |
| endspecify |
| `endif |
| |
| buf #0.001 ( X , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_buflp_8 ( X , A ); |
| output X ; |
| input A ; |
| |
| wire X , A ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X ) = (0:0:0,0:0:0); // delays are tris,tfall |
| endspecify |
| `endif |
| |
| buf #0.001 ( X , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_busdriver2_20 ( Z , A , TEB ); |
| |
| output Z ; |
| input A , TEB ; |
| |
| bufif0 #0.001 (Z , A , TEB ); |
| |
| `ifdef functional |
| `else |
| specify |
| if( ~TEB ) (A +=> Z ) = (0.000:0.000:0.000,0.000:0.000:0.000); |
| (TEB => Z ) = (0.000:0.000:0.000,0.000:0.000:0.000,0.000:0.000:0.000,0.000:0.000:0.000,0.000:0.000:0.000,0.000:0.000:0.000); // delays are t01,t10,t0Z,tZ1,t1Z,tZ0 |
| endspecify |
| `endif |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_busdriver_20 ( Z , A , TEB ); |
| |
| output Z ; |
| input A , TEB ; |
| |
| bufif0 #0.001 (Z , A , TEB ); |
| |
| `ifdef functional |
| `else |
| specify |
| if( ~TEB ) (A +=> Z ) = (0.000:0.000:0.000,0.000:0.000:0.000); |
| (TEB => Z ) = (0.000:0.000:0.000,0.000:0.000:0.000,0.000:0.000:0.000,0.000:0.000:0.000,0.000:0.000:0.000,0.000:0.000:0.000); // delays are t01,t10,t0Z,tZ1,t1Z,tZ0 |
| endspecify |
| `endif |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_bushold0_1 ( X , RESET ); |
| inout X ; |
| input RESET ; |
| |
| wire xb ; |
| |
| not #0.001 (xb,X); |
| nor (weak0,weak1) (X,xb,RESET); |
| `ifdef functional |
| `else |
| specify |
| if ((X)) ( RESET -=> X ) = (0:0:0); // delays are tris |
| endspecify |
| `endif |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_bushold_1 ( X , RESET ); |
| inout X ; |
| input RESET ; |
| |
| wire xb ; |
| |
| nor #0.001 (xb,X,RESET); |
| not (weak0,weak1) (X,xb); |
| `ifdef functional |
| `else |
| specify |
| if ((!X)) ( RESET +=> X ) = (0:0:0); // delays are tris |
| endspecify |
| `endif |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_busreceiver_0 ( X , A ); |
| output X ; |
| input A ; |
| |
| wire X , A ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X ) = (0:0:0,0:0:0); // delays are tris,tfall |
| endspecify |
| `endif |
| |
| buf #0.001 ( X , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_busreceiver_1 ( X , A ); |
| output X ; |
| input A ; |
| |
| wire X , A ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X ) = (0:0:0,0:0:0); // delays are tris,tfall |
| endspecify |
| `endif |
| |
| buf #0.001 ( X , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_clkbuf_0 ( X , A ); |
| output X ; |
| input A ; |
| |
| wire X , A ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X ) = (0:0:0,0:0:0); // delays are tris,tfall |
| endspecify |
| `endif |
| |
| buf #0.001 ( X , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_clkbuf_1 ( X , A ); |
| output X ; |
| input A ; |
| |
| wire X , A ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X ) = (0:0:0,0:0:0); // delays are tris,tfall |
| endspecify |
| `endif |
| |
| buf #0.001 ( X , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_clkbuf_16 ( X , A ); |
| output X ; |
| input A ; |
| |
| wire X , A ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X ) = (0:0:0,0:0:0); // delays are tris,tfall |
| endspecify |
| `endif |
| |
| buf #0.001 ( X , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_clkbuf_2 ( X , A ); |
| output X ; |
| input A ; |
| |
| wire X , A ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X ) = (0:0:0,0:0:0); // delays are tris,tfall |
| endspecify |
| `endif |
| |
| buf #0.001 ( X , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_clkbuf_4 ( X , A ); |
| output X ; |
| input A ; |
| |
| wire X , A ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X ) = (0:0:0,0:0:0); // delays are tris,tfall |
| endspecify |
| `endif |
| |
| buf #0.001 ( X , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_clkbuf_8 ( X , A ); |
| output X ; |
| input A ; |
| |
| wire X , A ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X ) = (0:0:0,0:0:0); // delays are tris,tfall |
| endspecify |
| `endif |
| |
| buf #0.001 ( X , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_clkbuflp_16 ( X , A ); |
| output X ; |
| input A ; |
| |
| wire X , A ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X ) = (0:0:0,0:0:0); // delays are tris,tfall |
| endspecify |
| `endif |
| |
| buf #0.001 ( X , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_clkbuflp_2 ( X , A ); |
| output X ; |
| input A ; |
| |
| wire X , A ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X ) = (0:0:0,0:0:0); // delays are tris,tfall |
| endspecify |
| `endif |
| |
| buf #0.001 ( X , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_clkbuflp_4 ( X , A ); |
| output X ; |
| input A ; |
| |
| wire X , A ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X ) = (0:0:0,0:0:0); // delays are tris,tfall |
| endspecify |
| `endif |
| |
| buf #0.001 ( X , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_clkbuflp_8 ( X , A ); |
| output X ; |
| input A ; |
| |
| wire X , A ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X ) = (0:0:0,0:0:0); // delays are tris,tfall |
| endspecify |
| `endif |
| |
| buf #0.001 ( X , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_clkdlybuf4s15_1 ( X , A ); |
| output X ; |
| input A ; |
| |
| wire X , A ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X ) = (0:0:0,0:0:0); // delays are tris,tfall |
| endspecify |
| `endif |
| |
| buf #0.001 ( X , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_clkdlybuf4s15_2 ( X , A ); |
| output X ; |
| input A ; |
| |
| wire X , A ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X ) = (0:0:0,0:0:0); // delays are tris,tfall |
| endspecify |
| `endif |
| |
| buf #0.001 ( X , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_clkdlybuf4s18_1 ( X , A ); |
| output X ; |
| input A ; |
| |
| wire X , A ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X ) = (0:0:0,0:0:0); // delays are tris,tfall |
| endspecify |
| `endif |
| |
| buf #0.001 ( X , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_clkdlybuf4s18_2 ( X , A ); |
| output X ; |
| input A ; |
| |
| wire X , A ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X ) = (0:0:0,0:0:0); // delays are tris,tfall |
| endspecify |
| `endif |
| |
| buf #0.001 ( X , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_clkdlybuf4s25_1 ( X , A ); |
| output X ; |
| input A ; |
| |
| wire X , A ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X ) = (0:0:0,0:0:0); // delays are tris,tfall |
| endspecify |
| `endif |
| |
| buf #0.001 ( X , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_clkdlybuf4s25_2 ( X , A ); |
| output X ; |
| input A ; |
| |
| wire X , A ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X ) = (0:0:0,0:0:0); // delays are tris,tfall |
| endspecify |
| `endif |
| |
| buf #0.001 ( X , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_clkdlybuf4s50_1 ( X , A ); |
| output X ; |
| input A ; |
| |
| wire X , A ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X ) = (0:0:0,0:0:0); // delays are tris,tfall |
| endspecify |
| `endif |
| |
| buf #0.001 ( X , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_clkdlybuf4s50_2 ( X , A ); |
| output X ; |
| input A ; |
| |
| wire X , A ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X ) = (0:0:0,0:0:0); // delays are tris,tfall |
| endspecify |
| `endif |
| |
| buf #0.001 ( X , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_clkinv_0 ( Y , A ); |
| output Y ; |
| input A ; |
| |
| wire Y , A ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A -=> Y ) = (0:0:0,0:0:0); // delays are tris,tfall |
| endspecify |
| `endif |
| |
| not #0.001 ( Y , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_clkinv_1 ( Y , A ); |
| output Y ; |
| input A ; |
| |
| wire Y , A ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A -=> Y ) = (0:0:0,0:0:0); // delays are tris,tfall |
| endspecify |
| `endif |
| |
| not #0.001 ( Y , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_clkinv_16 ( Y , A ); |
| output Y ; |
| input A ; |
| |
| wire Y , A ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A -=> Y ) = (0:0:0,0:0:0); // delays are tris,tfall |
| endspecify |
| `endif |
| |
| not #0.001 ( Y , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_clkinv_2 ( Y , A ); |
| output Y ; |
| input A ; |
| |
| wire Y , A ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A -=> Y ) = (0:0:0,0:0:0); // delays are tris,tfall |
| endspecify |
| `endif |
| |
| not #0.001 ( Y , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_clkinv_4 ( Y , A ); |
| output Y ; |
| input A ; |
| |
| wire Y , A ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A -=> Y ) = (0:0:0,0:0:0); // delays are tris,tfall |
| endspecify |
| `endif |
| |
| not #0.001 ( Y , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_clkinv_8 ( Y , A ); |
| output Y ; |
| input A ; |
| |
| wire Y , A ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A -=> Y ) = (0:0:0,0:0:0); // delays are tris,tfall |
| endspecify |
| `endif |
| |
| not #0.001 ( Y , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_clkinvlp_16 ( Y , A ); |
| output Y ; |
| input A ; |
| |
| wire Y , A ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A -=> Y ) = (0:0:0,0:0:0); // delays are tris,tfall |
| endspecify |
| `endif |
| |
| not #0.001 ( Y , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_clkinvlp_2 ( Y , A ); |
| output Y ; |
| input A ; |
| |
| wire Y , A ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A -=> Y ) = (0:0:0,0:0:0); // delays are tris,tfall |
| endspecify |
| `endif |
| |
| not #0.001 ( Y , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_clkinvlp_4 ( Y , A ); |
| output Y ; |
| input A ; |
| |
| wire Y , A ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A -=> Y ) = (0:0:0,0:0:0); // delays are tris,tfall |
| endspecify |
| `endif |
| |
| not #0.001 ( Y , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_clkinvlp_8 ( Y , A ); |
| output Y ; |
| input A ; |
| |
| wire Y , A ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A -=> Y ) = (0:0:0,0:0:0); // delays are tris,tfall |
| endspecify |
| `endif |
| |
| not #0.001 ( Y , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_conb_0 (HI, LO); |
| output HI, LO; |
| |
| pullup (HI); |
| pulldown (LO); |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_conb_1 (HI, LO); |
| output HI, LO; |
| |
| pullup (HI); |
| pulldown (LO); |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_dfbbn_1 (Q, QN, D, CLKN, SETB, RESETB); |
| output Q,QN; |
| input D,CLKN,SETB,RESETB; |
| |
| wire reset, set, clk, buf_Q; |
| wire CLKN_delayed, RESETB_delayed, SETB_delayed; |
| |
| `ifdef functional |
| not (reset,RESETB); |
| not (set,SETB); |
| not (clk, CLKN); |
| U_DFB_SETDOM #1 (buf_Q,set,reset,clk,D); |
| `else |
| reg notifier; |
| |
| wire COND0, COND1, CONDB; |
| assign COND0 = (RESETB_delayed === 1'b1); |
| assign COND1 = (SETB_delayed === 1'b1); |
| assign CONDB = (COND0 & COND1); |
| |
| not (reset,RESETB_delayed); |
| not (set,SETB_delayed); |
| not (clk, CLKN_delayed); |
| U_DFB_SETDOM_notify #0.001 (buf_Q,set,reset,clk,D_delayed,notifier); |
| |
| specify |
| (negedge RESETB => (Q +: RESETB ) ) = 0:0:0; // delay is tfall |
| (negedge RESETB => (QN -: RESETB ) ) = 0:0:0; // delay is tris |
| |
| (SETB => (Q -: SETB ) ) = (0:0:0,0:0:0); // delay is tris,tfall |
| (SETB => (QN +: SETB ) ) = (0:0:0,0:0:0); // delay is tris,tfall |
| |
| (negedge CLKN => (Q +: D ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| (negedge CLKN => (QN -: D ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| |
| $width (negedge CLKN &&& CONDB , 0:0:0, 0, notifier); |
| $width (posedge CLKN &&& CONDB , 0:0:0, 0, notifier); |
| $width (negedge SETB , 0.5, 0, notifier); |
| $width (negedge RESETB , 0.5, 0, notifier); |
| |
| $recrem ( posedge SETB , negedge CLKN , 0:0:0, 0:0:0, notifier , , COND0, SETB_delayed , CLKN_delayed ) ; |
| $recovery ( posedge SETB , negedge CLKN , 0:0:0, 0:0:0, notifier , , COND0, SETB_delayed , CLKN_delayed ) ; |
| $hold ( negedge CLKN , posedge SETB , 0:0:0, notifier ) ; |
| $recrem ( posedge RESETB , negedge CLKN , 0:0:0, 0:0:0, notifier , , COND1, RESETB_delayed , CLKN_delayed ) ; |
| $recovery ( posedge RESETB , negedge CLKN , 0:0:0, 0:0:0, notifier , , COND1, RESETB_delayed , CLKN_delayed ) ; |
| $hold ( negedge CLKN , posedge RESETB , 0:0:0, notifier ) ; |
| |
| $setuphold ( negedge CLKN , posedge D , 0:0:0, 0:0:0, notifier , , CONDB , CLKN_delayed , D_delayed ) ; |
| $setuphold ( negedge CLKN , negedge D , 0:0:0, 0:0:0, notifier , , CONDB , CLKN_delayed , D_delayed ) ; |
| |
| |
| $hold (posedge SETB, posedge RESETB, 3.0 , notifier); //arbitrary, uncharacterized value to |
| //flag possible state error |
| |
| $hold (posedge RESETB, posedge SETB, 3.0 , notifier); //arbitrary, uncharacterized value to |
| //flag possible state error |
| |
| endspecify |
| |
| |
| `endif |
| buf (Q,buf_Q); |
| not (QN,buf_Q); |
| |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_dfbbn_2 (Q, QN, D, CLKN, SETB, RESETB); |
| output Q,QN; |
| input D,CLKN,SETB,RESETB; |
| |
| wire reset, set, clk, buf_Q; |
| wire CLKN_delayed, RESETB_delayed, SETB_delayed; |
| |
| `ifdef functional |
| not (reset,RESETB); |
| not (set,SETB); |
| not (clk, CLKN); |
| U_DFB_SETDOM #1 (buf_Q,set,reset,clk,D); |
| `else |
| reg notifier; |
| |
| wire COND0, COND1, CONDB; |
| assign COND0 = (RESETB_delayed === 1'b1); |
| assign COND1 = (SETB_delayed === 1'b1); |
| assign CONDB = (COND0 & COND1); |
| |
| not (reset,RESETB_delayed); |
| not (set,SETB_delayed); |
| not (clk, CLKN_delayed); |
| U_DFB_SETDOM_notify #0.001 (buf_Q,set,reset,clk,D_delayed,notifier); |
| |
| specify |
| (negedge RESETB => (Q +: RESETB ) ) = 0:0:0; // delay is tfall |
| (negedge RESETB => (QN -: RESETB ) ) = 0:0:0; // delay is tris |
| |
| (SETB => (Q -: SETB ) ) = (0:0:0,0:0:0); // delay is tris,tfall |
| (SETB => (QN +: SETB ) ) = (0:0:0,0:0:0); // delay is tris,tfall |
| |
| (negedge CLKN => (Q +: D ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| (negedge CLKN => (QN -: D ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| |
| $width (negedge CLKN &&& CONDB , 0:0:0, 0, notifier); |
| $width (posedge CLKN &&& CONDB , 0:0:0, 0, notifier); |
| $width (negedge SETB , 0.5, 0, notifier); |
| $width (negedge RESETB , 0.5, 0, notifier); |
| |
| $recrem ( posedge SETB , negedge CLKN , 0:0:0, 0:0:0, notifier , , COND0, SETB_delayed , CLKN_delayed ) ; |
| $recovery ( posedge SETB , negedge CLKN , 0:0:0, 0:0:0, notifier , , COND0, SETB_delayed , CLKN_delayed ) ; |
| $hold ( negedge CLKN , posedge SETB , 0:0:0, notifier ) ; |
| $recrem ( posedge RESETB , negedge CLKN , 0:0:0, 0:0:0, notifier , , COND1, RESETB_delayed , CLKN_delayed ) ; |
| $recovery ( posedge RESETB , negedge CLKN , 0:0:0, 0:0:0, notifier , , COND1, RESETB_delayed , CLKN_delayed ) ; |
| $hold ( negedge CLKN , posedge RESETB , 0:0:0, notifier ) ; |
| |
| $setuphold ( negedge CLKN , posedge D , 0:0:0, 0:0:0, notifier , , CONDB , CLKN_delayed , D_delayed ) ; |
| $setuphold ( negedge CLKN , negedge D , 0:0:0, 0:0:0, notifier , , CONDB , CLKN_delayed , D_delayed ) ; |
| |
| |
| $hold (posedge SETB, posedge RESETB, 3.0 , notifier); //arbitrary, uncharacterized value to |
| //flag possible state error |
| |
| $hold (posedge RESETB, posedge SETB, 3.0 , notifier); //arbitrary, uncharacterized value to |
| //flag possible state error |
| |
| endspecify |
| |
| |
| `endif |
| buf (Q,buf_Q); |
| not (QN,buf_Q); |
| |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_dfbbp_1 (Q, QN, D, CLK, SETB, RESETB); |
| output Q,QN; |
| input D,CLK,SETB,RESETB; |
| |
| wire reset, set, buf_Q; |
| wire CLK_delayed, RESETB_delayed, SETB_delayed; |
| |
| `ifdef functional |
| not (reset,RESETB); |
| not (set,SETB); |
| U_DFB_SETDOM #1 (buf_Q,set,reset,CLK,D); |
| `else |
| reg notifier; |
| |
| wire COND0, COND1, CONDB; |
| assign COND0 = (RESETB_delayed === 1'b1); |
| assign COND1 = (SETB_delayed === 1'b1); |
| assign CONDB = (COND0 & COND1); |
| |
| not (reset,RESETB_delayed); |
| not (set,SETB_delayed); |
| U_DFB_SETDOM_notify #0.001 (buf_Q,set,reset,CLK_delayed,D_delayed,notifier); |
| |
| specify |
| (negedge RESETB => (Q +: RESETB ) ) = 0:0:0; // delay is tfall |
| (negedge RESETB => (QN -: RESETB ) ) = 0:0:0; // delay is tris |
| |
| (SETB => (Q -: SETB ) ) = (0:0:0,0:0:0); // delay is tris,tfall |
| (SETB => (QN +: SETB ) ) = (0:0:0,0:0:0); // delay is tris,tfall |
| |
| (posedge CLK => (Q +: D ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| (posedge CLK => (QN -: D ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| |
| $width (negedge CLK &&& CONDB , 0:0:0, 0, notifier); |
| $width (posedge CLK &&& CONDB , 0:0:0, 0, notifier); |
| $width (negedge SETB , 0.5, 0, notifier); |
| $width (negedge RESETB , 0.5, 0, notifier); |
| |
| $recrem ( posedge SETB , posedge CLK , 0:0:0, 0:0:0, notifier , , COND0, SETB_delayed , CLK_delayed ) ; |
| $recovery ( posedge SETB , posedge CLK , 0:0:0, 0:0:0, notifier , , COND0, SETB_delayed , CLK_delayed ) ; |
| $hold ( posedge CLK , posedge SETB , 0:0:0, notifier ) ; |
| $recrem ( posedge RESETB , posedge CLK , 0:0:0, 0:0:0, notifier , , COND1, RESETB_delayed , CLK_delayed ) ; |
| $recovery ( posedge RESETB , posedge CLK , 0:0:0, 0:0:0, notifier , , COND1, RESETB_delayed , CLK_delayed ) ; |
| $hold ( posedge CLK , posedge RESETB , 0:0:0, notifier ) ; |
| |
| $setuphold ( posedge CLK , posedge D , 0:0:0, 0:0:0, notifier , , CONDB , CLK_delayed , D_delayed ) ; |
| $setuphold ( posedge CLK , negedge D , 0:0:0, 0:0:0, notifier , , CONDB , CLK_delayed , D_delayed ) ; |
| |
| |
| $hold (posedge SETB, posedge RESETB, 3.0 , notifier); //arbitrary, uncharacterized value to |
| //flag possible state error |
| |
| $hold (posedge RESETB, posedge SETB, 3.0 , notifier); //arbitrary, uncharacterized value to |
| //flag possible state error |
| |
| endspecify |
| |
| |
| `endif |
| buf (Q,buf_Q); |
| not (QN,buf_Q); |
| |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_dfrbp_1 (RESETB,CLK,D,Q,QN); |
| |
| output Q,QN; |
| input CLK,D,RESETB; |
| wire buf_Q, reset; |
| |
| `ifdef functional |
| not (reset,RESETB); |
| U_DF_P_R #1 ( buf_Q , D , CLK , reset ) ; |
| `else |
| reg notifier; |
| wire COND0 ; |
| wire D_delayed, RESETB_delayed, CLK_delayed ; |
| not (reset,RESETB_delayed); |
| U_DF_P_R_NO #0.001 ( buf_Q , D_delayed , CLK_delayed , reset , notifier ) ; |
| |
| assign COND0 = (RESETB_delayed === 1'b1); |
| specify |
| (negedge RESETB => (Q +: RESETB ) ) = 0:0:0; // delay is tris |
| (negedge RESETB => (QN -: RESETB ) ) = 0:0:0; // delay is tris |
| (posedge CLK => (Q : CLK ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| (posedge CLK => (QN : CLK ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| $width (posedge CLK &&& (RESETB===1'b1) , 0:0:0, 0, notifier); |
| $width (negedge CLK &&& (RESETB===1'b1) , 0:0:0, 0, notifier); |
| $width (negedge RESETB , 0.5, 0, notifier); |
| $recrem ( posedge RESETB , posedge CLK , 0:0:0, 0:0:0, notifier , , , RESETB_delayed , CLK_delayed ) ; |
| $recovery ( posedge RESETB , posedge CLK , 0:0:0, 0:0:0, notifier , , , RESETB_delayed , CLK_delayed ) ; |
| $hold ( posedge CLK , posedge RESETB , 0:0:0, notifier ) ; |
| $setuphold ( posedge CLK , posedge D , 0:0:0, 0:0:0, notifier , , COND0 , CLK_delayed , D_delayed ) ; |
| $setuphold ( posedge CLK , negedge D , 0:0:0, 0:0:0, notifier , , COND0 , CLK_delayed , D_delayed ) ; |
| endspecify |
| `endif |
| |
| buf (Q,buf_Q); |
| not (QN,buf_Q); |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_dfrbp_2 (RESETB,CLK,D,Q,QN); |
| |
| output Q,QN; |
| input CLK,D,RESETB; |
| wire buf_Q, reset; |
| |
| `ifdef functional |
| not (reset,RESETB); |
| U_DF_P_R #1 ( buf_Q , D , CLK , reset ) ; |
| `else |
| reg notifier; |
| wire COND0 ; |
| wire D_delayed, RESETB_delayed, CLK_delayed ; |
| not (reset,RESETB_delayed); |
| U_DF_P_R_NO #0.001 ( buf_Q , D_delayed , CLK_delayed , reset , notifier ) ; |
| |
| assign COND0 = (RESETB_delayed === 1'b1); |
| specify |
| (negedge RESETB => (Q +: RESETB ) ) = 0:0:0; // delay is tris |
| (negedge RESETB => (QN -: RESETB ) ) = 0:0:0; // delay is tris |
| (posedge CLK => (Q : CLK ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| (posedge CLK => (QN : CLK ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| $width (posedge CLK &&& (RESETB===1'b1) , 0:0:0, 0, notifier); |
| $width (negedge CLK &&& (RESETB===1'b1) , 0:0:0, 0, notifier); |
| $width (negedge RESETB , 0.5, 0, notifier); |
| $recrem ( posedge RESETB , posedge CLK , 0:0:0, 0:0:0, notifier , , , RESETB_delayed , CLK_delayed ) ; |
| $recovery ( posedge RESETB , posedge CLK , 0:0:0, 0:0:0, notifier , , , RESETB_delayed , CLK_delayed ) ; |
| $hold ( posedge CLK , posedge RESETB , 0:0:0, notifier ) ; |
| $setuphold ( posedge CLK , posedge D , 0:0:0, 0:0:0, notifier , , COND0 , CLK_delayed , D_delayed ) ; |
| $setuphold ( posedge CLK , negedge D , 0:0:0, 0:0:0, notifier , , COND0 , CLK_delayed , D_delayed ) ; |
| endspecify |
| `endif |
| |
| buf (Q,buf_Q); |
| not (QN,buf_Q); |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_dfrtn_xs (RESETB,CLKN,D,Q); |
| |
| output Q; |
| input CLKN,D,RESETB; |
| wire buf_Q, reset, intclk; |
| |
| `ifdef functional |
| not (reset,RESETB); |
| not (intclk,CLKN); |
| U_DF_P_R #1 ( buf_Q , D , intclk , reset ) ; |
| `else |
| reg notifier; |
| wire COND0 ; |
| wire D_delayed, RESETB_delayed, CLKN_delayed ; |
| not (reset,RESETB_delayed); |
| not (intclk,CLKN_delayed); |
| U_DF_P_R_NO #0.001 ( buf_Q , D_delayed , intclk , reset , notifier ) ; |
| |
| assign COND0 = (RESETB_delayed === 1'b1); |
| specify |
| (negedge RESETB => (Q +: RESETB ) ) = 0:0:0; // delay is tris |
| (negedge CLKN => (Q : CLKN ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| $width (posedge CLKN &&& (RESETB===1'b1) , 0:0:0, 0, notifier); |
| $width (negedge CLKN &&& (RESETB===1'b1) , 0:0:0, 0, notifier); |
| $width (negedge RESETB , 0.5, 0, notifier); |
| $recrem ( posedge RESETB , negedge CLKN , 0:0:0, 0:0:0, notifier , , , RESETB_delayed , CLKN_delayed ) ; |
| $recovery ( posedge RESETB , negedge CLKN , 0:0:0, 0:0:0, notifier , , , RESETB_delayed , CLKN_delayed ) ; |
| $hold ( negedge CLKN , posedge RESETB , 0:0:0, notifier ) ; |
| $setuphold ( negedge CLKN , posedge D , 0:0:0, 0:0:0, notifier , , COND0 , CLKN_delayed , D_delayed ) ; |
| $setuphold ( negedge CLKN , negedge D , 0:0:0, 0:0:0, notifier , , COND0 , CLKN_delayed , D_delayed ) ; |
| endspecify |
| `endif |
| |
| buf (Q,buf_Q); |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_dfrtn_1 (RESETB,CLKN,D,Q); |
| |
| output Q; |
| input CLKN,D,RESETB; |
| wire buf_Q, reset, intclk; |
| |
| `ifdef functional |
| not (reset,RESETB); |
| not (intclk,CLKN); |
| U_DF_P_R #1 ( buf_Q , D , intclk , reset ) ; |
| `else |
| reg notifier; |
| wire COND0 ; |
| wire D_delayed, RESETB_delayed, CLKN_delayed ; |
| not (reset,RESETB_delayed); |
| not (intclk,CLKN_delayed); |
| U_DF_P_R_NO #0.001 ( buf_Q , D_delayed , intclk , reset , notifier ) ; |
| |
| assign COND0 = (RESETB_delayed === 1'b1); |
| specify |
| (negedge RESETB => (Q +: RESETB ) ) = 0:0:0; // delay is tris |
| (negedge CLKN => (Q : CLKN ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| $width (posedge CLKN &&& (RESETB===1'b1) , 0:0:0, 0, notifier); |
| $width (negedge CLKN &&& (RESETB===1'b1) , 0:0:0, 0, notifier); |
| $width (negedge RESETB , 0.5, 0, notifier); |
| $recrem ( posedge RESETB , negedge CLKN , 0:0:0, 0:0:0, notifier , , , RESETB_delayed , CLKN_delayed ) ; |
| $recovery ( posedge RESETB , negedge CLKN , 0:0:0, 0:0:0, notifier , , , RESETB_delayed , CLKN_delayed ) ; |
| $hold ( negedge CLKN , posedge RESETB , 0:0:0, notifier ) ; |
| $setuphold ( negedge CLKN , posedge D , 0:0:0, 0:0:0, notifier , , COND0 , CLKN_delayed , D_delayed ) ; |
| $setuphold ( negedge CLKN , negedge D , 0:0:0, 0:0:0, notifier , , COND0 , CLKN_delayed , D_delayed ) ; |
| endspecify |
| `endif |
| |
| buf (Q,buf_Q); |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_dfrtp_1 (RESETB,CLK,D,Q); |
| |
| output Q; |
| input CLK,D,RESETB; |
| wire buf_Q, reset; |
| |
| `ifdef functional |
| not (reset,RESETB); |
| U_DF_P_R #1 ( buf_Q , D , CLK , reset ) ; |
| `else |
| reg notifier; |
| wire COND0 ; |
| wire D_delayed, RESETB_delayed, CLK_delayed ; |
| not (reset,RESETB_delayed); |
| U_DF_P_R_NO #0.001 ( buf_Q , D_delayed , CLK_delayed , reset , notifier ) ; |
| |
| assign COND0 = (RESETB_delayed === 1'b1); |
| specify |
| (negedge RESETB => (Q +: RESETB ) ) = 0:0:0; // delay is tris |
| (posedge CLK => (Q : CLK ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| $width (posedge CLK &&& (RESETB===1'b1) , 0:0:0, 0, notifier); |
| $width (negedge CLK &&& (RESETB===1'b1) , 0:0:0, 0, notifier); |
| $width (negedge RESETB , 0.5, 0, notifier); |
| $recrem ( posedge RESETB , posedge CLK , 0:0:0, 0:0:0, notifier , , , RESETB_delayed , CLK_delayed ) ; |
| $recovery ( posedge RESETB , posedge CLK , 0:0:0, 0:0:0, notifier , , , RESETB_delayed , CLK_delayed ) ; |
| $hold ( posedge CLK , posedge RESETB , 0:0:0, notifier ) ; |
| $setuphold ( posedge CLK , posedge D , 0:0:0, 0:0:0, notifier , , COND0 , CLK_delayed , D_delayed ) ; |
| $setuphold ( posedge CLK , negedge D , 0:0:0, 0:0:0, notifier , , COND0 , CLK_delayed , D_delayed ) ; |
| endspecify |
| `endif |
| |
| buf (Q,buf_Q); |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_dfrtp_xs (RESETB,CLK,D,Q); |
| |
| output Q; |
| input CLK,D,RESETB; |
| wire buf_Q, reset; |
| |
| `ifdef functional |
| not (reset,RESETB); |
| U_DF_P_R #1 ( buf_Q , D , CLK , reset ) ; |
| `else |
| reg notifier; |
| wire COND0 ; |
| wire D_delayed, RESETB_delayed, CLK_delayed ; |
| not (reset,RESETB_delayed); |
| U_DF_P_R_NO #0.001 ( buf_Q , D_delayed , CLK_delayed , reset , notifier ) ; |
| |
| assign COND0 = (RESETB_delayed === 1'b1); |
| specify |
| (negedge RESETB => (Q +: RESETB ) ) = 0:0:0; // delay is tris |
| (posedge CLK => (Q : CLK ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| $width (posedge CLK &&& (RESETB===1'b1) , 0:0:0, 0, notifier); |
| $width (negedge CLK &&& (RESETB===1'b1) , 0:0:0, 0, notifier); |
| $width (negedge RESETB , 0.5, 0, notifier); |
| $recrem ( posedge RESETB , posedge CLK , 0:0:0, 0:0:0, notifier , , , RESETB_delayed , CLK_delayed ) ; |
| $recovery ( posedge RESETB , posedge CLK , 0:0:0, 0:0:0, notifier , , , RESETB_delayed , CLK_delayed ) ; |
| $hold ( posedge CLK , posedge RESETB , 0:0:0, notifier ) ; |
| $setuphold ( posedge CLK , posedge D , 0:0:0, 0:0:0, notifier , , COND0 , CLK_delayed , D_delayed ) ; |
| $setuphold ( posedge CLK , negedge D , 0:0:0, 0:0:0, notifier , , COND0 , CLK_delayed , D_delayed ) ; |
| endspecify |
| `endif |
| |
| buf (Q,buf_Q); |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_dfrtp_2 (RESETB,CLK,D,Q); |
| |
| output Q; |
| input CLK,D,RESETB; |
| wire buf_Q, reset; |
| |
| `ifdef functional |
| not (reset,RESETB); |
| U_DF_P_R #1 ( buf_Q , D , CLK , reset ) ; |
| `else |
| reg notifier; |
| wire COND0 ; |
| wire D_delayed, RESETB_delayed, CLK_delayed ; |
| not (reset,RESETB_delayed); |
| U_DF_P_R_NO #0.001 ( buf_Q , D_delayed , CLK_delayed , reset , notifier ) ; |
| |
| assign COND0 = (RESETB_delayed === 1'b1); |
| specify |
| (negedge RESETB => (Q +: RESETB ) ) = 0:0:0; // delay is tris |
| (posedge CLK => (Q : CLK ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| $width (posedge CLK &&& (RESETB===1'b1) , 0:0:0, 0, notifier); |
| $width (negedge CLK &&& (RESETB===1'b1) , 0:0:0, 0, notifier); |
| $width (negedge RESETB , 0.5, 0, notifier); |
| $recrem ( posedge RESETB , posedge CLK , 0:0:0, 0:0:0, notifier , , , RESETB_delayed , CLK_delayed ) ; |
| $recovery ( posedge RESETB , posedge CLK , 0:0:0, 0:0:0, notifier , , , RESETB_delayed , CLK_delayed ) ; |
| $hold ( posedge CLK , posedge RESETB , 0:0:0, notifier ) ; |
| $setuphold ( posedge CLK , posedge D , 0:0:0, 0:0:0, notifier , , COND0 , CLK_delayed , D_delayed ) ; |
| $setuphold ( posedge CLK , negedge D , 0:0:0, 0:0:0, notifier , , COND0 , CLK_delayed , D_delayed ) ; |
| endspecify |
| `endif |
| |
| buf (Q,buf_Q); |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_dfrtp_4 (RESETB,CLK,D,Q); |
| |
| output Q; |
| input CLK,D,RESETB; |
| wire buf_Q, reset; |
| |
| `ifdef functional |
| not (reset,RESETB); |
| U_DF_P_R #1 ( buf_Q , D , CLK , reset ) ; |
| `else |
| reg notifier; |
| wire COND0 ; |
| wire D_delayed, RESETB_delayed, CLK_delayed ; |
| not (reset,RESETB_delayed); |
| U_DF_P_R_NO #0.001 ( buf_Q , D_delayed , CLK_delayed , reset , notifier ) ; |
| |
| assign COND0 = (RESETB_delayed === 1'b1); |
| specify |
| (negedge RESETB => (Q +: RESETB ) ) = 0:0:0; // delay is tris |
| (posedge CLK => (Q : CLK ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| $width (posedge CLK &&& (RESETB===1'b1) , 0:0:0, 0, notifier); |
| $width (negedge CLK &&& (RESETB===1'b1) , 0:0:0, 0, notifier); |
| $width (negedge RESETB , 0.5, 0, notifier); |
| $recrem ( posedge RESETB , posedge CLK , 0:0:0, 0:0:0, notifier , , , RESETB_delayed , CLK_delayed ) ; |
| $recovery ( posedge RESETB , posedge CLK , 0:0:0, 0:0:0, notifier , , , RESETB_delayed , CLK_delayed ) ; |
| $hold ( posedge CLK , posedge RESETB , 0:0:0, notifier ) ; |
| $setuphold ( posedge CLK , posedge D , 0:0:0, 0:0:0, notifier , , COND0 , CLK_delayed , D_delayed ) ; |
| $setuphold ( posedge CLK , negedge D , 0:0:0, 0:0:0, notifier , , COND0 , CLK_delayed , D_delayed ) ; |
| endspecify |
| `endif |
| |
| buf (Q,buf_Q); |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_dfsbp_1 (CLK,D,Q,QN,SETB); |
| |
| output Q,QN; |
| input CLK,D,SETB; |
| wire buf_Q, set; |
| |
| `ifdef functional |
| not (set,SETB); |
| U_DF_P_S #1 ( buf_Q , D , CLK , set ) ; |
| `else |
| reg notifier; |
| wire COND0 ; |
| wire D_delayed, SETB_delayed, CLK_delayed ; |
| not (set,SETB_delayed); |
| U_DF_P_S_NO #0.001 ( buf_Q , D_delayed , CLK_delayed , set , notifier ) ; |
| |
| assign COND0 = (SETB_delayed === 1'b1); |
| specify |
| (negedge SETB => (Q -: SETB ) ) = 0:0:0; // delay is tris |
| (negedge SETB => (QN +: SETB ) ) = 0:0:0; // delay is tris |
| (posedge CLK => (Q : CLK ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| (posedge CLK => (QN : CLK ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| $width (posedge CLK &&& (SETB===1'b1) , 0:0:0, 0, notifier); |
| $width (negedge CLK &&& (SETB===1'b1) , 0:0:0, 0, notifier); |
| $width (negedge SETB , 0.5, 0, notifier); |
| $recrem ( posedge SETB , posedge CLK , 0:0:0, 0:0:0, notifier , , , SETB_delayed , CLK_delayed ) ; |
| $recovery ( posedge SETB , posedge CLK , 0:0:0, 0:0:0, notifier , , , SETB_delayed , CLK_delayed ) ; |
| $hold ( posedge CLK , posedge SETB , 0:0:0, notifier ) ; |
| $setuphold ( posedge CLK , posedge D , 0:0:0, 0:0:0, notifier , , COND0 , CLK_delayed , D_delayed ) ; |
| $setuphold ( posedge CLK , negedge D , 0:0:0, 0:0:0, notifier , , COND0 , CLK_delayed , D_delayed ) ; |
| endspecify |
| `endif |
| |
| buf (Q,buf_Q); |
| not (QN,buf_Q); |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_dfsbp_2 (CLK,D,Q,QN,SETB); |
| |
| output Q,QN; |
| input CLK,D,SETB; |
| wire buf_Q, set; |
| |
| `ifdef functional |
| not (set,SETB); |
| U_DF_P_S #1 ( buf_Q , D , CLK , set ) ; |
| `else |
| reg notifier; |
| wire COND0 ; |
| wire D_delayed, SETB_delayed, CLK_delayed ; |
| not (set,SETB_delayed); |
| U_DF_P_S_NO #0.001 ( buf_Q , D_delayed , CLK_delayed , set , notifier ) ; |
| |
| assign COND0 = (SETB_delayed === 1'b1); |
| specify |
| (negedge SETB => (Q -: SETB ) ) = 0:0:0; // delay is tris |
| (negedge SETB => (QN +: SETB ) ) = 0:0:0; // delay is tris |
| (posedge CLK => (Q : CLK ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| (posedge CLK => (QN : CLK ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| $width (posedge CLK &&& (SETB===1'b1) , 0:0:0, 0, notifier); |
| $width (negedge CLK &&& (SETB===1'b1) , 0:0:0, 0, notifier); |
| $width (negedge SETB , 0.5, 0, notifier); |
| $recrem ( posedge SETB , posedge CLK , 0:0:0, 0:0:0, notifier , , , SETB_delayed , CLK_delayed ) ; |
| $recovery ( posedge SETB , posedge CLK , 0:0:0, 0:0:0, notifier , , , SETB_delayed , CLK_delayed ) ; |
| $hold ( posedge CLK , posedge SETB , 0:0:0, notifier ) ; |
| $setuphold ( posedge CLK , posedge D , 0:0:0, 0:0:0, notifier , , COND0 , CLK_delayed , D_delayed ) ; |
| $setuphold ( posedge CLK , negedge D , 0:0:0, 0:0:0, notifier , , COND0 , CLK_delayed , D_delayed ) ; |
| endspecify |
| `endif |
| |
| buf (Q,buf_Q); |
| not (QN,buf_Q); |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_dfstp_1 (CLK,D,Q,SETB); |
| |
| output Q; |
| input CLK,D,SETB; |
| wire buf_Q, set; |
| |
| `ifdef functional |
| not (set,SETB); |
| U_DF_P_S #1 ( buf_Q , D , CLK , set ) ; |
| `else |
| reg notifier; |
| wire COND0 ; |
| wire D_delayed, SETB_delayed, CLK_delayed ; |
| not (set,SETB_delayed); |
| U_DF_P_S_NO #0.001 ( buf_Q , D_delayed , CLK_delayed , set , notifier ) ; |
| |
| assign COND0 = (SETB_delayed === 1'b1); |
| specify |
| (negedge SETB => (Q -: SETB ) ) = 0:0:0; // delay is tris |
| (posedge CLK => (Q : CLK ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| $width (posedge CLK &&& (SETB===1'b1) , 0:0:0, 0, notifier); |
| $width (negedge CLK &&& (SETB===1'b1) , 0:0:0, 0, notifier); |
| $width (negedge SETB , 0.5, 0, notifier); |
| $recrem ( posedge SETB , posedge CLK , 0:0:0, 0:0:0, notifier , , , SETB_delayed , CLK_delayed ) ; |
| $recovery ( posedge SETB , posedge CLK , 0:0:0, 0:0:0, notifier , , , SETB_delayed , CLK_delayed ) ; |
| $hold ( posedge CLK , posedge SETB , 0:0:0, notifier ) ; |
| $setuphold ( posedge CLK , posedge D , 0:0:0, 0:0:0, notifier , , COND0 , CLK_delayed , D_delayed ) ; |
| $setuphold ( posedge CLK , negedge D , 0:0:0, 0:0:0, notifier , , COND0 , CLK_delayed , D_delayed ) ; |
| endspecify |
| `endif |
| |
| buf (Q,buf_Q); |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_dfstp_2 (CLK,D,Q,SETB); |
| |
| output Q; |
| input CLK,D,SETB; |
| wire buf_Q, set; |
| |
| `ifdef functional |
| not (set,SETB); |
| U_DF_P_S #1 ( buf_Q , D , CLK , set ) ; |
| `else |
| reg notifier; |
| wire COND0 ; |
| wire D_delayed, SETB_delayed, CLK_delayed ; |
| not (set,SETB_delayed); |
| U_DF_P_S_NO #0.001 ( buf_Q , D_delayed , CLK_delayed , set , notifier ) ; |
| |
| assign COND0 = (SETB_delayed === 1'b1); |
| specify |
| (negedge SETB => (Q -: SETB ) ) = 0:0:0; // delay is tris |
| (posedge CLK => (Q : CLK ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| $width (posedge CLK &&& (SETB===1'b1) , 0:0:0, 0, notifier); |
| $width (negedge CLK &&& (SETB===1'b1) , 0:0:0, 0, notifier); |
| $width (negedge SETB , 0.5, 0, notifier); |
| $recrem ( posedge SETB , posedge CLK , 0:0:0, 0:0:0, notifier , , , SETB_delayed , CLK_delayed ) ; |
| $recovery ( posedge SETB , posedge CLK , 0:0:0, 0:0:0, notifier , , , SETB_delayed , CLK_delayed ) ; |
| $hold ( posedge CLK , posedge SETB , 0:0:0, notifier ) ; |
| $setuphold ( posedge CLK , posedge D , 0:0:0, 0:0:0, notifier , , COND0 , CLK_delayed , D_delayed ) ; |
| $setuphold ( posedge CLK , negedge D , 0:0:0, 0:0:0, notifier , , COND0 , CLK_delayed , D_delayed ) ; |
| endspecify |
| `endif |
| |
| buf (Q,buf_Q); |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_dfstp_4 (CLK,D,Q,SETB); |
| |
| output Q; |
| input CLK,D,SETB; |
| wire buf_Q, set; |
| |
| `ifdef functional |
| not (set,SETB); |
| U_DF_P_S #1 ( buf_Q , D , CLK , set ) ; |
| `else |
| reg notifier; |
| wire COND0 ; |
| wire D_delayed, SETB_delayed, CLK_delayed ; |
| not (set,SETB_delayed); |
| U_DF_P_S_NO #0.001 ( buf_Q , D_delayed , CLK_delayed , set , notifier ) ; |
| |
| assign COND0 = (SETB_delayed === 1'b1); |
| specify |
| (negedge SETB => (Q -: SETB ) ) = 0:0:0; // delay is tris |
| (posedge CLK => (Q : CLK ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| $width (posedge CLK &&& (SETB===1'b1) , 0:0:0, 0, notifier); |
| $width (negedge CLK &&& (SETB===1'b1) , 0:0:0, 0, notifier); |
| $width (negedge SETB , 0.5, 0, notifier); |
| $recrem ( posedge SETB , posedge CLK , 0:0:0, 0:0:0, notifier , , , SETB_delayed , CLK_delayed ) ; |
| $recovery ( posedge SETB , posedge CLK , 0:0:0, 0:0:0, notifier , , , SETB_delayed , CLK_delayed ) ; |
| $hold ( posedge CLK , posedge SETB , 0:0:0, notifier ) ; |
| $setuphold ( posedge CLK , posedge D , 0:0:0, 0:0:0, notifier , , COND0 , CLK_delayed , D_delayed ) ; |
| $setuphold ( posedge CLK , negedge D , 0:0:0, 0:0:0, notifier , , COND0 , CLK_delayed , D_delayed ) ; |
| endspecify |
| `endif |
| |
| buf (Q,buf_Q); |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_dfxbp_1 (CLK,D,Q,QN); |
| |
| output Q,QN; |
| input CLK,D; |
| wire buf_Q; |
| |
| `ifdef functional |
| U_DF_P #1 ( buf_Q , D , CLK ) ; |
| `else |
| reg notifier; |
| wire D_delayed, CLK_delayed ; |
| U_DF_P_NO #0.001 ( buf_Q , D_delayed , CLK_delayed , notifier ) ; |
| |
| specify |
| (posedge CLK => (Q : CLK ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| (posedge CLK => (QN : CLK ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| $width (posedge CLK , 0:0:0, 0, notifier); |
| $width (negedge CLK , 0:0:0, 0, notifier); |
| $setuphold ( posedge CLK , posedge D , 0:0:0, 0:0:0, notifier , , , CLK_delayed , D_delayed ) ; |
| $setuphold ( posedge CLK , negedge D , 0:0:0, 0:0:0, notifier , , , CLK_delayed , D_delayed ) ; |
| endspecify |
| `endif |
| |
| buf (Q,buf_Q); |
| not (QN,buf_Q); |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_dfxbp_2 (CLK,D,Q,QN); |
| |
| output Q,QN; |
| input CLK,D; |
| wire buf_Q; |
| |
| `ifdef functional |
| U_DF_P #1 ( buf_Q , D , CLK ) ; |
| `else |
| reg notifier; |
| wire D_delayed, CLK_delayed ; |
| U_DF_P_NO #0.001 ( buf_Q , D_delayed , CLK_delayed , notifier ) ; |
| |
| specify |
| (posedge CLK => (Q : CLK ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| (posedge CLK => (QN : CLK ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| $width (posedge CLK , 0:0:0, 0, notifier); |
| $width (negedge CLK , 0:0:0, 0, notifier); |
| $setuphold ( posedge CLK , posedge D , 0:0:0, 0:0:0, notifier , , , CLK_delayed , D_delayed ) ; |
| $setuphold ( posedge CLK , negedge D , 0:0:0, 0:0:0, notifier , , , CLK_delayed , D_delayed ) ; |
| endspecify |
| `endif |
| |
| buf (Q,buf_Q); |
| not (QN,buf_Q); |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_dfxtp_1 (CLK,D,Q); |
| |
| output Q; |
| input CLK,D; |
| wire buf_Q; |
| |
| `ifdef functional |
| U_DF_P #1 ( buf_Q , D , CLK ) ; |
| `else |
| reg notifier; |
| wire D_delayed, CLK_delayed ; |
| U_DF_P_NO #0.001 ( buf_Q , D_delayed , CLK_delayed , notifier ) ; |
| |
| specify |
| (posedge CLK => (Q : CLK ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| $width (posedge CLK , 0:0:0, 0, notifier); |
| $width (negedge CLK , 0:0:0, 0, notifier); |
| $setuphold ( posedge CLK , posedge D , 0:0:0, 0:0:0, notifier , , , CLK_delayed , D_delayed ) ; |
| $setuphold ( posedge CLK , negedge D , 0:0:0, 0:0:0, notifier , , , CLK_delayed , D_delayed ) ; |
| endspecify |
| `endif |
| |
| buf (Q,buf_Q); |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_dfxtp_2 (CLK,D,Q); |
| |
| output Q; |
| input CLK,D; |
| wire buf_Q; |
| |
| `ifdef functional |
| U_DF_P #1 ( buf_Q , D , CLK ) ; |
| `else |
| reg notifier; |
| wire D_delayed, CLK_delayed ; |
| U_DF_P_NO #0.001 ( buf_Q , D_delayed , CLK_delayed , notifier ) ; |
| |
| specify |
| (posedge CLK => (Q : CLK ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| $width (posedge CLK , 0:0:0, 0, notifier); |
| $width (negedge CLK , 0:0:0, 0, notifier); |
| $setuphold ( posedge CLK , posedge D , 0:0:0, 0:0:0, notifier , , , CLK_delayed , D_delayed ) ; |
| $setuphold ( posedge CLK , negedge D , 0:0:0, 0:0:0, notifier , , , CLK_delayed , D_delayed ) ; |
| endspecify |
| `endif |
| |
| buf (Q,buf_Q); |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_dfxtp_4 (CLK,D,Q); |
| |
| output Q; |
| input CLK,D; |
| wire buf_Q; |
| |
| `ifdef functional |
| U_DF_P #1 ( buf_Q , D , CLK ) ; |
| `else |
| reg notifier; |
| wire D_delayed, CLK_delayed ; |
| U_DF_P_NO #0.001 ( buf_Q , D_delayed , CLK_delayed , notifier ) ; |
| |
| specify |
| (posedge CLK => (Q : CLK ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| $width (posedge CLK , 0:0:0, 0, notifier); |
| $width (negedge CLK , 0:0:0, 0, notifier); |
| $setuphold ( posedge CLK , posedge D , 0:0:0, 0:0:0, notifier , , , CLK_delayed , D_delayed ) ; |
| $setuphold ( posedge CLK , negedge D , 0:0:0, 0:0:0, notifier , , , CLK_delayed , D_delayed ) ; |
| endspecify |
| `endif |
| |
| buf (Q,buf_Q); |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_diode_0 ( DIODE ); |
| input DIODE ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_diode_1 ( DIODE ); |
| input DIODE ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_dlclkp_1 ( GCLK, GATE, CLK ); |
| output GCLK; |
| input GATE, CLK; |
| wire m0, clkn; |
| |
| `ifdef functional |
| not (clkn,CLK); |
| U_DL_P #1 ( m0 , GATE , clkn ) ; |
| and (GCLK, m0, CLK); |
| |
| `else |
| wire CLK_delayed, GATE_delayed; |
| reg notifier; |
| |
| not (clkn,CLK_delayed); |
| U_DL_P_NO #0.001 ( m0 , GATE_delayed , clkn , notifier ) ; |
| and (GCLK, m0, CLK_delayed); |
| |
| specify |
| (CLK +=> GCLK) = (0:0:0,0:0:0); // delays are tris,tfall |
| $width (posedge CLK , 0:0:0, 0, notifier); |
| $width (negedge CLK , 0:0:0, 0, notifier); |
| $setuphold ( posedge CLK , posedge GATE , 0:0:0, 0:0:0, notifier , , , CLK_delayed , GATE_delayed ) ; |
| $setuphold ( posedge CLK , negedge GATE , 0:0:0, 0:0:0, notifier , , , CLK_delayed , GATE_delayed ) ; |
| endspecify |
| `endif |
| |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_dlclkp_2 ( GCLK, GATE, CLK ); |
| output GCLK; |
| input GATE, CLK; |
| wire m0, clkn; |
| |
| `ifdef functional |
| not (clkn,CLK); |
| U_DL_P #1 ( m0 , GATE , clkn ) ; |
| and (GCLK, m0, CLK); |
| |
| `else |
| wire CLK_delayed, GATE_delayed; |
| reg notifier; |
| |
| not (clkn,CLK_delayed); |
| U_DL_P_NO #0.001 ( m0 , GATE_delayed , clkn , notifier ) ; |
| and (GCLK, m0, CLK_delayed); |
| |
| specify |
| (CLK +=> GCLK) = (0:0:0,0:0:0); // delays are tris,tfall |
| $width (posedge CLK , 0:0:0, 0, notifier); |
| $width (negedge CLK , 0:0:0, 0, notifier); |
| $setuphold ( posedge CLK , posedge GATE , 0:0:0, 0:0:0, notifier , , , CLK_delayed , GATE_delayed ) ; |
| $setuphold ( posedge CLK , negedge GATE , 0:0:0, 0:0:0, notifier , , , CLK_delayed , GATE_delayed ) ; |
| endspecify |
| `endif |
| |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_dlclkp_4 ( GCLK, GATE, CLK ); |
| output GCLK; |
| input GATE, CLK; |
| wire m0, clkn; |
| |
| `ifdef functional |
| not (clkn,CLK); |
| U_DL_P #1 ( m0 , GATE , clkn ) ; |
| and (GCLK, m0, CLK); |
| |
| `else |
| wire CLK_delayed, GATE_delayed; |
| reg notifier; |
| |
| not (clkn,CLK_delayed); |
| U_DL_P_NO #0.001 ( m0 , GATE_delayed , clkn , notifier ) ; |
| and (GCLK, m0, CLK_delayed); |
| |
| specify |
| (CLK +=> GCLK) = (0:0:0,0:0:0); // delays are tris,tfall |
| $width (posedge CLK , 0:0:0, 0, notifier); |
| $width (negedge CLK , 0:0:0, 0, notifier); |
| $setuphold ( posedge CLK , posedge GATE , 0:0:0, 0:0:0, notifier , , , CLK_delayed , GATE_delayed ) ; |
| $setuphold ( posedge CLK , negedge GATE , 0:0:0, 0:0:0, notifier , , , CLK_delayed , GATE_delayed ) ; |
| endspecify |
| `endif |
| |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_dlrbn_1 (RESETB,D,GATEN,Q,QN); |
| |
| output Q,QN; |
| input RESETB,D,GATEN; |
| wire reset, intgate; |
| |
| `ifdef functional |
| not (reset,RESETB); |
| not (intgate,GATEN); |
| U_DL_P_R #1 ( buf_Q , D , intgate , reset ) ; |
| `else |
| reg notifier; |
| wire COND0 ; |
| wire D_delayed, GATEN_delayed, RESET_delayed ; |
| not (reset,RESETB_delayed); |
| not (intgate,GATEN_delayed); |
| U_DL_P_R_NO #0.001 ( buf_Q , D_delayed , intgate , reset , notifier ) ; |
| |
| assign COND0 = (RESETB_delayed === 1'b1); |
| specify |
| (negedge RESETB => (Q +: RESETB ) ) = (0:0:0,0:0:0); // delay is tfall |
| (posedge RESETB => (Q +: RESETB ) ) = (0:0:0,0:0:0); // delay is trise |
| (D +=> Q ) = (0:0:0,0:0:0); // delays are tris,tfall |
| (negedge GATEN => (Q : GATEN ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| |
| (negedge RESETB => (QN -: RESETB ) ) = (0:0:0,0:0:0); // delay is trise |
| (posedge RESETB => (QN -: RESETB ) ) = (0:0:0,0:0:0); // delay is tfall |
| (D -=> QN ) = (0:0:0,0:0:0); // delays are tris,tfall |
| (negedge GATEN => (QN : GATEN ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| |
| $width (posedge GATEN &&& (RESETB===1'b1) , 0:0:0, 0, notifier); |
| $width (negedge GATEN &&& (RESETB===1'b1) , 0:0:0, 0, notifier); |
| $width (negedge RESETB , 0.5, 0, notifier); |
| $recrem ( posedge RESETB , posedge GATEN , 0:0:0, 0:0:0, notifier , , , RESETB_delayed , GATEN_delayed ) ; |
| $recovery ( posedge RESETB , posedge GATEN , 0:0:0, 0:0:0, notifier , , , RESETB_delayed , GATEN_delayed ) ; |
| $hold ( posedge GATEN , posedge RESETB , 0:0:0, notifier ) ; |
| $setuphold ( posedge GATEN , posedge D , 0:0:0, 0:0:0, notifier , , COND0 , GATEN_delayed , D_delayed ) ; |
| $setuphold ( posedge GATEN , negedge D , 0:0:0, 0:0:0, notifier , , COND0 , GATEN_delayed , D_delayed ) ; |
| endspecify |
| `endif |
| |
| buf (Q,buf_Q); |
| not (QN,buf_Q); |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_dlrbn_2 (RESETB,D,GATEN,Q,QN); |
| |
| output Q,QN; |
| input RESETB,D,GATEN; |
| wire reset, intgate; |
| |
| `ifdef functional |
| not (reset,RESETB); |
| not (intgate,GATEN); |
| U_DL_P_R #1 ( buf_Q , D , intgate , reset ) ; |
| `else |
| reg notifier; |
| wire COND0 ; |
| wire D_delayed, GATEN_delayed, RESET_delayed ; |
| not (reset,RESETB_delayed); |
| not (intgate,GATEN_delayed); |
| U_DL_P_R_NO #0.001 ( buf_Q , D_delayed , intgate , reset , notifier ) ; |
| |
| assign COND0 = (RESETB_delayed === 1'b1); |
| specify |
| (negedge RESETB => (Q +: RESETB ) ) = (0:0:0,0:0:0); // delay is tfall |
| (posedge RESETB => (Q +: RESETB ) ) = (0:0:0,0:0:0); // delay is trise |
| (D +=> Q ) = (0:0:0,0:0:0); // delays are tris,tfall |
| (negedge GATEN => (Q : GATEN ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| |
| (negedge RESETB => (QN -: RESETB ) ) = (0:0:0,0:0:0); // delay is trise |
| (posedge RESETB => (QN -: RESETB ) ) = (0:0:0,0:0:0); // delay is tfall |
| (D -=> QN ) = (0:0:0,0:0:0); // delays are tris,tfall |
| (negedge GATEN => (QN : GATEN ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| |
| $width (posedge GATEN &&& (RESETB===1'b1) , 0:0:0, 0, notifier); |
| $width (negedge GATEN &&& (RESETB===1'b1) , 0:0:0, 0, notifier); |
| $width (negedge RESETB , 0.5, 0, notifier); |
| $recrem ( posedge RESETB , posedge GATEN , 0:0:0, 0:0:0, notifier , , , RESETB_delayed , GATEN_delayed ) ; |
| $recovery ( posedge RESETB , posedge GATEN , 0:0:0, 0:0:0, notifier , , , RESETB_delayed , GATEN_delayed ) ; |
| $hold ( posedge GATEN , posedge RESETB , 0:0:0, notifier ) ; |
| $setuphold ( posedge GATEN , posedge D , 0:0:0, 0:0:0, notifier , , COND0 , GATEN_delayed , D_delayed ) ; |
| $setuphold ( posedge GATEN , negedge D , 0:0:0, 0:0:0, notifier , , COND0 , GATEN_delayed , D_delayed ) ; |
| endspecify |
| `endif |
| |
| buf (Q,buf_Q); |
| not (QN,buf_Q); |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_dlrbp_1 (RESETB,D,GATE,Q,QN); |
| |
| output Q,QN; |
| input RESETB,D,GATE; |
| wire reset; |
| |
| `ifdef functional |
| not (reset,RESETB); |
| U_DL_P_R #1 ( buf_Q , D , GATE , reset ) ; |
| `else |
| reg notifier; |
| wire COND0 ; |
| wire D_delayed, GATE_delayed, RESET_delayed ; |
| not (reset,RESETB_delayed); |
| U_DL_P_R_NO #0.001 ( buf_Q , D_delayed , GATE_delayed , reset , notifier ) ; |
| |
| assign COND0 = (RESETB_delayed === 1'b1); |
| specify |
| (negedge RESETB => (Q +: RESETB ) ) = (0:0:0,0:0:0); // delay is tfall |
| (posedge RESETB => (Q +: RESETB ) ) = (0:0:0,0:0:0); // delay is trise |
| (D +=> Q ) = (0:0:0,0:0:0); // delays are tris,tfall |
| (posedge GATE => (Q : GATE ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| |
| (negedge RESETB => (QN -: RESETB ) ) = (0:0:0,0:0:0); // delay is trise |
| (posedge RESETB => (QN -: RESETB ) ) = (0:0:0,0:0:0); // delay is tfall |
| (D -=> QN ) = (0:0:0,0:0:0); // delays are tris,tfall |
| (posedge GATE => (QN : GATE ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| |
| $width ( posedge GATE &&& (RESETB===1'b1) , 0:0:0, 0, notifier); |
| $width ( negedge GATE &&& (RESETB===1'b1) , 0:0:0, 0, notifier); |
| $width (negedge RESETB , 0.5, 0, notifier); |
| $recrem ( posedge RESETB , negedge GATE , 0:0:0, 0:0:0, notifier , , , RESETB_delayed , GATE_delayed ) ; |
| $recovery ( posedge RESETB , negedge GATE , 0:0:0, 0:0:0, notifier , , , RESETB_delayed , GATE_delayed ) ; |
| $hold ( negedge GATE , posedge RESETB , 0:0:0, notifier ) ; |
| $setuphold ( negedge GATE , posedge D , 0:0:0, 0:0:0, notifier , , COND0 , GATE_delayed , D_delayed ) ; |
| $setuphold ( negedge GATE , negedge D , 0:0:0, 0:0:0, notifier , , COND0 , GATE_delayed , D_delayed ) ; |
| endspecify |
| `endif |
| |
| buf (Q,buf_Q); |
| not (QN,buf_Q); |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_dlrbp_2 (RESETB,D,GATE,Q,QN); |
| |
| output Q,QN; |
| input RESETB,D,GATE; |
| wire reset; |
| |
| `ifdef functional |
| not (reset,RESETB); |
| U_DL_P_R #1 ( buf_Q , D , GATE , reset ) ; |
| `else |
| reg notifier; |
| wire COND0 ; |
| wire D_delayed, GATE_delayed, RESET_delayed ; |
| not (reset,RESETB_delayed); |
| U_DL_P_R_NO #0.001 ( buf_Q , D_delayed , GATE_delayed , reset , notifier ) ; |
| |
| assign COND0 = (RESETB_delayed === 1'b1); |
| specify |
| (negedge RESETB => (Q +: RESETB ) ) = (0:0:0,0:0:0); // delay is tfall |
| (posedge RESETB => (Q +: RESETB ) ) = (0:0:0,0:0:0); // delay is trise |
| (D +=> Q ) = (0:0:0,0:0:0); // delays are tris,tfall |
| (posedge GATE => (Q : GATE ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| |
| (negedge RESETB => (QN -: RESETB ) ) = (0:0:0,0:0:0); // delay is trise |
| (posedge RESETB => (QN -: RESETB ) ) = (0:0:0,0:0:0); // delay is tfall |
| (D -=> QN ) = (0:0:0,0:0:0); // delays are tris,tfall |
| (posedge GATE => (QN : GATE ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| |
| $width ( posedge GATE &&& (RESETB===1'b1) , 0:0:0, 0, notifier); |
| $width ( negedge GATE &&& (RESETB===1'b1) , 0:0:0, 0, notifier); |
| $width (negedge RESETB , 0.5, 0, notifier); |
| $recrem ( posedge RESETB , negedge GATE , 0:0:0, 0:0:0, notifier , , , RESETB_delayed , GATE_delayed ) ; |
| $recovery ( posedge RESETB , negedge GATE , 0:0:0, 0:0:0, notifier , , , RESETB_delayed , GATE_delayed ) ; |
| $hold ( negedge GATE , posedge RESETB , 0:0:0, notifier ) ; |
| $setuphold ( negedge GATE , posedge D , 0:0:0, 0:0:0, notifier , , COND0 , GATE_delayed , D_delayed ) ; |
| $setuphold ( negedge GATE , negedge D , 0:0:0, 0:0:0, notifier , , COND0 , GATE_delayed , D_delayed ) ; |
| endspecify |
| `endif |
| |
| buf (Q,buf_Q); |
| not (QN,buf_Q); |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_dlrtn_1 (RESETB,D,GATEN,Q); |
| |
| output Q; |
| input RESETB,D,GATEN; |
| wire reset, intgate; |
| |
| `ifdef functional |
| not (reset,RESETB); |
| not (intgate,GATEN); |
| U_DL_P_R #1 ( buf_Q , D , intgate , reset ) ; |
| `else |
| reg notifier; |
| wire COND0 ; |
| wire D_delayed, GATEN_delayed, RESET_delayed ; |
| not (reset,RESETB_delayed); |
| not (intgate,GATEN_delayed); |
| U_DL_P_R_NO #0.001 ( buf_Q , D_delayed , intgate , reset , notifier ) ; |
| |
| assign COND0 = (RESETB_delayed === 1'b1); |
| specify |
| (negedge RESETB => (Q +: RESETB ) ) = (0:0:0,0:0:0); // delay is tfall |
| (posedge RESETB => (Q +: RESETB ) ) = (0:0:0,0:0:0); // delay is trise |
| (D +=> Q ) = (0:0:0,0:0:0); // delays are tris,tfall |
| (negedge GATEN => (Q : GATEN ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| |
| $width (posedge GATEN &&& (RESETB===1'b1) , 0:0:0, 0, notifier); |
| $width (negedge GATEN &&& (RESETB===1'b1) , 0:0:0, 0, notifier); |
| $width (negedge RESETB , 0.5, 0, notifier); |
| $recrem ( posedge RESETB , posedge GATEN , 0:0:0, 0:0:0, notifier , , , RESETB_delayed , GATEN_delayed ) ; |
| $recovery ( posedge RESETB , posedge GATEN , 0:0:0, 0:0:0, notifier , , , RESETB_delayed , GATEN_delayed ) ; |
| $hold ( posedge GATEN , posedge RESETB , 0:0:0, notifier ) ; |
| $setuphold ( posedge GATEN , posedge D , 0:0:0, 0:0:0, notifier , , COND0 , GATEN_delayed , D_delayed ) ; |
| $setuphold ( posedge GATEN , negedge D , 0:0:0, 0:0:0, notifier , , COND0 , GATEN_delayed , D_delayed ) ; |
| endspecify |
| `endif |
| |
| buf (Q,buf_Q); |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_dlrtn_2 (RESETB,D,GATEN,Q); |
| |
| output Q; |
| input RESETB,D,GATEN; |
| wire reset, intgate; |
| |
| `ifdef functional |
| not (reset,RESETB); |
| not (intgate,GATEN); |
| U_DL_P_R #1 ( buf_Q , D , intgate , reset ) ; |
| `else |
| reg notifier; |
| wire COND0 ; |
| wire D_delayed, GATEN_delayed, RESET_delayed ; |
| not (reset,RESETB_delayed); |
| not (intgate,GATEN_delayed); |
| U_DL_P_R_NO #0.001 ( buf_Q , D_delayed , intgate , reset , notifier ) ; |
| |
| assign COND0 = (RESETB_delayed === 1'b1); |
| specify |
| (negedge RESETB => (Q +: RESETB ) ) = (0:0:0,0:0:0); // delay is tfall |
| (posedge RESETB => (Q +: RESETB ) ) = (0:0:0,0:0:0); // delay is trise |
| (D +=> Q ) = (0:0:0,0:0:0); // delays are tris,tfall |
| (negedge GATEN => (Q : GATEN ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| |
| $width (posedge GATEN &&& (RESETB===1'b1) , 0:0:0, 0, notifier); |
| $width (negedge GATEN &&& (RESETB===1'b1) , 0:0:0, 0, notifier); |
| $width (negedge RESETB , 0.5, 0, notifier); |
| $recrem ( posedge RESETB , posedge GATEN , 0:0:0, 0:0:0, notifier , , , RESETB_delayed , GATEN_delayed ) ; |
| $recovery ( posedge RESETB , posedge GATEN , 0:0:0, 0:0:0, notifier , , , RESETB_delayed , GATEN_delayed ) ; |
| $hold ( posedge GATEN , posedge RESETB , 0:0:0, notifier ) ; |
| $setuphold ( posedge GATEN , posedge D , 0:0:0, 0:0:0, notifier , , COND0 , GATEN_delayed , D_delayed ) ; |
| $setuphold ( posedge GATEN , negedge D , 0:0:0, 0:0:0, notifier , , COND0 , GATEN_delayed , D_delayed ) ; |
| endspecify |
| `endif |
| |
| buf (Q,buf_Q); |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_dlrtn_4 (RESETB,D,GATEN,Q); |
| |
| output Q; |
| input RESETB,D,GATEN; |
| wire reset, intgate; |
| |
| `ifdef functional |
| not (reset,RESETB); |
| not (intgate,GATEN); |
| U_DL_P_R #1 ( buf_Q , D , intgate , reset ) ; |
| `else |
| reg notifier; |
| wire COND0 ; |
| wire D_delayed, GATEN_delayed, RESET_delayed ; |
| not (reset,RESETB_delayed); |
| not (intgate,GATEN_delayed); |
| U_DL_P_R_NO #0.001 ( buf_Q , D_delayed , intgate , reset , notifier ) ; |
| |
| assign COND0 = (RESETB_delayed === 1'b1); |
| specify |
| (negedge RESETB => (Q +: RESETB ) ) = (0:0:0,0:0:0); // delay is tfall |
| (posedge RESETB => (Q +: RESETB ) ) = (0:0:0,0:0:0); // delay is trise |
| (D +=> Q ) = (0:0:0,0:0:0); // delays are tris,tfall |
| (negedge GATEN => (Q : GATEN ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| |
| $width (posedge GATEN &&& (RESETB===1'b1) , 0:0:0, 0, notifier); |
| $width (negedge GATEN &&& (RESETB===1'b1) , 0:0:0, 0, notifier); |
| $width (negedge RESETB , 0.5, 0, notifier); |
| $recrem ( posedge RESETB , posedge GATEN , 0:0:0, 0:0:0, notifier , , , RESETB_delayed , GATEN_delayed ) ; |
| $recovery ( posedge RESETB , posedge GATEN , 0:0:0, 0:0:0, notifier , , , RESETB_delayed , GATEN_delayed ) ; |
| $hold ( posedge GATEN , posedge RESETB , 0:0:0, notifier ) ; |
| $setuphold ( posedge GATEN , posedge D , 0:0:0, 0:0:0, notifier , , COND0 , GATEN_delayed , D_delayed ) ; |
| $setuphold ( posedge GATEN , negedge D , 0:0:0, 0:0:0, notifier , , COND0 , GATEN_delayed , D_delayed ) ; |
| endspecify |
| `endif |
| |
| buf (Q,buf_Q); |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_dlrtp_1 (RESETB,D,GATE,Q); |
| |
| output Q; |
| input RESETB,D,GATE; |
| wire reset; |
| |
| `ifdef functional |
| not (reset,RESETB); |
| U_DL_P_R #1 ( buf_Q , D , GATE , reset ) ; |
| `else |
| reg notifier; |
| wire COND0 ; |
| wire D_delayed, GATE_delayed, RESET_delayed ; |
| not (reset,RESETB_delayed); |
| U_DL_P_R_NO #0.001 ( buf_Q , D_delayed , GATE_delayed , reset , notifier ) ; |
| |
| assign COND0 = (RESETB_delayed === 1'b1); |
| specify |
| (negedge RESETB => (Q +: RESETB ) ) = (0:0:0,0:0:0); // delay is tfall |
| (posedge RESETB => (Q +: RESETB ) ) = (0:0:0,0:0:0); // delay is trise |
| (D +=> Q ) = (0:0:0,0:0:0); // delays are tris,tfall |
| (posedge GATE => (Q : GATE ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| |
| $width ( posedge GATE &&& (RESETB===1'b1) , 0:0:0, 0, notifier); |
| $width ( negedge GATE &&& (RESETB===1'b1) , 0:0:0, 0, notifier); |
| $width ( negedge RESETB , 0.5, 0, notifier); |
| $recrem ( posedge RESETB , negedge GATE , 0:0:0, 0:0:0, notifier , , , RESETB_delayed , GATE_delayed ) ; |
| $recovery ( posedge RESETB , negedge GATE , 0:0:0, 0:0:0, notifier , , , RESETB_delayed , GATE_delayed ) ; |
| $hold ( negedge GATE , posedge RESETB , 0:0:0, notifier ) ; |
| $setuphold ( negedge GATE , posedge D , 0:0:0, 0:0:0, notifier , , COND0 , GATE_delayed , D_delayed ) ; |
| $setuphold ( negedge GATE , negedge D , 0:0:0, 0:0:0, notifier , , COND0 , GATE_delayed , D_delayed ) ; |
| endspecify |
| `endif |
| |
| buf (Q,buf_Q); |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_dlrtp_2 (RESETB,D,GATE,Q); |
| |
| output Q; |
| input RESETB,D,GATE; |
| wire reset; |
| |
| `ifdef functional |
| not (reset,RESETB); |
| U_DL_P_R #1 ( buf_Q , D , GATE , reset ) ; |
| `else |
| reg notifier; |
| wire COND0 ; |
| wire D_delayed, GATE_delayed, RESET_delayed ; |
| not (reset,RESETB_delayed); |
| U_DL_P_R_NO #0.001 ( buf_Q , D_delayed , GATE_delayed , reset , notifier ) ; |
| |
| assign COND0 = (RESETB_delayed === 1'b1); |
| specify |
| (negedge RESETB => (Q +: RESETB ) ) = (0:0:0,0:0:0); // delay is tfall |
| (posedge RESETB => (Q +: RESETB ) ) = (0:0:0,0:0:0); // delay is trise |
| (D +=> Q ) = (0:0:0,0:0:0); // delays are tris,tfall |
| (posedge GATE => (Q : GATE ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| |
| $width ( posedge GATE &&& (RESETB===1'b1) , 0:0:0, 0, notifier); |
| $width ( negedge GATE &&& (RESETB===1'b1) , 0:0:0, 0, notifier); |
| $width (negedge RESETB , 0.5, 0, notifier); |
| $recrem ( posedge RESETB , negedge GATE , 0:0:0, 0:0:0, notifier , , , RESETB_delayed , GATE_delayed ) ; |
| $recovery ( posedge RESETB , negedge GATE , 0:0:0, 0:0:0, notifier , , , RESETB_delayed , GATE_delayed ) ; |
| $hold ( negedge GATE , posedge RESETB , 0:0:0, notifier ) ; |
| $setuphold ( negedge GATE , posedge D , 0:0:0, 0:0:0, notifier , , COND0 , GATE_delayed , D_delayed ) ; |
| $setuphold ( negedge GATE , negedge D , 0:0:0, 0:0:0, notifier , , COND0 , GATE_delayed , D_delayed ) ; |
| endspecify |
| `endif |
| |
| buf (Q,buf_Q); |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_dlrtp_4 (RESETB,D,GATE,Q); |
| |
| output Q; |
| input RESETB,D,GATE; |
| wire reset; |
| |
| `ifdef functional |
| not (reset,RESETB); |
| U_DL_P_R #1 ( buf_Q , D , GATE , reset ) ; |
| `else |
| reg notifier; |
| wire COND0 ; |
| wire D_delayed, GATE_delayed, RESET_delayed ; |
| not (reset,RESETB_delayed); |
| U_DL_P_R_NO #0.001 ( buf_Q , D_delayed , GATE_delayed , reset , notifier ) ; |
| |
| assign COND0 = (RESETB_delayed === 1'b1); |
| specify |
| (negedge RESETB => (Q +: RESETB ) ) = (0:0:0,0:0:0); // delay is tfall |
| (posedge RESETB => (Q +: RESETB ) ) = (0:0:0,0:0:0); // delay is trise |
| (D +=> Q ) = (0:0:0,0:0:0); // delays are tris,tfall |
| (posedge GATE => (Q : GATE ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| |
| $width ( posedge GATE &&& (RESETB===1'b1) , 0:0:0, 0, notifier); |
| $width ( negedge GATE &&& (RESETB===1'b1) , 0:0:0, 0, notifier); |
| $width (negedge RESETB , 0.5, 0, notifier); |
| $recrem ( posedge RESETB , negedge GATE , 0:0:0, 0:0:0, notifier , , , RESETB_delayed , GATE_delayed ) ; |
| $recovery ( posedge RESETB , negedge GATE , 0:0:0, 0:0:0, notifier , , , RESETB_delayed , GATE_delayed ) ; |
| $hold ( negedge GATE , posedge RESETB , 0:0:0, notifier ) ; |
| $setuphold ( negedge GATE , posedge D , 0:0:0, 0:0:0, notifier , , COND0 , GATE_delayed , D_delayed ) ; |
| $setuphold ( negedge GATE , negedge D , 0:0:0, 0:0:0, notifier , , COND0 , GATE_delayed , D_delayed ) ; |
| endspecify |
| `endif |
| |
| buf (Q,buf_Q); |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_dlxbn_1 (Q, QN, D, GATEN); |
| |
| output Q, QN; |
| input D,GATEN; |
| |
| wire gate, buf_Q, GATEN_delayed , D_delayed; |
| |
| `ifdef functional |
| U_DL_P #1 ( buf_Q , D , gate ) ; |
| not (gate,GATEN); |
| `else |
| reg notifier; |
| U_DL_P_NO #0.001 ( buf_Q , D_delayed , gate , notifier ) ; |
| not (gate,GATEN_delayed); |
| |
| `endif |
| |
| buf (Q,buf_Q); |
| not (QN, buf_Q); |
| |
| `ifdef functional |
| `else |
| specify |
| (D +=> Q ) = (0:0:0,0:0:0); // delays are tris,tfall |
| (D -=> QN ) = (0:0:0,0:0:0); // delays are tris,tfall |
| |
| (negedge GATEN => (Q +: D ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| (negedge GATEN => (QN -: D ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| |
| $width (posedge GATEN , 0:0:0, 0, notifier); |
| $width (negedge GATEN , 0:0:0, 0, notifier); |
| |
| $setuphold ( posedge GATEN , posedge D , 0:0:0, 0:0:0, notifier , , , GATEN_delayed , D_delayed ) ; |
| $setuphold ( posedge GATEN , negedge D , 0:0:0, 0:0:0, notifier , , , GATEN_delayed , D_delayed ) ; |
| endspecify |
| `endif |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_dlxbn_2 (Q, QN, D, GATEN); |
| |
| output Q, QN; |
| input D,GATEN; |
| |
| wire gate, buf_Q, GATEN_delayed , D_delayed; |
| |
| `ifdef functional |
| U_DL_P #1 ( buf_Q , D , gate ) ; |
| not (gate,GATEN); |
| `else |
| reg notifier; |
| U_DL_P_NO #0.001 ( buf_Q , D_delayed , gate , notifier ) ; |
| not (gate,GATEN_delayed); |
| |
| `endif |
| |
| buf (Q,buf_Q); |
| not (QN, buf_Q); |
| |
| `ifdef functional |
| `else |
| specify |
| (D +=> Q ) = (0:0:0,0:0:0); // delays are tris,tfall |
| (D -=> QN ) = (0:0:0,0:0:0); // delays are tris,tfall |
| |
| (negedge GATEN => (Q +: D ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| (negedge GATEN => (QN -: D ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| |
| $width (posedge GATEN , 0:0:0, 0, notifier); |
| $width (negedge GATEN , 0:0:0, 0, notifier); |
| |
| $setuphold ( posedge GATEN , posedge D , 0:0:0, 0:0:0, notifier , , , GATEN_delayed , D_delayed ) ; |
| $setuphold ( posedge GATEN , negedge D , 0:0:0, 0:0:0, notifier , , , GATEN_delayed , D_delayed ) ; |
| endspecify |
| `endif |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_dlxbp_1 (Q, QN, D, GATE); |
| |
| output Q, QN; |
| input D,GATE; |
| |
| wire buf_Q, GATE_delayed , D_delayed; |
| |
| `ifdef functional |
| U_DL_P #1 ( buf_Q , D , GATE ) ; |
| `else |
| reg notifier; |
| U_DL_P_NO #0.001 ( buf_Q , D_delayed , GATE_delayed , notifier ) ; |
| `endif |
| |
| buf (Q,buf_Q); |
| not (QN, buf_Q); |
| |
| `ifdef functional |
| `else |
| specify |
| (D +=> Q ) = (0:0:0,0:0:0); // delays are tris,tfall |
| (D -=> QN ) = (0:0:0,0:0:0); // delays are tris,tfall |
| |
| (posedge GATE => (Q +: D ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| (posedge GATE => (QN -: D ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| |
| $width (posedge GATE , 0:0:0, 0, notifier); |
| $width (negedge GATE , 0:0:0, 0, notifier); |
| |
| $setuphold ( negedge GATE , posedge D , 0:0:0, 0:0:0, notifier , , , GATE_delayed , D_delayed ) ; |
| $setuphold ( negedge GATE , negedge D , 0:0:0, 0:0:0, notifier , , , GATE_delayed , D_delayed ) ; |
| endspecify |
| `endif |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_dlxtn_1 (Q, D, GATEN); |
| |
| output Q; |
| input D,GATEN; |
| |
| wire gate, buf_Q, GATEN_delayed , D_delayed; |
| |
| `ifdef functional |
| U_DL_P #1 ( buf_Q , D , gate ) ; |
| not(gate,GATEN); |
| `else |
| reg notifier; |
| U_DL_P_NO #0.001 ( buf_Q , D_delayed , gate , notifier ) ; |
| not (gate,GATEN_delayed); |
| |
| `endif |
| |
| buf (Q,buf_Q); |
| |
| `ifdef functional |
| `else |
| specify |
| (D +=> Q ) = (0:0:0,0:0:0); // delays are tris,tfall |
| |
| (negedge GATEN => (Q +: D ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| |
| $width (posedge GATEN , 0:0:0, 0, notifier); |
| $width (negedge GATEN , 0:0:0, 0, notifier); |
| |
| $setuphold ( posedge GATEN , posedge D , 0:0:0, 0:0:0, notifier , , , GATEN_delayed , D_delayed ) ; |
| $setuphold ( posedge GATEN , negedge D , 0:0:0, 0:0:0, notifier , , , GATEN_delayed , D_delayed ) ; |
| endspecify |
| `endif |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_dlxtn_2 (Q, D, GATEN); |
| |
| output Q; |
| input D,GATEN; |
| |
| wire gate, buf_Q, GATEN_delayed , D_delayed; |
| |
| `ifdef functional |
| U_DL_P #1 ( buf_Q , D , gate ) ; |
| not(gate,GATEN); |
| `else |
| reg notifier; |
| U_DL_P_NO #0.001 ( buf_Q , D_delayed , gate , notifier ) ; |
| not (gate,GATEN_delayed); |
| |
| `endif |
| |
| buf (Q,buf_Q); |
| |
| `ifdef functional |
| `else |
| specify |
| (D +=> Q ) = (0:0:0,0:0:0); // delays are tris,tfall |
| |
| (negedge GATEN => (Q +: D ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| |
| $width (posedge GATEN , 0:0:0, 0, notifier); |
| $width (negedge GATEN , 0:0:0, 0, notifier); |
| |
| $setuphold ( posedge GATEN , posedge D , 0:0:0, 0:0:0, notifier , , , GATEN_delayed , D_delayed ) ; |
| $setuphold ( posedge GATEN , negedge D , 0:0:0, 0:0:0, notifier , , , GATEN_delayed , D_delayed ) ; |
| endspecify |
| `endif |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_dlxtn_4 (Q, D, GATEN); |
| |
| output Q; |
| input D,GATEN; |
| |
| wire gate, buf_Q, GATEN_delayed , D_delayed; |
| |
| `ifdef functional |
| U_DL_P #1 ( buf_Q , D , gate ) ; |
| not(gate,GATEN); |
| `else |
| reg notifier; |
| U_DL_P_NO #0.001 ( buf_Q , D_delayed , gate , notifier ) ; |
| not (gate,GATEN_delayed); |
| |
| `endif |
| |
| buf (Q,buf_Q); |
| |
| `ifdef functional |
| `else |
| specify |
| (D +=> Q ) = (0:0:0,0:0:0); // delays are tris,tfall |
| |
| (negedge GATEN => (Q +: D ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| |
| $width (posedge GATEN , 0:0:0, 0, notifier); |
| $width (negedge GATEN , 0:0:0, 0, notifier); |
| |
| $setuphold ( posedge GATEN , posedge D , 0:0:0, 0:0:0, notifier , , , GATEN_delayed , D_delayed ) ; |
| $setuphold ( posedge GATEN , negedge D , 0:0:0, 0:0:0, notifier , , , GATEN_delayed , D_delayed ) ; |
| endspecify |
| `endif |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_dlxtp_1 (Q, D, GATE); |
| |
| output Q; |
| input D,GATE; |
| |
| wire buf_Q, GATE_delayed , D_delayed; |
| |
| `ifdef functional |
| U_DL_P #1 ( buf_Q , D , GATE ) ; |
| `else |
| reg notifier; |
| U_DL_P_NO #0.001 ( buf_Q , D_delayed , GATE_delayed , notifier ) ; |
| `endif |
| |
| buf (Q,buf_Q); |
| |
| `ifdef functional |
| `else |
| specify |
| (D +=> Q ) = (0:0:0,0:0:0); // delays are tris,tfall |
| |
| (posedge GATE => (Q +: D ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| |
| $width (posedge GATE , 0:0:0, 0, notifier); |
| $width (negedge GATE , 0:0:0, 0, notifier); |
| |
| $setuphold ( negedge GATE , posedge D , 0:0:0, 0:0:0, notifier , , , GATE_delayed , D_delayed ) ; |
| $setuphold ( negedge GATE , negedge D , 0:0:0, 0:0:0, notifier , , , GATE_delayed , D_delayed ) ; |
| endspecify |
| `endif |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_dlygate4s15_1 ( X , A ); |
| output X ; |
| input A ; |
| |
| wire X , A ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X ) = (0:0:0,0:0:0); // delays are tris,tfall |
| endspecify |
| `endif |
| |
| buf #0.001 ( X , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_dlygate4s18_1 ( X , A ); |
| output X ; |
| input A ; |
| |
| wire X , A ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X ) = (0:0:0,0:0:0); // delays are tris,tfall |
| endspecify |
| `endif |
| |
| buf #0.001 ( X , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_dlygate4s50_1 ( X , A ); |
| output X ; |
| input A ; |
| |
| wire X , A ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X ) = (0:0:0,0:0:0); // delays are tris,tfall |
| endspecify |
| `endif |
| |
| buf #0.001 ( X , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_dlymetal6s2s_1 ( X , A ); |
| output X ; |
| input A ; |
| |
| wire X , A ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X ) = (0:0:0,0:0:0); // delays are tris,tfall |
| endspecify |
| `endif |
| |
| buf #0.001 ( X , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_dlymetal6s4s_1 ( X , A ); |
| output X ; |
| input A ; |
| |
| wire X , A ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X ) = (0:0:0,0:0:0); // delays are tris,tfall |
| endspecify |
| `endif |
| |
| buf #0.001 ( X , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_dlymetal6s6s_1 ( X , A ); |
| output X ; |
| input A ; |
| |
| wire X , A ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X ) = (0:0:0,0:0:0); // delays are tris,tfall |
| endspecify |
| `endif |
| |
| buf #0.001 ( X , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_ebufn_1 ( Z , A , TEB ); |
| |
| output Z ; |
| input A , TEB ; |
| |
| bufif0 #0.001 (Z , A , TEB ); |
| |
| `ifdef functional |
| `else |
| specify |
| if( ~TEB ) (A +=> Z ) = (0.000:0.000:0.000,0.000:0.000:0.000); |
| (TEB => Z ) = (0.000:0.000:0.000,0.000:0.000:0.000,0.000:0.000:0.000,0.000:0.000:0.000,0.000:0.000:0.000,0.000:0.000:0.000); // delays are t01,t10,t0Z,tZ1,t1Z,tZ0 |
| endspecify |
| `endif |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_ebufn_2 ( Z , A , TEB ); |
| |
| output Z ; |
| input A , TEB ; |
| |
| bufif0 #0.001 (Z , A , TEB ); |
| |
| `ifdef functional |
| `else |
| specify |
| if( ~TEB ) (A +=> Z ) = (0.000:0.000:0.000,0.000:0.000:0.000); |
| (TEB => Z ) = (0.000:0.000:0.000,0.000:0.000:0.000,0.000:0.000:0.000,0.000:0.000:0.000,0.000:0.000:0.000,0.000:0.000:0.000); // delays are t01,t10,t0Z,tZ1,t1Z,tZ0 |
| endspecify |
| `endif |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_ebufn_4 ( Z , A , TEB ); |
| |
| output Z ; |
| input A , TEB ; |
| |
| bufif0 #0.001 (Z , A , TEB ); |
| |
| `ifdef functional |
| `else |
| specify |
| if( ~TEB ) (A +=> Z ) = (0.000:0.000:0.000,0.000:0.000:0.000); |
| (TEB => Z ) = (0.000:0.000:0.000,0.000:0.000:0.000,0.000:0.000:0.000,0.000:0.000:0.000,0.000:0.000:0.000,0.000:0.000:0.000); // delays are t01,t10,t0Z,tZ1,t1Z,tZ0 |
| endspecify |
| `endif |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_ebufn_8 ( Z , A , TEB ); |
| |
| output Z ; |
| input A , TEB ; |
| |
| bufif0 #0.001 (Z , A , TEB ); |
| |
| `ifdef functional |
| `else |
| specify |
| if( ~TEB ) (A +=> Z ) = (0.000:0.000:0.000,0.000:0.000:0.000); |
| (TEB => Z ) = (0.000:0.000:0.000,0.000:0.000:0.000,0.000:0.000:0.000,0.000:0.000:0.000,0.000:0.000:0.000,0.000:0.000:0.000); // delays are t01,t10,t0Z,tZ1,t1Z,tZ0 |
| endspecify |
| `endif |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_edfxbp_1 (Q,QN,CLK,D,DE); |
| |
| output Q,QN; |
| input CLK,D,DE; |
| wire buf_Q; |
| |
| `ifdef functional |
| U_EDF_P #1 ( buf_Q , D , CLK , DE ) ; |
| `else |
| reg notifier; |
| wire D_delayed, DE_delayed, CLK_delayed ; |
| U_EDF_P_NO #0.001 ( buf_Q , D_delayed , CLK_delayed , DE_delayed , notifier ) ; |
| |
| specify |
| (posedge CLK => (Q : CLK ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| (posedge CLK => (QN : CLK ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| $width (posedge CLK , 0:0:0, 0, notifier); |
| $width (negedge CLK , 0:0:0, 0, notifier); |
| $setuphold ( posedge CLK , posedge DE , 0:0:0, 0:0:0, notifier , , , CLK_delayed , DE_delayed ) ; |
| $setuphold ( posedge CLK , negedge DE , 0:0:0, 0:0:0, notifier , , , CLK_delayed , DE_delayed ) ; |
| $setuphold ( posedge CLK , posedge D , 0:0:0, 0:0:0, notifier , , DE_delayed , CLK_delayed , D_delayed ) ; |
| $setuphold ( posedge CLK , negedge D , 0:0:0, 0:0:0, notifier , , DE_delayed , CLK_delayed , D_delayed ) ; |
| endspecify |
| `endif |
| |
| buf (Q,buf_Q); |
| not (QN,buf_Q); |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_einvn_0 (A,TEB,Z); |
| |
| output Z; |
| input A,TEB; |
| |
| notif0 #0.001 (Z,A,TEB); |
| |
| `ifdef functional |
| `else |
| specify |
| if (~TEB ) (A -=> Z ) = (0:0:0,0:0:0); // delays are tris,tfall |
| (TEB => Z ) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); // delays are t01,t10,t0Z,tZ1,t1Z,tZ0 |
| endspecify |
| `endif |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_einvn_1 (A,TEB,Z); |
| |
| output Z; |
| input A,TEB; |
| |
| notif0 #0.001 (Z,A,TEB); |
| |
| `ifdef functional |
| `else |
| specify |
| if (~TEB ) (A -=> Z ) = (0:0:0,0:0:0); // delays are tris,tfall |
| (TEB => Z ) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); // delays are t01,t10,t0Z,tZ1,t1Z,tZ0 |
| endspecify |
| `endif |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_einvn_2 (A,TEB,Z); |
| |
| output Z; |
| input A,TEB; |
| |
| notif0 #0.001 (Z,A,TEB); |
| |
| `ifdef functional |
| `else |
| specify |
| if (~TEB ) (A -=> Z ) = (0:0:0,0:0:0); // delays are tris,tfall |
| (TEB => Z ) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); // delays are t01,t10,t0Z,tZ1,t1Z,tZ0 |
| endspecify |
| `endif |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_einvn_4 (A,TEB,Z); |
| |
| output Z; |
| input A,TEB; |
| |
| notif0 #0.001 (Z,A,TEB); |
| |
| `ifdef functional |
| `else |
| specify |
| if (~TEB ) (A -=> Z ) = (0:0:0,0:0:0); // delays are tris,tfall |
| (TEB => Z ) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); // delays are t01,t10,t0Z,tZ1,t1Z,tZ0 |
| endspecify |
| `endif |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_einvn_8 (A,TEB,Z); |
| |
| output Z; |
| input A,TEB; |
| |
| notif0 #0.001 (Z,A,TEB); |
| |
| `ifdef functional |
| `else |
| specify |
| if (~TEB ) (A -=> Z ) = (0:0:0,0:0:0); // delays are tris,tfall |
| (TEB => Z ) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); // delays are t01,t10,t0Z,tZ1,t1Z,tZ0 |
| endspecify |
| `endif |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_einvp_0 (A,TE,Z); |
| |
| output Z; |
| input A,TE; |
| |
| notif1 #0.001 (Z,A,TE); |
| |
| `ifdef functional |
| `else |
| specify |
| if (TE ) (A -=> Z ) = (0:0:0,0:0:0); // delays are tris,tfall |
| (TE => Z ) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); // delays are t01,t10,t0Z,tZ1,t1Z,tZ0 |
| endspecify |
| `endif |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_einvp_1 (A,TE,Z); |
| |
| output Z; |
| input A,TE; |
| |
| notif1 #0.001 (Z,A,TE); |
| |
| `ifdef functional |
| `else |
| specify |
| if (TE ) (A -=> Z ) = (0:0:0,0:0:0); // delays are tris,tfall |
| (TE => Z ) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); // delays are t01,t10,t0Z,tZ1,t1Z,tZ0 |
| endspecify |
| `endif |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_einvp_2 (A,TE,Z); |
| |
| output Z; |
| input A,TE; |
| |
| notif1 #0.001 (Z,A,TE); |
| |
| `ifdef functional |
| `else |
| specify |
| if (TE ) (A -=> Z ) = (0:0:0,0:0:0); // delays are tris,tfall |
| (TE => Z ) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); // delays are t01,t10,t0Z,tZ1,t1Z,tZ0 |
| endspecify |
| `endif |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_einvp_4 (A,TE,Z); |
| |
| output Z; |
| input A,TE; |
| |
| notif1 #0.001 (Z,A,TE); |
| |
| `ifdef functional |
| `else |
| specify |
| if (TE ) (A -=> Z ) = (0:0:0,0:0:0); // delays are tris,tfall |
| (TE => Z ) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); // delays are t01,t10,t0Z,tZ1,t1Z,tZ0 |
| endspecify |
| `endif |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_einvp_8 (A,TE,Z); |
| |
| output Z; |
| input A,TE; |
| |
| notif1 #0.001 (Z,A,TE); |
| |
| `ifdef functional |
| `else |
| specify |
| if (TE ) (A -=> Z ) = (0:0:0,0:0:0); // delays are tris,tfall |
| (TE => Z ) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); // delays are t01,t10,t0Z,tZ1,t1Z,tZ0 |
| endspecify |
| `endif |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_fa_0 ( COUT , SUM , A , B , CIN ); |
| output COUT , SUM ; |
| input A , B , CIN ; |
| |
| wire COUT , SUM , A , B ; |
| wire CIN , csi_opt_303, csi_opt_278, csi_opt_279 ; |
| wire csi_opt_276, csi_opt_275, csi_opt_277 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((!B&CIN)) (A +=> COUT) = (0:0:0,0:0:0); |
| if ((B&!CIN)) (A +=> COUT) = (0:0:0,0:0:0); |
| if ((!A&CIN)) (B +=> COUT) = (0:0:0,0:0:0); |
| if ((A&!CIN)) (B +=> COUT) = (0:0:0,0:0:0); |
| if ((!A&B)) (CIN +=> COUT) = (0:0:0,0:0:0); |
| if ((A&!B)) (CIN +=> COUT) = (0:0:0,0:0:0); |
| if ((!B&!CIN)) (A +=> SUM) = (0:0:0,0:0:0); |
| if ((!B&CIN)) (A -=> SUM) = (0:0:0,0:0:0); |
| if ((B&!CIN)) (A -=> SUM) = (0:0:0,0:0:0); |
| if ((B&CIN)) (A +=> SUM) = (0:0:0,0:0:0); |
| if ((!A&!CIN)) (B +=> SUM) = (0:0:0,0:0:0); |
| if ((!A&CIN)) (B -=> SUM) = (0:0:0,0:0:0); |
| if ((A&!CIN)) (B -=> SUM) = (0:0:0,0:0:0); |
| if ((A&CIN)) (B +=> SUM) = (0:0:0,0:0:0); |
| if ((!A&!B)) (CIN +=> SUM) = (0:0:0,0:0:0); |
| if ((!A&B)) (CIN -=> SUM) = (0:0:0,0:0:0); |
| if ((A&!B)) (CIN -=> SUM) = (0:0:0,0:0:0); |
| if ((A&B)) (CIN +=> SUM) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or ( csi_opt_303 , CIN , B ) ; |
| and ( csi_opt_278 , csi_opt_303 , A ) ; |
| and ( csi_opt_279 , B , CIN ) ; |
| or #0.001 ( COUT , csi_opt_279 , csi_opt_278 ) ; |
| and ( csi_opt_276 , CIN , A , B ) ; |
| nor ( csi_opt_275 , A , csi_opt_303 ) ; |
| nor ( csi_opt_277 , csi_opt_275 , COUT ) ; |
| or #0.001 ( SUM , csi_opt_277 , csi_opt_276 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_fa_1 ( COUT , SUM , A , B , CIN ); |
| output COUT , SUM ; |
| input A , B , CIN ; |
| |
| wire COUT , SUM , A , B ; |
| wire CIN , csi_opt_303, csi_opt_278, csi_opt_279 ; |
| wire csi_opt_276, csi_opt_275, csi_opt_277 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((!B&CIN)) (A +=> COUT) = (0:0:0,0:0:0); |
| if ((B&!CIN)) (A +=> COUT) = (0:0:0,0:0:0); |
| if ((!A&CIN)) (B +=> COUT) = (0:0:0,0:0:0); |
| if ((A&!CIN)) (B +=> COUT) = (0:0:0,0:0:0); |
| if ((!A&B)) (CIN +=> COUT) = (0:0:0,0:0:0); |
| if ((A&!B)) (CIN +=> COUT) = (0:0:0,0:0:0); |
| if ((!B&!CIN)) (A +=> SUM) = (0:0:0,0:0:0); |
| if ((!B&CIN)) (A -=> SUM) = (0:0:0,0:0:0); |
| if ((B&!CIN)) (A -=> SUM) = (0:0:0,0:0:0); |
| if ((B&CIN)) (A +=> SUM) = (0:0:0,0:0:0); |
| if ((!A&!CIN)) (B +=> SUM) = (0:0:0,0:0:0); |
| if ((!A&CIN)) (B -=> SUM) = (0:0:0,0:0:0); |
| if ((A&!CIN)) (B -=> SUM) = (0:0:0,0:0:0); |
| if ((A&CIN)) (B +=> SUM) = (0:0:0,0:0:0); |
| if ((!A&!B)) (CIN +=> SUM) = (0:0:0,0:0:0); |
| if ((!A&B)) (CIN -=> SUM) = (0:0:0,0:0:0); |
| if ((A&!B)) (CIN -=> SUM) = (0:0:0,0:0:0); |
| if ((A&B)) (CIN +=> SUM) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or ( csi_opt_303 , CIN , B ) ; |
| and ( csi_opt_278 , csi_opt_303 , A ) ; |
| and ( csi_opt_279 , B , CIN ) ; |
| or #0.001 ( COUT , csi_opt_279 , csi_opt_278 ) ; |
| and ( csi_opt_276 , CIN , A , B ) ; |
| nor ( csi_opt_275 , A , csi_opt_303 ) ; |
| nor ( csi_opt_277 , csi_opt_275 , COUT ) ; |
| or #0.001 ( SUM , csi_opt_277 , csi_opt_276 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_fa_2 ( COUT , SUM , A , B , CIN ); |
| output COUT , SUM ; |
| input A , B , CIN ; |
| |
| wire COUT , SUM , A , B ; |
| wire CIN , csi_opt_303, csi_opt_278, csi_opt_279 ; |
| wire csi_opt_276, csi_opt_275, csi_opt_277 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((!B&CIN)) (A +=> COUT) = (0:0:0,0:0:0); |
| if ((B&!CIN)) (A +=> COUT) = (0:0:0,0:0:0); |
| if ((!A&CIN)) (B +=> COUT) = (0:0:0,0:0:0); |
| if ((A&!CIN)) (B +=> COUT) = (0:0:0,0:0:0); |
| if ((!A&B)) (CIN +=> COUT) = (0:0:0,0:0:0); |
| if ((A&!B)) (CIN +=> COUT) = (0:0:0,0:0:0); |
| if ((!B&!CIN)) (A +=> SUM) = (0:0:0,0:0:0); |
| if ((!B&CIN)) (A -=> SUM) = (0:0:0,0:0:0); |
| if ((B&!CIN)) (A -=> SUM) = (0:0:0,0:0:0); |
| if ((B&CIN)) (A +=> SUM) = (0:0:0,0:0:0); |
| if ((!A&!CIN)) (B +=> SUM) = (0:0:0,0:0:0); |
| if ((!A&CIN)) (B -=> SUM) = (0:0:0,0:0:0); |
| if ((A&!CIN)) (B -=> SUM) = (0:0:0,0:0:0); |
| if ((A&CIN)) (B +=> SUM) = (0:0:0,0:0:0); |
| if ((!A&!B)) (CIN +=> SUM) = (0:0:0,0:0:0); |
| if ((!A&B)) (CIN -=> SUM) = (0:0:0,0:0:0); |
| if ((A&!B)) (CIN -=> SUM) = (0:0:0,0:0:0); |
| if ((A&B)) (CIN +=> SUM) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or ( csi_opt_303 , CIN , B ) ; |
| and ( csi_opt_278 , csi_opt_303 , A ) ; |
| and ( csi_opt_279 , B , CIN ) ; |
| or #0.001 ( COUT , csi_opt_279 , csi_opt_278 ) ; |
| and ( csi_opt_276 , CIN , A , B ) ; |
| nor ( csi_opt_275 , A , csi_opt_303 ) ; |
| nor ( csi_opt_277 , csi_opt_275 , COUT ) ; |
| or #0.001 ( SUM , csi_opt_277 , csi_opt_276 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_fa_4 ( COUT , SUM , A , B , CIN ); |
| output COUT , SUM ; |
| input A , B , CIN ; |
| |
| wire COUT , SUM , A , B ; |
| wire CIN , csi_opt_303, csi_opt_278, csi_opt_279 ; |
| wire csi_opt_276, csi_opt_275, csi_opt_277 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((!B&CIN)) (A +=> COUT) = (0:0:0,0:0:0); |
| if ((B&!CIN)) (A +=> COUT) = (0:0:0,0:0:0); |
| if ((!A&CIN)) (B +=> COUT) = (0:0:0,0:0:0); |
| if ((A&!CIN)) (B +=> COUT) = (0:0:0,0:0:0); |
| if ((!A&B)) (CIN +=> COUT) = (0:0:0,0:0:0); |
| if ((A&!B)) (CIN +=> COUT) = (0:0:0,0:0:0); |
| if ((!B&!CIN)) (A +=> SUM) = (0:0:0,0:0:0); |
| if ((!B&CIN)) (A -=> SUM) = (0:0:0,0:0:0); |
| if ((B&!CIN)) (A -=> SUM) = (0:0:0,0:0:0); |
| if ((B&CIN)) (A +=> SUM) = (0:0:0,0:0:0); |
| if ((!A&!CIN)) (B +=> SUM) = (0:0:0,0:0:0); |
| if ((!A&CIN)) (B -=> SUM) = (0:0:0,0:0:0); |
| if ((A&!CIN)) (B -=> SUM) = (0:0:0,0:0:0); |
| if ((A&CIN)) (B +=> SUM) = (0:0:0,0:0:0); |
| if ((!A&!B)) (CIN +=> SUM) = (0:0:0,0:0:0); |
| if ((!A&B)) (CIN -=> SUM) = (0:0:0,0:0:0); |
| if ((A&!B)) (CIN -=> SUM) = (0:0:0,0:0:0); |
| if ((A&B)) (CIN +=> SUM) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or ( csi_opt_303 , CIN , B ) ; |
| and ( csi_opt_278 , csi_opt_303 , A ) ; |
| and ( csi_opt_279 , B , CIN ) ; |
| or #0.001 ( COUT , csi_opt_279 , csi_opt_278 ) ; |
| and ( csi_opt_276 , CIN , A , B ) ; |
| nor ( csi_opt_275 , A , csi_opt_303 ) ; |
| nor ( csi_opt_277 , csi_opt_275 , COUT ) ; |
| or #0.001 ( SUM , csi_opt_277 , csi_opt_276 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_fah_1 ( COUT , SUM , A , B , CI ); |
| output COUT , SUM ; |
| input A , B , CI ; |
| |
| wire COUT , SUM , A , B, CI ; |
| |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((!B&CI)) (A +=> COUT) = (0:0:0,0:0:0); |
| if ((B&!CI)) (A +=> COUT) = (0:0:0,0:0:0); |
| if ((!A&CI)) (B +=> COUT) = (0:0:0,0:0:0); |
| if ((A&!CI)) (B +=> COUT) = (0:0:0,0:0:0); |
| if ((!A&B)) (CI +=> COUT) = (0:0:0,0:0:0); |
| if ((A&!B)) (CI +=> COUT) = (0:0:0,0:0:0); |
| if ((!B&!CI)) (A +=> SUM) = (0:0:0,0:0:0); |
| if ((!B&CI)) (A -=> SUM) = (0:0:0,0:0:0); |
| if ((B&!CI)) (A -=> SUM) = (0:0:0,0:0:0); |
| if ((B&CI)) (A +=> SUM) = (0:0:0,0:0:0); |
| if ((!A&!CI)) (B +=> SUM) = (0:0:0,0:0:0); |
| if ((!A&CI)) (B -=> SUM) = (0:0:0,0:0:0); |
| if ((A&!CI)) (B -=> SUM) = (0:0:0,0:0:0); |
| if ((A&CI)) (B +=> SUM) = (0:0:0,0:0:0); |
| if ((!A&!B)) (CI +=> SUM) = (0:0:0,0:0:0); |
| if ((!A&B)) (CI -=> SUM) = (0:0:0,0:0:0); |
| if ((A&!B)) (CI -=> SUM) = (0:0:0,0:0:0); |
| if ((A&B)) (CI +=> SUM) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| xor #0.001 (SUM,A,B,CI); |
| and (A$B,A,B),(A$CI,A,CI),(B$CI,B,CI); |
| or #0.001 (COUT,A$B,A$CI,B$CI); |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_fahcin_1 ( COUT , SUM , A , B , CIN ); |
| output COUT , SUM ; |
| input A , B , CIN ; |
| |
| wire COUT , SUM , A , B, CIN ; |
| wire CI ; |
| |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((!B&!CIN)) (A +=> COUT) = (0:0:0,0:0:0); |
| if ((B&CIN)) (A +=> COUT) = (0:0:0,0:0:0); |
| if ((!A&!CIN)) (B +=> COUT) = (0:0:0,0:0:0); |
| if ((A&CIN)) (B +=> COUT) = (0:0:0,0:0:0); |
| if ((!A&B)) (CIN -=> COUT) = (0:0:0,0:0:0); |
| if ((A&!B)) (CIN -=> COUT) = (0:0:0,0:0:0); |
| if ((!B&!CIN)) (A -=> SUM) = (0:0:0,0:0:0); |
| if ((!B&CIN)) (A +=> SUM) = (0:0:0,0:0:0); |
| if ((B&!CIN)) (A +=> SUM) = (0:0:0,0:0:0); |
| if ((B&CIN)) (A -=> SUM) = (0:0:0,0:0:0); |
| if ((!A&!CIN)) (B -=> SUM) = (0:0:0,0:0:0); |
| if ((!A&CIN)) (B +=> SUM) = (0:0:0,0:0:0); |
| if ((A&!CIN)) (B +=> SUM) = (0:0:0,0:0:0); |
| if ((A&CIN)) (B -=> SUM) = (0:0:0,0:0:0); |
| if ((!A&!B)) (CIN -=> SUM) = (0:0:0,0:0:0); |
| if ((!A&B)) (CIN +=> SUM) = (0:0:0,0:0:0); |
| if ((A&!B)) (CIN +=> SUM) = (0:0:0,0:0:0); |
| if ((A&B)) (CIN -=> SUM) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| not(CI,CIN); |
| xor #0.001 (SUM,A,B,CI); |
| and (A$B,A,B),(A$CI,A,CI),(B$CI,B,CI); |
| or #0.001 (COUT,A$B,A$CI,B$CI); |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_fahcon_1 ( COUTN , SUM , A , B , CI ); |
| output COUTN , SUM ; |
| input A , B , CI ; |
| |
| wire COUTN , SUM , A , B, CI ; |
| |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((!B&CI)) (A -=> COUTN) = (0:0:0,0:0:0); |
| if ((B&!CI)) (A -=> COUTN) = (0:0:0,0:0:0); |
| if ((!A&CI)) (B -=> COUTN) = (0:0:0,0:0:0); |
| if ((A&!CI)) (B -=> COUTN) = (0:0:0,0:0:0); |
| if ((!A&B)) (CI -=> COUTN) = (0:0:0,0:0:0); |
| if ((A&!B)) (CI -=> COUTN) = (0:0:0,0:0:0); |
| if ((!B&!CI)) (A +=> SUM) = (0:0:0,0:0:0); |
| if ((!B&CI)) (A -=> SUM) = (0:0:0,0:0:0); |
| if ((B&!CI)) (A -=> SUM) = (0:0:0,0:0:0); |
| if ((B&CI)) (A +=> SUM) = (0:0:0,0:0:0); |
| if ((!A&!CI)) (B +=> SUM) = (0:0:0,0:0:0); |
| if ((!A&CI)) (B -=> SUM) = (0:0:0,0:0:0); |
| if ((A&!CI)) (B -=> SUM) = (0:0:0,0:0:0); |
| if ((A&CI)) (B +=> SUM) = (0:0:0,0:0:0); |
| if ((!A&!B)) (CI +=> SUM) = (0:0:0,0:0:0); |
| if ((!A&B)) (CI -=> SUM) = (0:0:0,0:0:0); |
| if ((A&!B)) (CI -=> SUM) = (0:0:0,0:0:0); |
| if ((A&B)) (CI +=> SUM) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| xor #0.001 (SUM,A,B,CI); |
| nor (A$B,A,B),(A$CI,A,CI),(B$CI,B,CI); |
| or #0.001 (COUTN,A$B,A$CI,B$CI); |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_ha_0 ( COUT , SUM , A , B ); |
| output COUT , SUM ; |
| input A , B ; |
| |
| wire COUT , SUM , A , B ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> COUT) = (0:0:0,0:0:0); |
| (B +=> COUT) = (0:0:0,0:0:0); |
| if ((!B)) (A +=> SUM) = (0:0:0,0:0:0); |
| if ((B)) (A -=> SUM) = (0:0:0,0:0:0); |
| if ((!A)) (B +=> SUM) = (0:0:0,0:0:0); |
| if ((A)) (B -=> SUM) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and #0.001 ( COUT , A , B ) ; |
| xor #0.001 ( SUM , B , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_ha_1 ( COUT , SUM , A , B ); |
| output COUT , SUM ; |
| input A , B ; |
| |
| wire COUT , SUM , A , B ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> COUT) = (0:0:0,0:0:0); |
| (B +=> COUT) = (0:0:0,0:0:0); |
| if ((!B)) (A +=> SUM) = (0:0:0,0:0:0); |
| if ((B)) (A -=> SUM) = (0:0:0,0:0:0); |
| if ((!A)) (B +=> SUM) = (0:0:0,0:0:0); |
| if ((A)) (B -=> SUM) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and #0.001 ( COUT , A , B ) ; |
| xor #0.001 ( SUM , B , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_ha_2 ( COUT , SUM , A , B ); |
| output COUT , SUM ; |
| input A , B ; |
| |
| wire COUT , SUM , A , B ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> COUT) = (0:0:0,0:0:0); |
| (B +=> COUT) = (0:0:0,0:0:0); |
| if ((!B)) (A +=> SUM) = (0:0:0,0:0:0); |
| if ((B)) (A -=> SUM) = (0:0:0,0:0:0); |
| if ((!A)) (B +=> SUM) = (0:0:0,0:0:0); |
| if ((A)) (B -=> SUM) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and #0.001 ( COUT , A , B ) ; |
| xor #0.001 ( SUM , B , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_ha_4 ( COUT , SUM , A , B ); |
| output COUT , SUM ; |
| input A , B ; |
| |
| wire COUT , SUM , A , B ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> COUT) = (0:0:0,0:0:0); |
| (B +=> COUT) = (0:0:0,0:0:0); |
| if ((!B)) (A +=> SUM) = (0:0:0,0:0:0); |
| if ((B)) (A -=> SUM) = (0:0:0,0:0:0); |
| if ((!A)) (B +=> SUM) = (0:0:0,0:0:0); |
| if ((A)) (B -=> SUM) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| and #0.001 ( COUT , A , B ) ; |
| xor #0.001 ( SUM , B , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_inv_0 ( Y , A ); |
| output Y ; |
| input A ; |
| |
| wire Y , A ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A -=> Y ) = (0:0:0,0:0:0); // delays are tris,tfall |
| endspecify |
| `endif |
| |
| not #0.001 ( Y , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_inv_1 ( Y , A ); |
| output Y ; |
| input A ; |
| |
| wire Y , A ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A -=> Y ) = (0:0:0,0:0:0); // delays are tris,tfall |
| endspecify |
| `endif |
| |
| not #0.001 ( Y , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_inv_16 ( Y , A ); |
| output Y ; |
| input A ; |
| |
| wire Y , A ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A -=> Y ) = (0:0:0,0:0:0); // delays are tris,tfall |
| endspecify |
| `endif |
| |
| not #0.001 ( Y , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_inv_2 ( Y , A ); |
| output Y ; |
| input A ; |
| |
| wire Y , A ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A -=> Y ) = (0:0:0,0:0:0); // delays are tris,tfall |
| endspecify |
| `endif |
| |
| not #0.001 ( Y , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_inv_4 ( Y , A ); |
| output Y ; |
| input A ; |
| |
| wire Y , A ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A -=> Y ) = (0:0:0,0:0:0); // delays are tris,tfall |
| endspecify |
| `endif |
| |
| not #0.001 ( Y , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_inv_8 ( Y , A ); |
| output Y ; |
| input A ; |
| |
| wire Y , A ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A -=> Y ) = (0:0:0,0:0:0); // delays are tris,tfall |
| endspecify |
| `endif |
| |
| not #0.001 ( Y , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_invlp_0 ( Y , A ); |
| output Y ; |
| input A ; |
| |
| wire Y , A ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A -=> Y ) = (0:0:0,0:0:0); // delays are tris,tfall |
| endspecify |
| `endif |
| |
| not #0.001 ( Y , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_invlp_1 ( Y , A ); |
| output Y ; |
| input A ; |
| |
| wire Y , A ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A -=> Y ) = (0:0:0,0:0:0); // delays are tris,tfall |
| endspecify |
| `endif |
| |
| not #0.001 ( Y , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_invlp_2 ( Y , A ); |
| output Y ; |
| input A ; |
| |
| wire Y , A ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A -=> Y ) = (0:0:0,0:0:0); // delays are tris,tfall |
| endspecify |
| `endif |
| |
| not #0.001 ( Y , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_invlp_4 ( Y , A ); |
| output Y ; |
| input A ; |
| |
| wire Y , A ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A -=> Y ) = (0:0:0,0:0:0); // delays are tris,tfall |
| endspecify |
| `endif |
| |
| not #0.001 ( Y , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_invlp_8 ( Y , A ); |
| output Y ; |
| input A ; |
| |
| wire Y , A ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A -=> Y ) = (0:0:0,0:0:0); // delays are tris,tfall |
| endspecify |
| `endif |
| |
| not #0.001 ( Y , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_maj3_0 ( X , A , B , C ); |
| output X ; |
| input A , B , C ; |
| |
| wire X , A , B , C ; |
| wire csi_opt_296, csi_opt_274, csi_opt_275 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((!B&C)) (A +=> X) = (0:0:0,0:0:0); |
| if ((B&!C)) (A +=> X) = (0:0:0,0:0:0); |
| if ((!A&C)) (B +=> X) = (0:0:0,0:0:0); |
| if ((A&!C)) (B +=> X) = (0:0:0,0:0:0); |
| if ((!A&B)) (C +=> X) = (0:0:0,0:0:0); |
| if ((A&!B)) (C +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or ( csi_opt_296 , B , A ) ; |
| and ( csi_opt_274 , csi_opt_296 , C ) ; |
| and ( csi_opt_275 , A , B ) ; |
| or #0.001 ( X , csi_opt_275 , csi_opt_274 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_maj3_1 ( X , A , B , C ); |
| output X ; |
| input A , B , C ; |
| |
| wire X , A , B , C ; |
| wire csi_opt_296, csi_opt_274, csi_opt_275 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((!B&C)) (A +=> X) = (0:0:0,0:0:0); |
| if ((B&!C)) (A +=> X) = (0:0:0,0:0:0); |
| if ((!A&C)) (B +=> X) = (0:0:0,0:0:0); |
| if ((A&!C)) (B +=> X) = (0:0:0,0:0:0); |
| if ((!A&B)) (C +=> X) = (0:0:0,0:0:0); |
| if ((A&!B)) (C +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or ( csi_opt_296 , B , A ) ; |
| and ( csi_opt_274 , csi_opt_296 , C ) ; |
| and ( csi_opt_275 , A , B ) ; |
| or #0.001 ( X , csi_opt_275 , csi_opt_274 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_maj3_2 ( X , A , B , C ); |
| output X ; |
| input A , B , C ; |
| |
| wire X , A , B , C ; |
| wire csi_opt_296, csi_opt_274, csi_opt_275 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((!B&C)) (A +=> X) = (0:0:0,0:0:0); |
| if ((B&!C)) (A +=> X) = (0:0:0,0:0:0); |
| if ((!A&C)) (B +=> X) = (0:0:0,0:0:0); |
| if ((A&!C)) (B +=> X) = (0:0:0,0:0:0); |
| if ((!A&B)) (C +=> X) = (0:0:0,0:0:0); |
| if ((A&!B)) (C +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or ( csi_opt_296 , B , A ) ; |
| and ( csi_opt_274 , csi_opt_296 , C ) ; |
| and ( csi_opt_275 , A , B ) ; |
| or #0.001 ( X , csi_opt_275 , csi_opt_274 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_maj3_4 ( X , A , B , C ); |
| output X ; |
| input A , B , C ; |
| |
| wire X , A , B , C ; |
| wire csi_opt_296, csi_opt_274, csi_opt_275 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((!B&C)) (A +=> X) = (0:0:0,0:0:0); |
| if ((B&!C)) (A +=> X) = (0:0:0,0:0:0); |
| if ((!A&C)) (B +=> X) = (0:0:0,0:0:0); |
| if ((A&!C)) (B +=> X) = (0:0:0,0:0:0); |
| if ((!A&B)) (C +=> X) = (0:0:0,0:0:0); |
| if ((A&!B)) (C +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or ( csi_opt_296 , B , A ) ; |
| and ( csi_opt_274 , csi_opt_296 , C ) ; |
| and ( csi_opt_275 , A , B ) ; |
| or #0.001 ( X , csi_opt_275 , csi_opt_274 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_mux2_0 ( X , A0 , A1 , S ); |
| output X ; |
| input A0 , A1 , S ; |
| |
| wire X , A0 , A1 , S ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((!A1&!S)) (A0 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!S)) (A0 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&S)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((A0&S)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&A1)) (S +=> X) = (0:0:0,0:0:0); |
| if ((A0&!A1)) (S -=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| // aug27,2003 - bnb changed to udp model for muxs |
| |
| U_MUX_2_1 #0.001 (X, A0, A1, S); |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_mux2_1 ( X , A0 , A1 , S ); |
| output X ; |
| input A0 , A1 , S ; |
| |
| wire X , A0 , A1 , S ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((!A1&!S)) (A0 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!S)) (A0 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&S)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((A0&S)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&A1)) (S +=> X) = (0:0:0,0:0:0); |
| if ((A0&!A1)) (S -=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| // aug27,2003 - bnb changed to udp model for muxs |
| |
| U_MUX_2_1 #0.001 (X, A0, A1, S); |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_mux2_2 ( X , A0 , A1 , S ); |
| output X ; |
| input A0 , A1 , S ; |
| |
| wire X , A0 , A1 , S ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((!A1&!S)) (A0 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!S)) (A0 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&S)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((A0&S)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&A1)) (S +=> X) = (0:0:0,0:0:0); |
| if ((A0&!A1)) (S -=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| // aug27,2003 - bnb changed to udp model for muxs |
| |
| U_MUX_2_1 #0.001 (X, A0, A1, S); |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_mux2_4 ( X , A0 , A1 , S ); |
| output X ; |
| input A0 , A1 , S ; |
| |
| wire X , A0 , A1 , S ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((!A1&!S)) (A0 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!S)) (A0 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&S)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((A0&S)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&A1)) (S +=> X) = (0:0:0,0:0:0); |
| if ((A0&!A1)) (S -=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| // aug27,2003 - bnb changed to udp model for muxs |
| |
| U_MUX_2_1 #0.001 (X, A0, A1, S); |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_mux2_8 ( X , A0 , A1 , S ); |
| output X ; |
| input A0 , A1 , S ; |
| |
| wire X , A0 , A1 , S ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((!A1&!S)) (A0 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!S)) (A0 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&S)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((A0&S)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&A1)) (S +=> X) = (0:0:0,0:0:0); |
| if ((A0&!A1)) (S -=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| // aug27,2003 - bnb changed to udp model for muxs |
| |
| U_MUX_2_1 #0.001 (X, A0, A1, S); |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_mux2i_0 ( Y , A0 , A1 , S ); |
| output Y ; |
| input A0 , A1 , S ; |
| |
| wire Y , A0 , A1 , S ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((!A1&!S)) (A0 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!S)) (A0 -=> Y) = (0:0:0,0:0:0); |
| if ((!A0&S)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((A0&S)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A0&A1)) (S -=> Y) = (0:0:0,0:0:0); |
| if ((A0&!A1)) (S +=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| // aug27,2003 - bnb changed to udp model for muxs |
| |
| U_MUX_2_1_INV #0.001 (Y, A0, A1, S); |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_mux2i_1 ( Y , A0 , A1 , S ); |
| output Y ; |
| input A0 , A1 , S ; |
| |
| wire Y , A0 , A1 , S ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((!A1&!S)) (A0 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!S)) (A0 -=> Y) = (0:0:0,0:0:0); |
| if ((!A0&S)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((A0&S)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A0&A1)) (S -=> Y) = (0:0:0,0:0:0); |
| if ((A0&!A1)) (S +=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| // aug27,2003 - bnb changed to udp model for muxs |
| |
| U_MUX_2_1_INV #0.001 (Y, A0, A1, S); |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_mux2i_2 ( Y , A0 , A1 , S ); |
| output Y ; |
| input A0 , A1 , S ; |
| |
| wire Y , A0 , A1 , S ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((!A1&!S)) (A0 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!S)) (A0 -=> Y) = (0:0:0,0:0:0); |
| if ((!A0&S)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((A0&S)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A0&A1)) (S -=> Y) = (0:0:0,0:0:0); |
| if ((A0&!A1)) (S +=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| // aug27,2003 - bnb changed to udp model for muxs |
| |
| U_MUX_2_1_INV #0.001 (Y, A0, A1, S); |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_mux2i_4 ( Y , A0 , A1 , S ); |
| output Y ; |
| input A0 , A1 , S ; |
| |
| wire Y , A0 , A1 , S ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((!A1&!S)) (A0 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!S)) (A0 -=> Y) = (0:0:0,0:0:0); |
| if ((!A0&S)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((A0&S)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A0&A1)) (S -=> Y) = (0:0:0,0:0:0); |
| if ((A0&!A1)) (S +=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| // aug27,2003 - bnb changed to udp model for muxs |
| |
| U_MUX_2_1_INV #0.001 (Y, A0, A1, S); |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_mux4_0 ( X , A0 , A1 , A2 , A3 , S0 , S1 ); |
| output X ; |
| input A0 , A1 , A2 , A3 , S0 , S1 ; |
| |
| wire X , A0 , A1 , A2 ; |
| wire A3 , S0 , S1 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((!A1&!A2&!A3&!S0&!S1)) (A0 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&!S0&!S1)) (A0 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&!S0&!S1)) (A0 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&!S0&!S1)) (A0 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&!S0&!S1)) (A0 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&!S0&!S1)) (A0 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&!S0&!S1)) (A0 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&A3&!S0&!S1)) (A0 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&!A2&!A3&S0&!S1)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&!A2&A3&S0&!S1)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&A2&!A3&S0&!S1)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&A2&A3&S0&!S1)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((A0&!A2&!A3&S0&!S1)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((A0&!A2&A3&S0&!S1)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((A0&A2&!A3&S0&!S1)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((A0&A2&A3&S0&!S1)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&!A1&!A3&!S0&S1)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&!A1&A3&!S0&S1)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&A1&!A3&!S0&S1)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&A1&A3&!S0&S1)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((A0&!A1&!A3&!S0&S1)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((A0&!A1&A3&!S0&S1)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((A0&A1&!A3&!S0&S1)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((A0&A1&A3&!S0&S1)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&!A1&!A2&S0&S1)) (A3 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&!A1&A2&S0&S1)) (A3 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&A1&!A2&S0&S1)) (A3 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&A1&A2&S0&S1)) (A3 +=> X) = (0:0:0,0:0:0); |
| if ((A0&!A1&!A2&S0&S1)) (A3 +=> X) = (0:0:0,0:0:0); |
| if ((A0&!A1&A2&S0&S1)) (A3 +=> X) = (0:0:0,0:0:0); |
| if ((A0&A1&!A2&S0&S1)) (A3 +=> X) = (0:0:0,0:0:0); |
| if ((A0&A1&A2&S0&S1)) (A3 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&!A1&!A2&A3&S1)) (S0 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&!A1&A2&!A3&S1)) (S0 -=> X) = (0:0:0,0:0:0); |
| if ((!A0&A1&!A2&!A3&!S1)) (S0 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&A1&!A2&A3&!S1)) (S0 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&A1&!A2&A3&S1)) (S0 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&A1&A2&!A3&!S1)) (S0 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&A1&A2&!A3&S1)) (S0 -=> X) = (0:0:0,0:0:0); |
| if ((!A0&A1&A2&A3&!S1)) (S0 +=> X) = (0:0:0,0:0:0); |
| if ((A0&!A1&!A2&!A3&!S1)) (S0 -=> X) = (0:0:0,0:0:0); |
| if ((A0&!A1&!A2&A3&!S1)) (S0 -=> X) = (0:0:0,0:0:0); |
| if ((A0&!A1&!A2&A3&S1)) (S0 +=> X) = (0:0:0,0:0:0); |
| if ((A0&!A1&A2&!A3&!S1)) (S0 -=> X) = (0:0:0,0:0:0); |
| if ((A0&!A1&A2&!A3&S1)) (S0 -=> X) = (0:0:0,0:0:0); |
| if ((A0&!A1&A2&A3&!S1)) (S0 -=> X) = (0:0:0,0:0:0); |
| if ((A0&A1&!A2&A3&S1)) (S0 +=> X) = (0:0:0,0:0:0); |
| if ((A0&A1&A2&!A3&S1)) (S0 -=> X) = (0:0:0,0:0:0); |
| if ((!A0&!A1&!A2&A3&S0)) (S1 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&!A1&A2&!A3&!S0)) (S1 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&!A1&A2&A3&!S0)) (S1 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&!A1&A2&A3&S0)) (S1 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&A1&!A2&!A3&S0)) (S1 -=> X) = (0:0:0,0:0:0); |
| if ((!A0&A1&A2&!A3&!S0)) (S1 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&A1&A2&!A3&S0)) (S1 -=> X) = (0:0:0,0:0:0); |
| if ((!A0&A1&A2&A3&!S0)) (S1 +=> X) = (0:0:0,0:0:0); |
| if ((A0&!A1&!A2&!A3&!S0)) (S1 -=> X) = (0:0:0,0:0:0); |
| if ((A0&!A1&!A2&A3&!S0)) (S1 -=> X) = (0:0:0,0:0:0); |
| if ((A0&!A1&!A2&A3&S0)) (S1 +=> X) = (0:0:0,0:0:0); |
| if ((A0&!A1&A2&A3&S0)) (S1 +=> X) = (0:0:0,0:0:0); |
| if ((A0&A1&!A2&!A3&!S0)) (S1 -=> X) = (0:0:0,0:0:0); |
| if ((A0&A1&!A2&!A3&S0)) (S1 -=> X) = (0:0:0,0:0:0); |
| if ((A0&A1&!A2&A3&!S0)) (S1 -=> X) = (0:0:0,0:0:0); |
| if ((A0&A1&A2&!A3&S0)) (S1 -=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| // aug27,2003 - bnb changed to udp model for muxs |
| |
| U_MUX_4_2 #0.001 (X, A0, A1, A2, A3, S0, S1); |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_mux4_1 ( X , A0 , A1 , A2 , A3 , S0 , S1 ); |
| output X ; |
| input A0 , A1 , A2 , A3 , S0 , S1 ; |
| |
| wire X , A0 , A1 , A2 ; |
| wire A3 , S0 , S1 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((!A1&!A2&!A3&!S0&!S1)) (A0 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&!S0&!S1)) (A0 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&!S0&!S1)) (A0 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&!S0&!S1)) (A0 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&!S0&!S1)) (A0 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&!S0&!S1)) (A0 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&!S0&!S1)) (A0 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&A3&!S0&!S1)) (A0 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&!A2&!A3&S0&!S1)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&!A2&A3&S0&!S1)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&A2&!A3&S0&!S1)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&A2&A3&S0&!S1)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((A0&!A2&!A3&S0&!S1)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((A0&!A2&A3&S0&!S1)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((A0&A2&!A3&S0&!S1)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((A0&A2&A3&S0&!S1)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&!A1&!A3&!S0&S1)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&!A1&A3&!S0&S1)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&A1&!A3&!S0&S1)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&A1&A3&!S0&S1)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((A0&!A1&!A3&!S0&S1)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((A0&!A1&A3&!S0&S1)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((A0&A1&!A3&!S0&S1)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((A0&A1&A3&!S0&S1)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&!A1&!A2&S0&S1)) (A3 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&!A1&A2&S0&S1)) (A3 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&A1&!A2&S0&S1)) (A3 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&A1&A2&S0&S1)) (A3 +=> X) = (0:0:0,0:0:0); |
| if ((A0&!A1&!A2&S0&S1)) (A3 +=> X) = (0:0:0,0:0:0); |
| if ((A0&!A1&A2&S0&S1)) (A3 +=> X) = (0:0:0,0:0:0); |
| if ((A0&A1&!A2&S0&S1)) (A3 +=> X) = (0:0:0,0:0:0); |
| if ((A0&A1&A2&S0&S1)) (A3 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&!A1&!A2&A3&S1)) (S0 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&!A1&A2&!A3&S1)) (S0 -=> X) = (0:0:0,0:0:0); |
| if ((!A0&A1&!A2&!A3&!S1)) (S0 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&A1&!A2&A3&!S1)) (S0 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&A1&!A2&A3&S1)) (S0 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&A1&A2&!A3&!S1)) (S0 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&A1&A2&!A3&S1)) (S0 -=> X) = (0:0:0,0:0:0); |
| if ((!A0&A1&A2&A3&!S1)) (S0 +=> X) = (0:0:0,0:0:0); |
| if ((A0&!A1&!A2&!A3&!S1)) (S0 -=> X) = (0:0:0,0:0:0); |
| if ((A0&!A1&!A2&A3&!S1)) (S0 -=> X) = (0:0:0,0:0:0); |
| if ((A0&!A1&!A2&A3&S1)) (S0 +=> X) = (0:0:0,0:0:0); |
| if ((A0&!A1&A2&!A3&!S1)) (S0 -=> X) = (0:0:0,0:0:0); |
| if ((A0&!A1&A2&!A3&S1)) (S0 -=> X) = (0:0:0,0:0:0); |
| if ((A0&!A1&A2&A3&!S1)) (S0 -=> X) = (0:0:0,0:0:0); |
| if ((A0&A1&!A2&A3&S1)) (S0 +=> X) = (0:0:0,0:0:0); |
| if ((A0&A1&A2&!A3&S1)) (S0 -=> X) = (0:0:0,0:0:0); |
| if ((!A0&!A1&!A2&A3&S0)) (S1 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&!A1&A2&!A3&!S0)) (S1 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&!A1&A2&A3&!S0)) (S1 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&!A1&A2&A3&S0)) (S1 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&A1&!A2&!A3&S0)) (S1 -=> X) = (0:0:0,0:0:0); |
| if ((!A0&A1&A2&!A3&!S0)) (S1 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&A1&A2&!A3&S0)) (S1 -=> X) = (0:0:0,0:0:0); |
| if ((!A0&A1&A2&A3&!S0)) (S1 +=> X) = (0:0:0,0:0:0); |
| if ((A0&!A1&!A2&!A3&!S0)) (S1 -=> X) = (0:0:0,0:0:0); |
| if ((A0&!A1&!A2&A3&!S0)) (S1 -=> X) = (0:0:0,0:0:0); |
| if ((A0&!A1&!A2&A3&S0)) (S1 +=> X) = (0:0:0,0:0:0); |
| if ((A0&!A1&A2&A3&S0)) (S1 +=> X) = (0:0:0,0:0:0); |
| if ((A0&A1&!A2&!A3&!S0)) (S1 -=> X) = (0:0:0,0:0:0); |
| if ((A0&A1&!A2&!A3&S0)) (S1 -=> X) = (0:0:0,0:0:0); |
| if ((A0&A1&!A2&A3&!S0)) (S1 -=> X) = (0:0:0,0:0:0); |
| if ((A0&A1&A2&!A3&S0)) (S1 -=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| // aug27,2003 - bnb changed to udp model for muxs |
| |
| U_MUX_4_2 #0.001 (X, A0, A1, A2, A3, S0, S1); |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_mux4_2 ( X , A0 , A1 , A2 , A3 , S0 , S1 ); |
| output X ; |
| input A0 , A1 , A2 , A3 , S0 , S1 ; |
| |
| wire X , A0 , A1 , A2 ; |
| wire A3 , S0 , S1 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((!A1&!A2&!A3&!S0&!S1)) (A0 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&!S0&!S1)) (A0 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&!S0&!S1)) (A0 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&!S0&!S1)) (A0 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&!S0&!S1)) (A0 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&!S0&!S1)) (A0 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&!S0&!S1)) (A0 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&A3&!S0&!S1)) (A0 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&!A2&!A3&S0&!S1)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&!A2&A3&S0&!S1)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&A2&!A3&S0&!S1)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&A2&A3&S0&!S1)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((A0&!A2&!A3&S0&!S1)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((A0&!A2&A3&S0&!S1)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((A0&A2&!A3&S0&!S1)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((A0&A2&A3&S0&!S1)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&!A1&!A3&!S0&S1)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&!A1&A3&!S0&S1)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&A1&!A3&!S0&S1)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&A1&A3&!S0&S1)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((A0&!A1&!A3&!S0&S1)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((A0&!A1&A3&!S0&S1)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((A0&A1&!A3&!S0&S1)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((A0&A1&A3&!S0&S1)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&!A1&!A2&S0&S1)) (A3 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&!A1&A2&S0&S1)) (A3 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&A1&!A2&S0&S1)) (A3 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&A1&A2&S0&S1)) (A3 +=> X) = (0:0:0,0:0:0); |
| if ((A0&!A1&!A2&S0&S1)) (A3 +=> X) = (0:0:0,0:0:0); |
| if ((A0&!A1&A2&S0&S1)) (A3 +=> X) = (0:0:0,0:0:0); |
| if ((A0&A1&!A2&S0&S1)) (A3 +=> X) = (0:0:0,0:0:0); |
| if ((A0&A1&A2&S0&S1)) (A3 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&!A1&!A2&A3&S1)) (S0 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&!A1&A2&!A3&S1)) (S0 -=> X) = (0:0:0,0:0:0); |
| if ((!A0&A1&!A2&!A3&!S1)) (S0 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&A1&!A2&A3&!S1)) (S0 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&A1&!A2&A3&S1)) (S0 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&A1&A2&!A3&!S1)) (S0 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&A1&A2&!A3&S1)) (S0 -=> X) = (0:0:0,0:0:0); |
| if ((!A0&A1&A2&A3&!S1)) (S0 +=> X) = (0:0:0,0:0:0); |
| if ((A0&!A1&!A2&!A3&!S1)) (S0 -=> X) = (0:0:0,0:0:0); |
| if ((A0&!A1&!A2&A3&!S1)) (S0 -=> X) = (0:0:0,0:0:0); |
| if ((A0&!A1&!A2&A3&S1)) (S0 +=> X) = (0:0:0,0:0:0); |
| if ((A0&!A1&A2&!A3&!S1)) (S0 -=> X) = (0:0:0,0:0:0); |
| if ((A0&!A1&A2&!A3&S1)) (S0 -=> X) = (0:0:0,0:0:0); |
| if ((A0&!A1&A2&A3&!S1)) (S0 -=> X) = (0:0:0,0:0:0); |
| if ((A0&A1&!A2&A3&S1)) (S0 +=> X) = (0:0:0,0:0:0); |
| if ((A0&A1&A2&!A3&S1)) (S0 -=> X) = (0:0:0,0:0:0); |
| if ((!A0&!A1&!A2&A3&S0)) (S1 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&!A1&A2&!A3&!S0)) (S1 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&!A1&A2&A3&!S0)) (S1 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&!A1&A2&A3&S0)) (S1 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&A1&!A2&!A3&S0)) (S1 -=> X) = (0:0:0,0:0:0); |
| if ((!A0&A1&A2&!A3&!S0)) (S1 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&A1&A2&!A3&S0)) (S1 -=> X) = (0:0:0,0:0:0); |
| if ((!A0&A1&A2&A3&!S0)) (S1 +=> X) = (0:0:0,0:0:0); |
| if ((A0&!A1&!A2&!A3&!S0)) (S1 -=> X) = (0:0:0,0:0:0); |
| if ((A0&!A1&!A2&A3&!S0)) (S1 -=> X) = (0:0:0,0:0:0); |
| if ((A0&!A1&!A2&A3&S0)) (S1 +=> X) = (0:0:0,0:0:0); |
| if ((A0&!A1&A2&A3&S0)) (S1 +=> X) = (0:0:0,0:0:0); |
| if ((A0&A1&!A2&!A3&!S0)) (S1 -=> X) = (0:0:0,0:0:0); |
| if ((A0&A1&!A2&!A3&S0)) (S1 -=> X) = (0:0:0,0:0:0); |
| if ((A0&A1&!A2&A3&!S0)) (S1 -=> X) = (0:0:0,0:0:0); |
| if ((A0&A1&A2&!A3&S0)) (S1 -=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| // aug27,2003 - bnb changed to udp model for muxs |
| |
| U_MUX_4_2 #0.001 (X, A0, A1, A2, A3, S0, S1); |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_mux4_4 ( X , A0 , A1 , A2 , A3 , S0 , S1 ); |
| output X ; |
| input A0 , A1 , A2 , A3 , S0 , S1 ; |
| |
| wire X , A0 , A1 , A2 ; |
| wire A3 , S0 , S1 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((!A1&!A2&!A3&!S0&!S1)) (A0 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&!S0&!S1)) (A0 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&!S0&!S1)) (A0 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&!S0&!S1)) (A0 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&!S0&!S1)) (A0 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&!S0&!S1)) (A0 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&!S0&!S1)) (A0 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&A3&!S0&!S1)) (A0 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&!A2&!A3&S0&!S1)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&!A2&A3&S0&!S1)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&A2&!A3&S0&!S1)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&A2&A3&S0&!S1)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((A0&!A2&!A3&S0&!S1)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((A0&!A2&A3&S0&!S1)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((A0&A2&!A3&S0&!S1)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((A0&A2&A3&S0&!S1)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&!A1&!A3&!S0&S1)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&!A1&A3&!S0&S1)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&A1&!A3&!S0&S1)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&A1&A3&!S0&S1)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((A0&!A1&!A3&!S0&S1)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((A0&!A1&A3&!S0&S1)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((A0&A1&!A3&!S0&S1)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((A0&A1&A3&!S0&S1)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&!A1&!A2&S0&S1)) (A3 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&!A1&A2&S0&S1)) (A3 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&A1&!A2&S0&S1)) (A3 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&A1&A2&S0&S1)) (A3 +=> X) = (0:0:0,0:0:0); |
| if ((A0&!A1&!A2&S0&S1)) (A3 +=> X) = (0:0:0,0:0:0); |
| if ((A0&!A1&A2&S0&S1)) (A3 +=> X) = (0:0:0,0:0:0); |
| if ((A0&A1&!A2&S0&S1)) (A3 +=> X) = (0:0:0,0:0:0); |
| if ((A0&A1&A2&S0&S1)) (A3 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&!A1&!A2&A3&S1)) (S0 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&!A1&A2&!A3&S1)) (S0 -=> X) = (0:0:0,0:0:0); |
| if ((!A0&A1&!A2&!A3&!S1)) (S0 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&A1&!A2&A3&!S1)) (S0 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&A1&!A2&A3&S1)) (S0 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&A1&A2&!A3&!S1)) (S0 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&A1&A2&!A3&S1)) (S0 -=> X) = (0:0:0,0:0:0); |
| if ((!A0&A1&A2&A3&!S1)) (S0 +=> X) = (0:0:0,0:0:0); |
| if ((A0&!A1&!A2&!A3&!S1)) (S0 -=> X) = (0:0:0,0:0:0); |
| if ((A0&!A1&!A2&A3&!S1)) (S0 -=> X) = (0:0:0,0:0:0); |
| if ((A0&!A1&!A2&A3&S1)) (S0 +=> X) = (0:0:0,0:0:0); |
| if ((A0&!A1&A2&!A3&!S1)) (S0 -=> X) = (0:0:0,0:0:0); |
| if ((A0&!A1&A2&!A3&S1)) (S0 -=> X) = (0:0:0,0:0:0); |
| if ((A0&!A1&A2&A3&!S1)) (S0 -=> X) = (0:0:0,0:0:0); |
| if ((A0&A1&!A2&A3&S1)) (S0 +=> X) = (0:0:0,0:0:0); |
| if ((A0&A1&A2&!A3&S1)) (S0 -=> X) = (0:0:0,0:0:0); |
| if ((!A0&!A1&!A2&A3&S0)) (S1 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&!A1&A2&!A3&!S0)) (S1 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&!A1&A2&A3&!S0)) (S1 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&!A1&A2&A3&S0)) (S1 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&A1&!A2&!A3&S0)) (S1 -=> X) = (0:0:0,0:0:0); |
| if ((!A0&A1&A2&!A3&!S0)) (S1 +=> X) = (0:0:0,0:0:0); |
| if ((!A0&A1&A2&!A3&S0)) (S1 -=> X) = (0:0:0,0:0:0); |
| if ((!A0&A1&A2&A3&!S0)) (S1 +=> X) = (0:0:0,0:0:0); |
| if ((A0&!A1&!A2&!A3&!S0)) (S1 -=> X) = (0:0:0,0:0:0); |
| if ((A0&!A1&!A2&A3&!S0)) (S1 -=> X) = (0:0:0,0:0:0); |
| if ((A0&!A1&!A2&A3&S0)) (S1 +=> X) = (0:0:0,0:0:0); |
| if ((A0&!A1&A2&A3&S0)) (S1 +=> X) = (0:0:0,0:0:0); |
| if ((A0&A1&!A2&!A3&!S0)) (S1 -=> X) = (0:0:0,0:0:0); |
| if ((A0&A1&!A2&!A3&S0)) (S1 -=> X) = (0:0:0,0:0:0); |
| if ((A0&A1&!A2&A3&!S0)) (S1 -=> X) = (0:0:0,0:0:0); |
| if ((A0&A1&A2&!A3&S0)) (S1 -=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| // aug27,2003 - bnb changed to udp model for muxs |
| |
| U_MUX_4_2 #0.001 (X, A0, A1, A2, A3, S0, S1); |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_nand2_0 ( Y , A , B ); |
| output Y ; |
| input A , B ; |
| |
| wire Y , A , B ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A -=> Y) = (0:0:0,0:0:0); |
| (B -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nand #0.001 ( Y , B , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_nand2_1 ( Y , A , B ); |
| output Y ; |
| input A , B ; |
| |
| wire Y , A , B ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A -=> Y) = (0:0:0,0:0:0); |
| (B -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nand #0.001 ( Y , B , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_nand2_2 ( Y , A , B ); |
| output Y ; |
| input A , B ; |
| |
| wire Y , A , B ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A -=> Y) = (0:0:0,0:0:0); |
| (B -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nand #0.001 ( Y , B , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_nand2_4 ( Y , A , B ); |
| output Y ; |
| input A , B ; |
| |
| wire Y , A , B ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A -=> Y) = (0:0:0,0:0:0); |
| (B -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nand #0.001 ( Y , B , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_nand2_8 ( Y , A , B ); |
| output Y ; |
| input A , B ; |
| |
| wire Y , A , B ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A -=> Y) = (0:0:0,0:0:0); |
| (B -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nand #0.001 ( Y , B , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_nand2b_1 ( Y , AN , B ); |
| output Y ; |
| input AN , B ; |
| |
| wire Y , AN , B , csi_opt_276 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (AN +=> Y) = (0:0:0,0:0:0); |
| (B -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| not ( csi_opt_276 , B ) ; |
| or #0.001 ( Y , csi_opt_276 , AN ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_nand2b_2 ( Y , AN , B ); |
| output Y ; |
| input AN , B ; |
| |
| wire Y , AN , B , csi_opt_276 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (AN +=> Y) = (0:0:0,0:0:0); |
| (B -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| not ( csi_opt_276 , B ) ; |
| or #0.001 ( Y , csi_opt_276 , AN ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_nand2b_4 ( Y , AN , B ); |
| output Y ; |
| input AN , B ; |
| |
| wire Y , AN , B , csi_opt_276 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (AN +=> Y) = (0:0:0,0:0:0); |
| (B -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| not ( csi_opt_276 , B ) ; |
| or #0.001 ( Y , csi_opt_276 , AN ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_nand3_0 ( Y , A , B , C ); |
| output Y ; |
| input A , B , C ; |
| |
| wire Y , A , B , C ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A -=> Y) = (0:0:0,0:0:0); |
| (B -=> Y) = (0:0:0,0:0:0); |
| (C -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nand #0.001 ( Y , B , A , C ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_nand3_1 ( Y , A , B , C ); |
| output Y ; |
| input A , B , C ; |
| |
| wire Y , A , B , C ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A -=> Y) = (0:0:0,0:0:0); |
| (B -=> Y) = (0:0:0,0:0:0); |
| (C -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nand #0.001 ( Y , B , A , C ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_nand3_2 ( Y , A , B , C ); |
| output Y ; |
| input A , B , C ; |
| |
| wire Y , A , B , C ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A -=> Y) = (0:0:0,0:0:0); |
| (B -=> Y) = (0:0:0,0:0:0); |
| (C -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nand #0.001 ( Y , B , A , C ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_nand3_4 ( Y , A , B , C ); |
| output Y ; |
| input A , B , C ; |
| |
| wire Y , A , B , C ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A -=> Y) = (0:0:0,0:0:0); |
| (B -=> Y) = (0:0:0,0:0:0); |
| (C -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nand #0.001 ( Y , B , A , C ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_nand3b_1 ( Y , AN , B , C ); |
| output Y ; |
| input AN , B , C ; |
| |
| wire Y , AN , B , C ; |
| wire csi_opt_281 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (AN +=> Y) = (0:0:0,0:0:0); |
| (B -=> Y) = (0:0:0,0:0:0); |
| (C -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| not ( csi_opt_281 , AN ) ; |
| nand #0.001 ( Y , B , csi_opt_281 , C ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_nand3b_2 ( Y , AN , B , C ); |
| output Y ; |
| input AN , B , C ; |
| |
| wire Y , AN , B , C ; |
| wire csi_opt_281 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (AN +=> Y) = (0:0:0,0:0:0); |
| (B -=> Y) = (0:0:0,0:0:0); |
| (C -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| not ( csi_opt_281 , AN ) ; |
| nand #0.001 ( Y , B , csi_opt_281 , C ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_nand3b_4 ( Y , AN , B , C ); |
| output Y ; |
| input AN , B , C ; |
| |
| wire Y , AN , B , C ; |
| wire csi_opt_281 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (AN +=> Y) = (0:0:0,0:0:0); |
| (B -=> Y) = (0:0:0,0:0:0); |
| (C -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| not ( csi_opt_281 , AN ) ; |
| nand #0.001 ( Y , B , csi_opt_281 , C ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_nand4_0 ( Y , A , B , C , D ); |
| output Y ; |
| input A , B , C , D ; |
| |
| wire Y , A , B , C ; |
| wire D ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A -=> Y) = (0:0:0,0:0:0); |
| (B -=> Y) = (0:0:0,0:0:0); |
| (C -=> Y) = (0:0:0,0:0:0); |
| (D -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nand #0.001 ( Y , D , C , B , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_nand4_1 ( Y , A , B , C , D ); |
| output Y ; |
| input A , B , C , D ; |
| |
| wire Y , A , B , C ; |
| wire D ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A -=> Y) = (0:0:0,0:0:0); |
| (B -=> Y) = (0:0:0,0:0:0); |
| (C -=> Y) = (0:0:0,0:0:0); |
| (D -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nand #0.001 ( Y , D , C , B , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_nand4_2 ( Y , A , B , C , D ); |
| output Y ; |
| input A , B , C , D ; |
| |
| wire Y , A , B , C ; |
| wire D ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A -=> Y) = (0:0:0,0:0:0); |
| (B -=> Y) = (0:0:0,0:0:0); |
| (C -=> Y) = (0:0:0,0:0:0); |
| (D -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nand #0.001 ( Y , D , C , B , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_nand4_4 ( Y , A , B , C , D ); |
| output Y ; |
| input A , B , C , D ; |
| |
| wire Y , A , B , C ; |
| wire D ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A -=> Y) = (0:0:0,0:0:0); |
| (B -=> Y) = (0:0:0,0:0:0); |
| (C -=> Y) = (0:0:0,0:0:0); |
| (D -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nand #0.001 ( Y , D , C , B , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_nand4b_1 ( Y , AN , B , C , D ); |
| output Y ; |
| input AN , B , C , D ; |
| |
| wire Y , AN , B , C ; |
| wire D , csi_opt_285 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (AN +=> Y) = (0:0:0,0:0:0); |
| (B -=> Y) = (0:0:0,0:0:0); |
| (C -=> Y) = (0:0:0,0:0:0); |
| (D -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| not ( csi_opt_285 , AN ) ; |
| nand #0.001 ( Y , D , C , B , csi_opt_285 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_nand4b_2 ( Y , AN , B , C , D ); |
| output Y ; |
| input AN , B , C , D ; |
| |
| wire Y , AN , B , C ; |
| wire D , csi_opt_285 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (AN +=> Y) = (0:0:0,0:0:0); |
| (B -=> Y) = (0:0:0,0:0:0); |
| (C -=> Y) = (0:0:0,0:0:0); |
| (D -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| not ( csi_opt_285 , AN ) ; |
| nand #0.001 ( Y , D , C , B , csi_opt_285 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_nand4b_4 ( Y , AN , B , C , D ); |
| output Y ; |
| input AN , B , C , D ; |
| |
| wire Y , AN , B , C ; |
| wire D , csi_opt_285 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (AN +=> Y) = (0:0:0,0:0:0); |
| (B -=> Y) = (0:0:0,0:0:0); |
| (C -=> Y) = (0:0:0,0:0:0); |
| (D -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| not ( csi_opt_285 , AN ) ; |
| nand #0.001 ( Y , D , C , B , csi_opt_285 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_nand4bb_1 ( Y , AN , BN , C , D ); |
| output Y ; |
| input AN , BN , C , D ; |
| |
| wire Y , AN , BN , C ; |
| wire D , csi_opt_283 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (AN +=> Y) = (0:0:0,0:0:0); |
| (BN +=> Y) = (0:0:0,0:0:0); |
| (C -=> Y) = (0:0:0,0:0:0); |
| (D -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nand ( csi_opt_283 , D , C ) ; |
| or #0.001 ( Y , BN , AN , csi_opt_283 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_nand4bb_2 ( Y , AN , BN , C , D ); |
| output Y ; |
| input AN , BN , C , D ; |
| |
| wire Y , AN , BN , C ; |
| wire D , csi_opt_283 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (AN +=> Y) = (0:0:0,0:0:0); |
| (BN +=> Y) = (0:0:0,0:0:0); |
| (C -=> Y) = (0:0:0,0:0:0); |
| (D -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nand ( csi_opt_283 , D , C ) ; |
| or #0.001 ( Y , BN , AN , csi_opt_283 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_nand4bb_4 ( Y , AN , BN , C , D ); |
| output Y ; |
| input AN , BN , C , D ; |
| |
| wire Y , AN , BN , C ; |
| wire D , csi_opt_283 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (AN +=> Y) = (0:0:0,0:0:0); |
| (BN +=> Y) = (0:0:0,0:0:0); |
| (C -=> Y) = (0:0:0,0:0:0); |
| (D -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nand ( csi_opt_283 , D , C ) ; |
| or #0.001 ( Y , BN , AN , csi_opt_283 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_nor2_0 ( Y , A , B ); |
| output Y ; |
| input A , B ; |
| |
| wire Y , A , B ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A -=> Y) = (0:0:0,0:0:0); |
| (B -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nor #0.001 ( Y , A , B ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_nor2_1 ( Y , A , B ); |
| output Y ; |
| input A , B ; |
| |
| wire Y , A , B ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A -=> Y) = (0:0:0,0:0:0); |
| (B -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nor #0.001 ( Y , A , B ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_nor2_2 ( Y , A , B ); |
| output Y ; |
| input A , B ; |
| |
| wire Y , A , B ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A -=> Y) = (0:0:0,0:0:0); |
| (B -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nor #0.001 ( Y , A , B ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_nor2_4 ( Y , A , B ); |
| output Y ; |
| input A , B ; |
| |
| wire Y , A , B ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A -=> Y) = (0:0:0,0:0:0); |
| (B -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nor #0.001 ( Y , A , B ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_nor2_8 ( Y , A , B ); |
| output Y ; |
| input A , B ; |
| |
| wire Y , A , B ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A -=> Y) = (0:0:0,0:0:0); |
| (B -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nor #0.001 ( Y , A , B ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_nor2b_1 ( Y , A , BN ); |
| output Y ; |
| input A , BN ; |
| |
| wire Y , A , BN , csi_opt_276 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A -=> Y) = (0:0:0,0:0:0); |
| (BN +=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| not ( csi_opt_276 , A ) ; |
| and #0.001 ( Y , csi_opt_276 , BN ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_nor2b_2 ( Y , A , BN ); |
| output Y ; |
| input A , BN ; |
| |
| wire Y , A , BN , csi_opt_276 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A -=> Y) = (0:0:0,0:0:0); |
| (BN +=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| not ( csi_opt_276 , A ) ; |
| and #0.001 ( Y , csi_opt_276 , BN ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_nor2b_4 ( Y , A , BN ); |
| output Y ; |
| input A , BN ; |
| |
| wire Y , A , BN , csi_opt_276 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A -=> Y) = (0:0:0,0:0:0); |
| (BN +=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| not ( csi_opt_276 , A ) ; |
| and #0.001 ( Y , csi_opt_276 , BN ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_nor3_0 ( Y , A , B , C ); |
| output Y ; |
| input A , B , C ; |
| |
| wire Y , A , B , C ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A -=> Y) = (0:0:0,0:0:0); |
| (B -=> Y) = (0:0:0,0:0:0); |
| (C -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nor #0.001 ( Y , C , A , B ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_nor3_1 ( Y , A , B , C ); |
| output Y ; |
| input A , B , C ; |
| |
| wire Y , A , B , C ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A -=> Y) = (0:0:0,0:0:0); |
| (B -=> Y) = (0:0:0,0:0:0); |
| (C -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nor #0.001 ( Y , C , A , B ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_nor3_2 ( Y , A , B , C ); |
| output Y ; |
| input A , B , C ; |
| |
| wire Y , A , B , C ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A -=> Y) = (0:0:0,0:0:0); |
| (B -=> Y) = (0:0:0,0:0:0); |
| (C -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nor #0.001 ( Y , C , A , B ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_nor3_4 ( Y , A , B , C ); |
| output Y ; |
| input A , B , C ; |
| |
| wire Y , A , B , C ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A -=> Y) = (0:0:0,0:0:0); |
| (B -=> Y) = (0:0:0,0:0:0); |
| (C -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nor #0.001 ( Y , C , A , B ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_nor3b_1 ( Y , A , B , CN ); |
| output Y ; |
| input A , B , CN ; |
| |
| wire Y , A , B , CN ; |
| wire csi_opt_276 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A -=> Y) = (0:0:0,0:0:0); |
| (B -=> Y) = (0:0:0,0:0:0); |
| (CN +=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nor ( csi_opt_276 , A , B ) ; |
| and #0.001 ( Y , CN , csi_opt_276 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_nor3b_2 ( Y , A , B , CN ); |
| output Y ; |
| input A , B , CN ; |
| |
| wire Y , A , B , CN ; |
| wire csi_opt_276 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A -=> Y) = (0:0:0,0:0:0); |
| (B -=> Y) = (0:0:0,0:0:0); |
| (CN +=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nor ( csi_opt_276 , A , B ) ; |
| and #0.001 ( Y , CN , csi_opt_276 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_nor3b_4 ( Y , A , B , CN ); |
| output Y ; |
| input A , B , CN ; |
| |
| wire Y , A , B , CN ; |
| wire csi_opt_276 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A -=> Y) = (0:0:0,0:0:0); |
| (B -=> Y) = (0:0:0,0:0:0); |
| (CN +=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nor ( csi_opt_276 , A , B ) ; |
| and #0.001 ( Y , CN , csi_opt_276 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_nor4_0 ( Y , A , B , C , D ); |
| output Y ; |
| input A , B , C , D ; |
| |
| wire Y , A , B , C ; |
| wire D ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A -=> Y) = (0:0:0,0:0:0); |
| (B -=> Y) = (0:0:0,0:0:0); |
| (C -=> Y) = (0:0:0,0:0:0); |
| (D -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nor #0.001 ( Y , A , B , C , D ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_nor4_1 ( Y , A , B , C , D ); |
| output Y ; |
| input A , B , C , D ; |
| |
| wire Y , A , B , C ; |
| wire D ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A -=> Y) = (0:0:0,0:0:0); |
| (B -=> Y) = (0:0:0,0:0:0); |
| (C -=> Y) = (0:0:0,0:0:0); |
| (D -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nor #0.001 ( Y , A , B , C , D ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_nor4_2 ( Y , A , B , C , D ); |
| output Y ; |
| input A , B , C , D ; |
| |
| wire Y , A , B , C ; |
| wire D ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A -=> Y) = (0:0:0,0:0:0); |
| (B -=> Y) = (0:0:0,0:0:0); |
| (C -=> Y) = (0:0:0,0:0:0); |
| (D -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nor #0.001 ( Y , A , B , C , D ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_nor4_4 ( Y , A , B , C , D ); |
| output Y ; |
| input A , B , C , D ; |
| |
| wire Y , A , B , C ; |
| wire D ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A -=> Y) = (0:0:0,0:0:0); |
| (B -=> Y) = (0:0:0,0:0:0); |
| (C -=> Y) = (0:0:0,0:0:0); |
| (D -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nor #0.001 ( Y , A , B , C , D ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_nor4b_1 ( Y , A , B , C , DN ); |
| output Y ; |
| input A , B , C , DN ; |
| |
| wire Y , A , B , C ; |
| wire DN , csi_opt_280 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A -=> Y) = (0:0:0,0:0:0); |
| (B -=> Y) = (0:0:0,0:0:0); |
| (C -=> Y) = (0:0:0,0:0:0); |
| (DN +=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| not ( csi_opt_280 , DN ) ; |
| nor #0.001 ( Y , A , B , C , csi_opt_280 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_nor4b_2 ( Y , A , B , C , DN ); |
| output Y ; |
| input A , B , C , DN ; |
| |
| wire Y , A , B , C ; |
| wire DN , csi_opt_280 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A -=> Y) = (0:0:0,0:0:0); |
| (B -=> Y) = (0:0:0,0:0:0); |
| (C -=> Y) = (0:0:0,0:0:0); |
| (DN +=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| not ( csi_opt_280 , DN ) ; |
| nor #0.001 ( Y , A , B , C , csi_opt_280 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_nor4b_4 ( Y , A , B , C , DN ); |
| output Y ; |
| input A , B , C , DN ; |
| |
| wire Y , A , B , C ; |
| wire DN , csi_opt_280 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A -=> Y) = (0:0:0,0:0:0); |
| (B -=> Y) = (0:0:0,0:0:0); |
| (C -=> Y) = (0:0:0,0:0:0); |
| (DN +=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| not ( csi_opt_280 , DN ) ; |
| nor #0.001 ( Y , A , B , C , csi_opt_280 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_nor4bb_1 ( Y , A , B , CN , DN ); |
| output Y ; |
| input A , B , CN , DN ; |
| |
| wire Y , A , B , CN ; |
| wire DN , csi_opt_278 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A -=> Y) = (0:0:0,0:0:0); |
| (B -=> Y) = (0:0:0,0:0:0); |
| (CN +=> Y) = (0:0:0,0:0:0); |
| (DN +=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nor ( csi_opt_278 , A , B ) ; |
| and #0.001 ( Y , csi_opt_278 , CN , DN ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_nor4bb_2 ( Y , A , B , CN , DN ); |
| output Y ; |
| input A , B , CN , DN ; |
| |
| wire Y , A , B , CN ; |
| wire DN , csi_opt_278 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A -=> Y) = (0:0:0,0:0:0); |
| (B -=> Y) = (0:0:0,0:0:0); |
| (CN +=> Y) = (0:0:0,0:0:0); |
| (DN +=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nor ( csi_opt_278 , A , B ) ; |
| and #0.001 ( Y , csi_opt_278 , CN , DN ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_nor4bb_4 ( Y , A , B , CN , DN ); |
| output Y ; |
| input A , B , CN , DN ; |
| |
| wire Y , A , B , CN ; |
| wire DN , csi_opt_278 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A -=> Y) = (0:0:0,0:0:0); |
| (B -=> Y) = (0:0:0,0:0:0); |
| (CN +=> Y) = (0:0:0,0:0:0); |
| (DN +=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nor ( csi_opt_278 , A , B ) ; |
| and #0.001 ( Y , csi_opt_278 , CN , DN ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o2111a_0 ( X , A1 , A2 , B1 , C1 , D1 ); |
| output X ; |
| input A1 , A2 , B1 , C1 , D1 ; |
| |
| wire X , A1 , A2 , B1 ; |
| wire C1 , D1 , csi_opt_300 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 +=> X) = (0:0:0,0:0:0); |
| (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&C1&D1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&C1&D1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&C1&D1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&B1&D1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&B1&D1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&B1&D1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&B1&C1)) (D1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&B1&C1)) (D1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&B1&C1)) (D1 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or ( csi_opt_300 , A2 , A1 ) ; |
| and #0.001 ( X , B1 , C1 , csi_opt_300 , D1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o2111a_1 ( X , A1 , A2 , B1 , C1 , D1 ); |
| output X ; |
| input A1 , A2 , B1 , C1 , D1 ; |
| |
| wire X , A1 , A2 , B1 ; |
| wire C1 , D1 , csi_opt_300 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 +=> X) = (0:0:0,0:0:0); |
| (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&C1&D1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&C1&D1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&C1&D1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&B1&D1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&B1&D1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&B1&D1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&B1&C1)) (D1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&B1&C1)) (D1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&B1&C1)) (D1 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or ( csi_opt_300 , A2 , A1 ) ; |
| and #0.001 ( X , B1 , C1 , csi_opt_300 , D1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o2111a_2 ( X , A1 , A2 , B1 , C1 , D1 ); |
| output X ; |
| input A1 , A2 , B1 , C1 , D1 ; |
| |
| wire X , A1 , A2 , B1 ; |
| wire C1 , D1 , csi_opt_300 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 +=> X) = (0:0:0,0:0:0); |
| (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&C1&D1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&C1&D1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&C1&D1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&B1&D1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&B1&D1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&B1&D1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&B1&C1)) (D1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&B1&C1)) (D1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&B1&C1)) (D1 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or ( csi_opt_300 , A2 , A1 ) ; |
| and #0.001 ( X , B1 , C1 , csi_opt_300 , D1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o2111a_4 ( X , A1 , A2 , B1 , C1 , D1 ); |
| output X ; |
| input A1 , A2 , B1 , C1 , D1 ; |
| |
| wire X , A1 , A2 , B1 ; |
| wire C1 , D1 , csi_opt_300 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 +=> X) = (0:0:0,0:0:0); |
| (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&C1&D1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&C1&D1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&C1&D1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&B1&D1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&B1&D1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&B1&D1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&B1&C1)) (D1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&B1&C1)) (D1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&B1&C1)) (D1 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or ( csi_opt_300 , A2 , A1 ) ; |
| and #0.001 ( X , B1 , C1 , csi_opt_300 , D1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o2111ai_0 ( Y , A1 , A2 , B1 , C1 , D1 ); |
| output Y ; |
| input A1 , A2 , B1 , C1 , D1 ; |
| |
| wire Y , A1 , A2 , B1 ; |
| wire C1 , D1 , csi_opt_301 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 -=> Y) = (0:0:0,0:0:0); |
| (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&C1&D1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&C1&D1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&C1&D1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&B1&D1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&B1&D1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&B1&D1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&B1&C1)) (D1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&B1&C1)) (D1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&B1&C1)) (D1 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or ( csi_opt_301 , A2 , A1 ) ; |
| nand #0.001 ( Y , C1 , B1 , D1 , csi_opt_301 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o2111ai_1 ( Y , A1 , A2 , B1 , C1 , D1 ); |
| output Y ; |
| input A1 , A2 , B1 , C1 , D1 ; |
| |
| wire Y , A1 , A2 , B1 ; |
| wire C1 , D1 , csi_opt_301 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 -=> Y) = (0:0:0,0:0:0); |
| (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&C1&D1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&C1&D1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&C1&D1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&B1&D1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&B1&D1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&B1&D1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&B1&C1)) (D1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&B1&C1)) (D1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&B1&C1)) (D1 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or ( csi_opt_301 , A2 , A1 ) ; |
| nand #0.001 ( Y , C1 , B1 , D1 , csi_opt_301 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o2111ai_2 ( Y , A1 , A2 , B1 , C1 , D1 ); |
| output Y ; |
| input A1 , A2 , B1 , C1 , D1 ; |
| |
| wire Y , A1 , A2 , B1 ; |
| wire C1 , D1 , csi_opt_301 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 -=> Y) = (0:0:0,0:0:0); |
| (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&C1&D1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&C1&D1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&C1&D1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&B1&D1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&B1&D1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&B1&D1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&B1&C1)) (D1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&B1&C1)) (D1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&B1&C1)) (D1 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or ( csi_opt_301 , A2 , A1 ) ; |
| nand #0.001 ( Y , C1 , B1 , D1 , csi_opt_301 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o2111ai_4 ( Y , A1 , A2 , B1 , C1 , D1 ); |
| output Y ; |
| input A1 , A2 , B1 , C1 , D1 ; |
| |
| wire Y , A1 , A2 , B1 ; |
| wire C1 , D1 , csi_opt_301 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 -=> Y) = (0:0:0,0:0:0); |
| (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&C1&D1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&C1&D1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&C1&D1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&B1&D1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&B1&D1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&B1&D1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&B1&C1)) (D1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&B1&C1)) (D1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&B1&C1)) (D1 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or ( csi_opt_301 , A2 , A1 ) ; |
| nand #0.001 ( Y , C1 , B1 , D1 , csi_opt_301 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o211a_0 ( X , A1 , A2 , B1 , C1 ); |
| output X ; |
| input A1 , A2 , B1 , C1 ; |
| |
| wire X , A1 , A2 , B1 ; |
| wire C1 , csi_opt_294 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 +=> X) = (0:0:0,0:0:0); |
| (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or ( csi_opt_294 , A2 , A1 ) ; |
| and #0.001 ( X , csi_opt_294 , B1 , C1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o211a_1 ( X , A1 , A2 , B1 , C1 ); |
| output X ; |
| input A1 , A2 , B1 , C1 ; |
| |
| wire X , A1 , A2 , B1 ; |
| wire C1 , csi_opt_294 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 +=> X) = (0:0:0,0:0:0); |
| (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or ( csi_opt_294 , A2 , A1 ) ; |
| and #0.001 ( X , csi_opt_294 , B1 , C1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o211a_2 ( X , A1 , A2 , B1 , C1 ); |
| output X ; |
| input A1 , A2 , B1 , C1 ; |
| |
| wire X , A1 , A2 , B1 ; |
| wire C1 , csi_opt_294 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 +=> X) = (0:0:0,0:0:0); |
| (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or ( csi_opt_294 , A2 , A1 ) ; |
| and #0.001 ( X , csi_opt_294 , B1 , C1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o211a_4 ( X , A1 , A2 , B1 , C1 ); |
| output X ; |
| input A1 , A2 , B1 , C1 ; |
| |
| wire X , A1 , A2 , B1 ; |
| wire C1 , csi_opt_294 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 +=> X) = (0:0:0,0:0:0); |
| (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or ( csi_opt_294 , A2 , A1 ) ; |
| and #0.001 ( X , csi_opt_294 , B1 , C1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o211ai_0 ( Y , A1 , A2 , B1 , C1 ); |
| output Y ; |
| input A1 , A2 , B1 , C1 ; |
| |
| wire Y , A1 , A2 , B1 ; |
| wire C1 , csi_opt_294 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 -=> Y) = (0:0:0,0:0:0); |
| (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or ( csi_opt_294 , A2 , A1 ) ; |
| nand #0.001 ( Y , C1 , csi_opt_294 , B1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o211ai_1 ( Y , A1 , A2 , B1 , C1 ); |
| output Y ; |
| input A1 , A2 , B1 , C1 ; |
| |
| wire Y , A1 , A2 , B1 ; |
| wire C1 , csi_opt_294 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 -=> Y) = (0:0:0,0:0:0); |
| (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or ( csi_opt_294 , A2 , A1 ) ; |
| nand #0.001 ( Y , C1 , csi_opt_294 , B1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o211ai_2 ( Y , A1 , A2 , B1 , C1 ); |
| output Y ; |
| input A1 , A2 , B1 , C1 ; |
| |
| wire Y , A1 , A2 , B1 ; |
| wire C1 , csi_opt_294 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 -=> Y) = (0:0:0,0:0:0); |
| (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or ( csi_opt_294 , A2 , A1 ) ; |
| nand #0.001 ( Y , C1 , csi_opt_294 , B1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o211ai_4 ( Y , A1 , A2 , B1 , C1 ); |
| output Y ; |
| input A1 , A2 , B1 , C1 ; |
| |
| wire Y , A1 , A2 , B1 ; |
| wire C1 , csi_opt_294 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 -=> Y) = (0:0:0,0:0:0); |
| (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or ( csi_opt_294 , A2 , A1 ) ; |
| nand #0.001 ( Y , C1 , csi_opt_294 , B1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o21a_0 ( X , A1 , A2 , B1 ); |
| output X ; |
| input A1 , A2 , B1 ; |
| |
| wire X , A1 , A2 , B1 ; |
| wire csi_opt_287 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 +=> X) = (0:0:0,0:0:0); |
| (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2)) (B1 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or ( csi_opt_287 , A2 , A1 ) ; |
| and #0.001 ( X , csi_opt_287 , B1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o21a_1 ( X , A1 , A2 , B1 ); |
| output X ; |
| input A1 , A2 , B1 ; |
| |
| wire X , A1 , A2 , B1 ; |
| wire csi_opt_287 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 +=> X) = (0:0:0,0:0:0); |
| (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2)) (B1 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or ( csi_opt_287 , A2 , A1 ) ; |
| and #0.001 ( X , csi_opt_287 , B1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o21a_2 ( X , A1 , A2 , B1 ); |
| output X ; |
| input A1 , A2 , B1 ; |
| |
| wire X , A1 , A2 , B1 ; |
| wire csi_opt_287 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 +=> X) = (0:0:0,0:0:0); |
| (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2)) (B1 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or ( csi_opt_287 , A2 , A1 ) ; |
| and #0.001 ( X , csi_opt_287 , B1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o21a_4 ( X , A1 , A2 , B1 ); |
| output X ; |
| input A1 , A2 , B1 ; |
| |
| wire X , A1 , A2 , B1 ; |
| wire csi_opt_287 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 +=> X) = (0:0:0,0:0:0); |
| (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2)) (B1 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or ( csi_opt_287 , A2 , A1 ) ; |
| and #0.001 ( X , csi_opt_287 , B1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o21ai_0 ( Y , A1 , A2 , B1 ); |
| output Y ; |
| input A1 , A2 , B1 ; |
| |
| wire Y , A1 , A2 , B1 ; |
| wire csi_opt_287 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 -=> Y) = (0:0:0,0:0:0); |
| (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or ( csi_opt_287 , A2 , A1 ) ; |
| nand #0.001 ( Y , B1 , csi_opt_287 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o21ai_1 ( Y , A1 , A2 , B1 ); |
| output Y ; |
| input A1 , A2 , B1 ; |
| |
| wire Y , A1 , A2 , B1 ; |
| wire csi_opt_287 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 -=> Y) = (0:0:0,0:0:0); |
| (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or ( csi_opt_287 , A2 , A1 ) ; |
| nand #0.001 ( Y , B1 , csi_opt_287 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o21ai_2 ( Y , A1 , A2 , B1 ); |
| output Y ; |
| input A1 , A2 , B1 ; |
| |
| wire Y , A1 , A2 , B1 ; |
| wire csi_opt_287 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 -=> Y) = (0:0:0,0:0:0); |
| (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or ( csi_opt_287 , A2 , A1 ) ; |
| nand #0.001 ( Y , B1 , csi_opt_287 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o21ai_4 ( Y , A1 , A2 , B1 ); |
| output Y ; |
| input A1 , A2 , B1 ; |
| |
| wire Y , A1 , A2 , B1 ; |
| wire csi_opt_287 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 -=> Y) = (0:0:0,0:0:0); |
| (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or ( csi_opt_287 , A2 , A1 ) ; |
| nand #0.001 ( Y , B1 , csi_opt_287 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o21ba_0 ( X , A1 , A2 , B1N ); |
| output X ; |
| input A1 , A2 , B1N ; |
| |
| wire X , A1 , A2 , B1N ; |
| wire csi_opt_273 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 +=> X) = (0:0:0,0:0:0); |
| (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2)) (B1N -=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2)) (B1N -=> X) = (0:0:0,0:0:0); |
| if ((A1&A2)) (B1N -=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nor ( csi_opt_273 , A1 , A2 ) ; |
| nor #0.001 ( X , B1N , csi_opt_273 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o21ba_1 ( X , A1 , A2 , B1N ); |
| output X ; |
| input A1 , A2 , B1N ; |
| |
| wire X , A1 , A2 , B1N ; |
| wire csi_opt_273 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 +=> X) = (0:0:0,0:0:0); |
| (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2)) (B1N -=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2)) (B1N -=> X) = (0:0:0,0:0:0); |
| if ((A1&A2)) (B1N -=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nor ( csi_opt_273 , A1 , A2 ) ; |
| nor #0.001 ( X , B1N , csi_opt_273 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o21ba_2 ( X , A1 , A2 , B1N ); |
| output X ; |
| input A1 , A2 , B1N ; |
| |
| wire X , A1 , A2 , B1N ; |
| wire csi_opt_273 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 +=> X) = (0:0:0,0:0:0); |
| (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2)) (B1N -=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2)) (B1N -=> X) = (0:0:0,0:0:0); |
| if ((A1&A2)) (B1N -=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nor ( csi_opt_273 , A1 , A2 ) ; |
| nor #0.001 ( X , B1N , csi_opt_273 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o21ba_4 ( X , A1 , A2 , B1N ); |
| output X ; |
| input A1 , A2 , B1N ; |
| |
| wire X , A1 , A2 , B1N ; |
| wire csi_opt_273 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 +=> X) = (0:0:0,0:0:0); |
| (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2)) (B1N -=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2)) (B1N -=> X) = (0:0:0,0:0:0); |
| if ((A1&A2)) (B1N -=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nor ( csi_opt_273 , A1 , A2 ) ; |
| nor #0.001 ( X , B1N , csi_opt_273 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o21bai_0 (Y,A1,A2,B1N); |
| output Y; |
| input A1,A2,B1N; |
| wire b; |
| |
| not (b,B1N); |
| or ( csi_opt_287 , A2 , A1 ) ; |
| nand #0.001 ( Y , b , csi_opt_287 ) ; |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 -=> Y) = (0:0:0,0:0:0); |
| (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2)) (B1N +=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2)) (B1N +=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2)) (B1N +=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o21bai_1 (Y,A1,A2,B1N); |
| output Y; |
| input A1,A2,B1N; |
| wire b; |
| |
| not (b,B1N); |
| or ( csi_opt_287 , A2 , A1 ) ; |
| nand #0.001 ( Y , b , csi_opt_287 ) ; |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 -=> Y) = (0:0:0,0:0:0); |
| (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2)) (B1N +=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2)) (B1N +=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2)) (B1N +=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o21bai_2 (Y,A1,A2,B1N); |
| output Y; |
| input A1,A2,B1N; |
| wire b; |
| |
| not (b,B1N); |
| or ( csi_opt_287 , A2 , A1 ) ; |
| nand #0.001 ( Y , b , csi_opt_287 ) ; |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 -=> Y) = (0:0:0,0:0:0); |
| (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2)) (B1N +=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2)) (B1N +=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2)) (B1N +=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o21bai_4 (Y,A1,A2,B1N); |
| output Y; |
| input A1,A2,B1N; |
| wire b; |
| |
| not (b,B1N); |
| or ( csi_opt_287 , A2 , A1 ) ; |
| nand #0.001 ( Y , b , csi_opt_287 ) ; |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 -=> Y) = (0:0:0,0:0:0); |
| (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2)) (B1N +=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2)) (B1N +=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2)) (B1N +=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o221a_0 ( X , A1 , A2 , B1 , B2 , C1 ); |
| output X ; |
| input A1 , A2 , B1 , B2 , C1 ; |
| |
| wire X , A1 , A2 , B1 ; |
| wire B2 , C1 , csi_opt_299, csi_opt_301 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((!A2&!B1&B2&C1)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((!A2&B1&!B2&C1)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((!A2&B1&B2&C1)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!B1&B2&C1)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&B1&!B2&C1)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&B1&B2&C1)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B2&C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B2&C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!B2&C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B1&C1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B1&C1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!B1&C1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B1&B2)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&B1&!B2)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&B1&B2)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B1&B2)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&B1&!B2)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&B1&B2)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!B1&B2)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&B1&!B2)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&B1&B2)) (C1 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or ( csi_opt_299 , B2 , B1 ) ; |
| or ( csi_opt_301 , A2 , A1 ) ; |
| and #0.001 ( X , csi_opt_299 , csi_opt_301 , C1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o221a_1 ( X , A1 , A2 , B1 , B2 , C1 ); |
| output X ; |
| input A1 , A2 , B1 , B2 , C1 ; |
| |
| wire X , A1 , A2 , B1 ; |
| wire B2 , C1 , csi_opt_299, csi_opt_301 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((!A2&!B1&B2&C1)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((!A2&B1&!B2&C1)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((!A2&B1&B2&C1)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!B1&B2&C1)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&B1&!B2&C1)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&B1&B2&C1)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B2&C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B2&C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!B2&C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B1&C1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B1&C1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!B1&C1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B1&B2)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&B1&!B2)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&B1&B2)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B1&B2)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&B1&!B2)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&B1&B2)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!B1&B2)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&B1&!B2)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&B1&B2)) (C1 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or ( csi_opt_299 , B2 , B1 ) ; |
| or ( csi_opt_301 , A2 , A1 ) ; |
| and #0.001 ( X , csi_opt_299 , csi_opt_301 , C1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o221a_2 ( X , A1 , A2 , B1 , B2 , C1 ); |
| output X ; |
| input A1 , A2 , B1 , B2 , C1 ; |
| |
| wire X , A1 , A2 , B1 ; |
| wire B2 , C1 , csi_opt_299, csi_opt_301 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((!A2&!B1&B2&C1)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((!A2&B1&!B2&C1)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((!A2&B1&B2&C1)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!B1&B2&C1)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&B1&!B2&C1)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&B1&B2&C1)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B2&C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B2&C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!B2&C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B1&C1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B1&C1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!B1&C1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B1&B2)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&B1&!B2)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&B1&B2)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B1&B2)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&B1&!B2)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&B1&B2)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!B1&B2)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&B1&!B2)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&B1&B2)) (C1 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or ( csi_opt_299 , B2 , B1 ) ; |
| or ( csi_opt_301 , A2 , A1 ) ; |
| and #0.001 ( X , csi_opt_299 , csi_opt_301 , C1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o221a_4 ( X , A1 , A2 , B1 , B2 , C1 ); |
| output X ; |
| input A1 , A2 , B1 , B2 , C1 ; |
| |
| wire X , A1 , A2 , B1 ; |
| wire B2 , C1 , csi_opt_299, csi_opt_301 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((!A2&!B1&B2&C1)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((!A2&B1&!B2&C1)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((!A2&B1&B2&C1)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!B1&B2&C1)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&B1&!B2&C1)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&B1&B2&C1)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B2&C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B2&C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!B2&C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B1&C1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B1&C1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!B1&C1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B1&B2)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&B1&!B2)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&B1&B2)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B1&B2)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&B1&!B2)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&B1&B2)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!B1&B2)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&B1&!B2)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&B1&B2)) (C1 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or ( csi_opt_299 , B2 , B1 ) ; |
| or ( csi_opt_301 , A2 , A1 ) ; |
| and #0.001 ( X , csi_opt_299 , csi_opt_301 , C1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o221ai_0 ( Y , A1 , A2 , B1 , B2 , C1 ); |
| output Y ; |
| input A1 , A2 , B1 , B2 , C1 ; |
| |
| wire Y , A1 , A2 , B1 ; |
| wire B2 , C1 , csi_opt_297, csi_opt_299 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((!A2&!B1&B2&C1)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A2&B1&!B2&C1)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A2&B1&B2&C1)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!B1&B2&C1)) (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&B1&!B2&C1)) (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&B1&B2&C1)) (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B2&C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B2&C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!B2&C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B1&C1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B1&C1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!B1&C1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B1&B2)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&B1&!B2)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&B1&B2)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B1&B2)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&B1&!B2)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&B1&B2)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!B1&B2)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&B1&!B2)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&B1&B2)) (C1 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or ( csi_opt_297 , B2 , B1 ) ; |
| or ( csi_opt_299 , A2 , A1 ) ; |
| nand #0.001 ( Y , csi_opt_299 , csi_opt_297 , C1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o221ai_1 ( Y , A1 , A2 , B1 , B2 , C1 ); |
| output Y ; |
| input A1 , A2 , B1 , B2 , C1 ; |
| |
| wire Y , A1 , A2 , B1 ; |
| wire B2 , C1 , csi_opt_297, csi_opt_299 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((!A2&!B1&B2&C1)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A2&B1&!B2&C1)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A2&B1&B2&C1)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!B1&B2&C1)) (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&B1&!B2&C1)) (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&B1&B2&C1)) (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B2&C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B2&C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!B2&C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B1&C1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B1&C1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!B1&C1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B1&B2)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&B1&!B2)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&B1&B2)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B1&B2)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&B1&!B2)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&B1&B2)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!B1&B2)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&B1&!B2)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&B1&B2)) (C1 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or ( csi_opt_297 , B2 , B1 ) ; |
| or ( csi_opt_299 , A2 , A1 ) ; |
| nand #0.001 ( Y , csi_opt_299 , csi_opt_297 , C1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o221ai_2 ( Y , A1 , A2 , B1 , B2 , C1 ); |
| output Y ; |
| input A1 , A2 , B1 , B2 , C1 ; |
| |
| wire Y , A1 , A2 , B1 ; |
| wire B2 , C1 , csi_opt_297, csi_opt_299 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((!A2&!B1&B2&C1)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A2&B1&!B2&C1)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A2&B1&B2&C1)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!B1&B2&C1)) (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&B1&!B2&C1)) (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&B1&B2&C1)) (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B2&C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B2&C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!B2&C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B1&C1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B1&C1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!B1&C1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B1&B2)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&B1&!B2)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&B1&B2)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B1&B2)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&B1&!B2)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&B1&B2)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!B1&B2)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&B1&!B2)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&B1&B2)) (C1 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or ( csi_opt_297 , B2 , B1 ) ; |
| or ( csi_opt_299 , A2 , A1 ) ; |
| nand #0.001 ( Y , csi_opt_299 , csi_opt_297 , C1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o221ai_4 ( Y , A1 , A2 , B1 , B2 , C1 ); |
| output Y ; |
| input A1 , A2 , B1 , B2 , C1 ; |
| |
| wire Y , A1 , A2 , B1 ; |
| wire B2 , C1 , csi_opt_297, csi_opt_299 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((!A2&!B1&B2&C1)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A2&B1&!B2&C1)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A2&B1&B2&C1)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!B1&B2&C1)) (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&B1&!B2&C1)) (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&B1&B2&C1)) (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B2&C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B2&C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!B2&C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B1&C1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B1&C1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!B1&C1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B1&B2)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&B1&!B2)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&B1&B2)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B1&B2)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&B1&!B2)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&B1&B2)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!B1&B2)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&B1&!B2)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&B1&B2)) (C1 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or ( csi_opt_297 , B2 , B1 ) ; |
| or ( csi_opt_299 , A2 , A1 ) ; |
| nand #0.001 ( Y , csi_opt_299 , csi_opt_297 , C1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o22a_0 ( X , A1 , A2 , B1 , B2 ); |
| output X ; |
| input A1 , A2 , B1 , B2 ; |
| |
| wire X , A1 , A2 , B1 ; |
| wire B2 , csi_opt_294, csi_opt_292 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((!A2&!B1&B2)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((!A2&B1&!B2)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((!A2&B1&B2)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!B1&B2)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&B1&!B2)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&B1&B2)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or ( csi_opt_294 , A2 , A1 ) ; |
| or ( csi_opt_292 , B2 , B1 ) ; |
| and #0.001 ( X , csi_opt_294 , csi_opt_292 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o22a_1 ( X , A1 , A2 , B1 , B2 ); |
| output X ; |
| input A1 , A2 , B1 , B2 ; |
| |
| wire X , A1 , A2 , B1 ; |
| wire B2 , csi_opt_294, csi_opt_292 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((!A2&!B1&B2)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((!A2&B1&!B2)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((!A2&B1&B2)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!B1&B2)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&B1&!B2)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&B1&B2)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or ( csi_opt_294 , A2 , A1 ) ; |
| or ( csi_opt_292 , B2 , B1 ) ; |
| and #0.001 ( X , csi_opt_294 , csi_opt_292 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o22a_2 ( X , A1 , A2 , B1 , B2 ); |
| output X ; |
| input A1 , A2 , B1 , B2 ; |
| |
| wire X , A1 , A2 , B1 ; |
| wire B2 , csi_opt_294, csi_opt_292 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((!A2&!B1&B2)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((!A2&B1&!B2)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((!A2&B1&B2)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!B1&B2)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&B1&!B2)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&B1&B2)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or ( csi_opt_294 , A2 , A1 ) ; |
| or ( csi_opt_292 , B2 , B1 ) ; |
| and #0.001 ( X , csi_opt_294 , csi_opt_292 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o22a_4 ( X , A1 , A2 , B1 , B2 ); |
| output X ; |
| input A1 , A2 , B1 , B2 ; |
| |
| wire X , A1 , A2 , B1 ; |
| wire B2 , csi_opt_294, csi_opt_292 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((!A2&!B1&B2)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((!A2&B1&!B2)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((!A2&B1&B2)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!B1&B2)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&B1&!B2)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&B1&B2)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or ( csi_opt_294 , A2 , A1 ) ; |
| or ( csi_opt_292 , B2 , B1 ) ; |
| and #0.001 ( X , csi_opt_294 , csi_opt_292 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o22ai_0 ( Y , A1 , A2 , B1 , B2 ); |
| output Y ; |
| input A1 , A2 , B1 , B2 ; |
| |
| wire Y , A1 , A2 , B1 ; |
| wire B2 , csi_opt_273, csi_opt_274 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((!A2&!B1&B2)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A2&B1&!B2)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A2&B1&B2)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!B1&B2)) (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&B1&!B2)) (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&B1&B2)) (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nor ( csi_opt_273 , B1 , B2 ) ; |
| nor ( csi_opt_274 , A1 , A2 ) ; |
| or #0.001 ( Y , csi_opt_274 , csi_opt_273 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o22ai_1 ( Y , A1 , A2 , B1 , B2 ); |
| output Y ; |
| input A1 , A2 , B1 , B2 ; |
| |
| wire Y , A1 , A2 , B1 ; |
| wire B2 , csi_opt_273, csi_opt_274 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((!A2&!B1&B2)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A2&B1&!B2)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A2&B1&B2)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!B1&B2)) (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&B1&!B2)) (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&B1&B2)) (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nor ( csi_opt_273 , B1 , B2 ) ; |
| nor ( csi_opt_274 , A1 , A2 ) ; |
| or #0.001 ( Y , csi_opt_274 , csi_opt_273 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o22ai_2 ( Y , A1 , A2 , B1 , B2 ); |
| output Y ; |
| input A1 , A2 , B1 , B2 ; |
| |
| wire Y , A1 , A2 , B1 ; |
| wire B2 , csi_opt_273, csi_opt_274 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((!A2&!B1&B2)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A2&B1&!B2)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A2&B1&B2)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!B1&B2)) (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&B1&!B2)) (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&B1&B2)) (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nor ( csi_opt_273 , B1 , B2 ) ; |
| nor ( csi_opt_274 , A1 , A2 ) ; |
| or #0.001 ( Y , csi_opt_274 , csi_opt_273 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o22ai_4 ( Y , A1 , A2 , B1 , B2 ); |
| output Y ; |
| input A1 , A2 , B1 , B2 ; |
| |
| wire Y , A1 , A2 , B1 ; |
| wire B2 , csi_opt_273, csi_opt_274 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((!A2&!B1&B2)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A2&B1&!B2)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A2&B1&B2)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!B1&B2)) (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&B1&!B2)) (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&B1&B2)) (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nor ( csi_opt_273 , B1 , B2 ) ; |
| nor ( csi_opt_274 , A1 , A2 ) ; |
| or #0.001 ( Y , csi_opt_274 , csi_opt_273 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o2bb2a_0 ( X , A1N , A2N , B1 , B2 ); |
| output X ; |
| input A1N , A2N , B1 , B2 ; |
| |
| wire X , A1N , A2N , B1 ; |
| wire B2 , csi_opt_296, csi_opt_294 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((A2N&!B1&B2)) (A1N -=> X) = (0:0:0,0:0:0); |
| if ((A2N&B1&!B2)) (A1N -=> X) = (0:0:0,0:0:0); |
| if ((A2N&B1&B2)) (A1N -=> X) = (0:0:0,0:0:0); |
| if ((A1N&!B1&B2)) (A2N -=> X) = (0:0:0,0:0:0); |
| if ((A1N&B1&!B2)) (A2N -=> X) = (0:0:0,0:0:0); |
| if ((A1N&B1&B2)) (A2N -=> X) = (0:0:0,0:0:0); |
| if ((!A1N&!A2N&!B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1N&A2N&!B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1N&!A2N&!B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1N&!A2N&!B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1N&A2N&!B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((A1N&!A2N&!B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nand ( csi_opt_296 , A2N , A1N ) ; |
| or ( csi_opt_294 , B2 , B1 ) ; |
| and #0.001 ( X , csi_opt_296 , csi_opt_294 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o2bb2a_1 ( X , A1N , A2N , B1 , B2 ); |
| output X ; |
| input A1N , A2N , B1 , B2 ; |
| |
| wire X , A1N , A2N , B1 ; |
| wire B2 , csi_opt_296, csi_opt_294 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((A2N&!B1&B2)) (A1N -=> X) = (0:0:0,0:0:0); |
| if ((A2N&B1&!B2)) (A1N -=> X) = (0:0:0,0:0:0); |
| if ((A2N&B1&B2)) (A1N -=> X) = (0:0:0,0:0:0); |
| if ((A1N&!B1&B2)) (A2N -=> X) = (0:0:0,0:0:0); |
| if ((A1N&B1&!B2)) (A2N -=> X) = (0:0:0,0:0:0); |
| if ((A1N&B1&B2)) (A2N -=> X) = (0:0:0,0:0:0); |
| if ((!A1N&!A2N&!B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1N&A2N&!B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1N&!A2N&!B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1N&!A2N&!B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1N&A2N&!B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((A1N&!A2N&!B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nand ( csi_opt_296 , A2N , A1N ) ; |
| or ( csi_opt_294 , B2 , B1 ) ; |
| and #0.001 ( X , csi_opt_296 , csi_opt_294 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o2bb2a_2 ( X , A1N , A2N , B1 , B2 ); |
| output X ; |
| input A1N , A2N , B1 , B2 ; |
| |
| wire X , A1N , A2N , B1 ; |
| wire B2 , csi_opt_296, csi_opt_294 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((A2N&!B1&B2)) (A1N -=> X) = (0:0:0,0:0:0); |
| if ((A2N&B1&!B2)) (A1N -=> X) = (0:0:0,0:0:0); |
| if ((A2N&B1&B2)) (A1N -=> X) = (0:0:0,0:0:0); |
| if ((A1N&!B1&B2)) (A2N -=> X) = (0:0:0,0:0:0); |
| if ((A1N&B1&!B2)) (A2N -=> X) = (0:0:0,0:0:0); |
| if ((A1N&B1&B2)) (A2N -=> X) = (0:0:0,0:0:0); |
| if ((!A1N&!A2N&!B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1N&A2N&!B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1N&!A2N&!B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1N&!A2N&!B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1N&A2N&!B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((A1N&!A2N&!B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nand ( csi_opt_296 , A2N , A1N ) ; |
| or ( csi_opt_294 , B2 , B1 ) ; |
| and #0.001 ( X , csi_opt_296 , csi_opt_294 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o2bb2a_4 ( X , A1N , A2N , B1 , B2 ); |
| output X ; |
| input A1N , A2N , B1 , B2 ; |
| |
| wire X , A1N , A2N , B1 ; |
| wire B2 , csi_opt_296, csi_opt_294 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((A2N&!B1&B2)) (A1N -=> X) = (0:0:0,0:0:0); |
| if ((A2N&B1&!B2)) (A1N -=> X) = (0:0:0,0:0:0); |
| if ((A2N&B1&B2)) (A1N -=> X) = (0:0:0,0:0:0); |
| if ((A1N&!B1&B2)) (A2N -=> X) = (0:0:0,0:0:0); |
| if ((A1N&B1&!B2)) (A2N -=> X) = (0:0:0,0:0:0); |
| if ((A1N&B1&B2)) (A2N -=> X) = (0:0:0,0:0:0); |
| if ((!A1N&!A2N&!B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1N&A2N&!B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1N&!A2N&!B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1N&!A2N&!B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1N&A2N&!B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((A1N&!A2N&!B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nand ( csi_opt_296 , A2N , A1N ) ; |
| or ( csi_opt_294 , B2 , B1 ) ; |
| and #0.001 ( X , csi_opt_296 , csi_opt_294 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o2bb2ai_0 ( Y , A1N , A2N , B1 , B2 ); |
| output Y ; |
| input A1N , A2N , B1 , B2 ; |
| |
| wire Y , A1N , A2N , B1 ; |
| wire B2 , csi_opt_296, csi_opt_294 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((A2N&!B1&B2)) (A1N +=> Y) = (0:0:0,0:0:0); |
| if ((A2N&B1&!B2)) (A1N +=> Y) = (0:0:0,0:0:0); |
| if ((A2N&B1&B2)) (A1N +=> Y) = (0:0:0,0:0:0); |
| if ((A1N&!B1&B2)) (A2N +=> Y) = (0:0:0,0:0:0); |
| if ((A1N&B1&!B2)) (A2N +=> Y) = (0:0:0,0:0:0); |
| if ((A1N&B1&B2)) (A2N +=> Y) = (0:0:0,0:0:0); |
| if ((!A1N&!A2N&!B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1N&A2N&!B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1N&!A2N&!B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1N&!A2N&!B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1N&A2N&!B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1N&!A2N&!B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nand ( csi_opt_296 , A2N , A1N ) ; |
| or ( csi_opt_294 , B2 , B1 ) ; |
| nand #0.001 ( Y , csi_opt_296 , csi_opt_294 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o2bb2ai_1 ( Y , A1N , A2N , B1 , B2 ); |
| output Y ; |
| input A1N , A2N , B1 , B2 ; |
| |
| wire Y , A1N , A2N , B1 ; |
| wire B2 , csi_opt_296, csi_opt_294 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((A2N&!B1&B2)) (A1N +=> Y) = (0:0:0,0:0:0); |
| if ((A2N&B1&!B2)) (A1N +=> Y) = (0:0:0,0:0:0); |
| if ((A2N&B1&B2)) (A1N +=> Y) = (0:0:0,0:0:0); |
| if ((A1N&!B1&B2)) (A2N +=> Y) = (0:0:0,0:0:0); |
| if ((A1N&B1&!B2)) (A2N +=> Y) = (0:0:0,0:0:0); |
| if ((A1N&B1&B2)) (A2N +=> Y) = (0:0:0,0:0:0); |
| if ((!A1N&!A2N&!B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1N&A2N&!B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1N&!A2N&!B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1N&!A2N&!B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1N&A2N&!B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1N&!A2N&!B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nand ( csi_opt_296 , A2N , A1N ) ; |
| or ( csi_opt_294 , B2 , B1 ) ; |
| nand #0.001 ( Y , csi_opt_296 , csi_opt_294 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o2bb2ai_2 ( Y , A1N , A2N , B1 , B2 ); |
| output Y ; |
| input A1N , A2N , B1 , B2 ; |
| |
| wire Y , A1N , A2N , B1 ; |
| wire B2 , csi_opt_296, csi_opt_294 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((A2N&!B1&B2)) (A1N +=> Y) = (0:0:0,0:0:0); |
| if ((A2N&B1&!B2)) (A1N +=> Y) = (0:0:0,0:0:0); |
| if ((A2N&B1&B2)) (A1N +=> Y) = (0:0:0,0:0:0); |
| if ((A1N&!B1&B2)) (A2N +=> Y) = (0:0:0,0:0:0); |
| if ((A1N&B1&!B2)) (A2N +=> Y) = (0:0:0,0:0:0); |
| if ((A1N&B1&B2)) (A2N +=> Y) = (0:0:0,0:0:0); |
| if ((!A1N&!A2N&!B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1N&A2N&!B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1N&!A2N&!B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1N&!A2N&!B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1N&A2N&!B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1N&!A2N&!B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nand ( csi_opt_296 , A2N , A1N ) ; |
| or ( csi_opt_294 , B2 , B1 ) ; |
| nand #0.001 ( Y , csi_opt_296 , csi_opt_294 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o2bb2ai_4 ( Y , A1N , A2N , B1 , B2 ); |
| output Y ; |
| input A1N , A2N , B1 , B2 ; |
| |
| wire Y , A1N , A2N , B1 ; |
| wire B2 , csi_opt_296, csi_opt_294 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((A2N&!B1&B2)) (A1N +=> Y) = (0:0:0,0:0:0); |
| if ((A2N&B1&!B2)) (A1N +=> Y) = (0:0:0,0:0:0); |
| if ((A2N&B1&B2)) (A1N +=> Y) = (0:0:0,0:0:0); |
| if ((A1N&!B1&B2)) (A2N +=> Y) = (0:0:0,0:0:0); |
| if ((A1N&B1&!B2)) (A2N +=> Y) = (0:0:0,0:0:0); |
| if ((A1N&B1&B2)) (A2N +=> Y) = (0:0:0,0:0:0); |
| if ((!A1N&!A2N&!B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1N&A2N&!B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1N&!A2N&!B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1N&!A2N&!B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1N&A2N&!B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1N&!A2N&!B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nand ( csi_opt_296 , A2N , A1N ) ; |
| or ( csi_opt_294 , B2 , B1 ) ; |
| nand #0.001 ( Y , csi_opt_296 , csi_opt_294 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o311a_0 ( X , A1 , A2 , A3 , B1 , C1 ); |
| output X ; |
| input A1 , A2 , A3 , B1 , C1 ; |
| |
| wire X , A1 , A2 , A3 ; |
| wire B1 , C1 , csi_opt_300 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 +=> X) = (0:0:0,0:0:0); |
| (A2 +=> X) = (0:0:0,0:0:0); |
| (A3 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&A3&C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&A3&B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or ( csi_opt_300 , A2 , A1 , A3 ) ; |
| and #0.001 ( X , csi_opt_300 , B1 , C1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o311a_1 ( X , A1 , A2 , A3 , B1 , C1 ); |
| output X ; |
| input A1 , A2 , A3 , B1 , C1 ; |
| |
| wire X , A1 , A2 , A3 ; |
| wire B1 , C1 , csi_opt_300 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 +=> X) = (0:0:0,0:0:0); |
| (A2 +=> X) = (0:0:0,0:0:0); |
| (A3 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&A3&C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&A3&B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or ( csi_opt_300 , A2 , A1 , A3 ) ; |
| and #0.001 ( X , csi_opt_300 , B1 , C1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o311a_2 ( X , A1 , A2 , A3 , B1 , C1 ); |
| output X ; |
| input A1 , A2 , A3 , B1 , C1 ; |
| |
| wire X , A1 , A2 , A3 ; |
| wire B1 , C1 , csi_opt_300 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 +=> X) = (0:0:0,0:0:0); |
| (A2 +=> X) = (0:0:0,0:0:0); |
| (A3 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&A3&C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&A3&B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or ( csi_opt_300 , A2 , A1 , A3 ) ; |
| and #0.001 ( X , csi_opt_300 , B1 , C1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o311a_4 ( X , A1 , A2 , A3 , B1 , C1 ); |
| output X ; |
| input A1 , A2 , A3 , B1 , C1 ; |
| |
| wire X , A1 , A2 , A3 ; |
| wire B1 , C1 , csi_opt_300 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 +=> X) = (0:0:0,0:0:0); |
| (A2 +=> X) = (0:0:0,0:0:0); |
| (A3 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&A3&C1)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&A3&B1)) (C1 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or ( csi_opt_300 , A2 , A1 , A3 ) ; |
| and #0.001 ( X , csi_opt_300 , B1 , C1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o311ai_0 ( Y , A1 , A2 , A3 , B1 , C1 ); |
| output Y ; |
| input A1 , A2 , A3 , B1 , C1 ; |
| |
| wire Y , A1 , A2 , A3 ; |
| wire B1 , C1 , csi_opt_299 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 -=> Y) = (0:0:0,0:0:0); |
| (A2 -=> Y) = (0:0:0,0:0:0); |
| (A3 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&A3&C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&A3&B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or ( csi_opt_299 , A2 , A1 , A3 ) ; |
| nand #0.001 ( Y , C1 , csi_opt_299 , B1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o311ai_1 ( Y , A1 , A2 , A3 , B1 , C1 ); |
| output Y ; |
| input A1 , A2 , A3 , B1 , C1 ; |
| |
| wire Y , A1 , A2 , A3 ; |
| wire B1 , C1 , csi_opt_299 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 -=> Y) = (0:0:0,0:0:0); |
| (A2 -=> Y) = (0:0:0,0:0:0); |
| (A3 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&A3&C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&A3&B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or ( csi_opt_299 , A2 , A1 , A3 ) ; |
| nand #0.001 ( Y , C1 , csi_opt_299 , B1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o311ai_2 ( Y , A1 , A2 , A3 , B1 , C1 ); |
| output Y ; |
| input A1 , A2 , A3 , B1 , C1 ; |
| |
| wire Y , A1 , A2 , A3 ; |
| wire B1 , C1 , csi_opt_299 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 -=> Y) = (0:0:0,0:0:0); |
| (A2 -=> Y) = (0:0:0,0:0:0); |
| (A3 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&A3&C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&A3&B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or ( csi_opt_299 , A2 , A1 , A3 ) ; |
| nand #0.001 ( Y , C1 , csi_opt_299 , B1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o311ai_4 ( Y , A1 , A2 , A3 , B1 , C1 ); |
| output Y ; |
| input A1 , A2 , A3 , B1 , C1 ; |
| |
| wire Y , A1 , A2 , A3 ; |
| wire B1 , C1 , csi_opt_299 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 -=> Y) = (0:0:0,0:0:0); |
| (A2 -=> Y) = (0:0:0,0:0:0); |
| (A3 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&A3&C1)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&A3&B1)) (C1 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or ( csi_opt_299 , A2 , A1 , A3 ) ; |
| nand #0.001 ( Y , C1 , csi_opt_299 , B1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o31a_0 ( X , A1 , A2 , A3 , B1 ); |
| output X ; |
| input A1 , A2 , A3 , B1 ; |
| |
| wire X , A1 , A2 , A3 ; |
| wire B1 , csi_opt_292 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 +=> X) = (0:0:0,0:0:0); |
| (A2 +=> X) = (0:0:0,0:0:0); |
| (A3 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&A3)) (B1 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or ( csi_opt_292 , A2 , A1 , A3 ) ; |
| and #0.001 ( X , csi_opt_292 , B1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o31a_1 ( X , A1 , A2 , A3 , B1 ); |
| output X ; |
| input A1 , A2 , A3 , B1 ; |
| |
| wire X , A1 , A2 , A3 ; |
| wire B1 , csi_opt_292 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 +=> X) = (0:0:0,0:0:0); |
| (A2 +=> X) = (0:0:0,0:0:0); |
| (A3 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&A3)) (B1 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or ( csi_opt_292 , A2 , A1 , A3 ) ; |
| and #0.001 ( X , csi_opt_292 , B1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o31a_2 ( X , A1 , A2 , A3 , B1 ); |
| output X ; |
| input A1 , A2 , A3 , B1 ; |
| |
| wire X , A1 , A2 , A3 ; |
| wire B1 , csi_opt_292 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 +=> X) = (0:0:0,0:0:0); |
| (A2 +=> X) = (0:0:0,0:0:0); |
| (A3 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&A3)) (B1 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or ( csi_opt_292 , A2 , A1 , A3 ) ; |
| and #0.001 ( X , csi_opt_292 , B1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o31a_4 ( X , A1 , A2 , A3 , B1 ); |
| output X ; |
| input A1 , A2 , A3 , B1 ; |
| |
| wire X , A1 , A2 , A3 ; |
| wire B1 , csi_opt_292 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 +=> X) = (0:0:0,0:0:0); |
| (A2 +=> X) = (0:0:0,0:0:0); |
| (A3 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&A3)) (B1 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or ( csi_opt_292 , A2 , A1 , A3 ) ; |
| and #0.001 ( X , csi_opt_292 , B1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o31ai_0 ( Y , A1 , A2 , A3 , B1 ); |
| output Y ; |
| input A1 , A2 , A3 , B1 ; |
| |
| wire Y , A1 , A2 , A3 ; |
| wire B1 , csi_opt_292 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 -=> Y) = (0:0:0,0:0:0); |
| (A2 -=> Y) = (0:0:0,0:0:0); |
| (A3 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&A3)) (B1 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or ( csi_opt_292 , A2 , A1 , A3 ) ; |
| nand #0.001 ( Y , B1 , csi_opt_292 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o31ai_1 ( Y , A1 , A2 , A3 , B1 ); |
| output Y ; |
| input A1 , A2 , A3 , B1 ; |
| |
| wire Y , A1 , A2 , A3 ; |
| wire B1 , csi_opt_292 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 -=> Y) = (0:0:0,0:0:0); |
| (A2 -=> Y) = (0:0:0,0:0:0); |
| (A3 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&A3)) (B1 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or ( csi_opt_292 , A2 , A1 , A3 ) ; |
| nand #0.001 ( Y , B1 , csi_opt_292 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o31ai_2 ( Y , A1 , A2 , A3 , B1 ); |
| output Y ; |
| input A1 , A2 , A3 , B1 ; |
| |
| wire Y , A1 , A2 , A3 ; |
| wire B1 , csi_opt_292 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 -=> Y) = (0:0:0,0:0:0); |
| (A2 -=> Y) = (0:0:0,0:0:0); |
| (A3 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&A3)) (B1 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or ( csi_opt_292 , A2 , A1 , A3 ) ; |
| nand #0.001 ( Y , B1 , csi_opt_292 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o31ai_4 ( Y , A1 , A2 , A3 , B1 ); |
| output Y ; |
| input A1 , A2 , A3 , B1 ; |
| |
| wire Y , A1 , A2 , A3 ; |
| wire B1 , csi_opt_292 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 -=> Y) = (0:0:0,0:0:0); |
| (A2 -=> Y) = (0:0:0,0:0:0); |
| (A3 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&A3)) (B1 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or ( csi_opt_292 , A2 , A1 , A3 ) ; |
| nand #0.001 ( Y , B1 , csi_opt_292 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o32a_0 ( X , A1 , A2 , A3 , B1 , B2 ); |
| output X ; |
| input A1 , A2 , A3 , B1 , B2 ; |
| |
| wire X , A1 , A2 , A3 ; |
| wire B1 , B2 , csi_opt_299, csi_opt_297 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((!A2&!A3&!B1&B2)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((!A2&!A3&B1&!B2)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((!A2&!A3&B1&B2)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A3&!B1&B2)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A3&B1&!B2)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A3&B1&B2)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!B1&B2)) (A3 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&B1&!B2)) (A3 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&B1&B2)) (A3 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&!B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&!B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&!B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&!B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&!B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&!B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&A3&!B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&!B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&!B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&!B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&!B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&!B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&!B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&A3&!B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or ( csi_opt_299 , A2 , A1 , A3 ) ; |
| or ( csi_opt_297 , B2 , B1 ) ; |
| and #0.001 ( X , csi_opt_299 , csi_opt_297 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o32a_1 ( X , A1 , A2 , A3 , B1 , B2 ); |
| output X ; |
| input A1 , A2 , A3 , B1 , B2 ; |
| |
| wire X , A1 , A2 , A3 ; |
| wire B1 , B2 , csi_opt_299, csi_opt_297 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((!A2&!A3&!B1&B2)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((!A2&!A3&B1&!B2)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((!A2&!A3&B1&B2)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A3&!B1&B2)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A3&B1&!B2)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A3&B1&B2)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!B1&B2)) (A3 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&B1&!B2)) (A3 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&B1&B2)) (A3 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&!B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&!B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&!B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&!B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&!B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&!B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&A3&!B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&!B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&!B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&!B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&!B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&!B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&!B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&A3&!B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or ( csi_opt_299 , A2 , A1 , A3 ) ; |
| or ( csi_opt_297 , B2 , B1 ) ; |
| and #0.001 ( X , csi_opt_299 , csi_opt_297 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o32a_2 ( X , A1 , A2 , A3 , B1 , B2 ); |
| output X ; |
| input A1 , A2 , A3 , B1 , B2 ; |
| |
| wire X , A1 , A2 , A3 ; |
| wire B1 , B2 , csi_opt_299, csi_opt_297 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((!A2&!A3&!B1&B2)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((!A2&!A3&B1&!B2)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((!A2&!A3&B1&B2)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A3&!B1&B2)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A3&B1&!B2)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A3&B1&B2)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!B1&B2)) (A3 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&B1&!B2)) (A3 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&B1&B2)) (A3 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&!B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&!B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&!B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&!B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&!B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&!B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&A3&!B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&!B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&!B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&!B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&!B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&!B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&!B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&A3&!B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or ( csi_opt_299 , A2 , A1 , A3 ) ; |
| or ( csi_opt_297 , B2 , B1 ) ; |
| and #0.001 ( X , csi_opt_299 , csi_opt_297 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o32a_4 ( X , A1 , A2 , A3 , B1 , B2 ); |
| output X ; |
| input A1 , A2 , A3 , B1 , B2 ; |
| |
| wire X , A1 , A2 , A3 ; |
| wire B1 , B2 , csi_opt_299, csi_opt_297 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((!A2&!A3&!B1&B2)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((!A2&!A3&B1&!B2)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((!A2&!A3&B1&B2)) (A1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A3&!B1&B2)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A3&B1&!B2)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A3&B1&B2)) (A2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!B1&B2)) (A3 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&B1&!B2)) (A3 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&B1&B2)) (A3 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&!B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&!B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&!B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&!B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&!B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&!B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&A3&!B2)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&!B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&!B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&!B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&!B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&!B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&!B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&A3&!B1)) (B2 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or ( csi_opt_299 , A2 , A1 , A3 ) ; |
| or ( csi_opt_297 , B2 , B1 ) ; |
| and #0.001 ( X , csi_opt_299 , csi_opt_297 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o32ai_0 ( Y , A1 , A2 , A3 , B1 , B2 ); |
| output Y ; |
| input A1 , A2 , A3 , B1 , B2 ; |
| |
| wire Y , A1 , A2 , A3 ; |
| wire B1 , B2 , csi_opt_273, csi_opt_274 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((!A2&!A3&!B1&B2)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A2&!A3&B1&!B2)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A2&!A3&B1&B2)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A3&!B1&B2)) (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A3&B1&!B2)) (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A3&B1&B2)) (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!B1&B2)) (A3 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&B1&!B2)) (A3 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&B1&B2)) (A3 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&!B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&!B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&!B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&!B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&!B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&!B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&A3&!B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&!B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&!B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&!B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&!B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&!B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&!B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&A3&!B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nor ( csi_opt_273 , A3 , A1 , A2 ) ; |
| nor ( csi_opt_274 , B1 , B2 ) ; |
| or #0.001 ( Y , csi_opt_274 , csi_opt_273 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o32ai_1 ( Y , A1 , A2 , A3 , B1 , B2 ); |
| output Y ; |
| input A1 , A2 , A3 , B1 , B2 ; |
| |
| wire Y , A1 , A2 , A3 ; |
| wire B1 , B2 , csi_opt_273, csi_opt_274 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((!A2&!A3&!B1&B2)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A2&!A3&B1&!B2)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A2&!A3&B1&B2)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A3&!B1&B2)) (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A3&B1&!B2)) (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A3&B1&B2)) (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!B1&B2)) (A3 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&B1&!B2)) (A3 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&B1&B2)) (A3 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&!B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&!B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&!B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&!B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&!B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&!B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&A3&!B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&!B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&!B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&!B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&!B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&!B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&!B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&A3&!B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nor ( csi_opt_273 , A3 , A1 , A2 ) ; |
| nor ( csi_opt_274 , B1 , B2 ) ; |
| or #0.001 ( Y , csi_opt_274 , csi_opt_273 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o32ai_2 ( Y , A1 , A2 , A3 , B1 , B2 ); |
| output Y ; |
| input A1 , A2 , A3 , B1 , B2 ; |
| |
| wire Y , A1 , A2 , A3 ; |
| wire B1 , B2 , csi_opt_273, csi_opt_274 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((!A2&!A3&!B1&B2)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A2&!A3&B1&!B2)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A2&!A3&B1&B2)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A3&!B1&B2)) (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A3&B1&!B2)) (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A3&B1&B2)) (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!B1&B2)) (A3 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&B1&!B2)) (A3 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&B1&B2)) (A3 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&!B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&!B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&!B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&!B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&!B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&!B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&A3&!B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&!B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&!B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&!B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&!B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&!B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&!B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&A3&!B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nor ( csi_opt_273 , A3 , A1 , A2 ) ; |
| nor ( csi_opt_274 , B1 , B2 ) ; |
| or #0.001 ( Y , csi_opt_274 , csi_opt_273 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o32ai_4 ( Y , A1 , A2 , A3 , B1 , B2 ); |
| output Y ; |
| input A1 , A2 , A3 , B1 , B2 ; |
| |
| wire Y , A1 , A2 , A3 ; |
| wire B1 , B2 , csi_opt_273, csi_opt_274 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((!A2&!A3&!B1&B2)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A2&!A3&B1&!B2)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A2&!A3&B1&B2)) (A1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A3&!B1&B2)) (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A3&B1&!B2)) (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A3&B1&B2)) (A2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!B1&B2)) (A3 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&B1&!B2)) (A3 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&B1&B2)) (A3 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&!B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&!B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&!B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&!B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&!B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&!B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&A3&!B2)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&!B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&!B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&!B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&!B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&!B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&!B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&A3&!B1)) (B2 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nor ( csi_opt_273 , A3 , A1 , A2 ) ; |
| nor ( csi_opt_274 , B1 , B2 ) ; |
| or #0.001 ( Y , csi_opt_274 , csi_opt_273 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o41a_0 ( X , A1 , A2 , A3 , A4 , B1 ); |
| output X ; |
| input A1 , A2 , A3 , A4 , B1 ; |
| |
| wire X , A1 , A2 , A3 ; |
| wire A4 , B1 , csi_opt_297 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 +=> X) = (0:0:0,0:0:0); |
| (A2 +=> X) = (0:0:0,0:0:0); |
| (A3 +=> X) = (0:0:0,0:0:0); |
| (A4 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!A3&A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&A3&A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or ( csi_opt_297 , A4 , A3 , A2 , A1 ) ; |
| and #0.001 ( X , csi_opt_297 , B1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o41a_1 ( X , A1 , A2 , A3 , A4 , B1 ); |
| output X ; |
| input A1 , A2 , A3 , A4 , B1 ; |
| |
| wire X , A1 , A2 , A3 ; |
| wire A4 , B1 , csi_opt_297 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 +=> X) = (0:0:0,0:0:0); |
| (A2 +=> X) = (0:0:0,0:0:0); |
| (A3 +=> X) = (0:0:0,0:0:0); |
| (A4 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!A3&A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&A3&A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or ( csi_opt_297 , A4 , A3 , A2 , A1 ) ; |
| and #0.001 ( X , csi_opt_297 , B1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o41a_2 ( X , A1 , A2 , A3 , A4 , B1 ); |
| output X ; |
| input A1 , A2 , A3 , A4 , B1 ; |
| |
| wire X , A1 , A2 , A3 ; |
| wire A4 , B1 , csi_opt_297 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 +=> X) = (0:0:0,0:0:0); |
| (A2 +=> X) = (0:0:0,0:0:0); |
| (A3 +=> X) = (0:0:0,0:0:0); |
| (A4 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!A3&A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&A3&A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or ( csi_opt_297 , A4 , A3 , A2 , A1 ) ; |
| and #0.001 ( X , csi_opt_297 , B1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o41a_4 ( X , A1 , A2 , A3 , A4 , B1 ); |
| output X ; |
| input A1 , A2 , A3 , A4 , B1 ; |
| |
| wire X , A1 , A2 , A3 ; |
| wire A4 , B1 , csi_opt_297 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 +=> X) = (0:0:0,0:0:0); |
| (A2 +=> X) = (0:0:0,0:0:0); |
| (A3 +=> X) = (0:0:0,0:0:0); |
| (A4 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!A3&A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| if ((A1&A2&A3&A4)) (B1 +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or ( csi_opt_297 , A4 , A3 , A2 , A1 ) ; |
| and #0.001 ( X , csi_opt_297 , B1 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o41ai_0 ( Y , A1 , A2 , A3 , A4 , B1 ); |
| output Y ; |
| input A1 , A2 , A3 , A4 , B1 ; |
| |
| wire Y , A1 , A2 , A3 ; |
| wire A4 , B1 , csi_opt_297 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 -=> Y) = (0:0:0,0:0:0); |
| (A2 -=> Y) = (0:0:0,0:0:0); |
| (A3 -=> Y) = (0:0:0,0:0:0); |
| (A4 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!A3&A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&!A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&!A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&!A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&!A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&!A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&!A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&A3&!A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&A3&A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or ( csi_opt_297 , A4 , A3 , A2 , A1 ) ; |
| nand #0.001 ( Y , B1 , csi_opt_297 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o41ai_1 ( Y , A1 , A2 , A3 , A4 , B1 ); |
| output Y ; |
| input A1 , A2 , A3 , A4 , B1 ; |
| |
| wire Y , A1 , A2 , A3 ; |
| wire A4 , B1 , csi_opt_297 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 -=> Y) = (0:0:0,0:0:0); |
| (A2 -=> Y) = (0:0:0,0:0:0); |
| (A3 -=> Y) = (0:0:0,0:0:0); |
| (A4 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!A3&A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&!A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&!A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&!A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&!A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&!A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&!A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&A3&!A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&A3&A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or ( csi_opt_297 , A4 , A3 , A2 , A1 ) ; |
| nand #0.001 ( Y , B1 , csi_opt_297 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o41ai_2 ( Y , A1 , A2 , A3 , A4 , B1 ); |
| output Y ; |
| input A1 , A2 , A3 , A4 , B1 ; |
| |
| wire Y , A1 , A2 , A3 ; |
| wire A4 , B1 , csi_opt_297 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 -=> Y) = (0:0:0,0:0:0); |
| (A2 -=> Y) = (0:0:0,0:0:0); |
| (A3 -=> Y) = (0:0:0,0:0:0); |
| (A4 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!A3&A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&!A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&!A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&!A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&!A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&!A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&!A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&A3&!A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&A3&A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or ( csi_opt_297 , A4 , A3 , A2 , A1 ) ; |
| nand #0.001 ( Y , B1 , csi_opt_297 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_o41ai_4 ( Y , A1 , A2 , A3 , A4 , B1 ); |
| output Y ; |
| input A1 , A2 , A3 , A4 , B1 ; |
| |
| wire Y , A1 , A2 , A3 ; |
| wire A4 , B1 , csi_opt_297 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A1 -=> Y) = (0:0:0,0:0:0); |
| (A2 -=> Y) = (0:0:0,0:0:0); |
| (A3 -=> Y) = (0:0:0,0:0:0); |
| (A4 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&!A3&A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&!A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&!A2&A3&A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&!A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&!A3&A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&!A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((!A1&A2&A3&A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&!A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&!A3&A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&!A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&!A2&A3&A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&!A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&!A3&A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&A3&!A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| if ((A1&A2&A3&A4)) (B1 -=> Y) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or ( csi_opt_297 , A4 , A3 , A2 , A1 ) ; |
| nand #0.001 ( Y , B1 , csi_opt_297 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_or2_0 ( X , A , B ); |
| output X ; |
| input A , B ; |
| |
| wire X , A , B ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X) = (0:0:0,0:0:0); |
| (B +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or #0.001 ( X , B , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_or2_1 ( X , A , B ); |
| output X ; |
| input A , B ; |
| |
| wire X , A , B ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X) = (0:0:0,0:0:0); |
| (B +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or #0.001 ( X , B , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_or2_2 ( X , A , B ); |
| output X ; |
| input A , B ; |
| |
| wire X , A , B ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X) = (0:0:0,0:0:0); |
| (B +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or #0.001 ( X , B , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_or2_4 ( X , A , B ); |
| output X ; |
| input A , B ; |
| |
| wire X , A , B ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X) = (0:0:0,0:0:0); |
| (B +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or #0.001 ( X , B , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_or2b_1 ( X , A , BN ); |
| output X ; |
| input A , BN ; |
| |
| wire X , A , BN , csi_opt_276 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X) = (0:0:0,0:0:0); |
| (BN -=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| not ( csi_opt_276 , BN ) ; |
| or #0.001 ( X , csi_opt_276 , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_or2b_2 ( X , A , BN ); |
| output X ; |
| input A , BN ; |
| |
| wire X , A , BN , csi_opt_276 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X) = (0:0:0,0:0:0); |
| (BN -=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| not ( csi_opt_276 , BN ) ; |
| or #0.001 ( X , csi_opt_276 , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_or2b_4 ( X , A , BN ); |
| output X ; |
| input A , BN ; |
| |
| wire X , A , BN , csi_opt_276 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X) = (0:0:0,0:0:0); |
| (BN -=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| not ( csi_opt_276 , BN ) ; |
| or #0.001 ( X , csi_opt_276 , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_or3_0 ( X , A , B , C ); |
| output X ; |
| input A , B , C ; |
| |
| wire X , A , B , C ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X) = (0:0:0,0:0:0); |
| (B +=> X) = (0:0:0,0:0:0); |
| (C +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or #0.001 ( X , B , A , C ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_or3_1 ( X , A , B , C ); |
| output X ; |
| input A , B , C ; |
| |
| wire X , A , B , C ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X) = (0:0:0,0:0:0); |
| (B +=> X) = (0:0:0,0:0:0); |
| (C +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or #0.001 ( X , B , A , C ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_or3_2 ( X , A , B , C ); |
| output X ; |
| input A , B , C ; |
| |
| wire X , A , B , C ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X) = (0:0:0,0:0:0); |
| (B +=> X) = (0:0:0,0:0:0); |
| (C +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or #0.001 ( X , B , A , C ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_or3_4 ( X , A , B , C ); |
| output X ; |
| input A , B , C ; |
| |
| wire X , A , B , C ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X) = (0:0:0,0:0:0); |
| (B +=> X) = (0:0:0,0:0:0); |
| (C +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or #0.001 ( X , B , A , C ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_or3b_1 ( X , A , B , CN ); |
| output X ; |
| input A , B , CN ; |
| |
| wire X , A , B , CN ; |
| wire csi_opt_278 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X) = (0:0:0,0:0:0); |
| (B +=> X) = (0:0:0,0:0:0); |
| (CN -=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| not ( csi_opt_278 , CN ) ; |
| or #0.001 ( X , B , A , csi_opt_278 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_or3b_2 ( X , A , B , CN ); |
| output X ; |
| input A , B , CN ; |
| |
| wire X , A , B , CN ; |
| wire csi_opt_278 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X) = (0:0:0,0:0:0); |
| (B +=> X) = (0:0:0,0:0:0); |
| (CN -=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| not ( csi_opt_278 , CN ) ; |
| or #0.001 ( X , B , A , csi_opt_278 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_or3b_4 ( X , A , B , CN ); |
| output X ; |
| input A , B , CN ; |
| |
| wire X , A , B , CN ; |
| wire csi_opt_278 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X) = (0:0:0,0:0:0); |
| (B +=> X) = (0:0:0,0:0:0); |
| (CN -=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| not ( csi_opt_278 , CN ) ; |
| or #0.001 ( X , B , A , csi_opt_278 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_or4_0 ( X , A , B , C , D ); |
| output X ; |
| input A , B , C , D ; |
| |
| wire X , A , B , C ; |
| wire D ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X) = (0:0:0,0:0:0); |
| (B +=> X) = (0:0:0,0:0:0); |
| (C +=> X) = (0:0:0,0:0:0); |
| (D +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or #0.001 ( X , D , C , B , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_or4_1 ( X , A , B , C , D ); |
| output X ; |
| input A , B , C , D ; |
| |
| wire X , A , B , C ; |
| wire D ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X) = (0:0:0,0:0:0); |
| (B +=> X) = (0:0:0,0:0:0); |
| (C +=> X) = (0:0:0,0:0:0); |
| (D +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or #0.001 ( X , D , C , B , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_or4_2 ( X , A , B , C , D ); |
| output X ; |
| input A , B , C , D ; |
| |
| wire X , A , B , C ; |
| wire D ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X) = (0:0:0,0:0:0); |
| (B +=> X) = (0:0:0,0:0:0); |
| (C +=> X) = (0:0:0,0:0:0); |
| (D +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or #0.001 ( X , D , C , B , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_or4_4 ( X , A , B , C , D ); |
| output X ; |
| input A , B , C , D ; |
| |
| wire X , A , B , C ; |
| wire D ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X) = (0:0:0,0:0:0); |
| (B +=> X) = (0:0:0,0:0:0); |
| (C +=> X) = (0:0:0,0:0:0); |
| (D +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| or #0.001 ( X , D , C , B , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_or4b_1 ( X , A , B , C , DN ); |
| output X ; |
| input A , B , C , DN ; |
| |
| wire X , A , B , C ; |
| wire DN , csi_opt_281 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X) = (0:0:0,0:0:0); |
| (B +=> X) = (0:0:0,0:0:0); |
| (C +=> X) = (0:0:0,0:0:0); |
| (DN -=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| not ( csi_opt_281 , DN ) ; |
| or #0.001 ( X , csi_opt_281 , C , B , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_or4b_2 ( X , A , B , C , DN ); |
| output X ; |
| input A , B , C , DN ; |
| |
| wire X , A , B , C ; |
| wire DN , csi_opt_281 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X) = (0:0:0,0:0:0); |
| (B +=> X) = (0:0:0,0:0:0); |
| (C +=> X) = (0:0:0,0:0:0); |
| (DN -=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| not ( csi_opt_281 , DN ) ; |
| or #0.001 ( X , csi_opt_281 , C , B , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_or4b_4 ( X , A , B , C , DN ); |
| output X ; |
| input A , B , C , DN ; |
| |
| wire X , A , B , C ; |
| wire DN , csi_opt_281 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X) = (0:0:0,0:0:0); |
| (B +=> X) = (0:0:0,0:0:0); |
| (C +=> X) = (0:0:0,0:0:0); |
| (DN -=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| not ( csi_opt_281 , DN ) ; |
| or #0.001 ( X , csi_opt_281 , C , B , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_or4bb_1 ( X , A , B , CN , DN ); |
| output X ; |
| input A , B , CN , DN ; |
| |
| wire X , A , B , CN ; |
| wire DN , csi_opt_283 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X) = (0:0:0,0:0:0); |
| (B +=> X) = (0:0:0,0:0:0); |
| (CN -=> X) = (0:0:0,0:0:0); |
| (DN -=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nand ( csi_opt_283 , DN , CN ) ; |
| or #0.001 ( X , B , A , csi_opt_283 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_or4bb_2 ( X , A , B , CN , DN ); |
| output X ; |
| input A , B , CN , DN ; |
| |
| wire X , A , B , CN ; |
| wire DN , csi_opt_283 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X) = (0:0:0,0:0:0); |
| (B +=> X) = (0:0:0,0:0:0); |
| (CN -=> X) = (0:0:0,0:0:0); |
| (DN -=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nand ( csi_opt_283 , DN , CN ) ; |
| or #0.001 ( X , B , A , csi_opt_283 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_or4bb_4 ( X , A , B , CN , DN ); |
| output X ; |
| input A , B , CN , DN ; |
| |
| wire X , A , B , CN ; |
| wire DN , csi_opt_283 ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| (A +=> X) = (0:0:0,0:0:0); |
| (B +=> X) = (0:0:0,0:0:0); |
| (CN -=> X) = (0:0:0,0:0:0); |
| (DN -=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| nand ( csi_opt_283 , DN , CN ) ; |
| or #0.001 ( X , B , A , csi_opt_283 ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_sdfbbn_1 (Q, QN, D, SCD, SCE, CLKN, SETB, RESETB); |
| output Q,QN; |
| input D,SCD,SCE,CLKN,SETB,RESETB; |
| |
| wire reset, set, clk, buf_Q; |
| |
| `ifdef functional |
| not (reset,RESETB); |
| not (set,SETB); |
| not (clk, CLKN); |
| U_MUX_2_1 (mux_out,D,SCD,SCE); |
| U_DFB_SETDOM #1 (buf_Q,set,reset,clk,mux_out); |
| `else |
| reg notifier; |
| |
| wire D_delayed, SCD_delayed, SCE_delayed, CLKN_delayed, SETB_delayed, RESETB_delayed; |
| |
| not (reset,RESETB_delayed); |
| not (set,SETB_delayed); |
| not (clk, CLKN_delayed); |
| U_MUX_2_1 (mux_out,D_delayed,SCD_delayed,SCE_delayed); |
| U_DFB_SETDOM_notify #0.001 (buf_Q,set,reset,clk,mux_out,notifier); |
| |
| wire COND0, COND1, CONDB, COND_D, COND_SCD, COND_SCE ; |
| assign COND0 = (RESETB_delayed === 1'b1); |
| assign COND1 = (SETB_delayed === 1'b1); |
| assign CONDB = (COND0 & COND1); |
| assign COND_D = ((SCE_delayed === 1'b0)&CONDB); |
| assign COND_SCD = ((SCE_delayed === 1'b1)&CONDB); |
| assign COND_SCE = ((D_delayed !== SCD_delayed)&CONDB); |
| specify |
| (negedge RESETB => (Q +: RESETB ) ) = 0:0:0; // delay is tfall |
| (negedge RESETB => (QN -: RESETB ) ) = 0:0:0; // delay is tris |
| |
| (SETB => (Q -: SETB ) ) = (0:0:0,0:0:0); // delay is tris,tfall |
| (SETB => (QN +: SETB ) ) = (0:0:0,0:0:0); // delay is tris,tfall |
| |
| (negedge CLKN => (Q +: D ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| (negedge CLKN => (QN -: D ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| |
| $width (negedge CLKN &&& CONDB , 0:0:0, 0, notifier); |
| $width (posedge CLKN &&& CONDB , 0:0:0, 0, notifier); |
| $width (negedge SETB , 0.5, 0, notifier); |
| $width (negedge RESETB , 0.5, 0, notifier); |
| |
| $recrem ( posedge SETB , negedge CLKN , 0:0:0, 0:0:0, notifier , , COND0, SETB_delayed , CLKN_delayed ) ; |
| $recovery ( posedge SETB , negedge CLKN , 0:0:0, 0:0:0, notifier , , COND0, SETB_delayed , CLKN_delayed ) ; |
| $hold ( negedge CLKN , posedge SETB , 0:0:0, notifier ) ; |
| $recrem ( posedge RESETB , negedge CLKN , 0:0:0, 0:0:0, notifier , , COND1, RESETB_delayed , CLKN_delayed ) ; |
| $recovery ( posedge RESETB , negedge CLKN , 0:0:0, 0:0:0, notifier , , COND1, RESETB_delayed , CLKN_delayed ) ; |
| $hold ( negedge CLKN , posedge RESETB , 0:0:0, notifier ) ; |
| |
| $setuphold ( negedge CLKN , posedge D , 0:0:0, 0:0:0, notifier , , COND_D , CLKN_delayed , D_delayed ) ; |
| $setuphold ( negedge CLKN , negedge D , 0:0:0, 0:0:0, notifier , , COND_D , CLKN_delayed , D_delayed ) ; |
| |
| $setuphold ( negedge CLKN , posedge SCD , 0:0:0, 0:0:0, notifier , , COND_SCD , CLKN_delayed , SCD_delayed ) ; |
| $setuphold ( negedge CLKN , negedge SCD , 0:0:0, 0:0:0, notifier , , COND_SCD , CLKN_delayed , SCD_delayed ) ; |
| |
| $setuphold ( negedge CLKN , posedge SCE , 0:0:0, 0:0:0, notifier , , COND_SCE , CLKN_delayed , SCE_delayed ) ; |
| $setuphold ( negedge CLKN , negedge SCE , 0:0:0, 0:0:0, notifier , , COND_SCE , CLKN_delayed , SCE_delayed ) ; |
| |
| |
| $hold (posedge SETB, posedge RESETB, 3.0 , notifier); //arbitrary, uncharacterized value to |
| //flag possible state error |
| |
| $hold (posedge RESETB, posedge SETB, 3.0 , notifier); //arbitrary, uncharacterized value to |
| //flag possible state error |
| |
| endspecify |
| |
| |
| `endif |
| buf (Q,buf_Q); |
| not (QN,buf_Q); |
| |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_sdfbbn_2 (Q, QN, D, SCD, SCE, CLKN, SETB, RESETB); |
| output Q,QN; |
| input D,SCD,SCE,CLKN,SETB,RESETB; |
| |
| wire reset, set, clk, buf_Q; |
| |
| `ifdef functional |
| not (reset,RESETB); |
| not (set,SETB); |
| not (clk, CLKN); |
| U_MUX_2_1 (mux_out,D,SCD,SCE); |
| U_DFB_SETDOM #1 (buf_Q,set,reset,clk,mux_out); |
| `else |
| reg notifier; |
| |
| wire D_delayed, SCD_delayed, SCE_delayed, CLKN_delayed, SETB_delayed, RESETB_delayed; |
| |
| not (reset,RESETB_delayed); |
| not (set,SETB_delayed); |
| not (clk, CLKN_delayed); |
| U_MUX_2_1 (mux_out,D_delayed,SCD_delayed,SCE_delayed); |
| U_DFB_SETDOM_notify #0.001 (buf_Q,set,reset,clk,mux_out,notifier); |
| |
| wire COND0, COND1, CONDB, COND_D, COND_SCD, COND_SCE ; |
| assign COND0 = (RESETB_delayed === 1'b1); |
| assign COND1 = (SETB_delayed === 1'b1); |
| assign CONDB = (COND0 & COND1); |
| assign COND_D = ((SCE_delayed === 1'b0)&CONDB); |
| assign COND_SCD = ((SCE_delayed === 1'b1)&CONDB); |
| assign COND_SCE = ((D_delayed !== SCD_delayed)&CONDB); |
| specify |
| (negedge RESETB => (Q +: RESETB ) ) = 0:0:0; // delay is tfall |
| (negedge RESETB => (QN -: RESETB ) ) = 0:0:0; // delay is tris |
| |
| (SETB => (Q -: SETB ) ) = (0:0:0,0:0:0); // delay is tris,tfall |
| (SETB => (QN +: SETB ) ) = (0:0:0,0:0:0); // delay is tris,tfall |
| |
| (negedge CLKN => (Q +: D ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| (negedge CLKN => (QN -: D ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| |
| $width (negedge CLKN &&& CONDB , 0:0:0, 0, notifier); |
| $width (posedge CLKN &&& CONDB , 0:0:0, 0, notifier); |
| $width (negedge SETB , 0.5, 0, notifier); |
| $width (negedge RESETB , 0.5, 0, notifier); |
| |
| $recrem ( posedge SETB , negedge CLKN , 0:0:0, 0:0:0, notifier , , COND0, SETB_delayed , CLKN_delayed ) ; |
| $recovery ( posedge SETB , negedge CLKN , 0:0:0, 0:0:0, notifier , , COND0, SETB_delayed , CLKN_delayed ) ; |
| $hold ( negedge CLKN , posedge SETB , 0:0:0, notifier ) ; |
| $recrem ( posedge RESETB , negedge CLKN , 0:0:0, 0:0:0, notifier , , COND1, RESETB_delayed , CLKN_delayed ) ; |
| $recovery ( posedge RESETB , negedge CLKN , 0:0:0, 0:0:0, notifier , , COND1, RESETB_delayed , CLKN_delayed ) ; |
| $hold ( negedge CLKN , posedge RESETB , 0:0:0, notifier ) ; |
| |
| $setuphold ( negedge CLKN , posedge D , 0:0:0, 0:0:0, notifier , , COND_D , CLKN_delayed , D_delayed ) ; |
| $setuphold ( negedge CLKN , negedge D , 0:0:0, 0:0:0, notifier , , COND_D , CLKN_delayed , D_delayed ) ; |
| |
| $setuphold ( negedge CLKN , posedge SCD , 0:0:0, 0:0:0, notifier , , COND_SCD , CLKN_delayed , SCD_delayed ) ; |
| $setuphold ( negedge CLKN , negedge SCD , 0:0:0, 0:0:0, notifier , , COND_SCD , CLKN_delayed , SCD_delayed ) ; |
| |
| $setuphold ( negedge CLKN , posedge SCE , 0:0:0, 0:0:0, notifier , , COND_SCE , CLKN_delayed , SCE_delayed ) ; |
| $setuphold ( negedge CLKN , negedge SCE , 0:0:0, 0:0:0, notifier , , COND_SCE , CLKN_delayed , SCE_delayed ) ; |
| |
| |
| $hold (posedge SETB, posedge RESETB, 3.0 , notifier); //arbitrary, uncharacterized value to |
| //flag possible state error |
| |
| $hold (posedge RESETB, posedge SETB, 3.0 , notifier); //arbitrary, uncharacterized value to |
| //flag possible state error |
| |
| endspecify |
| |
| |
| `endif |
| buf (Q,buf_Q); |
| not (QN,buf_Q); |
| |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_sdfbbp_1 (Q, QN, D, SCD, SCE, CLK, SETB, RESETB); |
| output Q,QN; |
| input D,SCD,SCE,CLK,SETB,RESETB; |
| |
| wire reset, set, clk, buf_Q; |
| |
| `ifdef functional |
| not (reset,RESETB); |
| not (set,SETB); |
| U_MUX_2_1 (mux_out,D,SCD,SCE); |
| U_DFB_SETDOM #1 (buf_Q,set,reset,CLK,mux_out); |
| `else |
| reg notifier; |
| |
| wire D_delayed, SCD_delayed, SCE_delayed, CLK_delayed, SETB_delayed, RESETB_delayed; |
| |
| not (reset,RESETB_delayed); |
| not (set,SETB_delayed); |
| U_MUX_2_1 (mux_out,D_delayed,SCD_delayed,SCE_delayed); |
| U_DFB_SETDOM_notify #0.001 (buf_Q,set,reset,CLK_delayed,mux_out,notifier); |
| |
| wire COND0, COND1, CONDB, COND_D, COND_SCD, COND_SCE ; |
| assign COND0 = (RESETB_delayed === 1'b1); |
| assign COND1 = (SETB_delayed === 1'b1); |
| assign CONDB = (COND0 & COND1); |
| assign COND_D = ((SCE_delayed === 1'b0)&CONDB); |
| assign COND_SCD = ((SCE_delayed === 1'b1)&CONDB); |
| assign COND_SCE = ((D_delayed !== SCD_delayed)&CONDB); |
| specify |
| (negedge RESETB => (Q +: RESETB ) ) = 0:0:0; // delay is tfall |
| (negedge RESETB => (QN -: RESETB ) ) = 0:0:0; // delay is tris |
| |
| (SETB => (Q -: SETB ) ) = (0:0:0,0:0:0); // delay is tris,tfall |
| (SETB => (QN +: SETB ) ) = (0:0:0,0:0:0); // delay is tris,tfall |
| |
| (posedge CLK => (Q +: D ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| (posedge CLK => (QN -: D ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| |
| $width (negedge CLK &&& CONDB , 0:0:0, 0, notifier); |
| $width (posedge CLK &&& CONDB , 0:0:0, 0, notifier); |
| $width (negedge SETB , 0.5, 0, notifier); |
| $width (negedge RESETB , 0.5, 0, notifier); |
| |
| $recrem ( posedge SETB , posedge CLK , 0:0:0, 0:0:0, notifier , , COND0, SETB_delayed , CLK_delayed ) ; |
| $recovery ( posedge SETB , posedge CLK , 0:0:0, 0:0:0, notifier , , COND0, SETB_delayed , CLK_delayed ) ; |
| $hold ( posedge CLK , posedge SETB , 0:0:0, notifier ) ; |
| $recrem ( posedge RESETB , posedge CLK , 0:0:0, 0:0:0, notifier , , COND1, RESETB_delayed , CLK_delayed ) ; |
| $recovery ( posedge RESETB , posedge CLK , 0:0:0, 0:0:0, notifier , , COND1, RESETB_delayed , CLK_delayed ) ; |
| $hold ( posedge CLK , posedge RESETB , 0:0:0, notifier ) ; |
| |
| $setuphold ( posedge CLK , posedge D , 0:0:0, 0:0:0, notifier , , COND_D , CLK_delayed , D_delayed ) ; |
| $setuphold ( posedge CLK , negedge D , 0:0:0, 0:0:0, notifier , , COND_D , CLK_delayed , D_delayed ) ; |
| |
| $setuphold ( posedge CLK , posedge SCD , 0:0:0, 0:0:0, notifier , , COND_SCD , CLK_delayed , SCD_delayed ) ; |
| $setuphold ( posedge CLK , negedge SCD , 0:0:0, 0:0:0, notifier , , COND_SCD , CLK_delayed , SCD_delayed ) ; |
| |
| $setuphold ( posedge CLK , posedge SCE , 0:0:0, 0:0:0, notifier , , COND_SCE , CLK_delayed , SCE_delayed ) ; |
| $setuphold ( posedge CLK , negedge SCE , 0:0:0, 0:0:0, notifier , , COND_SCE , CLK_delayed , SCE_delayed ) ; |
| |
| |
| $hold (posedge SETB, posedge RESETB, 3.0 , notifier); //arbitrary, uncharacterized value to |
| //flag possible state error |
| |
| $hold (posedge RESETB, posedge SETB, 3.0 , notifier); //arbitrary, uncharacterized value to |
| //flag possible state error |
| |
| endspecify |
| |
| |
| `endif |
| buf (Q,buf_Q); |
| not (QN,buf_Q); |
| |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_sdfrbp_1 (RESETB,CLK,D,Q,QN,SCD,SCE); |
| |
| output Q,QN; |
| input CLK,D,SCD,SCE,RESETB; |
| wire buf_Q, reset, mux_out; |
| |
| `ifdef functional |
| not (reset,RESETB); |
| U_MUX_2_1 (mux_out,D,SCD,SCE); |
| U_DF_P_R #1 ( buf_Q , mux_out , CLK , reset ) ; |
| `else |
| reg notifier; |
| wire COND0, COND1, COND2, COND3 ; |
| wire D_delayed, SCD_delayed, SCE_delayed, RESETB_delayed , CLK_delayed ; |
| not (reset,RESETB_delayed); |
| U_MUX_2_1 (mux_out,D_delayed,SCD_delayed,SCE_delayed); |
| U_DF_P_R_NO #0.001 ( buf_Q , mux_out , CLK_delayed , reset , notifier ) ; |
| |
| assign COND0 = (RESETB_delayed === 1'b1); |
| assign COND1 = ((SCE_delayed === 1'b0)&COND0); |
| assign COND2 = ((SCE_delayed === 1'b1)&COND0); |
| assign COND3 = ((D_delayed !== SCD_delayed)&COND0); |
| specify |
| (negedge RESETB => (Q +: RESETB ) ) = 0:0:0; // delay is tris |
| (negedge RESETB => (QN -: RESETB ) ) = 0:0:0; // delay is tris |
| (posedge CLK => (Q : CLK ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| (posedge CLK => (QN : CLK ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| $width (posedge CLK &&& (RESETB===1'b1) , 0:0:0, 0, notifier); |
| $width (negedge CLK &&& (RESETB===1'b1) , 0:0:0, 0, notifier); |
| $width (negedge RESETB , 0.5, 0, notifier); |
| $recrem ( posedge RESETB , posedge CLK , 0:0:0, 0:0:0, notifier , , , RESETB_delayed , CLK_delayed ) ; |
| $recovery ( posedge RESETB , posedge CLK , 0:0:0, 0:0:0, notifier , , , RESETB_delayed , CLK_delayed ) ; |
| $hold ( posedge CLK , posedge RESETB , 0:0:0, notifier ) ; |
| $setuphold ( posedge CLK , posedge D , 0:0:0, 0:0:0, notifier , , COND1 , CLK_delayed , D_delayed ) ; |
| $setuphold ( posedge CLK , negedge D , 0:0:0, 0:0:0, notifier , , COND1 , CLK_delayed , D_delayed ) ; |
| $setuphold ( posedge CLK , posedge SCD , 0:0:0, 0:0:0, notifier , , COND2 , CLK_delayed , SCD_delayed ) ; |
| $setuphold ( posedge CLK , negedge SCD , 0:0:0, 0:0:0, notifier , , COND2 , CLK_delayed , SCD_delayed ) ; |
| $setuphold ( posedge CLK , posedge SCE , 0:0:0, 0:0:0, notifier , , COND3 , CLK_delayed , SCE_delayed ) ; |
| $setuphold ( posedge CLK , negedge SCE , 0:0:0, 0:0:0, notifier , , COND3 , CLK_delayed , SCE_delayed ) ; |
| endspecify |
| `endif |
| |
| buf (Q,buf_Q); |
| not (QN,buf_Q); |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_sdfrbp_2 (RESETB,CLK,D,Q,QN,SCD,SCE); |
| |
| output Q,QN; |
| input CLK,D,SCD,SCE,RESETB; |
| wire buf_Q, reset, mux_out; |
| |
| `ifdef functional |
| not (reset,RESETB); |
| U_MUX_2_1 (mux_out,D,SCD,SCE); |
| U_DF_P_R #1 ( buf_Q , mux_out , CLK , reset ) ; |
| `else |
| reg notifier; |
| wire COND0, COND1, COND2, COND3 ; |
| wire D_delayed, SCD_delayed, SCE_delayed, RESETB_delayed , CLK_delayed ; |
| not (reset,RESETB_delayed); |
| U_MUX_2_1 (mux_out,D_delayed,SCD_delayed,SCE_delayed); |
| U_DF_P_R_NO #0.001 ( buf_Q , mux_out , CLK_delayed , reset , notifier ) ; |
| |
| assign COND0 = (RESETB_delayed === 1'b1); |
| assign COND1 = ((SCE_delayed === 1'b0)&COND0); |
| assign COND2 = ((SCE_delayed === 1'b1)&COND0); |
| assign COND3 = ((D_delayed !== SCD_delayed)&COND0); |
| specify |
| (negedge RESETB => (Q +: RESETB ) ) = 0:0:0; // delay is tris |
| (negedge RESETB => (QN -: RESETB ) ) = 0:0:0; // delay is tris |
| (posedge CLK => (Q : CLK ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| (posedge CLK => (QN : CLK ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| $width (posedge CLK &&& (RESETB===1'b1) , 0:0:0, 0, notifier); |
| $width (negedge CLK &&& (RESETB===1'b1) , 0:0:0, 0, notifier); |
| $width (negedge RESETB , 0.5, 0, notifier); |
| $recrem ( posedge RESETB , posedge CLK , 0:0:0, 0:0:0, notifier , , , RESETB_delayed , CLK_delayed ) ; |
| $recovery ( posedge RESETB , posedge CLK , 0:0:0, 0:0:0, notifier , , , RESETB_delayed , CLK_delayed ) ; |
| $hold ( posedge CLK , posedge RESETB , 0:0:0, notifier ) ; |
| $setuphold ( posedge CLK , posedge D , 0:0:0, 0:0:0, notifier , , COND1 , CLK_delayed , D_delayed ) ; |
| $setuphold ( posedge CLK , negedge D , 0:0:0, 0:0:0, notifier , , COND1 , CLK_delayed , D_delayed ) ; |
| $setuphold ( posedge CLK , posedge SCD , 0:0:0, 0:0:0, notifier , , COND2 , CLK_delayed , SCD_delayed ) ; |
| $setuphold ( posedge CLK , negedge SCD , 0:0:0, 0:0:0, notifier , , COND2 , CLK_delayed , SCD_delayed ) ; |
| $setuphold ( posedge CLK , posedge SCE , 0:0:0, 0:0:0, notifier , , COND3 , CLK_delayed , SCE_delayed ) ; |
| $setuphold ( posedge CLK , negedge SCE , 0:0:0, 0:0:0, notifier , , COND3 , CLK_delayed , SCE_delayed ) ; |
| endspecify |
| `endif |
| |
| buf (Q,buf_Q); |
| not (QN,buf_Q); |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_sdfrtn_1 (RESETB,CLKN,D,Q,SCD,SCE); |
| |
| output Q; |
| input CLKN,D,SCD,SCE,RESETB; |
| wire buf_Q, reset, intclk, mux_out; |
| |
| `ifdef functional |
| not (reset,RESETB); |
| not (intclk,CLKN); |
| U_MUX_2_1 (mux_out,D,SCD,SCE); |
| U_DF_P_R #1 ( buf_Q , mux_out , intclk , reset ) ; |
| `else |
| reg notifier; |
| wire COND0, COND1, COND2, COND3 ; |
| wire D_delayed, SCD_delayed, SCE_delayed, RESETB_delayed , CLKN_delayed ; |
| not (reset,RESETB_delayed); |
| not (intclk,CLKN_delayed); |
| U_MUX_2_1 (mux_out,D_delayed,SCD_delayed,SCE_delayed); |
| U_DF_P_R_NO #0.001 ( buf_Q , mux_out , intclk , reset , notifier ) ; |
| |
| assign COND0 =(RESETB_delayed === 1'b1); |
| assign COND1 = ((SCE_delayed === 1'b0)&COND0); |
| assign COND2 = ((SCE_delayed === 1'b1)&COND0); |
| assign COND3 = ((D_delayed !== SCD_delayed)&COND0); |
| specify |
| (negedge RESETB => (Q +: RESETB ) ) = 0:0:0; // delay is tris |
| (negedge CLKN => (Q : CLKN ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| $width (posedge CLKN &&& (RESETB===1'b1) , 0:0:0, 0, notifier); |
| $width (negedge CLKN &&& (RESETB===1'b1) , 0:0:0, 0, notifier); |
| $width (negedge RESETB , 0.5, 0, notifier); |
| $recrem ( posedge RESETB , negedge CLKN , 0:0:0, 0:0:0, notifier , , , RESETB_delayed , CLKN_delayed ) ; |
| $recovery ( posedge RESETB , negedge CLKN , 0:0:0, 0:0:0, notifier , , , RESETB_delayed , CLKN_delayed ) ; |
| $hold ( negedge CLKN , posedge RESETB , 0:0:0, notifier ) ; |
| $setuphold ( negedge CLKN , posedge D , 0:0:0, 0:0:0, notifier , , COND1 , CLKN_delayed , D_delayed ) ; |
| $setuphold ( negedge CLKN , negedge D , 0:0:0, 0:0:0, notifier , , COND1 , CLKN_delayed , D_delayed ) ; |
| $setuphold ( negedge CLKN , posedge SCD , 0:0:0, 0:0:0, notifier , , COND2 , CLKN_delayed , SCD_delayed ) ; |
| $setuphold ( negedge CLKN , negedge SCD , 0:0:0, 0:0:0, notifier , , COND2 , CLKN_delayed , SCD_delayed ) ; |
| $setuphold ( negedge CLKN , posedge SCE , 0:0:0, 0:0:0, notifier , , COND3 , CLKN_delayed , SCE_delayed ) ; |
| $setuphold ( negedge CLKN , negedge SCE , 0:0:0, 0:0:0, notifier , , COND3 , CLKN_delayed , SCE_delayed ) ; |
| endspecify |
| `endif |
| |
| buf (Q,buf_Q); |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_sdfrtp_1 (RESETB,CLK,D,Q,SCD,SCE); |
| |
| output Q; |
| input CLK,D,SCD,SCE,RESETB; |
| wire buf_Q, reset, mux_out; |
| |
| `ifdef functional |
| not (reset,RESETB); |
| U_MUX_2_1 (mux_out,D,SCD,SCE); |
| U_DF_P_R #1 ( buf_Q , mux_out , CLK , reset ) ; |
| `else |
| reg notifier; |
| wire COND0, COND1, COND2, COND3 ; |
| wire D_delayed, SCD_delayed, SCE_delayed, RESETB_delayed , CLK_delayed ; |
| not (reset,RESETB_delayed); |
| U_MUX_2_1 (mux_out,D_delayed,SCD_delayed,SCE_delayed); |
| U_DF_P_R_NO #0.001 ( buf_Q , mux_out , CLK_delayed , reset , notifier ) ; |
| |
| assign COND0 = (RESETB_delayed === 1'b1); |
| assign COND1 = ((SCE_delayed === 1'b0)&COND0); |
| assign COND2 = ((SCE_delayed === 1'b1)&COND0); |
| assign COND3 = ((D_delayed !== SCD_delayed)&COND0); |
| specify |
| (negedge RESETB => (Q +: RESETB ) ) = 0:0:0; // delay is tris |
| (posedge CLK => (Q : CLK ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| $width (posedge CLK &&& (RESETB===1'b1) , 0:0:0, 0, notifier); |
| $width (negedge CLK &&& (RESETB===1'b1) , 0:0:0, 0, notifier); |
| $width (negedge RESETB , 0.5, 0, notifier); |
| $recrem ( posedge RESETB , posedge CLK , 0:0:0, 0:0:0, notifier , , , RESETB_delayed , CLK_delayed ) ; |
| $recovery ( posedge RESETB , posedge CLK , 0:0:0, 0:0:0, notifier , , , RESETB_delayed , CLK_delayed ) ; |
| $hold ( posedge CLK , posedge RESETB , 0:0:0, notifier ) ; |
| $setuphold ( posedge CLK , posedge D , 0:0:0, 0:0:0, notifier , , COND1 , CLK_delayed , D_delayed ) ; |
| $setuphold ( posedge CLK , negedge D , 0:0:0, 0:0:0, notifier , , COND1 , CLK_delayed , D_delayed ) ; |
| $setuphold ( posedge CLK , posedge SCD , 0:0:0, 0:0:0, notifier , , COND2 , CLK_delayed , SCD_delayed ) ; |
| $setuphold ( posedge CLK , negedge SCD , 0:0:0, 0:0:0, notifier , , COND2 , CLK_delayed , SCD_delayed ) ; |
| $setuphold ( posedge CLK , posedge SCE , 0:0:0, 0:0:0, notifier , , COND3 , CLK_delayed , SCE_delayed ) ; |
| $setuphold ( posedge CLK , negedge SCE , 0:0:0, 0:0:0, notifier , , COND3 , CLK_delayed , SCE_delayed ) ; |
| endspecify |
| `endif |
| |
| buf (Q,buf_Q); |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_sdfrtp_2 (RESETB,CLK,D,Q,SCD,SCE); |
| |
| output Q; |
| input CLK,D,SCD,SCE,RESETB; |
| wire buf_Q, reset, mux_out; |
| |
| `ifdef functional |
| not (reset,RESETB); |
| U_MUX_2_1 (mux_out,D,SCD,SCE); |
| U_DF_P_R #1 ( buf_Q , mux_out , CLK , reset ) ; |
| `else |
| reg notifier; |
| wire COND0, COND1, COND2, COND3 ; |
| wire D_delayed, SCD_delayed, SCE_delayed, RESETB_delayed , CLK_delayed ; |
| not (reset,RESETB_delayed); |
| U_MUX_2_1 (mux_out,D_delayed,SCD_delayed,SCE_delayed); |
| U_DF_P_R_NO #0.001 ( buf_Q , mux_out , CLK_delayed , reset , notifier ) ; |
| |
| assign COND0 = (RESETB_delayed === 1'b1); |
| assign COND1 = ((SCE_delayed === 1'b0)&COND0); |
| assign COND2 = ((SCE_delayed === 1'b1)&COND0); |
| assign COND3 = ((D_delayed !== SCD_delayed)&COND0); |
| specify |
| (negedge RESETB => (Q +: RESETB ) ) = 0:0:0; // delay is tris |
| (posedge CLK => (Q : CLK ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| $width (posedge CLK &&& (RESETB===1'b1) , 0:0:0, 0, notifier); |
| $width (negedge CLK &&& (RESETB===1'b1) , 0:0:0, 0, notifier); |
| $width (negedge RESETB , 0.5, 0, notifier); |
| $recrem ( posedge RESETB , posedge CLK , 0:0:0, 0:0:0, notifier , , , RESETB_delayed , CLK_delayed ) ; |
| $recovery ( posedge RESETB , posedge CLK , 0:0:0, 0:0:0, notifier , , , RESETB_delayed , CLK_delayed ) ; |
| $hold ( posedge CLK , posedge RESETB , 0:0:0, notifier ) ; |
| $setuphold ( posedge CLK , posedge D , 0:0:0, 0:0:0, notifier , , COND1 , CLK_delayed , D_delayed ) ; |
| $setuphold ( posedge CLK , negedge D , 0:0:0, 0:0:0, notifier , , COND1 , CLK_delayed , D_delayed ) ; |
| $setuphold ( posedge CLK , posedge SCD , 0:0:0, 0:0:0, notifier , , COND2 , CLK_delayed , SCD_delayed ) ; |
| $setuphold ( posedge CLK , negedge SCD , 0:0:0, 0:0:0, notifier , , COND2 , CLK_delayed , SCD_delayed ) ; |
| $setuphold ( posedge CLK , posedge SCE , 0:0:0, 0:0:0, notifier , , COND3 , CLK_delayed , SCE_delayed ) ; |
| $setuphold ( posedge CLK , negedge SCE , 0:0:0, 0:0:0, notifier , , COND3 , CLK_delayed , SCE_delayed ) ; |
| endspecify |
| `endif |
| |
| buf (Q,buf_Q); |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_sdfrtp_4 (RESETB,CLK,D,Q,SCD,SCE); |
| |
| output Q; |
| input CLK,D,SCD,SCE,RESETB; |
| wire buf_Q, reset, mux_out; |
| |
| `ifdef functional |
| not (reset,RESETB); |
| U_MUX_2_1 (mux_out,D,SCD,SCE); |
| U_DF_P_R #1 ( buf_Q , mux_out , CLK , reset ) ; |
| `else |
| reg notifier; |
| wire COND0, COND1, COND2, COND3 ; |
| wire D_delayed, SCD_delayed, SCE_delayed, RESETB_delayed , CLK_delayed ; |
| not (reset,RESETB_delayed); |
| U_MUX_2_1 (mux_out,D_delayed,SCD_delayed,SCE_delayed); |
| U_DF_P_R_NO #0.001 ( buf_Q , mux_out , CLK_delayed , reset , notifier ) ; |
| |
| assign COND0 = (RESETB_delayed === 1'b1); |
| assign COND1 = ((SCE_delayed === 1'b0)&COND0); |
| assign COND2 = ((SCE_delayed === 1'b1)&COND0); |
| assign COND3 = ((D_delayed !== SCD_delayed)&COND0); |
| specify |
| (negedge RESETB => (Q +: RESETB ) ) = 0:0:0; // delay is tris |
| (posedge CLK => (Q : CLK ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| $width (posedge CLK &&& (RESETB===1'b1) , 0:0:0, 0, notifier); |
| $width (negedge CLK &&& (RESETB===1'b1) , 0:0:0, 0, notifier); |
| $width (negedge RESETB , 0.5, 0, notifier); |
| $recrem ( posedge RESETB , posedge CLK , 0:0:0, 0:0:0, notifier , , , RESETB_delayed , CLK_delayed ) ; |
| $recovery ( posedge RESETB , posedge CLK , 0:0:0, 0:0:0, notifier , , , RESETB_delayed , CLK_delayed ) ; |
| $hold ( posedge CLK , posedge RESETB , 0:0:0, notifier ) ; |
| $setuphold ( posedge CLK , posedge D , 0:0:0, 0:0:0, notifier , , COND1 , CLK_delayed , D_delayed ) ; |
| $setuphold ( posedge CLK , negedge D , 0:0:0, 0:0:0, notifier , , COND1 , CLK_delayed , D_delayed ) ; |
| $setuphold ( posedge CLK , posedge SCD , 0:0:0, 0:0:0, notifier , , COND2 , CLK_delayed , SCD_delayed ) ; |
| $setuphold ( posedge CLK , negedge SCD , 0:0:0, 0:0:0, notifier , , COND2 , CLK_delayed , SCD_delayed ) ; |
| $setuphold ( posedge CLK , posedge SCE , 0:0:0, 0:0:0, notifier , , COND3 , CLK_delayed , SCE_delayed ) ; |
| $setuphold ( posedge CLK , negedge SCE , 0:0:0, 0:0:0, notifier , , COND3 , CLK_delayed , SCE_delayed ) ; |
| endspecify |
| `endif |
| |
| buf (Q,buf_Q); |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_sdfsbp_1 (CLK,D,Q,QN,SCD,SCE,SETB); |
| |
| output Q,QN; |
| input CLK,D,SCD,SCE,SETB; |
| wire buf_Q, set, mux_out; |
| |
| `ifdef functional |
| not (set,SETB); |
| U_MUX_2_1 (mux_out,D,SCD,SCE); |
| U_DF_P_S #1 ( buf_Q , mux_out , CLK , set ) ; |
| `else |
| reg notifier; |
| wire COND0, COND1, COND2, COND3 ; |
| wire D_delayed, SCD_delayed, SCE_delayed , SETB_delayed , CLK_delayed ; |
| not (set,SETB_delayed); |
| U_MUX_2_1 (mux_out,D_delayed,SCD_delayed,SCE_delayed); |
| U_DF_P_S_NO #0.001 ( buf_Q , mux_out , CLK_delayed , set , notifier ) ; |
| |
| assign COND0 = (SETB_delayed === 1'b1); |
| assign COND1 = ((SCE_delayed === 1'b0)&COND0); |
| assign COND2 = ((SCE_delayed === 1'b1)&COND0); |
| assign COND3 = ((D_delayed !== SCD_delayed)&COND0); |
| specify |
| (negedge SETB => (Q -: SETB ) ) = 0:0:0; // delay is tris |
| (negedge SETB => (QN +: SETB ) ) = 0:0:0; // delay is tris |
| (posedge CLK => (Q : CLK ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| (posedge CLK => (QN : CLK ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| $width (posedge CLK &&& (SETB===1'b1) , 0:0:0, 0, notifier); |
| $width (negedge CLK &&& (SETB===1'b1) , 0:0:0, 0, notifier); |
| $width (negedge SETB , 0.5, 0, notifier); |
| $recrem ( posedge SETB , posedge CLK , 0:0:0, 0:0:0, notifier , , , SETB_delayed , CLK_delayed ) ; |
| $recovery ( posedge SETB , posedge CLK , 0:0:0, 0:0:0, notifier , , , SETB_delayed , CLK_delayed ) ; |
| $hold ( posedge CLK , posedge SETB , 0:0:0, notifier ) ; |
| $setuphold ( posedge CLK , posedge D , 0:0:0, 0:0:0, notifier , , COND1 , CLK_delayed , D_delayed ) ; |
| $setuphold ( posedge CLK , negedge D , 0:0:0, 0:0:0, notifier , , COND1 , CLK_delayed , D_delayed ) ; |
| $setuphold ( posedge CLK , posedge SCD , 0:0:0, 0:0:0, notifier , , COND2 , CLK_delayed , SCD_delayed ) ; |
| $setuphold ( posedge CLK , negedge SCD , 0:0:0, 0:0:0, notifier , , COND2 , CLK_delayed , SCD_delayed ) ; |
| $setuphold ( posedge CLK , posedge SCE , 0:0:0, 0:0:0, notifier , , COND3 , CLK_delayed , SCE_delayed ) ; |
| $setuphold ( posedge CLK , negedge SCE , 0:0:0, 0:0:0, notifier , , COND3 , CLK_delayed , SCE_delayed ) ; |
| endspecify |
| `endif |
| |
| buf (Q,buf_Q); |
| not (QN,buf_Q); |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_sdfsbp_2 (CLK,D,Q,QN,SCD,SCE,SETB); |
| |
| output Q,QN; |
| input CLK,D,SCD,SCE,SETB; |
| wire buf_Q, set, mux_out; |
| |
| `ifdef functional |
| not (set,SETB); |
| U_MUX_2_1 (mux_out,D,SCD,SCE); |
| U_DF_P_S #1 ( buf_Q , mux_out , CLK , set ) ; |
| `else |
| reg notifier; |
| wire COND0, COND1, COND2, COND3 ; |
| wire D_delayed, SCD_delayed, SCE_delayed , SETB_delayed , CLK_delayed ; |
| not (set,SETB_delayed); |
| U_MUX_2_1 (mux_out,D_delayed,SCD_delayed,SCE_delayed); |
| U_DF_P_S_NO #0.001 ( buf_Q , mux_out , CLK_delayed , set , notifier ) ; |
| |
| assign COND0 = (SETB_delayed === 1'b1); |
| assign COND1 = ((SCE_delayed === 1'b0)&COND0); |
| assign COND2 = ((SCE_delayed === 1'b1)&COND0); |
| assign COND3 = ((D_delayed !== SCD_delayed)&COND0); |
| specify |
| (negedge SETB => (Q -: SETB ) ) = 0:0:0; // delay is tris |
| (negedge SETB => (QN +: SETB ) ) = 0:0:0; // delay is tris |
| (posedge CLK => (Q : CLK ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| (posedge CLK => (QN : CLK ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| $width (posedge CLK &&& (SETB===1'b1) , 0:0:0, 0, notifier); |
| $width (negedge CLK &&& (SETB===1'b1) , 0:0:0, 0, notifier); |
| $width (negedge SETB , 0.5, 0, notifier); |
| $recrem ( posedge SETB , posedge CLK , 0:0:0, 0:0:0, notifier , , , SETB_delayed , CLK_delayed ) ; |
| $recovery ( posedge SETB , posedge CLK , 0:0:0, 0:0:0, notifier , , , SETB_delayed , CLK_delayed ) ; |
| $hold ( posedge CLK , posedge SETB , 0:0:0, notifier ) ; |
| $setuphold ( posedge CLK , posedge D , 0:0:0, 0:0:0, notifier , , COND1 , CLK_delayed , D_delayed ) ; |
| $setuphold ( posedge CLK , negedge D , 0:0:0, 0:0:0, notifier , , COND1 , CLK_delayed , D_delayed ) ; |
| $setuphold ( posedge CLK , posedge SCD , 0:0:0, 0:0:0, notifier , , COND2 , CLK_delayed , SCD_delayed ) ; |
| $setuphold ( posedge CLK , negedge SCD , 0:0:0, 0:0:0, notifier , , COND2 , CLK_delayed , SCD_delayed ) ; |
| $setuphold ( posedge CLK , posedge SCE , 0:0:0, 0:0:0, notifier , , COND3 , CLK_delayed , SCE_delayed ) ; |
| $setuphold ( posedge CLK , negedge SCE , 0:0:0, 0:0:0, notifier , , COND3 , CLK_delayed , SCE_delayed ) ; |
| endspecify |
| `endif |
| |
| buf (Q,buf_Q); |
| not (QN,buf_Q); |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_sdfstp_1 (CLK,D,Q,SCD,SCE,SETB); |
| |
| output Q; |
| input CLK,D,SCD,SCE,SETB; |
| wire buf_Q, set, mux_out; |
| |
| `ifdef functional |
| not (set,SETB); |
| U_MUX_2_1 (mux_out,D,SCD,SCE); |
| U_DF_P_S #1 ( buf_Q , mux_out , CLK , set ) ; |
| `else |
| reg notifier; |
| wire COND0, COND1, COND2, COND3 ; |
| wire D_delayed, SCD_delayed, SCE_delayed, SETB_delayed , CLK_delayed ; |
| not (set,SETB_delayed); |
| U_MUX_2_1 (mux_out,D_delayed,SCD_delayed,SCE_delayed); |
| U_DF_P_S_NO #0.001 ( buf_Q , mux_out , CLK_delayed , set , notifier ) ; |
| |
| assign COND0 = (SETB_delayed === 1'b1); |
| assign COND1 = ((SCE_delayed === 1'b0)&COND0); |
| assign COND2 = ((SCE_delayed === 1'b1)&COND0); |
| assign COND3 = ((D_delayed !== SCD_delayed)&COND0); |
| specify |
| (negedge SETB => (Q -: SETB ) ) = 0:0:0; // delay is tris |
| (posedge CLK => (Q : CLK ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| $width (posedge CLK &&& (SETB===1'b1) , 0:0:0, 0, notifier); |
| $width (negedge CLK &&& (SETB===1'b1) , 0:0:0, 0, notifier); |
| $width (negedge SETB , 0.5, 0, notifier); |
| $recrem ( posedge SETB , posedge CLK , 0:0:0, 0:0:0, notifier , , , SETB_delayed , CLK_delayed ) ; |
| $recovery ( posedge SETB , posedge CLK , 0:0:0, 0:0:0, notifier , , , SETB_delayed , CLK_delayed ) ; |
| $hold ( posedge CLK , posedge SETB , 0:0:0, notifier ) ; |
| $setuphold ( posedge CLK , posedge D , 0:0:0, 0:0:0, notifier , , COND1 , CLK_delayed , D_delayed ) ; |
| $setuphold ( posedge CLK , negedge D , 0:0:0, 0:0:0, notifier , , COND1 , CLK_delayed , D_delayed ) ; |
| $setuphold ( posedge CLK , posedge SCD , 0:0:0, 0:0:0, notifier , , COND2 , CLK_delayed , SCD_delayed ) ; |
| $setuphold ( posedge CLK , negedge SCD , 0:0:0, 0:0:0, notifier , , COND2 , CLK_delayed , SCD_delayed ) ; |
| $setuphold ( posedge CLK , posedge SCE , 0:0:0, 0:0:0, notifier , , COND3 , CLK_delayed , SCE_delayed ) ; |
| $setuphold ( posedge CLK , negedge SCE , 0:0:0, 0:0:0, notifier , , COND3 , CLK_delayed , SCE_delayed ) ; |
| endspecify |
| `endif |
| |
| buf (Q,buf_Q); |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_sdfstp_2 (CLK,D,Q,SCD,SCE,SETB); |
| |
| output Q; |
| input CLK,D,SCD,SCE,SETB; |
| wire buf_Q, set, mux_out; |
| |
| `ifdef functional |
| not (set,SETB); |
| U_MUX_2_1 (mux_out,D,SCD,SCE); |
| U_DF_P_S #1 ( buf_Q , mux_out , CLK , set ) ; |
| `else |
| reg notifier; |
| wire COND0, COND1, COND2, COND3 ; |
| wire D_delayed, SCD_delayed, SCE_delayed, SETB_delayed , CLK_delayed ; |
| not (set,SETB_delayed); |
| U_MUX_2_1 (mux_out,D_delayed,SCD_delayed,SCE_delayed); |
| U_DF_P_S_NO #0.001 ( buf_Q , mux_out , CLK_delayed , set , notifier ) ; |
| |
| assign COND0 = (SETB_delayed === 1'b1); |
| assign COND1 = ((SCE_delayed === 1'b0)&COND0); |
| assign COND2 = ((SCE_delayed === 1'b1)&COND0); |
| assign COND3 = ((D_delayed !== SCD_delayed)&COND0); |
| specify |
| (negedge SETB => (Q -: SETB ) ) = 0:0:0; // delay is tris |
| (posedge CLK => (Q : CLK ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| $width (posedge CLK &&& (SETB===1'b1) , 0:0:0, 0, notifier); |
| $width (negedge CLK &&& (SETB===1'b1) , 0:0:0, 0, notifier); |
| $width (negedge SETB , 0.5, 0, notifier); |
| $recrem ( posedge SETB , posedge CLK , 0:0:0, 0:0:0, notifier , , , SETB_delayed , CLK_delayed ) ; |
| $recovery ( posedge SETB , posedge CLK , 0:0:0, 0:0:0, notifier , , , SETB_delayed , CLK_delayed ) ; |
| $hold ( posedge CLK , posedge SETB , 0:0:0, notifier ) ; |
| $setuphold ( posedge CLK , posedge D , 0:0:0, 0:0:0, notifier , , COND1 , CLK_delayed , D_delayed ) ; |
| $setuphold ( posedge CLK , negedge D , 0:0:0, 0:0:0, notifier , , COND1 , CLK_delayed , D_delayed ) ; |
| $setuphold ( posedge CLK , posedge SCD , 0:0:0, 0:0:0, notifier , , COND2 , CLK_delayed , SCD_delayed ) ; |
| $setuphold ( posedge CLK , negedge SCD , 0:0:0, 0:0:0, notifier , , COND2 , CLK_delayed , SCD_delayed ) ; |
| $setuphold ( posedge CLK , posedge SCE , 0:0:0, 0:0:0, notifier , , COND3 , CLK_delayed , SCE_delayed ) ; |
| $setuphold ( posedge CLK , negedge SCE , 0:0:0, 0:0:0, notifier , , COND3 , CLK_delayed , SCE_delayed ) ; |
| endspecify |
| `endif |
| |
| buf (Q,buf_Q); |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_sdfstp_4 (CLK,D,Q,SCD,SCE,SETB); |
| |
| output Q; |
| input CLK,D,SCD,SCE,SETB; |
| wire buf_Q, set, mux_out; |
| |
| `ifdef functional |
| not (set,SETB); |
| U_MUX_2_1 (mux_out,D,SCD,SCE); |
| U_DF_P_S #1 ( buf_Q , mux_out , CLK , set ) ; |
| `else |
| reg notifier; |
| wire COND0, COND1, COND2, COND3 ; |
| wire D_delayed, SCD_delayed, SCE_delayed, SETB_delayed , CLK_delayed ; |
| not (set,SETB_delayed); |
| U_MUX_2_1 (mux_out,D_delayed,SCD_delayed,SCE_delayed); |
| U_DF_P_S_NO #0.001 ( buf_Q , mux_out , CLK_delayed , set , notifier ) ; |
| |
| assign COND0 = (SETB_delayed === 1'b1); |
| assign COND1 = ((SCE_delayed === 1'b0)&COND0); |
| assign COND2 = ((SCE_delayed === 1'b1)&COND0); |
| assign COND3 = ((D_delayed !== SCD_delayed)&COND0); |
| specify |
| (negedge SETB => (Q -: SETB ) ) = 0:0:0; // delay is tris |
| (posedge CLK => (Q : CLK ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| $width (posedge CLK &&& (SETB===1'b1) , 0:0:0, 0, notifier); |
| $width (negedge CLK &&& (SETB===1'b1) , 0:0:0, 0, notifier); |
| $width (negedge SETB , 0.5, 0, notifier); |
| $recrem ( posedge SETB , posedge CLK , 0:0:0, 0:0:0, notifier , , , SETB_delayed , CLK_delayed ) ; |
| $recovery ( posedge SETB , posedge CLK , 0:0:0, 0:0:0, notifier , , , SETB_delayed , CLK_delayed ) ; |
| $hold ( posedge CLK , posedge SETB , 0:0:0, notifier ) ; |
| $setuphold ( posedge CLK , posedge D , 0:0:0, 0:0:0, notifier , , COND1 , CLK_delayed , D_delayed ) ; |
| $setuphold ( posedge CLK , negedge D , 0:0:0, 0:0:0, notifier , , COND1 , CLK_delayed , D_delayed ) ; |
| $setuphold ( posedge CLK , posedge SCD , 0:0:0, 0:0:0, notifier , , COND2 , CLK_delayed , SCD_delayed ) ; |
| $setuphold ( posedge CLK , negedge SCD , 0:0:0, 0:0:0, notifier , , COND2 , CLK_delayed , SCD_delayed ) ; |
| $setuphold ( posedge CLK , posedge SCE , 0:0:0, 0:0:0, notifier , , COND3 , CLK_delayed , SCE_delayed ) ; |
| $setuphold ( posedge CLK , negedge SCE , 0:0:0, 0:0:0, notifier , , COND3 , CLK_delayed , SCE_delayed ) ; |
| endspecify |
| `endif |
| |
| buf (Q,buf_Q); |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_sdfxbp_1 (CLK,D,Q,QN,SCD,SCE); |
| |
| output Q,QN; |
| input CLK,D,SCD,SCE; |
| wire buf_Q, mux_out; |
| |
| `ifdef functional |
| U_MUX_2_1 (mux_out,D,SCD,SCE); |
| U_DF_P #1 ( buf_Q , mux_out , CLK ) ; |
| `else |
| reg notifier; |
| wire COND1, COND2, COND3 ; |
| wire D_delayed, SCD_delayed, SCE_delayed, CLK_delayed ; |
| U_MUX_2_1 (mux_out,D_delayed,SCD_delayed,SCE_delayed); |
| U_DF_P_NO #0.001 ( buf_Q , mux_out , CLK_delayed , notifier ) ; |
| |
| assign COND1 = (SCE_delayed === 1'b0); |
| assign COND2 = (SCE_delayed === 1'b1); |
| assign COND3 = (D_delayed !== SCD_delayed); |
| specify |
| (posedge CLK => (Q : CLK ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| (posedge CLK => (QN : CLK ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| $width (posedge CLK , 0:0:0, 0, notifier); |
| $width (negedge CLK , 0:0:0, 0, notifier); |
| $setuphold ( posedge CLK , posedge D , 0:0:0, 0:0:0, notifier , , COND1 , CLK_delayed , D_delayed ) ; |
| $setuphold ( posedge CLK , negedge D , 0:0:0, 0:0:0, notifier , , COND1 , CLK_delayed , D_delayed ) ; |
| $setuphold ( posedge CLK , posedge SCD , 0:0:0, 0:0:0, notifier , , COND2 , CLK_delayed , SCD_delayed ) ; |
| $setuphold ( posedge CLK , negedge SCD , 0:0:0, 0:0:0, notifier , , COND2 , CLK_delayed , SCD_delayed ) ; |
| $setuphold ( posedge CLK , posedge SCE , 0:0:0, 0:0:0, notifier , , COND3 , CLK_delayed , SCE_delayed ) ; |
| $setuphold ( posedge CLK , negedge SCE , 0:0:0, 0:0:0, notifier , , COND3 , CLK_delayed , SCE_delayed ) ; |
| endspecify |
| `endif |
| |
| buf (Q,buf_Q); |
| not (QN,buf_Q); |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_sdfxbp_2 (CLK,D,Q,QN,SCD,SCE); |
| |
| output Q,QN; |
| input CLK,D,SCD,SCE; |
| wire buf_Q, mux_out; |
| |
| `ifdef functional |
| U_MUX_2_1 (mux_out,D,SCD,SCE); |
| U_DF_P #1 ( buf_Q , mux_out , CLK ) ; |
| `else |
| reg notifier; |
| wire COND1, COND2, COND3 ; |
| wire D_delayed, SCD_delayed, SCE_delayed, CLK_delayed ; |
| U_MUX_2_1 (mux_out,D_delayed,SCD_delayed,SCE_delayed); |
| U_DF_P_NO #0.001 ( buf_Q , mux_out , CLK_delayed , notifier ) ; |
| |
| assign COND1 = (SCE_delayed === 1'b0); |
| assign COND2 = (SCE_delayed === 1'b1); |
| assign COND3 = (D_delayed !== SCD_delayed); |
| specify |
| (posedge CLK => (Q : CLK ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| (posedge CLK => (QN : CLK ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| $width (posedge CLK , 0:0:0, 0, notifier); |
| $width (negedge CLK , 0:0:0, 0, notifier); |
| $setuphold ( posedge CLK , posedge D , 0:0:0, 0:0:0, notifier , , COND1 , CLK_delayed , D_delayed ) ; |
| $setuphold ( posedge CLK , negedge D , 0:0:0, 0:0:0, notifier , , COND1 , CLK_delayed , D_delayed ) ; |
| $setuphold ( posedge CLK , posedge SCD , 0:0:0, 0:0:0, notifier , , COND2 , CLK_delayed , SCD_delayed ) ; |
| $setuphold ( posedge CLK , negedge SCD , 0:0:0, 0:0:0, notifier , , COND2 , CLK_delayed , SCD_delayed ) ; |
| $setuphold ( posedge CLK , posedge SCE , 0:0:0, 0:0:0, notifier , , COND3 , CLK_delayed , SCE_delayed ) ; |
| $setuphold ( posedge CLK , negedge SCE , 0:0:0, 0:0:0, notifier , , COND3 , CLK_delayed , SCE_delayed ) ; |
| endspecify |
| `endif |
| |
| buf (Q,buf_Q); |
| not (QN,buf_Q); |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_sdfxtp_1 (CLK,D,Q,SCD,SCE); |
| |
| output Q; |
| input CLK,D,SCD,SCE; |
| wire buf_Q, mux_out; |
| |
| `ifdef functional |
| U_MUX_2_1 (mux_out,D,SCD,SCE); |
| U_DF_P #1 ( buf_Q , mux_out , CLK ) ; |
| `else |
| reg notifier; |
| wire COND1, COND2, COND3 ; |
| wire D_delayed, SCD_delayed, SCE_delayed, CLK_delayed ; |
| U_MUX_2_1 (mux_out,D_delayed,SCD_delayed,SCE_delayed); |
| U_DF_P_NO #0.001 ( buf_Q , mux_out , CLK_delayed , notifier ) ; |
| |
| assign COND1 = (SCE_delayed === 1'b0); |
| assign COND2 = (SCE_delayed === 1'b1); |
| assign COND3 = (D_delayed !== SCD_delayed); |
| specify |
| (posedge CLK => (Q : CLK ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| $width (posedge CLK , 0:0:0, 0, notifier); |
| $width (negedge CLK , 0:0:0, 0, notifier); |
| $setuphold ( posedge CLK , posedge D , 0:0:0, 0:0:0, notifier , , COND1 , CLK_delayed , D_delayed ) ; |
| $setuphold ( posedge CLK , negedge D , 0:0:0, 0:0:0, notifier , , COND1 , CLK_delayed , D_delayed ) ; |
| $setuphold ( posedge CLK , posedge SCD , 0:0:0, 0:0:0, notifier , , COND2 , CLK_delayed , SCD_delayed ) ; |
| $setuphold ( posedge CLK , negedge SCD , 0:0:0, 0:0:0, notifier , , COND2 , CLK_delayed , SCD_delayed ) ; |
| $setuphold ( posedge CLK , posedge SCE , 0:0:0, 0:0:0, notifier , , COND3 , CLK_delayed , SCE_delayed ) ; |
| $setuphold ( posedge CLK , negedge SCE , 0:0:0, 0:0:0, notifier , , COND3 , CLK_delayed , SCE_delayed ) ; |
| endspecify |
| `endif |
| |
| buf (Q,buf_Q); |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_sdfxtp_2 (CLK,D,Q,SCD,SCE); |
| |
| output Q; |
| input CLK,D,SCD,SCE; |
| wire buf_Q, mux_out; |
| |
| `ifdef functional |
| U_MUX_2_1 (mux_out,D,SCD,SCE); |
| U_DF_P #1 ( buf_Q , mux_out , CLK ) ; |
| `else |
| reg notifier; |
| wire COND1, COND2, COND3 ; |
| wire D_delayed, SCD_delayed, SCE_delayed, CLK_delayed ; |
| U_MUX_2_1 (mux_out,D_delayed,SCD_delayed,SCE_delayed); |
| U_DF_P_NO #0.001 ( buf_Q , mux_out , CLK_delayed , notifier ) ; |
| |
| assign COND1 = (SCE_delayed === 1'b0); |
| assign COND2 = (SCE_delayed === 1'b1); |
| assign COND3 = (D_delayed !== SCD_delayed); |
| specify |
| (posedge CLK => (Q : CLK ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| $width (posedge CLK , 0:0:0, 0, notifier); |
| $width (negedge CLK , 0:0:0, 0, notifier); |
| $setuphold ( posedge CLK , posedge D , 0:0:0, 0:0:0, notifier , , COND1 , CLK_delayed , D_delayed ) ; |
| $setuphold ( posedge CLK , negedge D , 0:0:0, 0:0:0, notifier , , COND1 , CLK_delayed , D_delayed ) ; |
| $setuphold ( posedge CLK , posedge SCD , 0:0:0, 0:0:0, notifier , , COND2 , CLK_delayed , SCD_delayed ) ; |
| $setuphold ( posedge CLK , negedge SCD , 0:0:0, 0:0:0, notifier , , COND2 , CLK_delayed , SCD_delayed ) ; |
| $setuphold ( posedge CLK , posedge SCE , 0:0:0, 0:0:0, notifier , , COND3 , CLK_delayed , SCE_delayed ) ; |
| $setuphold ( posedge CLK , negedge SCE , 0:0:0, 0:0:0, notifier , , COND3 , CLK_delayed , SCE_delayed ) ; |
| endspecify |
| `endif |
| |
| buf (Q,buf_Q); |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_sdfxtp_4 (CLK,D,Q,SCD,SCE); |
| |
| output Q; |
| input CLK,D,SCD,SCE; |
| wire buf_Q, mux_out; |
| |
| `ifdef functional |
| U_MUX_2_1 (mux_out,D,SCD,SCE); |
| U_DF_P #1 ( buf_Q , mux_out , CLK ) ; |
| `else |
| reg notifier; |
| wire COND1, COND2, COND3 ; |
| wire D_delayed, SCD_delayed, SCE_delayed, CLK_delayed ; |
| U_MUX_2_1 (mux_out,D_delayed,SCD_delayed,SCE_delayed); |
| U_DF_P_NO #0.001 ( buf_Q , mux_out , CLK_delayed , notifier ) ; |
| |
| assign COND1 = (SCE_delayed === 1'b0); |
| assign COND2 = (SCE_delayed === 1'b1); |
| assign COND3 = (D_delayed !== SCD_delayed); |
| specify |
| (posedge CLK => (Q : CLK ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| $width (posedge CLK , 0:0:0, 0, notifier); |
| $width (negedge CLK , 0:0:0, 0, notifier); |
| $setuphold ( posedge CLK , posedge D , 0:0:0, 0:0:0, notifier , , COND1 , CLK_delayed , D_delayed ) ; |
| $setuphold ( posedge CLK , negedge D , 0:0:0, 0:0:0, notifier , , COND1 , CLK_delayed , D_delayed ) ; |
| $setuphold ( posedge CLK , posedge SCD , 0:0:0, 0:0:0, notifier , , COND2 , CLK_delayed , SCD_delayed ) ; |
| $setuphold ( posedge CLK , negedge SCD , 0:0:0, 0:0:0, notifier , , COND2 , CLK_delayed , SCD_delayed ) ; |
| $setuphold ( posedge CLK , posedge SCE , 0:0:0, 0:0:0, notifier , , COND3 , CLK_delayed , SCE_delayed ) ; |
| $setuphold ( posedge CLK , negedge SCE , 0:0:0, 0:0:0, notifier , , COND3 , CLK_delayed , SCE_delayed ) ; |
| endspecify |
| `endif |
| |
| buf (Q,buf_Q); |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_sdlclkp_1 ( GCLK, GATE, CLK, SCE ); |
| output GCLK; |
| input SCE, GATE, CLK; |
| wire m0, m0n, clkn; |
| |
| `ifdef functional |
| |
| not (clkn,CLK); |
| nor (SCE_GATE,GATE,SCE); |
| U_DL_P #1 ( m0 , SCE_GATE , clkn ) ; |
| and (GCLK, m0n, CLK); |
| `else |
| wire CLK_delayed, SCE_delayed, GATE_delayed, SCE_GATE_delayed; |
| reg notifier; |
| not (clkn,CLK_delayed); |
| nor (SCE_GATE_delayed,GATE_delayed,SCE_delayed); |
| U_DL_P_NO #0.001 ( m0 , SCE_GATE_delayed , clkn , notifier ) ; |
| and (GCLK, m0n, CLK_delayed); |
| |
| specify |
| (CLK +=> GCLK) = (0:0:0,0:0:0); // delays are tris,tfall |
| $width (posedge CLK , 0:0:0, 0, notifier); |
| $width (negedge CLK , 0:0:0, 0, notifier); |
| $setuphold ( posedge CLK , posedge SCE , 0:0:0, 0:0:0, notifier , , , CLK_delayed , SCE_delayed ) ; |
| $setuphold ( posedge CLK , negedge SCE , 0:0:0, 0:0:0, notifier , , , CLK_delayed , SCE_delayed ) ; |
| $setuphold ( posedge CLK , posedge GATE , 0:0:0, 0:0:0, notifier , , , CLK_delayed , GATE_delayed ) ; |
| $setuphold ( posedge CLK , negedge GATE , 0:0:0, 0:0:0, notifier , , , CLK_delayed , GATE_delayed ) ; |
| endspecify |
| `endif |
| |
| not(m0n,m0); |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_sdlclkp_2 ( GCLK, GATE, CLK, SCE ); |
| output GCLK; |
| input SCE, GATE, CLK; |
| wire m0, m0n, clkn; |
| |
| `ifdef functional |
| |
| not (clkn,CLK); |
| nor (SCE_GATE,GATE,SCE); |
| U_DL_P #1 ( m0 , SCE_GATE , clkn ) ; |
| and (GCLK, m0n, CLK); |
| `else |
| wire CLK_delayed, SCE_delayed, GATE_delayed, SCE_GATE_delayed; |
| reg notifier; |
| not (clkn,CLK_delayed); |
| nor (SCE_GATE_delayed,GATE_delayed,SCE_delayed); |
| U_DL_P_NO #0.001 ( m0 , SCE_GATE_delayed , clkn , notifier ) ; |
| and (GCLK, m0n, CLK_delayed); |
| |
| specify |
| (CLK +=> GCLK) = (0:0:0,0:0:0); // delays are tris,tfall |
| $width (posedge CLK , 0:0:0, 0, notifier); |
| $width (negedge CLK , 0:0:0, 0, notifier); |
| $setuphold ( posedge CLK , posedge SCE , 0:0:0, 0:0:0, notifier , , , CLK_delayed , SCE_delayed ) ; |
| $setuphold ( posedge CLK , negedge SCE , 0:0:0, 0:0:0, notifier , , , CLK_delayed , SCE_delayed ) ; |
| $setuphold ( posedge CLK , posedge GATE , 0:0:0, 0:0:0, notifier , , , CLK_delayed , GATE_delayed ) ; |
| $setuphold ( posedge CLK , negedge GATE , 0:0:0, 0:0:0, notifier , , , CLK_delayed , GATE_delayed ) ; |
| endspecify |
| `endif |
| |
| not(m0n,m0); |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_sdlclkp_4 ( GCLK, GATE, CLK, SCE ); |
| output GCLK; |
| input SCE, GATE, CLK; |
| wire m0, m0n, clkn; |
| |
| `ifdef functional |
| |
| not (clkn,CLK); |
| nor (SCE_GATE,GATE,SCE); |
| U_DL_P #1 ( m0 , SCE_GATE , clkn ) ; |
| and (GCLK, m0n, CLK); |
| `else |
| wire CLK_delayed, SCE_delayed, GATE_delayed, SCE_GATE_delayed; |
| reg notifier; |
| not (clkn,CLK_delayed); |
| nor (SCE_GATE_delayed,GATE_delayed,SCE_delayed); |
| U_DL_P_NO #0.001 ( m0 , SCE_GATE_delayed , clkn , notifier ) ; |
| and (GCLK, m0n, CLK_delayed); |
| |
| specify |
| (CLK +=> GCLK) = (0:0:0,0:0:0); // delays are tris,tfall |
| $width (posedge CLK , 0:0:0, 0, notifier); |
| $width (negedge CLK , 0:0:0, 0, notifier); |
| $setuphold ( posedge CLK , posedge SCE , 0:0:0, 0:0:0, notifier , , , CLK_delayed , SCE_delayed ) ; |
| $setuphold ( posedge CLK , negedge SCE , 0:0:0, 0:0:0, notifier , , , CLK_delayed , SCE_delayed ) ; |
| $setuphold ( posedge CLK , posedge GATE , 0:0:0, 0:0:0, notifier , , , CLK_delayed , GATE_delayed ) ; |
| $setuphold ( posedge CLK , negedge GATE , 0:0:0, 0:0:0, notifier , , , CLK_delayed , GATE_delayed ) ; |
| endspecify |
| `endif |
| |
| not(m0n,m0); |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_sregrbp_1 (ASYNC,CLK,D,Q,QN,SCD,SCE); |
| |
| output Q,QN; |
| input CLK,D,SCD,SCE,ASYNC; |
| wire buf_Q, reset, mux_out; |
| |
| `ifdef functional |
| not (reset,ASYNC); |
| U_MUX_2_1 (mux_out,D,SCD,SCE); |
| U_DF_P_R #1 ( buf_Q , mux_out , CLK , reset ) ; |
| `else |
| reg notifier; |
| wire COND0, COND1, COND2, COND3 ; |
| wire D_delayed, SCD_delayed, SCE_delayed, ASYNC_delayed , CLK_delayed ; |
| not (reset,ASYNC_delayed); |
| U_MUX_2_1 (mux_out,D_delayed,SCD_delayed,SCE_delayed); |
| U_DF_P_R_NO #0.001 ( buf_Q , mux_out , CLK_delayed , reset , notifier ) ; |
| |
| assign COND0 = (ASYNC_delayed === 1'b1); |
| assign COND1 = ((SCE_delayed === 1'b0)&COND0); |
| assign COND2 = ((SCE_delayed === 1'b1)&COND0); |
| assign COND3 = ((D_delayed !== SCD_delayed)&COND0); |
| specify |
| (negedge ASYNC => (Q +: ASYNC ) ) = 0:0:0; // delay is tris |
| (negedge ASYNC => (QN -: ASYNC ) ) = 0:0:0; // delay is tris |
| (posedge CLK => (Q : CLK ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| (posedge CLK => (QN : CLK ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| $width (posedge CLK &&& (ASYNC===1'b1) , 0:0:0, 0, notifier); |
| $width (negedge CLK &&& (ASYNC===1'b1) , 0:0:0, 0, notifier); |
| $recrem ( posedge ASYNC , posedge CLK , 0:0:0, 0:0:0, notifier , , , ASYNC_delayed , CLK_delayed ) ; |
| $recovery ( posedge ASYNC , posedge CLK , 0:0:0, 0:0:0, notifier , , , ASYNC_delayed , CLK_delayed ) ; |
| $hold ( posedge CLK , posedge ASYNC , 0:0:0, notifier ) ; |
| $setuphold ( posedge CLK , posedge D , 0:0:0, 0:0:0, notifier , , COND1 , CLK_delayed , D_delayed ) ; |
| $setuphold ( posedge CLK , negedge D , 0:0:0, 0:0:0, notifier , , COND1 , CLK_delayed , D_delayed ) ; |
| $setuphold ( posedge CLK , posedge SCD , 0:0:0, 0:0:0, notifier , , COND2 , CLK_delayed , SCD_delayed ) ; |
| $setuphold ( posedge CLK , negedge SCD , 0:0:0, 0:0:0, notifier , , COND2 , CLK_delayed , SCD_delayed ) ; |
| $setuphold ( posedge CLK , posedge SCE , 0:0:0, 0:0:0, notifier , , COND3 , CLK_delayed , SCE_delayed ) ; |
| $setuphold ( posedge CLK , negedge SCE , 0:0:0, 0:0:0, notifier , , COND3 , CLK_delayed , SCE_delayed ) ; |
| endspecify |
| `endif |
| |
| buf (Q,buf_Q); |
| not (QN,buf_Q); |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_sregsbp_1 (CLK,D,Q,QN,SCD,SCE,ASYNC); |
| |
| output Q,QN; |
| input CLK,D,SCD,SCE,ASYNC; |
| wire buf_Q, set, mux_out; |
| |
| `ifdef functional |
| not (set,ASYNC); |
| U_MUX_2_1 (mux_out,D,SCD,SCE); |
| U_DF_P_S #1 ( buf_Q , mux_out , CLK , set ) ; |
| `else |
| reg notifier; |
| wire COND0, COND1, COND2, COND3 ; |
| wire D_delayed, SCD_delayed, SCE_delayed , ASYNC_delayed , CLK_delayed ; |
| not (set,ASYNC_delayed); |
| U_MUX_2_1 (mux_out,D_delayed,SCD_delayed,SCE_delayed); |
| U_DF_P_S_NO #0.001 ( buf_Q , mux_out , CLK_delayed , set , notifier ) ; |
| |
| assign COND0 = (ASYNC_delayed === 1'b1); |
| assign COND1 = ((SCE_delayed === 1'b0)&COND0); |
| assign COND2 = ((SCE_delayed === 1'b1)&COND0); |
| assign COND3 = ((D_delayed !== SCD_delayed)&COND0); |
| specify |
| (negedge ASYNC => (Q -: ASYNC ) ) = 0:0:0; // delay is tris |
| (negedge ASYNC => (QN +: ASYNC ) ) = 0:0:0; // delay is tris |
| (posedge CLK => (Q : CLK ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| (posedge CLK => (QN : CLK ) ) = (0:0:0,0:0:0); // delays are tris,tfall |
| $width (posedge CLK &&& (ASYNC===1'b1) , 0:0:0, 0, notifier); |
| $width (negedge CLK &&& (ASYNC===1'b1) , 0:0:0, 0, notifier); |
| $recrem ( posedge ASYNC , posedge CLK , 0:0:0, 0:0:0, notifier , , , ASYNC_delayed , CLK_delayed ) ; |
| $recovery ( posedge ASYNC , posedge CLK , 0:0:0, 0:0:0, notifier , , , ASYNC_delayed , CLK_delayed ) ; |
| $hold ( posedge CLK , posedge ASYNC , 0:0:0, notifier ) ; |
| $setuphold ( posedge CLK , posedge D , 0:0:0, 0:0:0, notifier , , COND1 , CLK_delayed , D_delayed ) ; |
| $setuphold ( posedge CLK , negedge D , 0:0:0, 0:0:0, notifier , , COND1 , CLK_delayed , D_delayed ) ; |
| $setuphold ( posedge CLK , posedge SCD , 0:0:0, 0:0:0, notifier , , COND2 , CLK_delayed , SCD_delayed ) ; |
| $setuphold ( posedge CLK , negedge SCD , 0:0:0, 0:0:0, notifier , , COND2 , CLK_delayed , SCD_delayed ) ; |
| $setuphold ( posedge CLK , posedge SCE , 0:0:0, 0:0:0, notifier , , COND3 , CLK_delayed , SCE_delayed ) ; |
| $setuphold ( posedge CLK , negedge SCE , 0:0:0, 0:0:0, notifier , , COND3 , CLK_delayed , SCE_delayed ) ; |
| endspecify |
| `endif |
| |
| buf (Q,buf_Q); |
| not (QN,buf_Q); |
| |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_xnor2_0 ( Y , A , B ); |
| output Y ; |
| input A , B ; |
| |
| wire Y , A , B ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((B)) (A +=> Y ) = (0:0:0,0:0:0); // delays are tris,tfall |
| if ((!B)) (A -=> Y ) = (0:0:0,0:0:0); // delays are tris,tfall |
| if ((A)) (B +=> Y ) = (0:0:0,0:0:0); // delays are tris,tfall |
| if ((!A)) (B -=> Y ) = (0:0:0,0:0:0); // delays are tris,tfall |
| endspecify |
| `endif |
| |
| xnor #0.001 ( Y , A , B ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_xnor2_1 ( Y , A , B ); |
| output Y ; |
| input A , B ; |
| |
| wire Y , A , B ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((B)) (A +=> Y ) = (0:0:0,0:0:0); // delays are tris,tfall |
| if ((!B)) (A -=> Y ) = (0:0:0,0:0:0); // delays are tris,tfall |
| if ((A)) (B +=> Y ) = (0:0:0,0:0:0); // delays are tris,tfall |
| if ((!A)) (B -=> Y ) = (0:0:0,0:0:0); // delays are tris,tfall |
| endspecify |
| `endif |
| |
| xnor #0.001 ( Y , A , B ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_xnor2_2 ( Y , A , B ); |
| output Y ; |
| input A , B ; |
| |
| wire Y , A , B ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((B)) (A +=> Y ) = (0:0:0,0:0:0); // delays are tris,tfall |
| if ((!B)) (A -=> Y ) = (0:0:0,0:0:0); // delays are tris,tfall |
| if ((A)) (B +=> Y ) = (0:0:0,0:0:0); // delays are tris,tfall |
| if ((!A)) (B -=> Y ) = (0:0:0,0:0:0); // delays are tris,tfall |
| endspecify |
| `endif |
| |
| xnor #0.001 ( Y , A , B ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_xnor2_4 ( Y , A , B ); |
| output Y ; |
| input A , B ; |
| |
| wire Y , A , B ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((B)) (A +=> Y ) = (0:0:0,0:0:0); // delays are tris,tfall |
| if ((!B)) (A -=> Y ) = (0:0:0,0:0:0); // delays are tris,tfall |
| if ((A)) (B +=> Y ) = (0:0:0,0:0:0); // delays are tris,tfall |
| if ((!A)) (B -=> Y ) = (0:0:0,0:0:0); // delays are tris,tfall |
| endspecify |
| `endif |
| |
| xnor #0.001 ( Y , A , B ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_xnor3_1 ( X , A , B , C ); |
| output X ; |
| input A , B , C ; |
| |
| wire X , A , B , C ; |
| |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((!B&!C)) (A -=> X) = (0:0:0,0:0:0); |
| if ((!B&C)) (A +=> X) = (0:0:0,0:0:0); |
| if ((B&!C)) (A +=> X) = (0:0:0,0:0:0); |
| if ((B&C)) (A -=> X) = (0:0:0,0:0:0); |
| if ((!A&!C)) (B -=> X) = (0:0:0,0:0:0); |
| if ((!A&C)) (B +=> X) = (0:0:0,0:0:0); |
| if ((A&!C)) (B +=> X) = (0:0:0,0:0:0); |
| if ((A&C)) (B -=> X) = (0:0:0,0:0:0); |
| if ((!A&!B)) (C -=> X) = (0:0:0,0:0:0); |
| if ((!A&B)) (C +=> X) = (0:0:0,0:0:0); |
| if ((A&!B)) (C +=> X) = (0:0:0,0:0:0); |
| if ((A&B)) (C -=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| xnor #0.001 ( X , A , B , C ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_xor2_0 ( X , A , B ); |
| output X ; |
| input A , B ; |
| |
| wire X , A , B ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((!B)) (A +=> X ) = (0:0:0,0:0:0); // delays are tris,tfall |
| if ((B)) (A -=> X ) = (0:0:0,0:0:0); // delays are tris,tfall |
| if ((!A)) (B +=> X ) = (0:0:0,0:0:0); // delays are tris,tfall |
| if ((A)) (B -=> X ) = (0:0:0,0:0:0); // delays are tris,tfall |
| endspecify |
| `endif |
| |
| xor #0.001 ( X , B , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_xor2_1 ( X , A , B ); |
| output X ; |
| input A , B ; |
| |
| wire X , A , B ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((!B)) (A +=> X ) = (0:0:0,0:0:0); // delays are tris,tfall |
| if ((B)) (A -=> X ) = (0:0:0,0:0:0); // delays are tris,tfall |
| if ((!A)) (B +=> X ) = (0:0:0,0:0:0); // delays are tris,tfall |
| if ((A)) (B -=> X ) = (0:0:0,0:0:0); // delays are tris,tfall |
| endspecify |
| `endif |
| |
| xor #0.001 ( X , B , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_xor2_2 ( X , A , B ); |
| output X ; |
| input A , B ; |
| |
| wire X , A , B ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((!B)) (A +=> X ) = (0:0:0,0:0:0); // delays are tris,tfall |
| if ((B)) (A -=> X ) = (0:0:0,0:0:0); // delays are tris,tfall |
| if ((!A)) (B +=> X ) = (0:0:0,0:0:0); // delays are tris,tfall |
| if ((A)) (B -=> X ) = (0:0:0,0:0:0); // delays are tris,tfall |
| endspecify |
| `endif |
| |
| xor #0.001 ( X , B , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_xor2_4 ( X , A , B ); |
| output X ; |
| input A , B ; |
| |
| wire X , A , B ; |
| |
| // modification by BNB, based on SPR13943. need to have |
| // the reg and specify gone when using a functional model. |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((!B)) (A +=> X ) = (0:0:0,0:0:0); // delays are tris,tfall |
| if ((B)) (A -=> X ) = (0:0:0,0:0:0); // delays are tris,tfall |
| if ((!A)) (B +=> X ) = (0:0:0,0:0:0); // delays are tris,tfall |
| if ((A)) (B -=> X ) = (0:0:0,0:0:0); // delays are tris,tfall |
| endspecify |
| `endif |
| |
| xor #0.001 ( X , B , A ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| `celldefine |
| `suppress_faults |
| `enable_portfaults |
| |
| `ifdef TETRAMAX |
| `define functional |
| `endif |
| |
| `ifdef functional |
| `timescale 1ns / 1ns |
| `delay_mode_distributed |
| `delay_mode_unit |
| `else |
| `timescale 1ns / 1ps |
| `delay_mode_path |
| `endif |
| |
| module hkscl5hdv1_xor3_1 ( X , A , B , C ); |
| output X ; |
| input A , B , C ; |
| |
| wire X , A , B , C ; |
| |
| `ifdef functional |
| `else |
| reg csi_notifier; |
| |
| specify |
| if ((!B&!C)) (A +=> X) = (0:0:0,0:0:0); |
| if ((!B&C)) (A -=> X) = (0:0:0,0:0:0); |
| if ((B&!C)) (A -=> X) = (0:0:0,0:0:0); |
| if ((B&C)) (A +=> X) = (0:0:0,0:0:0); |
| if ((!A&!C)) (B +=> X) = (0:0:0,0:0:0); |
| if ((!A&C)) (B -=> X) = (0:0:0,0:0:0); |
| if ((A&!C)) (B -=> X) = (0:0:0,0:0:0); |
| if ((A&C)) (B +=> X) = (0:0:0,0:0:0); |
| if ((!A&!B)) (C +=> X) = (0:0:0,0:0:0); |
| if ((!A&B)) (C -=> X) = (0:0:0,0:0:0); |
| if ((A&!B)) (C -=> X) = (0:0:0,0:0:0); |
| if ((A&B)) (C +=> X) = (0:0:0,0:0:0); |
| endspecify |
| `endif |
| |
| xor #0.001 ( X , A , B , C ) ; |
| endmodule |
| `endcelldefine |
| `disable_portfaults |
| `nosuppress_faults |
| |
| primitive U_DFB(Q, S, R, CK, D); |
| output Q; |
| input S, R, CK, D; |
| reg Q; |
| table |
| 1 0 ? ? : ? : 1; // Asserting preset |
| * 0 ? ? : 1 : 1; // Changing preset |
| ? 1 ? ? : ? : 0; // Asserting reset (dominates preset) |
| 0 * ? ? : 0 : 0; // Changing reset |
| 0 ? (01) 0 : ? : 0; // rising clock |
| ? 0 (01) 1 : ? : 1; // rising clock |
| 0 ? p 0 : 0 : 0; // potential rising clock |
| ? 0 p 1 : 1 : 1; // potential rising clock |
| 0 0 n ? : ? : -; // Clock falling register output does not change |
| 0 0 ? * : ? : -; // Changing Data |
| |
| endtable |
| endprimitive |
| // bnb mar4,2003 - this is a modification of the verplex FF udp |
| // that was edited to work with tetramax and compiles |
| // with verilog-xl with no warnings |
| primitive U_DFB_SETDOM (Q, S, R, CK, D); |
| // same as U_DFB udp but the set line is dominant. |
| output Q; |
| input S, R, CK, D; |
| reg Q; |
| table |
| 0 1 ? ? : ? : 0; // Asserting reset |
| 0 * ? ? : 0 : 0; // Changing reset |
| 1 ? ? ? : ? : 1; // Asserting set (dominates reset) |
| * 0 ? ? : 1 : 1; // Changing set |
| 0 ? (01) 0 : ? : 0; // rising clock |
| ? 0 (01) 1 : ? : 1; // rising clock |
| 0 ? p 0 : 0 : 0; // potential rising clock |
| ? 0 p 1 : 1 : 1; // potential rising clock |
| 0 0 n ? : ? : -; // Clock falling register output does not change |
| 0 0 ? * : ? : -; // Changing Data |
| |
| endtable |
| endprimitive |
| // bnb mar4,2003 - this is a modification of the verplex FF udp |
| // that was edited to work with tetramax and compiles |
| // with verilog-xl with no warnings |
| primitive U_DFB_SETDOM_notify (Q, S, R, CK, D, ntfy); |
| // same as U_DFB udp but the set line is dominant. |
| output Q; |
| input S, R, CK, D, ntfy; |
| reg Q; |
| table |
| 0 1 ? ? ?: ? : 0; // Asserting reset |
| 0 * ? ? ?: 0 : 0; // Changing reset |
| 1 ? ? ? ?: ? : 1; // Asserting set (dominates reset) |
| * 0 ? ? ?: 1 : 1; // Changing set |
| 0 ? (01) 0 ?: ? : 0; // rising clock |
| ? 0 (01) 1 ?: ? : 1; // rising clock |
| 0 ? p 0 ?: 0 : 0; // potential rising clock |
| ? 0 p 1 ?: 1 : 1; // potential rising clock |
| 0 0 n ? ?: ? : -; // Clock falling register output does not change |
| 0 0 ? * ?: ? : -; // Changing Data |
| ? ? ? ? *: ? : X; // go to X on notify |
| |
| endtable |
| endprimitive |
| // bnb mar4,2003 - this is a modification of the verplex FF udp |
| // that was edited to work with tetramax and compiles |
| // with verilog-xl with no warnings |
| primitive U_DFB_notify(Q, S, R, CK, D, ntfy); |
| output Q; |
| input S, R, CK, D, ntfy; |
| reg Q; |
| table |
| 1 0 ? ? ?: ? : 1; // Asserting preset |
| * 0 ? ? ?: 1 : 1; // Changing preset |
| ? 1 ? ? ?: ? : 0; // Asserting reset (dominates preset) |
| 0 * ? ? ?: 0 : 0; // Changing reset |
| 0 ? (01) 0 ?: ? : 0; // rising clock |
| ? 0 (01) 1 ?: ? : 1; // rising clock |
| 0 ? p 0 ?: 0 : 0; // potential rising clock |
| ? 0 p 1 ?: 1 : 1; // potential rising clock |
| 0 0 n ? ?: ? : -; // Clock falling register output does not change |
| 0 0 ? * ?: ? : -; // Changing Data |
| ? ? ? ? *: ? : X; // go to X on notify |
| |
| endtable |
| endprimitive |
| // bnb mar4,2003 - this is a modification of the verplex FF udp |
| // that was edited to work with tetramax and compiles |
| // with verilog-xl with no warnings |
| primitive U_DF_P (Q, D, CP); |
| output Q; |
| input D, CP; |
| reg Q; |
| // FUNCTION : POSITIVE EDGE TRIGGERED D FLIP-FLOP ( Q OUTPUT UDP ). |
| table |
| // D CP : Qt : Qt+1 |
| |
| 1 (01) : ? : 1; // clocked data |
| 0 (01) : ? : 0; |
| |
| 1 (x1) : 1 : 1; // reducing pessimism |
| 0 (x1) : 0 : 0; |
| 1 (0x) : 1 : 1; |
| 0 (0x) : 0 : 0; |
| |
| ? (1x) : ? : -; // no change on falling edge |
| ? (?0) : ? : -; |
| |
| * ? : ? : -; // ignore edges on data |
| endtable |
| endprimitive |
| primitive U_DF_P_KAPWR (Q, D, CP, KAPWR, SLEEPB); |
| output Q; |
| input D, CP, KAPWR, SLEEPB; |
| reg Q; |
| // FUNCTION : POSITIVE EDGE TRIGGERED D FLIP-FLOP ( Q OUTPUT UDP ). |
| table |
| // D CP KAPWR SLEEPB : Qt : Qt+1 |
| |
| ? ? 1 0 : ? : -; // Retain state when in sleep |
| |
| 1 (01) 1 1 : ? : 1; // clocked data |
| 0 (01) 1 1 : ? : 0; |
| |
| 1 (x1) 1 1 : 1 : 1; // reducing pessimism |
| 0 (x1) 1 1 : 0 : 0; |
| 1 (0x) 1 1 : 1 : 1; |
| 0 (0x) 1 1 : 0 : 0; |
| |
| ? (1x) 1 1 : ? : -; // no change on falling edge |
| ? (?0) 1 1 : ? : -; |
| |
| * ? 1 1 : ? : -; // ignore edges on data |
| |
| ? ? 0 ? : ? : x; // KAPWR != 1 |
| ? ? x ? : ? : x; // KAPWR != 1 |
| |
| endtable |
| endprimitive |
| primitive U_DF_P_NO (Q, D, CP , NOTIFIER); |
| output Q; |
| input NOTIFIER, |
| D, CP; |
| reg Q; |
| |
| // FUNCTION : POSITIVE EDGE TRIGGERED D FLIP-FLOP ( Q OUTPUT UDP ). |
| |
| |
| table |
| |
| // D CP NOTIFIER : Qt : Qt+1 |
| |
| 1 (01) ? : ? : 1; // clocked data |
| 0 (01) ? : ? : 0; |
| |
| 1 (x1) ? : 1 : 1; // reducing pessimism |
| 0 (x1) ? : 0 : 0; |
| 1 (0x) ? : 1 : 1; |
| 0 (0x) ? : 0 : 0; |
| |
| ? (1x) ? : ? : -; // no change on falling edge |
| ? (?0) ? : ? : -; |
| |
| * ? ? : ? : -; // ignore edges on data |
| |
| ? ? * : ? : x; |
| endtable |
| endprimitive |
| primitive U_DF_P_NO_KAPWR (Q, D, CP , KAPWR, SLEEPB, NOTIFIER); |
| output Q; |
| input NOTIFIER, |
| D, CP, KAPWR, SLEEPB; |
| reg Q; |
| |
| // FUNCTION : POSITIVE EDGE TRIGGERED D FLIP-FLOP ( Q OUTPUT UDP ). |
| |
| |
| table |
| |
| // D CP KAPWR SLEEPB NOTIFIER : Qt : Qt+1 |
| |
| ? ? 1 0 ? : ? : -; // Retain state during sleep |
| |
| 1 (01) 1 1 ? : ? : 1; // clocked data |
| 0 (01) 1 1 ? : ? : 0; |
| |
| 1 (x1) 1 1 ? : 1 : 1; // reducing pessimism |
| 0 (x1) 1 1 ? : 0 : 0; |
| 1 (0x) 1 1 ? : 1 : 1; |
| 0 (0x) 1 1 ? : 0 : 0; |
| |
| ? (1x) 1 1 ? : ? : -; // no change on falling edge |
| ? (?0) 1 1 ? : ? : -; |
| |
| * ? 1 1 ? : ? : -; // ignore edges on data |
| |
| ? ? 0 ? ? : ? : x; // KAPWR != 1 |
| ? ? x ? ? : ? : x; // KAPWR != 1 |
| |
| ? ? 1 1 * : ? : x; |
| endtable |
| endprimitive |
| primitive U_DF_P_NO_SLEEPB (Q, D, CP , SLEEPB, NOTIFIER); |
| output Q; |
| input D, CP, SLEEPB, NOTIFIER; |
| reg Q; |
| |
| // FUNCTION : POSITIVE EDGE TRIGGERED D FLIP-FLOP ( Q OUTPUT UDP ). |
| |
| |
| table |
| |
| // D CP SLEEPB NOTIFIER : Qt : Qt+1 |
| |
| ? ? 0 ? : ? : -; // Retain state during sleep |
| ? 0 * ? : ? : -; // Retain state during sleep |
| ? 1 * ? : ? : x; // SLEEPB cannot change unless CLK is low |
| ? x * ? : ? : x; // SLEEPB cannot change unless CLK is low |
| |
| 1 (01) 1 ? : ? : 1; // clocked data |
| 0 (01) 1 ? : ? : 0; |
| |
| 1 (x1) 1 ? : 1 : 1; // reducing pessimism |
| 0 (x1) 1 ? : 0 : 0; |
| 1 (0x) 1 ? : 1 : 1; |
| 0 (0x) 1 ? : 0 : 0; |
| |
| ? (1x) 1 ? : ? : -; // no change on falling edge |
| ? (?0) 1 ? : ? : -; |
| |
| * ? 1 ? : ? : -; // ignore edges on data |
| |
| ? ? 1 * : ? : x; |
| endtable |
| endprimitive |
| primitive U_DF_P_R (Q, D, CP, R); |
| output Q; |
| input D, CP, R; |
| reg Q; |
| |
| // FUNCTION : POSITIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE HIGH |
| // ASYNCHRONOUS CLEAR ( Q OUTPUT UDP ). |
| |
| table |
| |
| // D CP R : Qt : Qt+1 |
| |
| 1 (01) 0 : ? : 1; // clocked data |
| 0 (01) 0 : ? : 0; |
| |
| 0 (01) x : ? : 0; // pessimism |
| 0 ? x : 0 : 0; // pessimism |
| |
| 1 0 x : 0 : 0; // pessimism |
| 1 x (?x) : 0 : 0; // pessimism |
| 1 1 (?x) : 0 : 0; // pessimism |
| |
| x 0 x : 0 : 0; // pessimism |
| x x (?x) : 0 : 0; // pessimism |
| x 1 (?x) : 0 : 0; // pessimism |
| |
| 1 (x1) 0 : 1 : 1; // reducing pessimism |
| 0 (x1) 0 : 0 : 0; |
| 1 (0x) 0 : 1 : 1; |
| 0 (0x) 0 : 0 : 0; |
| |
| |
| ? ? 1 : ? : 0; // asynchronous clear |
| |
| ? (?0) ? : ? : -; // ignore falling clock |
| ? (1x) ? : ? : -; // ignore falling clock |
| * ? ? : ? : -; // ignore the edges on data |
| |
| ? ? (?0) : ? : -; // ignore the edges on clear |
| |
| |
| endtable |
| endprimitive |
| primitive U_DF_P_R_KAPWR (Q, D, CP, R, SLEEPB, KAPWR); |
| output Q; |
| input D, CP, R, KAPWR, SLEEPB; |
| reg Q; |
| |
| // FUNCTION : POSITIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE HIGH |
| // ASYNCHRONOUS CLEAR ( Q OUTPUT UDP ). |
| |
| table |
| |
| // D CP R KAPWR SLEEPB : Qt : Qt+1 |
| |
| ? ? ? 1 0 : ? : -; // Retain state during sleep |
| |
| 1 (01) 0 1 1 : ? : 1; // clocked data |
| 0 (01) 0 1 1 : ? : 0; |
| |
| 0 (01) x 1 1 : ? : 0; // pessimism |
| 0 ? x 1 1 : 0 : 0; // pessimism |
| |
| 1 0 x 1 1 : 0 : 0; // pessimism |
| 1 x (?x) 1 1 : 0 : 0; // pessimism |
| 1 1 (?x) 1 1 : 0 : 0; // pessimism |
| |
| x 0 x 1 1 : 0 : 0; // pessimism |
| x x (?x) 1 1 : 0 : 0; // pessimism |
| x 1 (?x) 1 1 : 0 : 0; // pessimism |
| |
| 1 (x1) 0 1 1 : 1 : 1; // reducing pessimism |
| 0 (x1) 0 1 1 : 0 : 0; |
| 1 (0x) 0 1 1 : 1 : 1; |
| 0 (0x) 0 1 1 : 0 : 0; |
| |
| |
| ? ? 1 1 1 : ? : 0; // asynchronous clear |
| |
| ? (?0) ? 1 1 : ? : -; // ignore falling clock |
| ? (1x) ? 1 1 : ? : -; // ignore falling clock |
| * ? ? 1 1 : ? : -; // ignore the edges on data |
| |
| ? ? (?0) 1 1 : ? : -; // ignore the edges on clear |
| |
| ? ? ? 0 ? : ? : x; // KAPWR != 1 |
| ? ? ? x ? : ? : x; // KAPWR != 1 |
| |
| endtable |
| endprimitive |
| primitive U_DF_P_R_NO (Q, D, CP, R, NOTIFIER); |
| output Q; |
| input NOTIFIER, |
| D, CP, R; |
| reg Q; |
| |
| // FUNCTION : POSITIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE HIGH |
| // ASYNCHRONOUS CLEAR ( Q OUTPUT UDP ). |
| |
| |
| table |
| |
| // D CP R NOTIFIER : Qt : Qt+1 |
| |
| 1 (01) 0 ? : ? : 1; // clocked data |
| 0 (01) 0 ? : ? : 0; |
| |
| 0 (01) x ? : ? : 0; // pessimism |
| 0 ? x ? : 0 : 0; // pessimism |
| |
| 1 0 x ? : 0 : 0; // pessimism |
| 1 x (?x) ? : 0 : 0; // pessimism |
| 1 1 (?x) ? : 0 : 0; // pessimism |
| |
| x 0 x ? : 0 : 0; // pessimism |
| x x (?x) ? : 0 : 0; // pessimism |
| x 1 (?x) ? : 0 : 0; // pessimism |
| |
| 1 (x1) 0 ? : 1 : 1; // reducing pessimism |
| 0 (x1) 0 ? : 0 : 0; |
| 1 (0x) 0 ? : 1 : 1; |
| 0 (0x) 0 ? : 0 : 0; |
| |
| |
| ? ? 1 ? : ? : 0; // asynchronous clear |
| |
| ? (?0) ? ? : ? : -; // ignore falling clock |
| ? (1x) ? ? : ? : -; // ignore falling clock |
| * ? ? ? : ? : -; // ignore the edges on data |
| |
| ? ? (?0) ? : ? : -; // ignore the edges on clear |
| ? ? ? * : ? : x; |
| |
| endtable |
| endprimitive |
| primitive U_DF_P_R_NO_KAPWR (Q, D, CP, R, KAPWR, SLEEPB, NOTIFIER); |
| output Q; |
| input D, CP, R, KAPWR, SLEEPB, NOTIFIER; |
| reg Q; |
| |
| // FUNCTION : POSITIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE HIGH |
| // ASYNCHRONOUS CLEAR ( Q OUTPUT UDP ). |
| |
| |
| table |
| |
| // D CP R KAPWR SLEEPB NOTIFIER : Qt : Qt+1 |
| |
| ? ? ? 1 0 ? : ? : -; // Retain state during sleep |
| |
| 1 (01) 0 1 1 ? : ? : 1; // clocked data |
| 0 (01) 0 1 1 ? : ? : 0; |
| |
| 0 (01) x 1 1 ? : ? : 0; // pessimism |
| 0 ? x 1 1 ? : 0 : 0; // pessimism |
| |
| 1 0 x 1 1 ? : 0 : 0; // pessimism |
| 1 x (?x) 1 1 ? : 0 : 0; // pessimism |
| 1 1 (?x) 1 1 ? : 0 : 0; // pessimism |
| |
| x 0 x 1 1 ? : 0 : 0; // pessimism |
| x x (?x) 1 1 ? : 0 : 0; // pessimism |
| x 1 (?x) 1 1 ? : 0 : 0; // pessimism |
| |
| 1 (x1) 0 1 1 ? : 1 : 1; // reducing pessimism |
| 0 (x1) 0 1 1 ? : 0 : 0; |
| 1 (0x) 0 1 1 ? : 1 : 1; |
| 0 (0x) 0 1 1 ? : 0 : 0; |
| |
| |
| ? ? 1 1 1 ? : ? : 0; // asynchronous clear |
| |
| ? (?0) ? 1 1 ? : ? : -; // ignore falling clock |
| ? (1x) ? 1 1 ? : ? : -; // ignore falling clock |
| * ? ? 1 1 ? : ? : -; // ignore the edges on data |
| |
| ? ? (?0) 1 1 ? : ? : -; // ignore the edges on clear |
| |
| ? ? ? 0 ? ? : ? : x; // KAPWR != 1 |
| ? ? ? x ? ? : ? : x; // KAPWR != 1 |
| |
| ? ? ? 1 1 * : ? : x; |
| |
| endtable |
| endprimitive |
| primitive U_DF_P_R_NO_SLEEPB (Q, D, CP, R, SLEEPB, NOTIFIER); |
| output Q; |
| input D, CP, R, SLEEPB, NOTIFIER; |
| reg Q; |
| |
| // FUNCTION : POSITIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE HIGH |
| // ASYNCHRONOUS CLEAR ( Q OUTPUT UDP ). |
| |
| |
| table |
| |
| // D CP R SLEEPB NOTIFIER : Qt : Qt+1 |
| |
| ? ? ? 0 ? : ? : -; // Retain state during sleep |
| ? 0 0 * ? : ? : -; // Retain state during sleep |
| ? 0 1 * ? : ? : -; // Retain state during sleep |
| ? 0 x * ? : ? : x; // SLEEPB cannot change if clear is unknown |
| ? 1 ? * ? : ? : x; // SLEEPB cannot change unless CLK is low |
| ? x ? * ? : ? : x; // SLEEPB cannot change unless CLK is low |
| |
| 1 (01) 0 1 ? : ? : 1; // clocked data |
| 0 (01) 0 1 ? : ? : 0; |
| |
| 0 (01) x 1 ? : ? : 0; // pessimism |
| 0 ? x 1 ? : 0 : 0; // pessimism |
| |
| 1 0 x 1 ? : 0 : 0; // pessimism |
| 1 x (?x) 1 ? : 0 : 0; // pessimism |
| 1 1 (?x) 1 ? : 0 : 0; // pessimism |
| |
| x 0 x 1 ? : 0 : 0; // pessimism |
| x x (?x) 1 ? : 0 : 0; // pessimism |
| x 1 (?x) 1 ? : 0 : 0; // pessimism |
| |
| 1 (x1) 0 1 ? : 1 : 1; // reducing pessimism |
| 0 (x1) 0 1 ? : 0 : 0; |
| 1 (0x) 0 1 ? : 1 : 1; |
| 0 (0x) 0 1 ? : 0 : 0; |
| |
| |
| ? ? 1 1 ? : ? : 0; // asynchronous clear |
| |
| ? (?0) ? 1 ? : ? : -; // ignore falling clock |
| ? (1x) ? 1 ? : ? : -; // ignore falling clock |
| * ? ? 1 ? : ? : -; // ignore the edges on data |
| |
| ? ? (?0) 1 ? : ? : -; // ignore the edges on clear |
| |
| ? ? ? 1 * : ? : x; |
| |
| endtable |
| endprimitive |
| primitive U_DF_P_R_SLEEPB (Q, D, CP, R, SLEEPB); |
| output Q; |
| input D, CP, R, SLEEPB; |
| reg Q; |
| |
| // FUNCTION : POSITIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE HIGH |
| // ASYNCHRONOUS CLEAR ( Q OUTPUT UDP ). |
| |
| table |
| |
| // D CP R SLEEPB : Qt : Qt+1 |
| |
| ? ? ? 0 : ? : -; // Retain state during sleep |
| * ? ? 0 : ? : -; // Retain state during sleep |
| ? ? * 0 : ? : -; // Retain state during sleep |
| ? 0 0 * : ? : -; // Retain state during sleep |
| ? 0 1 * : ? : -; // Retain state during sleep |
| ? 0 x * : ? : x; //SLEEPB cannot change if clear is unknown |
| ? 1 ? * : ? : x; //SLEEPB cannot change unless CLK is low |
| ? x ? * : ? : x; //SLEEPB cannot change unless CLK is low |
| |
| 1 (01) 0 1 : ? : 1; // clocked data |
| 0 (01) 0 1 : ? : 0; |
| |
| 0 (01) x 1 : ? : 0; // pessimism |
| 0 ? x 1 : 0 : 0; // pessimism |
| |
| 1 0 x 1 : 0 : 0; // pessimism |
| 1 x (?x) 1 : 0 : 0; // pessimism |
| 1 1 (?x) 1 : 0 : 0; // pessimism |
| |
| x 0 x 1 : 0 : 0; // pessimism |
| x x (?x) 1 : 0 : 0; // pessimism |
| x 1 (?x) 1 : 0 : 0; // pessimism |
| |
| 1 (x1) 0 1 : 1 : 1; // reducing pessimism |
| 0 (x1) 0 1 : 0 : 0; |
| 1 (0x) 0 1 : 1 : 1; |
| 0 (0x) 0 1 : 0 : 0; |
| |
| |
| ? ? 1 1 : ? : 0; // asynchronous clear |
| |
| ? (?0) ? 1 : ? : -; // ignore falling clock |
| ? (1x) ? 1 : ? : -; // ignore falling clock |
| * ? ? 1 : ? : -; // ignore the edges on data |
| |
| ? ? (?0) 1 : ? : -; // ignore the edges on clear |
| |
| endtable |
| endprimitive |
| primitive U_DF_P_R_SLEEPB_TMAX (Q, D, CP, R, SLEEPB); |
| output Q; |
| input D, CP, R, SLEEPB; |
| reg Q; |
| |
| // FUNCTION : POSITIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE HIGH |
| // ASYNCHRONOUS CLEAR ( Q OUTPUT UDP ). |
| |
| table |
| |
| // D CP R SLEEPB : Qt : Qt+1 |
| |
| ? ? ? 0 : ? : x; // Retain state during sleep |
| |
| 1 (01) 0 1 : ? : 1; // clocked data |
| 0 (01) 0 1 : ? : 0; |
| |
| 0 (01) x 1 : ? : 0; // pessimism |
| 0 ? x 1 : 0 : 0; // pessimism |
| |
| 1 0 x 1 : 0 : 0; // pessimism |
| 1 x (?x) 1 : 0 : 0; // pessimism |
| 1 1 (?x) 1 : 0 : 0; // pessimism |
| |
| x 0 x 1 : 0 : 0; // pessimism |
| x x (?x) 1 : 0 : 0; // pessimism |
| x 1 (?x) 1 : 0 : 0; // pessimism |
| |
| 1 (x1) 0 1 : 1 : 1; // reducing pessimism |
| 0 (x1) 0 1 : 0 : 0; |
| 1 (0x) 0 1 : 1 : 1; |
| 0 (0x) 0 1 : 0 : 0; |
| |
| |
| ? ? 1 1 : ? : 0; // asynchronous clear |
| |
| ? (?0) ? 1 : ? : -; // ignore falling clock |
| ? (1x) ? 1 : ? : -; // ignore falling clock |
| * ? ? 1 : ? : -; // ignore the edges on data |
| |
| ? ? (?0) 1 : ? : -; // ignore the edges on clear |
| |
| endtable |
| endprimitive |
| primitive U_DF_P_S (Q, D, CP, S); |
| output Q; |
| input D, CP, S; |
| reg Q; |
| |
| // FUNCTION : POSITIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE HIGH |
| // ASYNCHRONOUS SET ( Q OUTPUT UDP ) |
| |
| |
| table |
| |
| // D CP S : Qt : Qt+1 |
| |
| 1 (01) 0 : ? : 1; // clocked data |
| 0 (01) 0 : ? : 0; |
| 1 (01) x : ? : 1; // reducing pessimism |
| 1 ? x : 1 : 1; // pessimism |
| |
| 0 0 x : 1 : 1; // pessimism |
| 0 x (?x) : 1 : 1; // pessimism |
| 0 1 (?x) : 1 : 1; // pessimism |
| |
| x 0 x : 1 : 1; // pessimism |
| x x (?x) : 1 : 1; // pessimism |
| x 1 (?x) : 1 : 1; // pessimism |
| |
| 1 (x1) 0 : 1 : 1; // reducing pessimism |
| 0 (x1) 0 : 0 : 0; |
| 1 (0x) 0 : 1 : 1; |
| 0 (0x) 0 : 0 : 0; |
| |
| ? ? 1 : ? : 1; // asynchronous clear |
| |
| ? (?0) ? : ? : -; // ignore falling clock |
| ? (1x) ? : ? : -; // ignore falling clock |
| * ? ? : ? : -; // ignore the data edges |
| |
| ? ? (?0) : ? : -; // ignore the edges on set |
| |
| endtable |
| endprimitive |
| primitive U_DF_P_SLEEPB (Q, D, CP, SLEEPB); |
| output Q; |
| input D, CP, SLEEPB; |
| reg Q; |
| // FUNCTION : POSITIVE EDGE TRIGGERED D FLIP-FLOP ( Q OUTPUT UDP ). |
| table |
| // D CP SLEEPB : Qt : Qt+1 |
| |
| ? ? 0 : ? : -; // Retain state when in sleep |
| * ? 0 : ? : -; // Retain state when in sleep |
| ? 0 * : ? : -; // Retain state during sleep |
| ? 1 * : ? : x; // SLEEPB cannot change unless CLK is low |
| ? x * : ? : x; // SLEEPB cannot change unless CLK is low |
| |
| 1 (01) 1 : ? : 1; // clocked data |
| 0 (01) 1 : ? : 0; |
| |
| 1 (x1) 1 : 1 : 1; // reducing pessimism |
| 0 (x1) 1 : 0 : 0; |
| 1 (0x) 1 : 1 : 1; |
| 0 (0x) 1 : 0 : 0; |
| |
| ? (1x) 1 : ? : -; // no change on falling edge |
| ? (?0) 1 : ? : -; |
| |
| * ? 1 : ? : -; // ignore edges on data |
| |
| endtable |
| endprimitive |
| primitive U_DF_P_SLEEPB_TMAX (Q, D, CP, SLEEPB); |
| output Q; |
| input D, CP, SLEEPB; |
| reg Q; |
| // FUNCTION : POSITIVE EDGE TRIGGERED D FLIP-FLOP ( Q OUTPUT UDP ). |
| table |
| // D CP SLEEPB : Qt : Qt+1 |
| |
| ? ? 0 : ? : x; // Retain state when in sleep |
| |
| 1 (01) 1 : ? : 1; // clocked data |
| 0 (01) 1 : ? : 0; |
| |
| 1 (x1) 1 : 1 : 1; // reducing pessimism |
| 0 (x1) 1 : 0 : 0; |
| 1 (0x) 1 : 1 : 1; |
| 0 (0x) 1 : 0 : 0; |
| |
| ? (1x) 1 : ? : -; // no change on falling edge |
| ? (?0) 1 : ? : -; |
| |
| * ? 1 : ? : -; // ignore edges on data |
| |
| endtable |
| endprimitive |
| primitive U_DF_P_S_KAPWR (Q, D, CP, S, KAPWR, SLEEPB); |
| output Q; |
| input D, CP, S, KAPWR, SLEEPB; |
| reg Q; |
| |
| // FUNCTION : POSITIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE HIGH |
| // ASYNCHRONOUS SET ( Q OUTPUT UDP ) |
| |
| |
| table |
| |
| // D CP S KAPWR SLEEPB : Qt : Qt+1 |
| |
| ? ? ? 1 0 : ? : -; // Retain state during sleep |
| |
| 1 (01) 0 1 1 : ? : 1; // clocked data |
| 0 (01) 0 1 1 : ? : 0; |
| 1 (01) x 1 1 : ? : 1; // reducing pessimism |
| 1 ? x 1 1 : 1 : 1; // pessimism |
| |
| 0 0 x 1 1 : 1 : 1; // pessimism |
| 0 x (?x) 1 1 : 1 : 1; // pessimism |
| 0 1 (?x) 1 1 : 1 : 1; // pessimism |
| |
| x 0 x 1 1 : 1 : 1; // pessimism |
| x x (?x) 1 1 : 1 : 1; // pessimism |
| x 1 (?x) 1 1 : 1 : 1; // pessimism |
| |
| 1 (x1) 0 1 1 : 1 : 1; // reducing pessimism |
| 0 (x1) 0 1 1 : 0 : 0; |
| 1 (0x) 0 1 1 : 1 : 1; |
| 0 (0x) 0 1 1 : 0 : 0; |
| |
| ? ? 1 1 1 : ? : 1; // asynchronous preset |
| |
| ? (?0) ? 1 1 : ? : -; // ignore falling clock |
| ? (1x) ? 1 1 : ? : -; // ignore falling clock |
| * ? ? 1 1 : ? : -; // ignore the data edges |
| |
| ? ? (?0) 1 1 : ? : -; // ignore the edges on set |
| |
| ? ? ? 0 ? : ? : x; // KAPWR != 1 |
| ? ? ? x ? : ? : x; // KAPWR != 1 |
| |
| endtable |
| endprimitive |
| primitive U_DF_P_S_NO (Q, D, CP, S, NOTIFIER); |
| output Q; |
| input NOTIFIER, |
| D, CP, S; |
| reg Q; |
| |
| // FUNCTION : POSITIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE HIGH |
| // ASYNCHRONOUS SET ( Q OUTPUT UDP ) |
| |
| |
| table |
| |
| // D CP S NOTIFIER : Qt : Qt+1 |
| |
| 1 (01) 0 ? : ? : 1; // clocked data |
| 0 (01) 0 ? : ? : 0; |
| 1 (01) x ? : ? : 1; // reducing pessimism |
| 1 ? x ? : 1 : 1; // pessimism |
| |
| 0 0 x ? : 1 : 1; // pessimism |
| 0 x (?x) ? : 1 : 1; // pessimism |
| 0 1 (?x) ? : 1 : 1; // pessimism |
| |
| x 0 x ? : 1 : 1; // pessimism |
| x x (?x) ? : 1 : 1; // pessimism |
| x 1 (?x) ? : 1 : 1; // pessimism |
| |
| 1 (x1) 0 ? : 1 : 1; // reducing pessimism |
| 0 (x1) 0 ? : 0 : 0; |
| 1 (0x) 0 ? : 1 : 1; |
| 0 (0x) 0 ? : 0 : 0; |
| |
| ? ? 1 ? : ? : 1; // asynchronous clear |
| |
| ? (?0) ? ? : ? : -; // ignore falling clock |
| ? (1x) ? ? : ? : -; // ignore falling clock |
| * ? ? ? : ? : -; // ignore the data edges |
| |
| ? ? (?0) ? : ? : -; // ignore the edges on set |
| |
| ? ? ? * : ? : x; |
| |
| endtable |
| endprimitive |
| primitive U_DF_P_S_NO_KAPWR (Q, D, CP, S, KAPWR, SLEEPB, NOTIFIER); |
| output Q; |
| input D, CP, S, KAPWR, SLEEPB, NOTIFIER; |
| reg Q; |
| |
| // FUNCTION : POSITIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE HIGH |
| // ASYNCHRONOUS SET ( Q OUTPUT UDP ) |
| |
| |
| table |
| |
| // D CP S KAPWR SLEEPB NOTIFIER : Qt : Qt+1 |
| |
| ? ? ? 1 0 ? : ? : -; // Retain state during sleep |
| |
| 1 (01) 0 1 1 ? : ? : 1; // clocked data |
| 0 (01) 0 1 1 ? : ? : 0; |
| 1 (01) x 1 1 ? : ? : 1; // reducing pessimism |
| 1 ? x 1 1 ? : 1 : 1; // pessimism |
| |
| 0 0 x 1 1 ? : 1 : 1; // pessimism |
| 0 x (?x) 1 1 ? : 1 : 1; // pessimism |
| 0 1 (?x) 1 1 ? : 1 : 1; // pessimism |
| |
| x 0 x 1 1 ? : 1 : 1; // pessimism |
| x x (?x) 1 1 ? : 1 : 1; // pessimism |
| x 1 (?x) 1 1 ? : 1 : 1; // pessimism |
| |
| 1 (x1) 0 1 1 ? : 1 : 1; // reducing pessimism |
| 0 (x1) 0 1 1 ? : 0 : 0; |
| 1 (0x) 0 1 1 ? : 1 : 1; |
| 0 (0x) 0 1 1 ? : 0 : 0; |
| |
| ? ? 1 1 1 ? : ? : 1; // asynchronous preset |
| |
| ? (?0) ? 1 1 ? : ? : -; // ignore falling clock |
| ? (1x) ? 1 1 ? : ? : -; // ignore falling clock |
| * ? ? 1 1 ? : ? : -; // ignore the data edges |
| |
| ? ? (?0) 1 1 ? : ? : -; // ignore the edges on set |
| |
| ? ? ? 0 ? ? : ? : x; // KAPWR != 1 |
| ? ? ? x ? ? : ? : x; // KAPWR != 1 |
| |
| ? ? ? 1 1 * : ? : x; |
| |
| endtable |
| endprimitive |
| primitive U_DF_P_S_NO_SLEEPB (Q, D, CP, S, SLEEPB, NOTIFIER); |
| output Q; |
| input D, CP, S, SLEEPB, NOTIFIER; |
| reg Q; |
| |
| // FUNCTION : POSITIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE HIGH |
| // ASYNCHRONOUS SET ( Q OUTPUT UDP ) |
| |
| |
| table |
| |
| // D CP S SLEEPB NOTIFIER : Qt : Qt+1 |
| |
| ? ? ? 0 ? : ? : -; // Retain state during sleep |
| ? 0 0 * ? : ? : -; // Retain state during sleep |
| ? 0 1 * ? : ? : -; // Retain state during sleep |
| ? 0 x * ? : ? : x; // SLEEPB cannot change if preset is unknown |
| ? 1 ? * ? : ? : x; // SLEEPB cannot change unless CLK is low |
| ? x ? * ? : ? : x; // SLEEPB cannot change unless CLK is low |
| |
| 1 (01) 0 1 ? : ? : 1; // clocked data |
| 0 (01) 0 1 ? : ? : 0; |
| 1 (01) x 1 ? : ? : 1; // reducing pessimism |
| 1 ? x 1 ? : 1 : 1; // pessimism |
| |
| 0 0 x 1 ? : 1 : 1; // pessimism |
| 0 x (?x) 1 ? : 1 : 1; // pessimism |
| 0 1 (?x) 1 ? : 1 : 1; // pessimism |
| |
| x 0 x 1 ? : 1 : 1; // pessimism |
| x x (?x) 1 ? : 1 : 1; // pessimism |
| x 1 (?x) 1 ? : 1 : 1; // pessimism |
| |
| 1 (x1) 0 1 ? : 1 : 1; // reducing pessimism |
| 0 (x1) 0 1 ? : 0 : 0; |
| 1 (0x) 0 1 ? : 1 : 1; |
| 0 (0x) 0 1 ? : 0 : 0; |
| |
| ? ? 1 1 ? : ? : 1; // asynchronous preset |
| |
| ? (?0) ? 1 ? : ? : -; // ignore falling clock |
| ? (1x) ? 1 ? : ? : -; // ignore falling clock |
| * ? ? 1 ? : ? : -; // ignore the data edges |
| |
| ? ? (?0) 1 ? : ? : -; // ignore the edges on set |
| |
| ? ? ? 1 * : ? : x; |
| |
| endtable |
| endprimitive |
| primitive U_DF_P_S_SLEEPB (Q, D, CP, S, SLEEPB); |
| output Q; |
| input D, CP, S, SLEEPB; |
| reg Q; |
| |
| // FUNCTION : POSITIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE HIGH |
| // ASYNCHRONOUS SET ( Q OUTPUT UDP ) |
| |
| |
| table |
| |
| // D CP S SLEEPB : Qt : Qt+1 |
| |
| ? ? ? 0 : ? : -; // Retain state during sleep |
| * ? ? 0 : ? : -; // Retain state during sleep |
| ? ? * 0 : ? : -; // Retain state during sleep |
| ? 0 0 * : ? : -; // Retain state during sleep |
| ? 0 1 * : ? : -; // Retain state during sleep |
| ? 0 x * : ? : x; // SLEEPB cannot change if preset is unknown |
| ? 1 ? * : ? : x; // SLEEPB cannot change unless CLK is low |
| ? x ? * : ? : x; // SLEEPB cannot change unless CLK is low |
| |
| 1 (01) 0 1 : ? : 1; // clocked data |
| 0 (01) 0 1 : ? : 0; |
| 1 (01) x 1 : ? : 1; // reducing pessimism |
| 1 ? x 1 : 1 : 1; // pessimism |
| |
| 0 0 x 1 : 1 : 1; // pessimism |
| 0 x (?x) 1 : 1 : 1; // pessimism |
| 0 1 (?x) 1 : 1 : 1; // pessimism |
| |
| x 0 x 1 : 1 : 1; // pessimism |
| x x (?x) 1 : 1 : 1; // pessimism |
| x 1 (?x) 1 : 1 : 1; // pessimism |
| |
| 1 (x1) 0 1 : 1 : 1; // reducing pessimism |
| 0 (x1) 0 1 : 0 : 0; |
| 1 (0x) 0 1 : 1 : 1; |
| 0 (0x) 0 1 : 0 : 0; |
| |
| ? ? 1 1 : ? : 1; // asynchronous preset |
| |
| ? (?0) ? 1 : ? : -; // ignore falling clock |
| ? (1x) ? 1 : ? : -; // ignore falling clock |
| * ? ? 1 : ? : -; // ignore the data edges |
| |
| ? ? (?0) 1 : ? : -; // ignore the edges on set |
| |
| endtable |
| endprimitive |
| primitive U_DF_P_S_SLEEPB_TMAX (Q, D, CP, S, SLEEPB); |
| output Q; |
| input D, CP, S, SLEEPB; |
| reg Q; |
| |
| // FUNCTION : POSITIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE HIGH |
| // ASYNCHRONOUS SET ( Q OUTPUT UDP ) |
| |
| |
| table |
| |
| // D CP S SLEEPB : Qt : Qt+1 |
| |
| ? ? ? 0 : ? : x; // Retain state during sleep |
| |
| 1 (01) 0 1 : ? : 1; // clocked data |
| 0 (01) 0 1 : ? : 0; |
| 1 (01) x 1 : ? : 1; // reducing pessimism |
| 1 ? x 1 : 1 : 1; // pessimism |
| |
| 0 0 x 1 : 1 : 1; // pessimism |
| 0 x (?x) 1 : 1 : 1; // pessimism |
| 0 1 (?x) 1 : 1 : 1; // pessimism |
| |
| x 0 x 1 : 1 : 1; // pessimism |
| x x (?x) 1 : 1 : 1; // pessimism |
| x 1 (?x) 1 : 1 : 1; // pessimism |
| |
| 1 (x1) 0 1 : 1 : 1; // reducing pessimism |
| 0 (x1) 0 1 : 0 : 0; |
| 1 (0x) 0 1 : 1 : 1; |
| 0 (0x) 0 1 : 0 : 0; |
| |
| ? ? 1 1 : ? : 1; // asynchronous preset |
| |
| ? (?0) ? 1 : ? : -; // ignore falling clock |
| ? (1x) ? 1 : ? : -; // ignore falling clock |
| * ? ? 1 : ? : -; // ignore the data edges |
| |
| ? ? (?0) 1 : ? : -; // ignore the edges on set |
| |
| endtable |
| endprimitive |
| primitive U_DLB(Q, S, R, G, D); |
| output Q; |
| input S, R, G, D; |
| reg Q; |
| table |
| 1 0 ? ? : ? : 1; // Asserting preset |
| ? 1 ? ? : ? : 0; // Asserting reset (dominates preset) |
| 0 0 1 0 : ? : 0; // Data clocked |
| 0 ? * 0 : 0 : 0; // Clock transitions |
| 0 * 0 ? : 0 : 0; // Changing reset |
| 0 * ? 0 : 0 : 0; |
| 0 x 1 0 : ? : 0; // reset unk. but we dont care -bnb |
| x 0 1 1 : ? : 1; // set unk. but we dont care -bnb |
| 0 0 1 1 : ? : 1; // Data clocked |
| * 0 0 ? : 1 : 1; // Changing preset |
| * 0 ? 1 : 1 : 1; |
| ? 0 * 1 : 1 : 1; // Clock transitions |
| 0 0 0 ? : ? : -; // Hold |
| endtable |
| endprimitive |
| // bnb mar4,2003 - this is a modification of the verplex FF udp |
| // that was edited to work with tetramax and compiles |
| // with verilog-xl with no warnings |
| primitive U_DLB_notify(Q, S, R, G, D, ntfy); |
| output Q; |
| input S, R, G, D, ntfy; |
| reg Q; |
| table |
| 1 0 ? ? ? : ? : 1; // Asserting preset |
| ? 1 ? ? ? : ? : 0; // Asserting reset (dominates preset) |
| 0 0 1 0 ? : ? : 0; // Data clocked |
| 0 ? * 0 ? : 0 : 0; // Clock transitions |
| 0 * 0 ? ? : 0 : 0; // Changing reset |
| 0 * ? 0 ? : 0 : 0; |
| 0 x 1 0 ? : ? : 0; // reset unk. but we dont care -bnb |
| x 0 1 1 ? : ? : 1; // set unk. but we dont care -bnb |
| 0 0 1 1 ? : ? : 1; // Data clocked |
| * 0 0 ? ? : 1 : 1; // Changing preset |
| * 0 ? 1 ? : 1 : 1; |
| ? 0 * 1 ? : 1 : 1; // Clock transitions |
| 0 0 0 ? ? : ? : -; // Hold |
| ? ? ? ? * : ? : X; // go to x on notify. |
| endtable |
| endprimitive |
| // bnb mar4,2003 - this is a modification of the verplex FF udp |
| // that was edited to work with tetramax and compiles |
| // with verilog-xl with no warnings |
| primitive U_DL_P (Q, D, G); |
| // |
| // FUNCTION : DLATCH, GATED STANDARD DRIVE / ACTIVE HIGH ( Q OUTPUT UDP ) |
| // |
| |
| output Q; |
| reg Q; |
| input D, G; |
| |
| table |
| // D G : Qt : Qt+1 |
| |
| ? 0 : ? : - ; // clock disabled |
| |
| 0 1 : ? : 0 ; //clock enabled |
| 1 1 : ? : 1 ; //transparent data |
| |
| 1 x : 1 : 1 ; // Reducing pessimism. |
| 0 x : 0 : 0 ; |
| |
| ? n : ? : - ; |
| |
| endtable |
| |
| endprimitive |
| primitive U_DL_P_KAPWR (Q, D, G, KAPWR, SLEEPB); |
| // |
| // FUNCTION : DLATCH, GATED STANDARD DRIVE / ACTIVE HIGH ( Q OUTPUT UDP ) |
| // |
| |
| output Q; |
| reg Q; |
| input D, G, KAPWR, SLEEPB; |
| |
| table |
| // D G KAPWR SLEEPB : Qt : Qt+1 |
| |
| ? ? 1 0 : ? : - ; // Retain state during sleep |
| |
| ? 0 1 1 : ? : - ; // clock disabled |
| |
| 0 1 1 1 : ? : 0 ; //clock enabled |
| 1 1 1 1 : ? : 1 ; //transparent data |
| |
| 1 x 1 1 : 1 : 1 ; // Reducing pessimism. |
| 0 x 1 1 : 0 : 0 ; |
| |
| ? n 1 1 : ? : - ; |
| |
| ? ? 0 ? : ? : x ; // KAPWR != 1 |
| ? ? x ? : ? : x ; // KAPWR != 1 |
| |
| endtable |
| |
| endprimitive |
| primitive U_DL_P_NO (Q, D, G, NOTIFIER); |
| output Q; |
| reg Q; |
| input D, // data |
| G, // clock |
| NOTIFIER; |
| // FUNCTION : DLATCH, GATED STANDARD DRIVE / ACTIVE HIGH ( Q OUTPUT UDP ) |
| // |
| |
| |
| table |
| // D G NOTIFIER : Qtn : Qtn+1 |
| |
| * 0 ? : ? : - ; |
| |
| ? n ? : ? : - ; |
| |
| 0 (0x) ? : 0 : 0 ; |
| 1 (0x) ? : 1 : 1 ; |
| 0 (x1) ? : ? : 0 ; |
| 1 (x1) ? : ? : 1 ; |
| |
| (?0) 1 ? : ? : 0 ; |
| (?1) 1 ? : ? : 1 ; |
| 0 (01) ? : ? : 0 ; |
| 1 (01) ? : ? : 1 ; |
| |
| (?1) x ? : 1 : 1 ; // Reducing pessimism. |
| (?0) x ? : 0 : 0 ; |
| |
| ? ? * : ? : x ; |
| |
| |
| endtable |
| |
| endprimitive |
| primitive U_DL_P_NO_KAPWR (Q, D, G, KAPWR, SLEEPB, NOTIFIER); |
| output Q; |
| reg Q; |
| input D, // data |
| G, // clock |
| KAPWR, SLEEPB, |
| NOTIFIER; |
| // FUNCTION : DLATCH, GATED STANDARD DRIVE / ACTIVE HIGH ( Q OUTPUT UDP ) |
| // |
| |
| |
| table |
| // D G KAPWR SLEEPB NOTIFIER : Qtn : Qtn+1 |
| |
| ? ? 1 0 ? : ? : - ; |
| |
| * 0 1 1 ? : ? : - ; |
| |
| ? n 1 1 ? : ? : - ; |
| |
| 0 (0x) 1 1 ? : 0 : 0 ; |
| 1 (0x) 1 1 ? : 1 : 1 ; |
| 0 (x1) 1 1 ? : ? : 0 ; |
| 1 (x1) 1 1 ? : ? : 1 ; |
| |
| (?0) 1 1 1 ? : ? : 0 ; |
| (?1) 1 1 1 ? : ? : 1 ; |
| 0 (01) 1 1 ? : ? : 0 ; |
| 1 (01) 1 1 ? : ? : 1 ; |
| |
| (?1) x 1 1 ? : 1 : 1 ; // Reducing pessimism. |
| (?0) x 1 1 ? : 0 : 0 ; |
| |
| ? ? 0 ? ? : ? : x ; |
| ? ? x ? ? : ? : x ; |
| |
| ? ? 1 1 * : ? : x ; |
| |
| |
| endtable |
| |
| endprimitive |
| primitive U_DL_P_NO_SLEEPB (Q, D, G, SLEEPB, NOTIFIER); |
| output Q; |
| reg Q; |
| input D, // data |
| G, // clock |
| SLEEPB, |
| NOTIFIER; |
| // FUNCTION : DLATCH, GATED STANDARD DRIVE / ACTIVE HIGH ( Q OUTPUT UDP ) |
| // |
| |
| |
| table |
| // D G SLEEPB NOTIFIER : Qtn : Qtn+1 |
| |
| ? ? 0 ? : ? : - ; // Retain state during sleep |
| ? 0 * ? : ? : - ; // Retain state during sleep |
| ? 1 * ? : ? : x ; // SLEEPB cannot change unless GATE is low |
| ? x * ? : ? : x ; // SLEEPB cannot change unless GATE is low |
| |
| * 0 1 ? : ? : - ; |
| |
| ? n 1 ? : ? : - ; |
| |
| 0 (0x) 1 ? : 0 : 0 ; |
| 1 (0x) 1 ? : 1 : 1 ; |
| 0 (x1) 1 ? : ? : 0 ; |
| 1 (x1) 1 ? : ? : 1 ; |
| |
| (?0) 1 1 ? : ? : 0 ; |
| (?1) 1 1 ? : ? : 1 ; |
| 0 (01) 1 ? : ? : 0 ; |
| 1 (01) 1 ? : ? : 1 ; |
| |
| (?1) x 1 ? : 1 : 1 ; // Reducing pessimism. |
| (?0) x 1 ? : 0 : 0 ; |
| |
| ? ? 1 * : ? : x ; |
| |
| |
| endtable |
| |
| endprimitive |
| primitive U_DL_P_R (Q, D, G, R); |
| // |
| // FUNCTION : D-LATCH, GATED CLEAR DIRECT /GATE ACTIVE HIGH ( Q OUTPUT UDP ) |
| // |
| |
| output Q; |
| reg Q; |
| input D, |
| G, // Gate- active high |
| R; // Clear-active high |
| |
| table |
| // D G R : Qt : Qt+1 |
| |
| ? 0 0 : ? : - ; // latch state |
| |
| 0 1 0 : ? : 0 ; // latch data |
| 1 1 0 : ? : 1 ; |
| |
| 1 x 0 : 1 : 1 ; // Reducing pessimism. |
| 0 x 0 : 0 : 0 ; // Reducing pessimism |
| |
| ? n 0 : ? : - ; |
| |
| ? ? 1 : ? : 0 ; // Clear |
| |
| 0 1 x : ? : 0 ; // Reducing pessimism. |
| ? 0 x : 0 : 0 ; // Reducing pessimism |
| |
| endtable |
| |
| endprimitive |
| |
| primitive U_DL_P_R_KAPWR (Q, D, G, R, KAPWR, SLEEPB); |
| // |
| // FUNCTION : D-LATCH, GATED CLEAR DIRECT /GATE ACTIVE HIGH ( Q OUTPUT UDP ) |
| // |
| |
| output Q; |
| reg Q; |
| input D, |
| G, // Gate- active high |
| R, // Clear-active high |
| KAPWR, SLEEPB; |
| |
| table |
| // D G R KAPWR SLEEPB : Qt : Qt+1 |
| |
| ? ? ? 1 0 : ? : - ; // Retain state during sleep |
| |
| ? 0 0 1 1 : ? : - ; // latch state |
| |
| 0 1 0 1 1 : ? : 0 ; // latch data |
| 1 1 0 1 1 : ? : 1 ; |
| |
| 1 x 0 1 1 : 1 : 1 ; // Reducing pessimism. |
| 0 x 0 1 1 : 0 : 0 ; // Reducing pessimism |
| |
| ? n 0 1 1 : ? : - ; |
| |
| ? ? 1 1 1 : ? : 0 ; // Clear |
| |
| 0 1 x 1 1 : ? : 0 ; // Reducing pessimism. |
| ? 0 x 1 1 : 0 : 0 ; // Reducing pessimism |
| |
| ? ? ? 0 ? : ? : x ; // KAPWR != 1 |
| ? ? ? x ? : ? : x ; // KAPWR != 1 |
| |
| endtable |
| |
| endprimitive |
| |
| primitive U_DL_P_R_NO (Q, D, G, R, NOTIFIER); |
| output Q; |
| reg Q; |
| input D, // DATA |
| G, // CLOCK |
| R, // CLEAR ACTIVE HIGH |
| NOTIFIER; // NOTIFY REG |
| // FUNCTION : D-LATCH, GATED CLEAR DIRECT /GATE ACTIVE HIGH ( Q OUTPUT UDP ) |
| // |
| table |
| // D G R NOTIFIER : Qt : Qt+1 |
| |
| * 0 0 ? : ? : - ; |
| |
| ? ? 1 ? : ? : 0 ; // asynchro clear |
| |
| ? (?0) 0 ? : ? : - ; // Changed R=? to R=0 ; jek 08/14/06 |
| ? (1x) 0 ? : ? : - ; // Changed R=? to R=0 ; jek 08/14/06 |
| |
| 0 (0x) 0 ? : 0 : 0 ; |
| 1 (0x) 0 ? : 1 : 1 ; |
| 0 (x1) 0 ? : ? : 0 ; |
| 1 (x1) 0 ? : ? : 1 ; |
| |
| (?0) 1 0 ? : ? : 0 ; |
| (?1) 1 0 ? : ? : 1 ; |
| 0 (01) 0 ? : ? : 0 ; |
| 1 (01) 0 ? : ? : 1 ; |
| |
| ? 0 (?x) ? : 0 : 0 ; // Reducing pessimism.//AB |
| * 0 x ? : 0 : 0 ; // Reducing pessimism//AB |
| |
| 0 (?1) x ? : ? : 0 ; // Reducing pessimism. |
| (?0) 1 x ? : ? : 0 ; // Reducing pessimism. |
| 0 1 (?x) ? : ? : 0 ; // Reducing pessimism.//AB |
| |
| ? 0 (?0) ? : ? : - ; // ignore edge on clear |
| 0 1 (?0) ? : ? : 0 ; // pessimism . |
| 1 1 (?0) ? : ? : 1 ; |
| |
| (?1) x 0 ? : 1 : 1 ; // Reducing pessimism. |
| (?0) x 0 ? : 0 : 0 ; // Reducing pessimism. |
| |
| ? ? ? * : ? : x ; |
| |
| endtable |
| |
| endprimitive |
| primitive U_DL_P_R_NO_KAPWR (Q, D, G, R, KAPWR, SLEEPB, NOTIFIER); |
| output Q; |
| reg Q; |
| input D, // DATA |
| G, // CLOCK |
| R, // CLEAR ACTIVE HIGH |
| KAPWR, SLEEPB, |
| NOTIFIER; // NOTIFY REG |
| // FUNCTION : D-LATCH, GATED CLEAR DIRECT /GATE ACTIVE HIGH ( Q OUTPUT UDP ) |
| // |
| table |
| // D G R KAPWR SLEEPB NOTIFIER : Qt : Qt+1 |
| |
| ? ? ? 1 0 ? : ? : - ; // Retain state during sleep |
| |
| * 0 0 1 1 ? : ? : - ; |
| |
| ? ? 1 1 1 ? : ? : 0 ; // asynchro clear |
| |
| ? (?0) 0 1 1 ? : ? : - ; // Changed R=? to R=0 |
| ? (1x) 0 1 1 ? : ? : - ; // Changed R=? to R=0 |
| |
| 0 (0x) 0 1 1 ? : 0 : 0 ; |
| 1 (0x) 0 1 1 ? : 1 : 1 ; |
| 0 (x1) 0 1 1 ? : ? : 0 ; |
| 1 (x1) 0 1 1 ? : ? : 1 ; |
| |
| (?0) 1 0 1 1 ? : ? : 0 ; |
| (?1) 1 0 1 1 ? : ? : 1 ; |
| 0 (01) 0 1 1 ? : ? : 0 ; |
| 1 (01) 0 1 1 ? : ? : 1 ; |
| |
| ? 0 (?x) 1 1 ? : 0 : 0 ; // Reducing pessimism.//AB |
| * 0 x 1 1 ? : 0 : 0 ; // Reducing pessimism//AB |
| |
| 0 (?1) x 1 1 ? : ? : 0 ; // Reducing pessimism. |
| (?0) 1 x 1 1 ? : ? : 0 ; // Reducing pessimism. |
| 0 1 (?x) 1 1 ? : ? : 0 ; // Reducing pessimism.//AB |
| |
| ? 0 (?0) 1 1 ? : ? : - ; // ignore edge on clear |
| 0 1 (?0) 1 1 ? : ? : 0 ; // pessimism . |
| 1 1 (?0) 1 1 ? : ? : 1 ; |
| |
| (?1) x 0 1 1 ? : 1 : 1 ; // Reducing pessimism. |
| (?0) x 0 1 1 ? : 0 : 0 ; // Reducing pessimism. |
| |
| ? ? ? 0 ? ? : ? : x ; // kapwr != 1 |
| ? ? ? x ? ? : ? : x ; // kapwr != 1 |
| |
| ? ? ? 1 1 * : ? : x ; |
| |
| endtable |
| |
| endprimitive |
| primitive U_DL_P_R_NO_SLEEPB (Q, D, G, R, SLEEPB, NOTIFIER); |
| output Q; |
| reg Q; |
| input D, // DATA |
| G, // CLOCK |
| R, // CLEAR ACTIVE HIGH |
| SLEEPB, |
| NOTIFIER; // NOTIFY REG |
| // FUNCTION : D-LATCH, GATED CLEAR DIRECT /GATE ACTIVE HIGH ( Q OUTPUT UDP ) |
| // |
| table |
| // D G R SLEEPB NOTIFIER : Qt : Qt+1 |
| |
| ? ? ? 0 ? : ? : - ; // Retain state during sleep |
| ? 0 0 * ? : ? : - ; // Retain state during sleep |
| ? 0 1 * ? : ? : - ; // Retain state during sleep |
| ? 0 x * ? : ? : x ; // SLEEPB cannot change if clear is unknown |
| ? 1 ? * ? : ? : x ; // SLEEPB cannot change unless GATE is low |
| ? x ? * ? : ? : x ; // SLEEPB cannot change unless GATE is low |
| |
| * 0 0 1 ? : ? : - ; |
| |
| ? ? 1 1 ? : ? : 0 ; // asynchro clear |
| |
| ? (?0) 0 1 ? : ? : - ; // Changed R=? to R=0 |
| ? (1x) 0 1 ? : ? : - ; // Changed R=? to R=0 |
| |
| 0 (0x) 0 1 ? : 0 : 0 ; |
| 1 (0x) 0 1 ? : 1 : 1 ; |
| 0 (x1) 0 1 ? : ? : 0 ; |
| 1 (x1) 0 1 ? : ? : 1 ; |
| |
| (?0) 1 0 1 ? : ? : 0 ; |
| (?1) 1 0 1 ? : ? : 1 ; |
| 0 (01) 0 1 ? : ? : 0 ; |
| 1 (01) 0 1 ? : ? : 1 ; |
| |
| ? 0 (?x) 1 ? : 0 : 0 ; // Reducing pessimism.//AB |
| * 0 x 1 ? : 0 : 0 ; // Reducing pessimism//AB |
| |
| 0 (?1) x 1 ? : ? : 0 ; // Reducing pessimism. |
| (?0) 1 x 1 ? : ? : 0 ; // Reducing pessimism. |
| 0 1 (?x) 1 ? : ? : 0 ; // Reducing pessimism.//AB |
| |
| ? 0 (?0) 1 ? : ? : - ; // ignore edge on clear |
| 0 1 (?0) 1 ? : ? : 0 ; // pessimism . |
| 1 1 (?0) 1 ? : ? : 1 ; |
| |
| (?1) x 0 1 ? : 1 : 1 ; // Reducing pessimism. |
| (?0) x 0 1 ? : 0 : 0 ; // Reducing pessimism. |
| |
| ? ? ? 1 * : ? : x ; |
| |
| endtable |
| |
| endprimitive |
| primitive U_DL_P_R_SLEEPB (Q, D, G, R, SLEEPB); |
| // |
| // FUNCTION : D-LATCH, GATED CLEAR DIRECT /GATE ACTIVE HIGH ( Q OUTPUT UDP ) |
| // |
| |
| output Q; |
| reg Q; |
| input D, |
| G, // Gate- active high |
| R, // Clear-active high |
| SLEEPB; |
| |
| table |
| // D G R SLEEPB : Qt : Qt+1 |
| |
| ? ? ? 0 : ? : - ; // Retain state during sleep |
| * ? ? 0 : ? : - ; // Retain state during sleep |
| ? ? * 0 : ? : - ; // Retain state during sleep |
| ? 0 1 * : ? : - ; // Retain state during sleep |
| ? 0 0 * : ? : - ; // Retain state during sleep |
| ? 0 x * : ? : x ; // SLEEPB cannot change if clear is unknown |
| ? 1 ? * : ? : x ; // SLEEPB cannot change unless GATE is low |
| ? x ? * : ? : x ; // SLEEPB cannot change unless GATE is low |
| |
| ? 0 0 1 : ? : - ; // latch state |
| |
| 0 1 0 1 : ? : 0 ; // latch data |
| 1 1 0 1 : ? : 1 ; |
| |
| 1 x 0 1 : 1 : 1 ; // Reducing pessimism. |
| 0 x 0 1 : 0 : 0 ; // Reducing pessimism |
| |
| ? n 0 1 : ? : - ; |
| |
| ? ? 1 1 : ? : 0 ; // Clear |
| |
| 0 1 x 1 : ? : 0 ; // Reducing pessimism. |
| ? 0 x 1 : 0 : 0 ; // Reducing pessimism |
| |
| endtable |
| |
| endprimitive |
| |
| primitive U_DL_P_R_SLEEPB_TMAX (Q, D, G, R, SLEEPB); |
| // |
| // FUNCTION : D-LATCH, GATED CLEAR DIRECT /GATE ACTIVE HIGH ( Q OUTPUT UDP ) |
| // |
| |
| output Q; |
| reg Q; |
| input D, |
| G, // Gate- active high |
| R, // Clear-active high |
| SLEEPB; |
| |
| table |
| // D G R SLEEPB : Qt : Qt+1 |
| |
| ? ? ? 0 : ? : x ; // Retain state during sleep |
| |
| ? 0 0 1 : ? : - ; // latch state |
| |
| 0 1 0 1 : ? : 0 ; // latch data |
| 1 1 0 1 : ? : 1 ; |
| |
| 1 x 0 1 : 1 : 1 ; // Reducing pessimism. |
| 0 x 0 1 : 0 : 0 ; // Reducing pessimism |
| |
| ? n 0 1 : ? : - ; |
| |
| ? ? 1 1 : ? : 0 ; // Clear |
| |
| 0 1 x 1 : ? : 0 ; // Reducing pessimism. |
| ? 0 x 1 : 0 : 0 ; // Reducing pessimism |
| |
| endtable |
| |
| endprimitive |
| |
| primitive U_DL_P_SB (Q, D, G, SB); |
| // |
| // FUNCTION : D-LATCH, GATED SET DIRECT /GATE ACTIVE HIGH ( Q OUTPUT UDP ) |
| // |
| |
| output Q; |
| reg Q; |
| input D, |
| G, // Gate- active high |
| SB; // Set-active low |
| |
| table |
| // D G SB : Qt : Qt+1 |
| |
| ? 0 1 : ? : - ; // latch state |
| |
| 0 1 1 : ? : 0 ; // latch data |
| 1 1 1 : ? : 1 ; |
| |
| 1 x 1 : 1 : 1 ; // Reducing pessimism. |
| 0 x 1 : 0 : 0 ; // Reducing pessimism |
| |
| ? n 1 : ? : - ; |
| |
| ? ? 0 : ? : 1 ; // Set |
| |
| 1 1 x : ? : 1 ; // Reducing pessimism. |
| ? 0 x : 1 : 1 ; // Reducing pessimism |
| 1 ? x : 1 : 1 ; // Reducing pessimism |
| |
| endtable |
| |
| endprimitive |
| primitive U_DL_P_SB_KAPWR ( Q, D, G, SB, KAPWR, SLEEPB ); |
| |
| output Q; |
| reg Q; |
| input D, |
| G, |
| SB, |
| KAPWR, SLEEPB; |
| |
| // FUNCTION : POSITIVE LEVEL SENSITIVE D-TYPE LATCH WITH ACTIVE LOW |
| // ASYNCHRONOUS SET ( Q OUTPUT UDP ). |
| |
| table |
| // D G SB KAPWR SLEEPB : Qt : Qt+1 |
| |
| ? ? ? 1 0 : ? : - ; // Retain state during sleep |
| |
| 1 1 1 1 1 : ? : 1 ; // clock enabled transparent data. |
| 0 1 1 1 1 : ? : 0 ; |
| |
| 1 x 1 1 1 : 1 : 1 ; // possible enabled clock. |
| 0 x 1 1 1 : 0 : 0 ; |
| |
| ? ? 0 1 1 : ? : 1 ; // asynchronous set. |
| |
| ? 0 1 1 1 : ? : - ; // clock disabled. |
| |
| 1 1 x 1 1 : ? : 1 ; // pessimism |
| 1 ? x 1 1 : 1 : 1 ; // pessimism |
| ? 0 x 1 1 : 1 : 1 ; // pessimism |
| |
| ? n 1 1 1 : ? : - ; |
| |
| ? ? ? 0 ? : ? : x ; // KAPWR != 1 |
| ? ? ? x ? : ? : x ; // KAPWR != 1 |
| |
| endtable |
| |
| endprimitive |
| primitive U_DL_P_SB_NO (Q, D, G, SB, NOTI_REG); |
| |
| |
| output Q; |
| reg Q; |
| input D, // DATA |
| G, // CLOCK |
| SB, // SET ACTIVE LOW |
| NOTI_REG; // NOTIFY REG |
| // FUNCTION : POSITIVE LEVEL SENSITIVE D-TYPE LATCH WITH ACTIVE LOW |
| // ASYNCHRONOUS SET ( Q OUTPUT UDP ). |
| |
| |
| table |
| // D G SB NOTI_REG : Qt : Qt+1 |
| |
| * 0 1 ? : ? : - ; |
| |
| ? ? 0 ? : ? : 1 ; // asynchro SET |
| |
| ? (?0) ? ? : ? : - ; //AB |
| ? (1X) ? ? : ? : - ; //AB |
| |
| 0 (X1) 1 ? : ? : 0 ; |
| 1 (X1) 1 ? : ? : 1 ; |
| 0 (0X) 1 ? : 0 : 0 ; |
| 1 (0X) 1 ? : 1 : 1 ; |
| |
| (?0) 1 1 ? : ? : 0 ; |
| (?1) 1 1 ? : ? : 1 ; |
| 0 (01) 1 ? : ? : 0 ; |
| 1 (01) 1 ? : ? : 1 ; |
| |
| |
| ? 0 (?x) ? : 1 : 1 ; // Reducing pessimism.//AB |
| * 0 x ? : 1 : 1 ; // Reducing pessimism//AB |
| |
| (?1) x x ? : 1 : 1 ; // Reducing pessimism.//AB |
| 1 x * ? : 1 : 1 ; // Reducing pessimism.//AB |
| 1 (0x) x ? : 1 : 1 ; // Reducing pessimism.//AB |
| |
| 1 (?1) x ? : ? : 1 ; // Reducing pessimism. |
| (?1) 1 x ? : ? : 1 ; // Reducing pessimism. |
| 1 1 (?x) ? : ? : 1 ; // Reducing pessimism. |
| |
| ? 0 (?1) ? : ? : - ; // ignore edge on clear |
| 0 1 (?1) ? : ? : 0 ; |
| 1 1 (?1) ? : ? : 1 ; |
| |
| (?1) x 1 ? : 1 : 1 ; // Reducing pessimism. |
| (?0) x 1 ? : 0 : 0 ; // Reducing pessimism. |
| |
| ? ? ? * : ? : x ; |
| |
| endtable |
| |
| endprimitive |
| primitive U_DL_P_SB_NO_KAPWR (Q, D, G, SB, KAPWR, SLEEPB, NOTI_REG); |
| |
| |
| output Q; |
| reg Q; |
| input D, // DATA |
| G, // CLOCK |
| SB, // SET ACTIVE LOW |
| KAPWR, SLEEPB, |
| NOTI_REG; // NOTIFY REG |
| // FUNCTION : POSITIVE LEVEL SENSITIVE D-TYPE LATCH WITH ACTIVE LOW |
| // ASYNCHRONOUS SET ( Q OUTPUT UDP ). |
| |
| |
| table |
| // D G SB KAPWR SLEEPB NOTI_REG : Qt : Qt+1 |
| |
| ? ? ? 1 0 ? : ? : - ; // Retain state during sleep |
| |
| * 0 1 1 1 ? : ? : - ; |
| |
| ? ? 0 1 1 ? : ? : 1 ; // asynchro SET |
| |
| ? (?0) ? 1 1 ? : ? : - ; //AB |
| ? (1X) ? 1 1 ? : ? : - ; //AB |
| |
| 0 (X1) 1 1 1 ? : ? : 0 ; |
| 1 (X1) 1 1 1 ? : ? : 1 ; |
| 0 (0X) 1 1 1 ? : 0 : 0 ; |
| 1 (0X) 1 1 1 ? : 1 : 1 ; |
| |
| (?0) 1 1 1 1 ? : ? : 0 ; |
| (?1) 1 1 1 1 ? : ? : 1 ; |
| 0 (01) 1 1 1 ? : ? : 0 ; |
| 1 (01) 1 1 1 ? : ? : 1 ; |
| |
| |
| ? 0 (?x) 1 1 ? : 1 : 1 ; // Reducing pessimism.//AB |
| * 0 x 1 1 ? : 1 : 1 ; // Reducing pessimism//AB |
| |
| (?1) x x 1 1 ? : 1 : 1 ; // Reducing pessimism.//AB |
| 1 x * 1 1 ? : 1 : 1 ; // Reducing pessimism.//AB |
| 1 (0x) x 1 1 ? : 1 : 1 ; // Reducing pessimism.//AB |
| |
| 1 (?1) x 1 1 ? : ? : 1 ; // Reducing pessimism. |
| (?1) 1 x 1 1 ? : ? : 1 ; // Reducing pessimism. |
| 1 1 (?x) 1 1 ? : ? : 1 ; // Reducing pessimism. |
| |
| ? 0 (?1) 1 1 ? : ? : - ; // ignore edge on clear |
| 0 1 (?1) 1 1 ? : ? : 0 ; |
| 1 1 (?1) 1 1 ? : ? : 1 ; |
| |
| (?1) x 1 1 1 ? : 1 : 1 ; // Reducing pessimism. |
| (?0) x 1 1 1 ? : 0 : 0 ; // Reducing pessimism. |
| |
| ? ? ? 0 ? ? : ? : x ; |
| ? ? ? x ? ? : ? : x ; |
| |
| ? ? ? 1 1 * : ? : x ; |
| |
| endtable |
| |
| endprimitive |
| primitive U_DL_P_SB_NO_SLEEPB (Q, D, G, SB, SLEEPB, NOTI_REG); |
| |
| |
| output Q; |
| reg Q; |
| input D, // DATA |
| G, // CLOCK |
| SB, // SET ACTIVE LOW |
| SLEEPB, |
| NOTI_REG; // NOTIFY REG |
| // FUNCTION : POSITIVE LEVEL SENSITIVE D-TYPE LATCH WITH ACTIVE LOW |
| // ASYNCHRONOUS SET ( Q OUTPUT UDP ). |
| |
| |
| table |
| // D G SB SLEEPB NOTI_REG : Qt : Qt+1 |
| |
| ? ? ? 0 ? : ? : - ; // Retain state during sleep |
| ? 0 0 * ? : ? : - ; // Retain state during sleep |
| ? 0 1 * ? : ? : - ; // Retain state during sleep |
| ? 0 x * ? : ? : x ; // SLEEPB cannot change if preset is unknown |
| ? 1 ? * ? : ? : x ; // SLEEPB cannot change unless GATE is low |
| ? x ? * ? : ? : x ; // SLEEPB cannot change unless GATE is low |
| |
| * 0 1 1 ? : ? : - ; |
| |
| ? ? 0 1 ? : ? : 1 ; // asynchro SET |
| |
| ? (?0) ? 1 ? : ? : - ; //AB |
| ? (1X) ? 1 ? : ? : - ; //AB |
| |
| 0 (X1) 1 1 ? : ? : 0 ; |
| 1 (X1) 1 1 ? : ? : 1 ; |
| 0 (0X) 1 1 ? : 0 : 0 ; |
| 1 (0X) 1 1 ? : 1 : 1 ; |
| |
| (?0) 1 1 1 ? : ? : 0 ; |
| (?1) 1 1 1 ? : ? : 1 ; |
| 0 (01) 1 1 ? : ? : 0 ; |
| 1 (01) 1 1 ? : ? : 1 ; |
| |
| |
| ? 0 (?x) 1 ? : 1 : 1 ; // Reducing pessimism.//AB |
| * 0 x 1 ? : 1 : 1 ; // Reducing pessimism//AB |
| |
| (?1) x x 1 ? : 1 : 1 ; // Reducing pessimism.//AB |
| 1 x * 1 ? : 1 : 1 ; // Reducing pessimism.//AB |
| 1 (0x) x 1 ? : 1 : 1 ; // Reducing pessimism.//AB |
| |
| 1 (?1) x 1 ? : ? : 1 ; // Reducing pessimism. |
| (?1) 1 x 1 ? : ? : 1 ; // Reducing pessimism. |
| 1 1 (?x) 1 ? : ? : 1 ; // Reducing pessimism. |
| |
| ? 0 (?1) 1 ? : ? : - ; // ignore edge on clear |
| 0 1 (?1) 1 ? : ? : 0 ; |
| 1 1 (?1) 1 ? : ? : 1 ; |
| |
| (?1) x 1 1 ? : 1 : 1 ; // Reducing pessimism. |
| (?0) x 1 1 ? : 0 : 0 ; // Reducing pessimism. |
| |
| ? ? ? 1 * : ? : x ; |
| |
| endtable |
| |
| endprimitive |
| primitive U_DL_P_SB_SLEEPB ( Q, D, G, SB, SLEEPB ); |
| |
| output Q; |
| reg Q; |
| input D, |
| G, |
| SB, |
| SLEEPB; |
| |
| // FUNCTION : POSITIVE LEVEL SENSITIVE D-TYPE LATCH WITH ACTIVE LOW |
| // ASYNCHRONOUS SET ( Q OUTPUT UDP ). |
| |
| table |
| // D G SB SLEEPB : Qt : Qt+1 |
| |
| ? ? ? 0 : ? : - ; // Retain state during sleep |
| * ? ? 0 : ? : - ; // Retain state during sleep |
| ? ? * 0 : ? : - ; // Retain state during sleep |
| ? 0 0 * : ? : - ; // Retain state during sleep |
| ? 0 1 * : ? : - ; // Retain state during sleep |
| ? 0 x * : ? : x ; // SLEEPB cannot change if preset is unknown |
| ? 1 ? * : ? : x ; // SLEEPB cannot change unless GATE is low |
| ? x ? * : ? : x ; // SLEEPB cannot change unless GATE is low |
| |
| 1 1 1 1 : ? : 1 ; // clock enabled transparent data. |
| 0 1 1 1 : ? : 0 ; |
| |
| 1 x 1 1 : 1 : 1 ; // possible enabled clock. |
| 0 x 1 1 : 0 : 0 ; |
| |
| ? ? 0 1 : ? : 1 ; // asynchronous set. |
| |
| ? 0 1 1 : ? : - ; // clock disabled. |
| |
| 1 1 x 1 : ? : 1 ; // pessimism |
| 1 ? x 1 : 1 : 1 ; // pessimism |
| ? 0 x 1 : 1 : 1 ; // pessimism |
| |
| ? n 1 1 : ? : - ; |
| |
| endtable |
| |
| endprimitive |
| primitive U_DL_P_SB_SLEEPB_TMAX ( Q, D, G, SB, SLEEPB ); |
| |
| output Q; |
| reg Q; |
| input D, |
| G, |
| SB, |
| SLEEPB; |
| |
| // FUNCTION : POSITIVE LEVEL SENSITIVE D-TYPE LATCH WITH ACTIVE LOW |
| // ASYNCHRONOUS SET ( Q OUTPUT UDP ). |
| |
| table |
| // D G SB SLEEPB : Qt : Qt+1 |
| |
| ? ? ? 0 : ? : x ; // Retain state during sleep |
| |
| 1 1 1 1 : ? : 1 ; // clock enabled transparent data. |
| 0 1 1 1 : ? : 0 ; |
| |
| 1 x 1 1 : 1 : 1 ; // possible enabled clock. |
| 0 x 1 1 : 0 : 0 ; |
| |
| ? ? 0 1 : ? : 1 ; // asynchronous set. |
| |
| ? 0 1 1 : ? : - ; // clock disabled. |
| |
| 1 1 x 1 : ? : 1 ; // pessimism |
| 1 ? x 1 : 1 : 1 ; // pessimism |
| ? 0 x 1 : 1 : 1 ; // pessimism |
| |
| ? n 1 1 : ? : - ; |
| |
| endtable |
| |
| endprimitive |
| primitive U_DL_P_SLEEPB (Q, D, G, SLEEPB); |
| // |
| // FUNCTION : DLATCH, GATED STANDARD DRIVE / ACTIVE HIGH ( Q OUTPUT UDP ) |
| // |
| |
| output Q; |
| reg Q; |
| input D, G, SLEEPB; |
| |
| table |
| // D G SLEEPB : Qt : Qt+1 |
| |
| ? ? 0 : ? : - ; // Retain state during sleep |
| * ? 0 : ? : - ; // Retain state during sleep |
| ? 0 * : ? : - ; // Retain state during sleep |
| ? 1 * : ? : x ; // SLEEPB cannot change unless GATE is low |
| ? x * : ? : x ; // SLEEPB cannot change unless GATE is low |
| |
| ? 0 1 : ? : - ; // clock disabled |
| |
| 0 1 1 : ? : 0 ; //clock enabled |
| 1 1 1 : ? : 1 ; //transparent data |
| |
| 1 x 1 : 1 : 1 ; // Reducing pessimism. |
| 0 x 1 : 0 : 0 ; |
| |
| ? n 1 : ? : - ; |
| |
| endtable |
| |
| endprimitive |
| primitive U_DL_P_SLEEPB_TMAX (Q, D, G, SLEEPB); |
| // |
| // FUNCTION : DLATCH, GATED STANDARD DRIVE / ACTIVE HIGH ( Q OUTPUT UDP ) |
| // |
| |
| output Q; |
| reg Q; |
| input D, G, SLEEPB; |
| |
| table |
| // D G SLEEPB : Qt : Qt+1 |
| |
| ? ? 0 : ? : x ; // Retain state during sleep |
| |
| ? 0 1 : ? : - ; // clock disabled |
| |
| 0 1 1 : ? : 0 ; //clock enabled |
| 1 1 1 : ? : 1 ; //transparent data |
| |
| 1 x 1 : 1 : 1 ; // Reducing pessimism. |
| 0 x 1 : 0 : 0 ; |
| |
| ? n 1 : ? : - ; |
| |
| endtable |
| |
| endprimitive |
| primitive U_EDF_P (Q, D, CP, DE); |
| output Q; |
| input D, CP, DE; |
| reg Q; |
| // FUNCTION : POSITIVE EDGE TRIGGERED ENABLED D FLIP-FLOP ( Q OUTPUT UDP ). |
| table |
| |
| // D CP DE : Qt : Qt+1 |
| |
| 0 r 1 : ? : 0 ; // clocked data |
| 1 r 1 : ? : 1 ; // clocked data |
| ? * 0 : ? : - ; // no change when DE disabled |
| * ? 0 : ? : - ; // no change when DE disabled |
| 1 * ? : 1 : 1 ; // reducing pessimism |
| 0 * ? : 0 : 0 ; // reducing pessimism |
| ? f ? : ? : - ; // no change on falling edge |
| * b ? : ? : - ; // no change when D transitions |
| 1 x ? : 1 : 1 ; // reducing pessimism |
| 0 x ? : 0 : 0 ; // reducing pessimism |
| ? b * : ? : - ; // no change when DE transitions |
| ? x 0 : ? : - ; // no change when DE disabled |
| |
| endtable |
| endprimitive |
| primitive U_EDF_P_NO (Q, D, CP , DE, NOTIFIER); |
| output Q; |
| input D, CP, DE, NOTIFIER; |
| reg Q; |
| |
| // FUNCTION : POSITIVE EDGE TRIGGERED ENABLED D FLIP-FLOP ( Q OUTPUT UDP ). |
| |
| |
| table |
| |
| // D CP DE NOTIFIER : Qt : Qt+1 |
| |
| 0 r 1 ? : ? : 0; // clocked data |
| 1 r 1 ? : ? : 1; // clocked data |
| ? * 0 ? : ? : -; // no change when DE disabled |
| * ? 0 ? : ? : -; // no change when DE disabled |
| 1 * ? ? : 1 : 1; // reducing pessimism |
| 0 * ? ? : 0 : 0; // reducing pessimism |
| ? f ? ? : ? : -; // no change on falling edge |
| * b ? ? : ? : -; // no change when D transitions |
| 1 x ? ? : 1 : 1; // reducing pessimism |
| 0 x ? ? : 0 : 0; // reducing pessimism |
| ? b * ? : ? : -; // no change when DE transitions |
| ? x 0 ? : ? : -; // no change when DE disabled |
| ? ? 1 * : ? : x; // any notifier change |
| |
| endtable |
| endprimitive |
| primitive U_MUX_2_1 (X, A0, A1, S); |
| output X; |
| input A0, A1, S; |
| |
| // FUNCTION : TWO TO ONE MULTIPLEXER |
| |
| table |
| // A0 A1 S : X |
| 0 0 ? : 0 ; |
| 1 1 ? : 1 ; |
| |
| 0 ? 0 : 0 ; |
| 1 ? 0 : 1 ; |
| |
| ? 0 1 : 0 ; |
| ? 1 1 : 1 ; |
| |
| endtable |
| endprimitive |
| primitive U_MUX_2_1_INV (Y, A0, A1, S); |
| |
| input A0, A1, S; |
| output Y; |
| |
| // FUNCTION : TWO TO ONE MULTIPLEXER WITH INVERTING OUTPUT |
| |
| table |
| // A0 A1 S : Y |
| |
| 0 ? 0 : 1 ; |
| 1 ? 0 : 0 ; |
| |
| ? 0 1 : 1 ; |
| ? 1 1 : 0 ; |
| |
| 0 0 ? : 1 ; |
| 1 1 ? : 0 ; |
| |
| endtable |
| endprimitive |
| primitive U_MUX_4_2 (X, A0, A1, A2, A3, S0, S1); |
| |
| input A0, A1, A2, A3, S0, S1; |
| output X; |
| |
| // FUNCTION : FOUR TO ONE MULTIPLEXER WITH 2 SELECT CONTROLS |
| |
| table |
| |
| // A0 A1 A2 A3 S0 S1 : X |
| |
| 0 ? ? ? 0 0 : 0 ; |
| 1 ? ? ? 0 0 : 1 ; |
| |
| ? 0 ? ? 1 0 : 0 ; |
| ? 1 ? ? 1 0 : 1 ; |
| |
| ? ? 0 ? 0 1 : 0 ; |
| ? ? 1 ? 0 1 : 1 ; |
| |
| ? ? ? 0 1 1 : 0 ; |
| ? ? ? 1 1 1 : 1 ; |
| |
| |
| 0 0 0 0 ? ? : 0 ; |
| |
| 1 1 1 1 ? ? : 1 ; |
| |
| 0 0 ? ? ? 0 : 0 ; |
| 1 1 ? ? ? 0 : 1 ; |
| |
| ? ? 0 0 ? 1 : 0 ; |
| ? ? 1 1 ? 1 : 1 ; |
| |
| 0 ? 0 ? 0 ? : 0 ; |
| 1 ? 1 ? 0 ? : 1 ; |
| |
| ? 0 ? 0 1 ? : 0 ; |
| ? 1 ? 1 1 ? : 1 ; |
| |
| endtable |
| endprimitive |
| primitive U_MUX_4_2_INV (Y, A0, A1, A2, A3, S0, S1); |
| |
| input A0, A1, A2, A3, S0, S1; |
| output Y; |
| |
| // FUNCTION : FOUR TO ONE MULTIPLEXER WITH 2 SELECT CONTROLS AND INVERTING OUTPUT |
| |
| table |
| |
| // A0 A1 A2 A3 S0 S1 : Y |
| |
| 0 ? ? ? 0 0 : 1 ; |
| 1 ? ? ? 0 0 : 0 ; |
| |
| ? 0 ? ? 1 0 : 1 ; |
| ? 1 ? ? 1 0 : 0 ; |
| |
| ? ? 0 ? 0 1 : 1 ; |
| ? ? 1 ? 0 1 : 0 ; |
| |
| ? ? ? 0 1 1 : 1 ; |
| ? ? ? 1 1 1 : 0 ; |
| |
| |
| 0 0 0 0 ? ? : 1 ; |
| |
| 1 1 1 1 ? ? : 0 ; |
| |
| 0 0 ? ? ? 0 : 1 ; |
| 1 1 ? ? ? 0 : 0 ; |
| |
| ? ? 0 0 ? 1 : 1 ; |
| ? ? 1 1 ? 1 : 0 ; |
| |
| 0 ? 0 ? 0 ? : 1 ; |
| 1 ? 1 ? 0 ? : 0 ; |
| |
| ? 0 ? 0 1 ? : 1 ; |
| ? 1 ? 1 1 ? : 0 ; |
| |
| endtable |
| endprimitive |
