| |
| |
| // ******************************************************** |
| // Copyright (c) 2020 by SkyWater Technology |
| // SkyWater Confidential Information |
| // ******************************************************** |
| |
| //////////////////////////////////////////////////////////////////////////////// |
| // |
| // ========================= |
| // Comments / Update Section |
| // ========================= |
| // |
| // ========== ======== ======================================================== |
| // Date Modifier Notes |
| // ========== ======== ======================================================== |
| // 3/24/2020 JAG New DRC runset |
| // & |
| // RY |
| // 6/17/2020 JAG Corrected message for met2.ENC.2 to read 0.085 (was 0.06) |
| // Updated lonely via/contact code to correct errors |
| // Improved latchup error messages |
| // 6/25/2020 JAG Added layer thkox - v5 is now only a marker layer |
| // and thkox is a mask layer for thick oxide. |
| // Adjusted numerous rules for this change. |
| // 6/29/2020 JAG Changed licon.ENC.6 to use polyi rather than poly to |
| // avoid false flag in HP/HS poly res |
| // Changed pwres.CON.5 to use nw_hole rather than pwell to |
| // avoid false flag in pwres pcell |
| // Changed non-manhatten check on poly to ignore poly in |
| // npn to avoid error |
| // Changed poly.OVL.3 to not flag 5v npn |
| // 6/30/2020 JAG Modified nsdm.ENC.1 to avoid checking the 5v npn's |
| // internal octagonal nsdm |
| // Rewrote v5.SP.1 to remove false flags |
| // 7/09/2020 JAG Updated seal ring rules to accomodate new seal ring pcell |
| // 7/10/2020 JAG Updated pad rules |
| // 7/13/2020 JAG Updated valid pads to include S8 definition for backwards |
| // compatibility |
| // 7/20/2020 RY Revamped the DENMOS and DEPMOS checks |
| // 7/20/2020 JAG Changed definition of pwellSigPadNtr to include ptub |
| // 7/23/2020 JAG Removed old latchup rule numbers from latchup rules |
| // 7/24/2020 JAG Added new lonely via contact checks |
| // 7/26/2020 JAG Finished adding supplemental recommended lonely via rules |
| // Fixed some syntax and spelling issues |
| // Standardized many rules with cap first letter and value |
| // following rule text |
| // 7/29/2020 JAG Converted latchup rules from verbatim to TVF |
| // 7/30/2020 JAG Implemented new floating net rule and removed old |
| // floating layer rules (now based on devices from LVS) |
| // 8/04/2020 JAG Removed redundant "difftap.SP.6" from rule message |
| // Removed "m2.3c" from met2.CON.8 message |
| // Added missing message to latchup.1 |
| // Updated definition of bond pad recognition for stress |
| // checks |
| // 8/07/2020 JAG Removed a debug output statement |
| // 8/12/2020 JAG Updated some via enclosure messages to include "by met" |
| // 8/14/2020 JAG Added rule name back to message at request of layout |
| // design |
| // 8/20/2020 JAG Removed use of areaid/extDrain20 and replaced any usage |
| // with ENID as areaid/extDrain20 was removed from the |
| // tech file as obsolete |
| // Corrected rule v20.ENC.2 to correct spelling error |
| // 8/27/2020 JAG Added 20V net identification |
| // Enhanced net idenification by voltage markers |
| // Added some but not all voltage rules |
| // 9/02/2020 JAG Reverted net identification by enclosed marker |
| // 9/04/2020 JAG Started adding new 20v denmos/depmos rules |
| // 9/10/2020 JAG Removed V20.ENC.2 as it is not needed |
| // Removed pad.CON.2 text pad must have text "plastic" |
| // 9/11/2020 JAG Changed definition of diffHV to use diffi not diff |
| // 9/14/2020 JAG Changed v12.OVL.7 to use polyi and avoid poly inside v12 |
| // Added rule to check that v20 doesn't straddle poly |
| // Changed some pad rules to not false flag probe pads |
| // Changed rule v20.ENC.3 to v20.ENC.2 and rewrote to |
| // check for dnw interact v20 must be covered by v20 |
| // 9/15/2020 JAG Rewrote Hdifftap.WID.3/4 as they were not flagging |
| // testcases |
| // 9/23/2020 JAG Added rules to enforce proper use of areaid/pad_io, |
| // pad_pwr and pad_gnd |
| // Added substrateCut softcheck - sub cut with no ptap |
| // 9/24/2020 JAG Changed lvtn.SP.3 from 0.235 to 0.19 per Xena ticket #282 |
| // 10/12/2020 JAG Added illegal device checks originally coded in the LVS |
| // 10/19/2020 JAG Finished updating and testing illegal device code |
| // 11/05/2020 JAG Revised all Latch-Up checks to new document |
| // Removed dnw not over ptub from ptap definition |
| // 11/13/2020 JAG Updated denmos_20.SP.8 to redefine ptap def for iso nmos |
| // 20v |
| // 11/14/2020 JAG Updated the ILLEGAL DEVICE rules (WIP) up to NMOS |
| // The remainder are in dev |
| // 11/24/2020 JAG Updated Device rules from Device Table |
| // 11/30/2020 JAG Updated latch-up rules |
| // 12/01/2020 JAG Changed via to via1 |
| // |
| // ----- |
| // Q4.02 |
| // ----- |
| // 12/03/2020 JAG Updates for Q4.02: |
| // Changed via to via in relevent places |
| // Changed li1 to li |
| // Changed licon1 to licon |
| // Changed illegal device check for dnsd_pw_nat to allow |
| // thkox |
| // Changed illegal device check for pad to disallow met4 |
| // Changed illegal device check for pnp to allow hvtp |
| // Changed illegal device check for npn to allow ldntm |
| // Changed illegal device check for pwres to allow npn/pnp |
| // Added CON rule to insure npn/pnp are only in allowed |
| // cells |
| // Updated rules to use new layer names |
| // Rewrote li.WID.3 to fix false errors |
| // Updated cap2m.SP.2 as it was flagging cap2m to unrelated |
| // met4 |
| // 12/26/2020 JAG Merged in fill layers with dwg layers |
| // --------------------------------------------------------------------------- |
| // 01/04/2021 JAG Corrected met4_block layer number |
| // Added definition for diff/poly block and added to |
| // predicitive fill so it will NOT generate predictive |
| // poly or diff fill inside respective block layers. |
| // 01/07/2021 JAG Added new checks for LVS_exclude layer |
| // 01/08/2021 RY Revamped the diffTap checks to diff checks to remove the |
| // old tap layer references |
| // 01/11/2021 JAG Renamed HdifHtap rules to diff_v5. |
| // 01/18/2021 JAG Added new fill rules |
| // Updated prune.CON.1 and renamed LVS_exclude.OVL.1 |
| // 01/19/2021 JAG Renamed psd/nsd.ENC.4 to psd/nsd.ENC.3 |
| // 01/20/2021 JAG Removed references to pwelliso and pwell_dg |
| // 01/21/2021 JAG Removed licon.SP.13 as duplicate of licon.SP.11 |
| // 01/22/2021 JAG Updated cap/cap2m to prohibit L-shaped capm/cap2m |
| // (modified capm.CON.5 & cap2m.CON.4) |
| // 01/25/2021 JAG Added rule pwbm.OVL.1 |
| // Added rules met2.AR.2 and met1.AR.2 |
| // 01/28/2021 JAG Added urpm.ANG.3 |
| // 02/01/2021 JAG Modified licon.ANG.1 as it referenced li not licon in msg |
| // and changed name from licon_not_seal.ANG.1 to licon.ANG.1 |
| // Removed fuse.CON.4 (check of tap over target as it is checked for diff already) |
| // Changed fuse.SP.1 spacing from 3.295 to 2.75 |
| // 02/03/2021 JAG Added pad.SP.6 and pad.AR.1 |
| // Added v5.OVL.12 |
| // 02/05/2021 JAG Combined rules metx.SP.2a and metxSP.2b into metx.SP.2 |
| // for met1-met4 |
| // 02/09/2021 JAG Renamed all DRC checks with "OVLP" to "OVL" such as: |
| // rule_name.OVLP.num to rule_name.OVL.num |
| // to standardize |
| // Removed rule PAD.AR.1 per Pete and Sam |
| // 02/26/2021 JAG Changed instances of "inside core" or "in core" to areaid:core |
| // Changed instances of "inside seal" or "in seal" to areaid:seal |
| // 03/02/2021 JAG Updated the pad rules to account for Pcell change in |
| // areaid:padLength rect. |
| // 03/02/2021 JAG Renamed rule met2.CON.8 to met2.ANT.2 and moved to antenna |
| // section as a recommended antenna rule. Also inverted the |
| // ratios to improve readibility. |
| // 03/08/2021 JAG Corrected pad.SP.11 as it was checking met1 under pad which |
| // was cut by met1/res - changed to check met1 input |
| // Changed diff_5v definition of hv_diff to be NOT tap |
| // after comparing IO Lib results btw s8 and s130 |
| // Corrected poly res term definition for float checks |
| // 03/09/2021 JAG Rewrote v5.OVL.3 as it was just plain wrong |
| // 03/10/2021 JAG Made same corrections to v12.OVL.3 |
| // Removed rule v5.OVL.3 as it was coded in error. |
| // 03/11/2021 JAG Added poly check for anchor min width |
| // 03/12/2021 JAG Modified two diff_5v rules to remove tap which should not |
| // have been checked after getting false errors in IO Libs |
| // 03/12/2021 JAG Rewrote wide metal spacing checks after consult with SV to verify code |
| // and added a keep layer for wide metal derivation |
| // Renamed metals.WID.stress.1 and created 5 rules as metx_stress.WID.1 |
| // 03/15/2021 JAG Removed thkox from rndiff_v5 rpdiff_v5 illegal device list |
| // Added code to illegal device checks to use areaid names |
| // Combined stress.CON.7 and stress.CON.8 to 1 rule |
| // 03/16/2021 JAG Updated verbiage in messages for stress.SP.1 stress.ENC.2 & stress.CON.9 |
| // Changed viax.viay.stress.CON.1 rules to viax.viay.anchor.CON.2 rules |
| // because it makes more sense as they tested via overlap in anchors |
| // 03/17/2021 JAG Renamed metx.stress.CON.9 to metx.SLOT.CON.9 |
| // 03/18/2021 JAG Removed non-octagonal check for pnp as it is checked to be in pcell |
| // 03/24/2021 JAG Renamed pwbm.OVL.1 as pwbm.ENC.2 after review showed |
| // pwbm.OVL.1 was flagging legal 20v de devices |
| // 03/25/2021 JAG Removed poly endcaps from lonely licon checks |
| // Exempted poly, li, m1-m5 inside text_pcell from |
| // floating net checks |
| // 03/26/2021 JAG Removed checks for poly and diff boundary layer |
| // since these were removed from the tech file |
| // 02/28/2021 JAG Modified poly.SP.7 to only check HP/HP2K res to diff |
| // 03/31/2021 JAG Added missing licon.anchor.SP.1 rule |
| // 04/14/2021 JAG SWT changed device table to allow devices under pad |
| // and other changes (eg met res over other layers) |
| // so created skip_pad, skip_res and skip_dnw to |
| // skip checking some devices and clean up IO Lib. |
| // 04/14/2021 JAG Added nmos_esd to illegal device checks |
| // |
| // ----- |
| // Q5.01 |
| // ----- |
| // |
| // 04/16/2021 JAG Removed old hv checks based on diff:hv marker and put in new |
| // hv checks based on v12 or v20 over diff (src/drn) |
| // 04/20/2021 JAG Removed check npc.ENC.1 per PM |
| // 04/22/2021 JAG Removed core from met1.ENC.1 and 1a |
| // Added licon.SP.13 for poly licon space to diff in core |
| // Added licon.SP.14 licon min space in core |
| // Added licon.CON.12 for core psdm prohibited over poly licon |
| // Added met2.ENC.3 min enclosure of via1 by met2 in core |
| // Changed rule diff_5v.WID.2 to thkox.WID.2 for diff width |
| // inside thkox inside core |
| // Split rule li.WID.1 into two rules li.WID.1/2/3 for |
| // width of li in/out of vpp/core |
| // and moved old li.WID.3 to li.WID.4 |
| // 04/23/2021 JAG Modified v5/v12/v20.CON.9 to include diff in check to |
| // ensure they are over thkox. |
| // Changed via.CON.10 to check all vias and deleted via ring |
| // check in seal ring |
| // Deleted via size in seal ring checks (no via/conts in seal) |
| // Removed construction checks which ensure rings shaped vias |
| // and contacts are only in the seal ring |
| // Renamed npc.ENC.1 as licon.ENC.8 for consistency |
| // 04/28/2021 JAG Exempted LATCHUP.generic.2a/b for areas covered by areaid:ESD |
| // Corrected latchup.misc.4 to removed gates under areaid:ESD |
| // |
| // ----- |
| // Q6.01 |
| // ----- |
| // |
| // 05/03/2021 JAG Updated exemptions for floating metals/poly to include anchor |
| // areas to avoid flagging anchors. |
| // 05/05/2021 JAG Removed nsd in isolated p-substrate from rule latchup.signal.12g |
| // per PM @ SWT |
| // Rewrote latchup.signal.2.1b as it was false flagging the level |
| // shifter design |
| // 05/05/2021 JAG Rewrote latchup.shv.1 based on work done on latchup.signal.2.1b |
| // Changed fill construction checks for non-floating fill to not check |
| // anchor region in the unlikely event that users put in fill layers |
| // rather than drawing layers in for anchors. |
| // 05/10/2021 JAG Modified the v5/v12/v20 nwell derivation to find the highest |
| // voltage marker over an nwell to use it to identify nwell voltage |
| // Added word "WARNING" to nwell of one voltage must not be connected |
| // to nwell of another voltage |
| // 05/17/2021 JAG Removed rule v12.SP.1 NW 12V check for 11.24u per PM |
| // Removed use of DFM commands in pad rules |
| // 05/19/2021 JAG Updated dnwell.CON.2 to check all P+ diff not just P+ src/drns |
| // Added REGION to many ENC checks to improve visibility |
| // 05/20/2021 JAG Removed s8_plowvt exemptions from poly.LEN.1 |
| // Removed M5RDL via pcell exemption from bond pad checks |
| // Removed psoc4*_top exemption from from bond pad checks |
| // Removed tsg5_m_tcg5_top exemption from from bond pad checks |
| // Removed s8hpbtoolkit_dual_rx_2* exemption from from bond pad checks |
| // Removed s8hpbtoolkit_dual_rx_inv* exemption from from bond pad checks |
| // Removed s8bio_top_biocmux_vccio* exemption from from bond pad checks |
| // Removed k2_east_pads_top* & k2_west_pads_top* exemption from from bond pad checks |
| // Removed krypton_io_pframe* & krypton2_toplevel* exemption from from bond pad checks |
| // Removed s8ppscio_top_vca_2*, s8ppscio_top_vcd_2*, s8ppscio_top_vda_2*, |
| // s8ppscio_top_vdd_3*, s8ppscio_top_vssa_2*, s8ppscio_top_vddabuf*, |
| // s8ppscio_top_vio*, s8ppscio_top_vssd_2*, s8ppscio_top_vssio_2*, |
| // s8ppscio_top_vssio_3*, s8ppscio_top_vssio_2*, s8tsg4io_top_vssd_2, |
| // s8ppscio_top_vssabuf*, s8ppscio_top_vusb_2 exemption from from bond pad checks |
| // Removed s8esdg4_net_io_b*, s8ppscio_top_vcd_2*, s8ppscio_top_vdd_2*, |
| // s8tsg4io_top_vio*, s8tsg4io_top_vssio_2*, s8tkm0s8_corner_tp2 |
| // exemption from from bond pad checks |
| // Removed exemptions for s8cell_ee_plus_sseln_a, s8cell_ee_plus_sseln_b, |
| // s8cell_ee_plus_sselp_a, s8cell_ee_plus_sselp_b & s8fpls_pl8 s8fs_cmux4_fm |
| // from met1.ENC.1 |
| // REMOVED s8usbpdv2_csa_top, s8usbpdv2_20vconn_sw_300ma_ovp_ngate_unit |
| // s8usbpdv2_20vconn_sw_300ma_ovp, s8usbpdv2_20sbu_sw_300ma_ovp cell |
| // exemptions from rpm rules |
| // Check coreID.CON.1 needs to be revamped when memory is supported (no change) |
| // 05/23/2021 JAG Updated gate definition for lvtn.ENC.1 |
| // 05/26/2021 JAG Corrected message for ubm.SP.2 (had value for ubm.SP.1) but check was OK |
| // 06/08/2021 JAG Added ptap.FL.1 and ntap.FL.1 to check for p+ tap or n+ tap which is |
| // not connected to a pad to RECOMMENDED rules |
| // 06/14/2021 JAG Fixed issue in latchup where m4 was shorting through caps to m3 and m5 was |
| // shorting through caps to m4. |
| // 06/16/2021 JAG Tightened slot definitions for stress using the following assumptions |
| // due to a design with a ptap ring around the entire chip which caused |
| // false metal slotting errors: |
| // 1. a metal hole of interest will have an area < 5000 sq um |
| // 2. a metal slot will have a width < 20.0 um |
| // 06/24/2021 JAG Added warnings for insufficient vias in anchor cells |
| // JAG Commented out fuse rules and implemented two rules to flag polygons on |
| // fuse and target layers |
| // Commented out illegal device fuse checks |
| // 06/25/2021 JAG Exempted rule latchup.signal.12e for n+ diff inside an isolated ptub |
| // Exempted rule latchup.signal.2.1b for dnw tied to gnd with n+ diff inside |
| // tied to ground (back-to-back diodes protecting separate ground supplies) |
| // 06/29/2021 JAG Removed (commented out) the following fuse related rules: diff_fill.CON.2, |
| // diff_fill.SP.3 and LVS_exclude.CON.15 at request of Linda A. |
| // 07/01/2021 JAG Added rule to output any shapes on areaid:NotCritSide - stress.CON.8 |
| // 07/02/2021 JAG Changed rule name of photo.WID.2 to photo.ENC.2 |
| // Changed rule name of lonely.via to lonely.via1 (2 rules) |
| // 07/08/2021 JAG nwell_missing_tap.1 deleted as duplicate of nwell.OVL.1 |
| // dnwell_missing_nwell.1 deleted as duplicate of dnwell.CON.4 |
| // Moved remaining "SOFT" checks to floating checks: |
| // pwell_missing_tap.1 became floating.net.pwell.R |
| // ptub_missing_tap.1 became floating.net.ptub.R |
| // subcut_missing_tap.1 became floating.net.localsub.R |
| // Renamed ptap.FL.1.R as floating.net.ptap.R for consistancy with other float checks |
| // Renamed ntap.FL.1.R as floating.net.ntap.R for consistancy with other float checks |
| // Removed SKIP_SOFT_CONNECT_CHECKS switch as all rules were moved to recommended rules |
| // 07/09/2021 JAG Rewrote hnwell section to NOT use areaid:hvnwell |
| // Removed v5.SP.1 as it was a duplicate of hnwell.SP.1 |
| // Removed hv.nwell.SP.1 as it was a duplicate of hnwell.SP.1 |
| // 07/15/2021 JAG Moved all nwell checks to nwell section (removed hnwell) |
| // 07/21/2021 RY Removed v20.CON.5 as it was a duplicate of v20.CON.2 |
| // |
| // 09/24/2021 JAG changed value from 0.055 to 0.050 for licon.SP.10 per CB and PC |
| //////////////////////////////////////////////////////////////////////////////// |
| |
| // ******************************************************** |
| // Begin control statements |
| // ******************************************************** |
| input_scale 1000 |
| |
| unit -length u |
| |
| incr_conn YES |
| |
| max_results -drc -all |
| |
| // Tolerance for round-off errors on skew edges |
| tolerance 0.001 |
| |
| // ******************************************************** |
| // End control statements |
| // ******************************************************** |
| |
| // ******************************************************** |
| // Begin layer definitions |
| // ******************************************************** |
| |
| layer_def nwell 1000 |
| layer_map 64 -datatype 20 1000 // nwell drawing |
| |
| layer_def tunm 1001 |
| layer_map 80 -datatype 20 1001 // tunm drawing |
| |
| layer_def diffii 1002 |
| layer_map 65 -datatype 20 1002 // diff drawing |
| |
| layer_def polyii 1003 |
| layer_map 66 -datatype 20 1003 // poly drawing |
| |
| layer_def lvtn 1004 |
| layer_map 125 -datatype 44 1004 // lvtn drawing |
| |
| layer_def hvtp 1005 |
| layer_map 78 -datatype 44 1005 // hvtp drawing |
| |
| layer_def npc 1006 |
| layer_map 95 -datatype 20 1006 // npc drawing |
| |
| layer_def nsdm 1007 |
| layer_map 93 -datatype 44 1007 // nsdm drawing |
| |
| layer_def psdm 1008 |
| layer_map 94 -datatype 20 1008 // psdm drawing |
| |
| layer_def mcon 1009 |
| layer_map 67 -datatype 44 1009 // mcon drawing |
| |
| layer_def met1ii 1010 |
| layer_map 68 -datatype 20 1010 // met1 drawing |
| |
| layer_def m1res 1011 |
| layer_map 68 -datatype 13 1011 // met1 res |
| |
| layer_def via1 1012 |
| layer_map 68 -datatype 44 1012 // via1 drawing |
| |
| layer_def met2ii 1013 |
| layer_map 69 -datatype 20 1013 // met2 drawing |
| |
| layer_def m2res 1014 |
| layer_map 69 -datatype 13 1014 // met2 res |
| |
| layer_def via2 1015 |
| layer_map 69 -datatype 44 1015 // via2 drawing |
| |
| layer_def met3ii 1016 |
| layer_map 70 -datatype 20 1016 // met3 drawing |
| |
| layer_def m3res 1017 |
| layer_map 70 -datatype 13 1017 // met3 res |
| |
| layer_def via3 1018 |
| layer_map 70 -datatype 44 1018 // via3 drawing |
| |
| layer_def met4ii 1019 |
| layer_map 71 -datatype 20 1019 // met4 drawing |
| |
| layer_def m4res 1020 |
| layer_map 71 -datatype 13 1020 // met4 res |
| |
| layer_def via4 1021 |
| layer_map 71 -datatype 44 1021 // via4 drawing |
| |
| layer_def met5ii 1022 |
| layer_map 72 -datatype 20 1022 // met5 drawing |
| |
| layer_def m5res 1023 |
| layer_map 72 -datatype 13 1023 // met5 res |
| |
| layer_def pad 1024 |
| layer_map 76 -datatype 20 1024 // pad drawing |
| |
| layer_def licon 1025 |
| layer_map 66 -datatype 44 1025 // licon drawing |
| |
| layer_def li_ii 1026 |
| layer_map 67 -datatype 20 1026 // li drawing |
| |
| layer_def pnp 1028 |
| layer_map 82 -datatype 44 1028 // pnp drawing |
| |
| layer_def npn 1029 |
| layer_map 82 -datatype 20 1029 // npn drawing |
| |
| layer_def v5 1030 |
| layer_map 75 -datatype 20 1030 // hvi drawing |
| |
| layer_def ldntm 1031 |
| layer_map 11 -datatype 44 1031 // ldntm drawing |
| |
| layer_def capacitor 1032 |
| layer_map 82 -datatype 64 1032 // capacitor drawing |
| |
| layer_def ncm 1033 |
| layer_map 92 -datatype 44 1033 // ncm drawing |
| |
| layer_def rdl 1034 |
| layer_map 74 -datatype 20 1034 // rdl drawing |
| |
| layer_def rpm 1035 |
| layer_map 86 -datatype 20 1035 // rpm drawing |
| |
| layer_def inductor 1036 |
| layer_map 82 -datatype 24 1036 // inductor drawing |
| |
| layer_def pmm 1037 |
| layer_map 85 -datatype 44 1037 // pmm drawing |
| |
| layer_def ubm 1038 |
| layer_map 127 -datatype 21 1038 // ubm drawing |
| |
| layer_def bump 1039 |
| layer_map 127 -datatype 22 1039 // bump drawing |
| |
| layer_def cviam 1040 |
| layer_map 105 -datatype 20 1040 // cviam drawing |
| |
| layer_def cmm1 1041 |
| layer_map 62 -datatype 20 1041 // cmm1 drawing |
| |
| layer_def cmm2 1042 |
| layer_map 105 -datatype 44 1042 // cmm2 drawing |
| |
| layer_def cmm3 1043 |
| layer_map 107 -datatype 20 1043 // cmm3 drawing |
| |
| layer_def metop1 1044 |
| layer_map 70 -datatype 32 1044 // met3 option1 |
| |
| layer_def metop2 1045 |
| layer_map 70 -datatype 33 1045 // met3 option2 |
| |
| layer_def metop3 1046 |
| layer_map 70 -datatype 34 1046 // met3 option3 |
| |
| layer_def metop4 1047 |
| layer_map 70 -datatype 35 1047 // met3 option4 |
| |
| layer_def metop5 1048 |
| layer_map 70 -datatype 36 1048 // met3 option5 |
| |
| layer_def metop6 1049 |
| layer_map 70 -datatype 37 1049 // met3 option6 |
| |
| layer_def metop7 1050 |
| layer_map 70 -datatype 38 1050 // met3 option7 |
| |
| layer_def metop8 1051 |
| layer_map 70 -datatype 39 1051 // met3 option8 |
| |
| layer_def dnwell 1052 |
| layer_map 64 -datatype 18 1052 // dnwell drawing |
| |
| layer_def DiodeID 1053 |
| layer_map 81 -datatype 23 1053 // areaid diode |
| |
| layer_def ESDID 1054 |
| layer_map 81 -datatype 19 1054 // areaid esd |
| |
| layer_def ENID 1055 |
| layer_map 81 -datatype 57 1055 // areaid extendedDrain |
| |
| layer_def COREID 1056 |
| layer_map 81 -datatype 2 1056 // areaid core |
| |
| layer_def SEALID 1057 |
| layer_map 81 -datatype 1 1057 // areaid seal |
| |
| layer_def FRAMEID 1058 |
| layer_map 81 -datatype 3 1058 // areaid frame |
| |
| layer_def LVID 1059 |
| layer_map 81 -datatype 60 1059 // areaid lvNative |
| |
| layer_def STDCID 1060 |
| layer_map 81 -datatype 4 1060 // areaid standardc |
| |
| layer_def localSub 1061 |
| layer_map 81 -datatype 53 1061 // areaid substrateCut |
| |
| layer_def PHdiodeID 1062 |
| layer_map 81 -datatype 81 1062 // areaid photo |
| |
| layer_def diffRes 1063 |
| layer_map 65 -datatype 13 1063 // diff res |
| |
| layer_def fuse 1064 |
| layer_map 71 -datatype 17 1064 // met4 fuse |
| |
| //LAYER padCenter 1065 |
| // LAYER MAP 81 DATATYPE 20 1065 // padCenter drawing |
| |
| //LAYER prune 1066 |
| // LAYER MAP 84 DATATYPE 44 1066 // prune drawing |
| |
| layer_def polyres 1067 |
| layer_map 66 -datatype 13 1067 // poly res |
| |
| layer_def lires 1068 |
| layer_map 67 -datatype 13 1068 // li res |
| |
| layer_def pwres 1069 |
| layer_map 64 -datatype 13 1069 // pwell res |
| |
| layer_def clvom 1070 |
| layer_map 45 -datatype 20 1070 // clvom drawing |
| |
| layer_def cntm 1071 |
| layer_map 26 -datatype 20 1071 // cntm drawing |
| |
| layer_def chvntm 1072 |
| layer_map 38 -datatype 20 1072 // chvntm drawing |
| |
| layer_def cnpc 1073 |
| layer_map 44 -datatype 20 1073 // cnpc drawing |
| |
| layer_def cnsdm 1074 |
| layer_map 29 -datatype 20 1074 // cnsdm drawing |
| |
| layer_def cpsdm 1075 |
| layer_map 31 -datatype 20 1075 // cpsdm drawing |
| |
| layer_def cli1m 1076 |
| layer_map 115 -datatype 44 1076 // cli1m drawing |
| |
| layer_def cviam3 1077 |
| layer_map 112 -datatype 20 1077 // cviam3 drawing |
| |
| layer_def cviam4 1078 |
| layer_map 117 -datatype 20 1078 // cviam4 drawing |
| |
| layer_def pmm2 1079 |
| layer_map 77 -datatype 20 1079 // pmm2 drawing |
| |
| layer_def conom 1080 |
| layer_map 87 -datatype 44 1080 // conom drawing |
| |
| layer_def chvtpm 1081 |
| layer_map 88 -datatype 44 1081 // chvtpm drawing |
| |
| layer_def clvtnm 1082 |
| layer_map 25 -datatype 44 1082 |
| |
| layer_def cfom 1083 |
| layer_map 22 -datatype 20 1083 |
| |
| layer_def hvtr 1084 |
| layer_map 18 -datatype 20 1084 |
| |
| layer_def hvntm 1085 |
| layer_map 125 -datatype 20 1085 |
| |
| layer_def nsm 1086 |
| layer_map 61 -datatype 20 1086 |
| |
| layer_def padtt 1087 1088 |
| layer_map 76 -texttype 20 1087 // pad drawing |
| layer_map 76 -texttype 5 1088 // pad label |
| |
| layer_def rdltt 1089 1090 |
| layer_map 74 -texttype 20 1089 // rdl drawing |
| layer_map 74 -texttype 5 1090 // rdl label |
| |
| layer_def met5tt 1091 |
| layer_map 72 -texttype 5 1091 // met5 label |
| |
| layer_def met4tt 1092 |
| layer_map 71 -texttype 5 1092 // met4 label |
| |
| layer_def met3tt 1093 |
| layer_map 70 -texttype 5 1093 // met3 label |
| |
| layer_def met2tt 1094 |
| layer_map 69 -texttype 5 1094 // met2 label |
| |
| layer_def met1tt 1095 |
| layer_map 68 -texttype 5 1095 // met1 label |
| |
| layer_def litt 1096 |
| layer_map 67 -texttype 5 1096 // li label |
| |
| layer_def polytt 1097 |
| layer_map 66 -texttype 5 1097 // poly label |
| |
| layer_def difftt 1098 |
| layer_map 65 -texttype 6 1098 // diff label |
| |
| layer_def pwelltt 1099 |
| layer_map 64 -texttype 59 1099 // pwell label |
| |
| //LAYER pwellisott 1100 |
| // LAYER MAP 44 TEXTTYPE 5 1100 // pwelliso label |
| |
| layer_def nwelltt 1101 |
| layer_map 64 -texttype 5 1101 // nwell label |
| |
| layer_def textdraw 1102 |
| layer_map 83 -texttype 44 1102 // text drawing |
| |
| layer_def pwell_pin 1103 |
| layer_map 122 -datatype 16 1103 // pwell pin |
| |
| //LAYER pwelliso_pin 1104 |
| // LAYER MAP 44 DATATYPE 16 1104 // pwelliso pin |
| |
| layer_def nwell_pin 1105 |
| layer_map 64 -datatype 16 1105 // nwell pin |
| |
| layer_def diff_pin 1106 |
| layer_map 65 -datatype 16 1106 // diff pin |
| |
| layer_def poly_pin 1107 |
| layer_map 66 -datatype 16 1107 // poly pin |
| |
| layer_def li_pin 1108 |
| layer_map 67 -datatype 16 1108 // li pin |
| |
| layer_def met1_pin 1109 |
| layer_map 68 -datatype 16 1109 // met1 pin |
| |
| layer_def met2_pin 1110 |
| layer_map 69 -datatype 16 1110 // met2 pin |
| |
| layer_def met3_pin 1111 |
| layer_map 70 -datatype 16 1111 // met3 pin |
| |
| layer_def met4_pin 1112 |
| layer_map 71 -datatype 16 1112 // met4 pin |
| |
| layer_def met5_pin 1113 |
| layer_map 72 -datatype 16 1113 // met5 pin |
| |
| layer_def rdl_pin 1114 |
| layer_map 74 -datatype 16 1114 // rdl pin |
| |
| layer_def pad_pin 1115 |
| layer_map 76 -datatype 16 1115 // pad pin |
| |
| layer_def pwellpt 1116 |
| layer_map 122 -texttype 16 1116 // pwell pin |
| layer_map 122 -texttype 0 1116 // pwell pin |
| |
| //LAYER pwellisopt 1117 |
| // LAYER MAP 44 TEXTTYPE 16 1117 // pwelliso pin |
| // LAYER MAP 44 TEXTTYPE 0 1117 // pwelliso pin |
| |
| layer_def nwellpt 1118 |
| layer_map 64 -texttype 16 1118 // nwell pin |
| layer_map 64 -texttype 0 1118 // nwell pin |
| |
| layer_def diffpt 1119 |
| layer_map 65 -texttype 16 1119 // diff pin |
| layer_map 65 -texttype 0 1119 // diff pin |
| |
| layer_def polypt 1120 |
| layer_map 66 -texttype 16 1120 // poly pin |
| layer_map 66 -texttype 0 1120 // poly pin |
| |
| layer_def lipt 1121 |
| layer_map 67 -texttype 16 1121 // li pin |
| layer_map 67 -texttype 0 1121 // li pin |
| |
| layer_def met1pt 1122 |
| layer_map 68 -texttype 16 1122 // met1 pin |
| layer_map 68 -texttype 0 1122 // met1 pin |
| |
| layer_def met2pt 1123 |
| layer_map 69 -texttype 16 1123 // met2 pin |
| layer_map 69 -texttype 0 1123 // met2 pin |
| |
| layer_def met3pt 1124 |
| layer_map 70 -texttype 16 1124 // met3 pin |
| layer_map 70 -texttype 0 1124 // met3 pin |
| |
| layer_def met4pt 1125 |
| layer_map 71 -texttype 16 1125 // met4 pin |
| layer_map 71 -texttype 0 1125 // met4 pin |
| |
| layer_def met5pt 1126 |
| layer_map 72 -texttype 16 1126 // met5 pin |
| layer_map 72 -texttype 0 1126 // met5 pin |
| |
| layer_def rdlpt 1127 |
| layer_map 74 -texttype 16 1127 // rdl pin |
| layer_map 74 -texttype 0 1127 // rdl pin |
| |
| layer_def padpt 1128 |
| layer_map 76 -texttype 16 1128 // pad pin |
| layer_map 76 -texttype 0 1128 // pad pin |
| |
| layer_def met5probe 1129 |
| layer_map 72 -texttype 25 1129 // met5 probe |
| |
| layer_def met4probe 1130 |
| layer_map 71 -texttype 25 1130 // met4 probe |
| |
| layer_def met3probe 1131 |
| layer_map 70 -texttype 25 1131 // met3 probe |
| |
| layer_def met2probe 1132 |
| layer_map 69 -texttype 25 1132 // met2 probe |
| |
| layer_def met1probe 1133 |
| layer_map 68 -texttype 25 1133 // met1 probe |
| |
| layer_def liprobe 1134 |
| layer_map 67 -texttype 25 1134 // li probe |
| |
| layer_def polyprobe 1135 |
| layer_map 66 -texttype 25 1135 // poly probe |
| |
| layer_def fomWaffDrop 1136 |
| layer_map 22 -datatype 24 1136 // cfom waffleDrop |
| |
| layer_def moduleCutAREA 1137 |
| layer_map 81 -datatype 10 1137 // areaid moduleCut |
| |
| layer_def indLabel 1138 |
| layer_map 82 -texttype 25 1138 // inductor label |
| |
| layer_def indTerm1 1139 |
| layer_map 82 -datatype 26 1139 // inductor term1 |
| |
| layer_def indTerm2 1140 |
| layer_map 82 -datatype 27 1140 // inductor term2 |
| |
| layer_def indTerm3 1141 |
| layer_map 82 -datatype 28 1141 // inductor term3 |
| |
| layer_def capm 1142 |
| layer_map 89 -datatype 44 1142 // capm drawing |
| |
| layer_def cap2m 1143 |
| layer_map 97 -datatype 44 1143 // cap2m drawing |
| |
| layer_def urpm 1144 |
| layer_map 79 -datatype 20 1144 // urpm drawing |
| |
| //LAYER EXTDRAIN20 1145 |
| // LAYER MAP 81 DATATYPE 58 1145 // extd20v drawing |
| |
| layer_def pwbm 1146 |
| layer_map 19 -datatype 44 1146 // pwbm drawing |
| |
| layer_def pwde 1147 |
| layer_map 124 -datatype 20 1147 // pwbm drawing |
| |
| layer_def LOWVTID 1148 |
| layer_map 81 -datatype 108 1148 // areaid low_vt drawing |
| |
| layer_def v20 1149 |
| layer_map 74 -datatype 22 1149 // uhvi drawing |
| |
| layer_def v12 1150 |
| layer_map 74 -datatype 21 1150 // vhvi drawing |
| |
| layer_def LVTNMdg 1151 |
| // 1151 -> clvtnm drawing |
| |
| layer_def HVTPMdg 1152 |
| // 1152 -> chvtpm drawing |
| |
| layer_def HVNTMdg 1153 |
| // 1153 -> chvntm drawing |
| |
| //LAYER NTMdg 1154 |
| // 1154 -> cntm drawing |
| |
| layer_def NTMdrop 1155 |
| layer_map 26 -datatype 22 1155 // cntm maskDrop |
| |
| layer_def LVTNMdrop 1156 |
| layer_map 25 -datatype 42 1156 // clvtnm maskDrop |
| |
| layer_def HVTPMdrop 1157 |
| layer_map 97 -datatype 42 1157 // chvtpm maskDrop |
| |
| layer_def LI1Mdrop 1158 |
| layer_map 115 -datatype 42 1158 // cli1m maskDrop |
| |
| layer_def LICM1drop 1159 |
| layer_map 106 -datatype 42 1159 // clicm1 maskDrop |
| |
| layer_def PSDMdrop 1160 |
| layer_map 31 -datatype 22 1160 // cpsdm maskDrop |
| |
| layer_def NSDMdrop 1161 |
| layer_map 29 -datatype 22 1161 // cnsdm maskDrop |
| |
| layer_def P1Mdrop 1162 |
| layer_map 33 -datatype 42 1162 // cp1m maskDrop |
| |
| layer_def FOMdrop 1163 |
| layer_map 22 -datatype 22 1163 // cfom maskDrop |
| |
| layer_def NTMadd 1164 |
| layer_map 26 -datatype 21 1164 // cntm maskAdd |
| |
| layer_def LVTNMadd 1165 |
| layer_map 25 -datatype 43 1165 // clvtnm maskAdd |
| |
| layer_def HVTPMadd 1166 |
| layer_map 97 -datatype 43 1166 // chvtpm maskAdd |
| |
| layer_def LI1Madd 1167 |
| layer_map 115 -datatype 43 1167 // cli1m maskAdd |
| |
| layer_def LICM1add 1168 |
| layer_map 106 -datatype 43 1168 // clicm1 maskAdd |
| |
| layer_def PSDMadd 1169 |
| layer_map 31 -datatype 21 1169 // cpsdm maskAdd |
| |
| layer_def NSDMadd 1170 |
| layer_map 29 -datatype 21 1170 // cnsdm maskAdd |
| |
| layer_def P1Madd 1171 |
| layer_map 33 -datatype 43 1171 // cp1m maskAdd |
| |
| layer_def FOMadd 1172 |
| layer_map 22 -datatype 21 1172 // cfom maskAdd |
| |
| layer_def PMM2mk 1173 |
| layer_map 94 -datatype 0 1173 // cpmm2 mask |
| |
| layer_def CU1Mmk 1174 |
| layer_map 93 -datatype 0 1174 // ccu1m mask |
| |
| layer_def RPMmk 1175 |
| layer_map 96 -datatype 0 1175 // crpm mask |
| |
| layer_def PBOmk 1176 |
| layer_map 99 -datatype 0 1176 // cpbo mask |
| |
| layer_def PDMmk 1177 |
| layer_map 37 -datatype 0 1177 // cpdm mask |
| |
| layer_def NSMmk 1178 |
| layer_map 22 -datatype 0 1178 // cnsm mask |
| |
| layer_def MM5mk 1179 |
| layer_map 59 -datatype 0 1179 // cmm5 mask |
| |
| layer_def VIM4mk 1180 |
| layer_map 58 -datatype 0 1180 // cviam4 mask |
| |
| layer_def MM4mk 1181 |
| layer_map 51 -datatype 0 1181 // cmm4 mask |
| |
| layer_def VIM3mk 1182 |
| layer_map 50 -datatype 0 1182 // cviam3 mask |
| |
| layer_def MM3mk 1183 |
| layer_map 34 -datatype 0 1183 // cmm3 mask |
| |
| layer_def VIM2mk 1184 |
| layer_map 44 -datatype 0 1184 // cviam2 mask |
| |
| layer_def MM2mk 1185 |
| layer_map 41 -datatype 0 1185 // cmm2 mask |
| |
| layer_def VIMmk 1186 |
| layer_map 40 -datatype 0 1186 // cviam mask |
| |
| layer_def MM1mk 1187 |
| layer_map 36 -datatype 0 1187 // cmm1 mask |
| |
| layer_def CTM1mk 1188 |
| layer_map 35 -datatype 0 1188 // cctm1 mask |
| |
| layer_def LI1Mmk 1189 |
| layer_map 56 -datatype 0 1189 // cli1m mask |
| |
| layer_def LICM1mk 1190 |
| layer_map 43 -datatype 0 1190 // clicm1 mask |
| |
| layer_def PSDMmk 1191 |
| layer_map 32 -datatype 0 1191 // cpsdm mask |
| |
| layer_def NSDMmk 1192 |
| layer_map 30 -datatype 0 1192 // cnsdm mask |
| |
| layer_def LDNTMmk 1193 |
| layer_map 11 -datatype 0 1193 // cldntm mask |
| |
| layer_def NPCMmk 1194 |
| layer_map 49 -datatype 0 1194 // cnpc mask |
| |
| layer_def HVNTMmk 1195 |
| layer_map 39 -datatype 0 1195 // chvntm mask |
| |
| layer_def NTMmk 1196 |
| layer_map 27 -datatype 0 1196 // cntm mask |
| |
| layer_def P1Mmk 1197 |
| layer_map 28 -datatype 0 1197 // cp1m mask |
| |
| layer_def LVOMmk 1198 |
| layer_map 46 -datatype 0 1198 // clvom mask |
| |
| layer_def ONOMmk 1199 |
| layer_map 88 -datatype 0 1199 // conom mask |
| |
| layer_def TUNMmk 1200 |
| layer_map 20 -datatype 0 1200 // ctunm mask |
| |
| layer_def HVTRMmk 1201 |
| layer_map 98 -datatype 0 1201 // chvtrm mask |
| |
| layer_def HVTPMmk 1202 |
| layer_map 97 -datatype 0 1202 // chvtpm mask |
| |
| layer_def LVTNMmk 1203 |
| layer_map 25 -datatype 0 1203 // clvtnm mask |
| |
| layer_def NWMmk 1204 |
| layer_map 21 -datatype 0 1204 // cnwm mask |
| |
| layer_def DNMmk 1205 |
| layer_map 48 -datatype 0 1205 // cdnm mask |
| |
| layer_def FOMmk 1206 |
| layer_map 23 -datatype 0 1206 // cfom mask |
| |
| layer_def met5Pin 1207 // met5 pin |
| layer_map 72 -datatype 16 1207 // met5 pin |
| |
| layer_def met4Pin 1208 // met4 pin |
| layer_map 71 -datatype 16 1208 // met4 pin |
| |
| layer_def met3Pin 1209 // met3 pin |
| layer_map 70 -datatype 16 1209 // met3 pin |
| |
| layer_def met2Pin 1210 // met2 pin |
| layer_map 69 -datatype 16 1210 // met2 pin |
| |
| layer_def met1Pin 1211 // met1 pin |
| layer_map 68 -datatype 16 1211 // met1 pin |
| |
| layer_def liPin 1212 // li pin |
| layer_map 67 -datatype 16 1212 // li pin |
| |
| layer_def polyPin 1213 // poly pin |
| layer_map 66 -datatype 16 1213 // poly pin |
| |
| layer_def diffPin 1214 // diff pin |
| layer_map 65 -datatype 16 1214 // diff pin |
| |
| layer_def cmm4WaffleDrop 1215 |
| layer_map 112 -datatype 4 1215 // cmm4 waffleDrop |
| |
| layer_def cmm3WaffleDrop 1216 |
| layer_map 107 -datatype 24 1216 // cmm3 waffleDrop |
| |
| layer_def cmm2WaffleDrop 1217 |
| layer_map 105 -datatype 52 1217 // cmm2 waffleDrop |
| |
| layer_def cmm1WaffleDrop 1218 |
| layer_map 62 -datatype 24 1218 // cmm1 waffleDrop |
| |
| layer_def cp1mWaffleDrop 1219 |
| layer_map 33 -datatype 24 1219 // cp1m waffleDrop |
| |
| layer_def cfomWaffleDrop 1220 |
| layer_map 22 -datatype 24 1220 // cfom waffleDrop |
| |
| layer_def pwellLabel 1221 |
| layer_map 64 -datatype 5 1221 // pwell label |
| |
| //LAYER fomDummyDRC 1222 |
| // LAYER MAP 22 DATATYPE 23 1222 // fom dummy |
| |
| layer_def viatop 1224 |
| layer_map 203 -datatype 2 1224 // viatop drawing |
| |
| layer_def ccorner 1225 |
| layer_map 81 -datatype 51 1225 // areaid critCorner |
| |
| layer_def critside 1226 |
| layer_map 81 -datatype 52 1226 // areaid critSid |
| |
| layer_def ANALOGID 1227 |
| layer_map 81 -datatype 79 1227 // areaid analog |
| |
| //LAYER pwell_dg 1228 // pwell drawing |
| // LAYER MAP 64 DATATYPE 44 1228 |
| |
| layer_def dieCut 1229 // areaid dieCut |
| layer_map 81 -datatype 11 1229 |
| |
| layer_def frameBndr 1230 |
| layer_map 81 -datatype 12 1230 // areaid frameRect |
| |
| layer_def padText 1231 |
| layer_map 76 -texttype 5 1231 // pad label |
| |
| layer_def ETESTID 1232 |
| layer_map 81 -datatype 101 1232 // areaid etest |
| |
| layer_def ccapm 1233 |
| layer_map 89 -datatype 45 1233 // capm mask |
| |
| layer_def target 1234 |
| layer_map 76 -datatype 44 1234 // capm mask |
| |
| layer_def HVNID 1235 |
| layer_map 81 -datatype 63 1235 // areaid hvnwell |
| |
| layer_def met1_block 1236 |
| layer_map 68 -datatype 10 1236 // metal1 blockage |
| |
| layer_def met2_block 1237 |
| layer_map 69 -datatype 10 1237 // metal2 blockage |
| |
| layer_def met3_block 1238 |
| layer_map 70 -datatype 10 1238 // metal3 blockage |
| |
| layer_def met4_block 1239 |
| layer_map 71 -datatype 10 1239 // metal4 blockage |
| |
| layer_def met5_block 1240 |
| layer_map 72 -datatype 10 1240 // metal5 blockage |
| |
| layer_def li_block 1241 |
| layer_map 67 -datatype 10 1241 // li blockage |
| |
| layer_def cmm5WaffleDrop 1242 |
| layer_map 117 -datatype 4 1242 // cmm5 waffleDrop |
| |
| layer_def tap_old 1243 |
| layer_map 65 -datatype 44 1243 // read in layer tap from S8 datatbases |
| |
| layer_def diffhvp 1244 |
| layer_map 65 -datatype 8 1244 // diff hv |
| |
| layer_def polyGate 1245 |
| layer_map 66 -datatype 9 1245 // poly gate |
| |
| layer_def prBndry 1246 |
| layer_map 235 -datatype 4 1246 // prBoundary boundary |
| |
| //LAYER polyBndry 1247 |
| // LAYER MAP 66 DATATYPE 4 1247 // poly boundary |
| |
| //LAYER diffBndry 1248 |
| // LAYER MAP 65 DATATYPE 4 1248 // diff boundary |
| |
| layer_def sigPadMetNtr 1249 |
| layer_map 81 -datatype 8 1249 // areaid sig_pad_met_not_res |
| |
| layer_def sigPadWell 1250 |
| layer_map 81 -datatype 7 1250 // areaid sig_pad_well |
| |
| layer_def sigPadDiff 1251 |
| layer_map 81 -datatype 6 1251 // areaid sig_pad_diff |
| |
| layer_def LTDID 1252 |
| layer_map 81 -datatype 14 1252 // areaid lowTapDensity |
| |
| layer_def NTMdg 1253 // cntm drawing |
| layer_map 26 -datatype 20 1253 |
| |
| layer_def pwcut 1254 // pwell cut |
| layer_map 64 -datatype 14 1254 |
| |
| layer_def deadzoneID 1255 |
| layer_map 81 -datatype 50 1255 // areaid deadZon |
| |
| layer_def notCritSideID 1256 |
| layer_map 81 -datatype 15 1256 // areaid notCritSide |
| |
| layer_def met1Block 1257 |
| layer_map 68 -datatype 10 1257 // met1 blockage |
| |
| layer_def met2Block 1258 |
| layer_map 69 -datatype 10 1258 // met2 blockage |
| |
| layer_def met3Block 1259 |
| layer_map 70 -datatype 10 1259 // met3 blockage |
| |
| layer_def met4Block 1260 |
| layer_map 71 -datatype 10 1260 // met4 blockage |
| |
| layer_def met5Block 1261 |
| layer_map 72 -datatype 10 1261 // met5 blockage |
| |
| layer_def liBlock 1262 |
| layer_map 67 -datatype 10 1262 // li blockage |
| |
| layer_def thkox 1263 |
| layer_map 75 -datatype 21 1263 // thick oxide drawing |
| |
| layer_def pad_length 1264 |
| layer_map 81 -datatype 67 1264 // pad length marker |
| |
| layer_def polyModeltt 1265 |
| layer_map 66 -texttype 83 1265 |
| |
| layer_def pad_io 1266 |
| layer_map 81 -datatype 70 1266 |
| |
| layer_def pad_pwr 1267 |
| layer_map 81 -datatype 71 1267 |
| |
| layer_def pad_gnd 1268 |
| layer_map 81 -datatype 72 1268 |
| |
| layer_def polyModel 1269 |
| layer_map 66 -datatype 83 1269 |
| |
| layer_def rrpm 1270 |
| layer_map 102 -datatype 20 1270 // rrpm drawing |
| |
| layer_def diff_fill 1271 |
| layer_map 65 -datatype 99 1271 // diff fill |
| |
| layer_def poly_fill 1272 |
| layer_map 66 -datatype 99 1272 // poly fill |
| |
| layer_def li_fill 1273 |
| layer_map 67 -datatype 99 1273 // li fill |
| |
| layer_def m1_fill 1274 |
| layer_map 68 -datatype 99 1274 // m1 fill |
| |
| layer_def m2_fill 1275 |
| layer_map 69 -datatype 99 1275 // m2 fill |
| |
| layer_def m3_fill 1276 |
| layer_map 70 -datatype 99 1276 // m3 fill |
| |
| layer_def m4_fill 1277 |
| layer_map 71 -datatype 99 1277 // m4 fill |
| |
| layer_def m5_fill 1278 |
| layer_map 72 -datatype 99 1278 // m5 fill |
| |
| layer_def LVS_exclude 1279 |
| layer_map 84 -datatype 44 1279 // LVS_exclude drawing |
| |
| layer_def poly_block 1280 |
| layer_map 66 -datatype 98 1280 // poly fill block |
| |
| layer_def diff_block 1281 |
| layer_map 65 -datatype 98 1281 // diff fill block |
| |
| extent_drawn -original -outputlayer boundary |
| |
| treat_non_baselayer_as_toplayer yes |
| base_layer diffii polyii pnp npn nsdm psdm thkox v5 v12 v20 lvtn hvtp |
| |
| // ******************************************************** |
| // End layer definitions |
| // ******************************************************** |
| |
| // ******************************************************** |
| // Begin merge of fill layers with design layers |
| // ******************************************************** |
| |
| |
| or diff_fill diffii tap_old -outputlayer diffi |
| or poly_fill polyii -outputlayer polyi |
| or li_fill li_ii -outputlayer li_i |
| or m1_fill met1ii -outputlayer met1i |
| or m2_fill met2ii -outputlayer met2i |
| or m3_fill met3ii -outputlayer met3i |
| or m4_fill met4ii -outputlayer met4i |
| or m5_fill met5ii -outputlayer met5i |
| |
| |
| // ******************************************************** |
| // Begin base logical operations |
| // ******************************************************** |
| |
| |
| extent_cell "*_tech_CD_top*" -outputlayer exempt_tech_CD |
| holes LDNTMmk -outputlayer nikon_1 |
| or LDNTMmk nikon_1 -outputlayer nikon_2 |
| vertex nikon_2 -eq 8 -outputlayer nikon_3 |
| select -enclose nikon_3 ( and ( and ( and VIMmk VIM2mk ) VIM3mk ) VIM4mk ) -outputlayer nikon_cross |
| and dnwell ( select -interact ( or pwbm ( holes pwbm ) ) ENID ) -outputlayer dnwell_touch_pwbm_touch_extd20 |
| not dnwell dnwell_touch_pwbm_touch_extd20 -outputlayer dnwell_not_extended_drain |
| not localSub ( size localSub -by -0.005 ) -outputlayer localSub_not_size_localSub |
| and dnwell_not_extended_drain nwell -outputlayer dnwell_not_dnwell_ext_drain |
| not boundary ( or ( not dnwell_not_extended_drain ( size dnwell_not_extended_drain -by -0.01 ) ) dnwell_not_dnwell_ext_drain ) -outputlayer sub_iso_other |
| not sub_iso_other localSub_not_size_localSub -outputlayer sub_local |
| not sub_local npn -outputlayer substrate_not_npn |
| and pwres dnwell -outputlayer pwellresistor |
| not substrate_not_npn pwellresistor -outputlayer pwell1 |
| select -interact -not ( not ( select -interact dnwell nwell ) nwell ) ENID -outputlayer iso_pw_basic |
| not dnwell nwell -outputlayer dnw_not_nw |
| holes nwell -outputlayer nw_hole |
| not nw_hole nwell -outputlayer nw_hole_not_nw |
| xor nw_hole_not_nw dnw_not_nw -outputlayer nw_hole_outside_dnw |
| select -interact dnw_not_nw nw_hole_outside_dnw -outputlayer dnw_to_remove_iso_pw |
| not iso_pw_basic dnw_to_remove_iso_pw -outputlayer ptub |
| not pwell1 ( or pwbm ptub nwell localSub ) -outputlayer pwell |
| not ( and ( and nsdm diffi ) nwell ) ( and polyi ENID ) -outputlayer ntap |
| not ( not ( not ( and psdm diffi ) nwell ) ( and polyi ENID ) ) ( not dnwell ptub ) -outputlayer ptap |
| or ptap ntap -outputlayer tap |
| not diffi tap -outputlayer diff1 |
| and ( and diffi nwell ) psdm -outputlayer pdiff |
| and ( not diffi nwell ) nsdm -outputlayer ndiff |
| not ( not ( not ( and diffi nsdm ) polyi ) diffres ) ntap -outputlayer nsd |
| not ( not ( not ( and diffi psdm ) polyi ) diffres ) ptap -outputlayer psd |
| and ( and diffi psdm ) ptub -outputlayer ptubtap |
| or tap diff1 -outputlayer diffTap |
| not ( or psd nsd ) polyi -outputlayer srcdrn |
| and srcdrn ndiff -outputlayer nsrcdrn |
| and srcdrn pdiff -outputlayer psrcdrn |
| and polyi diff1 -outputlayer polyAndDiff |
| copy POLYandDIFF -outputlayer gate |
| not gate nwell -outputlayer ngate |
| and gate nwell -outputlayer pgate |
| edge_boolean -inside GATE diff1 -outputlayer gateside |
| edge_boolean -coincident_only -inside GATE diff1 -outputlayer gateend |
| edge_boolean -coincident_only -outside diff1 tap -outputlayer diffTapEdge |
| copy GATE -outputlayer MOSGATE |
| copy MOSGATE -outputlayer EMOSGATE |
| or NDIFF NTAP -outputlayer nDiffTap |
| or PDIFF PTAP -outputlayer pDiffTap |
| not GATE COREID -outputlayer gate_PERI |
| not PDIFF COREID -outputlayer pdiff_PERI |
| and PDIFF COREID -outputlayer pdiff_CORE |
| and NDIFF COREID -outputlayer ndiff_CORE |
| not NDIFF COREID -outputlayer ndiff_PERI |
| not EMOSGATE COREID -outputlayer emosgate_PERI |
| and EMOSGATE COREID -outputlayer emosgate_CORE |
| not polyi COREID -outputlayer poly_PERI |
| and polyi COREID -outputlayer poly_CORE |
| not li_i COREID -outputlayer li1_PERI |
| and li_i COREID -outputlayer li1_CORE |
| not licon COREID -outputlayer licon1_PERI |
| and licon COREID -outputlayer licon1_CORE |
| not diff1 COREID -outputlayer diff_PERI |
| and diff1 COREID -outputlayer diff_CORE |
| not tap COREID -outputlayer tap_PERI |
| and tap COREID -outputlayer tap_CORE |
| and diffTap COREID -outputlayer diffTap_CORE |
| not diffTap COREID -outputlayer diffTap_PERI |
| not mcon COREID -outputlayer mcon_PERI |
| and mcon COREID -outputlayer mcon_CORE |
| not hvtp COREID -outputlayer hvtp_PERI |
| and hvtp COREID -outputlayer hvtp_CORE |
| not lvtn COREID -outputlayer lvtn_PERI |
| and lvtn COREID -outputlayer lvtn_CORE |
| not nsdm COREID -outputlayer nsdm_PERI |
| and nsdm COREID -outputlayer nsdm_CORE |
| not psdm COREID -outputlayer psdm_PERI |
| and psdm COREID -outputlayer psdm_CORE |
| not PTAP COREID -outputlayer PTAP_PERI |
| and PTAP COREID -outputlayer PTAP_CORE |
| not NTAP COREID -outputlayer NTAP_PERI |
| and NTAP COREID -outputlayer NTAP_CORE |
| not via1 COREID -outputlayer via_PERI |
| and via1 COREID -outputlayer via_CORE |
| not via2 COREID -outputlayer via2_PERI |
| and via2 COREID -outputlayer via2_CORE |
| not diff1 diffres -outputlayer diff |
| not polyi polyres -outputlayer poly |
| not li_i lires -outputlayer li |
| not met1i m1res -outputlayer met1 |
| not met2i m2res -outputlayer met2 |
| not met3i m3res -outputlayer met3 |
| not met4i m4res -outputlayer met4 |
| not met5i m5res -outputlayer met5 |
| size ( and capm met3 ) -by 0.14 -outputlayer m3_bot_plate |
| and capm met3 -outputlayer capm_cont_dmy |
| size ( and cap2m met4 ) -by 0.14 -outputlayer m4_bot_plate |
| and cap2m met4 -outputlayer cap2m_cont_dmy |
| not diff ( or diffres poly ) -outputlayer HVSrcDrnProp |
| select -interact HVSrcDrnProp ( and HVSrcDrnProp diffhvp ) -outputlayer HVSrcDrn |
| not HVSrcDrn nwell -outputlayer HVnSrcDrn |
| not poly polyres -outputlayer HVpolyNotRes |
| select -interact licon ( and licon ( and tap nwell ) ) -outputlayer lcTapnw |
| and npc licon -outputlayer npccon |
| select -donut nwell -outputlayer nwellring |
| holes nwell -outputlayer nwellHoles |
| and dnwell v20 -outputlayer dnwell_v20 |
| and ( and diffi nsdm ) diffres -outputlayer rndiff |
| and ( and diffi psdm ) diffres -outputlayer rpdiff |
| and ( and met3 met4 ) capm -outputlayer cap_34 |
| and ( and met4 met5 ) cap2m -outputlayer cap_45 |
| not via3 cap_34 -outputlayer via3_c |
| not via4 cap_45 -outputlayer via4_c |
| |
| |
| // ******************************************************** |
| // Begin connectivity statements |
| // ******************************************************** |
| |
| connect met5 met4 -by via4_c |
| connect met4 met3 -by via3_c |
| connect met4 m4_bot_plate -by cap2m_cont_dmy |
| connect met3 met2 -by via2 |
| |
| |
| connect met3 m3_bot_plate -by capm_cont_dmy |
| connect met2 met1 -by via1 |
| connect met1 li -by mcon |
| connect li nsd -by licon |
| connect li psd -by licon |
| connect li ntap -by licon |
| connect li ptap -by licon |
| connect li ptubtap -by licon |
| connect li poly -by licon |
| connect gate poly |
| |
| connect ntap nwell |
| connect ptap pwell |
| connect ptubtap ptub |
| connect nwell dnwell |
| |
| connect met5 pad |
| connect rdl pad |
| connect pwde v20 -by ptap |
| |
| // |
| // Off Grid checks |
| // |
| |
| |
| rule "nwell.GR" { |
| caption "nwell.GR: nwell off 0.005 grid vertex" |
| offgrid nwell 5 |
| } |
| rule "diff.GR" { |
| caption "diff.GR: diff off 0.005 grid vertex" |
| offgrid diffi 5 |
| } |
| rule "dnwell.GR" { |
| caption "dnwell.GR: dnwell off 0.005 grid vertex" |
| offgrid dnwell 5 |
| } |
| rule "lvtn.GR" { |
| caption "lvtn.GR: lvtn off 0.005 grid vertex" |
| offgrid lvtn 5 |
| } |
| rule "hvtp.GR" { |
| caption "hvtp.GR: hvtp off 0.005 grid vertex" |
| offgrid hvtp 5 |
| } |
| rule "thkox.GR" { |
| caption "thkox.GR: thkox off 0.005 grid vertex" |
| offgrid thkox 5 |
| } |
| rule "v5.GR" { |
| caption "v5.GR: v5 off 0.005 grid vertex" |
| offgrid v5 5 |
| } |
| rule "v12.GR" { |
| caption "v12.GR: v12 off 0.005 grid vertex" |
| offgrid v12 5 |
| } |
| rule "v20.GR" { |
| caption "v20.GR: v20 off 0.005 grid vertex" |
| offgrid v20 5 |
| } |
| rule "tunm.GR" { |
| caption "tunm.GR: tunm off 0.005 grid vertex" |
| offgrid tunm 5 |
| } |
| rule "poly.GR" { |
| caption "poly.GR: poly off 0.005 grid vertex" |
| offgrid polyi 5 |
| } |
| rule "npc.GR" { |
| caption "npc.GR: npc off 0.005 grid vertex" |
| offgrid npc 5 |
| } |
| rule "nsdm.GR" { |
| caption "nsdm.GR: nsdm off 0.005 grid vertex" |
| offgrid nsdm 5 |
| } |
| rule "psdm.GR" { |
| caption "psdm.GR: psdm off 0.005 grid vertex" |
| offgrid psdm 5 |
| } |
| rule "licon.GR" { |
| caption "licon.GR: licon off 0.005 grid vertex" |
| offgrid licon 5 |
| } |
| rule "li.GR" { |
| caption "li.GR: li off 0.005 grid vertex" |
| offgrid li_i 5 |
| } |
| rule "mcon.GR" { |
| caption "mcon.GR: mcon off 0.005 grid vertex" |
| offgrid mcon 5 |
| } |
| rule "met1.GR" { |
| caption "met1.GR: met1 off 0.005 grid vertex" |
| offgrid met1i 5 |
| } |
| rule "via1.GR" { |
| caption "via1.GR: via1 off 0.005 grid vertex" |
| offgrid via1 5 |
| } |
| rule "met2.GR" { |
| caption "met2.GR: met2 off 0.005 grid vertex" |
| offgrid met2i 5 |
| } |
| rule "via2.GR" { |
| caption "via2.GR: via2 off 0.005 grid vertex" |
| offgrid via2 5 |
| } |
| rule "met3.GR" { |
| caption "met3.GR: met3 off 0.005 grid vertex" |
| offgrid met3i 5 |
| } |
| rule "via3.GR" { |
| caption "via3.GR: via3 off 0.005 grid vertex" |
| offgrid via3 5 |
| } |
| rule "met4.GR" { |
| caption "met4.GR: met4 off 0.005 grid vertex" |
| offgrid met4i 5 |
| } |
| rule "via4.GR" { |
| caption "via4.GR: via4 off 0.005 grid vertex" |
| offgrid via4 5 |
| } |
| rule "met5.GR" { |
| caption "met5.GR: met5 off 0.005 grid vertex" |
| offgrid met5i 5 |
| } |
| rule "nsm.GR" { |
| caption "nsm.GR: nsm off 0.005 grid vertex" |
| offgrid nsm 5 |
| } |
| rule "pad.GR" { |
| caption "pad.GR: pad off 0.005 grid vertex" |
| offgrid pad 5 |
| } |
| rule "ldntm.GR" { |
| caption "ldntm.GR: ldntm off 0.005 grid vertex" |
| offgrid ldntm 5 |
| } |
| rule "hvntm.GR" { |
| caption "hvntm.GR: hvntm off 0.005 grid vertex" |
| offgrid hvntm 5 |
| } |
| rule "pnp.GR" { |
| caption "pnp.GR: pnp off 0.005 grid vertex" |
| offgrid pnp 5 |
| } |
| rule "capacitor.GR" { |
| caption "capacitor.GR: capacitor off 0.005 grid vertex" |
| offgrid capacitor 5 |
| } |
| rule "ncm.GR" { |
| caption "ncm.GR: ncm off 0.005 grid vertex" |
| offgrid ncm 5 |
| } |
| rule "inductor.GR" { |
| caption "inductor.GR: inductor off 0.005 grid vertex" |
| offgrid inductor 5 |
| } |
| rule "rpm.GR" { |
| caption "rpm.GR: rpm off 0.005 grid vertex" |
| offgrid rpm 5 |
| } |
| rule "hvtr.GR" { |
| caption "hvtr.GR: hvtr off 0.005 grid vertex" |
| offgrid hvtr 5 |
| } |
| rule "NTMdrop.GR" { |
| caption "NTMdrop.GR: NTMdrop off 0.005 grid vertex" |
| offgrid NTMdrop 5 |
| } |
| rule "LVTNMdrop.GR" { |
| caption "LVTNMdrop.GR: LVTNMdrop off 0.005 grid vertex" |
| offgrid LVTNMdrop 5 |
| } |
| rule "HVTPMdrop.GR" { |
| caption "HVTPMdrop.GR: HVTPMdrop off 0.005 grid vertex" |
| offgrid HVTPMdrop 5 |
| } |
| rule "LI1Mdrop.GR" { |
| caption "LI1Mdrop.GR: LI1Mdrop off 0.005 grid vertex" |
| offgrid LI1Mdrop 5 |
| } |
| rule "LICM1drop.GR" { |
| caption "LICM1drop.GR: LICM1drop off 0.005 grid vertex" |
| offgrid LICM1drop 5 |
| } |
| rule "PSDMdrop.GR" { |
| caption "PSDMdrop.GR: PSDMdrop off 0.005 grid vertex" |
| offgrid PSDMdrop 5 |
| } |
| rule "NSDMdrop.GR" { |
| caption "NSDMdrop.GR: NSDMdrop off 0.005 grid vertex" |
| offgrid NSDMdrop 5 |
| } |
| rule "FOMdrop.GR" { |
| caption "FOMdrop.GR: FOMdrop off 0.005 grid vertex" |
| offgrid FOMdrop 5 |
| } |
| rule "NTMadd.GR" { |
| caption "NTMadd.GR: NTMadd off 0.005 grid vertex" |
| offgrid NTMadd 5 |
| } |
| rule "LVTNMadd.GR" { |
| caption "LVTNMadd.GR: LVTNMadd off 0.005 grid vertex" |
| offgrid LVTNMadd 5 |
| } |
| rule "HVTPMadd.GR" { |
| caption "HVTPMadd.GR: HVTPMadd off 0.005 grid vertex" |
| offgrid HVTPMadd 5 |
| } |
| rule "LI1Madd.GR" { |
| caption "LI1Madd.GR: LI1Madd off 0.005 grid vertex" |
| offgrid LI1Madd 5 |
| } |
| rule "LICM1add.GR" { |
| caption "LICM1add.GR: LICM1add off 0.005 grid vertex" |
| offgrid LICM1add 5 |
| } |
| rule "PSDMadd.GR" { |
| caption "PSDMadd.GR: PSDMadd off 0.005 grid vertex" |
| offgrid PSDMadd 5 |
| } |
| rule "NSDMadd.GR" { |
| caption "NSDMadd.GR: NSDMadd off 0.005 grid vertex" |
| offgrid NSDMadd 5 |
| } |
| rule "FOMadd.GR" { |
| caption "FOMadd.GR: FOMadd off 0.005 grid vertex" |
| offgrid FOMadd 5 |
| } |
| rule "PMM2mk.GR" { |
| caption "PMM2mk.GR: PMM2mk off 0.005 grid vertex" |
| offgrid PMM2mk 5 |
| } |
| rule "CU1Mmk.GR" { |
| caption "CU1Mmk.GR: CU1Mmk off 0.005 grid vertex" |
| offgrid CU1Mmk 5 |
| } |
| rule "RPMmk.GR" { |
| caption "RPMmk.GR: RPMmk off 0.005 grid vertex" |
| offgrid RPMmk 5 |
| } |
| rule "PBOmk.GR" { |
| caption "PBOmk.GR: PBOmk off 0.005 grid vertex" |
| offgrid PBOmk 5 |
| } |
| rule "PDMmk.GR" { |
| caption "PDMmk.GR: PDMmk off 0.005 grid vertex" |
| offgrid PDMmk 5 |
| } |
| rule "NSMmk.GR" { |
| caption "NSMmk.GR: NSMmk off 0.005 grid vertex" |
| offgrid NSMmk 5 |
| } |
| rule "MM5mk.GR" { |
| caption "MM5mk.GR: MM5mk off 0.005 grid vertex" |
| offgrid MM5mk 5 |
| } |
| rule "VIM4mk.GR" { |
| caption "VIM4mk.GR: VIM4mk off 0.005 grid vertex" |
| offgrid VIM4mk 5 |
| } |
| rule "MM4mk.GR" { |
| caption "MM4mk.GR: MM4mk off 0.005 grid vertex" |
| offgrid MM4mk 5 |
| } |
| rule "VIM3mk.GR" { |
| caption "VIM3mk.GR: VIM3mk off 0.005 grid vertex" |
| offgrid VIM3mk 5 |
| } |
| rule "MM3mk.GR" { |
| caption "MM3mk.GR: MM3mk off 0.005 grid vertex" |
| offgrid MM3mk 5 |
| } |
| rule "VIM2mk.GR" { |
| caption "VIM2mk.GR: VIM2mk off 0.005 grid vertex" |
| offgrid VIM2mk 5 |
| } |
| rule "CTM1mk.GR" { |
| caption "CTM1mk.GR: CTM1mk off 0.005 grid vertex" |
| offgrid CTM1mk 5 |
| } |
| rule "LI1Mmk.GR" { |
| caption "LI1Mmk.GR: LI1Mmk off 0.005 grid vertex" |
| offgrid LI1Mmk 5 |
| } |
| rule "LICM1mk.GR" { |
| caption "LICM1mk.GR: LICM1mk off 0.005 grid vertex" |
| offgrid LICM1mk 5 |
| } |
| rule "PSDMmk.GR" { |
| caption "PSDMmk.GR: PSDMmk off 0.005 grid vertex" |
| offgrid PSDMmk 5 |
| } |
| rule "NSDMmk.GR" { |
| caption "NSDMmk.GR: NSDMmk off 0.005 grid vertex" |
| offgrid NSDMmk 5 |
| } |
| rule "LDNTMmk.GR" { |
| caption "LDNTMmk.GR: LDNTMmk off 0.005 grid vertex" |
| offgrid LDNTMmk 5 |
| } |
| rule "NPCMmk.GR" { |
| caption "NPCMmk.GR: NPCMmk off 0.005 grid vertex" |
| offgrid NPCMmk 5 |
| } |
| rule "HVNTMmk.GR" { |
| caption "HVNTMmk.GR: HVNTMmk off 0.005 grid vertex" |
| offgrid HVNTMmk 5 |
| } |
| rule "NTMmk.GR" { |
| caption "NTMmk.GR: NTMmk off 0.005 grid vertex" |
| offgrid NTMmk 5 |
| } |
| rule "LVOMmk.GR" { |
| caption "LVOMmk.GR: LVOMmk off 0.005 grid vertex" |
| offgrid LVOMmk 5 |
| } |
| rule "ONOMmk.GR" { |
| caption "ONOMmk.GR: ONOMmk off 0.005 grid vertex" |
| offgrid ONOMmk 5 |
| } |
| rule "TUNMmk.GR" { |
| caption "TUNMmk.GR: TUNMmk off 0.005 grid vertex" |
| offgrid TUNMmk 5 |
| } |
| rule "HVTRMmk.GR" { |
| caption "HVTRMmk.GR: HVTRMmk off 0.005 grid vertex" |
| offgrid HVTRMmk 5 |
| } |
| rule "HVTPMmk.GR" { |
| caption "HVTPMmk.GR: HVTPMmk off 0.005 grid vertex" |
| offgrid HVTPMmk 5 |
| } |
| rule "LVTNMmk.GR" { |
| caption "LVTNMmk.GR: LVTNMmk off 0.005 grid vertex" |
| offgrid LVTNMmk 5 |
| } |
| rule "NWMmk.GR" { |
| caption "NWMmk.GR: NWMmk off 0.005 grid vertex" |
| offgrid NWMmk 5 |
| } |
| rule "DNMmk.GR" { |
| caption "DNMmk.GR: DNMmk off 0.005 grid vertex" |
| offgrid DNMmk 5 |
| } |
| rule "FOMmk.GR" { |
| caption "FOMmk.GR: FOMmk off 0.005 grid vertex" |
| offgrid FOMmk 5 |
| } |
| rule "cfom.GR" { |
| caption "cfom.GR: cfom off 0.005 grid vertex" |
| offgrid cfom 5 |
| } |
| rule "clvtnm.GR" { |
| caption "clvtnm.GR: clvtnm off 0.005 grid vertex" |
| offgrid clvtnm 5 |
| } |
| rule "chvtpm.GR" { |
| caption "chvtpm.GR: chvtpm off 0.005 grid vertex" |
| offgrid chvtpm 5 |
| } |
| rule "conom.GR" { |
| caption "conom.GR: conom off 0.005 grid vertex" |
| offgrid conom 5 |
| } |
| rule "clvom.GR" { |
| caption "clvom.GR: clvom off 0.005 grid vertex" |
| offgrid clvom 5 |
| } |
| rule "cntm.GR" { |
| caption "cntm.GR: cntm off 0.005 grid vertex" |
| offgrid cntm 5 |
| } |
| rule "chvntm.GR" { |
| caption "chvntm.GR: chvntm off 0.005 grid vertex" |
| offgrid chvntm 5 |
| } |
| rule "cnpc.GR" { |
| caption "cnpc.GR: cnpc off 0.005 grid vertex" |
| offgrid cnpc 5 |
| } |
| rule "cnsdm.GR" { |
| caption "cnsdm.GR: cnsdm off 0.005 grid vertex" |
| offgrid cnsdm 5 |
| } |
| rule "cpsdm.GR" { |
| caption "cpsdm.GR: cpsdm off 0.005 grid vertex" |
| offgrid cpsdm 5 |
| } |
| rule "cli1m.GR" { |
| caption "cli1m.GR: cli1m off 0.005 grid vertex" |
| offgrid cli1m 5 |
| } |
| rule "cviam3.GR" { |
| caption "cviam3.GR: cviam3 off 0.005 grid vertex" |
| offgrid cviam3 5 |
| } |
| rule "cviam4.GR" { |
| caption "cviam4.GR: cviam4 off 0.005 grid vertex" |
| offgrid cviam4 5 |
| } |
| rule "pmm.GR" { |
| caption "pmm.GR: pmm off 0.005 grid vertex" |
| offgrid pmm 5 |
| } |
| rule "rdl.GR" { |
| caption "rdl.GR: rdl off 0.005 grid vertex" |
| offgrid rdl 5 |
| } |
| rule "pmm2.GR" { |
| caption "pmm2.GR: pmm2 off 0.005 grid vertex" |
| offgrid pmm2 5 |
| } |
| rule "ubm.GR" { |
| caption "ubm.GR: ubm off 0.005 grid vertex" |
| offgrid ubm 5 |
| } |
| rule "bump.GR" { |
| caption "bump.GR: bump off 0.005 grid vertex" |
| offgrid bump 5 |
| } |
| rule "capm.GR" { |
| caption "capm.GR: capm off 0.005 grid vertex" |
| offgrid capm 5 |
| } |
| rule "cap2m.GR" { |
| caption "cap2m.GR: cap2m off 0.005 grid vertex" |
| offgrid cap2m 5 |
| } |
| extent_cell "advSeal_6um*" -original -outputlayer SEALID_6um_1 |
| extent_cell "cuPillarAdvSeal_6um*" -original -outputlayer SEALID_6um_2 |
| extent_cell "sealring*" -original -outputlayer SEALID_6um_3 |
| and SEALID ( or SEALID_6um_1 SEALID_6um_2 SEALID_6um_3 ) -outputlayer SEALID_6um |
| select -interact diffi ( edge_expand ( edge_length ( select -donut DIFF ) -gt 1000 ) -inside_by 0.005 ) -outputlayer diffOfA1K |
| select -interact ( select -interact diffi ( inte diffOfA1K -eq 0.3 -abut -lt 90 -single_point -output region ) ) SEALID -outputlayer diffRingSeal |
| not diffi ( or SEALID_6um diffRingSeal ) -outputlayer diffNotAdvSeal6um |
| not diffNotAdvSeal6um ( or v5 v12 v20 ) -outputlayer diffNOtSealUHVI |
| and polyi anchor -outputlayer polyAnc |
| size ESDID -by 0.2 -outputlayer ESDID_sz |
| and polyi ESDID_sz -outputlayer poly_ESD |
| not polyi ESDID_sz -outputlayer poly_nonESD |
| extent_cell "s8rf_npn_1x1_2p0_HV" -original -outputlayer gated_npn |
| not poly_nonESD polyAnc -outputlayer poly_noESD_noAnch |
| and ( or critside ccorner ) ( holes SEALID ) -outputlayer critArea |
| and polyi critArea -outputlayer p_and_c |
| and li_i critArea -outputlayer l_and_c |
| and met1i critArea -outputlayer m1_and_c |
| and met1i critArea -outputlayer m2_and_c |
| and met3i critArea -outputlayer m3_and_c |
| and met4i critArea -outputlayer m4_and_c |
| and p_and_c ( and l_and_c ( and m1_and_c ( and m2_and_c ( and m3_and_c m4_and_c ) ) ) ) -outputlayer anch1 |
| and ( and p_and_c ( and l_and_c ( and m1_and_c ( and m2_and_c ( and m3_and_c m4_and_c ) ) ) ) ) critArea -outputlayer anch2 |
| select -interact anch1 anch2 -outputlayer anchLayers |
| and mcon anchLayers -outputlayer amcon |
| and licon anchLayers -outputlayer alicon1 |
| and via1 anchLayers -outputlayer avia |
| and via2 anchLayers -outputlayer avia2 |
| and via3 anchLayers -outputlayer avia3 |
| select -outside amcon ( or avia3 avia2 avia alicon1 ) -outputlayer anchmcon |
| select -outside alicon1 ( or avia3 avia2 avia amcon ) -outputlayer anchlicon1 |
| select -outside avia ( or avia3 avia2 alicon1 amcon ) -outputlayer anchvia |
| select -outside avia2 ( or avia3 avia alicon1 amcon ) -outputlayer anchvia2 |
| select -outside avia3 ( or avia2 avia alicon1 amcon ) -outputlayer anchvia3 |
| or amcon alicon1 avia avia2 avia3 -outputlayer acontacts |
| or anchmcon anchlicon1 anchvia anchvia2 anchvia3 -outputlayer anchcontacts |
| not acontacts anchcontacts -outputlayer overlapCon |
| select -enclose ( select -enclose ( select -enclose ( select -enclose ( select -enclose anchLayers mcon ) licon ) via1 ) via2 ) via3 -outputlayer anchorTmp |
| select -cut poly anchLayers -outputlayer falseAnch |
| select -outside anchorTmp ( or overlapCon falseAnch ) -outputlayer anchor |
| and li anchor -outputlayer li1Anc |
| not li1_PERI SEALID -outputlayer li1_PERI_nonSEAL |
| not li1_PERI_nonSEAL ( or li1Anc falseAnch ) -outputlayer li1Peri_noSEAL_noAnch |
| not licon SEALID -outputlayer licon_nonSEAL |
| not mcon SEALID -outputlayer mcon_nonSEAL |
| not via1 SEALID -outputlayer via_nonSEAL |
| not via2 SEALID -outputlayer via2_nonSEAL |
| not via3 SEALID -outputlayer via3_nonSEAL |
| not via4 SEALID -outputlayer via4_nonSEAL |
| and tap SEALID -outputlayer tap_SEAL |
| and ( not tap SEALID ) ENID -outputlayer tap_ENID |
| not tap ( or SEALID ENID ) -outputlayer tap_nonSEAL |
| and li_i SEALID -outputlayer li_SEAL |
| and li_i COREID -outputlayer li_CORE |
| and licon SEALID -outputlayer licon_SEAL |
| and mcon SEALID -outputlayer mcon_SEAL |
| and via1 SEALID -outputlayer via1_SEAL |
| and via2 SEALID -outputlayer via2_SEAL |
| and via3 SEALID -outputlayer via3_SEAL |
| select -donut SEALID -outputlayer sealRing |
| holes SEALID -outputlayer sealHoles |
| not FOMdrop SEALID_6um -outputlayer FOMdrop_noSeal |
| |
| |
| // |
| // Angle checks |
| // |
| |
| |
| not poly_noESD_noAnch npn -outputlayer poly_noESD_noAnch_no_npn |
| rule "diff.ANG.1" { |
| caption "diff.ANG.1: diffusion not in areaid:seal or 20v device non-manhattan edge" |
| angle diffNOtSealUHVI -ltgt 0 90 |
| } |
| rule "poly_not_in_ESD.ANG.1" { |
| caption "poly_not_in_ESD.ANG.1: poly not in NPN, ESD or anchor non-manhattan edge" |
| angle poly_noESD_noAnch_no_npn -ltgt 0 90 |
| } |
| rule "li.ANG.1" { |
| caption "li.ANG.1: local interconnect not in areaid:seal or achnor non-manhattan edge" |
| angle li1Peri_noSEAL_noAnch -ltgt 0 90 |
| } |
| rule "licon.ANG.1" { |
| caption "licon.ANG.1: licon interconnect not in areaid:seal non-manhattan edge" |
| angle licon_nonSEAL -ltgt 0 90 |
| } |
| rule "mcon.ANG.1" { |
| caption "mcon.ANG.1: metal contact not in areaid:seal non-manhattan edge" |
| angle mcon_nonSEAL -ltgt 0 90 |
| } |
| rule "via1.ANG.1" { |
| caption "via1.ANG.1: via contact not in areaid:seal non-manhattan edge" |
| angle via_nonSEAL -ltgt 0 90 |
| } |
| rule "via2.ANG.1" { |
| caption "via2.ANG.1: via2 contact not in areaid:seal non-manhattan edge" |
| angle via2_nonSEAL -ltgt 0 90 |
| } |
| rule "via3.ANG.1" { |
| caption "via3.ANG.1: via3 contact not in areaid:seal non-manhattan edge" |
| angle via3_nonSEAL -ltgt 0 90 |
| } |
| rule "via4.ANG.1" { |
| caption "via4.ANG.1: via4 contact not in areaid:seal non-manhattan edge" |
| angle via4_nonSEAL -ltgt 0 90 |
| } |
| select -inside diffTap ANALOGID -outputlayer analog_difftap |
| select -interact -not analog_difftap ( select -donut analog_difftap ) -outputlayer non_ring_difftap |
| rect_chk -not non_ring_difftap -outputlayer bad_analog_difftap |
| rule "diff.ANG.2" { |
| caption "diff.ANG.2: A diff or tap shape enclosed in areaid:analog must be rectangular" |
| copy bad_analog_difftap |
| } |
| rule "licon.ANG.2" { |
| caption "licon.ANG.2: licon must be a rectangle" |
| not licon ( select -interact licon ( select -donut licon ) ) -outputlayer not_donut_lay |
| rect_chk -not not_donut_lay |
| } |
| rule "mcon.ANG.2" { |
| caption "mcon.ANG.2: mcon must be a rectangle" |
| not mcon ( select -interact mcon ( select -donut mcon ) ) -outputlayer not_donut_lay |
| rect_chk -not not_donut_lay |
| } |
| rule "via1.ANG.2" { |
| caption "via1.ANG.2: via1 must be a rectangle" |
| not via1 ( select -interact via1 ( select -donut via1 ) ) -outputlayer not_donut_lay |
| rect_chk -not not_donut_lay |
| } |
| rule "via2.ANG.2" { |
| caption "via2.ANG.2: via2 must be a rectangle" |
| not via2 ( select -interact via2 ( select -donut via2 ) ) -outputlayer not_donut_lay |
| rect_chk -not not_donut_lay |
| } |
| rule "via3.ANG.2" { |
| caption "via3.ANG.2: via3 must be a rectangle" |
| not via3 ( select -interact via3 ( select -donut via3 ) ) -outputlayer not_donut_lay |
| rect_chk -not not_donut_lay |
| } |
| rule "via4.ANG.2" { |
| caption "via4.ANG.2: via4 must be a rectangle" |
| not via4 ( select -interact via4 ( select -donut via4 ) ) -outputlayer not_donut_lay |
| rect_chk -not not_donut_lay |
| } |
| rule "nwell.ANG.3" { |
| caption "nwell.ANG.3: nwell non-octagonal edge" |
| angle nwell -ltgt 0 45 |
| angle nwell -ltgt 45 90 |
| } |
| rule "diff.ANG.3" { |
| caption "diff.ANG.3: diff non-octagonal edge" |
| angle diff -ltgt 0 45 |
| angle diff -ltgt 45 90 |
| } |
| rule "dnwell.ANG.3" { |
| caption "dnwell.ANG.3: dnwell non-octagonal edge" |
| angle dnwell -ltgt 0 45 |
| angle dnwell -ltgt 45 90 |
| } |
| rule "lvtn.ANG.3" { |
| caption "lvtn.ANG.3: lvtn non-octagonal edge" |
| angle lvtn -ltgt 0 45 |
| angle lvtn -ltgt 45 90 |
| } |
| rule "hvtp.ANG.3" { |
| caption "hvtp.ANG.3: hvtp non-octagonal edge" |
| angle hvtp -ltgt 0 45 |
| angle hvtp -ltgt 45 90 |
| } |
| rule "thkox.ANG.3" { |
| caption "thkox.ANG.3: thkox non-octagonal edge" |
| angle thkox -ltgt 0 45 |
| angle thkox -ltgt 45 90 |
| } |
| rule "tunm.ANG.3" { |
| caption "tunm.ANG.3: tunm non-octagonal edge" |
| angle tunm -ltgt 0 45 |
| angle tunm -ltgt 45 90 |
| } |
| rule "npc.ANG.3" { |
| caption "npc.ANG.3: npc non-octagonal edge" |
| angle npc -ltgt 0 45 |
| angle npc -ltgt 45 90 |
| } |
| rule "nsdm.ANG.3" { |
| caption "nsdm.ANG.3: nsdm non-octagonal edge" |
| angle nsdm -ltgt 0 45 |
| angle nsdm -ltgt 45 90 |
| } |
| rule "psdm.ANG.3" { |
| caption "psdm.ANG.3: psdm non-octagonal edge" |
| angle psdm -ltgt 0 45 |
| angle psdm -ltgt 45 90 |
| } |
| rule "met1.ANG.3" { |
| caption "met1.ANG.3: met1 non-octagonal edge" |
| angle met1 -ltgt 0 45 |
| angle met1 -ltgt 45 90 |
| } |
| rule "met2.ANG.3" { |
| caption "met2.ANG.3: met2 non-octagonal edge" |
| angle met2 -ltgt 0 45 |
| angle met2 -ltgt 45 90 |
| } |
| rule "v12.ANG.3" { |
| caption "v12.ANG.3: v12 non-octagonal edge" |
| angle v12 -ltgt 0 45 |
| angle v12 -ltgt 45 90 |
| } |
| rule "met3.ANG.3" { |
| caption "met3.ANG.3: met3 non-octagonal edge" |
| angle met3 -ltgt 0 45 |
| angle met3 -ltgt 45 90 |
| } |
| rule "met4.ANG.3" { |
| caption "met4.ANG.3: met4 non-octagonal edge" |
| angle met4 -ltgt 0 45 |
| angle met4 -ltgt 45 90 |
| } |
| rule "met5.ANG.3" { |
| caption "met5.ANG.3: met5 non-octagonal edge" |
| angle met5 -ltgt 0 45 |
| angle met5 -ltgt 45 90 |
| } |
| rule "nsm.ANG.3" { |
| caption "nsm.ANG.3: nsm non-octagonal edge" |
| angle nsm -ltgt 0 45 |
| angle nsm -ltgt 45 90 |
| } |
| rule "pad.ANG.3" { |
| caption "pad.ANG.3: pad non-octagonal edge" |
| angle pad -ltgt 0 45 |
| angle pad -ltgt 45 90 |
| } |
| rule "ldntm.ANG.3" { |
| caption "ldntm.ANG.3: ldntm non-octagonal edge" |
| angle ldntm -ltgt 0 45 |
| angle ldntm -ltgt 45 90 |
| } |
| rule "hvntm.ANG.3" { |
| caption "hvntm.ANG.3: hvntm non-octagonal edge" |
| angle hvntm -ltgt 0 45 |
| angle hvntm -ltgt 45 90 |
| } |
| rule "capacitor.ANG.3" { |
| caption "capacitor.ANG.3: capacitor non-octagonal edge" |
| angle capacitor -ltgt 0 45 |
| angle capacitor -ltgt 45 90 |
| } |
| rule "ncm.ANG.3" { |
| caption "ncm.ANG.3: ncm non-octagonal edge" |
| angle ncm -ltgt 0 45 |
| angle ncm -ltgt 45 90 |
| } |
| rule "inductor.ANG.3" { |
| caption "inductor.ANG.3: inductor non-octagonal edge" |
| angle inductor -ltgt 0 45 |
| angle inductor -ltgt 45 90 |
| } |
| rule "rpm.ANG.3" { |
| caption "rpm.ANG.3: rpm non-octagonal edge" |
| angle rpm -ltgt 0 45 |
| angle rpm -ltgt 45 90 |
| } |
| rule "urpm.ANG.3" { |
| caption "urpm.ANG.3: urpm non-octagonal edge" |
| angle urpm -ltgt 0 45 |
| angle urpm -ltgt 45 90 |
| } |
| rule "hvtr.ANG.3" { |
| caption "hvtr.ANG.3: hvtr non-octagonal edge" |
| angle hvtr -ltgt 0 45 |
| angle hvtr -ltgt 45 90 |
| } |
| rule "metop1.ANG.3" { |
| caption "metop1.ANG.3: metop1 non-octagonal edge" |
| angle metop1 -ltgt 0 45 |
| angle metop1 -ltgt 45 90 |
| } |
| rule "metop2.ANG.3" { |
| caption "metop2.ANG.3: metop2 non-octagonal edge" |
| angle metop2 -ltgt 0 45 |
| angle metop2 -ltgt 45 90 |
| } |
| rule "metop3.ANG.3" { |
| caption "metop3.ANG.3: metop3 non-octagonal edge" |
| angle metop3 -ltgt 0 45 |
| angle metop3 -ltgt 45 90 |
| } |
| rule "metop4.ANG.3" { |
| caption "metop4.ANG.3: metop4 non-octagonal edge" |
| angle metop4 -ltgt 0 45 |
| angle metop4 -ltgt 45 90 |
| } |
| rule "metop5.ANG.3" { |
| caption "metop5.ANG.3: metop5 non-octagonal edge" |
| angle metop5 -ltgt 0 45 |
| angle metop5 -ltgt 45 90 |
| } |
| rule "metop6.ANG.3" { |
| caption "metop6.ANG.3: metop6 non-octagonal edge" |
| angle metop6 -ltgt 0 45 |
| angle metop6 -ltgt 45 90 |
| } |
| rule "metop7.ANG.3" { |
| caption "metop7.ANG.3: metop7 non-octagonal edge" |
| angle metop7 -ltgt 0 45 |
| angle metop7 -ltgt 45 90 |
| } |
| rule "metop8.ANG.3" { |
| caption "metop8.ANG.3: metop8 non-octagonal edge" |
| angle metop8 -ltgt 0 45 |
| angle metop8 -ltgt 45 90 |
| } |
| rule "NTMdrop.ANG.3" { |
| caption "NTMdrop.ANG.3: NTMdrop non-octagonal edge" |
| angle NTMdrop -ltgt 0 45 |
| angle NTMdrop -ltgt 45 90 |
| } |
| rule "LVTNMdrop.ANG.3" { |
| caption "LVTNMdrop.ANG.3: LVTNMdrop non-octagonal edge" |
| angle LVTNMdrop -ltgt 0 45 |
| angle LVTNMdrop -ltgt 45 90 |
| } |
| rule "HVTPMdrop.ANG.3" { |
| caption "HVTPMdrop.ANG.3: HVTPMdrop non-octagonal edge" |
| angle HVTPMdrop -ltgt 0 45 |
| angle HVTPMdrop -ltgt 45 90 |
| } |
| rule "LI1Mdrop.ANG.3" { |
| caption "LI1Mdrop.ANG.3: LI1Mdrop non-octagonal edge" |
| angle LI1Mdrop -ltgt 0 45 |
| angle LI1Mdrop -ltgt 45 90 |
| } |
| rule "LICM1drop.ANG.3" { |
| caption "LICM1drop.ANG.3: LICM1drop non-octagonal edge" |
| angle LICM1drop -ltgt 0 45 |
| angle LICM1drop -ltgt 45 90 |
| } |
| rule "PSDMdrop.ANG.3" { |
| caption "PSDMdrop.ANG.3: PSDMdrop non-octagonal edge" |
| angle PSDMdrop -ltgt 0 45 |
| angle PSDMdrop -ltgt 45 90 |
| } |
| rule "NSDMdrop.ANG.3" { |
| caption "NSDMdrop.ANG.3: NSDMdrop non-octagonal edge" |
| angle NSDMdrop -ltgt 0 45 |
| angle NSDMdrop -ltgt 45 90 |
| } |
| rule "P1Mdrop.ANG.3" { |
| caption "P1Mdrop.ANG.3: P1Mdrop non-octagonal edge" |
| angle P1Mdrop -ltgt 0 45 |
| angle P1Mdrop -ltgt 45 90 |
| } |
| rule "FOMdrop.ANG.3" { |
| caption "FOMdrop.ANG.3: FOMdrop non-octagonal edge" |
| angle FOMdrop -ltgt 0 45 |
| angle FOMdrop -ltgt 45 90 |
| } |
| rule "NTMadd.ANG.3" { |
| caption "NTMadd.ANG.3: NTMadd non-octagonal edge" |
| angle NTMadd -ltgt 0 45 |
| angle NTMadd -ltgt 45 90 |
| } |
| rule "LVTNMadd.ANG.3" { |
| caption "LVTNMadd.ANG.3: LVTNMadd non-octagonal edge" |
| angle LVTNMadd -ltgt 0 45 |
| angle LVTNMadd -ltgt 45 90 |
| } |
| rule "HVTPMadd.ANG.3" { |
| caption "HVTPMadd.ANG.3: HVTPMadd non-octagonal edge" |
| angle HVTPMadd -ltgt 0 45 |
| angle HVTPMadd -ltgt 45 90 |
| } |
| rule "LI1Madd.ANG.3" { |
| caption "LI1Madd.ANG.3: LI1Madd non-octagonal edge" |
| angle LI1Madd -ltgt 0 45 |
| angle LI1Madd -ltgt 45 90 |
| } |
| rule "LICM1add.ANG.3" { |
| caption "LICM1add.ANG.3: LICM1add non-octagonal edge" |
| angle LICM1add -ltgt 0 45 |
| angle LICM1add -ltgt 45 90 |
| } |
| rule "PSDMadd.ANG.3" { |
| caption "PSDMadd.ANG.3: PSDMadd non-octagonal edge" |
| angle PSDMadd -ltgt 0 45 |
| angle PSDMadd -ltgt 45 90 |
| } |
| rule "NSDMadd.ANG.3" { |
| caption "NSDMadd.ANG.3: NSDMadd non-octagonal edge" |
| angle NSDMadd -ltgt 0 45 |
| angle NSDMadd -ltgt 45 90 |
| } |
| rule "P1Madd.ANG.3" { |
| caption "P1Madd.ANG.3: P1Madd non-octagonal edge" |
| angle P1Madd -ltgt 0 45 |
| angle P1Madd -ltgt 45 90 |
| } |
| rule "FOMadd.ANG.3" { |
| caption "FOMadd.ANG.3: FOMadd non-octagonal edge" |
| angle FOMadd -ltgt 0 45 |
| angle FOMadd -ltgt 45 90 |
| } |
| rule "cfom.ANG.3" { |
| caption "cfom.ANG.3: cfom non-octagonal edge" |
| angle cfom -ltgt 0 45 |
| angle cfom -ltgt 45 90 |
| } |
| rule "clvtnm.ANG.3" { |
| caption "clvtnm.ANG.3: clvtnm non-octagonal edge" |
| angle clvtnm -ltgt 0 45 |
| angle clvtnm -ltgt 45 90 |
| } |
| rule "chvtpm.ANG.3" { |
| caption "chvtpm.ANG.3: chvtpm non-octagonal edge" |
| angle chvtpm -ltgt 0 45 |
| angle chvtpm -ltgt 45 90 |
| } |
| rule "conom.ANG.3" { |
| caption "conom.ANG.3: conom non-octagonal edge" |
| angle conom -ltgt 0 45 |
| angle conom -ltgt 45 90 |
| } |
| rule "clvom.ANG.3" { |
| caption "clvom.ANG.3: clvom non-octagonal edge" |
| angle clvom -ltgt 0 45 |
| angle clvom -ltgt 45 90 |
| } |
| rule "cntm.ANG.3" { |
| caption "cntm.ANG.3: cntm non-octagonal edge" |
| angle cntm -ltgt 0 45 |
| angle cntm -ltgt 45 90 |
| } |
| rule "chvntm.ANG.3" { |
| caption "chvntm.ANG.3: chvntm non-octagonal edge" |
| angle chvntm -ltgt 0 45 |
| angle chvntm -ltgt 45 90 |
| } |
| rule "cnpc.ANG.3" { |
| caption "cnpc.ANG.3: cnpc non-octagonal edge" |
| angle cnpc -ltgt 0 45 |
| angle cnpc -ltgt 45 90 |
| } |
| rule "cnsdm.ANG.3" { |
| caption "cnsdm.ANG.3: cnsdm non-octagonal edge" |
| angle cnsdm -ltgt 0 45 |
| angle cnsdm -ltgt 45 90 |
| } |
| rule "cpsdm.ANG.3" { |
| caption "cpsdm.ANG.3: cpsdm non-octagonal edge" |
| angle cpsdm -ltgt 0 45 |
| angle cpsdm -ltgt 45 90 |
| } |
| rule "cli1m.ANG.3" { |
| caption "cli1m.ANG.3: cli1m non-octagonal edge" |
| angle cli1m -ltgt 0 45 |
| angle cli1m -ltgt 45 90 |
| } |
| rule "cviam3.ANG.3" { |
| caption "cviam3.ANG.3: cviam3 non-octagonal edge" |
| angle cviam3 -ltgt 0 45 |
| angle cviam3 -ltgt 45 90 |
| } |
| rule "cviam4.ANG.3" { |
| caption "cviam4.ANG.3: cviam4 non-octagonal edge" |
| angle cviam4 -ltgt 0 45 |
| angle cviam4 -ltgt 45 90 |
| } |
| rule "PMM2mk.ANG.3" { |
| caption "PMM2mk.ANG.3: PMM2mk non-octagonal edge" |
| angle PMM2mk -ltgt 0 45 |
| angle PMM2mk -ltgt 45 90 |
| } |
| rule "CU1Mmk.ANG.3" { |
| caption "CU1Mmk.ANG.3: CU1Mmk non-octagonal edge" |
| angle CU1Mmk -ltgt 0 45 |
| angle CU1Mmk -ltgt 45 90 |
| } |
| rule "RPMmk.ANG.3" { |
| caption "RPMmk.ANG.3: RPMmk non-octagonal edge" |
| angle RPMmk -ltgt 0 45 |
| angle RPMmk -ltgt 45 90 |
| } |
| rule "PBOmk.ANG.3" { |
| caption "PBOmk.ANG.3: PBOmk non-octagonal edge" |
| angle PBOmk -ltgt 0 45 |
| angle PBOmk -ltgt 45 90 |
| } |
| rule "PDMmk.ANG.3" { |
| caption "PDMmk.ANG.3: PDMmk non-octagonal edge" |
| angle PDMmk -ltgt 0 45 |
| angle PDMmk -ltgt 45 90 |
| } |
| rule "NSMmk.ANG.3" { |
| caption "NSMmk.ANG.3: NSMmk non-octagonal edge" |
| angle NSMmk -ltgt 0 45 |
| angle NSMmk -ltgt 45 90 |
| } |
| rule "MM5mk.ANG.3" { |
| caption "MM5mk.ANG.3: MM5mk non-octagonal edge" |
| angle MM5mk -ltgt 0 45 |
| angle MM5mk -ltgt 45 90 |
| } |
| rule "VIM4mk.ANG.3" { |
| caption "VIM4mk.ANG.3: VIM4mk non-octagonal edge" |
| angle VIM4mk -ltgt 0 45 |
| angle VIM4mk -ltgt 45 90 |
| } |
| rule "MM4mk.ANG.3" { |
| caption "MM4mk.ANG.3: MM4mk non-octagonal edge" |
| angle MM4mk -ltgt 0 45 |
| angle MM4mk -ltgt 45 90 |
| } |
| rule "VIM3mk.ANG.3" { |
| caption "VIM3mk.ANG.3: VIM3mk non-octagonal edge" |
| angle VIM3mk -ltgt 0 45 |
| angle VIM3mk -ltgt 45 90 |
| } |
| rule "MM3mk.ANG.3" { |
| caption "MM3mk.ANG.3: MM3mk non-octagonal edge" |
| angle MM3mk -ltgt 0 45 |
| angle MM3mk -ltgt 45 90 |
| } |
| rule "VIM2mk.ANG.3" { |
| caption "VIM2mk.ANG.3: VIM2mk non-octagonal edge" |
| angle VIM2mk -ltgt 0 45 |
| angle VIM2mk -ltgt 45 90 |
| } |
| rule "MM2mk.ANG.3" { |
| caption "MM2mk.ANG.3: MM2mk non-octagonal edge" |
| angle MM2mk -ltgt 0 45 |
| angle MM2mk -ltgt 45 90 |
| } |
| rule "VIMmk.ANG.3" { |
| caption "VIMmk.ANG.3: VIMmk non-octagonal edge" |
| angle VIMmk -ltgt 0 45 |
| angle VIMmk -ltgt 45 90 |
| } |
| rule "MM1mk.ANG.3" { |
| caption "MM1mk.ANG.3: MM1mk non-octagonal edge" |
| angle MM1mk -ltgt 0 45 |
| angle MM1mk -ltgt 45 90 |
| } |
| rule "CTM1mk.ANG.3" { |
| caption "CTM1mk.ANG.3: CTM1mk non-octagonal edge" |
| angle CTM1mk -ltgt 0 45 |
| angle CTM1mk -ltgt 45 90 |
| } |
| rule "LI1Mmk.ANG.3" { |
| caption "LI1Mmk.ANG.3: LI1Mmk non-octagonal edge" |
| angle LI1Mmk -ltgt 0 45 |
| angle LI1Mmk -ltgt 45 90 |
| } |
| rule "LICM1mk.ANG.3" { |
| caption "LICM1mk.ANG.3: LICM1mk non-octagonal edge" |
| angle LICM1mk -ltgt 0 45 |
| angle LICM1mk -ltgt 45 90 |
| } |
| rule "PSDMmk.ANG.3" { |
| caption "PSDMmk.ANG.3: PSDMmk non-octagonal edge" |
| angle PSDMmk -ltgt 0 45 |
| angle PSDMmk -ltgt 45 90 |
| } |
| rule "NSDMmk.ANG.3" { |
| caption "NSDMmk.ANG.3: NSDMmk non-octagonal edge" |
| angle NSDMmk -ltgt 0 45 |
| angle NSDMmk -ltgt 45 90 |
| } |
| rule "LDNTMmk.ANG.3" { |
| caption "LDNTMmk.ANG.3: LDNTMmk non-octagonal edge" |
| angle LDNTMmk -ltgt 0 45 |
| angle LDNTMmk -ltgt 45 90 |
| } |
| rule "NPCMmk.ANG.3" { |
| caption "NPCMmk.ANG.3: NPCMmk non-octagonal edge" |
| angle NPCMmk -ltgt 0 45 |
| angle NPCMmk -ltgt 45 90 |
| } |
| rule "HVNTMmk.ANG.3" { |
| caption "HVNTMmk.ANG.3: HVNTMmk non-octagonal edge" |
| angle HVNTMmk -ltgt 0 45 |
| angle HVNTMmk -ltgt 45 90 |
| } |
| rule "NTMmk.ANG.3" { |
| caption "NTMmk.ANG.3: NTMmk non-octagonal edge" |
| angle NTMmk -ltgt 0 45 |
| angle NTMmk -ltgt 45 90 |
| } |
| rule "P1Mmk.ANG.3" { |
| caption "P1Mmk.ANG.3: P1Mmk non-octagonal edge" |
| angle P1Mmk -ltgt 0 45 |
| angle P1Mmk -ltgt 45 90 |
| } |
| rule "LVOMmk.ANG.3" { |
| caption "LVOMmk.ANG.3: LVOMmk non-octagonal edge" |
| angle LVOMmk -ltgt 0 45 |
| angle LVOMmk -ltgt 45 90 |
| } |
| rule "ONOMmk.ANG.3" { |
| caption "ONOMmk.ANG.3: ONOMmk non-octagonal edge" |
| angle ONOMmk -ltgt 0 45 |
| angle ONOMmk -ltgt 45 90 |
| } |
| rule "TUNMmk.ANG.3" { |
| caption "TUNMmk.ANG.3: TUNMmk non-octagonal edge" |
| angle TUNMmk -ltgt 0 45 |
| angle TUNMmk -ltgt 45 90 |
| } |
| rule "HVTRMmk.ANG.3" { |
| caption "HVTRMmk.ANG.3: HVTRMmk non-octagonal edge" |
| angle HVTRMmk -ltgt 0 45 |
| angle HVTRMmk -ltgt 45 90 |
| } |
| rule "HVTPMmk.ANG.3" { |
| caption "HVTPMmk.ANG.3: HVTPMmk non-octagonal edge" |
| angle HVTPMmk -ltgt 0 45 |
| angle HVTPMmk -ltgt 45 90 |
| } |
| rule "LVTNMmk.ANG.3" { |
| caption "LVTNMmk.ANG.3: LVTNMmk non-octagonal edge" |
| angle LVTNMmk -ltgt 0 45 |
| angle LVTNMmk -ltgt 45 90 |
| } |
| rule "NWMmk.ANG.3" { |
| caption "NWMmk.ANG.3: NWMmk non-octagonal edge" |
| angle NWMmk -ltgt 0 45 |
| angle NWMmk -ltgt 45 90 |
| } |
| rule "DNMmk.ANG.3" { |
| caption "DNMmk.ANG.3: DNMmk non-octagonal edge" |
| angle DNMmk -ltgt 0 45 |
| angle DNMmk -ltgt 45 90 |
| } |
| rule "FOMmk.ANG.3" { |
| caption "FOMmk.ANG.3: FOMmk non-octagonal edge" |
| angle FOMmk -ltgt 0 45 |
| angle FOMmk -ltgt 45 90 |
| } |
| rule "tap_seal.ANG.3" { |
| caption "tap_seal.ANG.3: tap in areaid:seal non-octagonal edge" |
| angle tap_SEAL -ltgt 0 45 |
| angle tap_SEAL -ltgt 45 90 |
| } |
| rule "tap_extended_drain.ANG.3" { |
| caption "tap_extended_drain.ANG.3: tap in areaid:extendedDrain non-octagonal edge" |
| angle tap_ENID -ltgt 0 45 |
| angle tap_ENID -ltgt 45 90 |
| } |
| rule "poly_ESD.ANG.3" { |
| caption "poly_ESD.ANG.3: poly edge inside areaid:esd non-octagonal edge" |
| angle poly_ESD -ltgt 0 45 |
| angle poly_ESD -ltgt 45 90 |
| } |
| rule "li_core.ANG.3" { |
| caption "li_core.ANG.3: li in areaid:core non-octagonal edge" |
| angle li_CORE -ltgt 0 45 |
| angle li_CORE -ltgt 45 90 |
| } |
| rule "li_seal.ANG.3" { |
| caption "li_seal.ANG.3: li in areaid:seal non-octagonal edge" |
| angle li_SEAL -ltgt 0 45 |
| angle li_SEAL -ltgt 45 90 |
| } |
| rule "capm.ANG.3" { |
| caption "capm.ANG.3: capm non-octagonal edge" |
| angle capm -ltgt 0 45 |
| angle capm -ltgt 45 90 |
| } |
| rule "cap2m.ANG.3" { |
| caption "cap2m.ANG.3: cap2m non-octagonal edge" |
| angle cap2m -ltgt 0 45 |
| angle cap2m -ltgt 45 90 |
| } |
| |
| |
| // |
| // Construction checks |
| // |
| |
| |
| |
| rule "diff.WARN.1" { |
| caption "diff.WARN.1: diffusion without implant" |
| not ( not ( not diffi ( or nsdm psdm ) ) SEALID ) npn |
| } |
| rule "met5Pin.CON.1" { |
| caption "met5Pin.CON.1: met5/pin must be enclosed by met5" |
| not met5Pin met5i |
| } |
| rule "met4Pin.CON.1" { |
| caption "met4Pin.CON.1: met4/pin must be enclosed by met4" |
| not met4Pin met4i |
| } |
| rule "met3Pin.CON.1" { |
| caption "met3Pin.CON.1: met3/pin must be enclosed by met3" |
| not met3Pin met3i |
| } |
| rule "met2Pin.CON.1" { |
| caption "met2Pin.CON.1: met2/pin must be enclosed by met2" |
| not met2Pin met2i |
| } |
| rule "met1Pin.CON.1" { |
| caption "met1Pin.CON.1: met1/pin must be enclosed by met1" |
| not met1Pin met1i |
| } |
| rule "liPin.CON.1" { |
| caption "liPin.CON.1: li/pin must be enclosed by li" |
| not liPin li_i |
| } |
| rule "polyPin.CON.1" { |
| caption "polyPin.CON.1: poly/pin must be enclosed by poly" |
| not polyPin polyi |
| } |
| rule "diffPin.CON.1" { |
| caption "diffPin.CON.1: diff/pin must be enclosed by diff" |
| not diffPin diffi |
| } |
| rule "mcon.CON.2" { |
| caption "mcon.CON.2: mcon must be inside met1 and li" |
| not mcon li_i |
| not mcon met1i |
| } |
| rule "via1.CON.2" { |
| caption "via1.CON.2: via1 must be inside met2 and met1" |
| not via1 met1i |
| not via1 met2i |
| } |
| rule "via2.CON.2" { |
| caption "via2.CON.2: via2 must be inside met3 and met2" |
| not via2 met2i |
| not via2 met3i |
| } |
| rule "via3.CON.2" { |
| caption "via3.CON.2: via3 must be inside met4 and met3" |
| not via3 met3i |
| not via3 met4i |
| } |
| rule "via4.CON.2" { |
| caption "via4.CON.2: via4 must be inside met5 and met4" |
| not via4 met4i |
| not via4 met5i |
| } |
| rule "licon.CON.2" { |
| caption "licon.CON.2: licon must be inside li as well as diff or poly" |
| not licon ( and li ( or diffi polyi ) ) |
| } |
| rule "NTMdrop.CON.3" { |
| caption "NTMdrop.CON.3: NTMdrop must be enclosed by COREID" |
| not NTMdrop COREID |
| } |
| rule "LVTNMdrop.CON.3" { |
| caption "LVTNMdrop.CON.3: LVTNMdrop must be enclosed by COREID" |
| not LVTNMdrop COREID |
| } |
| rule "HVTPMdrop.CON.3" { |
| caption "HVTPMdrop.CON.3: HVTPMdrop must be enclosed by COREID" |
| not HVTPMdrop COREID |
| } |
| rule "LI1Mdrop.CON.3" { |
| caption "LI1Mdrop.CON.3: LI1Mdrop must be enclosed by COREID" |
| not LI1Mdrop COREID |
| } |
| rule "LICM1drop.CON.3" { |
| caption "LICM1drop.CON.3: LICM1drop must be enclosed by COREID" |
| not LICM1drop COREID |
| } |
| rule "PSDMdrop.CON.3" { |
| caption "PSDMdrop.CON.3: PSDMdrop must be enclosed by COREID" |
| not PSDMdrop COREID |
| } |
| rule "NSDMdrop.CON.3" { |
| caption "NSDMdrop.CON.3: NSDMdrop must be enclosed by COREID" |
| not NSDMdrop COREID |
| } |
| rule "P1Mdrop.CON.3" { |
| caption "P1Mdrop.CON.3: P1Mdrop must be enclosed by COREID" |
| not P1Mdrop COREID |
| } |
| rule "NTMadd.CON.3" { |
| caption "NTMadd.CON.3: NTMadd must be enclosed by COREID" |
| not NTMadd COREID |
| } |
| rule "LVTNMadd.CON.3" { |
| caption "LVTNMadd.CON.3: LVTNMadd must be enclosed by COREID" |
| not LVTNMadd COREID |
| } |
| rule "HVTPMadd.CON.3" { |
| caption "HVTPMadd.CON.3: HVTPMadd must be enclosed by COREID" |
| not HVTPMadd COREID |
| } |
| rule "LI1Madd.CON.3" { |
| caption "LI1Madd.CON.3: LI1Madd must be enclosed by COREID" |
| not LI1Madd COREID |
| } |
| rule "LICM1add.CON.3" { |
| caption "LICM1add.CON.3: LICM1add must be enclosed by COREID" |
| not LICM1add COREID |
| } |
| rule "PSDMadd.CON.3" { |
| caption "PSDMadd.CON.3: PSDMadd must be enclosed by COREID" |
| not PSDMadd COREID |
| } |
| rule "NSDMadd.CON.3" { |
| caption "NSDMadd.CON.3: NSDMadd must be enclosed by COREID" |
| not NSDMadd COREID |
| } |
| rule "P1Madd.CON.3" { |
| caption "P1Madd.CON.3: P1Madd must be enclosed by COREID" |
| not P1Madd COREID |
| } |
| rule "FOMadd.CON.3" { |
| caption "FOMadd.CON.3: FOMadd must be enclosed by COREID" |
| not FOMadd COREID |
| } |
| rule "FOMdrop_noSeal.CON.3" { |
| caption "FOMdrop_noSeal.CON.3: FOMdrop_noSeal must be enclosed by COREID" |
| not FOMdrop_noSeal COREID |
| } |
| rule "diffres.CON.4" { |
| caption "diffres.CON.4: diffres must not overlap licon" |
| and diffres licon |
| } |
| rule "polyres.CON.4" { |
| caption "polyres.CON.4: polyres must not overlap licon" |
| and polyres licon |
| } |
| rule "pwres.CON.5" { |
| caption "pwres.CON.5: pwres must fit exactly inside nw_hole and break it into two nets" |
| not pwres nw_hole |
| not nw_hole pwres -outputlayer conn_lay_not_res_lay |
| select -touch -not pwres conn_lay_not_res_lay -eq 2 |
| edge_boolean -coincident_only -inside pwres nw_hole -outputlayer res_touch_conn |
| edge_expand res_touch_conn -inside_by 0.005 -outputlayer res_touch_conn_exp |
| size res_touch_conn_exp -by 0.05 -outputlayer res_touch_conn_exp_size |
| select -interact pwres res_touch_conn_exp_size -eq 2 -outputlayer good_res |
| not pwres good_res |
| } |
| rule "diffres.CON.5" { |
| caption "diffres.CON.5: diffres must fit exactly inside diff and break it into two nets" |
| not diffres diffi |
| not diffi diffres -outputlayer conn_lay_not_res_lay |
| select -touch -not diffres conn_lay_not_res_lay -eq 2 |
| edge_boolean -coincident_only -inside diffres diffi -outputlayer res_touch_conn |
| edge_expand res_touch_conn -inside_by 0.005 -outputlayer res_touch_conn_exp |
| size res_touch_conn_exp -by 0.05 -outputlayer res_touch_conn_exp_size |
| select -interact diffres res_touch_conn_exp_size -eq 2 -outputlayer good_res |
| not diffres good_res |
| } |
| rule "polyres.CON.5" { |
| caption "polyres.CON.5: polyres must fit exactly inside poly and break it into two nets" |
| not polyres polyi |
| not polyi polyres -outputlayer conn_lay_not_res_lay |
| select -touch -not polyres conn_lay_not_res_lay -eq 2 |
| edge_boolean -coincident_only -inside polyres polyi -outputlayer res_touch_conn |
| edge_expand res_touch_conn -inside_by 0.005 -outputlayer res_touch_conn_exp |
| size res_touch_conn_exp -by 0.05 -outputlayer res_touch_conn_exp_size |
| select -interact polyres res_touch_conn_exp_size -eq 2 -outputlayer good_res |
| not polyres good_res |
| } |
| rule "lires.CON.5" { |
| caption "lires.CON.5: lires must fit exactly inside li and break it into two nets" |
| not lires li_i |
| not li_i lires -outputlayer conn_lay_not_res_lay |
| select -touch -not lires conn_lay_not_res_lay -eq 2 |
| edge_boolean -coincident_only -inside lires li_i -outputlayer res_touch_conn |
| edge_expand res_touch_conn -inside_by 0.005 -outputlayer res_touch_conn_exp |
| size res_touch_conn_exp -by 0.05 -outputlayer res_touch_conn_exp_size |
| select -interact lires res_touch_conn_exp_size -eq 2 -outputlayer good_res |
| not lires good_res |
| } |
| rule "met1res.CON.5" { |
| caption "m1res.CON.5: m1res must fit exactly inside met1 and break it into two nets" |
| not m1res met1i |
| not met1i m1res -outputlayer conn_lay_not_res_lay |
| select -touch -not m1res conn_lay_not_res_lay -eq 2 |
| edge_boolean -coincident_only -inside m1res met1i -outputlayer res_touch_conn |
| edge_expand res_touch_conn -inside_by 0.005 -outputlayer res_touch_conn_exp |
| size res_touch_conn_exp -by 0.05 -outputlayer res_touch_conn_exp_size |
| select -interact m1res res_touch_conn_exp_size -eq 2 -outputlayer good_res |
| not m1res good_res |
| } |
| rule "met2res.CON.5" { |
| caption "m2res.CON.5: m2res must fit exactly inside met2 and break it into two nets" |
| not m2res met2i |
| not met2i m2res -outputlayer conn_lay_not_res_lay |
| select -touch -not m2res conn_lay_not_res_lay -eq 2 |
| edge_boolean -coincident_only -inside m2res met2i -outputlayer res_touch_conn |
| edge_expand res_touch_conn -inside_by 0.005 -outputlayer res_touch_conn_exp |
| size res_touch_conn_exp -by 0.05 -outputlayer res_touch_conn_exp_size |
| select -interact m2res res_touch_conn_exp_size -eq 2 -outputlayer good_res |
| not m2res good_res |
| } |
| rule "met3res.CON.5" { |
| caption "m3res.CON.5: m3res must fit exactly inside met3 and break it into two nets" |
| not m3res met3i |
| not met3i m3res -outputlayer conn_lay_not_res_lay |
| select -touch -not m3res conn_lay_not_res_lay -eq 2 |
| edge_boolean -coincident_only -inside m3res met3i -outputlayer res_touch_conn |
| edge_expand res_touch_conn -inside_by 0.005 -outputlayer res_touch_conn_exp |
| size res_touch_conn_exp -by 0.05 -outputlayer res_touch_conn_exp_size |
| select -interact m3res res_touch_conn_exp_size -eq 2 -outputlayer good_res |
| not m3res good_res |
| } |
| rule "met4res.CON.5" { |
| caption "m4res.CON.5: m4res must fit exactly inside met4 and break it into two nets" |
| not m4res met4i |
| not met4i m4res -outputlayer conn_lay_not_res_lay |
| select -touch -not m4res conn_lay_not_res_lay -eq 2 |
| edge_boolean -coincident_only -inside m4res met4i -outputlayer res_touch_conn |
| edge_expand res_touch_conn -inside_by 0.005 -outputlayer res_touch_conn_exp |
| size res_touch_conn_exp -by 0.05 -outputlayer res_touch_conn_exp_size |
| select -interact m4res res_touch_conn_exp_size -eq 2 -outputlayer good_res |
| not m4res good_res |
| } |
| rule "met5res.CON.5" { |
| caption "m5res.CON.5: m5res must fit exactly inside met5 and break it into two nets" |
| not m5res met5i |
| not met5i m5res -outputlayer conn_lay_not_res_lay |
| select -touch -not m5res conn_lay_not_res_lay -eq 2 |
| edge_boolean -coincident_only -inside m5res met5i -outputlayer res_touch_conn |
| edge_expand res_touch_conn -inside_by 0.005 -outputlayer res_touch_conn_exp |
| size res_touch_conn_exp -by 0.05 -outputlayer res_touch_conn_exp_size |
| select -interact m5res res_touch_conn_exp_size -eq 2 -outputlayer good_res |
| not m5res good_res |
| } |
| rule "licon.CON.6" { |
| caption "licon.CON.6: licon must not overlap gate" |
| and licon gate |
| } |
| rule "psdm.CON.6" { |
| caption "psdm.CON.6: psdm must not overlap nsdm" |
| and psdm nsdm |
| } |
| rule "tap.CON.7" { |
| caption "tap.CON.7: a tap must not overlap areaid:seal" |
| and tap SEALID |
| } |
| rule "poly.CON.7" { |
| caption "poly.CON.7: poly must not overlap areaid:seal" |
| and polyi SEALID |
| } |
| rule "li.CON.7" { |
| caption "li.CON.7: li must not overlap areaid:seal" |
| and li_i SEALID |
| } |
| rule "met1.CON.7" { |
| caption "met1.CON.7: met1 must not overlap areaid:seal" |
| and met1i SEALID |
| } |
| rule "met2.CON.7" { |
| caption "met2.CON.7: met2 must not overlap areaid:seal" |
| and met2i SEALID |
| } |
| rule "met3.CON.7" { |
| caption "met3.CON.7: met3 must not overlap areaid:seal" |
| and met3i SEALID |
| } |
| rule "met4.CON.7" { |
| caption "met4.CON.7: met4 must not overlap areaid:seal" |
| and met4i SEALID |
| } |
| rule "met5.CON.7" { |
| caption "met5.CON.7: met5 must not overlap areaid:seal" |
| and met5i SEALID |
| } |
| rule "diff.CON.8" { |
| caption "diff.CON.8: diff must not straddle areaid:seal" |
| select -cut diffi SEALID |
| } |
| rule "thkox.WARN.1" { |
| caption "thkox.WARN.1: Layer thkox doesn't interact with v5, v12 or v20" |
| select -interact -not thkox ( or v5 v12 v20 ) |
| } |
| rule "mcon.CON.10" { |
| caption "mcon.CON.10: mcon must be enclosed by li" |
| not mcon li |
| } |
| rule "via1.CON.10" { |
| caption "via1.CON.10: via1 outside of areaid:moduleCut should be orthogonal rectangle" |
| rect_chk -not via1 -orthogonal_only |
| } |
| rule "via2.CON.10" { |
| caption "via2.CON.10: via2 outside of areaid:moduleCut should be orthogonal rectangle" |
| rect_chk -not via2 -orthogonal_only |
| } |
| rule "via3.CON.10" { |
| caption "via3.CON.10: via3 outside of areaid:moduleCut should be orthogonal rectangle" |
| rect_chk -not via3 -orthogonal_only |
| } |
| rule "via4.CON.10" { |
| caption "via4.CON.10: via4 outside of areaid:moduleCut should be orthogonal rectangle" |
| rect_chk -not via4 -orthogonal_only |
| } |
| or COREID SEALID moduleCutAREA frameBndr -outputlayer areaid_layers |
| rule "cfom.CON.12" { |
| caption "cfom.CON.12: cfom allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only" |
| not cfom areaid_layers |
| } |
| rule "clvtnm.CON.12" { |
| caption "clvtnm.CON.12: clvtnm allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only" |
| not clvtnm areaid_layers |
| } |
| rule "chvtpm.CON.12" { |
| caption "chvtpm.CON.12: chvtpm allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only" |
| not chvtpm areaid_layers |
| } |
| rule "conom.CON.12" { |
| caption "conom.CON.12: conom allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only" |
| not conom areaid_layers |
| } |
| rule "clvom.CON.12" { |
| caption "clvom.CON.12: clvom allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only" |
| not clvom areaid_layers |
| } |
| rule "cntm.CON.12" { |
| caption "cntm.CON.12: cntm allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only" |
| not cntm areaid_layers |
| } |
| rule "chvntm.CON.12" { |
| caption "chvntm.CON.12: chvntm allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only" |
| not chvntm areaid_layers |
| } |
| rule "cnpc.CON.12" { |
| caption "cnpc.CON.12: cnpc allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only" |
| not cnpc areaid_layers |
| } |
| rule "cnsdm.CON.12" { |
| caption "cnsdm.CON.12: cnsdm allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only" |
| not cnsdm areaid_layers |
| } |
| rule "cpsdm.CON.12" { |
| caption "cpsdm.CON.12: cpsdm allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only" |
| not cpsdm areaid_layers |
| } |
| rule "cli1m.CON.12" { |
| caption "cli1m.CON.12: cli1m allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only" |
| not cli1m areaid_layers |
| } |
| rule "cviam3.CON.12" { |
| caption "cviam3.CON.12: cviam3 allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only" |
| not cviam3 areaid_layers |
| } |
| rule "cviam4.CON.12" { |
| caption "cviam4.CON.12: cviam4 allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only" |
| not cviam4 areaid_layers |
| } |
| rule "PMM2mk.CON.12" { |
| caption "PMM2mk.CON.12: PMM2mk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only" |
| not PMM2mk areaid_layers |
| } |
| rule "CU1Mmk.CON.12" { |
| caption "CU1Mmk.CON.12: CU1Mmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only" |
| not CU1Mmk areaid_layers |
| } |
| rule "RPMmk.CON.12" { |
| caption "RPMmk.CON.12: RPMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only" |
| not RPMmk areaid_layers |
| } |
| rule "PBOmk.CON.12" { |
| caption "PBOmk.CON.12: PBOmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only" |
| not PBOmk areaid_layers |
| } |
| rule "PDMmk.CON.12" { |
| caption "PDMmk.CON.12: PDMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only" |
| not PDMmk areaid_layers |
| } |
| rule "NSMmk.CON.12" { |
| caption "NSMmk.CON.12: NSMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only" |
| not NSMmk areaid_layers |
| } |
| rule "MM5mk.CON.12" { |
| caption "MM5mk.CON.12: MM5mk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only" |
| not MM5mk areaid_layers |
| } |
| rule "VIM4mk.CON.12" { |
| caption "VIM4mk.CON.12: VIM4mk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only" |
| not VIM4mk areaid_layers |
| } |
| rule "MM4mk.CON.12" { |
| caption "MM4mk.CON.12: MM4mk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only" |
| not MM4mk areaid_layers |
| } |
| rule "VIM3mk.CON.12" { |
| caption "VIM3mk.CON.12: VIM3mk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only" |
| not VIM3mk areaid_layers |
| } |
| rule "MM3mk.CON.12" { |
| caption "MM3mk.CON.12: MM3mk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only" |
| not MM3mk areaid_layers |
| } |
| rule "VIM2mk.CON.12" { |
| caption "VIM2mk.CON.12: VIM2mk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only" |
| not VIM2mk areaid_layers |
| } |
| rule "MM2mk.CON.12" { |
| caption "MM2mk.CON.12: MM2mk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only" |
| not MM2mk areaid_layers |
| } |
| rule "VIMmk.CON.12" { |
| caption "VIMmk.CON.12: VIMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only" |
| not VIMmk areaid_layers |
| } |
| rule "MM1mk.CON.12" { |
| caption "MM1mk.CON.12: MM1mk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only" |
| not MM1mk areaid_layers |
| } |
| rule "CTM1mk.CON.12" { |
| caption "CTM1mk.CON.12: CTM1mk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only" |
| not CTM1mk areaid_layers |
| } |
| rule "LI1Mmk.CON.12" { |
| caption "LI1Mmk.CON.12: LI1Mmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only" |
| not LI1Mmk areaid_layers |
| } |
| rule "LICM1mk.CON.12" { |
| caption "LICM1mk.CON.12: LICM1mk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only" |
| not LICM1mk areaid_layers |
| } |
| rule "PSDMmk.CON.12" { |
| caption "PSDMmk.CON.12: PSDMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only" |
| not PSDMmk areaid_layers |
| } |
| rule "NSDMmk.CON.12" { |
| caption "NSDMmk.CON.12: NSDMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only" |
| not NSDMmk areaid_layers |
| } |
| rule "LDNTMmk.CON.12" { |
| caption "LDNTMmk.CON.12: LDNTMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only" |
| not LDNTMmk areaid_layers |
| } |
| rule "NPCMmk.CON.12" { |
| caption "NPCMmk.CON.12: NPCMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only" |
| not NPCMmk areaid_layers |
| } |
| rule "HVNTMmk.CON.12" { |
| caption "HVNTMmk.CON.12: HVNTMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only" |
| not HVNTMmk areaid_layers |
| } |
| rule "NTMmk.CON.12" { |
| caption "NTMmk.CON.12: NTMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only" |
| not NTMmk areaid_layers |
| } |
| rule "P1Mmk.CON.12" { |
| caption "P1Mmk.CON.12: P1Mmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only" |
| not P1Mmk areaid_layers |
| } |
| rule "LVOMmk.CON.12" { |
| caption "LVOMmk.CON.12: LVOMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only" |
| not LVOMmk areaid_layers |
| } |
| rule "ONOMmk.CON.12" { |
| caption "ONOMmk.CON.12: ONOMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only" |
| not ONOMmk areaid_layers |
| } |
| rule "TUNMmk.CON.12" { |
| caption "TUNMmk.CON.12: TUNMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only" |
| not TUNMmk areaid_layers |
| } |
| rule "HVTRMmk.CON.12" { |
| caption "HVTRMmk.CON.12: HVTRMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only" |
| not HVTRMmk areaid_layers |
| } |
| rule "HVTPMmk.CON.12" { |
| caption "HVTPMmk.CON.12: HVTPMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only" |
| not HVTPMmk areaid_layers |
| } |
| rule "LVTNMmk.CON.12" { |
| caption "LVTNMmk.CON.12: LVTNMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only" |
| not LVTNMmk areaid_layers |
| } |
| rule "NWMmk.CON.12" { |
| caption "NWMmk.CON.12: NWMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only" |
| not NWMmk areaid_layers |
| } |
| rule "DNMmk.CON.12" { |
| caption "DNMmk.CON.12: DNMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only" |
| not DNMmk areaid_layers |
| } |
| rule "FOMmk.CON.12" { |
| caption "FOMmk.CON.12: FOMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only" |
| not FOMmk areaid_layers |
| } |
| rule "localsub.CON.1" { |
| caption "localsub.CON.1: ptap must not straddle local sub layer" |
| select -cut PTAP localSub |
| } |
| inside_cell npn "npn_1x1" "npn_1x1_v5" "npn_1x2" -outputlayer valid_npn |
| rule "npn.CON.1" { |
| caption "npn.CON.1: Layer npn can only be used inside cell npn_1x1, npn_1x1_v5 or npn_1x2" |
| not npn valid_npn |
| } |
| inside_cell pnp "pnp" "pnp_5x" -outputlayer valid_pnp |
| rule "pnp.CON.1" { |
| caption "pnp.CON.1: Layer pnp can only be used inside cell pnp2 or pnp_5x" |
| not pnp valid_pnp |
| } |
| |
| |
| // |
| // hvtp checks |
| // |
| |
| |
| |
| and GATE PDIFF -outputlayer PFETa |
| not PFETa COREID -outputlayer PFET_PERI |
| rule "hvtp.WID.1" { |
| caption "hvtp.WID.1: Min width of hvtp < 0.38" |
| inte hvtp -lt 0.38 -abut -lt 90 -single_point -output region |
| } |
| rule "hvtp.SP.1" { |
| caption "hvtp.SP.1: Min spacing/notch of hvtp < 0.38" |
| exte hvtp -lt 0.38 -abut -lt 90 -single_point -output region |
| } |
| rule "hvtp.ENC.1" { |
| caption "hvtp.ENC.1: Min enclosure of pfet not in areaid:core by hvtp < 0.18" |
| enc ( and PFET_PERI hvtp ) hvtp -lt 0.18 -measure all -abut -lt 90 -single_point -output region |
| } |
| rule "hvtp.SP.2" { |
| caption "hvtp.SP.2: Min spacing of pfet not in areaid:core to hvtp < 0.18" |
| exte PFET_PERI hvtp -lt 0.18 -abut -lt 90 -single_point -output region |
| } |
| rule "hvtp.AR.1" { |
| caption "hvtp.AR.1: Min area of hvtp < 0.265" |
| area hvtp -lt 0.265 |
| } |
| rule "hvtp.AR.2" { |
| caption "hvtp.AR.2: Min area of hvtpHole < 0.265" |
| area ( holes hvtp ) -lt 0.265 |
| } |
| rule "hvtp.ENC.2" { |
| caption "hvtp.ENC.2: Min/Max enclosure of nwell by hvtp in areaid:core == 0" |
| not ( select -interact hvtp_CORE ( and hvtp_CORE nwell ) ) nwell |
| } |
| |
| |
| // |
| // hvtr checks |
| // |
| |
| |
| |
| rule "hvtr.WID.1" { |
| caption "hvtr.WID.1: Min width of hvtr < 0.38" |
| inte hvtr -lt 0.38 -abut -lt 90 -single_point -output region |
| } |
| rule "hvtr.SP.1" { |
| caption "hvtr.SP.1: Min. spacing of hvtr to hvtp < 0.38" |
| exte hvtr hvtp -lt 0.38 -abut -lt 90 -single_point -output region |
| } |
| rule "hvtr.CON.1" { |
| caption "hvtr.CON.1: hvtr must not overlap hvtp" |
| and hvtr hvtp |
| } |
| rule "hvtr.ENC.1" { |
| caption "hvtr.ENC.1: Min enclosure of PFET by hvtr < 0.18" |
| enc PFETa hvtr -lt 0.18 -measure all -abut -lt 90 -single_point -output region |
| } |
| |
| |
| // |
| // lvtn checks |
| // |
| |
| |
| |
| not nwell v5 -outputlayer lvNwell_drc |
| and poly lvNwell_drc -outputlayer PolyLvNwell |
| and tap lvNwell_drc -outputlayer lvNtap |
| not ( and PolylvNwell lvNtap ) COREID -outputlayer varChannel_drc |
| not lvNwell_drc ( select -interact lvNwell_drc ( and lvNwell_drc varChannel_drc ) ) -outputlayer LVnwellnovarChannel |
| select -enclose lvtn PDIFF -outputlayer lvtEncPDiff |
| not diff_PERI lvtn_PERI -outputlayer periDiffNoLvt |
| and lvtn GATE -outputlayer lvtGate |
| select -inside -not ( not nwell ( select -interact nwell ( and nwell varChannel_drc ) ) ) lvtn -outputlayer nwellNoVarac |
| select -inside nwell COREID -outputlayer coreNwell |
| holes lvtn -outputlayer lvtnHoles |
| not gate_PERI v20 -outputlayer GATE_PERI_non_v20 |
| rule "lvtn.WID.1" { |
| caption "lvtn.WID.1: Min width of lvtn < 0.38" |
| inte lvtn -lt 0.38 -abut -lt 90 -single_point -output region |
| } |
| rule "lvtn.SP.1" { |
| caption "lvtn.SP.1: Min spacing/notch of lvtn < 0.38" |
| exte lvtn -lt 0.38 -abut -lt 90 -single_point -output region |
| } |
| rule "lvtn.SP.2" { |
| caption "lvtn.SP.2: Min spacing of lvtn to gate. Rule exempted inside v20 and outside areaid:core < 0.18" |
| exte GATE_PERI_non_v20 lvtn_PERI -lt 0.18 -abut -lt 90 -single_point -output region |
| } |
| rule "lvtn.SP.3" { |
| caption "lvtn.SP.3: Min spacing of lvtn not in areaid:core to pfet along S/D direction < 0.19" |
| exte ( edge_boolean -coincident_only -outside ( select -interact -not pgate lvtn ) psrcdrn ) lvtn -lt 0.19 -abut -lt 90 -output region |
| } |
| not ( and diffi polyi ) ( or COREID v20 ) -outputlayer non_20v_gate_peri |
| rule "lvtn.ENC.1" { |
| caption "lvtn.ENC.1: Min enclosure of gate not in areaid:core or v20 by lvtn not in areaid:core < 0.18" |
| enc non_20v_gate_peri lvtn_PERI -lt 0.18 -measure all -abut -lt 90 -single_point -output region |
| } |
| rule "lvtn.SP.4" { |
| caption "lvtn.SP.4: Min spacing of lvtn & hvtp < 0.38" |
| exte lvtn hvtp -lt 0.38 -abut -lt 90 -single_point -output region |
| } |
| rule "lvtn.OVL.1" { |
| caption "lvtn.OVL.1: lvtn must not overlap hvtp" |
| and lvtn hvtp |
| } |
| rule "lvtn.ENC.2" { |
| caption "lvtn.ENC.2: Min enclosure of lvtn by (nwell not overlapping Var_channel) (exclude coincident edges) < 0.38" |
| select -touch -not ( enc lvtn nwellNoVarac -lt 0.38 -output region ) nwellNoVarac |
| } |
| rule "lvtn.SP.5" { |
| caption "lvtn.SP.5: Min spacing of lvtn & nwell in areaid:core < 0.38" |
| exte lvtn coreNwell -lt 0.38 -abut -lt 90 -single_point -output region |
| } |
| rule "lvtn.AR.1" { |
| caption "lvtn.AR.1: Min area of lvtn < 0.265" |
| area lvtn -lt 0.265 |
| } |
| rule "lvtn.AR.2" { |
| caption "lvtn.AR.2: Min area of lvtn Holes < 0.265" |
| area lvtnHoles -lt 0.265 |
| } |
| |
| |
| // |
| // diff checks |
| // |
| |
| |
| |
| inte diffi -lt 0.15 -abut -lt 90 -single_point -output region -outputlayer tmp1Diff |
| inte ( not diffi COREID ) -lt 0.15 -abut -lt 90 -single_point -output region -outputlayer tmp2Diff |
| edge_boolean -outside diff tap -outputlayer diffEdge |
| select -inside ntap nwell -outputlayer ntapTouchNwell |
| select -inside nwell ntap -outputlayer nwellTouchNtap |
| select -inside ( holes ndiff ) ( or ntapTouchNwell nwellTouchNtap ) -outputlayer ntapnwellInNdiff |
| and ESDID ( and ntapTouchNwell ntapnwellInNdiff ) -outputlayer ESD_nwell_tap |
| not nwell ESD_nwell_tap -outputlayer nwell_noesd |
| not diff ESD_nwell_tap -outputlayer diff_noesd |
| not tap ESD_nwell_tap -outputlayer tap_noesd |
| edge_select -coincident_only tap_noesd diff_noesd -outputlayer tabut_edge |
| edge_select -coincident_only diff_noesd tap_noesd -outputlayer dabut_edge |
| rule "diff.WID.1" { |
| caption "diff.WID.1: Min width of diff crossing areaid:core < 0.15" |
| size ( select -inside tmp2Diff ( select -cut tmp1Diff COREID ) ) -by 0.005 -inside_of tmp1Diff -step 0.15 |
| } |
| rule "diff.WID.2" { |
| caption "diff.WID.2: Min width of diff inside periphery < 0.15" |
| select -outside tmp1Diff COREID |
| } |
| rule "diff.WID.3" { |
| caption "diff.WID.3: Min width of diff inside areaid:core < 0.14" |
| select -inside ( inte ( and diffi COREID ) -lt 0.14 -abut -lt 90 -single_point -output region ) COREID |
| } |
| inte tap -lt 0.15 -abut -lt 90 -single_point -output region -outputlayer tmp1DiffTap |
| rule "diff.WID.4" { |
| caption "diff.WID.4: Min width of tap crossing areaid:core < 0.15" |
| size ( select -inside ( inte ( not tap COREID ) -lt 0.15 -abut -lt 90 -single_point -output region ) ( select -cut tmp1DiffTap COREID ) ) -by 0.005 -inside_of tmp1DiffTap -step 0.15 |
| } |
| rule "diff.WID.5" { |
| caption "diff.WID.5: Min width of tap inside periphery < 0.15" |
| select -outside tmp1DiffTap COREID |
| } |
| rule "diff.WID.6" { |
| caption "diff.WID.6: Min width of tap inside areaid:core < 0.14" |
| select -inside ( inte tap -lt 0.14 -abut -lt 90 -single_point -output region ) COREID |
| } |
| rule "diff.WID.7" { |
| caption "diff.WID.7: Min width of gate outside areaid:standardc < 0.42" |
| inte ( edge_boolean -coincident_only -inside ( not GATE_PERI STDCID ) diff ) -lt 0.42 -abut -lt 90 -output region -metric opposite |
| } |
| rule "diff.WID.8" { |
| caption "diff.WID.8: Min width of gate inside areaid:standardc < 0.36" |
| inte ( edge_boolean -coincident_only -inside ( and GATE_PERI STDCID ) diff ) -lt 0.36 -abut -lt 90 -output region -metric opposite |
| } |
| rule "diff.SP.1" { |
| caption "diff.SP.1: Min spacing/notch of diff < 0.27" |
| exte diffi -lt 0.27 -abut -lt 90 -single_point -output region |
| } |
| rule "diff.WID.9" { |
| caption "diff.WID.9: Min width of tap butting diff < 0.29" |
| enc ( edge_boolean -coincident_only -outside diff tap ) tap -lt 0.29 -abut -lt 90 -measure coin -output region |
| } |
| rule "diff.WID.10" { |
| caption "diff.WID.10: Min width of tap in periphery butting and between diff < 0.40" |
| inte ( edge_boolean -coincident_only -outside tap_PERI diff ) -lt 0.40 -abut -lt 90 -output region |
| } |
| rule "diff.WARN.2" { |
| caption "diff.WARN.2: diff and tap are not allowed to extend beyond their abutting edge" |
| or ( edge_expand ( edge_boolean -outside ( edge_select -coincident_only tap diff ) diff ) -outside_by 0.005 ) ( edge_expand ( edge_boolean -outside ( edge_select -coincident_only diff tap ) tap ) -outside_by 0.005 ) |
| } |
| rule "diff.SP.2" { |
| caption "diff.SP.2: Min spacing of diff butting edge to non-coincident diff edge < 0.13" |
| or ( exte nsdm ( and diffi psdm ) -lt 0.13 -metric opposite -para ONLY -output region ) ( exte psdm ( and diffi nsdm ) -lt 0.13 -metric opposite -para ONLY -output region ) |
| } |
| rule "diff.ENC.1" { |
| caption "diff.ENC.1: Min enclosure of pdiff in periphery outside areaid:esd or v20 by nwell < 0.18" |
| enc ( and ( not PDIFF_PERI ( or ( or ESD_nwell_tap ENID ) v20 ) ) nwell ) nwell -lt 0.18 -measure all -abut -lt 90 -single_point -output region |
| } |
| rule "diff.SP.3" { |
| caption "diff.SP.3: Min spacing of ndiff outside (areaid:esd or v20) or nwell outside areaid:esd < 0.34" |
| exte ( not NDIFF_PERI ( or ESD_nwell_tap ENID ) ) nwell_noesd -lt 0.34 -abut -lt 90 -single_point -output region |
| } |
| rule "diff.ENC.2" { |
| caption "diff.ENC.2: Min enclosure of ntap outside areaid:esd or v20 by nwell < 0.18" |
| enc ( and ( not NTAP_PERI ( or ESD_nwell_tap v20 ) ) nwell ) nwell -lt 0.18 -measure all -abut -lt 90 -single_point -output region |
| } |
| rule "diff.SP.4" { |
| caption "diff.SP.4: Min spacing of ptap outside v20 to nwell < 0.13" |
| exte ( not PTAP v20 ) nwell -lt 0.13 -abut -lt 90 -single_point -output region |
| } |
| rule "diff.WID.11" { |
| caption "diff.WID.11: Min width of gate in areaid:core < 0.14" |
| inte ( edge_boolean -coincident_only -inside emosgate_CORE diff ) -lt 0.14 -abut -lt 90 -output region |
| } |
| rule "diff.WID.12" { |
| caption "diff.WID.12: Min width of tap in areaid:core butting & between diff < 0.38" |
| inte ( edge_boolean -coincident_only -outside tap_CORE diff ) -lt 0.38 -abut -lt 90 -output region |
| } |
| rule "diff.ENC.3" { |
| caption "diff.ENC.3: Min enclosure of pdiff in areaid:core by nwell < 0.15" |
| enc ( and pdiff_CORE nwell ) nwell -lt 0.15 -measure all -abut -lt 90 -single_point -output region |
| } |
| rule "diff.ENC.4" { |
| caption "diff.ENC.4: Min enclosure of ntap in areaid:core by nwell < 0.15" |
| enc ( and NTAP_CORE nwell ) nwell -lt 0.15 -measure all -abut -lt 90 -single_point -output region |
| } |
| rule "diff.ENC.5" { |
| caption "diff.ENC.5: Min enclosure of adjacent sides of pdiff in areaid:core by nwell < 0.18" |
| rect_chk -not ( edge_expand ( enc pdiff_CORE nwell -lt 0.18 -abut -lt 90 -para -measure all -project -gt 0 -output positive1 ) -inside_by 0.005 ) -orthogonal_only |
| } |
| rule "diff.ENC.6" { |
| caption "diff.ENC.6: Min enclosure of adjacent sides of ndiff in areaid:core by pwell < 0.34" |
| rect_chk -not ( edge_expand ( enc ndiff_CORE pwell -lt 0.34 -abut -lt 90 -para -measure all -project -gt 0 -output positive1 ) -inside_by 0.005 ) -orthogonal_only |
| } |
| rule "diff.SP.5" { |
| caption "diff.SP.5: Min spacing of ndiff in areaid:core & nwell < 0.32" |
| exte ndiff_CORE nwell -lt 0.32 -abut -lt 90 -single_point -output region |
| } |
| rule "diff.SP.6" { |
| caption "diff.SP.6: Min spacing of pwbm and diff not in v20 < 0.5" |
| exte pwbm ( not diff v20 ) -lt 0.5 -abut -lt 90 -single_point -output region |
| } |
| |
| |
| // |
| // NSDM and PSDM checks |
| // |
| |
| |
| |
| copy 4002 -outputlayer ZENERID |
| and poly ENID -outputlayer ENIDgate |
| select -interact diff ENIDgate -outputlayer ENIDsource |
| select -interact -not NDIFF ENIDgate -outputlayer ENIDNsource |
| not pDiffTap ( or ENIDsource ZENERID ) -outputlayer pDiffTapNotENIDsource |
| not ( not ndiffTap ENIDsource ) SEALID_6um -outputlayer nDiffTapNotENIDsource |
| not nDiffTapNotENIDsource ( or gated_npn ZENERID ) -outputlayer nDiffTapNotENIDsource_not_gated_npn |
| not nsdm ZENERID -outputlayer nsdmFoo |
| not psdm ZENERID -outputlayer psdmFoo |
| inte nsdm -lt 0.38 -abut -lt 90 -single_point -output region -outputlayer nsdm_width |
| rule "nsdm.WID.1" { |
| caption "nsdm.WID.1: Min width of nsdm across areaid:core < 0.38" |
| size ( select -inside ( inte ( not nsdm COREID ) -lt 0.38 -abut -lt 90 -single_point -output region ) ( select -cut nsdm_width COREID ) ) -by 0.005 -inside_of nsdm_width -step 0.38 |
| } |
| rule "nsdm.WID.2" { |
| caption "nsdm.WID.2: Min width of nsdm in PERI < 0.38" |
| select -outside nsdm_width COREID |
| } |
| rule "nsdm.WID.3" { |
| caption "nsdm.WID.3: Min width of nsdm in COREID < 0.29" |
| select -inside ( inte nsdm -lt 0.29 -abut -lt 90 -single_point -output region ) COREID |
| } |
| rule "nsdm.SP.1" { |
| caption "nsdm.SP.1: Min spacing/notch of nsdm in periphery < 0.38" |
| exte nsdm_PERI -lt 0.38 -abut -lt 90 -single_point -output region |
| } |
| rule "nsdm.SP.2" { |
| caption "nsdm.SP.2: Min spacing of nsdm across areaid:core boundary < 0.38" |
| exte nsdm_CORE nsdm_PERI -ltgt 0 0.38 -abut -ltgt 0 90 -single_point -output region |
| } |
| not ( and nsdm diffi ) ( select -inside ( and ( and diffi v5 ) thkox ) npn ) -outputlayer diff2chk |
| rule "nsdm.ENC.1" { |
| caption "nsdm.ENC.1: Min enclosure of n+ diff by nsdm < 0.125" |
| edge_boolean -outside ( enc diff2chk nsdm -lt 0.125 -single_point -measure all -abut -lt 90 -output positive1 ) tap |
| } |
| rule "nsdm.ENC.2" { |
| caption "nsdm.ENC.2: Min enclosure of n+ tap in peri by nsdm < 0.125" |
| edge_boolean -outside ( enc NTAP_PERI nsdm -lt 0.125 -single_point -measure all -abut -lt 90 -output positive1 ) diff |
| } |
| rule "nsdm.SP.3" { |
| caption "nsdm.SP.3: Min spacing of nsdm & opposite implant diff or tap < 0.13" |
| exte nsdm diffTap -lt 0.13 -abut -lt 90 -single_point -output region |
| } |
| rule "nsdm.OVL.1" { |
| caption "nsdm.OVL.1: nsdm must not overlap pdiff/ptap (source of extendedDrain fet exempted)" |
| and nsdm pDiffTapNotENIDsource |
| } |
| rule "nsdm.AR.1" { |
| caption "nsdm.AR.1: Min area of nsdm < 0.265" |
| area nsdm -lt 0.265 |
| } |
| rule "nsdm.AR.2" { |
| caption "nsdm.AR.2: Min area of nsdmHole < 0.265" |
| area ( not ( holes nsdm ) nsdm ) -lt 0.265 |
| } |
| rule "nsdm.WID.4" { |
| caption "nsdm.WID.4: Min width of nsdm (opposite parallel) < 0.38" |
| select -inside ( inte nsdm -lt 0.38 -metric opposite -para ONLY -output region ) COREID |
| } |
| rule "nsdm.SP.4" { |
| caption "nsdm.SP.4: Min spacing/notch of nsdm in areaid:core (opposite parallel) < 0.38" |
| exte nsdm_CORE -lt 0.38 -output region -para ONLY -metric opposite |
| } |
| rule "nsdm.SP.5" { |
| caption "nsdm.SP.5: Min spacing/notch of nsdm in areaid:core < 0.29" |
| exte nsdm_CORE -lt 0.29 -abut -lt 90 -single_point -output region |
| } |
| rule "nsdm.ENC.3" { |
| caption "nsdm.ENC.3: Min enclosure of n+ tap in areaid:core by nsdm < 0.13" |
| edge_boolean -outside ( enc NTAP_CORE nsdm -lt 0.13 -single_point -measure all -abut -ltgt 0 90 -output positive1 ) diff |
| } |
| inte psdm -lt 0.38 -abut -lt 90 -single_point -output region -outputlayer psdm_width |
| rule "psdm.WID.1" { |
| caption "psdm.WID.1: Min width of psdm across areaid:core < 0.38" |
| size ( select -inside ( not psdm COREID ) ( select -cut psdm_width COREID ) ) -by 0.005 -inside_of psdm_width -step 0.38 |
| } |
| rule "psdm.WID.2" { |
| caption "psdm.WID.2: Min width of psdm in PERI < 0.38" |
| select -outside psdm_width COREID |
| } |
| rule "psdm.WID.3" { |
| caption "psdm.WID.3: Min width of psdm in COREID < 0.29" |
| select -inside ( inte psdm -lt 0.29 -abut -lt 90 -single_point -output region ) COREID |
| } |
| rule "psdm.SP.1" { |
| caption "psdm.SP.1: Min spacing/notch of psdm in periphery < 0.38" |
| exte psdm_PERI -lt 0.38 -abut -lt 90 -single_point -output region |
| } |
| rule "psdm.SP.2" { |
| caption "psdm.SP.2: Min spacing of psdm across areaid:core boundary < 0.38" |
| exte psdm_CORE psdm_PERI -ltgt 0 0.38 -abut -ltgt 0 90 -single_point -output region |
| } |
| rule "psdm.ENC.1" { |
| caption "psdm.ENC.1: Min enclosure of p+ diff by psdm < 0.125" |
| edge_boolean -outside ( enc PDIFF psdm -lt 0.125 -single_point -measure all -abut -lt 90 -output positive1 ) tap |
| } |
| rule "psdm.ENC.2" { |
| caption "psdm.ENC.2: Min enclosure of p+ tap in peri by psdm < 0.125" |
| edge_boolean -outside ( enc PTAP_PERI psdm -lt 0.125 -single_point -measure all -abut -lt 90 -output positive1 ) diff |
| } |
| rule "psdm.SP.3" { |
| caption "psdm.SP.3: Min spacing of psdm & opposite implant diff or tap < 0.13" |
| exte psdm diffTap -lt 0.13 -abut -lt 90 -single_point -output region |
| } |
| rule "psdm.OVL.1" { |
| caption "psdm.OVL.1: psdm must not overlap ndiff/ntap (source of extendedDrain fet exempted)" |
| and psdm nDiffTapNotENIDsource |
| } |
| rule "psdm.AR.1" { |
| caption "psdm.AR.1: Min area of psdm < 0.255" |
| area psdm -lt 0.255 |
| } |
| rule "psdm.AR.2" { |
| caption "psdm.AR.2: Min area of psdmHole < 0.265" |
| area ( not ( holes psdm ) psdm ) -lt 0.265 |
| } |
| rule "psdm.WID.4" { |
| caption "psdm.WID.4: Min width of psdm (opposite parallel) < 0.38" |
| select -inside ( inte psdm -lt 0.38 -metric opposite -para ONLY -output region ) COREID |
| } |
| rule "psdm.SP.4" { |
| caption "psdm.SP.4: Min spacing/notch of psdm in areaid:core (opposite parallel) < 0.38" |
| exte psdm_CORE -lt 0.38 -output region -para ONLY -metric opposite |
| } |
| rule "psdm.SP.5" { |
| caption "psdm.SP.5: Min spacing/notch of psdm in areaid:core < 0.29" |
| exte psdm_CORE -lt 0.29 -abut -lt 90 -single_point -output region |
| } |
| rule "psdm.ENC.3" { |
| caption "psdm.ENC.3: Min enclosure of p+ tap in areaid:core by psdm < 0.12" |
| edge_boolean -outside ( enc PTAP_CORE psdm -lt 0.12 -single_point -measure all -abut -ltgt 0 90 -output positive1 ) diff |
| } |
| |
| |
| // |
| // Poly checks |
| // |
| |
| |
| |
| rule "poly.WID.1" { |
| caption "poly.WID.1: Min width of poly over diff inside thkox in periphery < 0.5" |
| inte ( inte ( edge_boolean -coincident_only poly ( and gate_PERI thkox ) ) -lt 0.5 -metric opposite -para ONLY -output region ) -lt 0.5 -abut -lt 90 -single_point -output region |
| } |
| rule "poly.CON.2" { |
| caption "poly.CON.2: gate must not straddle thkox" |
| select -cut GATE thkox |
| } |
| rule "poly.WID.2" { |
| caption "poly.WID.2: Min width of poly < 0.15" |
| inte poly -lt 0.15 -abut -lt 90 -single_point -output region |
| } |
| rule "poly.LEN.1" { |
| caption "poly.LEN.1: Min channel length of pfet overlapping lvtn < 0.35" |
| inte ( edge_boolean -coincident_only -outside ( select -interact PFETa ( and PFETa lvtn ) ) SRCDRN ) -lt 0.35 -metric opposite -para ONLY -output region |
| } |
| rule "poly.SP.1" { |
| caption "poly.SP.1: Min spacing/notch of poly in periphery < 0.21" |
| exte poly_PERI -lt 0.21 -abut -lt 90 -single_point -output region |
| } |
| rule "poly.SP.2" { |
| caption "poly.SP.2: Min spacing of poly not covered by cell sr_bltd_eq across areaid:core boundary < 0.21" |
| not poly ( extent_cell "sr_bltd_eq" -original ) -outputlayer poly2noXmt |
| exte ( and poly2noXmt COREID ) ( not poly2noXmt COREID ) -ltgt 0 0.21 -abut -ltgt 0 90 -single_point -output region |
| } |
| edge_length poly_CORE -le 0.15 -outputlayer polyGapLEedg |
| select -inside ( edge_expand polyGapLEedg -outside_by "(0.16/2)" ) ( exte polyGapLEedg -le 0.16 -metric opposite -output region ) -outputlayer polyGapGoodSp |
| rule "poly.SP.3" { |
| caption "poly.SP.3: Min spacing of poly (except for poly core gap) < 0.175" |
| select -interact -not ( exte poly_CORE -lt 0.175 -abut -lt 90 -output region -single_point ) polyGapGoodSp |
| } |
| rule "poly.SP.4" { |
| caption "poly.SP.4: Min spacing of poly for poly core gap < 0.16" |
| select -interact ( exte poly_CORE -lt 0.16 -abut -lt 90 -output region -single_point ) polyGapGoodSp |
| } |
| rule "poly.WID.3" { |
| caption "poly.WID.3: Min width of poly resistor < 0.33" |
| edge_boolean -coincident_only -outside poly polyres -outputlayer q0polyAndRes |
| edge_length q0polyAndRes -lt 0.33 -outputlayer q1polyAndRes |
| edge_expand q1polyAndRes -outside_by 0.005 -corner_fill -outputlayer q2polyAndRes |
| select -with_edge polyres ( edge_boolean -coincident_only polyres q2polyAndRes ) -outputlayer q3polyAndRes |
| edge_boolean -outside polyres poly -outputlayer q4polyAndRes |
| edge_expand q4polyAndRes -inside_by 0.16 -corner_fill -outputlayer q5polyAndRes |
| not polyres q5polyAndRes -outputlayer q6polyAndRes |
| inte q6polyAndRes -lt 0.005 -abut -lt 90 -output region -outputlayer q7polyAndRes |
| not q6polyAndRes q7polyAndRes -outputlayer q8polyAndRes |
| select -interact polyres ( and polyres q8polyAndRes ) -eq 1 -outputlayer q9polyAndRes |
| not polyres q9polyAndRes -outputlayer q10polyAndRes |
| or q3polyAndRes q10polyAndRes |
| } |
| rule "poly.SP.5" { |
| caption "poly.SP.5: Min spacing of poly in periphery & diff < 0.075" |
| exte poly_PERI diff -lt 0.075 -abut -eq 0 -output region -para ONLY |
| } |
| rule "poly.SP.6" { |
| caption "poly.SP.6: Min spacing of poly in periphery & tap < 0.055" |
| exte poly_PERI tap -lt 0.055 -abut -lt 90 -single_point -output region |
| } |
| edge_boolean -outside GATESIDE COREID -outputlayer GATESIDE_PERI |
| rule "poly.ENC.1" { |
| caption "poly.ENC.1: Min extension of diff edge butting a tap beyond gate edge in periphery < 0.3" |
| enc GATESIDE_PERI diffTapEdge -lt 0.3 -measure coin -abut -lt 90 -output region |
| } |
| rule "poly.ENC.2" { |
| caption "poly.ENC.2: Min extension of diff beyond gate edge in periphery < 0.25" |
| enc GATESIDE_PERI diff -lt 0.25 -measure coin -abut -lt 90 -output region |
| } |
| rule "poly.ENC.3" { |
| caption "poly.ENC.3: Min extension of poly beyond gate end in periphery < 0.13" |
| enc ( edge_boolean -outside GATEEND COREID ) poly -lt 0.13 -measure coin -abut -lt 90 -output region |
| } |
| rule "poly.SP.7" { |
| caption "poly.SP.7: Min spacing of high precision or high sheet poly resistor & diff < 0.48" |
| exte ( select -interact polyres ( or rpm urpm ) ) diffTap -lt 0.48 -abut -lt 90 -single_point -output region |
| } |
| rule "poly.OVL.1" { |
| caption "poly.OVL.1: poly resistor must not overlap diff or tap" |
| and polyres diffTap |
| } |
| rule "poly.SP.8" { |
| caption "poly.SP.8: Min spacing of poly resistor & poly < 0.21" |
| exte polyres poly -lt 0.21 -abut -ltgt 0 90 -single_point -output region |
| } |
| rect_chk -not ( and poly diff ) -orthogonal_only -outputlayer q1poly |
| rule "poly.OVL.2" { |
| caption "poly.OVL.2: poly must not overlap any inner corner of diff" |
| and ( exte q1poly -le 0.005 -abut -output region ) poly |
| } |
| rule "poly.ANG.1" { |
| caption "poly.ANG.1: No 90 degree bends of poly on diff" |
| inte q1poly -le 0.005 -abut -eq 90 -perp ONLY -output region -outputlayer q2poly |
| select -with_edge q2poly ( edge_boolean -coincident_only -inside q2poly diff ) -outputlayer q4poly |
| not q2poly q4poly -outputlayer q6poly |
| exte q1poly -le 0.005 -abut -eq 90 -perp ONLY -output region -outputlayer q3poly |
| select -touch q3poly diff -outputlayer q5poly |
| not q3poly q5poly -outputlayer q7poly |
| or q6poly q7poly -outputlayer q8poly |
| copy q8poly |
| } |
| rule "poly.OVL.3" { |
| caption "poly.OVL.3: poly not in nwell or v20 must not overlap a tap in the periphery" |
| extent_cell "s8fgvr_fg2n" -original -outputlayer exemptNhvnativeCell |
| not ( not poly lvNwell_drc ) ( or exemptNhvnativeCell ( or gated_npn v20 ) ) -outputlayer PolyNotLvNwell |
| not PolyNotLvNwell v20 -outputlayer PolyNotLvNwellno_v20 |
| not ( not PolyNotLvNwell v20 ) ( and npn v5 ) -outputlayer PolyNotLvNwellno_v20_not_npn_5v |
| and PolyNotLvNwellno_v20_not_npn_5v tap_PERI |
| } |
| rule "poly.OVL.4" { |
| caption "poly.OVL.4: poly must not overlap diffres" |
| and poly diffres |
| } |
| rule "poly.SP.9" { |
| caption "poly.SP.9: Min spacing of poly in areaid:core & diff < 0.03" |
| exte poly_CORE diff -lt 0.03 -abut -eq 0 -output region -para ONLY |
| } |
| rule "poly.SP.10" { |
| caption "poly.SP.10: Min spacing of poly in areaid:core & tap < 0.03" |
| exte poly_CORE tap -lt 0.03 -abut -lt 90 -single_point -output region |
| } |
| |
| |
| // |
| // coreID checks |
| // |
| |
| |
| |
| inside_cell COREID s8cell_ee_bseln s8cell_ee_cellcorn_n s8cell_ee_termcella s8cell_ee_bselp s8cell_ee_cellcorn_p s8cell_ee_termcella_int s8cell_ee_cell s8cell_ee_colend_lasta s8cell_ee_termcellb s8cell_ee_cell_int s8cell_ee_colend_lastb s8cell_ee_termcellb_int s8cell_ee_cell_last s8cell_ee_colenda s8cell_mcell4_last_int s8cell_ee_cell_last_int s8cell_ee_colendb s8sram_colenda s8sram_precharge_ce_3x s8sram_colend_cent s8sram_horstrap_opt1_blx_ce s8sram_rowend_hstrap_ce s8sram_colend s8sram_cell s8sram_hor_wlstrap_ce s8sram_cornera s8sram_precharge s8sram_precharge_ce s8sram_precharge_end_2x s8sram_corner s8sram_precharge_end s8sram_precharge_end_3x s8sram_wlstrap_ce s8sram_colenda_cent s8sram_precharge_2x s8sram_rowend_ce s8sram_horstrap_opt1_ce s8sram_precharge_3x s8sram_precharge_ce_2x s8sram_precharge_ce_via1 s8sram_precharge_ce_2x_via1 s8sram_precharge_ce_3x_via1 s8sram_precharge_end_via1 s8sram_precharge_end_2x_via1 s8sram_precharge_end_3x_via1 s8cell_col_precharge s8cell_sp_colend_opt1_ce s8cell_sp_horstrap_opt1_ce s8cell_col_precharge_ce s8cell_sp_colend_opt1a_ce s8cell_sp_horstrap_opt3_ce s8cell_col_precharge_end s8cell_sp_colend1_ce s8cell_sp_rowend_ce s8cell_sp_cell s8cell_sp_corner_ce s8cell_sp_rowend_hstrap_ce s8cell_sp_colend_ce s8cell_sp_hor_wlstrap_ce s8cell_sp_wlstrap_ce s8cell_sp_colend_cent_ce s8cell_sp_horstrap_opt1_blx_ce s8cell_tc_tech_CD_top s8cell_tc_tech_CD_lcross s8cell_tc_tech_CD_top_pcell s8nvlatch_cell1ux s8nvlatch_lvD s8nvlatch_s8cell_ee_cell s8nvlatch_cell s8nvlatch_lvC s8nvlatch_cellg s8nvlatch_cells s8nvlatch_s8cell_ee_cell_back s8cell_nvlfp_cell s8sram16x16_wlstrap_p_ce s8sram16x16_colend s8sram16x16_ctl_load_unit s8sram16x16_colend_p_cent s8sram16x16_colenda s8sram16x16_wlstrapa2x s8sram16x16_cornerb s8sram16x16_rowend_ce s8sram16x16_wlstrap2x s8sram16x16_cornera s8sram16x16_colenda_p_cent s8sram16x16_corner s8sram16x16_ctl_load s8cell_ee_colend_last s8cell_ee_colend s8cell_ee_cell s8cell_ee_corner_east s8cell_ee_cell_opt0 s8cell_ee_colend_lastb_opt0 s8cell_ee_cell_last s8cell_ee_termcellb_ref s8cell_ee_colendb s8cell_ee_cellcorn_p_ref_opt0 s8cell_ee_termcella_ref s8cell_ee_colenda s8cell_ee_colenda_opt0 s8cell_ee_rowend_west s8cell_ee_corner_east_opt0 s8cell_ee_rowend_east_opt0 s8cell_ee_cellcorn_n_ref_opt0 s8cell_ee_corner_west_opt0 s8cell_ee_colend_lasta_opt0 s8cell_ee_cell_last_opt0 s8cell_ee_cellcorn_p_ref s8cell_ee_rowend_west_opt0 s8cell_ee_termcellb_ref_opt0 s8cell_ee_corner_west s8cell_ee_colend_opt0 s8cell_ee_rowend_east s8cell_ee_cellcorn_n_ref s8cell_ee_colend_lastb s8cell_ee_termcella_ref_opt0 s8cell_ee_colenda_d s8cell_ee_colend_lasta s8cell_ee_colendb_opt0 s8cell_ee_colend_lasta_d s8cell_ee_bseln_enda_d s8cell_ee_bseln_enda_poly_d s8cell_ee_bselp_enda_d s8cell_ee_plus_1t_cell s8cell_ee_plus_rowtie_ref s8cell_ee_plus_sselptie_ref s8cell_ee_plus_sselp_ref s8cell_ee_plus_sselntie_ref s8cell_ee_plus_sseln_a s8cell_ee_plus_sseln_b s8cell_ee_plus_coltie_ref s8cell_ee_plus_corner_tie s8cell_ee_plus_sselp_a s8cell_ee_plus_sselp_b sr_blld sr_mcell_tie up_rom_tie sr_bltd_eq sr_tcell up_rom1 sr_mcell sr_tcell_tie up_romref sr_mcell_tie_L sr_mcell_tie_R sr_tcell_tie_L sr_tcell_tie_R s8tnvcell_mcell_tie_END_b_cell7 s8tnvcell_mcell_tie_END_t_cell7 s8tnvcell_tcell_END_t_cell7 s8tnvcell_tcell_END_b_cell7 s8tnvcell_mcell_tie_END_sub_t_cell7 s8tnvcell_mcell_tie_END_sub_b_cell7 s8tnvcell_tcell_tie_Rt_cell7 s8tnvcell_tcell_tie_Rb_cell7 s8tnvcell_mcell_tie_Rt_cell7 s8tnvcell_mcell_tie_Rb_cell7 s8tnvcell_mcell_Mt_cell7 s8tnvcell_mcell_Mb_cell7 s8tnvcell_mcell_t_cell7 s8tnvcell_mcell_b_cell7 s8tnvcell_tcell_t_cell7 s8tnvcell_tcell_b_cell7 s8tnvcell_mcell_tie_Lt_cell7 s8tnvcell_mcell_tie_Lb_cell7 s8tnvcell_tcell_tie_Lb_cell7 s8tnvcell_tcell_tie_Lt_cell7 s8tnvcell_tcell_tie_t_cell7 s8tnvcell_tcell_tie_b_cell7 s8tnvcell_mcell_tie_t_cell7 s8tnvcell_mcell_tie_b_cell7 s8tnvssr_bltd_eq s8tnvssr_bltd_tie s8tnvssr_blld_tie s8tnvssr_blld s8ovation_atc2_pd_12_6_BiCell -outputlayer validCoreID9 |
| inside_cell COREID ram8_buildspace s8diaet_md3235_a s8diaet_md7301_a s8diaet_md7302_a s8diaet_md7303_a s8diaet_md7304_a s8diaet_md7321_a s8diaet_md7322_a s8diaet_md7333_a s8diaet_md7334_a s8diaet_s7333_hvpmos_cap_a s8Fab_etch_a s8Fab_etch_b s8Fab_etch_c s8Fab_etch_d s8Fab_etch_e s8Fab_etch_f s8Fab_fab_fomc s8Fab_fab_li1mc s8Fab_fab_pimc s8Fab_fabCD_b s8Fab_fabCD_c s8Fab_fabCD_d s8Fab_fabCD_e s8Fab_plot_etch_a s8Fab_sem_CDcross s8Fab_tech_CD_drawn_a s8te2et_2t_cell_end01 s8te2et_2t_cell_end01_NoVia s8te2et_2t_cell_end01_sonos_Diff s8te2et_2t_cell_end01_sonos_Diff_b s8te2et_2t_cell_end01_sonos_Diff_R s8te2et_2t_cell_end02_opt1_L s8te2et_2t_cell_end02_opt1_L_b s8te2et_2t_cell_end02_opt1_R s8te2et_2t_cell_end02_opt1_R01 s8te2et_2t_cell_end02_opt2_L s8te2et_2t_cell_end02_opt2_L_b s8te2et_2t_cell_end02_opt2_L_c s8te2et_2t_cell_end02_opt2_R s8te2et_2t_cell_end02_opt2_R01 s8te2et_2t_cell_end02_opt3_L s8te2et_2t_cell_end02_opt3_L_b s8te2et_2t_cell_end02_opt3_L_c s8te2et_2t_cell_end02_opt3_R s8te2et_2t_cell_end02_opt3_R01 s8te2et_2t_cell_end02_opt4_L s8te2et_2t_cell_end02_opt4_L_c s8te2et_2t_cell_end02_opt4_R s8te2et_2t_cell_end02_opt4_R01 s8te2et_2t_cell_end02_sonos_Diff s8te2et_2t_cell_end02_sonos_Diff_b s8te2et_2t_cell_end02_sonos_Diff_L s8te2et_2t_cell_end02_sonos_Diff_L_b s8te2et_2t_cell_end02_sonos_Diff_R s8te2et_2t_cell_option1_swap s8te2et_2t_cell_option1_swap_b s8te2et_2t_cell_option1_swap_ncBot s8te2et_2t_cell_option1_swap_ncBot_b s8te2et_2t_cell_option1_swap_ncTop s8te2et_2t_cell_option1_swap_ncTop_b s8te2et_2t_cell_option2_swap s8te2et_2t_cell_option2_swap_b s8te2et_2t_cell_option2_swap_ncBot s8te2et_2t_cell_option2_swap_ncBot_b s8te2et_2t_cell_option2_swap_ncTop s8te2et_2t_cell_option2_swap_ncTop_b s8te2et_2t_cell_option3_swap s8te2et_2t_cell_option3_swap_b s8te2et_2t_cell_option3_swap_c s8te2et_2t_cell_option3_swap_ncTop s8te2et_2t_cell_option3_swap_ncTop_b s8te2et_2t_cell_option3_swap_ncTop_c s8te2et_2t_cell_option3_swap1_ncBot s8te2et_2t_cell_option3_swap1_ncBot_b s8te2et_2t_cell_option3_swap1_ncBot_c s8te2et_2t_cell_option4_swap s8te2et_2t_cell_option4_swap_c s8te2et_2t_cell_option4_swap_ncBot s8te2et_2t_cell_option4_swap_ncBot_c s8te2et_2t_cell_option4_swap_ncTop s8te2et_2t_cell_option4_swap_ncTop_c s8te2et_2t_cell_sonos_Diff_swap s8te2et_2t_cell_sonos_Diff_swap_b s8te2et_2t_cell_sonos_Diff_swap_ncTop s8te2et_2t_cell_sonos_Diff_swap_ncTop_b s8te2et_2t_cell_sonos_Diff_swap1_ncBot s8te2et_2t_cell_sonos_Diff_swap1_ncBot_b s8te2et_2t_cell_sonos_Diff_swapR s8te2et_2t_cell_sonos_Diff_swapR_b s8te2et_2t_cellcrnr_L s8te2et_2t_cellcrnr_R s8te2et_md1005_a s8te2et_md1092_a s8te2et_md1701_a -outputlayer validCoreID1 |
| inside_cell COREID s8te2et_md1702_a s8te2et_md1702_b s8te2et_md1703_a s8te2et_md1705_a s8te2et_md1773_a s8te2et_md3235_a s8te2et_md3242_b s8te2et_md3244_b s8te2et_md3248_d s8te2et_md3251_b s8te2et_md3277_b s8te2et_md3288_b s8te2et_md3288_c s8te2et_md7301_a s8te2et_md7302_a s8te2et_md7303_a s8te2et_md7304_a s8te2et_md8111_a s8te2et_md8113_a s8te2et_PassGate_sonos_Fet_novia s8te2et_s_hv_depmos_dieler_opt1 s8te2et_s_hv_depmos_dieler_opt2 s8te2et_s_hv_depmos_dieler_opt3 s8te2et_s0755_rowend_1 s8te2et_s0790_cell_1 s8te2et_s0790_cell_2 s8te2et_s0790_colend_1 s8te2et_s0791_cell_1 s8te2et_s0791_colend_1 s8te2et_s0791_rowend_1 s8te2et_s1700_hier0_basecell_a s8te2et_s1700_hier0_basecell_b s8te2et_s1700_hier0_bot_basecell_a s8te2et_s1700_hier0_corner_a s8te2et_s1700_hier0_elem_a s8te2et_s1700_hier0_elem_b s8te2et_s1700_hier0_left_a s8te2et_s1700_hier0_rcorner_a s8te2et_s1700_hier0_right_a s8te2et_s1700_hier0_top_basecell_a s8te2et_s1701_hier0_base_cell_a s8te2et_s1701_hier0_bot_con_a s8te2et_s1701_hier0_corner_a s8te2et_s1701_hier0_lft_con_a s8te2et_s1701_hier0_rht_con_a s8te2et_s1701_hier0_top_con_a s8te2et_s1702_hier0_base_cell_a s8te2et_s1702_hier0_base_cell_b s8te2et_s1702_hier0_bot_a s8te2et_s1702_hier0_corner_l_a s8te2et_s1702_hier0_corner_r_a s8te2et_s1702_hier0_left_a s8te2et_s1702_hier0_right_a s8te2et_s1702_hier0_top_a s8te2et_s1703_hier0_base_cell_a s8te2et_s1703_hier0_bot_con_a s8te2et_s1703_hier0_corner_a s8te2et_s1703_hier0_lft_con_a s8te2et_s1703_hier0_rht_con_a s8te2et_s1703_hier0_top_con_a s8te2et_s1705_hier0_base_cell_a s8te2et_s1709_hier0_base_cell_a s8te2et_s1709_hier0_lft_con_a s8te2et_s1709_hier0_rht_con_a s8te2et_s1709_hier0_top_con_a s8te2et_s1726_hier0_base_cell_a s8te2et_s1726_hier0_base_cell_b s8te2et_s1726_hier0_lft_con_a s8te2et_s1726_hier0_rht_con_b s8te2et_s1726_hier1_array_b s8te2et_s1726_hier1_array_c s8te2et_s1726_hier1_array_d s8te2et_s1726_hier2_array_a s8te2et_s1743_hier0_base_cell_a s8te2et_s1743_hier0_sl_a s8te2et_s1743_hier0_sr_a s8te2et_s1743_hier1_array_a s8te2et_s1743_hier1_array_b s8te2et_s1744_hstrap_term_a s8te2et_s1744_hstrap_term_n_a s8te2et_s1744_hstrap2_a s8te2et_s1744_npass_a s8te2et_s1744_npass_b s8te2et_s1744_npass_cent_a s8te2et_s1744_npass_horiz_term_cent_a s8te2et_s1744_npass_vert_a s8te2et_s1744_npd_a s8te2et_s1744_npd_b s8te2et_s1744_npd_cent_a s8te2et_s1744_npd_horiz_a s8te2et_s1744_npd_horiz_term_a s8te2et_s1744_npd_horiz_term_cent_a s8te2et_s1744_npd_horiz_term_wl_a s8te2et_s1744_npd_vert_a s8te2et_s1744_npd_vert_term_cent_a -outputlayer validCoreID2 |
| inside_cell COREID s8te2et_s1744_ppu_a s8te2et_s1744_ppu_b s8te2et_s1744_ppu_cent_c s8te2et_s1744_ppu_corn_a s8te2et_s1744_ppu_cornu_a s8te2et_s1744_ppu_vert_a s8te2et_s1744_ppu_vert_hstrap2_a s8te2et_s1744_ppu_vert_term_a s8te2et_s1744_ppu_vert_term_cent_a s8te2et_s1744_topbot_hstrap2_a s8te2et_s1756_hier0_base_cell_1_a s8te2et_s1756_hier0_base_cell_1_b s8te2et_s1756_hier0_base_cell_2_a s8te2et_s1756_hier0_bot_con_1_a s8te2et_s1756_hier0_bot_con_2_a s8te2et_s1756_hier0_top_con_1_a s8te2et_s1756_hier0_top_con_2_a s8te2et_s1756_hier1_array_2_a s8te2et_s1756_npass_bot_term_a s8te2et_s1756_npass_top_term_a s8te2et_s1756_npd_4x2_a s8te2et_s1756_npd_4x2_b s8te2et_s1756_npd_a s8te2et_s1756_npd_b s8te2et_s1756_npd_bot_term_a s8te2et_s1756_npd_top_term_a s8te2et_s1758_ppu_4x2_a s8te2et_s1758_ppu_4x2_c s8te2et_s1758_ppu_a s8te2et_s1758_ppu_bot_term_a s8te2et_s1758_ppu_c s8te2et_s1758_ppu_top_term_a s8te2et_s1760_hier1_array_a s8te2et_s1760_hier1_array_b s8te2et_s1761_hier1_array_a s8te2et_s1762_hier0_cell_1 s8te2et_s1762_hier0_colend_a s8te2et_s1762_hier0_rowend_2_a s8te2et_s1762_hier1_array_b s8te2et_s1773_hier0_base_cell_a s8te2et_s2t_cell_end02 s8te2et_s2t_cell_end02_NoVia s8te2et_s2t_cell_end03 s8te2et_s2t_cell_end03_NoVia s8te2et_s2t_cellcrnr_01_L s8te2et_s2t_cellcrnr_01_R s8te2et_s3243_sonos_0p42_0p18 s8te2et_s3243_sonos_0p42_0p18_c s8te2et_s3243_sonos_0p42_0p22 s8te2et_s3243_sonos_0p42_0p22_c s8te2et_s3243_sonos_0p42_0p26 s8te2et_s3243_sonos_0p42_0p26_c s8te2et_s3243_sonos_25_0p22 s8te2et_s3243_sonos_25_0p22_c s8te2et_s3243_sonos_25_25 s8te2et_s3243_sonos_25_25_c s8te2et_s3248_sonos_2p0_2p0 s8te2et_s3248_sonos_2p0_2p0_d s8te2et_s3255_MiniArray_b s8te2et_s3259_2t_cell_end02_opt2_L s8te2et_s3259_2t_cellcrnr_L s8te2et_s3262_2t_cell_a s8te2et_s3262_2t_cell_end02_L s8te2et_s3262_2t_cell_end02_R s8te2et_s3262_2t_cell_end02_R01 s8te2et_s3262_2t_cell_ncBot s8te2et_s3262_2t_cell_ncTop s8te2et_s3263_2t_cell_a s8te2et_s3263_2t_cell_end02_L s8te2et_s3263_2t_cell_end02_R s8te2et_s3263_2t_cell_end02_R01 s8te2et_s3263_2t_cell_ncBot s8te2et_s3263_2t_cell_ncTop s8te2et_s3264_2t_2x2_b s8te2et_s3264_2t_2x2_NoVia_b s8te2et_s3264_2t_cell_a s8te2et_s3264_2t_cell_c s8te2et_s3264_2t_cell_end02_L s8te2et_s3264_2t_cell_end02_L_b s8te2et_s3264_2t_cell_end02_L_c s8te2et_s3264_2t_cell_end02_R s8te2et_s3264_2t_cell_end02_R01 s8te2et_s3264_2t_cell_ncBot s8te2et_s3264_2t_cell_ncBot_c s8te2et_s3264_2t_cell_ncTop s8te2et_s3264_2t_cell_ncTop_c s8te2et_s3265_2t_cell_a s8te2et_s3265_2t_cell_b s8te2et_s3265_2t_cell_end01 s8te2et_s3265_2t_cell_end01_NoVia s8te2et_s3265_2t_cell_end02_L s8te2et_s3265_2t_cell_end02_L_b s8te2et_s3265_2t_cell_end02_R s8te2et_s3265_2t_cell_end02_R01 s8te2et_s3265_2t_cell_ncBot -outputlayer validCoreID3 |
| inside_cell COREID s8te2et_s3265_2t_cell_ncBot_b s8te2et_s3265_2t_cell_ncTop s8te2et_s3265_2t_cell_ncTop_b s8te2et_s3266_2t_cell_a s8te2et_s3266_2t_cell_b s8te2et_s3266_2t_cell_end02_L s8te2et_s3266_2t_cell_end02_L_b s8te2et_s3266_2t_cell_end02_R s8te2et_s3266_2t_cell_end02_R01 s8te2et_s3266_2t_cell_ncBot s8te2et_s3266_2t_cell_ncBot_b s8te2et_s3266_2t_cell_ncTop s8te2et_s3266_2t_cell_ncTop_b s8te2et_s3267_2t_2x2_a s8te2et_s3267_2t_2x2_b s8te2et_s3267_2t_2x2_c s8te2et_s3267_PassGate_sonos_2x2 s8te2et_s3267_PassGate_sonos_2x2_b s8te2et_s3267_PassGate_sonos_2x2_novia s8te2et_s3267_PassGate_sonos_2x2_novia_b s8te2et_s3267_PassGate_sonos_2x2_novia_c s8te2et_s3268_sonos_Fet_novia s8te2et_s3268_sonos_Fet_novia_b s8te2et_s3268_sonos_Fet_novia_c s8te2et_s3268_Sonos_soFet_2x2 s8te2et_s3268_Sonos_soFet_2x2_c s8te2et_s3269_2t_2x2_a s8te2et_s3269_2t_2x2_b s8te2et_s3269_2t_2x2_c s8te2et_s3269_PassGate_sonos_2x2 s8te2et_s3269_PassGate_sonos_2x2_b s8te2et_s3269_PassGate_sonos_2x2_c s8te2et_s3270_2t_2x2_opt3 s8te2et_s3270_2t_2x2_opt3_b s8te2et_s3270_2t_2x2_opt3_c s8te2et_s3270_2x2_NoVia s8te2et_s3270_2x2_NoVia_b s8te2et_s3270_2x2_NoVia_c s8te2et_s3270_Sonos_soFet_2x2 s8te2et_s3270_Sonos_soFet_2x2_b s8te2et_s3270_Sonos_soFet_2x2_c s8te2et_s3271_32x32_Array s8te2et_s3272_2t_2x2_a s8te2et_s3272_2t_2x2_NoVia s8te2et_s3272_2t_cell_end02_L s8te2et_s3272_2t_cell_end02_R s8te2et_s3272_32x32_Array s8te2et_s3273_2t_end02_L s8te2et_s3273_2t_end02_L_b s8te2et_s3273_2t_end02_R s8te2et_s3274_2x2_NoVia s8te2et_s3274_2x2_NoVia_b s8te2et_s3274_32x32_Array s8te2et_s3274_32x32_Array_b s8te2et_s3275_2t_cell s8te2et_s3275_2t_cell_a s8te2et_s3275_2t_cell_b s8te2et_s3275_2t_cell_end01 s8te2et_s3275_2t_cell_end01_NoVia s8te2et_s3275_2t_cell_ncBot s8te2et_s3275_2t_cell_ncTop s8te2et_s3275_2x2_NoVia s8te2et_s3275_2x2_NoVia_b s8te2et_s3275_32x32_Array s8te2et_s3275_32x32_Array_b s8te2et_s3275_cell s8te2et_s3275_cell_end01 s8te2et_s3275_cell_end01_NoVia s8te2et_s3276_W2_L2 s8te2et_s3277_W2_L2 s8te2et_s3278_clock_latch s8te2et_s3279_8T_latch s8te2et_s3280_6T_latch s8te2et_s3280_6T_latch_b s8te2et_s3282_2T_Spl_cell2x2 s8te2et_s3282_2T_Spl_cell2x2_b s8te2et_s3282_2T_Spl_cell2x2_nc s8te2et_s3282_2T_Spl_cell2x2_nosrc s8te2et_s3282_cellend s8te2et_s3282_cellend_cntr s8te2et_s3282_celltop s8te2et_s3282_celltop_nc s8te2et_s3283_3T_Dual_cell2x2_nc s8te2et_s3283_3T_Dual_cell2x2_nc_b s8te2et_s3283_3T_Dual_cell2x2_nosrc s8te2et_s3283_3T_Spl_Chanel_cell s8te2et_s3283_cellend s8te2et_s3283_cellend_cntr s8te2et_s3284_1T_SSL_cell2x2 s8te2et_s3284_1T_SSL_cell2x2_nc s8te2et_s3284_1T_SSL_cell2x2_nosrc s8te2et_s3284_cellend s8te2et_s3284_cellend_cntr s8te2et_s3284_celltop s8te2et_s3284_celltop_nc -outputlayer validCoreID4 |
| inside_cell COREID s8te2et_s3286_cell2x2 s8te2et_s3286_cell2x2_nc s8te2et_s3286_cell2x2_nosrc s8te2et_s3287_2t_cell_end02_opt3_L s8te2et_s3287_2x2 s8te2et_s3287_2x2_Bot s8te2et_s3287_2x2_NoVia s8te2et_s3287_2x2_NoViaB s8te2et_s3287_2x2_Top s8te2et_s3287_32x32_Array s8te2et_s3287_32x32_Array_b s8te2et_s3287_cell_end01 s8te2et_s3287_cell_end01_NoVia s8te2et_s3289_14T_latch s8te2et_s3t_cell_end s8te2et_s3t_cell_end_01 s8te2et_s3t_cell_end_01_NoVia s8te2et_s3t_cell_end_NoVia s8te2et_s3t_cellcrnr_01_L s8te2et_s3t_cellcrnr_01_R s8te2et_s3t_cellcrnr_L s8te2et_s3t_cellcrnr_R s8te2et_s4100_2t_cell_end02_opt3_L s8te2et_s4100_2t_cell_option3_NP1 s8te2et_s4100_2t_cell_option3_swap_ncTop s8te2et_s4100_2t_cell_option3_swap1_ncBot s8te2et_s4100_2t_cellcrnr_01_L s8te2et_s4100_2t_cellend_R s8te2et_s4100_2t_cellend_R01 s8te2et_s4101_2t_cell_option3_IP2 s8te2et_s4102_2t_cell_option3_swap_ncTop s8te2et_s4102_2t_cell_option3_swap1_ncBot s8te2et_s4102_2t_cell_STD s8te2et_s4102_2t_cellend_L s8te2et_s4102_2t_cellend_R s8te2et_s4102_2t_cellend_R01 s8te2et_s4103_2t_cell_Bot s8te2et_s4103_2t_cell_NoLvtn s8te2et_s4103_2t_cell_NP1 s8te2et_s4103_2t_cell_option3_swap_ncTop s8te2et_s4103_2t_cell_option3_swap1_ncBot s8te2et_s4103_2t_cell_Top s8te2et_s4103_2t_cellend_L s8te2et_s4103_2t_cellend_L_NoLvtn s8te2et_s4103_2t_cellend_R s8te2et_s4103_2t_cellend_R01 s8te2et_s4104_2t_cell_Bot s8te2et_s4104_2t_cell_NP2 s8te2et_s4104_2t_cell_Top s8te2et_s4104_2t_cellend_L s8te2et_s4105_2t_cell_Bot s8te2et_s4105_2t_cell_NP3 s8te2et_s4105_2t_cell_Top s8te2et_s4105_2t_cellend_L s8te2et_s4105_2t_cellend_R s8te2et_s4105_2t_cellend_R01 s8te2et_s4106_2t_cell_Bot s8te2et_s4106_2t_cell_NP4 s8te2et_s4106_2t_cell_Top s8te2et_s4106_2t_cellend_L s8te2et_s4106_2t_cellend_R s8te2et_s4106_2t_cellend_R01 s8te2et_s4107_2t_cell_Bot s8te2et_s4107_2t_cell_NP5 s8te2et_s4107_2t_cell_Top s8te2et_s4107_2t_cellend_L s8te2et_s4107_2t_cellend_R s8te2et_s4107_2t_cellend_R01 s8te2et_s4108_2t_cell_Bot s8te2et_s4108_2t_cell_STD s8te2et_s4108_2t_cell_Top s8te2et_s4108_2t_cellend_L s8te2et_s4108_2t_cellend_R s8te2et_s4108_2t_cellend_R01 s8te2et_s4109_2t_cell_Bot s8te2et_s4109_2t_cell_NP1 s8te2et_s4109_2t_cell_Top s8te2et_s4109_2t_cellend_L s8te2et_s4109_2t_cellend_R s8te2et_s4109_2t_cellend_R01 s8te2et_s4110_2t_cell_Bot s8te2et_s4110_2t_cell_NP2 s8te2et_s4110_2t_cell_Top s8te2et_s4110_2t_cellend_L s8te2et_s4111_2t_cell_Bot s8te2et_s4111_2t_cell_NP3 s8te2et_s4111_2t_cell_Top s8te2et_s4111_2t_cellend_L s8te2et_s4112_2t_cell_Bot s8te2et_s4112_2t_cell_NP4 s8te2et_s4112_2t_cell_Top s8te2et_s4112_2t_cellend_L s8te2et_s4112_2t_cellend_R s8te2et_s4112_2t_cellend_R01 s8te2et_s4113_2t_cell_Bot -outputlayer validCoreID5 |
| inside_cell COREID s8te2et_s4113_2t_cell_NP5 s8te2et_s4113_2t_cell_Top s8te2et_s4113_2t_cellend_L s8te2et_s4113_2t_cellend_R s8te2et_s4113_2t_cellend_R01 s8te2et_s4114_2t_cell_Bot s8te2et_s4114_2t_cell_STD s8te2et_s4114_2t_cell_Top s8te2et_s4114_2t_cellend_L s8te2et_s4114_2t_cellend_R s8te2et_s4114_2t_cellend_R01 s8te2et_s4115_2t_cell_Bot s8te2et_s4115_2t_cell_NP1 s8te2et_s4115_2t_cell_Top s8te2et_s4115_2t_cellend_L s8te2et_s4115_2t_cellend_R s8te2et_s4115_2t_cellend_R01 s8te2et_s4116_2t_cell_Bot s8te2et_s4116_2t_cell_NP2 s8te2et_s4116_2t_cell_Top s8te2et_s4116_2t_cellend_L s8te2et_s4117_2t_cell_Bot s8te2et_s4117_2t_cell_NP3 s8te2et_s4117_2t_cell_Top s8te2et_s4117_2t_cellend_L s8te2et_s4118_2t_cell_Bot s8te2et_s4118_2t_cell_NP4 s8te2et_s4118_2t_cell_Top s8te2et_s4118_2t_cellend_L s8te2et_s4118_2t_cellend_R s8te2et_s4118_2t_cellend_R01 s8te2et_s4119_2t_cell_Bot s8te2et_s4119_2t_cell_NP5 s8te2et_s4119_2t_cell_Top s8te2et_s4119_2t_cellend_L s8te2et_s4119_2t_cellend_R s8te2et_s4119_2t_cellend_R01 s8te2et_s4120_2t_cell_Bot s8te2et_s4120_2t_cell_STD s8te2et_s4120_2t_cell_Top s8te2et_s4120_2t_cellend_L s8te2et_s4120_2t_cellend_R s8te2et_s4120_2t_cellend_R01 s8te2et_s4121_2t_cell_Bot s8te2et_s4121_2t_cell_NP1 s8te2et_s4121_2t_cell_Top s8te2et_s4121_2t_cellend_L s8te2et_s4121_2t_cellend_R s8te2et_s4121_2t_cellend_R01 s8te2et_s4122_2t_cell_Bot s8te2et_s4122_2t_cell_NP2 s8te2et_s4122_2t_cell_Top s8te2et_s4122_2t_cellend_L s8te2et_s4123_2t_cell_Bot s8te2et_s4123_2t_cell_NP3 s8te2et_s4123_2t_cell_Top s8te2et_s4123_2t_cellend_L s8te2et_s4124_2t_cell_Bot s8te2et_s4124_2t_cell_NP4 s8te2et_s4124_2t_cell_Top s8te2et_s4124_2t_cellend_L s8te2et_s4124_2t_cellend_R s8te2et_s4124_2t_cellend_R01 s8te2et_s4125_2t_cell_Bot s8te2et_s4125_2t_cell_NP5 s8te2et_s4125_2t_cell_Top s8te2et_s4125_2t_cellend_L s8te2et_s4125_2t_cellend_R s8te2et_s4125_2t_cellend_R01 s8te2et_s4126_2t_cell_Bot s8te2et_s4126_2t_cell_STD s8te2et_s4126_2t_cell_Top s8te2et_s4126_2t_cellend_L s8te2et_s4126_2t_cellend_R s8te2et_s4126_2t_cellend_R01 s8te2et_s4127_2t_cell_Bot s8te2et_s4127_2t_cell_NP1 s8te2et_s4127_2t_cell_Top s8te2et_s4127_2t_cellend_L s8te2et_s4127_2t_cellend_R s8te2et_s4127_2t_cellend_R01 s8te2et_s4128_2t_cell_Bot s8te2et_s4128_2t_cell_NP2 s8te2et_s4128_2t_cell_Top s8te2et_s4128_2t_cellend_L s8te2et_s4128_2t_cellend_R s8te2et_s4128_2t_cellend_R01 s8te2et_s4129_2t_cell_Bot s8te2et_s4129_2t_cell_NP3 s8te2et_s4129_2t_cell_Top s8te2et_s4129_2t_cellend_L s8te2et_s4129_2t_cellend_R s8te2et_s4129_2t_cellend_R01 s8te2et_s4130_2t_cell_Bot s8te2et_s4130_2t_cell_NP4 -outputlayer validCoreID6 |
| inside_cell COREID s8te2et_s4130_2t_cell_Top s8te2et_s4130_2t_cellend_L s8te2et_s4130_2t_cellend_R s8te2et_s4130_2t_cellend_R01 s8te2et_s4131_2t_cell_Bot s8te2et_s4131_2t_cell_NP5 s8te2et_s4131_2t_cell_Top s8te2et_s4131_2t_cellend_L s8te2et_s4131_2t_cellend_R s8te2et_s4131_2t_cellend_R01 s8te2et_s4132_2t_cellend_L s8te2et_s4132_3t_cell_Bot s8te2et_s4132_3t_cell_STD s8te2et_s4132_3t_cell_Top s8te2et_s4132_3t_cellend_R s8te2et_s4132_3t_cellend_R01 s8te2et_s4133_2t_cellend_L s8te2et_s4133_3t_cell_Bot s8te2et_s4133_3t_cell_NP1 s8te2et_s4133_3t_cell_Top s8te2et_s4133_3t_cellend_R s8te2et_s4133_3t_cellend_R01 s8te2et_s4135_2t_cellend_L s8te2et_s4135_3t_cell_Bot s8te2et_s4135_3t_cell_NP3 s8te2et_s4135_3t_cell_Top s8te2et_s4135_3t_cellend_R s8te2et_s4135_3t_cellend_R01 s8te2et_s4150_2t_cell s8te2et_s4150_2t_cell_Bot s8te2et_s4150_2t_cell_Top s8te2et_s4150_2t_cellcrnr_L s8te2et_s4150_2t_cellcrnr_R s8te2et_s4150_2t_cellend_L s8te2et_s4150_2t_cellend_R s8te2et_s4150_32x32_Array s8te2et_s4151_2t_2x2_a s8te2et_s4151_2t_cell_end01 s8te2et_s4151_2t_cell_end01_no_mcon s8te2et_s4151_2t_cell_end02_L s8te2et_s4151_2t_cell_end02_R s8te2et_s4151_2t_cell_end02_R01 s8te2et_s4151_2t_cellcrnr_L s8te2et_s4151_2t_cellcrnr_R s8te2et_s4151_PassGate_sonos_2x2 s8te2et_s4151_PassGate_sonos_2x2_no_mcon s8te2et_s4152_2t_2x2_a s8te2et_s4152_PassGate_sonos_2x2 s8te2et_s4154_2t_cell_a s8te2et_s4154_2t_cell_end02_L s8te2et_s4154_2t_cell_end02_R s8te2et_s4154_2t_cell_end02_R01 s8te2et_s4154_2t_cell_ncBot s8te2et_s4154_2t_cell_ncTop s8te2et_s4155_2t_cell_a s8te2et_s4155_2t_cell_end02_L s8te2et_s4155_2t_cell_end02_R s8te2et_s4155_2t_cell_end02_R01 s8te2et_s4155_2t_cell_ncBot s8te2et_s4155_2t_cell_ncTop s8te2et_s4156_2t_cell s8te2et_s4156_2t_cell_end s8te2et_s4156_2t_cell_end_no_mcon s8te2et_s4156_2t_cell_ncBot s8te2et_s4156_2t_cell_ncTop s8te2et_s7300_DNW_Ring s8te2et_s7300_DNW_Ring_Big s8te2et_s7300_DNW_Ring_s s8te2et_s7306_cap_padNFPASS_a s8te2et_sonos_Diff_MiniArray_opt3 s8te2et_SONOS_L0p13_Wmin s8te2et_SONOS_L0p15_Wmin s8te2et_SONOS_L0p17_Wmin s8te2et_SONOS_L0p18_Wmin s8te2et_sonos_L0p22_W25 s8te2et_SONOS_L0p22_W25 s8te2et_SONOS_L0p22_Wmin s8te2et_SONOS_L0p26_Wmin s8te2et_sonos_L25_W25 s8te2et_SONOS_L25_W25 s8te2et_sonos_L25_W25_cntm_ldntm s8te2et_SONOS_L25_Wmin s8te2et_sonos_Lmin_W25 s8te2et_SONOS_Lmin_W25 s8te2et_sonos_Lmin_W25_cntm_ldntm s8te2et_SONOS_Lmin_Wmin s8te2et_sonos_Lp5_W25 s8te2et_sonos_Lp5_Wp8 s8te2et_Sonos_soFet_2x2 s8te2et_sonos_W1_L1 s8te2et_sonos_W1_L1_NoDnw s8te2et_sonos_W1_L25 s8te2et_sonos_W1_L25_NoDnw s8tnvet_md5216_a s8tnvet_s9xxx_cyp_cap_padNHLV40 -outputlayer validCoreID7 |
| inside_cell COREID s8tnvet_s9xxx_cyp_cap_padNPD40 s8tnvet_s9xxx_cyp_cap_padPPU40 s8tnvet_s9xxx_cyp_cap_padS40 s8tnvet_s9xxx_pcm_iso_ppu_14_15 s8tnvet_s9xxx_pcm_iso_ppu_21_15 s8tnvet_s9xxx_pcm_iso_ppu_30_15 s8tnvet_s9xxx_pcm_multi_nhlv s8tnvet_s9xxx_pcm_multi_npass s8tnvet_s9xxx_pcm_multi_npd s8tnvet_s9xxx_pcm_multi_ppu s8tnvet_s9xxx_sr_mcell s8tnvet_s9xxx_sr_mcell_nTfr_1x s8tnvet_s9xxx_sr_mcell_pLoad_1x s8tnvet_s9xxx_sr_mcell_pLoad_1x_2 s8tnvet_s9xxx_sr_mcell_rcl s8tnvet_s9xxx_sr_mcell_rcl_2 s8tnvet_s9xxx_sr_mcell_TGvsr_1x_b s8tnvet_s9xxx_sr_mcell_TGvsr_1x_b_2 s8tnvet_s9xxx_sr_mcell_tie s8tnvet_s9xxx_sr_mcell_tie_special_L s8tnvet_s9xxx_sr_mcell_tie_special_R s8tnvet_s9xxx_sr_tcell s8cell_ee_vcctrk_cell s8cell_ee_vcctrk_cellcorn_p s8cell_ee_vcctrk_termcella s8cell_ee_vcctrk_cellcorn_n s8cell_ee_vcctrk_colend s8cell_ee_vcctrk_termcellb s8cell_ee_colenda_d s8cell_ee_colend_lasta_d "s8sram_tech_CD_top*" s8sram_tech_CD_lcross s8sram_tech_CD_top_pcell "s8cell_ee_tech_CD_top*" s8cell_ee_tech_CD_lcross s8cell_ee_tech_CD_top_pcell -outputlayer validCoreID8 |
| inside_cell COREID "s8q_tech_CD_top*" s8q_tech_CD_lcross s8q_tech_CD_top_pcell -outputlayer validCoreID10 |
| inside_cell COREID sr_mcell_b_cell7 sr_mcell_tie_Mt_cell7 sr_tcell_tie_b_cell7 sr_mcell_t_cell7 sr_mcell_tie_Rb_cell7 sr_tcell_tie_t_cell7 sr_mcell_tie_END_b_cell7 sr_mcell_tie_Rt_cell7 sr_tcell_END_b_cell7 sr_mcell_tie_END_t_cell7 sr_tcell_b_cell7 sr_tcell_END_t_cell7 sr_mcell_tie_Lb_cell7 sr_tcell_t_cell7 sr_tcell_tie_Rb_cell7 sr_mcell_tie_Lt_cell7 sr_tcell_tie_Lt_cell7 sr_tcell_tie_Rt_cell7 sr_mcell_tie_Mb_cell7 sr_tcell_tie_Lb_cell7 sr_blld_tie "s8sram_s8p_tech_CD_top*" -outputlayer validCoreIDAW |
| inside_cell COREID s8tnvpsr_bltd_eq s8tnvpsr_bltd_tie s8tnvpsr_blld_tie s8tnvpsr_blld s8tnvpsr_mcell_tie_END_sub_t_cell7 s8tnvpsr_mcell_tie_Mt_cell7 s8tnvpsr_mcell_tie_Lt_cell7 s8tnvpsr_mcell_tie_Rt_cell7 s8tnv64kssr_bltd_eq s8tnv64kssr_bltd_tie s8tnv64kssr_blld_tie s8tnv64kssr_blld -outputlayer validCoreID_TDRrevCA |
| inside_cell COREID s8fmlt64k_cell_cell s8fmlt64k_cell_cell_last s8fmlt64k_cell_cellcorn_n s8fmlt64k_cell_cellcorn_p s8fmlt64k_cell_colend_lasta_d s8fmlt64k_cell_colend_lastb s8fmlt64k_cell_colenda_d s8fmlt64k_cell_colendb s8fmlt64k_cell_strapn s8fmlt64k_cell_strapp -outputlayer validCoreID_TDRrevCL |
| inside_cell COREID s8rom_rom_wlvnb2 s8rom_romb0 s8rom_romb1 -outputlayer validCoreID_TDRrevCW |
| inside_cell COREID s8fmlt_cell_cell s8fmlt_cell_cellcorn_p s8fmlt_cell_colenda_d s8fmlt_cell_strapp s8fmlt_cell_cell_last s8fmlt_cell_colend_lasta_d s8fmlt_cell_colendb s8fmlt_cell_cellcorn_n s8fmlt_cell_colend_lastb s8fmlt_cell_strapn -outputlayer validCoreID_s8fmlt_cell |
| inside_cell COREID "*_srom*_rom*" -outputlayer validCoreID_product_srom |
| inside_cell COREID s8fs_cell_vcctrk_cell s8fs_cell_bseln_endb s8fs_cell_strapn s8fs_cell_vcctrk_cellcorn_n s8fs_cell_bselp_enda_d s8fs_cell_strapn_colendb_d s8fs_cell_vcctrk_cellcorn_p s8fs_cell_cellcorn_n s8fs_cell_strapp s8fs_cell_vcctrk_colend s8fs_cell_cellcorn_p s8fs_cell_strapp_colenda_d s8fs_cell_vcctrk_termcella s8fs_cell_cellcorn_poly s8fs_cell_termcella s8fs_cell_vcctrk_termcellb s8fs_cell_colenda_d s8fs_cell_termcellb s8fs_cell_cell s8fs_cell_colendb -outputlayer validCoreID_s8fs |
| or ( or ( or ( or validCoreID1 validCoreID2 ) ( or validCoreID3 validCoreID4 ) ) ( or ( or validCoreID5 validCoreID6 ) ( or validCoreID7 ( or validCoreID8 validCoreID10 ) ) ) ) ( or validCoreID9 ( or validCoreIDAW ( or validCoreID_TDRrevCA ( or validCoreID_TDRrevCL ( or validCoreID_TDRrevCW ( or validCoreID_s8fmlt_cell ( or validCoreID_product_srom validCoreID_s8fs ) ) ) ) ) ) ) -outputlayer validCoreID |
| not COREID validCoreID -outputlayer inValidCoreID |
| rule "coreID.CON.1" { |
| caption "coreID.CON.1: Unapproved cells contain areaid:core marker layer" |
| copy inValidCoreID |
| } |
| |
| |
| // |
| // denmos checks |
| // |
| |
| |
| |
| select -enclose thkox ( select -interact nwell ( not ENID dnwell ) ) -outputlayer deNFetDevice |
| select -interact nwell deNFetDevice -outputlayer deNFetNwell |
| select -interact diffi deNFetNwell -outputlayer deNFetDiff |
| select -interact ( and poly ENID ) deNFetDiff -outputlayer deNFetGate |
| select -interact deNFetDiff deNFetGate -outputlayer deNFetSource |
| and deNFetSource deNFetGate -outputlayer deNFetSourceOvlPoly |
| not deNFetSource deNFetGate -outputlayer deNFetSourceNotPoly |
| select -inside diffi deNFetNwell -outputlayer deNFetDrain |
| bbox deNFetDrain -outputlayer deNFetDrainBB |
| edge_select -coincident_only deNFetDrain deNFetDrainBB -outputlayer deNFetDrainEdges |
| and deNFetSource deNFetNwell -outputlayer deNFetSourceOvlNwell |
| inte deNFetSourceOvlNwell -eq 0.225 -output region -outputlayer deNFetSourceGood |
| not ( and ENID deNFetNwell ) ( or deNFetSource deNFetDrainBB ) -outputlayer deNFetSourceToDrainRegion |
| inte deNFetSourceToDrainRegion -eq 1.585 -para -output region -outputlayer deNFetSourceToDrainSpacingGood |
| rule "denmos.WID.1" { |
| caption "denmos.WID.1: Min width of de_nFet_gate < 1.055" |
| inte deNFetGate -lt 1.055 -abut -lt 90 -single_point -output region |
| } |
| rule "denmos.WID.2" { |
| caption "denmos.WID.2: Min width of de_nFet_source not overlapping poly < 0.28" |
| inte deNFetSourceNotPoly -lt 0.28 -abut -lt 90 -single_point -output region |
| } |
| rule "denmos.WID.3" { |
| caption "denmos.WID.3: Min width of de_nFet_source overlapping poly < 0.925" |
| inte deNFetSourceOvlPoly -lt 0.925 -abut -lt 90 -single_point -output region |
| } |
| rule "denmos.WID.4" { |
| caption "denmos.WID.4: Min width of the de_nFet_drain < 0.17" |
| edge_length deNFetDrainEdges -lt 0.17 |
| } |
| rule "denmos.ENC.1" { |
| caption "denmos.ENC.1: Min/Max extension between de_nFET_source over nwell = 0.225" |
| not deNFetSourceOvlNwell deNFetSourceGood |
| } |
| rule "denmos.SP.1" { |
| caption "denmos.SP.1: Min/Max spacing between de_nFET_source and de_nFET_drain = 1.585" |
| not deNFetSourceToDrainRegion deNFetSourceToDrainSpacingGood |
| } |
| rule "denmos.WID.5" { |
| caption "denmos.WID.5: Min channel width for de_nFet_gate < 5.0" |
| edge_length ( edge_boolean -inside deNFetGate deNFetSource ) -lt 5.0 |
| } |
| rule "denmos.CON.1" { |
| caption "denmos.CON.1: 90 degree angles are not permitted for nwell overlapping de_nFET_drain" |
| convex_edge deNFetNwell -angle1 -eq 90 -angle2 -gt 0 |
| } |
| rule "denmos.ENC.2" { |
| caption "denmos.ENC.2: Min enclosure of de_nFet_drain by nwell < 0.66" |
| enc deNFetDrain deNFetNwell -lt 0.66 -measure all -abut -lt 90 -single_point -output region |
| } |
| rule "denmos.SP.2" { |
| caption "denmos.SP.2: Min spacing between p+ tap and (nwell overlapping de_nFet_drain) < 0.86" |
| and ( select -outside diffi deNFetNwell ) deNFetDevice -outputlayer deNFetPtap |
| exte deNFetPtap deNFetNwell -lt 0.86 -abut -lt 90 -single_point -output region |
| } |
| rule "denmos.SP.3" { |
| caption "denmos.SP.3: Min spacing between nwells overlapping de_nFET_drain < 2.4" |
| exte deNFetNwell -lt 2.4 -abut -lt 90 -single_point -output region -notch not |
| } |
| rule "denmos.ENC.3" { |
| caption "denmos.ENC.3: Min enclosure of de_nFet_source by nsdm < 0.13" |
| enc deNFetSource nsdm -lt 0.13 -measure all -abut -lt 90 -single_point -output region |
| } |
| rule "denmos.CON.2" { |
| caption "denmos.CON.2: de_nFet_source must be enclosed by nsdm" |
| not deNFetSource nsdm |
| } |
| |
| |
| // |
| // standard denmos 20v checks |
| // |
| |
| |
| |
| not ( and ( and ( not ( and ( and gate nsdm ) v20 ) dnwell ) thkox ) lvtn ) ( or v5 v12 ESDID LVID pnp npn ) -outputlayer ngate_v20a |
| select -interact ( not ( not ( and ( and ( and ( and gate nsdm ) v20 ) dnwell ) thkox ) lvtn ) ( or ngate_v20a v5 v12 ESDID LVID pnp npn ) ) pwbm -outputlayer ngate_v20_iso_rec |
| and ( select -interact ( holes pwbm ) ngate_v20_iso_rec ) dnwell -outputlayer ngate_v20_iso_sub |
| and ( and psdm diff ) ngate_v20_iso_sub -outputlayer ngate_v20_iso_sub_cont |
| copy ngate_v20_iso_rec -outputlayer ngate_v20_iso_gate |
| or ngate_v20a ngate_v20_iso_rec -outputlayer ngate_v20 |
| not ( and diff nsdm ) ngate_v20 -outputlayer nsd_20v |
| edge_expand ( edge_boolean -coincident_only ( not nsd_20v ngate_v20 ) ENID ) -outside_by 0.05 -outputlayer nsd_20v_src_1 |
| select -touch ( not nsd_20v ngate_v20 ) nsd_20v_src_1 -eq 3 -outputlayer nsd_20v_src |
| not ( and ( select -enclose lvtn nsdm ) ngate_v20 ) pwbm -outputlayer ngate_v20_nat |
| not ( not ( select -interact ENID ngate_v20_nat ) ngate_v20_nat ) nsd_20v_src -outputlayer nsd_20v_nat_drn |
| not ( not ( not ( select -interact ENID ngate_v20 ) ngate_v20 ) nsd_20v_src ) nsd_20v_nat_drn -outputlayer nsd_20v_drn |
| not ( and ( not ( select -cut lvtn nsdm ) ( select -enclose lvtn nsdm ) ) ngate_v20 ) ( or ngate_v20_iso_rec ngate_v20_nat ) -outputlayer ngate_v20_zvt |
| not ngate_v20 ( select -interact poly ( or ngate_v20_nat ngate_v20_zvt ngate_v20_iso_rec ) ) -outputlayer ngate_v20_nom |
| rule "denmos_20.WID.1" { |
| caption "denmos_20.WID.1: Min width of gate poly in standard 20v nmos drain extended device < 3.0" |
| inte ( select -interact poly ngate_v20_nom ) -lt 3.0 -abut -lt 90 -output region |
| } |
| rule "denmos_20.WID.2" { |
| caption "denmos_20.WID.2: Min width of source in standard 20v nmos drain extended device < 0.29" |
| inte ( select -interact nsd_20v_src ngate_v20_nom ) -lt 0.29 -abut -lt 90 -output region |
| } |
| rule "denmos_20.WID.3" { |
| caption "denmos_20.WID.3: Min width of gate of standard 20v nmos drain extended device < 1.5" |
| inte ( select -interact ( select -interact ( and diffi poly ) ENID ) ( select -interact dnwell ngate_v20_nom ) ) -lt 1.5 -abut -lt 90 -output region |
| } |
| rule "denmos_20.WID.4" { |
| caption "denmos_20.WID.4: Min width of drain of standard 20v nmos drain extended device < 0.75" |
| inte ( and ( and nsd_20v_drn ( select -interact dnwell ngate_v20_nom ) ) ( not diffi polyi ) ) -lt 0.75 -abut -lt 90 -output region -metric opposite -para |
| } |
| rule "denmos_20.OVL.1" { |
| caption "denmos_20.OVL.1: Min extension of deep nwell over channel of standard 20v nmos drain extended device < 0.5" |
| inte ( not ( and ( select -interact dnwell ngate_v20_nom ) diffi ) ( and ( and nsd_20v_drn ( select -interact dnwell ngate_v20_nom ) ) ( not diffi polyi ) ) ) -lt 0.5 -abut -lt 90 -output region |
| } |
| rule "denmos_20.SP.1" { |
| caption "denmos_20.SP.1: Min space from drain_diff to gate or src_diff of standard 20v nmos drain extended device < 3.0" |
| exte ( and ( and nsd_20v_drn ( select -interact dnwell ngate_v20_nom ) ) ( not diffi polyi ) ) ( select -interact diffi ngate_v20_nom ) -lt 3.0 -abut -lt 90 -output region |
| } |
| rule "denmos_20.LEN.1" { |
| caption "denmos_20.LEN.1: Min channel width of standard 20v nmos drain extended device < 30.0" |
| edge_expand ( edge_length ( edge_boolean -coincident_only ngate_v20_nom nsd_20v_src ) -lt 30.0 ) -outside_by 0.05 |
| } |
| rule "denmos_20.ANG.1" { |
| caption "denmos_20.ANG.1: 90 degree corners are not allowed on the drain_diff of the standard 20v nmos drain extended device" |
| select -enclose diffi ( inte ( select -interact -not ( and diffi ( and nsd_20v_drn ( select -interact dnwell ngate_v20_nom ) ) ) polyi ) -lt 0.05 -abut -eq 90 -output region ) |
| } |
| rule "denmos_20.ENC.1" { |
| caption "denmos_20.ENC.1: Min enclosure of drain tap by dnwell in the direction of current flow of standard 20v nmos drain extended device < 3.5" |
| enc ( edge_boolean -coincident_only ( select -interact -not ( and diffi ( and nsd_20v_drn ( select -interact dnwell ngate_v20_nom ) ) ) polyi ) nwell ) dnwell -lt 3.5 -abut -lt 90 -output region |
| } |
| rule "denmos_20.ENC.2" { |
| caption "denmos_20.ENC.2: Min pwbm enclosure of dnwell of standard 20v nmos drain extended device < 0.5" |
| enc ( select -interact dnwell ngate_v20_nom ) pwbm -lt 0.5 -abut -lt 90 -output region |
| } |
| rule "denmos_20.WID.5" { |
| caption "denmos_20.WID.5: Min channel length of standard 20v nmos drain extended device < 0.5" |
| inte ngate_v20_nom -lt 0.5 -abut -lt 90 -output region -metric opposite -para |
| } |
| rule "denmos_20.EXT.1" { |
| caption "denmos_20.EXT.1: Min poly field extension past diffusion of standard 20v nmos drain extended device < 1.0" |
| enc ( select -interact diffi nsd_20v_drn ) ( select -interact polyi ngate_v20_nom ) -lt 1.0 -abut -lt 90 -output region |
| } |
| rule "denmos_20.SP.2" { |
| caption "denmos_20.SP.2: Min space from P+ tap to source of standard 20v nmos drain extended device < 0.5" |
| exte ptap ( select -interact nsd_20v_src ( select -interact ENID ngate_v20_nom ) ) -lt 0.5 -abut -lt 90 -output region |
| } |
| rule "denmos_20.XOR.1" { |
| caption "denmos_20.XOR.1: lvtn must be coincident with pwbm of standard 20v nmos drain extended device" |
| xor ( select -interact ( select -interact lvtn ENID ) ngate_v20_nom ) ( select -interact ( select -interact pwbm ENID ) ngate_v20_nom ) |
| } |
| rule "denmos_20.ENC.3" { |
| caption "denmos_20.ENC.3: Min enclosure of drain by nwell of standard 20v nmos drain extended device < 0.05" |
| edge_length ( edge_boolean -coincident_only -not ( and ( select -interact nsd_20v_drn ( select -interact ENID ngate_v20_nom ) ) diffi ) nwell ) -gt 10 -outputlayer dnm_20_drn_not_coin_edge_nw |
| enc dnm_20_drn_not_coin_edge_nw nwell -lt 0.05 -abut -lt 90 -output region -metric opposite -para |
| } |
| |
| |
| // |
| // native denmos 20v checks |
| // |
| |
| |
| |
| rule "denmos_20.WID.6" { |
| caption "denmos_20.WID.6: Min width of poly gate in native 20v nmos drain extended device < 3.0" |
| inte ( select -interact poly ngate_v20_nat ) -lt 3.0 -abut -lt 90 -output region |
| } |
| rule "denmos_20.WID.7" { |
| caption "denmos_20.WID.7: Min width of source in native 20v nmos drain extended device < 0.29" |
| inte ( select -interact nsd_20v_src ngate_v20_nat ) -lt 0.29 -abut -lt 90 -output region |
| } |
| rule "denmos_20.WID.8" { |
| caption "denmos_20.WID.8: Min width of gate of native 20v nmos drain extended device < 1.5" |
| inte ( select -interact ( select -interact ( and diffi poly ) ENID ) ( select -interact ENID ngate_v20_nat ) ) -lt 1.5 -abut -lt 90 -output region |
| } |
| rule "denmos_20.WID.9" { |
| caption "denmos_20.WID.9: Min width of drain of native 20v nmos drain extended device < 0.75" |
| inte ( and ( select -interact ENID nsd_20v_nat_drn ) ( select -interact -not diffi polyi ) ) -lt 0.75 -abut -lt 90 -output region -metric opposite -para |
| } |
| rule "denmos_20.OVL.2" { |
| caption "denmos_20.OVL.2: Min extension of deep nwell over channel of native 20v nmos drain extended device < 0.5" |
| inte ( and dnwell ( select -interact diffi ngate_v20_nat ) ) -lt 0.5 -abut -lt 90 -output region |
| } |
| rule "denmos_20.SP.3" { |
| caption "denmos_20.SP.3: Min space from drain_diff to gate or src_diff of native 20v nmos drain extended device < 3.0" |
| exte ( and ( select -interact ENID nsd_20v_nat_drn ) ( select -interact -not diffi polyi ) ) ( select -interact diffi ngate_v20_nat ) -lt 3.0 -abut -lt 90 -output region |
| } |
| rule "denmos_20.LEN.2" { |
| caption "denmos_20.LEN.2: Min channel width of native 20v nmos drain extended device < 30.0" |
| edge_expand ( edge_length ( edge_boolean -coincident_only ngate_v20_nat nsd_20v_src ) -lt 30.0 ) -outside_by 0.05 |
| } |
| rule "denmos_20.ANG.2" { |
| caption "denmos_20.ANG.2: 90 degree corners are not allowed on the drain_diff of the native 20v nmos drain extended device" |
| select -enclose diffi ( inte ( select -interact -not ( and diffi ( and nsd_20v_nat_drn ( select -interact ENID ngate_v20_nat ) ) ) polyi ) -lt 0.05 -abut -eq 90 -output region ) |
| } |
| rule "denmos_20.ENC.4" { |
| caption "denmos_20.ENC.4: Min enclosure of drain tap by dnwell in the direction of current flow of native 20v nmos drain extended device < 3.5" |
| enc ( edge_boolean -coincident_only ( select -interact -not ( and diffi ( and nsd_20v_nat_drn ( select -interact ENID ngate_v20_nat ) ) ) polyi ) nwell ) dnwell -lt 4.0 -abut -lt 90 -output region |
| } |
| rule "denmos_20.ENC.5" { |
| caption "denmos_20.ENC.5: Min pwbm enclosure of dnwell of native 20v nmos drain extended device < 0.5" |
| enc ( select -interact dnwell ( select -interact ENID ngate_v20_nat ) ) pwbm -lt 0.5 -abut -lt 90 -output region |
| } |
| rule "denmos_20.WID.10" { |
| caption "denmos_20.WID.10: Min channel length of native 20v nmos drain extended device < 0.5" |
| inte ngate_v20_nat -lt 0.5 -abut -lt 90 -output region -metric opposite -para |
| } |
| rule "denmos_20.EXT.2" { |
| caption "denmos_20.EXT.2: Min poly field extension past diffusion of native 20v nmos drain extended device < 1.5" |
| enc ( select -interact diffi ( and diffi ( and nsd_20v_nat_drn ( select -interact ENID ngate_v20_nat ) ) ) ) ( select -interact polyi ngate_v20_nat ) -lt 1.5 -abut -lt 90 -output region |
| } |
| rule "denmos_20.SP.4" { |
| caption "denmos_20.SP.4: Min space from P+ tap to source of native 20v nmos drain extended device < 0.5" |
| exte ptap ( select -interact nsd_20v_src ( select -interact ENID ngate_v20_nat ) ) -lt 0.5 -abut -lt 90 -output region |
| } |
| rule "denmos_20.OVL.3" { |
| caption "denmos_20.OVL.3: lvtn must cover entire device of native 20v nmos drain extended device" |
| select -interact lvtn ( edge_expand ( edge_boolean -outside lvtn pwbm ) -outside_by 0.05 ) -outputlayer ngate_v20_nat_ovlp3_a |
| or polyi ( holes polyi ) -outputlayer all_p |
| select -interact ( select -interact ( or all_p diffi ) ngate_v20_nat_ovlp3_a ) ngate_v20 -outputlayer ngate_v20_nat_ovlp3 |
| not ngate_v20_nat_ovlp3 lvtn |
| } |
| rule "denmos_20.ENC.6" { |
| caption "denmos_20.ENC.6: Min enclosure of drain by nwell of native 20v nmos drain extended device < 0.05" |
| and ( select -interact ENID nsd_20v_nat_drn ) ( select -interact -not diffi polyi ) -outputlayer nat_drn_diff |
| edge_length ( edge_boolean -coincident_only -not nat_drn_diff nwell ) -gt 10 -outputlayer nat_dnm_20_drn_not_coin_edge_nw |
| enc nat_dnm_20_drn_not_coin_edge_nw nwell -lt 0.05 -abut -lt 90 -output region -metric opposite -para |
| } |
| |
| |
| // |
| // zvt denmos 20v checks |
| // |
| |
| |
| |
| rule "denmos_20.WID.11" { |
| caption "denmos_20.WID.11: Min width of poly gate in zvt 20v nmos drain extended device < 7.0" |
| select -interact diffi ngate_v20_zvt -outputlayer diff_inter_zvt |
| select -interact dnwell ngate_v20_zvt -outputlayer dnw_inter_zvt |
| and ( and polyi ( or diff_inter_zvt dnw_inter_zvt ) ) ENID -outputlayer ply2chk |
| inte ply2chk -lt 7.0 -abut -lt 90 -output region |
| } |
| rule "denmos_20.WID.12" { |
| caption "denmos_20.WID.12: Min width of source in zvt 20v nmos drain extended device < 0.29" |
| inte ( select -interact nsd_20v_src ngate_v20_zvt ) -lt 0.29 -abut -lt 90 -output region |
| } |
| rule "denmos_20.WID.13" { |
| caption "denmos_20.WID.13: Min width of gate of zvt 20v nmos drain extended device < 6.0" |
| inte ( select -interact ( select -interact ( and diffi poly ) ENID ) ( select -interact ENID ngate_v20_zvt ) ) -lt 6.0 -abut -lt 90 -output region |
| } |
| rule "denmos_20.WID.14" { |
| caption "denmos_20.WID.14: Min width of drain of zvt 20v nmos drain extended device < 0.75" |
| inte ( and ( and nsd_20v_drn ( select -interact dnwell ngate_v20_zvt ) ) ( not diffi polyi ) ) -lt 0.75 -abut -lt 90 -output region -metric opposite -para |
| } |
| rule "denmos_20.OVL.4" { |
| caption "denmos_20.OVL.4: Min extension of deep nwell over channel of zvt 20v nmos drain extended device < 0.5" |
| inte ( not ( and ( select -interact dnwell ngate_v20_zvt ) diffi ) ( and ( and nsd_20v_drn ( select -interact dnwell ngate_v20_zvt ) ) ( not diffi polyi ) ) ) -lt 0.5 -abut -lt 90 -output region |
| } |
| rule "denmos_20.SP.5" { |
| caption "denmos_20.SP.5: Min space from drain diffusion to gate/src diffusion of zvt 20v nmos drain extended device < 2.0" |
| exte ( and ( and nsd_20v_drn ( select -interact dnwell ngate_v20_zvt ) ) ( not diffi polyi ) ) ( select -interact diffi ngate_v20_zvt ) -lt 2.0 -abut -lt 90 -output region |
| } |
| rule "denmos_20.LEN.3" { |
| caption "denmos_20.LEN.3: Min channel width of zvt 20v nmos drain extended device < 30.0" |
| edge_expand ( edge_length ( edge_boolean -coincident_only ngate_v20_zvt nsd_20v_src ) -lt 30.0 ) -outside_by 0.05 |
| } |
| rule "denmos_20.ANG.3" { |
| caption "denmos_20.ANG.3: 90 degree corners are not allowed on the drain_diff of the zvt 20v nmos drain extended device" |
| select -enclose diffi ( inte ( select -interact -not ( and diffi ( and nsd_20v_drn ( select -interact dnwell ngate_v20_zvt ) ) ) polyi ) -lt 0.05 -abut -eq 90 -output region ) |
| } |
| rule "denmos_20.ENC.7" { |
| caption "denmos_20.ENC.7: Min enclosure of drain tap by dnwell in the direction of current flow of zvt 20v nmos drain extended device < 3.0" |
| enc ( edge_boolean -coincident_only ( select -interact -not ( and diffi ( and nsd_20v_drn ( select -interact dnwell ngate_v20_zvt ) ) ) polyi ) nwell ) dnwell -lt 3.0 -abut -lt 90 -output region |
| } |
| rule "denmos_20.WID.15" { |
| caption "denmos_20.WID.15: Min channel length of zvt 20v nmos drain extended device < 5.5" |
| inte ngate_v20_zvt -lt 5.5 -abut -lt 90 -output region -metric opposite -para |
| } |
| rule "denmos_20.EXT.3" { |
| caption "denmos_20.EXT.3: Min poly field extension past diffusion of zvt 20v nmos drain extended device < 1.0" |
| enc ( select -interact diffi nsd_20v_drn ) ( select -interact polyi ngate_v20_zvt ) -lt 1.0 -abut -lt 90 -output region |
| } |
| rule "denmos_20.SP.6" { |
| caption "denmos_20.SP.6: Min space from P+ tap to source of zvt 20v nmos drain extended device < 0.5" |
| exte ptap ( select -interact nsd_20v_src ( select -interact ENID ngate_v20_zvt ) ) -lt 0.5 -abut -lt 90 -output region |
| } |
| rule "denmos_20.XOR.2" { |
| caption "denmos_20.XOR.2: lvtn must be coincident with pwbm of zvt 20v nmos drain extended device" |
| xor ( select -interact ( select -interact lvtn ENID ) ngate_v20_zvt ) ( select -interact ( select -interact pwbm ENID ) ngate_v20_zvt ) |
| } |
| rule "denmos_20.ENC.8" { |
| caption "denmos_20.ENC.8: Min pwbm enclosure of dnwell of zvt 20v nmos drain extended device < 6.0" |
| edge_boolean -inside dnwell ( select -interact diffi ngate_v20_zvt ) -outputlayer dnw_edge |
| enc dnw_edge pwbm -lt 6.0 -abut -lt 90 -output region |
| } |
| rule "denmos_20.ENC.9" { |
| caption "denmos_20.ENC.9: Min enclosure of drain by nwell of zvt 20v nmos drain extended device < 0.05" |
| edge_length ( edge_boolean -coincident_only -not ( and ( select -interact nsd_20v_drn ( select -interact ENID ngate_v20_zvt ) ) diffi ) nwell ) -gt 10 -outputlayer dnm_20_drn_not_coin_edge_nw |
| enc dnm_20_drn_not_coin_edge_nw nwell -lt 0.05 -abut -lt 90 -output region -metric opposite -para |
| } |
| |
| |
| // |
| // iso denmos 20v checks |
| // |
| |
| |
| |
| rule "denmos_20.WID.16" { |
| caption "denmos_20.WID.16: Min width of gate poly in iso 20v nmos drain extended device < 2.5" |
| inte ( select -interact poly ngate_v20_iso_rec ) -lt 2.5 -abut -lt 90 -output region |
| } |
| rule "denmos_20.WID.17" { |
| caption "denmos_20.WID.17: Min width of source in iso 20v nmos drain extended device < 0.63" |
| inte ( select -interact nsd_20v_src ngate_v20_iso_rec ) -lt 0.63 -abut -lt 90 -output region |
| } |
| rule "denmos_20.WID.18" { |
| caption "denmos_20.WID.18: Min width of gate of iso 20v nmos drain extended device < 1.5" |
| inte ( select -interact ( select -interact ( and diffi poly ) ENID ) ( select -interact dnwell ngate_v20_iso_rec ) ) -lt 1.5 -abut -lt 90 -output region |
| } |
| rule "denmos_20.WID.19" { |
| caption "denmos_20.WID.19: Min width of drain of iso 20v nmos drain extended device < 1.5" |
| inte ( and ( and nsd_20v_drn ( select -interact dnwell ngate_v20_iso_rec ) ) ( not diffi polyi ) ) -lt 1.5 -abut -lt 90 -output region -metric opposite -para |
| } |
| rule "denmos_20.OVL.5" { |
| caption "denmos_20.OVL.5: Min extension of pwbm over channel of iso 20v nmos drain extended device < 1.0" |
| inte ( not ( and ( select -interact pwbm ngate_v20_iso_rec ) diffi ) ( and ( and nsd_20v_drn ( select -interact pwbm ngate_v20_iso_rec ) ) ( not diffi polyi ) ) ) -lt 1.0 -abut -lt 90 -output region |
| } |
| rule "denmos_20.SP.7" { |
| caption "denmos_20.SP.7: Min space from drain_diff to gate or src_diff of iso 20v nmos drain extended device < 2.0" |
| exte ( and ( and nsd_20v_drn ( select -interact dnwell ngate_v20_iso_rec ) ) ( not diffi polyi ) ) ( select -interact diffi ngate_v20_iso_rec ) -lt 2.0 -abut -lt 90 -output region |
| } |
| rule "denmos_20.LEN.4" { |
| caption "denmos_20.LEN.4: Min channel width of iso 20v nmos drain extended device < 30.0" |
| edge_expand ( edge_length ( edge_boolean -coincident_only ngate_v20_iso_rec nsd_20v_src ) -lt 30.0 ) -outside_by 0.05 |
| } |
| rule "denmos_20.ANG.4" { |
| caption "denmos_20.ANG.4: 90 degree corners are not allowed on the drain_diff of the iso 20v nmos drain extended device" |
| select -enclose diffi ( inte ( select -interact -not ( and diffi ( and nsd_20v_drn ( select -interact dnwell ngate_v20_iso_rec ) ) ) polyi ) -lt 0.05 -abut -eq 90 -output region ) |
| } |
| rule "denmos_20.WID.20" { |
| caption "denmos_20.WID.20: Min channel length of iso 20v nmos drain extended device < 0.5" |
| inte ngate_v20_iso_rec -lt 0.5 -abut -lt 90 -output region -metric opposite -para |
| } |
| rule "denmos_20.EXT.4" { |
| caption "denmos_20.EXT.4: Min poly field extension past diffusion of iso 20v nmos drain extended device < 1.0" |
| enc ( select -interact diffi nsd_20v_drn ) ( select -interact polyi ngate_v20_iso_rec ) -lt 1.0 -abut -lt 90 -output region |
| } |
| rule "denmos_20.SP.8" { |
| caption "denmos_20.SP.8: Min space from P+ tap to source of iso 20v nmos drain extended device < 0.5" |
| and ( and ( not ( and diff psdm ) pwbm ) dnwell ) ( holes pwbm ) -outputlayer n20_iso_ptap |
| exte n20_iso_ptap ( select -interact nsd_20v_src ( select -interact ENID ngate_v20_iso_rec ) ) -lt 0.5 -abut -lt 90 -output region |
| } |
| rule "denmos_20.XOR.3" { |
| caption "denmos_20.XOR.3: lvtn inside poly must be coincident with pwbm inside poly of isolated 20v nmos drain extended device" |
| or ( select -interact polyi ngate_v20_iso_rec ) ( holes ( select -interact polyi ngate_v20_iso_rec ) ) -outputlayer poly_healed |
| size poly_healed -by -0.5 -outputlayer poly_healed_size |
| xor ( and ( select -interact ( select -interact lvtn ENID ) ngate_v20_iso_rec ) poly_healed_size ) ( select -interact ( and ( select -interact pwbm ENID ) poly_healed_size ) ngate_v20_iso_rec ) |
| } |
| rule "denmos_20.ENC.10" { |
| caption "denmos_20.ENC.10: Min enclosure of drain by nwell of iso 20v nmos drain extended device < 0.05" |
| edge_length ( edge_boolean -coincident_only -not ( and ( select -interact nsd_20v_drn ( select -interact ENID ngate_v20_iso_rec ) ) diffi ) nwell ) -gt 10 -outputlayer dnm_20_drn_not_coin_edge_nw |
| enc dnm_20_drn_not_coin_edge_nw nwell -lt 0.05 -abut -lt 90 -output region -metric opposite -para |
| } |
| |
| // |
| // depmos checks |
| // |
| |
| |
| |
| select -enclose thkox ( select -interact nwell ( and ENID dnwell ) ) -outputlayer dePFetDevice |
| select -interact nwell dePFetDevice -outputlayer dePFetNwell |
| holes dePFetNwell -outputlayer dePFetNwellHole |
| select -interact diffi dePFetNwellHole -outputlayer dePFetDiff |
| select -interact ( and poly ENID ) dePFetDiff -outputlayer dePFetGate |
| select -interact dePFetDiff dePFetGate -outputlayer dePFetSource |
| and dePFetSource dePFetGate -outputlayer dePFetSourceAndPoly |
| not dePFetSource dePFetGate -outputlayer dePFetSourceNotPoly |
| select -inside diffi dePFetNwellHole -outputlayer dePFetDrain |
| bbox dePFetDrain -outputlayer dePFetDrainBB |
| edge_select -coincident_only dePFetDrain dePFetDrainBB -outputlayer dePFetDrainEdges |
| and ( and dePFetNwellHole ENID ) dePFetSource -outputlayer dePFetSourceOvlNwellHole |
| inte dePFetSourceOvlNwellHole -eq 0.26 -output region -outputlayer dePFetSourceGood |
| not ( and ENID dePFetNwellHole ) ( or dePFetSource dePFetDrainBB ) -outputlayer dePFetSourceToDrainRegion |
| inte dePFetSourceToDrainRegion -eq 1.19 -para -output region -outputlayer dePFetSourceToDrainSpacingGood |
| rule "depmos.WID.1" { |
| caption "depmos.WID.1: Min width of de_pFet_gate < 1.05" |
| inte dePFetGate -lt 1.05 -abut -lt 90 -single_point -output region |
| } |
| rule "depmos.WID.2" { |
| caption "depmos.WID.2: Min width of de_pFet_source not overlapping poly < 0.28" |
| inte dePFetSourceNotpoly -lt 0.28 -abut -lt 90 -single_point -output region |
| } |
| rule "depmos.WID.3" { |
| caption "depmos.WID.3: Min width of de_pFet_source overlapping poly < 0.92" |
| inte dePFetSourceAndPoly -lt 0.92 -abut -lt 90 -single_point -output region |
| } |
| rule "depmos.WID.4" { |
| caption "depmos.WID.4: Min width of the de_pFet_drain < 0.17" |
| edge_length dePFetDrainEdges -lt 0.17 |
| } |
| rule "depmos.EXT.1" { |
| caption "depmos.EXT.1: Min/Max extension of de_pFet_source beyond nwell = 0.26" |
| select -interact -not ( not dePFetSourceOvlNwellHole dePFetSourceGood ) ( select -interact ENID pgate_de_20v ) |
| } |
| rule "depmos.SP.2" { |
| caption "depmos.SP.2: Min/Max spacing between de_pFET_source and de_pFET_drain = 1.19" |
| select -interact -not ( not dePFetSourceToDrainRegion dePFetSourceToDrainSpacingGood ) ( select -interact ENID pgate_de_20v ) |
| } |
| rule "depmos.WID.5" { |
| caption "depmos.WID.5: Min channel width for de_pFet_gate < 5.0" |
| edge_length ( edge_boolean -inside dePFetGate dePFetSource ) -lt 5.0 |
| } |
| rule "depmos.CON.1" { |
| caption "depmos.CON.1: 90-degree angles are not permitted for nwell hole overlapping de_pFET_drain" |
| select -interact -not ( edge_expand ( convex_edge dePFetNwellHole -angle1 -eq 90 -angle2 -gt 0 ) -outside_by 0.05 ) ( select -interact dnwell pgate_de_20v ) |
| } |
| rule "depmos.ENC.1" { |
| caption "depmos.ENC.1: Min enclosure of de_pFet_drain by nwell hole < 0.86" |
| enc dePFetDrain dePFetNwellHole -lt 0.86 -measure all -abut -lt 90 -single_point -output region |
| } |
| rule "depmos.SP.3" { |
| caption "depmos.SP.3: Min spacing between n+ tap and (nwell hole enclosing de_pFET_drain) < 0.66" |
| and ( select -outside diffi dePFetNwellHole ) dePFetDevice -outputlayer dePFetNtap |
| exte dePFetNtap dePFetNwellHole -lt 0.66 -abut -lt 90 -single_point -output region |
| } |
| rule "depmos.ENC.2" { |
| caption "depmos.ENC.2: de_pFet_source must be enclosed by psdm < 0.13" |
| enc dePFetSource psdm -lt 0.13 -measure all -abut -lt 90 -single_point -output region |
| } |
| rule "depmos.CON.2" { |
| caption "depmos.CON.2: de_pFet_source must be enclosed by psdm" |
| not dePFetSource psdm |
| } |
| |
| |
| // |
| // denpos 20v checks |
| // |
| |
| |
| |
| and ( not ( and ( and ( and ( and poly v20 ) thkox ) diff ) psdm ) lvtn ) ( select -interact ENID pwde ) -outputlayer pgate_de_20v |
| select -interact ( not ( and diff psdm ) pgate_de_20v ) pgate_de_20v -outputlayer psd_20v |
| edge_expand ( edge_boolean -coincident_only ( not psd_20v pgate_de_20v ) ENID ) -outside_by 0.05 -outputlayer psd_20v_src_1 |
| select -touch ( not psd_20v pgate_de_20v ) psd_20v_src_1 -eq 3 -outputlayer psrc_de_20v |
| not ( select -interact ENID pgate_de_20v ) ( or pgate_de_20v psrc_de_20v ) -outputlayer pdrn_de_20v |
| rule "depmos_20.WID.1" { |
| caption "depmos_20.WID.1: Min width of gate poly in 20v pmos drain extended device < 2.0" |
| inte ( select -interact poly pgate_de_20v ) -lt 2.0 -abut -lt 90 -output region |
| } |
| rule "depmos_20.WID.2" { |
| caption "depmos_20.WID.2: Min width of source of 20v pmos drain extended device < 0.29" |
| inte psrc_de_20v -lt 0.29 -abut -lt 90 -output region |
| } |
| rule "depmos_20.WID.3" { |
| caption "depmos_20.WID.3: Min width of gate of 20v pmos drain extended device < 1.5" |
| inte ( select -interact ( select -interact ( and diffi poly ) ENID ) ( select -interact dnwell pgate_de_20v ) ) -lt 1.5 -abut -lt 90 -output region |
| } |
| rule "depmos_20.WID.4" { |
| caption "depmos_20.WID.4: Min width of drain of 20v pmos drain extended device < 0.75" |
| inte ( and ( and pdrn_de_20v ( select -interact dnwell pgate_de_20v ) ) ( not diffi polyi ) ) -lt 0.75 -abut -lt 90 -output region -metric opposite -para |
| } |
| rule "depmos_20.WID.5" { |
| caption "depmos_20.WID.5: Min width of pwde AND diff AND poly < 0.5" |
| inte ( and ( select -interact pwde ( select -interact polyi pdrn_de_20v ) ) diffi ) -lt 0.5 -abut -lt 90 -output region |
| } |
| rule "depmos_20.SP.1" { |
| caption "depmos_20.SP.1: Min space from drain_diff to gate or src_diff of 20v pmos drain extended device < 1.5" |
| exte ( and ( and pdrn_de_20v ( select -interact dnwell pgate_de_20v ) ) ( not diffi polyi ) ) ( select -interact diffi pgate_de_20v ) -lt 1.5 -abut -lt 90 -output region |
| } |
| rule "depmos_20.LEN.1" { |
| caption "depmos_20.LEN.1: Min channel width of 20v pmos drain extended device < 30.0" |
| edge_expand ( edge_length ( edge_boolean -coincident_only pgate_de_20v psrc_de_20v ) -lt 30.0 ) -outside_by 0.05 |
| } |
| rule "depmos_20.ANG.1" { |
| caption "depmos_20.ANG.1: 90 degree corners are not allowed on the drain_diff of the 20v pmos drain extended device" |
| select -enclose diffi ( inte ( select -interact -not ( and diffi pdrn_de_20v ) polyi ) -lt 0.05 -abut -eq 90 -output region ) |
| } |
| rule "depmos_20.ENC.1" { |
| caption "depmos_20.ENC.1: Min enclosure of drain tap by pwbm in the direction of current flow of 20v pmos drain extended device < 3.0" |
| enc ( edge_boolean -coincident_only ( select -interact -not ( and diffi ( and pdrn_de_20v ( select -interact dnwell pgate_de_20v ) ) ) polyi ) ENID ) pwbm -lt 3.0 -abut -lt 90 -output region |
| } |
| rule "depmos_20.ENC.2" { |
| caption "depmos_20.ENC.2: Min enclosure of drain tap by pwde in the direction of current flow of 20v pmos drain extended device < 2.5" |
| enc ( edge_boolean -coincident_only ( select -interact -not ( and diffi ( and pdrn_de_20v ( select -interact dnwell pgate_de_20v ) ) ) polyi ) ENID ) pwde -lt 2.5 -abut -lt 90 -output region |
| } |
| rule "depmos_20.ENC.3" { |
| caption "depmos_20.ENC.3: Min enclosure of pwde by pwdm of 20v pmos drain extended device < 0.5" |
| enc ( select -interact pwde ( select -interact ENID pdrn_de_20v ) ) ( select -interact pwbm ( select -interact ENID pdrn_de_20v ) ) -lt 0.5 -abut -lt 90 -output region |
| } |
| rule "depmos_20.WID.6" { |
| caption "depmos_20.WID.6: Min channel length of 20v pmos drain extended device < 0.5" |
| inte pgate_de_20v -lt 0.5 -abut -lt 90 -output region |
| } |
| rule "depmos_20.EXT.1" { |
| caption "depmos_20.EXT.1: Min poly field extension past diffusion of 20v pmos drain extended device < 0.5" |
| enc ( select -interact diffi pdrn_de_20v ) ( select -interact polyi pgate_de_20v ) -lt 0.5 -abut -lt 90 -output region |
| } |
| rule "depmos_20.SP.2" { |
| caption "depmos_20.SP.2: Min space from ntap to source of 20v pmos drain extended device < 0.29" |
| exte ntap psrc_de_20v -lt 0.29 -abut -lt 90 -output region |
| } |
| |
| |
| // |
| // pwres checks |
| // |
| |
| |
| |
| not dnwell nwellring -outputlayer DnwNoRing |
| and pwres DnwNoRing -outputlayer PwresDnw |
| edge_boolean -coincident_only -outside PwresDnw nwell -outputlayer PwresNwell |
| select -with_edge PwresDnw PwresNwell -eq 2 -outputlayer GoodPwresNwell |
| not PwresDnw GoodPwresNwell -outputlayer BadPwresNwell |
| edge_select -coincident_only PwresDnw tap -outputlayer PwresTap |
| select -with_edge PwresDnw PwresTap -eq 2 -outputlayer GoodPwresTap |
| not PwresDnw GoodPwresTap -outputlayer BadPwresTap |
| select -with_edge tap ( edge_boolean -coincident_only -outside tap GoodPwresTap ) -outputlayer PwresTerm |
| exte PwresTerm nwell -eq 0.22 -abut -lt 90 -single_point -output region -outputlayer GoodPwTap |
| edge_boolean -coincident_only -not PwresTerm PwresDnw -outputlayer PwresTermOutEdge |
| edge_boolean -coincident_only -not PwresTermOutEdge GoodPwTap -outputlayer BadPwTap |
| size ( size PwresTerm -by "-(0.53/2)" ) -by "(0.53/2)" -outputlayer BadTapW |
| select -interact PwresTerm ( and PwresTerm Licon ) -eq 12 -outputlayer GoodTapLicon |
| select -interact PwresTerm ( and PwresTerm Mcon ) -eq 12 -outputlayer GoodTapMcon |
| not PwresTerm GoodTapLicon -outputlayer BadTapLicon |
| not PwresTerm GoodTapMcon -outputlayer BadTapMcon_tmp |
| and BadTapMcon_tmp met1 -outputlayer BadTapMcon |
| select -touch nwell PwresDnw -outputlayer nwellEnclosePwres |
| and ( select -donut tap ) nwellEnclosePwres -outputlayer tapRing |
| and licon tapRing -outputlayer tapRingLicon |
| select -interact li tapRingLicon -outputlayer tapRingLi1 |
| and mcon tapRingLi1 -outputlayer tapRingMcon |
| select -interact met1 tapRingMcon -outputlayer tapRingMet1 |
| select -interact tapRing tapRingMet1 -outputlayer tapRingMetStrap |
| not nwellEnclosePwres ( select -interact nwell tapRingMetStrap ) -outputlayer nonTapwell |
| rule "pwres.CON.1" { |
| caption "pwres.CON.1: pwres must be inside dnwell and inside an nwell hole" |
| not pwres DnwNoRing |
| } |
| rule "pwres.CON.2" { |
| caption "pwres.CON.2: pwres enclosed by dnwell should be rectangular" |
| rect_chk -not PwresDnw -orthogonal_only |
| } |
| rule "pwres.WID.1" { |
| caption "pwres.WID.1: Min/Max width of pwres = 2.65" |
| inte PwresDnw -lt 2.65 -output region -outputlayer pwresWidth1 |
| inte PwresDnw -eq 2.65 -output region -outputlayer pwresWidth2 |
| or pwresWidth1 ( not PwresDnw pwresWidth2 ) |
| } |
| rule "pwres.LEN.1" { |
| caption "pwres.LEN.1: Min length of pwres < 26.50" |
| inte PwresDnw -lt 26.50 -project -lt 26.50 -output region |
| } |
| rule "pwres.LEN.2" { |
| caption "pwres.LEN.2: Max length of pwres = 265.00" |
| select -with_edge PwresDnw ( edge_length PwresDnw -gt 265.00 ) |
| } |
| rule "pwres.SP.1" { |
| caption "pwres.SP.1: Min/Max spacing of a tap inside the pwell resistor to nwell = 0.22" |
| copy BadPwTap |
| } |
| rule "pwres.WID.2" { |
| caption "pwres.WID.2: Min width of pwres terminal < 0.53" |
| inte PwresTerm -lt 0.53 -abut -lt 90 -single_point -output region |
| } |
| rule "pwres.CON.3" { |
| caption "pwres.CON.3: pwres cannot be wider than width of pwell resistor P+ tap" |
| copy BadTapW |
| } |
| rule "pwres.CON.4" { |
| caption "pwres.CON.4: P+ tap of pwell resister terminal must enclose 12 licons" |
| or BadTapLicon BadTapMcon |
| } |
| rule "pwres.CON.5a" { |
| caption "pwres.CON.5a: diff or poly is not allowed in the pwell resistor" |
| and ( or diff poly ) PwresDnw |
| } |
| rule "pwres.CON.6" { |
| caption "pwres.CON.6: N+ tap inside nwell ring of pwres must have metal straps" |
| copy nonTapwell |
| } |
| rule "pwres.CON.7" { |
| caption "pwres.CON.7: pwell:res must abut pwell resistor terminals on opposite and parallel edges" |
| copy BadPwresTap |
| } |
| rule "pwres.CON.8" { |
| caption "pwres.CON.8: pwell res must abut nwell edges on opposite sides" |
| copy BadPwresNwell |
| } |
| |
| |
| // |
| // hnwell checks |
| // |
| |
| |
| |
| not ( or ( select -interact nwell v12 ) ( select -interact nwell v20 ) ) exempt_tech_CD -outputlayer nw_12_20v |
| |
| |
| // |
| // hpoly checks |
| // |
| |
| |
| and gate_PERI v5 -outputlayer gateHV_PERI |
| edge_boolean -coincident_only poly gateHV_PERI -outputlayer gateEdgeHV_PERI |
| inte gateEdgeHV_PERI -lt 0.5 -metric opposite -para ONLY -output region -outputlayer gateEdgeHV_PERI_err |
| rule "hpoly.WID.1" { |
| caption "hpoly.WID.1: Min width of poly over diff inside v5 in periphery < 0.5" |
| inte gateEdgeHV_PERI_err -lt 0.5 -abut -lt 90 -single_point -output region |
| } |
| rule "hpoly.CON.1" { |
| caption "hpoly.CON.1: gate must not straddle v5" |
| select -cut GATE v5 |
| } |
| |
| |
| // |
| // extd checks |
| // |
| |
| |
| |
| select -interact poly ( and poly ENID ) -outputlayer deFetPoly |
| and deFetPoly ENID -outputlayer deFetGate |
| select -inside difftap ENID -outputlayer difftapInsideEnid |
| edge_boolean -coincident_only -inside difftapInsideEnid ENID -outputlayer difftapEndidEdg |
| edge_expand difftapEndidEdg -outside_by 0.005 -outputlayer difftapEndidEdgExp |
| select -touch difftapInsideEnid difftapEndidEdgExp -lege 2 3 -outputlayer goodHvdifftap |
| not difftapInsideEnid goodHvdifftap -outputlayer badHvdifftap |
| not deFetGate difftapInsideEnid -outputlayer polyGap |
| rule "extd.CON.1" { |
| caption "extd.CON.1: diff must not straddle areaid:extendedDrain" |
| select -cut difftap ENID |
| } |
| rule "extd.CON.2" { |
| caption "extd.CON.2: diff must have two or three coincident edges with areaid:extendedDrain if enclosed by areaid:extendedDrain" |
| copy badHvdifftap |
| } |
| rule "extd.CON.3" { |
| caption "extd.CON.3: poly must extend beyond overlapping diffusion inside areaid:extendedDrain" |
| select -outside deFetPoly polyGap |
| } |
| |
| |
| // |
| // npc checks |
| // |
| |
| |
| |
| select -donut licon -outputlayer ringLCON1 |
| not licon ringLCON1 -outputlayer rectLCON1 |
| and rectLCON1 ( or rpm urpm ) -outputlayer LCON1AndRpm |
| select -with_edge ( with_width LCON1AndRpm -eq 0.19 ) ( edge_length LCON1AndRpm -eq 2.0 ) -outputlayer slotted_licon |
| select -enclose polyi slotted_licon -outputlayer poly_with_slotlicon |
| select -interact -not npc poly_with_slotlicon -outputlayer npc_no_hrpoly |
| angle poly_with_slotlicon -eq 0 -outputlayer poly_edges_horiz |
| angle poly_with_slotlicon -eq 90 -outputlayer poly_edges_vert |
| rule "npc.WID.1" { |
| caption "npc.WID.1: Min width of npc < 0.270" |
| inte npc -lt 0.270 -abut -lt 90 -single_point -output region |
| } |
| rule "npc.SP.1" { |
| caption "npc.SP.1: Min spacing/notch of npc < 0.270" |
| exte npc -lt 0.270 -abut -lt 90 -single_point -output region |
| } |
| rule "npc.SP.2" { |
| caption "npc.SP.2: Min spacing of npc & gate < 0.090" |
| exte npc GATE -lt 0.090 -abut -lt 90 -single_point -output region |
| } |
| rule "npc.CON.1" { |
| caption "npc.CON.1: npc must not overlap gate" |
| and npc GATE |
| } |
| |
| |
| // |
| // diff dummy (formally fom/dummy) |
| // |
| |
| |
| |
| rule "diff_fill.WID.1" { |
| caption "diff_fill.WID.1: Min width of diff fill < 0.50" |
| inte diff_fill -lt 0.50 -abut -lt 90 -single_point -output region |
| } |
| rule "diff_fill.WID.2" { |
| caption "diff_fill.WID.2: Max width of diff fill > 25.00" |
| edge_length diff_fill -gt 25.00 |
| } |
| rule "diff_fill.SP.1" { |
| caption "diff_fill.SP.1: Min spacing/notch of diff fill < 0.40" |
| exte diff_fill -lt 0.40 -abut -lt 90 -single_point -output region |
| } |
| rule "diff_fill.SP.2" { |
| caption "diff_fill.SP.2: Min spacing of diff fill to areaid:seal < 1.00" |
| exte diff_fill SEALID -lt 1.00 -abut -lt 90 -single_point -output region |
| } |
| rule "diff_fill.CON.1" { |
| caption "diff_fill.CON.1: diff fill must not overlap areaid:seal" |
| and diff_fill SEALID |
| } |
| rule "diff_fill.SP.4" { |
| caption "diff_fill.SP.4: Min spacing of diff fill to nsdm < 0.13" |
| exte diff_fill nsdm -lt 0.13 -abut -lt 90 -single_point -output region |
| } |
| rule "diff_fill.CON.3" { |
| caption "diff_fill.CON.3: diff fill must not overlap nsdm" |
| and diff_fill nsdm |
| } |
| rule "diff_fill.SP.5" { |
| caption "diff_fill.SP.5: Min spacing of diff fill to psdm < 0.13" |
| exte diff_fill psdm -lt 0.13 -abut -lt 90 -single_point -output region |
| } |
| rule "diff_fill.CON.4" { |
| caption "diff_fill.CON.4: diff fill must not overlap psdm" |
| and diff_fill psdm |
| } |
| rule "diff_fill.ENC.1" { |
| caption "diff_fill.ENC.1: Min enclosure of diff fill by nwell < 0.18" |
| enc ( and diff_fill nwell ) nwell -lt 0.18 -measure all -abut -lt 90 -single_point |
| } |
| rule "diff_fill.SP.6" { |
| caption "diff_fill.SP.6: Min spacing of diff fill to nwell < 0.34" |
| exte diff_fill nwell -lt 0.34 -abut -lt 90 -single_point -output region |
| } |
| select -interact -not ( select -interact nwell v5 ) ( or v12 v20 ) -outputlayer five_volt_nw |
| rule "diff_fill.ENC.2" { |
| caption "diff_fill.ENC.2: Min enclosure of diff fill by 5 volt nwell < 0.43" |
| enc ( and diff_fill five_volt_nw ) five_volt_nw -lt 0.43 -measure all -abut -lt 90 -single_point |
| } |
| rule "diff_fill.SP.7" { |
| caption "diff_fill.SP.7: Min spacing of diff fill to HVnwell < 0.33" |
| exte diff_fill five_volt_nw -lt 0.33 -abut -lt 90 -single_point -output region |
| } |
| rule "diff_fill.ENC.3" { |
| caption "diff_fill.ENC.3: Min enclosure of diff fill by areaid:frame < 0.50" |
| enc ( and diff_fill FRAMEID ) FRAMEID -lt 0.50 -measure all -abut -lt 90 -single_point |
| } |
| rule "diff_fill.SP.8" { |
| caption "diff_fill.SP.8: Min spacing of diff fill to areaid:dieCut < 0.50" |
| exte diff_fill dieCut -lt 0.50 -abut -lt 90 -single_point -output region |
| } |
| |
| |
| // |
| // diff_v5 checks |
| // |
| |
| |
| |
| and ( and diffi v5 ) thkox -outputlayer diffHV |
| and diffHV COREID -outputlayer diffHV_CORE |
| not diffHV COREID -outputlayer diffHV_PERI |
| and diffHV_PERI ( and diffRes nwell ) -outputlayer diffHVpRes_PERI |
| select -interact diffHVpRes_PERI ( edge_expand ( edge_length ( edge_boolean -inside diffHVpRes_PERI diffHV ) -ge 0.29 ) -inside_by 0.005 ) -outputlayer diffHVpResNormSize |
| or ( not diffHV_PERI diffHVpRes_PERI ) diffHVpResNormSize -outputlayer diffHVnopRes_PERI |
| and ( and NDIFF v5 ) thkox -outputlayer ndiffHV |
| not ndiffHV COREID -outputlayer ndiffHV_PERI |
| and ( and tap v5 ) thkox -outputlayer tapHV |
| not tapHV COREID -outputlayer tapHV_PERI |
| and ( and PTAP v5 ) thkox -outputlayer ptapHV |
| not ptapHV COREID -outputlayer ptapHV_PERI |
| select -interact ( and diffTap v5 ) thkox -outputlayer diffTapHV |
| not diffTapHV ( or COREID v20 ) -outputlayer diffTapHV_PERI_nonV20 |
| not diffTap ( and v5 thkox ) -outputlayer diffTapNoHv |
| not diffTapNoHv COREID -outputlayer diffTapNoHv_PERI |
| not NTAP_PERI ( or ESD_nwell_tap v20 ) -outputlayer NTAP_nonESD_nonv20 |
| and NTAP_nonESD_nonv20 ( or ( and v5 thkox ) HVNID ) -outputlayer nTapHV_nonESD_v20 |
| select -touch -not ptapHV_PERI ndiffHV_PERI -outputlayer ptapHV_PERI_noAbut |
| not PTAP ( select -touch PTAP pwres ) -outputlayer PTAP_noPwellRes |
| not ( not ndiffHV ESDID ) ENID -outputlayer ndiffHV_nonESD |
| not ( not NDIFF ESD_nwell_tap ) ENID -outputlayer ndiff_nonESD |
| not ( and ( and ( not PDIFF ESD_nwell_tap ) ( or v5 HVNID ) ) thkox ) ( or ENID v20 ) -outputlayer pdiffHV_nonESD |
| not diffHV v20 -outputlayer diffHV_noV20 |
| not tapHV v20 -outputlayer tapHV_noV20 |
| not ndiff_nonESD v20 -outputlayer ndiff_nonESDv20 |
| not ndiffHV_nonESD v20 -outputlayer ndiffHV_nonESDv20 |
| not PTAP_noPwellRes v20 -outputlayer PTAP_noPwellRes_noV20 |
| rule "diff_5v.WID.1" { |
| caption "diff_5v.WID.1: Min width of diff (not tap) in v5 and periphery (exempt for pdiff resistor inside v5) < 0.29" |
| inte ( not ( or diffHVnopRes_PERI ( select -interact diffres diffHVnopRes_PERI ) ) tap ) -lt 0.29 -abut -lt 90 -single_point -output region |
| } |
| rule "diff_5v.WID.2" { |
| caption "diff_5v.WID.2: Min width of pdiff resistor inside v5 in periphery < 0.15" |
| inte ( not ( and ( and ( and nwell diffi ) diffRes ) v5 ) COREID ) -lt 0.15 -abut -lt 90 -single_point -output region |
| } |
| rule "diff_5v.SP.1" { |
| caption "diff_5v.SP.1: Min spacing/notch of diff inside v5 and periphery < 0.3" |
| exte ( not diffHV_PERI tap ) -lt 0.3 -abut -lt 90 -single_point -output region |
| } |
| rule "diff_5v.SP.2" { |
| caption "diff_5v.SP.2: Min space of n+diff to non-abutting p+tap inside v5 < 0.37" |
| exte ndiffHV_PERI ptapHV_PERI_noAbut -lt 0.37 -abut -lt 90 -single_point -output region |
| } |
| edge_expand ( edge_boolean -coincident_only diffHV_noV20 tapHV ) -outside_by 0.05 -outputlayer butting_edge_marker |
| rule "diff_5v.WID.3" { |
| caption "diff_5v.WID.3: Min width tap butting diff on one or two sides inside v5 (rule exempted inside v20) < 0.7" |
| inte ( select -touch PTAP butting_edge_marker -eq 3 ) -lt 0.7 -abut -lt 90 -output region |
| } |
| rule "diff_5v.WID.4" { |
| caption "diff_5v.WID.4: Min width of abutting tap abutting and between diff inside v5 < 0.7" |
| inte ( select -touch PTAP butting_edge_marker -eq 2 ) -lt 0.7 -abut -lt 90 -output region |
| } |
| rule "diff_5v.ENC.1" { |
| caption "diff_5v.ENC.1: nwell inside v5 min enclosure of (pdiff outside areaid:esd) < 0.33" |
| enc ( and pdiffHV_nonESD five_volt_nw ) five_volt_nw -lt 0.33 -measure all -abut -lt 90 -single_point |
| } |
| rule "diff_5v.SP.3" { |
| caption "diff_5v.SP.3: Min spacing of ndiff (outside areaid:ESD) to nwell inside v5 < 0.43" |
| exte ndiff_nonESDv20 five_volt_nw -lt 0.43 -abut -lt 90 -single_point -output region |
| } |
| rule "diff_5v.ENC.2" { |
| caption "diff_5v.ENC.2: nwell inside v5 min enclosure of (ntap outside areaid:esd) < 0.33" |
| enc ( and nTapHV_nonESD_v20 five_volt_nw ) five_volt_nw -lt 0.33 -measure all -abut -lt 90 -single_point -output region |
| } |
| rule "diff_5v.SP.4" { |
| caption "diff_5v.SP.4: Min spacing of P+ tap to nwell inside v5 (Exempt for p+tap butting pwell resistor and inside v20) < 0.43" |
| exte PTAP_noPwellRes_noV20 five_volt_nw -lt 0.43 -abut -lt 90 -single_point -output region |
| } |
| rule "diff_5v.CON.1" { |
| caption "diff_5v.CON.1: diff in periphery must not straddle v5" |
| select -cut diffTap_PERI v5 |
| } |
| rule "diff_5v.CON.1a" { |
| caption "diff_5v.CON.1a: diff in periphery must not straddle thkox" |
| select -cut diffTap_PERI thkox |
| } |
| rule "diff_5v.ENC.3" { |
| caption "diff_5v.ENC.3: Min enclosure of diff inside v5 by thkox (exempt inside v20) < 0.18" |
| enc ( and diffTapHV_PERI_nonV20 thkox ) thkox -lt 0.18 -measure all -abut -lt 90 -single_point -output region |
| } |
| rule "diff_5v.SP.5" { |
| caption "diff_5v.SP.5: Min spacing between diff outside thkox to thkox < 0.18" |
| exte diffTapNoHv_PERI thkox -lt 0.18 -abut -lt 90 -single_point -output region |
| } |
| rule "diff_5v.SP.6" { |
| caption "diff_5v.SP.6: Min spacing of ndiff inside v5 (outside areaid:ESD and outside v20)) to nwell < 0.43" |
| exte ndiffHV_nonESDv20 nwell -lt 0.43 -abut -lt 90 -single_point -output region |
| } |
| |
| |
| // |
| // hv checks |
| // |
| |
| |
| |
| antenna nsd ( and nsd ( or v12 v20 ) ) -gt 0 -outputlayer hv_diff_n |
| antenna psd ( and psd ( or v12 v20 ) ) -gt 0 -outputlayer hv_diff_p |
| or hv_diff_n hv_diff_p -outputlayer hv_diff |
| select -touch -not hv_diff tap -outputlayer hv_diff_not_tap |
| connect li hv_diff_not_tap -by licon |
| not ( not diffi tap ) ( or v12 v20 ) -outputlayer lv_diff_not_tap |
| select -touch -not hv_diff_not_tap tap -outputlayer hv_diff_not_butting_tap |
| select -touch -not lv_diff_not_tap tap -outputlayer lv_diff_not_butting_tap |
| and ntap ( or v12 v20 ) -outputlayer shv_ntap |
| antenna nwell shv_ntap -gt 0 -outputlayer shv_nw |
| rule "hv.SP.1" { |
| caption "hv.SP.1: Minimum 12v or 20v source/drain spacing to diff for edges of 12v or 20v source/drain diff not butting tap < 0.3" |
| exte hv_diff_not_butting_tap diffi -lt 0.3 -abut -lt 90 -output region |
| } |
| antenna nsd hv_diff_not_tap -gt 0 -outputlayer nsd_net_hv_diff_1a |
| antenna psd hv_diff_not_tap -gt 0 -outputlayer psd_net_hv_diff_1b |
| or nsd_net_hv_diff_1a psd_net_hv_diff_1b -outputlayer net_conn_hv_diff |
| select -touch net_conn_hv_diff ( or rndiff rpdiff ) -outputlayer diff_res_term_touch_net_conn_hv_diff |
| select -touch ( or rpdiff rndiff ) diff_res_term_touch_net_conn_hv_diff -outputlayer diff_res_body_touch_diff_term_hv_net |
| rule "hv.SP.2" { |
| caption "hv.SP.2: Minimum spacing of n+/p+ diff resistors connected to 12v or 20v source/drain to diff < 0.3" |
| exte diff_res_body_touch_diff_term_hv_net diffi -lt 0.3 -abut -lt 90 -single_point -output region |
| } |
| and diffi DIODEID -outputlayer dio_body |
| and dio_body net_conn_hv_diff -outputlayer dio_body_conn_hv_diff |
| and dio_body_conn_hv_diff diffi -outputlayer diff_dio_conn_hv_diff |
| rule "hv.SP.3" { |
| caption "hv.SP.3: Minimum spacing of n+/p+ diff diodes connected to 12v or 20v source/drain to diff < 0.3" |
| exte diff_dio_conn_hv_diff diffi -lt 0.3 -abut -lt 90 -single_point -output region |
| } |
| antenna nwell hv_diff_not_tap -gt 0 -outputlayer nw_net_hv_diff |
| rule "hv.SP.4" { |
| caption "hv.SP.4: Minimum spacing of nwell connected to 12v or 20v source/drain to n+ diff < 0.43" |
| exte nw_net_hv_diff ( and diffi nsdm ) -lt 0.43 -abut -lt 90 -single_point -output region |
| } |
| rule "hv.SP.5" { |
| caption "hv.SP.5: Minimum N+ 12v or 20v source/drain spacing to nwell < 0.55" |
| exte hv_diff_not_tap nwell -lt 0.55 -abut -lt 90 -single_point -output region |
| } |
| rule "hv.SP.6" { |
| caption "hv.SP.6: Minimum spacing of n+ diff resistors connected to 12v or 20v source/drain to nwell < 0.55" |
| exte ( and diff_res_body_touch_diff_term_hv_net nsdm ) nwell -lt 0.55 -abut -lt 90 -single_point -output region |
| } |
| rule "hv.SP.7" { |
| caption "hv.SP.7: Minimum spacing of n+ diff diodes connected to 12v or 20v source/drain to nwell < 0.55" |
| exte ( and diff_dio_conn_hv_diff nsdm ) nwell -lt 0.55 -abut -lt 90 -single_point -output region |
| } |
| and gate ( and ( or v12 v20 ) thkox ) -outputlayer hv_gate |
| or nsd psd -outputlayer sd |
| or v12 v20 -outputlayer hv_mark |
| and sd hv_mark -outputlayer hv_sd |
| select -touch polyi ( and sd ( and hv_mark thkox ) ) -outputlayer hv_poly |
| net_interact hv_gate nsd -eq 2 -outputlayer poly_touch_nsd_tied |
| net_interact hv_gate psd -eq 2 -outputlayer poly_touch_psd_tied |
| or poly_touch_nsd_tied poly_touch_psd_tied -outputlayer poly_touch_sd_tied |
| select -interact hv_poly sd -gt 2 -outputlayer hv_poly_cross_gt_1_diff |
| rule "hv.CON.1" { |
| caption "hv.CON.1: 12v or 20v poly must overlap only one diff unless source and drains are tied" |
| select -interact -not hv_poly_cross_gt_1_diff poly_touch_sd_tied |
| } |
| inside_cell polyii "pmos_de_v12*" "pmos_de_v20*" "nmos_de_12" "nmos_de_v20" -outputlayer poly_x_nw_exempt |
| rule "hv.CON.2" { |
| caption "hv.CON.2: 12v or 20v poly cannot cross nwell boundary except for pmos drain extended devices" |
| not ( edge_expand ( edge_boolean -inside nwell hv_poly ) -outside_by 0.05 ) poly_x_nw_exempt |
| } |
| rule "hv.SP.8" { |
| caption "hv.SP.8: Min spacing of 12v or 20v poly to 1.8v, 3.3v or 5v diff (exempt for diff butting v12 or v20 poly) < 0.3" |
| select -touch diffi hv_poly -outputlayer diff_butt_poly |
| exte hv_poly ( not diffi ( or v12 v20 diff_butt_poly ) ) -lt 0.3 -abut -lt 90 -output region |
| } |
| rule "hv.SP.9" { |
| caption "hv.SP.9: Min spacing of 12v or 20v poly to nwell (exempt poly stradding nwell in a depmos) < 0.55" |
| exte ( not hv_poly poly_x_nw_exempt ) nwell -lt 0.55 -abut -lt 90 -single_point -output region |
| } |
| rule "hv.ENC.1" { |
| caption "hv.ENC.1: Min enclosure of 12v or 20v poly (including high voltage poly resistor) by nwell (exempt for poly straddling nwell in a depmos) < 0.3" |
| enc ( not ( and hv_poly nwell ) poly_x_nw_exempt ) nwell -lt 0.3 -output region -measure all -abut -lt 90 -single_point |
| } |
| inside_cell diffii "pmos_de_v12*" "pmos_de_v20*" "nmos_de_v12*" "nmos_de_v20*" -outputlayer diff_exempt |
| rule "hv.ENC.2" { |
| caption "hv.ENC.2: Min extension of poly beyond 12v or 20v gate (exempt poly extending beyond diff along the S/D direction in a denmos/depmos) < 0.16" |
| enc ( select -interact ( not diffi diff_exempt ) hv_sd ) polyi -lt 0.16 -abut -lt 90 -output region -single_point |
| } |
| |
| |
| // |
| // tunm checks |
| // |
| |
| |
| |
| rule "tunm.WID.1" { |
| caption "tunm.WID.1: Min width of tunm < 0.41" |
| inte tunm -lt 0.41 -abut -lt 90 -single_point -output region |
| } |
| rule "tunm.SP.1" { |
| caption "tunm.SP.1: Min spacing/notch of tunm to tunm < 0.5" |
| exte tunm -lt 0.5 -abut -lt 90 -single_point -output region |
| } |
| rule "tunm.ENC.1" { |
| caption "tunm.ENC.1: Extension of tunm beyond (poly and diff) < 0.095" |
| enc GATE tunm -lt 0.095 -measure coin -abut -lt 90 -single_point -output region |
| } |
| rule "tunm.SP.2" { |
| caption "tunm.SP.2: Min spacing of tunm to (poly and diff) outside tunm < 0.095" |
| exte ( not GATE tunm ) tunm -lt 0.095 -abut -lt 90 -single_point -output region |
| } |
| rule "tunm.CON.1" { |
| caption "tunm.CON.1: gate (poly and diff) may not straddle tunm" |
| select -cut GATE tunm |
| } |
| rule "tunm.CON.2" { |
| caption "tunm.CON.2: tunm outside deep n-well is not allowed" |
| not ( not tunm dnwell ) exempt_tech_CD |
| } |
| rule "tunm.AR.1" { |
| caption "tunm.AR.1: Min tunm area < 0.672" |
| area tunm -lt 0.672 |
| } |
| rule "tunm.CON.3" { |
| caption "tunm.CON.3: tunm must be enclosed by areaid:core" |
| not tunm COREID |
| } |
| |
| |
| // |
| // hvntm checks |
| // |
| |
| |
| |
| not hvntm COREID -outputlayer hvntm_peri |
| and ( and NDIFF v5 ) thkox -outputlayer ndiffInV5 |
| not ndiffInV5 ( and ndiffInV5 COREID ) -outputlayer ndiffInV5Peri |
| select -outside NDIFF v5 -outputlayer ndiffOutsideV5 |
| not PDIFF ENID -outputlayer PDIFF_notENID |
| edge_boolean -outside PTAP NDIFF -outputlayer PTAPnoButtDiff |
| edge_expand ( edge_boolean -coincident_only -outside NDIFF PTAP ) -outside_by 0.005 -outputlayer diffpTapButtEdge_sz |
| select -inside ESD_nwell_tap ( select -interact v5 thkox ) -outputlayer ESD_nwell_tap_inside_v5 |
| rule "hvntm.CON.2" { |
| caption "hvntm.CON.2: hvntm must be drawn inside v5 and thkox" |
| select -inside -not hvntm ( and v5 thkox ) |
| } |
| rule "hvntm.WID.1" { |
| caption "hvntm.WID.1: Min width of hvntm not in areaid:core < 0.7" |
| inte hvntm_peri -lt 0.7 -abut -lt 90 -single_point -output region |
| } |
| rule "hvntm.SP.1" { |
| caption "hvntm.SP.1: Min spacing/notch of hvntm not in areaid:core < 0.7" |
| exte hvntm_peri -lt 0.7 -abut -lt 90 -single_point -output region |
| } |
| rule "hvntm.ENC.1" { |
| caption "hvntm.ENC.1: Min enclosure of (n+_diff inside v5 and thkox) but not overlapping areaid:core by hvntm < 0.185" |
| enc ( and ndiffInV5Peri hvntm_peri ) hvntm_peri -lt 0.185 -measure all -abut -lt 90 -single_point -output region |
| } |
| rule "hvntm.SP.2" { |
| caption "hvntm.SP.2: Min spacing between n+_diff outside v5 and thkox and hvntm < 0.185" |
| exte hvntm_peri ndiffOutsideV5 -lt 0.185 -abut -lt 90 -single_point -output region |
| } |
| rule "hvntm.CON.3" { |
| caption "hvntm.CON.3: No overlap between n+_diff outside v5 and thkox and hvntm" |
| and hvntm_peri ndiffOutsideV5 |
| not hvntm_peri thkox |
| } |
| rule "hvntm.SP.3" { |
| caption "hvntm.SP.3: Min spacing between p+_diff and hvntm < 0.185" |
| exte hvntm_peri PDIFF_notENID -lt 0.185 -abut -lt 90 -single_point -output region |
| } |
| rule "hvntm.CON.4" { |
| caption "hvntm.CON.4: No overlap between p+_diff and hvntm" |
| and hvntm_peri PDIFF_notENID |
| } |
| rule "hvntm.SP.4" { |
| caption "hvntm.SP.4: Min spacing between p+_tap and hvntm (except along the diff-butting edge) < 0.185" |
| exte hvntm_peri PTAPnoButtDiff -lt 0.185 -abut -lt 90 -output region |
| } |
| rule "hvntm.CON.5" { |
| caption "hvntm.CON.5: No overlap between p+_tap and hvntm (except along the diff-butting edge)" |
| and hvntm_peri PTAP |
| } |
| rule "hvntm.CON.6" { |
| caption "hvntm.CON.6: No overlap between p+_tap and hvntm along the diff-butting edge" |
| and hvntm_peri diffpTapButtEdge_sz |
| } |
| rule "hvntm.CON.7" { |
| caption "hvntm.CON.7: hvntm not in areaid:CORE must enclose ESD nwell n+ tap inside v5 and thkox" |
| not ( and esd_nwell_tap_inside_v5 thkox ) hvntm_peri |
| } |
| rule "hvntm.CON.8" { |
| caption "hvntm.CON.8: A 5v ESD nwell n+ tap must be enclosed by hvntm when not in areaid:core" |
| not ESD_nwell_tap_inside_v5 hvntm_peri |
| } |
| rule "hvntm.CON.9" { |
| caption "hvntm.CON.9: hvntm must not overlap areaid:core" |
| and hvntm COREID |
| } |
| |
| |
| // |
| // metal blockage checks |
| // |
| |
| |
| |
| rule "met1_block.SP.1" { |
| caption "met1_block.SP.1: Min spacing of met1 to met1_block < 0.14" |
| exte met1 met1_block -lt 0.14 -abut -lt 90 -single_point -output region |
| } |
| rule "met1_block.CON.1" { |
| caption "met1_block.CON.1: met1 must not overlap met1_block" |
| and met1 met1_block |
| } |
| rule "met1_block.SP.2" { |
| caption "met1_block.SP.2: Min spacing of met1_block to met1_routing < 0.145" |
| exte met1_block ( size met1pin -by 0.07 -inside_of met1 -step 0.095 ) -lt 0.145 -abut -lt 90 -single_point -output region |
| } |
| rule "met2_block.SP.1" { |
| caption "met2_block.SP.1: Min spacing of met2 to met2_block < 0.14" |
| exte met2 met2_block -lt 0.14 -abut -lt 90 -single_point -output region |
| } |
| rule "met2_block.CON.1" { |
| caption "met2_block.CON.1: met2 must not overlap met2_block" |
| and met2 met2_block |
| } |
| rule "met2_block.SP.2" { |
| caption "met2_block.SP.2: Min spacing of met2_block to met2_routing < 0.145" |
| exte met2_block ( size met2pin -by 0.07 -inside_of met2 -step 0.095 ) -lt 0.145 -abut -lt 90 -single_point -output region |
| } |
| rule "met3_block.SP.1" { |
| caption "met3_block.SP.1: Min spacing of met3 to met3_block < 0.3" |
| exte met3 met3_block -lt 0.3 -abut -lt 90 -single_point -output region |
| } |
| rule "met3_block.CON.1" { |
| caption "met3_block.CON.1: met3 must not overlap met3_block" |
| and met3 met3_block |
| } |
| rule "met3_block.SP.2" { |
| caption "met3_block.SP.2: Min spacing of met3_block to met3_routing < 0.305" |
| exte met3_block ( size met3pin -by 0.15 -inside_of met3 -step 0.21 ) -lt 0.305 -abut -lt 90 -single_point -output region |
| } |
| rule "met4_block.SP.1" { |
| caption "met4_block.SP.1: Min spacing of met4 to met4_block < 0.3" |
| exte met4 met4_block -lt 0.3 -abut -lt 90 -single_point -output region |
| } |
| rule "met4_block.CON.1" { |
| caption "met4_block.CON.1: met4 must not overlap met4_block" |
| and met4 met4_block |
| } |
| rule "met4_block.SP.2" { |
| caption "met4_block.SP.2: Min spacing of met4_block to met4_routing < 0.305" |
| exte met4_block ( size met4pin -by 0.15 -inside_of met4 -step 0.21 ) -lt 0.305 -abut -lt 90 -single_point -output region |
| } |
| rule "met5_block.SP.1" { |
| caption "met5_block.SP.1: Min spacing of met5 to met5_block < 1.6" |
| exte met5 met5_block -lt 1.6 -abut -lt 90 -single_point -output region |
| } |
| rule "met5_block.CON.1" { |
| caption "met5_block.CON.1: met5 must not overlap met5_block" |
| and met5 met5_block |
| } |
| rule "met5_block.SP.2" { |
| caption "met5_block.SP.2: Min spacing of met5_block to met5_routing < 1.605" |
| exte met5_block ( size met5pin -by 0.8 -inside_of met5 -step 1.13 ) -lt 1.605 -abut -lt 90 -single_point -output region |
| } |
| rule "li_block.SP.1" { |
| caption "li_block.SP.1: Min spacing of li to li_block < 0.17" |
| exte li li_block -lt 0.17 -abut -lt 90 -single_point -output region |
| } |
| rule "li_block.CON.1" { |
| caption "li_block.CON.1: li must not overlap li_block" |
| and li li_block |
| } |
| rule "li_block.SP.2" { |
| caption "li_block.SP.2: Min spacing of li_block to li_routing < 0.17" |
| exte li_block ( size lipin -by 0.085 -inside_of li -step 0.12 ) -lt 0.17 -abut -lt 90 -single_point -output region |
| } |
| or ( select -donut SEALID ) ( holes SEALID ) -outputlayer SEALnoHoles_ORIGIN |
| and prBndry SEALnoHoles_ORIGIN -outputlayer pr_chip_check_REQUIRED |
| not prBndry SEALnoHoles_ORIGIN -outputlayer pr_ip_check_REQUIRED |
| rule "prBndry.CON.1" { |
| caption "prBndry.CON.1: prBoundary.boundary not allowed in IP layout" |
| copy pr_ip_check_REQUIRED |
| } |
| // |
| // PAD rules |
| // |
| holes SEALID -outputlayer sealid_hole |
| angle SEALID -eq 0 -outputlayer dieEdgeHoriz |
| angle SEALID -eq 90 -outputlayer dieEdgePerp |
| edge_expand dieEdgeHoriz -outside_by 0.005 -outputlayer dieEdgeHorizSz |
| edge_expand dieEdgePerp -outside_by 0.005 -outputlayer dieEdgePerpSz |
| edge_boolean -coincident_only dieEdgeHorizSz sealid_hole -outputlayer dieEdgeH |
| edge_boolean -coincident_only dieEdgePerpSz sealid_hole -outputlayer dieEdgeP |
| copy 4006 -outputlayer hoizXaxis |
| copy 4007 -outputlayer perpXaxis |
| not pad SEALID -outputlayer padNoSEAL |
| edge_expand dieEdgeH -inside_by 41 -outputlayer dieEdgStepH41 |
| not ( select -interact padNoSEAL ( and padNoSEAL dieEdgStepH41 ) ) perpXaxis -outputlayer dieEdgStepHpad41 |
| or hoizXaxis dieEdgStepHpad41 -outputlayer allHorizX41 |
| edge_expand dieEdgeP -inside_by 41 -outputlayer dieEdgStepP41 |
| not ( select -interact padNoSEAL ( and padNoSEAL dieEdgStepP41 ) ) dieEdgStepHpad41 -outputlayer dieEdgStepPpad41 |
| or perpXaxis dieEdgStepPpad41 -outputlayer allPerpX41 |
| not padNoSEAL ( or dieEdgStepHpad41 dieEdgStepPpad41 ) -outputlayer newSetPad41 |
| and ( select -interact padNoSEAL ( and padNoSEAL dieEdgStepH41 ) ) ( select -interact padNoSEAL ( and padNoSEAL dieEdgStepP41 ) ) -outputlayer cornerPads41 |
| and dieEdgStepH41 cornerPads41 -outputlayer horzAndCornPad |
| and dieEdgStepP41 cornerPads41 -outputlayer vertAndCornPad |
| exte padCenter horzAndCornPad -lt 60.0 -abut -lt 90 -para -metric opposite -outputlayer padEdgeHorzErr |
| exte padCenter vertAndCornPad -lt 60.0 -abut -lt 90 -para -metric opposite -outputlayer padEdgeVertErr |
| angle ( and cornerPads41 pad_length ) -eq 0 -outputlayer pad_length_ang_0 |
| angle ( and cornerPads41 pad_length ) -eq 90 -outputlayer pad_length_ang_90 |
| select -enclose cornerPads41 ( edge_expand pad_length_ang_90 -outside_by 0.2 ) -outputlayer dfmVertXedge |
| select -enclose cornerPads41 ( edge_expand pad_length_ang_0 -outside_by 0.2 ) -outputlayer dfmHorzXedge |
| edge_expand dieEdgeH -inside_by 82 -outputlayer dieEdgStepH82 |
| not ( select -interact padNoSEAL ( and padNoSEAL dieEdgStepH82 ) ) allPerpX41 -outputlayer dieEdgStepHpad82 |
| or allHorizX41 dieEdgStepHpad82 -outputlayer allHorizX82 |
| edge_expand dieEdgeP -inside_by 82 -outputlayer dieEdgStepP82 |
| not ( select -interact padNoSEAL ( and padNoSEAL dieEdgStepP82 ) ) dieEdgStepHpad82 -outputlayer dieEdgStepPpad82 |
| or allPerpX41 dieEdgStepPpad82 -outputlayer allPerpX82 |
| not padNoSEAL ( or dieEdgStepHpad82 dieEdgStepPpad82 ) -outputlayer newSetPad82 |
| edge_expand dieEdgeH -inside_by 123 -outputlayer dieEdgStepH123 |
| not ( select -interact padNoSEAL ( and padNoSEAL dieEdgStepH123 ) ) allPerpX82 -outputlayer dieEdgStepHpad123 |
| or allHorizX82 dieEdgStepHpad123 -outputlayer allHorizX123 |
| edge_expand dieEdgeP -inside_by 123 -outputlayer dieEdgStepP123 |
| not ( select -interact padNoSEAL ( and padNoSEAL dieEdgStepP123 ) ) dieEdgStepHpad123 -outputlayer dieEdgStepPpad123 |
| or allPerpX82 dieEdgStepPpad123 -outputlayer allPerpX123 |
| not padNoSEAL ( or dieEdgStepHpad123 dieEdgStepPpad123 ) -outputlayer newSetPad123 |
| edge_expand dieEdgeH -inside_by 164 -outputlayer dieEdgStepH164 |
| not ( select -interact padNoSEAL ( and padNoSEAL dieEdgStepH164 ) ) allPerpX123 -outputlayer dieEdgStepHpad164 |
| or allHorizX123 dieEdgStepHpad164 -outputlayer allHorizX164 |
| edge_expand dieEdgeP -inside_by 164 -outputlayer dieEdgStepP164 |
| not ( select -interact padNoSEAL ( and padNoSEAL dieEdgStepP164 ) ) dieEdgStepHpad164 -outputlayer dieEdgStepPpad164 |
| or allPerpX123 dieEdgStepPpad164 -outputlayer allPerpX164 |
| not padNoSEAL ( or dieEdgStepHpad164 dieEdgStepPpad164 ) -outputlayer newSetPad164 |
| edge_expand dieEdgeH -inside_by 205 -outputlayer dieEdgStepH205 |
| not ( select -interact padNoSEAL ( and padNoSEAL dieEdgStepH205 ) ) allPerpX164 -outputlayer dieEdgStepHpad205 |
| or allHorizX164 dieEdgStepHpad205 -outputlayer allHorizX205 |
| edge_expand dieEdgeP -inside_by 205 -outputlayer dieEdgStepP205 |
| not ( select -interact padNoSEAL ( and padNoSEAL dieEdgStepP205 ) ) dieEdgStepHpad205 -outputlayer dieEdgStepPpad205 |
| or allPerpX164 dieEdgStepPpad205 -outputlayer allPerpX205 |
| not padNoSEAL ( or dieEdgStepHpad205 dieEdgStepPpad205 ) -outputlayer newSetPad205 |
| edge_expand dieEdgeH -inside_by 246 -outputlayer dieEdgStepH246 |
| not ( select -interact padNoSEAL ( and padNoSEAL dieEdgStepH246 ) ) allPerpX205 -outputlayer dieEdgStepHpad246 |
| or allHorizX205 dieEdgStepHpad246 -outputlayer allHorizX246 |
| edge_expand dieEdgeP -inside_by 246 -outputlayer dieEdgStepP246 |
| not ( select -interact padNoSEAL ( and padNoSEAL dieEdgStepP246 ) ) dieEdgStepHpad246 -outputlayer dieEdgStepPpad246 |
| or allPerpX205 dieEdgStepPpad246 -outputlayer allPerpX246 |
| not padNoSEAL ( or dieEdgStepHpad246 dieEdgStepPpad246 ) -outputlayer newSetPad246 |
| edge_expand dieEdgeH -inside_by 287 -outputlayer dieEdgStepH287 |
| not ( select -interact padNoSEAL ( and padNoSEAL dieEdgStepH287 ) ) allPerpX246 -outputlayer dieEdgStepHpad287 |
| or allHorizX246 dieEdgStepHpad287 -outputlayer allHorizX287 |
| edge_expand dieEdgeP -inside_by 287 -outputlayer dieEdgStepP287 |
| not ( select -interact padNoSEAL ( and padNoSEAL dieEdgStepP287 ) ) dieEdgStepHpad287 -outputlayer dieEdgStepPpad287 |
| or allPerpX246 dieEdgStepPpad287 -outputlayer allPerpX287 |
| not padNoSEAL ( or dieEdgStepHpad287 dieEdgStepPpad287 ) -outputlayer newSetPad287 |
| edge_expand dieEdgeH -inside_by 328 -outputlayer dieEdgStepH328 |
| not ( select -interact padNoSEAL ( and padNoSEAL dieEdgStepH328 ) ) allPerpX287 -outputlayer dieEdgStepHpad328 |
| or allHorizX287 dieEdgStepHpad328 -outputlayer allHorizX328 |
| edge_expand dieEdgeP -inside_by 328 -outputlayer dieEdgStepP328 |
| not ( select -interact padNoSEAL ( and padNoSEAL dieEdgStepP328 ) ) dieEdgStepHpad328 -outputlayer dieEdgStepPpad328 |
| or allPerpX287 dieEdgStepPpad328 -outputlayer allPerpX328 |
| not padNoSEAL ( or dieEdgStepHpad328 dieEdgStepPpad328 ) -outputlayer newSetPad328 |
| edge_expand dieEdgeH -inside_by 369 -outputlayer dieEdgStepH369 |
| not ( select -interact padNoSEAL ( and padNoSEAL dieEdgStepH369 ) ) allPerpX328 -outputlayer dieEdgStepHpad369 |
| or allHorizX328 dieEdgStepHpad369 -outputlayer allHorizX369 |
| edge_expand dieEdgeP -inside_by 369 -outputlayer dieEdgStepP369 |
| not ( select -interact padNoSEAL ( and padNoSEAL dieEdgStepP369 ) ) dieEdgStepHpad369 -outputlayer dieEdgStepPpad369 |
| or allPerpX328 dieEdgStepPpad369 -outputlayer allPerpX369 |
| not padNoSEAL ( or dieEdgStepHpad369 dieEdgStepPpad369 ) -outputlayer newSetPad369 |
| edge_expand dieEdgeH -inside_by 410 -outputlayer dieEdgStepH410 |
| not ( select -interact padNoSEAL ( and padNoSEAL dieEdgStepH410 ) ) allPerpX369 -outputlayer dieEdgStepHpad410 |
| or allHorizX369 dieEdgStepHpad410 -outputlayer allHorizX410 |
| edge_expand dieEdgeP -inside_by 410 -outputlayer dieEdgStepP410 |
| not ( select -interact padNoSEAL ( and padNoSEAL dieEdgStepP410 ) ) dieEdgStepHpad410 -outputlayer dieEdgStepPpad410 |
| or allPerpX369 dieEdgStepPpad410 -outputlayer allPerpX410 |
| not padNoSEAL ( or dieEdgStepHpad410 dieEdgStepPpad410 ) -outputlayer newSetPad410 |
| edge_expand dieEdgeH -inside_by 451 -outputlayer dieEdgStepH451 |
| not ( select -interact padNoSEAL ( and padNoSEAL dieEdgStepH451 ) ) allPerpX410 -outputlayer dieEdgStepHpad451 |
| or allHorizX410 dieEdgStepHpad451 -outputlayer allHorizX451 |
| edge_expand dieEdgeP -inside_by 451 -outputlayer dieEdgStepP451 |
| not ( select -interact padNoSEAL ( and padNoSEAL dieEdgStepP451 ) ) dieEdgStepHpad451 -outputlayer dieEdgStepPpad451 |
| or allPerpX410 dieEdgStepPpad451 -outputlayer allPerpX451 |
| not padNoSEAL ( or dieEdgStepHpad451 dieEdgStepPpad451 ) -outputlayer newSetPad451 |
| edge_expand dieEdgeH -inside_by 492 -outputlayer dieEdgStepH492 |
| not ( select -interact padNoSEAL ( and padNoSEAL dieEdgStepH492 ) ) allPerpX451 -outputlayer dieEdgStepHpad492 |
| or allHorizX451 dieEdgStepHpad492 -outputlayer allHorizX492 |
| edge_expand dieEdgeP -inside_by 492 -outputlayer dieEdgStepP492 |
| not ( select -interact padNoSEAL ( and padNoSEAL dieEdgStepP492 ) ) dieEdgStepHpad492 -outputlayer dieEdgStepPpad492 |
| or allPerpX451 dieEdgStepPpad492 -outputlayer allPerpX492 |
| not padNoSEAL ( or dieEdgStepHpad492 dieEdgStepPpad492 ) -outputlayer newSetPad492 |
| edge_expand dieEdgeH -inside_by 533 -outputlayer dieEdgStepH533 |
| not ( select -interact padNoSEAL ( and padNoSEAL dieEdgStepH533 ) ) allPerpX492 -outputlayer dieEdgStepHpad533 |
| or allHorizX492 dieEdgStepHpad533 -outputlayer allHorizX533 |
| edge_expand dieEdgeP -inside_by 533 -outputlayer dieEdgStepP533 |
| not ( select -interact padNoSEAL ( and padNoSEAL dieEdgStepP533 ) ) dieEdgStepHpad533 -outputlayer dieEdgStepPpad533 |
| or allPerpX492 dieEdgStepPpad533 -outputlayer allPerpX533 |
| not padNoSEAL ( or dieEdgStepHpad533 dieEdgStepPpad533 ) -outputlayer newSetPad533 |
| copy allHorizX533 -outputlayer padXorg |
| copy allPerpX533 -outputlayer padYorg |
| copy dfmHorzXedge -outputlayer padCornerXtmp |
| copy dfmVertXedge -outputlayer padCornerYtmp |
| edge_expand ( angle padCornerXtmp -eq 90 ) -outside_by 7 -outputlayer padCornXpitchPadX |
| edge_expand ( angle padCornerXtmp -eq 0 ) -outside_by 7 -outputlayer padCornXpitchPadY |
| select -touch padCornXpitchPadY pad -eq 2 -outputlayer padCornXtouchPitchInY |
| select -touch padCornXpitchPadX pad -eq 2 -outputlayer padCornXtouchPitchInX |
| select -touch -not ( select -touch padCornerXtmp padCornXtouchPitchInY ) padCornXtouchPitchInX -outputlayer padCornerSwapxtoY |
| not ( or padCornerXtmp padCornerSwapYtoX ) padCornerSwapXtoY -outputlayer padCornerX |
| edge_expand ( angle padCornerYtmp -eq 90 ) -outside_by 7 -outputlayer padCornYpitchPadY |
| edge_expand ( angle padCornerYtmp -eq 0 ) -outside_by 7 -outputlayer padCornYpitchPadX |
| select -touch padCornYpitchPadY pad -eq 2 -outputlayer padCornYtouchPitchInY |
| select -touch padCornYpitchPadX pad -eq 2 -outputlayer padCornYtouchPitchInX |
| select -touch -not ( select -touch padCornerYtmp padCornYtouchPitchInY ) padCornYtouchPitchInX -outputlayer padCornerSwapYtoX |
| not ( or padCornerYtmp padCornerSwapXtoY ) padCornerSwapYtoX -outputlayer padCornerY |
| not ( or padXorg padCornerX ) padCornerY -outputlayer padX |
| not ( or padYorg padCornerY ) padCornerX -outputlayer padY |
| edge_expand ( angle padY -eq 0 ) -inside_by 0.005 -outputlayer minSpacepadYedges |
| edge_expand ( angle padY -eq 90 ) -inside_by 0.005 -outputlayer minSpacepadYyEdge |
| edge_expand ( angle padX -eq 90 ) -inside_by 0.005 -outputlayer minSpacepadXedges |
| edge_expand ( angle padX -eq 0 ) -inside_by 0.005 -outputlayer minSpacepadXyEdge |
| extent_cell "lazX_*" "lazY_*" -original -outputlayer laser_targetCells |
| select -outside pad ( or SEALID fuse FRAMEID laser_targetCells ) -outputlayer BONDPAD |
| and pad inductor -outputlayer padInInd |
| or ( extent_cell "padPL*" -original ) bondpadCuPillar -outputlayer bondpadPcell_0 |
| extent_cell "pad_bond*" -original -outputlayer bondpadPcell_1 |
| extent_cell "pad_microprobe*" -original -outputlayer bondpadPcell_2 |
| extent_cell "pad_probe*" -original -outputlayer bondpadPcell_3 |
| or bondpadPcell_0 bondpadPcell_1 bondpadPcell_2 bondpadPcell_3 -outputlayer bondpadPcell |
| select -label bondpadPcell -textname "plastic" -textlayer textdraw -outputlayer plasticPackPad |
| select -label bondpadPcell -textname "hermetic" -textlayer textdraw -outputlayer hermeticPackPad |
| select -label BONDPAD -textname "HP" -textlayer textdraw -outputlayer PadPLhp |
| select -label BONDPAD -textname "FP" -textlayer textdraw -outputlayer PadPLfp |
| select -label BONDPAD -textname "STG" -textlayer textdraw -outputlayer PadPLstg |
| select -label BONDPAD -textname "WLBI" -textlayer textdraw -outputlayer PadPLwlbi |
| extent_cell "s8fpafeg1_io_amkor_pad*" "fpg1_amkor_39x39_pad*" -original -outputlayer bondpadCuPillar |
| not BONDPAD ( or padInInd ( or bondpadPcell bondpadCuPillar ) ) -outputlayer notValidbondPad |
| not bondpadPcell plasticPackPad -outputlayer bondpadPcellNoText |
| and pad plasticPackPad -outputlayer anyPadPlastic |
| rule "pad.CON.1" { |
| caption "pad.CON.1: pad pcells should be used for bondpad" |
| copy notValidbondPad |
| } |
| rule "pad.CON.3" { |
| caption "pad.CON.3: Hermetic package pads are not supported in this flow" |
| copy hermeticPackPad |
| } |
| and BONDPAD bondpadPcell -outputlayer bondpadNormal |
| and BONDPAD plasticPackPad -outputlayer bondpadNormalPlastic |
| and BONDPAD PadPLhp -outputlayer bondpadHP |
| and BONDPAD PadPLfp -outputlayer bondpadFP |
| and BONDPAD PadPLstg -outputlayer bondpadSTG |
| and BONDPAD PadPLwlbi -outputlayer bondpadWLBI |
| and pad ( select -interact ( select -enclose met5 pad ) met4 ) -outputlayer pad_in_bond |
| select -label pad -textname "e-test" -outputlayer probe_pad |
| select -label pad -textname "u-test" -outputlayer uprobe_pad |
| rule "pad.ENC.1" { |
| caption "pad.ENC.1: Min. enclosure of normal bond pad by met5 < 0.27" |
| enc ( not pad_in_bond ( or probe_pad uprobe_pad ) ) met5 -lt 2.7 -measure all -abut -lt 90 -single_point -output region |
| } |
| select -donut ( select -interact met4 pad_in_bond ) -outputlayer met4_ring |
| rule "pad.SP.1" { |
| caption "pad.SP.1: Metal4 ring in bond pad must be coincident and outside pad layer of pad cell" |
| select -interact met4_ring ( and met4_ring pad_in_bond ) |
| } |
| edge_boolean -coincident_only BONDPAD ( or minSpacepadXedges minSpacepadYedges ) -outputlayer bondpadEdges |
| edge_expand bondpadEdges -inside_by 30 -outputlayer bondpadEdgesSz |
| edge_expand ( edge_length ( edge_boolean -inside bondpadEdgesSz BONDPAD ) -legt "(60.0 / 2.0)" 60.0 ) -inside_by 0.005 -outputlayer bondpadEdgesSide |
| select -interact BONDPAD bondpadEdgesSide -outputlayer SmallBondPad |
| not BONDPAD SmallBondPad -outputlayer LargeBondPad |
| or ( select -interact BONDPAD ( and BONDPAD ( and padCenter padCenterDieY ) ) ) padCenterDieY -outputlayer padGroupingY |
| and ( select -interact padGroupingY ( and padGroupingY ( and padCenter SmallBondPad ) ) ) BONDPAD -outputlayer smallGroupingY |
| and ( not padGroupingY smallGroupingY ) BONDPAD -outputlayer largeGroupingY |
| or ( select -interact BONDPAD ( and BONDPAD ( and padCenter padCenterDieX ) ) ) padCenterDieX -outputlayer padGroupingX |
| and ( select -interact padGroupingX ( and padGroupingX ( and padCenter SmallBondPad ) ) ) BONDPAD -outputlayer smallGroupingX |
| and ( not padGroupingX smallGroupingX ) BONDPAD -outputlayer largeGroupingX |
| select -outside met4 bondPadPcell -outputlayer met4OutsidePad |
| select -outside met5 bondPadPcell -outputlayer met5OutsidePad |
| rule "pad.SP.2" { |
| caption "pad.SP.2: Min. spacing of pad opening inside a group of small bondpads in the Y direction to met4/5 outside the bond pad < 5.0" |
| caption "if at least one pad opening across the chip in x-direction is <= 60um" |
| exte smallGroupingY met5OutsidePad -lt 5.0 -abut -lt 90 -single_point -output region |
| exte smallGroupingY met4OutsidePad -lt 5.0 -abut -lt 90 -single_point -output region |
| } |
| rule "pad.SP.3" { |
| caption "pad.SP.3: Min. spacing of pad opening of inside a group of large bondpads in the Y direction met4/5 outside the bond pad < 10.0" |
| caption "if at least one pad opening across the chip in x-direction is > 60um" |
| exte largeGroupingY met5OutsidePad -lt 10.0 -abut -lt 90 -single_point -output region |
| exte largeGroupingY met4OutsidePad -lt 10.0 -abut -lt 90 -single_point -output region |
| } |
| rule "pad.SP.4" { |
| caption "pad.SP.4: Min. spacing of pad opening of small bondpads in the X direction to met4/5 outside the bond pad < 5.0" |
| caption "if at least one pad opening across the chip in x-direction is <= 60um" |
| exte smallGroupingX met5OutsidePad -lt 5.0 -abut -lt 90 -single_point -output region |
| exte smallGroupingX met4OutsidePad -lt 5.0 -abut -lt 90 -single_point -output region |
| } |
| rule "pad.SP.5" { |
| caption "pad.SP.5: Min. spacing of pad opening inside a group of large bondpads in the X direction to met4/5 outside the bond pad < 10.0" |
| caption "if at least one pad opening across the chip in x-direction is > 60um" |
| exte largeGroupingX met5OutsidePad -lt 10.0 -abut -lt 90 -single_point -output region |
| exte largeGroupingX met4OutsidePad -lt 10.0 -abut -lt 90 -single_point -output region |
| } |
| select -label bondpadNormalPlastic -textname "probe-only" -textlayer textdraw -outputlayer bondpadNormalprobe |
| not bondpadNormalPlastic ( or cuPillarPadText bondpadNormalprobe ) -outputlayer bondpadNormalNoprobe |
| rule "pad.OVL.1" { |
| caption "pad.OVL.1: Normal pad opening (not probe) must not overlap met4" |
| and bondpadNormalNoprobe met4 |
| } |
| edge_expand ( select -interact -not pad ( or uprobe_pad probe_pad ) ) -outside_by 0.05 -outputlayer bp_outl1 |
| edge_boolean -coincident_only -outside ( select -interact -not pad ( or uprobe_pad probe_pad ) ) bp_outl1 -outputlayer bp_outl |
| angle bp_outl -eq 45 -outputlayer bondpad_45_edges |
| angle -not bp_outl -eq 45 -outputlayer bondpad_90_edges |
| inte pad_squared_off -lt 10 -abut -eq 90 -output region -outputlayer bondpad_corner |
| rule "pad.CON.4" { |
| caption "pad.CON.4: Bondpad should not have 90 degree corner" |
| size ( inte bondpadNormalPlastic -lt 0.005 -abut -eq 90 -intersecting -output region ) -by 0.5 -inside_of pad |
| } |
| rule "pad.CON.5" { |
| caption "pad.CON.5: Bondpad missing 45 degree corner" |
| select -interact -not bondpad_corner ( edge_expand bondpad_45_edges -outside_by 0.05 ) |
| } |
| rule "pad.CON.6" { |
| caption "pad.CON.6: Bondpad does not have 4 chamferred 45 degree corners" |
| select -touch -not ( not pad ( or uprobe_pad probe_pad ) ) ( edge_expand bondpad_45_edges -outside_by 0.05 ) -eq 4 |
| } |
| rule "pad.CON.7" { |
| caption "pad.CON.7: Bondpad should have only 4 orthogonal edges" |
| select -touch -not ( not pad ( or uprobe_pad probe_pad ) ) ( edge_expand bondpad_90_edges -outside_by 0.05 ) -eq 4 |
| } |
| rule "pad.LEN.1" { |
| caption "pad.LEN.1: Min length of 45 degree bevel on Bond pad < 7.0" |
| edge_length bondpad_45_edges -lt 7 |
| } |
| rule "pad.LEN.2" { |
| caption "pad.LEN.2: Max length of 45 degree bevel on Bond pad > 8.8" |
| edge_length bondpad_45_edges -gt 8.8 |
| } |
| or ( holes SEALID ) ( select -donut SEALID ) -outputlayer solid_seal |
| size solid_seal -by -500.0 -outputlayer solid_seal_shrink |
| select -with_edge bondpadNormalPlastic ( edge_boolean -coincident_only -inside bondpadNormalPlastic solid_seal_shrink ) -outputlayer maxSpcPadSeal |
| select -cut bondpadNormalPlastic solid_seal_shrink -outputlayer lessMaxSpcPadSeal |
| select -interact pad ( select -label pad -textname "CU-PILLAR-PAD" -textlayer textdraw ) -outputlayer cuPillarPadText |
| select -interact bondpadCuPillar ( select -label pad -textname "AUP-DUMMY-OK" -textlayer textdraw ) -outputlayer aupDummyPadText |
| copy cuPillarPadText -outputlayer cadXmpt |
| and ( not bondpadNormalPlastic ( or maxSpcPadSeal ( or lessMaxSpcPadSeal cadXmpt ) ) ) solid_seal_shrink -outputlayer err_pad_15 |
| rule "pad.ENC.2" { |
| caption "pad.ENC.2: Min. enclosure of any plastic pad by solid_seal < 16.99" |
| and anyPadPlastic solid_seal -outputlayer q0anyPadPlasticand |
| enc q0anyPadPlasticand solid_seal -lt 16.99 -measure all -abut -lt 90 -single_point -output region |
| } |
| rule "pad.SP.10" { |
| caption "pad.SP.10: Max spacing between bondpad opening and edge of scribe line (outer end of seal ring) > 500.0" |
| copy err_pad_15 |
| } |
| and pad ( and bondPadPcell met5 ) -outputlayer padMetal |
| copy 4008 -outputlayer met1Shield |
| select -interact met1i ( and met1i padMetal ) -outputlayer met1UndPadMet |
| and met1UndPadMet ( not BONDPAD aupDummyPadText ) -outputlayer met1UndPadMetOnly |
| inte met1UndPadMetOnly -lt 0.14 -para -metric opposite -output region -outputlayer met1UndPadMetMinW |
| rule "pad.SP.11" { |
| caption "pad.SP.11: Min. spacing/notch of met1 under pad metal < 1.5" |
| exte met1UndPadMetOnly -lt 1.5 -abut -lt 90 -single_point -output region -metric opposite |
| } |
| rule "pad.WID.1" { |
| caption "pad.WID.1: Min width of met1 under pad metal < 0.14" |
| copy met1UndPadMetMinW |
| } |
| select -interact met2 ( and met2 padMetal ) -outputlayer met2UndPadMet |
| and met2UndPadMet ( not BONDPAD aupDummyPadText ) -outputlayer met2UndPadMetOnly |
| inte met2UndPadMetOnly -lt 0.14 -para -metric opposite -output region -outputlayer met2UndPadMetMinW |
| rule "pad.SP.12" { |
| caption "pad.SP.12: Min. spacing/notch of met2 under pad metal < 1.5" |
| exte met2UndPadMetOnly -lt 1.5 -abut -lt 90 -single_point -output region -metric opposite |
| } |
| rule "pad.WID.2" { |
| caption "pad.WID.2: Min width of met2 under pad metal < 0.14" |
| copy met2UndPadMetMinW |
| } |
| select -interact met3 ( and met3 padMetal ) -outputlayer met3UndPadMet |
| and met3UndPadMet ( not BONDPAD aupDummyPadText ) -outputlayer met3UndPadMetOnly |
| inte met3UndPadMetOnly -lt 0.3 -para -metric opposite -output region -outputlayer met3UndPadMetMinW |
| rule "pad.SP.13" { |
| caption "pad.SP.13: Min. spacing/notch of met3 under pad metal < 1.5" |
| exte met3UndPadMetOnly -lt 1.5 -abut -lt 90 -single_point -output region -metric opposite |
| } |
| rule "pad.WID.3" { |
| caption "pad.WID.3: Min width of met3 under pad metal < 0.3" |
| copy met3UndPadMetMinW |
| } |
| rule "pad.WID.4" { |
| caption "pad.WID.4: Max width of met1 under pad metal > 25.0" |
| with_width ( not ( and met1 padMetal ) met1Shield ) -gt 25.0 |
| } |
| rule "pad.WID.5" { |
| caption "pad.WID.5: Max width of met2 under pad metal > 25.0" |
| with_width ( not ( and met2 padMetal ) met1Shield ) -gt 25.0 |
| } |
| rule "pad.SP.6" { |
| caption "pad.SP.6: Min pad spacing < 1.27" |
| exte pad -lt 1.27 -abut -lt 90 -output region |
| } |
| extent_cell "hpb_esdTriggerULB_b*" -original -outputlayer hpb_exemptions |
| extent_cell "s8tnvsio18_io_top" "s8tnviso18_io_top_hv" "quadspinvsram_top*" -original -outputlayer qspi_exemptions |
| or hpb_exemptions qspi_exemptions -outputlayer pad_19_exemptions |
| rule "pad.WID.6" { |
| caption "pad.WID.6: Max width of met3 under pad metal > 6.0" |
| not ( with_width ( and met3 padMetal ) -gt 6.0 ) pad_19_exemptions |
| } |
| edge_boolean -coincident_only bondpadFP ( or minSpacepadXedges minSpacepadYedges ) -outputlayer padFPedgX |
| edge_expand padFPedgX -inside_by 30 -outputlayer padFPedgXsz |
| edge_length ( edge_boolean -coincident_only -not padFPedgXsz padFPedgX ) -ltgt 30.0 60.0 -outputlayer badFPwEdg |
| edge_expand badFPwEdg -inside_by 0.005 -outputlayer badFPwEdgSz |
| select -interact ( not bondpadFP bondpadCuPillar ) ( and ( not bondpadFP bondpadCuPillar ) ( select -interact ( edge_expand padFPedgX -inside_by 0.005 ) ( and ( edge_expand padFPedgX -inside_by 0.005 ) badFPwEdgSz ) -eq 2 ) ) -outputlayer badFPwidth |
| edge_boolean -coincident_only bondpadFP ( or minSpacepadXyEdge minSpacepadYyedge ) -outputlayer padFPedgY |
| edge_expand padFPedgY -inside_by 30 -outputlayer padFPedgYsz |
| edge_length ( edge_boolean -coincident_only -not padFPedgYsz padFPedgY ) -ltgt 30.0 60.0 -outputlayer badFPlEdg |
| edge_expand badFPlEdg -inside_by 0.005 -outputlayer badFPlEdgSz |
| select -interact ( not bondpadFP bondpadCuPillar ) ( and ( not bondpadFP bondpadCuPillar ) ( select -interact ( edge_expand padFPedgY -inside_by 0.005 ) ( and ( edge_expand padFPedgY -inside_by 0.005 ) badFPlEdgSz ) -eq 2 ) ) -outputlayer badFPlength |
| edge_boolean -coincident_only bondpadSTG ( or minSpacepadXedges minSpacepadYedges ) -outputlayer padSTGedgX |
| edge_expand padSTGedgX -inside_by 30 -outputlayer padSTGedgXsz |
| edge_length ( edge_boolean -coincident_only -not padSTGedgXsz padSTGedgX ) -ltgt 30.0 60.0 -outputlayer badSTGwEdg |
| edge_expand badSTGwEdg -inside_by 0.005 -outputlayer badSTGwEdgSz |
| select -interact bondpadSTG ( and bondpadSTG ( select -interact ( edge_expand padSTGedgX -inside_by 0.005 ) ( and ( edge_expand padSTGedgX -inside_by 0.005 ) badSTGwEdgSz ) -eq 2 ) ) -outputlayer badSTGwidth |
| edge_boolean -coincident_only bondpadSTG ( or minSpacepadXyEdge minSpacepadYyedge ) -outputlayer padSTGedgY |
| edge_expand padSTGedgY -inside_by 30 -outputlayer padSTGedgYsz |
| edge_length ( edge_boolean -coincident_only -not padSTGedgYsz padSTGedgY ) -ltgt 30.0 60.0 -outputlayer badSTGlEdg |
| edge_expand badSTGlEdg -inside_by 0.005 -outputlayer badSTGlEdgSz |
| select -interact bondpadSTG ( and bondpadSTG ( select -interact ( edge_expand padSTGedgY -inside_by 0.005 ) ( and ( edge_expand padSTGedgY -inside_by 0.005 ) badSTGlEdgSz ) -eq 2 ) ) -outputlayer badSTGlength |
| extent_cell "psoc4*_top*" -outputlayer psoc4cuCells |
| and bondpadHP psoc4cuCells -outputlayer bondpadHPcu |
| not bondpadHP bondpadHPcu -outputlayer bondpadHPorg |
| edge_boolean -coincident_only bondpadHPorg ( or minSpacepadXedges minSpacepadYedges ) -outputlayer padHPedgX |
| edge_expand padHPedgX -inside_by 30 -outputlayer padHPedgXsz |
| edge_length ( edge_boolean -coincident_only -not padHPedgXsz padHPedgX ) -ltgt 30.0 60.0 -outputlayer badHPwEdg |
| edge_expand badHPwEdg -inside_by 0.005 -outputlayer badHPwEdgSz |
| select -interact bondpadHP ( and bondpadHP ( select -interact ( edge_expand padHPedgX -inside_by 0.005 ) ( and ( edge_expand padHPedgX -inside_by 0.005 ) badHPwEdgSz ) -eq 2 ) ) -outputlayer badHPwidth |
| edge_boolean -coincident_only bondpadHPorg ( or minSpacepadXyEdge minSpacepadYyedge ) -outputlayer padHPedgY |
| edge_expand padHPedgY -inside_by 30 -outputlayer padHPedgYsz |
| edge_length ( edge_boolean -coincident_only -not padHPedgYsz padHPedgY ) -ltgt 30.0 60.0 -outputlayer badHPlEdg |
| edge_expand badHPlEdg -inside_by 0.005 -outputlayer badHPlEdgSz |
| select -interact bondpadHP ( and bondpadHP ( select -interact ( edge_expand padHPedgY -inside_by 0.005 ) ( and ( edge_expand padHPedgY -inside_by 0.005 ) badHPlEdgSz ) -eq 2 ) ) -outputlayer badHPlength |
| edge_boolean -coincident_only bondpadHPcu ( or minSpacepadXedges minSpacepadYedges ) -outputlayer padHPcuedgX |
| edge_expand padHPcuedgX -inside_by 29 -outputlayer padHPcuedgXsz |
| edge_length ( edge_boolean -coincident_only -not padHPcuedgXsz padHPcuedgX ) -ltgt 29.0 58.0 -outputlayer badHPcuwEdg |
| edge_expand badHPcuwEdg -inside_by 0.005 -outputlayer badHPcuwEdgSz |
| select -interact ( not bondpadHPcu bondpadHPcuSolo ) ( and ( not bondpadHPcu bondpadHPcuSolo ) ( select -interact ( edge_expand padHPcuedgX -inside_by 0.005 ) ( and ( edge_expand padHPcuedgX -inside_by 0.005 ) badHPcuwEdgSz ) -eq 2 ) ) -outputlayer badHPcuwidth |
| edge_boolean -coincident_only bondpadHPcu ( or minSpacepadXyEdge minSpacepadYyedge ) -outputlayer padHPcuedgY |
| edge_expand padHPcuedgY -inside_by 30 -outputlayer padHPcuedgYsz |
| edge_length ( edge_boolean -coincident_only -not padHPcuedgYsz padHPcuedgY ) -ltgt 30.0 60.0 -outputlayer badHPculEdg |
| edge_expand badHPculEdg -inside_by 0.005 -outputlayer badHPculEdgSz |
| select -interact ( not bondpadHPcu bondpadHPcuSolo ) ( and ( not bondpadHPcu bondpadHPcuSolo ) ( select -interact ( edge_expand padHPcuedgY -inside_by 0.005 ) ( and ( edge_expand padHPcuedgY -inside_by 0.005 ) badHPculEdgSz ) -eq 2 ) ) -outputlayer badHPculength |
| size bondPadHPcu -by "(50.0 / 2)" -outputlayer bondpadHPcuSz |
| and bondpadHPcu ( select -interact bondpadHPcuSz bondpadHPcu -eq 1 ) -outputlayer bondpadHPcuSolo |
| size bondPadHPcuSolo -by 10 -underover -outputlayer bondpadHPcuSoloSz |
| rect_chk -not bondpadHPcuSoloSz -ge 58.0 -by -ge 60.0 -outputlayer badHPcuSoloWL |
| edge_boolean -coincident_only bondpadWLBI ( or minSpacepadXedges minSpacepadYedges ) -outputlayer padWLBIedgX |
| edge_expand padWLBIedgX -inside_by 25 -outputlayer padWLBIedgXsz |
| edge_length ( edge_boolean -coincident_only -not padWLBIedgXsz padWLBIedgX ) -ltgt 25.0 50.0 -outputlayer badWLBIwEdg |
| edge_expand badWLBIwEdg -inside_by 0.005 -outputlayer badWLBIwEdgSz |
| select -interact bondpadWLBI ( and bondpadWLBI ( select -interact ( edge_expand padWLBIedgX -inside_by 0.005 ) ( and ( edge_expand padWLBIedgX -inside_by 0.005 ) badWLBIwEdgSz ) -eq 2 ) ) -outputlayer badWLBIwidth |
| edge_boolean -coincident_only bondpadWLBI ( or minSpacepadXyEdge minSpacepadYyedge ) -outputlayer padWLBIedgY |
| edge_expand padWLBIedgY -inside_by 30 -outputlayer padWLBIedgYsz |
| edge_length ( edge_boolean -coincident_only -not padWLBIedgYsz padWLBIedgY ) -ltgt 30.0 60.0 -outputlayer badWLBIlEdg |
| edge_expand badWLBIlEdg -inside_by 0.005 -outputlayer badWLBIlEdgSz |
| select -interact bondpadWLBI ( and bondpadWLBI ( select -interact ( edge_expand padWLBIedgY -inside_by 0.005 ) ( and ( edge_expand padWLBIedgY -inside_by 0.005 ) badWLBIlEdgSz ) -eq 2 ) ) -outputlayer badWLBIlength |
| size ( select -interact -not BONDPAD ( or uprobe_pad probe_pad ) ) -by 10 -underover -outputlayer pad_squared_off |
| inte pad_squared_off -lt 150 -abut -lt 90 -metric opposite -para -output region_centerline 1 -outputlayer pad_ctr_cross |
| not pad_ctr_cross ( inte pad_ctr_cross -lt 1.005 -abut -lt 90 -metric opposite -para -output region ) -outputlayer pad_ctr_box |
| bbox pad -centers 0.2 -outputlayer padCenter |
| not pad_ctr_cross pad_ctr_box -outputlayer pad_cross_not_ctr |
| or ( select -interact pad_cross_not_ctr pad_length ) pad_ctr_box -outputlayer pad_cross_len |
| or ( select -interact -not pad_cross_not_ctr pad_length ) pad_ctr_box -outputlayer pad_cross_wid |
| angle ( edge_length pad_cross_len -gt 2 ) -eq 0 -outputlayer pad_cross_len_x |
| angle ( edge_length pad_cross_len -gt 2 ) -eq 90 -outputlayer pad_cross_len_y |
| angle ( edge_length pad_cross_wid -gt 2 ) -eq 0 -outputlayer pad_cross_wid_x |
| angle ( edge_length pad_cross_wid -gt 2 ) -eq 90 -outputlayer pad_cross_wid_y |
| rule "pad.WID.7" { |
| caption "pad.WID.7: Min width of fine pitch pad in x direction < 60.0" |
| edge_length ( edge_boolean -inside pad_cross_len_x bondpadFP ) -lt 60 |
| } |
| rule "pad.LEN.3" { |
| caption "pad.LEN.3: Min length of fine pitch pad in y direction < 60.0" |
| edge_length ( edge_boolean -inside pad_cross_len_y bondpadFP ) -lt 60 |
| } |
| rule "pad.WID.8" { |
| caption "pad.WID.8: Min width of staggered pad in x direction < 60.0" |
| edge_length ( edge_boolean -inside pad_cross_len_x bondpadSTG ) -lt 60 |
| } |
| rule "pad.LEN.4" { |
| caption "pad.LEN.4: Min length of staggered pad in y direction < 60.0" |
| edge_length ( edge_boolean -inside pad_cross_len_y bondpadSTG ) -lt 60 |
| } |
| rule "pad.WID.9" { |
| caption "pad.WID.9: Min width of high parallel pad in x direction < 60.0" |
| edge_length ( edge_boolean -inside pad_cross_len_x bondpadHP ) -lt 60 |
| } |
| rule "pad.LEN.5" { |
| caption "pad.LEN.5: Min length of high parallel pad in y direction < 60.0" |
| edge_length ( edge_boolean -inside pad_cross_len_y bondpadHP ) -lt 60 |
| } |
| exte pad -lt 50 -abut -lt 90 -output region -outputlayer isolated_pad_1 |
| select -interact -not pad isolated_pad_1 -outputlayer isolated_pad |
| not pad isolated_pad -outputlayer non_iso_pad |
| edge_expand ( edge_boolean -inside pad_cross_len_x non_iso_pad ) -outside_by 0.05 -outputlayer isolated_pad_x |
| edge_expand ( edge_boolean -inside pad_cross_len_y non_iso_pad ) -outside_by 0.05 -outputlayer isolated_pad_y |
| rule "pad.WID.12" { |
| caption "pad.WID.12: Min width of wafer level burn-in pad in x direction < 50.0" |
| edge_length ( edge_boolean -inside pad_cross_len_x bondpadWLBI ) -lt 50 |
| } |
| rule "pad.LEN.7" { |
| caption "pad.LEN.7: Min length of wafer level burn-in pad in y direction < 60.0" |
| edge_length ( edge_boolean -inside pad_cross_len_y bondpadWLBI ) -lt 60 |
| } |
| rule "pad.SP.14" { |
| caption "pad.SP.14: Min space of fine pitch pad in x direction to fine pitch, high pitch, staggered or wafer level burn_in in pad < 8.0" |
| select -interact ( exte bondpadFP ( or bondpadFP bondpadHP bondpadSTG bondpadWLBI ) -lt 8 -abut -lt 90 -output region -metric opposite -para ) ( edge_expand pad_cross_wid_x -by 0.1 ) |
| } |
| rule "pad.SP.15" { |
| caption "pad.SP.15: Min space of high pitch pad in x direction to high pitch, staggered and wafer level burn in pad < 15.0" |
| select -interact ( exte bondpadHP ( or bondpadHP bondpadSTG bondpadWLBI ) -lt 15 -abut -lt 90 -output region -metric opposite -para ) ( edge_expand pad_cross_wid_x -by 0.1 ) |
| } |
| rule "pad.SP.17" { |
| caption "pad.SP.17: Min space of wafer level burn in pad in x direction to staggered or wafer level burn in pad < 50.0" |
| select -interact ( exte bondpadWLBI ( or bondpadSTG bondpadWLBI ) -lt 50 -abut -lt 90 -output region -metric opposite -para ) ( edge_expand pad_cross_wid_x -by 0.1 ) |
| } |
| rule "pad.SP.18" { |
| caption "pad.SP.18: Min space of staggered pad in x direction < 30.0" |
| select -interact ( exte bondpadSTG -lt 30 -abut -lt 90 -output region -metric opposite -para ) ( edge_expand pad_cross_wid_x -by 0.1 ) |
| } |
| rule "pad.LEN.9" { |
| caption "pad.LEN.9: Max width/length of bond pad > 150.0" |
| edge_length pad_squared_off -gt 150 |
| } |
| and padCenter ( and BONDPAD padX ) -outputlayer padCenterAllX |
| and padCenter ( and BONDPAD padY ) -outputlayer padCenterAllY |
| edge_expand ( angle padCenterAllX -eq 90 ) -outside_by 200000 -outputlayer padCenterAllxSz |
| edge_expand ( angle padCenterAllY -eq 0 ) -outside_by 200000 -outputlayer padCenterAllySz |
| and ( or padCenterAllX padCenterAllxSz ) solid_seal -outputlayer padCenterDieX |
| and ( or padCenterAllY padCenterAllySz ) solid_seal -outputlayer padCenterDieY |
| inte padCenterDieX -eq 0.2 -abut -lt 90 -metric opposite -para -output region -outputlayer padCenterinDieXw |
| inte padCenterDieY -eq 0.2 -abut -lt 90 -metric opposite -para -output region -outputlayer padCenterinDieYw |
| exte padCenterDieX -lt 9.0 -abut -lt 90 -single_point -output region -outputlayer padCenterinDieXsp |
| exte padCenterDieY -lt 9.0 -abut -lt 90 -single_point -output region -outputlayer padCenterinDieYsp |
| not padCenterDieX padCenterinDieXw -outputlayer padCenterinDieXwBad |
| not padCenterDieY padCenterinDieYw -outputlayer padCenterinDieYwBad |
| or padCenterinDieXsp ( select -interact BONDPAD ( and BONDPAD ( select -interact padCenterAllX padCenterinDieXsp ) ) ) -outputlayer padCenterinDieXspBad |
| or padCenterinDieYsp ( select -interact BONDPAD ( and BONDPAD ( select -interact padCenterAllY padCenterinDieYsp ) ) ) -outputlayer padCenterinDieYspBad |
| edge_expand ( angle ( and bondpadSTG padCenterAllX ) -eq 0 ) -outside_by 5000 -outputlayer padCenterSTGxySz |
| edge_expand ( angle ( and bondpadSTG padCenterAllY ) -eq 90 ) -outside_by 5000 -outputlayer padCenterSTGyySz |
| and ( or padCenterAllX padCenterSTGxySz ) solid_seal -outputlayer padCenterSTGinDieXy |
| and ( or padCenterAllY padCenterSTGyySz ) solid_seal -outputlayer padCenterSTGinDieYy |
| rule "pad.SP.19" { |
| caption "pad.SP.19: Min. pitch spacing of staggered pad (adjacent row) in X-direction < 40.0" |
| select -interact ( exte ( and pad_ctr_box bondPadSTG ) -lt 39 -abut -lt 90 -output region -metric opposite -para ) ( edge_expand pad_cross_len_x -by 0.1 ) |
| } |
| rule "pad.SP.20" { |
| caption "pad.SP.20: Min. pitch spacing of staggered pad (adjacent row) in Y-direction < 40.0" |
| select -interact ( exte ( and pad_ctr_box bondPadSTG ) -lt 39 -abut -lt 90 -output region -metric opposite -para ) ( edge_expand pad_cross_len_y -by 0.1 ) |
| } |
| edge_expand ( angle ( and bondpadSTG padCenterAllX ) -eq 90 ) -outside_by 5000 -outputlayer padCenterSTGxxSz |
| and ( or padCenterAllX padCenterSTGxxSz ) solid_seal -outputlayer padCenterSTGinDieXx |
| exte padCenterSTGinDieXx -lt 9.0 -abut -lt 90 -single_point -output region -outputlayer padCenterinDieXspSTG |
| not padCenterSTGinDieXx padCenterinDieXspSTG -outputlayer padCenterinDieXspSTGGood |
| select -interact bondPadSTG ( and bondPadSTG ( select -interact ( and padCenterAllX bondPadSTG ) padCenterinDieXspSTGGood ) ) -outputlayer padSTGinDieXsp |
| rule "pad.SP.21" { |
| caption "pad.SP.21: Min. spacing of staggered pad in adjacent rows in y direction < 9.0" |
| exte padSTGinDieXsp bondPadSTG -lt 9.0 -abut -lt 90 -single_point -output region |
| } |
| edge_expand padSTGedgX -outside_by 284 -outputlayer bondpadSTGscribe |
| edge_expand padFPedgX -outside_by 200 -outputlayer bondpadFPscribe |
| edge_expand padHPedgX -outside_by 200 -outputlayer bondpadHPscribe |
| edge_expand padWLBIedgX -outside_by 200 -outputlayer bondpadWLBIscribe |
| edge_expand ( edge_boolean -coincident_only solid_seal SEALID ) -outside_by 0.005 -outputlayer outsideSEALedge |
| select -interact bondpadSTGscribe ( and bondpadSTGscribe outsideSEALedge ) -outputlayer bondpadSTGscribeBad |
| select -interact bondpadFPscribe ( and bondpadFPscribe outsideSEALedge ) -outputlayer bondpadFPscribeBad |
| select -interact bondpadHPscribe ( and bondpadHPscribe outsideSEALedge ) -outputlayer bondpadHPscribeBad |
| select -interact bondpadWLBIscribe ( and bondpadWLBIscribe outsideSEALedge ) -outputlayer bondpadWLBIscribeBad |
| rule "pad.SP.22" { |
| caption "pad.SP.22: Min space staggered pad opening to adj. scribe (outer edge of seal) in x direction < 200.0" |
| copy bondpadSTGscribeBad |
| } |
| rule "pad.SP.23" { |
| caption "pad.SP.23: Min space fine pitch pad opening to adj. scribe (outer edge of seal) < 200.0" |
| copy bondpadFPscribeBad |
| } |
| rule "pad.SP.24" { |
| caption "pad.SP.24: Min space of wafer level burn in pad opening in x direction to adj. scribe in x direction < 200.0" |
| copy bondpadWLBIscribeBad |
| } |
| and pmm inductor -outputlayer pmmInInd |
| rule "pad.WID.14" { |
| caption "pad.WID.14: Min. width of pad opening inside inductor < 5.0" |
| inte padInInd -lt 5.0 -abut -lt 90 -single_point -output region |
| } |
| rule "pad.ENC.3" { |
| caption "pad.ENC.3: Min. enclosure of pad opening inside inductor by pmm is 0" |
| and padInInd pmm -outputlayer q0padInIndand |
| not padInInd pmm |
| } |
| rule "pad.CON.10" { |
| caption "pad.CON.10: pad opening inside inductor must be enclosed by pmm" |
| not padInInd pmm |
| } |
| rule "pad.ENC.4" { |
| caption "pad.ENC.4: Min. enclosure of pad opening inside inductor by met5 < 2.7" |
| and padInInd met5 -outputlayer q1padInIndand |
| enc q1padInIndand met5 -lt 2.7 -measure all -abut -lt 90 -single_point -output region |
| } |
| rule "pad.CON.11" { |
| caption "pad.CON.11: pad opening inside inductor must be enclosed by met5" |
| not padInInd met5 |
| } |
| rule "pad.ENC.5" { |
| caption "pad.ENC.5: Min. enclosure of pmm inside inductor by rdl < 10.75" |
| and pmmInInd rdl -outputlayer q0pmmInIndand |
| enc q0pmmInIndand rdl -lt 10.75 -measure all -abut -lt 90 -single_point |
| } |
| rule "pad.ENC.6" { |
| caption "pad.ENC.6: pmm inside inductor must be enclosed by rdl" |
| not pmmInInd rdl |
| } |
| select -interact pad pad_pwr -outputlayer pad_power |
| select -interact pad pad_gnd -outputlayer pad_ground |
| select -interact pad pad_io -outputlayer pad_signal |
| rule "pad.CON.12" { |
| caption "pad.CON.12: Only one layer areaid/pad_pwr, areaid/pad_io and/or areaid/pad_gnd can be used on a single pad" |
| and ( and pad pad_power ) pad_ground |
| and ( and pad pad_power ) pad_signal |
| and ( and pad pad_ground ) pad_signal |
| and ( and pad pad_signal ) pad_power |
| and ( and pad pad_signal ) pad_ground |
| } |
| rule "pad.CON.13" { |
| caption "pad.CON.13: Layers areaid/pad_pwr, areaid/pad_io and/or areaid/pad_gnd must be inside layer pad" |
| not pad_gnd pad |
| not pad_pwr pad |
| not pad_io pad |
| } |
| rule "pad.CON.14" { |
| caption "pad.con.14: Met4 is prohibited inside pad" |
| and pad met4i |
| } |
| |
| |
| // |
| // LVS Exclude Rules |
| // |
| |
| |
| |
| rule "LVS_exclude.WARN.1" { |
| caption "LVS_exclude.WARN.1: LVS_exclude does not enclose any device" |
| select -enclose -not LVS_exclude ( or diffi polyi capm cap2m npn pnp diffres polyres lires m1res m2res m3res m4res m5res pwres DIODEID PHdiodeID fuse pad ) |
| } |
| rule "LVS_exclude.CON.1" { |
| caption "LVS_exclude.CON.1: LVS_exclude must not straddle gate" |
| edge_boolean -inside LVS_exclude gate |
| } |
| rule "LVS_exclude.CON.2" { |
| caption "LVS_exclude.CON.2: LVS_exclude must not straddle N+ source/drain" |
| edge_boolean -inside LVS_exclude nsd |
| } |
| rule "LVS_exclude.CON.3" { |
| caption "LVS_exclude.CON.3: LVS_exclude must not straddle P+ source/drain" |
| edge_boolean -inside LVS_exclude psd |
| } |
| rule "LVS_exclude.CON.4" { |
| caption "LVS_exclude.CON.4: LVS_exclude must not straddle capm" |
| edge_boolean -inside LVS_exclude capm |
| } |
| rule "LVS_exclude.CON.5" { |
| caption "LVS_exclude.CON.5: LVS_exclude must not straddle cap2m" |
| edge_boolean -inside LVS_exclude cap2m |
| } |
| rule "LVS_exclude.CON.6" { |
| caption "LVS_exclude.CON.6: LVS_exclude must not straddle pwell:res" |
| edge_boolean -inside LVS_exclude pwres |
| } |
| rule "LVS_exclude.CON.7" { |
| caption "LVS_exclude.CON.7: LVS_exclude must not straddle diff:res" |
| edge_boolean -inside LVS_exclude diffres |
| } |
| rule "LVS_exclude.CON.8" { |
| caption "LVS_exclude.CON.8: LVS_exclude must not straddle poly:res" |
| edge_boolean -inside LVS_exclude polyres |
| } |
| rule "LVS_exclude.CON.9" { |
| caption "LVS_exclude.CON.9: LVS_exclude must not straddle li:res" |
| edge_boolean -inside LVS_exclude lires |
| } |
| rule "LVS_exclude.CON.10" { |
| caption "LVS_exclude.CON.10: LVS_exclude must not straddle met1:res" |
| edge_boolean -inside LVS_exclude m1res |
| } |
| rule "LVS_exclude.CON.11" { |
| caption "LVS_exclude.CON.11: LVS_exclude must not straddle met2:res" |
| edge_boolean -inside LVS_exclude m2res |
| } |
| rule "LVS_exclude.CON.12" { |
| caption "LVS_exclude.CON.12: LVS_exclude must not straddle met3:res" |
| edge_boolean -inside LVS_exclude m3res |
| } |
| rule "LVS_exclude.CON.13" { |
| caption "LVS_exclude.CON.13: LVS_exclude must not straddle met4:res" |
| edge_boolean -inside LVS_exclude m4res |
| } |
| rule "LVS_exclude.CON.14" { |
| caption "LVS_exclude.CON.14: LVS_exclude must not straddle met5:res" |
| edge_boolean -inside LVS_exclude m5res |
| } |
| rule "LVS_exclude.CON.15" { |
| caption "LVS_exclude.CON.15: LVS_exclude must not straddle areaid:diode" |
| edge_boolean -inside LVS_exclude DiodeID |
| } |
| rule "LVS_exclude.CON.16" { |
| caption "LVS_exclude.CON.16: LVS_exclude must not straddle pnp" |
| edge_boolean -inside LVS_exclude pnp |
| } |
| rule "LVS_exclude.CON.17" { |
| caption "LVS_exclude.CON.17: LVS_exclude must not straddle npn" |
| edge_boolean -inside LVS_exclude npn |
| } |
| rule "LVS_exclude.CON.18" { |
| caption "LVS_exclude.CON.18: LVS_exclude must not straddle areaid:photo" |
| edge_boolean -inside LVS_exclude PHdiodeID |
| } |
| rule "LVS_exclude.CON.19" { |
| caption "LVS_exclude.CON.19: LVS_exclude must not straddle pad" |
| edge_boolean -inside LVS_exclude pad |
| } |
| rule "LVS_exclude.OVL.1" { |
| caption "LVS_exclude.OVL.1: LVS_exclude must be inside areaid:moduleCut" |
| not LVS_exclude moduleCutArea |
| } |
| |
| // |
| // RECOMMENDED RULES |
| // |
| |
| #IFNDEF SKIP_RECOMMENDED_CHECKS |
| and prBndry SEALnoHoles_ORIGIN -outputlayer pr_chip_check_RECOMMENDED |
| not prBndry SEALnoHoles_ORIGIN -outputlayer pr_ip_check_RECOMMENDED |
| rule "prBndry.CON.2" { |
| caption "prBndry.CON.2: prBoundary.boundary not allowed in chip layout" |
| copy pr_chip_check_RECOMMENDED |
| } |
| |
| |
| #ENDIF |
| |
| |
| |
| |
| // |
| // photo checks |
| // |
| |
| select -interact dnwell ( and dnwell ( and ntap PHdiodeID ) ) -outputlayer photoDiode |
| rule "photo.WID.1" { |
| caption "photo.WID.1: Min/Max width of areaid:photo = 3.0" |
| edge_length -not photoDiode -eq 3.0 |
| } |
| rule "photo.SP.1" { |
| caption "photo.SP.1: Min spacing/notch of areaid:photo < 5.0" |
| exte photoDiode -lt 5.0 -abut -lt 90 -single_point -output region |
| } |
| rule "photo.SP.2" { |
| caption "photo.SP.2: Min spacing between areaid:photo and deep nwell < 5.3" |
| exte photoDiode ( not dnwell photoDiode ) -lt 5.3 -abut -lt 90 -single_point -output region |
| } |
| rule "photo.CON.1" { |
| caption "photo.CON.1: Photo diode edges must be coincident with areaid:photo" |
| edge_boolean -coincident_only -inside -not photoDiode PHdiodeID |
| } |
| rule "photo.CON.2" { |
| caption "photo.CON.2: areaid:photo must be enclosed by dnwell ring" |
| not photoDiode ( holes dnwell -inner ) |
| } |
| rule "photo.CON.3" { |
| caption "photo.CON.3: areaid:photo must be enclosed by p+tap ring" |
| not photoDiode ( holes PTAP -inner ) |
| } |
| rule "photo.WID.2" { |
| caption "photo.WID.2: Min/Max width of nwell inside areaid:photo = 0.84" |
| edge_length -not ( and photoDiode nwell ) -eq 0.84 |
| } |
| rule "photo.ENC.1" { |
| caption "photo.ENC.1: Min/Max enclosure of nwell by areaid:photo = 1.08" |
| not photoDiode nwell -outputlayer photoOutsideNwell |
| not photoOutsideNwell ( inte photoOutsideNwell -eq 1.08 -metric opposite_extended 1.08 -para ONLY -output region ) |
| } |
| rule "photo.WID.3" { |
| caption "photo.WID.3: Min/Max width of tap inside areaid:photo = 0.41" |
| edge_length -not ( and photoDiode tap ) -eq 0.41 |
| } |
| rule "photo.ENC.2" { |
| caption "photo.ENC.2: Min/Max enclosure of tap by nwell inside areaid:photo = 0.215" |
| not ( and photoDiode nwell ) tap -outputlayer photoNwellBeyondTap |
| not photoNwellBeyondTap ( inte photoNwellBeyondTap -eq 0.215 -metric opposite_extended 0.215 -para ONLY -output region ) |
| } |
| |
| |
| // |
| // Metal checks |
| // |
| |
| |
| |
| rule "met1.AR.1" { |
| caption "met1.AR.1: Min area of met1 < 0.083" |
| area met1i -lt 0.083 |
| } |
| holes met1i -outputlayer met1_hole |
| holes met1i -inner -outputlayer met1_hole_empty |
| rule "met1.AR.2" { |
| caption "met1.AR.2: Min area of met1 hole < 0.14" |
| area met1_hole -lt 0.14 |
| area met1_hole_empty -lt 0.14 |
| } |
| rule "met1.WID.1" { |
| caption "met1.WID.1: Min width of met1 < 0.14" |
| inte met1i -lt 0.14 -abut -lt 90 -single_point -output region |
| } |
| rule "met1.SP.1" { |
| caption "met1.SP.1: Min space & notch of met1 < 0.14" |
| exte met1i -lt 0.14 -abut -lt 90 -single_point -output region |
| } |
| with_width met1i -gt 3.0 -outputlayer wide_met1a |
| size wide_met1a -by 0.28 -inside_of met1i -step 0.07 -outputlayer wide_met1 |
| rule "met1.SP.2" { |
| caption "met1.SP.2: Wide met1 (including wide metal extending 0.28 into narrow metal) min spacing to met1 < 0.28" |
| exte wide_met1 met1i -lt 0.28 -abut -lt 90 -output region |
| } |
| #IFDEF SAVE_CONSTRUCTION_LAYERS |
| rule "keep_wide_met1" { |
| caption "keep_wide_met1: Derived wide met1 for reference" |
| copy wide_met1 |
| } |
| #ENDIF |
| rule "met2.AR.1" { |
| caption "met2.AR.1: Min area of met2 < 0.0676" |
| area met2i -lt 0.0676 |
| } |
| holes met2i -outputlayer met2_hole |
| holes met2i -inner -outputlayer met2_hole_empty |
| rule "met2.AR.2" { |
| caption "met2.AR.2: Min area of met2 hole < 0.14" |
| area met2_hole -lt 0.14 |
| area met2_hole_empty -lt 0.14 |
| } |
| rule "met2.WID.1" { |
| caption "met2.WID.1: Min width of met2 < 0.14" |
| inte met2i -lt 0.14 -abut -lt 90 -single_point -output region |
| } |
| rule "met2.SP.1" { |
| caption "met2.SP.1: Min space & notch of met2 < 0.14" |
| exte met2i -lt 0.14 -abut -lt 90 -single_point -output region |
| } |
| with_width met2i -gt 3.0 -outputlayer wide_met2a |
| size wide_met2a -by 0.28 -inside_of met2i -step 0.07 -outputlayer wide_met2 |
| rule "met2.SP.2" { |
| caption "met2.SP.2: Wide met2 (including wide metal extending 0.28 into narrow metal) min spacing to met2 < 0.28" |
| exte wide_met2 met2i -lt 0.28 -abut -lt 90 -output region |
| } |
| #IFDEF SAVE_CONSTRUCTION_LAYERS |
| rule "keep_wide_met2" { |
| caption "keep_wide_met2: Derived wide met2 for reference" |
| copy wide_met2 |
| } |
| #ENDIF |
| rule "met3.AR.1" { |
| caption "met3.AR.1: Min area of met3 < 0.24" |
| area met3i -lt 0.24 |
| } |
| holes met3i -outputlayer met3_hole |
| holes met3i -inner -outputlayer met3_hole_empty |
| rule "met3.AR.2" { |
| caption "met3.AR.2: Min area of met3 hole < 0.2" |
| area met3_hole -lt 0.2 |
| area met3_hole_empty -lt 0.2 |
| } |
| rule "met3.WID.1" { |
| caption "met3.WID.1: Min width of met3 < 0.3" |
| inte met3i -lt 0.3 -abut -lt 90 -single_point -output region |
| } |
| rule "met3.SP.1" { |
| caption "met3.SP.1: Min space & notch of met3 < 0.3" |
| exte met3i -lt 0.3 -abut -lt 90 -single_point -output region |
| } |
| with_width met3i -gt 3.0 -outputlayer wide_met3a |
| size wide_met3a -by 0.28 -inside_of met3i -step 0.07 -outputlayer wide_met3 |
| rule "met3.SP.2" { |
| caption "met3.SP.2: Wide met3 (including wide metal extending 0.28 into narrow metal) min spacing to met3 < 0.4" |
| exte wide_met3 met3i -lt 0.4 -abut -lt 90 -output region |
| } |
| #IFDEF SAVE_CONSTRUCTION_LAYERS |
| rule "keep_wide_met3" { |
| caption "keep_wide_met3: Derived wide met3 for reference" |
| copy wide_met3 |
| } |
| #ENDIF |
| rule "met4.AR.1" { |
| caption "met4.AR.1: Min area of met4 < 0.24" |
| area met4i -lt 0.24 |
| } |
| holes met4i -outputlayer met4_hole |
| holes met4i -inner -outputlayer met4_hole_empty |
| rule "met4.AR.2" { |
| caption "met4.AR.2: Min area of met4 hole < 0.2" |
| area met4_hole -lt 0.2 |
| area met4_hole_empty -lt 0.2 |
| } |
| rule "met4.WID.1" { |
| caption "met4.WID.1: Min width of met4 < 0.3" |
| inte met4i -lt 0.3 -abut -lt 90 -single_point -output region |
| } |
| rule "met4.SP.1" { |
| caption "met4.SP.1: Min space & notch of met4 < 0.3" |
| exte met4i -lt 0.3 -abut -lt 90 -single_point -output region |
| } |
| with_width met4i -gt 3.0 -outputlayer wide_met4a |
| size wide_met4a -by 0.28 -inside_of met4i -step 0.07 -outputlayer wide_met4 |
| rule "met4.SP.2" { |
| caption "met4.SP.2: Wide met4 (including wide metal extending 0.28 into narrow metal) min spacing to met4 < 0.4" |
| exte wide_met4 met4i -lt 0.4 -abut -lt 90 -output region |
| } |
| #IFDEF SAVE_CONSTRUCTION_LAYERS |
| rule "keep_wide_met4" { |
| caption "keep_wide_met4: Derived wide met4 for reference" |
| copy wide_met4 |
| } |
| #ENDIF |
| rule "met5.AR.1" { |
| caption "met5.AR.1: Min area of met5 < 4.0" |
| area met5i -lt 4.0 |
| } |
| holes met5i -outputlayer met5_hole |
| holes met5i -inner -outputlayer met5_hole_empty |
| rule "met5.AR.2" { |
| caption "met5.AR.2: Min area of met5 hole < 0.14" |
| area met5_hole -lt 0.14 |
| area met5_hole_empty -lt 0.14 |
| } |
| rule "met5.WID.1" { |
| caption "met5.WID.1: Min width of met5 < 1.6" |
| inte met5i -lt 1.6 -abut -lt 90 -single_point -output region |
| } |
| rule "met5.SP.1" { |
| caption "met5.SP.1: Min space & notch of met5 < 1.6" |
| exte met5i -lt 1.6 -abut -lt 90 -single_point -output region |
| } |
| with_width met5i -gt 3.0 -outputlayer wide_met5a |
| size wide_met5a -by 0.28 -inside_of met5i -step 0.07 -outputlayer wide_met5 |
| extent_cell "s8cell_ee_plus_sseln_a" "s8cell_ee_plus_sseln_b" "s8cell_ee_plus_sselp_a" "s8cell_ee_plus_sselp_b" "s8fpls_pl8" "s8fs_cmux4_fm" -outputlayer m1_enc_mc_exempt |
| rule "met1.ENC.1" { |
| caption "met1.ENC.1: Min enclosure of mcon by met1 (except inside areaid:core) < 0.03" |
| enc ( not mcon COREID ) met1i -lt 0.03 -measure all -abut -lt 90 -single_point -output region |
| } |
| rule "met1.ENC.1a" { |
| caption "met1.ENC.1a: Min enclosure of mcon by met1 (for exempt cells) < 0.005" |
| enc ( not ( and mcon m1_enc_mc_exempt ) COREID ) met1i -lt 0.005 -measure all -abut -lt 90 -single_point -output region |
| } |
| rule "met1.ENC.2" { |
| caption "met1.ENC.2: Min enclosure of adj. sides of mcon in periphery by met1 < 0.06" |
| enc mcon_PERI met1i -lt 0.06 -abut -lt 90 -para -measure all -project -gt 0 -output positive1 -outputlayer m1_enc_1 |
| rect_chk -not ( edge_expand m1_enc_1 -inside_by 0.005 ) -orthogonal_only |
| } |
| rule "met2.ENC.1" { |
| caption "met2.ENC.1: Min enclosure of via1 by met2 outside areaid:core < 0.055" |
| enc ( not via1 COREID ) met2 -lt 0.055 -abut -lt 90 -output region -single_point |
| } |
| rule "met2.ENC.3" { |
| caption "met2.ENC.3: Min enclosure of via1 by met2 inside areaid:core < 0.045" |
| enc ( and via1 COREID ) met2 -lt 0.045 -abut -lt 90 -output region -single_point |
| } |
| rule "met2.ENC.2" { |
| caption "met2.ENC.2: Min enclosure of adj. sides of via1 in periphery by met2 < 0.085" |
| enc via1 met2i -lt 0.085 -abut -lt 90 -para -measure all -project -gt 0 -output positive1 -outputlayer m2_enc_1 |
| rect_chk -not ( edge_expand m2_enc_1 -inside_by 0.005 ) -orthogonal_only |
| } |
| rule "met3.ENC.1" { |
| caption "met3.ENC.1: Min enclosure of via2 by met3 < 0.065" |
| enc via2 met3i -lt 0.065 -abut -lt 90 -output region -single_point |
| } |
| rule "met4.ENC.1" { |
| caption "met4.ENC.1: Min enclosure of via3 by met4 < 0.065" |
| enc via3 met4i -lt 0.065 -abut -lt 90 -output region -single_point |
| } |
| rule "met5.ENC.1" { |
| caption "met5.ENC.1: Min enclosure of via4 by met5 < 0.31" |
| enc via4 met5i -lt 0.31 -abut -lt 90 -output region -single_point |
| } |
| |
| |
| // |
| // Local interconnect checks |
| // |
| |
| |
| |
| extent_cell "vpp*" -outputlayer vpp_hd5 |
| and li_i vpp_hd5 -outputlayer li_in_vpp |
| not li_i li_in_vpp -outputlayer li_not_vpp |
| or ( select -interact -not li_not_vpp COREID ) ( select -cut li_not_vpp COREID ) -outputlayer li_not_vpp_cut_or_outside_core |
| or li_in_vpp ( select -inside li_not_vpp COREID ) -outputlayer li_in_vpp_or_inside_core |
| select -inside li COREID -outputlayer li_inside_core |
| rule "li.WID.1" { |
| caption "li.WID.1: Min width of local interconnect (not vpp) crossing or outside areaid:core < 0.17" |
| inte ( or ( not ( not li_i COREID ) vpp_hd5 ) ( not ( select -cut li_i COREID ) vpp_hd5 ) ) -lt 0.17 -abut -lt 90 -single_point -output region |
| } |
| rule "li.WID.2" { |
| caption "li.WID.2: Min width of local interconnect in vppcap < 0.14" |
| inte ( and li_i vpp_hd5 ) -lt 0.14 -abut -lt 90 -single_point -output region |
| } |
| rule "li.WID.3" { |
| caption "li.WID.3: Min width of local interconnect in areaid:core < 0.14" |
| inte ( and li_i COREID ) -lt 0.14 -abut -lt 90 -single_point -output region |
| } |
| rule "li.SP.1" { |
| caption "li.SP.1: Min space of local interconnect (not vpp) crossing or outside areaid:core < 0.17" |
| exte ( not li_i COREID ) li_i -lt 0.17 -abut -lt 90 -single_point -output region |
| } |
| rule "li.SP.2" { |
| caption "li.SP.2: Min space of local interconnect in vppcap < 0.14" |
| exte li_in_vpp li -lt 0.14 -abut -lt 90 -single_point -output region |
| } |
| rule "li.SP.3" { |
| caption "li.SP.3: Min space of local interconnect inside areaid:core < 0.165" |
| exte li_inside_core li -lt 0.165 -abut -lt 90 -single_point -output region |
| } |
| not licon COREID -outputlayer licon_nocore |
| rule "li.ENC.1" { |
| caption "li.ENC.1: Enclosure of licon by one of two adjacent local interconnect sides < 0.08" |
| enc licon_nocore li -lt 0.08 -abut -lt 90 -para -measure all -project -gt 0 -output positive1 -outputlayer li_en_1 |
| rect_chk -not ( edge_expand li_en_1 -inside_by 0.005 ) -orthogonal_only |
| } |
| rule "li.AR.1" { |
| caption "li.AR.1: Min area of local interconnect < 0.0561" |
| area li -lt 0.0561 |
| } |
| rule "li.WID.4" { |
| caption "li.WID.3: Min local interconnect resistor width < 0.29" |
| and lires li_i -outputlayer li_and_res |
| not li_and_res ESDID -outputlayer li_and_res_not_esd |
| edge_expand ( edge_boolean -coincident_only -not li_and_res_not_esd li ) -outside_by 0.005 -outputlayer li_and_res_not_esd_not_li_edge |
| and ( exte li_and_res_not_esd_not_li_edge -lt 0.29 -abut -lt 90 -output region ) li_and_res_not_esd |
| } |
| |
| |
| // |
| // Via/contact checks |
| // |
| |
| |
| |
| not ( select -interact -not licon ( or rpm urpm ) ) SEALID -outputlayer licon_no_prec_res |
| select -interact licon ( or rpm urpm ) -outputlayer licon_prec_res |
| rule "licon.WID.1" { |
| caption "licon.WID.1: Min licon width (non-bar) < 0.17" |
| inte licon_no_prec_res -lt 0.17 -abut -lt 90 -output region |
| } |
| rule "licon.LEN.1" { |
| caption "licon.LEN.1: Max licon length (non-bar) > 0.17" |
| edge_length licon_no_prec_res -gt 0.17 |
| } |
| rule "licon.WID.2" { |
| caption "licon.WID.2: Exact size of bar licon = 0.19 X 2.0" |
| rect_chk -not licon_prec_res -eq 0.19 -by -eq 2.0 -orthogonal_only |
| } |
| rule "licon.SP.1" { |
| caption "licon.SP.1: Min licon space (non-bar) outside areaid:core < 0.17" |
| exte ( not licon_no_prec_res COREID ) -lt 0.17 -abut -lt 90 -single_point -output region |
| } |
| rule "licon.SP.2" { |
| caption "licon.SP.2: Min end-to-end space of bar licon < 0.35" |
| edge_length licon_prec_res -lt 2.0 -outputlayer bar_licon_end |
| exte bar_licon_end -lt 0.35 -abut -lt 90 -output region |
| } |
| rule "licon.SP.3" { |
| caption "licon.SP.3: Min side-to-side spacing of bar licon < 0.510" |
| edge_length licon_prec_res -gt 0.19 -outputlayer bar_licon_side |
| exte bar_licon_side -lt 0.510 -abut -lt 90 -output region |
| } |
| rule "licon.SP.4" { |
| caption "licon.SP.4: Min space from bar licon to square licon < 0.510" |
| exte licon_no_prec_res licon_prec_res -lt 0.510 -abut -lt 90 -output region -single_point |
| } |
| rule "licon.WID.3" { |
| caption "licon.WID.3: Min width licon in areaid:seal < 0.17" |
| inte ( and licon SEALID ) -lt 0.17 -abut -lt 90 -output region |
| } |
| rule "licon.WID.4" { |
| caption "licon.WID.4: Max width of licon in areaid:seal > 0.17+0.005" |
| with_width ( and licon SEALID ) -gt "0.17+0.005" |
| } |
| rule "licon.ENC.1" { |
| caption "licon.ENC.1: Min enclosure of licon by diff (not tap) < 0.04" |
| enc ( not licon_nocore tap ) diffi -lt 0.04 -measure all -abut -lt 90 -output region -single_point |
| } |
| rule "licon.SP.5" { |
| caption "licon.SP.5: Min space from tap licon to diff-abutting tap edge > 0.06" |
| exte ( and licon_nocore tap ) ( edge_boolean -coincident_only -outside diff tap ) -lt 0.06 -abut -lt 90 -output region |
| } |
| rule "licon.ENC.2" { |
| caption "licon.ENC.2: Min enclosure of licon by diff on one of two adjacent sides < 0.06" |
| enc licon_nocore diff -lt 0.06 -abut -lt 90 -para -measure all -project -gt 0 -output positive1 -outputlayer li_enc_2 |
| rect_chk -not ( edge_expand li_enc_2 -inside_by 0.005 ) -orthogonal_only |
| } |
| rule "licon.CON.7" { |
| caption "licon.CON.7: Layer licon cannot straddle tap" |
| select -cut licon_nocore tap |
| } |
| rule "licon.ENC.4" { |
| caption "licon.ENC.4: Min enclosure of licon by isolated tap on one of two adjacent sides < 0.12" |
| select -with_edge tap ( edge_boolean -coincident_only -outside tap diff ) -outputlayer non_isolated_tap |
| not tap non_isolated_tap -outputlayer isolated_tap |
| enc licon_nocore isolated_tap -lt 0.12 -abut -lt 90 -para -measure all -project -gt 0 -output positive1 -outputlayer li_enc_4 |
| rect_chk -not ( edge_expand li_enc_4 -inside_by 0.005 ) -orthogonal_only |
| } |
| rule "licon.ENC.5" { |
| caption "licon.ENC.5: Min enclosure of licon by poly < 0.05" |
| enc licon_nocore polyi -lt 0.05 -abut -lt 90 -output region -single_point |
| } |
| rule "licon.ENC.6" { |
| caption "licon.ENC.6: Min enclosure of licon by poly on one of two adjacent sides < 0.08" |
| enc licon_nocore polyi -lt 0.08 -abut -lt 90 -para -measure all -project -gt 0 -output positive1 -outputlayer li_enc_6 |
| rect_chk -not ( edge_expand li_enc_6 -inside_by 0.005 ) -orthogonal_only |
| } |
| rule "licon.SP.6" { |
| caption "licon.SP.6: Min space from poly licon to psdm (no overlap alowed) < 0.110" |
| exte ( select -outside ( and licon_nocore poly ) ( or rpm urpm ) ) psdm -lt 0.110 -abut -lt 90 -single_point -output region |
| and ( select -outside ( and poly licon_nocore ) ( or rpm urpm ) ) psdm |
| } |
| rule "licon.SP.7" { |
| caption "licon.SP.7: Min space from licon on (tap in low voltage nwell) to varactor channel < 0.25" |
| and poly ( select -interact -not nwell ( or v5 v12 v20 ) ) -outputlayer poly_in_lv_nw |
| and poly_in_lv_nw ( and tap ( select -interact -not nwell ( or v5 v12 v20 ) ) ) -outputlayer var_ch |
| and ( and licon_nocore ( select -interact -not nwell ( or v5 v12 v20 ) ) ) tap -outputlayer var_licon |
| exte var_licon var_ch -lt 0.25 -abut -lt 90 -output region -single_point |
| } |
| and diffi polyi -outputlayer MOSDIFFandPOLY |
| and MOSDIFFandPOLY polyGate -outputlayer userGate |
| select -outside MOSDIFFandPOLY polyGate -outputlayer derivedGate |
| not ( or derivedGate userGate ) ENID -outputlayer allGatetmp |
| select -touch allGatetmp drainGate -eq 1 -outputlayer remGate |
| not allGatetmp remGate -outputlayer allGate |
| edge_expand ( edge_boolean -coincident_only -inside MOSDIFFandPOLY poly ) -outside_by 0.005 -outputlayer drainGate |
| rule "licon.SP.8" { |
| caption "licon.SP.8: Min space and no overlap from licon on diff to poly on diff (except standard cells) < 0.055" |
| and allGate ESDID -outputlayer esdGate |
| and esdGate nwell -outputlayer pesd |
| select -interact pesd v5 -outputlayer phvesd |
| and ENID ( and poly v5 ) -outputlayer allENIDgate |
| select -interact nwell ENID -outputlayer nwellENID |
| and allENIDgate dnwell -outputlayer pfetExtDrTmp |
| and pfetExtDrTmp nwellENID -outputlayer pfetExtDr |
| copy pfetExtDr -outputlayer pvhv |
| not allGate esdGate -outputlayer fetGate |
| and fetGate nwell -outputlayer pfet_dev |
| not ( select -interact pfet_dev v5 ) ( or pvhv phvesd ) -outputlayer phv |
| not gate STDCID -outputlayer gate_not_std_cell |
| not diff poly -outputlayer xfom |
| select -interact licon ( and licon xfom ) -outputlayer licon1ToXfom |
| not licon1ToXfom COREID -outputlayer licon1ToXfom_PERI |
| exte licon1ToXfom_PERI gate_not_std_cell -lt 0.055 -abut -lt 90 -output region -single_point |
| and licon1ToXfom_PERI gate_not_std_cell |
| } |
| inte ( and ( and ( and poly diff ) psdm ) hvtp ) -eq 0.15 -output region -abut -lt 90 -outputlayer phvt_15_gate |
| rule "licon.SP.9" { |
| caption "licon.SP.9: Min space from licon on diff to poly on diff in standard cells (except 0.15um p+ high vt) < 0.05" |
| exte ( and ( and licon_nocore diff ) STDCID ) ( not ( and poly diff ) phvt_15_gate ) -lt 0.05 -abut -lt 90 -output region -single_point |
| } |
| // JAG changed from 0.055 to 0.050 per CB and PC: |
| rule "licon.SP.10" { |
| caption "licon.SP.10: Min space from licon on diff to poly on diff in standard cells for p+ high vt < 0.05" |
| exte ( and phvt_15_gate STDCID ) ( and ( and licon_nocore diff ) STDCID ) -lt 0.05 -abut -lt 90 -output region -single_point |
| } |
| rule "licon.SP.11" { |
| caption "licon.SP.11: Min space (no overlap) from licon on diff to npc < 0.09" |
| exte ( not ( and diffi licon_nocore ) COREID ) npc -lt 0.09 -abut -lt 90 -single_point -output region |
| and ( and diffi licon_nocore ) npc |
| } |
| rule "licon.SP.12" { |
| caption "licon.SP.12: Min space from poly licon to diff < 0.19" |
| exte ( not ( and polyi licon ) COREID ) diffi -lt 0.19 -abut -lt 90 -output region -single_point |
| } |
| rule "licon.SP.13" { |
| caption "licon.SP.13: Min space from poly licon to diff in core < 0.13" |
| exte ( and ( and polyi licon ) COREID ) diffi -lt 0.13 -abut -lt 90 -output region -single_point |
| } |
| rule "licon.SP.14" { |
| caption "licon.SP.14: Min licon space (non-bar) inside areaid:core < 0.165" |
| exte ( and licon_no_prec_res COREID ) -lt 0.165 -abut -lt 90 -single_point -output region |
| } |
| rule "licon.ENC.7" { |
| caption "licon.ENC.7: Min enclosure of poly licon by npc outside areaid:core < 0.1" |
| enc ( not ( and polyi licon ) COREID ) npc -lt 0.1 -abut -lt 90 -output region -single_point |
| } |
| rule "licon.ENC.8" { |
| caption "licon.ENC.8: Min enclosure of poly licon by npc inside areaid:core >= 0.045" |
| enc ( and ( and polyi licon ) COREID ) npc -lt 0.045 -abut -lt 90 -output region -single_point |
| } |
| rule "licon.CON.8" { |
| caption "licon.CON.8: Every source or drain diff must enclose at least 1 licon (except in v20)" |
| and ( not diff poly ) nsdm -outputlayer nsrcdrn |
| and ( not diff poly ) psdm -outputlayer psrcdrn |
| or ( select -with_edge nsrcdrn ( edge_boolean -coincident_only -outside nsrcdrn ptap ) ) ( select -with_edge psrcdrn ( edge_boolean -coincident_only -outside psrcdrn ntap ) ) -outputlayer source_diffusion |
| not source_diffusion COREID -outputlayer source_diffusion_peri |
| select -inside licon source_diffusion_peri -outputlayer licon_in_source |
| not ( select -outside source_diffusion_peri licon_in_source ) V20 |
| } |
| rule "licon.CON.9" { |
| caption "licon.CON.9: Every tap must enclose at least 1 licon (except in v20)" |
| not tap COREID -outputlayer tap_PERI |
| or tap_PERI ( select -cut tap COREID ) -outputlayer npcon_tap |
| not ( select -enclose -not npcon_tap licon ) v20 |
| } |
| rule "licon.CON.10" { |
| caption "licon.CON.10: Layer licon must not overlap both poly and diff" |
| and ( and poly licon ) diff |
| } |
| rule "licon.CON.11" { |
| caption "licon.CON.11: Poly licon must be inside npc" |
| not ( and poly licon ) npc |
| } |
| rule "licon.CON.12" { |
| caption "licon.CON.12: psdm overlapping poly and licon is prohibited inside areaid:core" |
| and ( and ( and poly licon ) psdm ) COREID |
| } |
| select -donut mcon -outputlayer mcon_donut |
| not mcon mcon_donut -outputlayer non_ring_mcon |
| rule "mcon.WID.1" { |
| caption "mcon.WID.1: Min width of mcon < 0.17" |
| inte mcon -lt 0.17 -output region |
| } |
| rule "mcon.LEN.1" { |
| caption "mcon.LEN.1: Max width of mcon > 0.17" |
| select -with_edge non_ring_mcon ( edge_length non_ring_mcon -gt 0.17 ) |
| } |
| rule "mcon.SP.1" { |
| caption "mcon.SP.1: Min spacing of mcon < 0.19" |
| exte mcon -lt 0.19 -abut -lt 90 -single_point -output region |
| } |
| rule "via1.WID.1" { |
| caption "via1.WID.1: Min width of via1 outside areaid:moduleCut < 0.15" |
| inte ( not via1 moduleCutAREA ) -lt 0.15 -abut -lt 90 -output region |
| } |
| rule "via1.LEN.1" { |
| caption "via1.LEN.1: Max length of via1 outside areaid:moduleCut > 0.15" |
| edge_length ( not via1 moduleCutAREA ) -gt 0.15 |
| } |
| rect_chk ( and via1 moduleCutAREA ) -eq 0.15 -by -eq 0.15 -orthogonal_only -outputlayer via_in_mc_good_1 |
| rect_chk ( and via1 moduleCutAREA ) -eq 0.23 -by -eq 0.23 -orthogonal_only -outputlayer via_in_mc_good_2 |
| rect_chk ( and via1 moduleCutAREA ) -eq 0.28 -by -eq 0.28 -orthogonal_only -outputlayer via_in_mc_good_3 |
| rule "via1.WID.2" { |
| caption "via1.WID.2: Only three size of square via1s allowed inside areaid:moduleCut: 0.15, 0.23 or 0.28" |
| not ( and via1 moduleCutAREA ) ( or via_in_mc_good_1 via_in_mc_good_2 via_in_mc_good_3 ) |
| } |
| rule "via1.SP.1" { |
| caption "via1.SP.1: Min space of via1 < 0.17" |
| exte via1 -lt 0.17 -abut -lt 90 -output region -single_point |
| } |
| rule "via1.ENC.1" { |
| caption "via1.ENC.1: Min enclosure of via1 by metal 1 outside module cut area < 0.055" |
| enc ( not via1 moduleCutAREA ) met1i -lt 0.055 -measure all -abut -lt 90 -single_point -output region |
| } |
| rule "via1.ENC.2" { |
| caption "via1.ENC.2: Min enclosure of 0.23um via1 by met1 inside module cut area < 0.03" |
| enc via_in_mc_good_2 met1i -lt 0.03 -measure all -abut -lt 90 -single_point -output region |
| } |
| rule "via1.ENC.3" { |
| caption "via1.ENC.3: Min enclosure of 0.28 um via by met1 inside module cut area < 0" |
| not via_in_mc_good_3 met1i |
| } |
| rule "via1.ENC.4" { |
| caption "via1.ENC.4: Min enclosure of 0.15um via by met1 on one of two adjacent sides < 0.085" |
| rect_chk via1 -eq 0.15 -by -eq 0.15 -orthogonal_only -outputlayer via_15 |
| enc via_15 met1i -lt 0.085 -abut -lt 90 -para -measure all -project -gt 0 -output positive1 -outputlayer via_enc_5 |
| rect_chk -not ( edge_expand via_enc_5 -inside_by 0.005 ) -orthogonal_only |
| } |
| rule "via1.ENC.5" { |
| caption "via1.ENC.5: Min enclosure of 0.23um via by met1 on one of two adjacent sides < 0.085" |
| rect_chk via1 -eq 0.23 -by -eq 0.23 -orthogonal_only -outputlayer via_23 |
| enc via_23 met1i -lt 0.06 -abut -lt 90 -para -measure all -project -gt 0 -output positive1 -outputlayer via_enc_5 |
| rect_chk -not ( edge_expand via_enc_5 -inside_by 0.005 ) -orthogonal_only |
| } |
| rule "via2.WID.1" { |
| caption "via2.WID.1: Min via2 width outside areaid:moduleCut < 0.2" |
| inte ( not via2 moduleCutAREA ) -lt 0.2 -abut -lt 90 -output region |
| } |
| rule "via2.LEN.1" { |
| caption "via2.LEN.1: Max length via2 outside areaid:moduleCut > 0.2" |
| edge_length ( not via2 moduleCutAREA ) -gt 0.2 |
| } |
| rect_chk ( and via2 moduleCutAREA ) -eq 0.2 -by -eq 0.2 -orthogonal_only -outputlayer via2_in_mc_good_1 |
| rect_chk ( and via2 moduleCutAREA ) -eq 0.28 -by -eq 0.28 -orthogonal_only -outputlayer via2_in_mc_good_2 |
| rect_chk ( and via2 moduleCutAREA ) -eq 1.2 -by -eq 1.2 -orthogonal_only -outputlayer via2_in_mc_good_3 |
| rect_chk ( and via2 moduleCutAREA ) -eq 1.5 -by -eq 1.5 -orthogonal_only -outputlayer via2_in_mc_good_4 |
| rule "via2.WID.2" { |
| caption "via2.WID.2: Only four sizes of square via2s allowed inside areaid:moduleCut: 0.2, 0.28, 1.2 or 1.5" |
| not ( and via2 moduleCutAREA ) ( or via2_in_mc_good_1 via2_in_mc_good_2 via2_in_mc_good_3 via2_in_mc_good_4 ) |
| } |
| rule "via2.SP.1" { |
| caption "via2.SP.1: Min space of via2 < 0.2" |
| exte via2 -lt 0.2 -abut -lt 90 -output region -single_point |
| } |
| rule "via2.ENC.1" { |
| caption "via2.ENC.1: Min enclosure of via2 by met2 < 0.04" |
| enc via2 met2 -lt 0.04 -abut -lt 90 -measure all -single_point -output region |
| } |
| rule "via2.ENC.2" { |
| caption "via2.ENC.2: Min enclosure of 1.5um via2 by met2 inside module cut area < 0.14" |
| enc via2_in_mc_good_4 met2i -lt 0.14 -abut -lt 90 -measure all -single_point -output region |
| } |
| rule "via2.ENC.3" { |
| caption "via2.ENC.3: Min enclosure of via2 by met2 on one of two adjacent sides < 0.085" |
| enc via2 met2i -lt 0.085 -abut -lt 90 -para -measure all -project -gt 0 -output positive1 -outputlayer via2_enc_5 |
| rect_chk -not ( edge_expand via2_enc_5 -inside_by 0.005 ) -orthogonal_only |
| } |
| select -donut via3 -outputlayer ring_via3 |
| not via3 ring_via3 -outputlayer non_ring_via3 |
| not via3 moduleCutAREA -outputlayer via3_not_modulecut |
| and via3 moduleCutAREA -outputlayer via3_and_modulecut |
| rule "via3.WID.1" { |
| caption "via3.WID.1: Min width of via3 outside areaid:moduleCut < 0.20" |
| inte via3_not_modulecut -lt 0.20 -output region |
| } |
| rule "via3.LEN.1" { |
| caption "via3.LEN.1: Max length via3 outside areaid:moduleCut > 0.20" |
| select -with_edge via3_not_modulecut ( edge_length via3_not_modulecut -gt 0.20 ) |
| } |
| rule "via3.WID.2" { |
| caption "via3.WID.2: via3 size inside areaid:moduleCut must be 0.20 or 0.80" |
| rect_chk via3_and_modulecut -eq 0.20 -by -eq 0.20 -orthogonal_only -outputlayer good_a_v3 |
| rect_chk via3_and_modulecut -eq 0.80 -by -eq 0.80 -orthogonal_only -outputlayer good_b_v3 |
| or good_a_v3 good_b_v3 -outputlayer all_good_v3 |
| not via3_and_modulecut all_good_v3 |
| } |
| rule "via3.SP.1" { |
| caption "via3.SP.1: Min space of via3 < 0.20" |
| exte via3 -lt 0.20 -abut -lt 90 -single_point -output region |
| } |
| rule "via3.ENC.1" { |
| caption "via3.ENC.1: Min enclosure of via3 by met3 < 0.06" |
| enc via3 met3i -lt 0.06 -measure all -abut -lt 90 -single_point |
| } |
| rule "via3.ENC.2" { |
| caption "via3.ENC.2: Min enclosure of adjacent sides of via3 by met3 < 0.09" |
| enc via3 met3i -lt 0.09 -abut -lt 90 -para -measure all -project -gt 0 -output positive1 -outputlayer via3_enc_2 |
| rect_chk -not ( edge_expand via3_enc_2 -inside_by 0.005 ) -orthogonal_only |
| } |
| select -donut via4 -outputlayer ring_via4 |
| not via4 ring_via4 -outputlayer non_ring_via4 |
| not non_ring_via4 moduleCutAREA -outputlayer via4_not_modulecut |
| and non_ring_via4 moduleCutAREA -outputlayer via4_and_modulecut |
| rule "via4.WID.1" { |
| caption "via4.WID.1: Min width via4 outside areaid:moduleCut < 0.80" |
| inte non_ring_via4 -lt 0.80 -output region |
| } |
| rule "via4.LEN.1" { |
| caption "via4.LEN.1: Max length via4 outside areaid:moduleCut > 0.80" |
| select -with_edge non_ring_via4 ( edge_length non_ring_via4 -gt 0.80 ) |
| } |
| rule "via4.SP.1" { |
| caption "via4.SP.1: Min space of via4 < 0.80" |
| exte via4 -lt 0.80 -abut -lt 90 -single_point -output region |
| } |
| rule "via4.ENC.1" { |
| caption "via4.ENC.1: Min enclosure of via4 by met4 < 0.06" |
| enc via4 met4i -lt 0.06 -abut -lt 90 -measure all -output region -single_point |
| } |
| |
| |
| // |
| // NSM checks |
| // |
| |
| |
| |
| rule "nsm.WID.1" { |
| caption "nsm.WID.1: Min width nsm < 3.0" |
| inte nsm -lt 3.0 -abut -lt 90 -single_point -output region |
| } |
| rule "nsm.SP.1" { |
| caption "nsm.SP.1: Min space nsm < 4.0" |
| exte nsm -lt 4.0 -abut -lt 90 -single_point -output region |
| } |
| or nsm NSMmk -outputlayer nsm_or_nsm_mask |
| or ( and SEALID ( select -donut diff ) ) ( or ( extent_cell "nikon*" ) nikon_cross ) -outputlayer exempt_NSM3_Cells |
| or ( extent_cell "s8Fab_crntic*" ) dieCut -outputlayer exempt_NSM3a_Cells |
| not diffi exempt_NSM3_Cells -outputlayer diffi_not_exempt |
| rule "nsm.SP.2" { |
| caption "nsm.SP.2: nsm or nsm mask space to non-exempt diff < 1.0" |
| exte diffi_not_exempt nsm -lt 1.0 -abut -lt 90 -single_point -output region |
| exte diffi_not_exempt NSMmk -lt 1.0 -abut -lt 90 -single_point -output region |
| } |
| rule "nsm.OVL.2" { |
| caption "nsm.OVL.2: diff cannot overlap nsm or nsm mask" |
| and diffi_not_exempt nsm_or_nsm_mask |
| } |
| rule "nsm.ENC.2" { |
| caption "nsm.ENC.2: diff enclosure by frame boundary < 3.0" |
| not diffi exempt_NSM3a_Cells -outputlayer diffi_not_exempt2 |
| enc diffi_not_exempt2 frameBndr -lt 3.0 -measure all -abut -lt 90 -single_point -output region |
| } |
| not diff_fill exempt_NSM3_Cells -outputlayer diff_fill_not_exempt |
| rule "nsm.SP.3" { |
| caption "nsm.SP.3: nsm or nsm mask space to non-exempt diff fill < 1.0" |
| exte diff_fill_not_exempt nsm -lt 1.0 -abut -lt 90 -single_point -output region |
| exte diff_fill_not_exempt NSMmk -lt 1.0 -abut -lt 90 -single_point -output region |
| } |
| rule "nsm.OVL.3" { |
| caption "nsm.OVL.3: diff fill cannot overlap nsm or nsm mask" |
| and diff_fill_not_exempt nsm_or_nsm_mask |
| } |
| rule "nsm.ENC.3" { |
| caption "nsm.ENC.3: diff fill enclosure by frame boundary < 3.0" |
| not diff_fill exempt_NSM3a_Cells -outputlayer diff_fill_not_exempt2 |
| enc diff_fill_not_exempt2 frameBndr -lt 3.0 -measure all -abut -lt 90 -single_point -output region |
| } |
| not FOMmk exempt_NSM3_Cells -outputlayer FOMmk_not_exempt |
| rule "nsm.SP.4" { |
| caption "nsm.SP.4: nsm or nsm mask space to non-exempt cfom mask < 1.0" |
| exte FOMmk_not_exempt nsm -lt 1.0 -abut -lt 90 -single_point -output region |
| exte FOMmk_not_exempt NSMmk -lt 1.0 -abut -lt 90 -single_point -output region |
| } |
| rule "nsm.OVL.4" { |
| caption "nsm.OVL.4: cfom mask cannot overlap nsm or nsm mask" |
| and FOMmk_not_exempt nsm_or_nsm_mask |
| } |
| rule "nsm.ENC.4" { |
| caption "nsm.ENC.4: cfom mask enclosure by frame boundary < 3.0" |
| not FOMmk exempt_NSM3a_Cells -outputlayer FOMmk_not_exempt2 |
| enc FOMmk_not_exempt2 frameBndr -lt 3.0 -measure all -abut -lt 90 -single_point -output region |
| } |
| not polyi exempt_NSM3_Cells -outputlayer polyi_not_exempt |
| rule "nsm.SP.5" { |
| caption "nsm.SP.5: nsm or nsm mask space to non-exempt poly < 1.0" |
| exte polyi_not_exempt nsm -lt 1.0 -abut -lt 90 -single_point -output region |
| exte polyi_not_exempt NSMmk -lt 1.0 -abut -lt 90 -single_point -output region |
| } |
| rule "nsm.OVL.5" { |
| caption "nsm.OVL.5: poly cannot overlap nsm or nsm mask" |
| and polyi_not_exempt nsm_or_nsm_mask |
| } |
| rule "nsm.ENC.5" { |
| caption "nsm.ENC.5: poly enclosure by frame boundary < 3.0" |
| not polyi exempt_NSM3a_Cells -outputlayer polyi_not_exempt2 |
| enc polyi_not_exempt2 frameBndr -lt 3.0 -measure all -abut -lt 90 -single_point -output region |
| } |
| not P1Mmk exempt_NSM3_Cells -outputlayer P1Mmk_not_exempt |
| rule "nsm.SP.6" { |
| caption "nsm.SP.6: nsm or nsm mask space to non-exempt poly mask < 1.0" |
| exte P1Mmk_not_exempt nsm -lt 1.0 -abut -lt 90 -single_point -output region |
| exte P1Mmk_not_exempt NSMmk -lt 1.0 -abut -lt 90 -single_point -output region |
| } |
| rule "nsm.OVL.6" { |
| caption "nsm.OVL.6: poly mask cannot overlap nsm or nsm mask" |
| and P1Mmk_not_exempt nsm_or_nsm_mask |
| } |
| rule "nsm.ENC.6" { |
| caption "nsm.ENC.6: poly mask enclosure by frame boundary < 3.0" |
| not P1Mmk exempt_NSM3a_Cells -outputlayer P1Mmk_not_exempt2 |
| enc P1Mmk_not_exempt2 frameBndr -lt 3.0 -measure all -abut -lt 90 -single_point -output region |
| } |
| not li_i exempt_NSM3_Cells -outputlayer li_i_not_exempt |
| rule "nsm.SP.7" { |
| caption "nsm.SP.7: nsm or nsm mask space to non-exempt li < 1.0" |
| exte li_i_not_exempt nsm -lt 1.0 -abut -lt 90 -single_point -output region |
| exte li_i_not_exempt NSMmk -lt 1.0 -abut -lt 90 -single_point -output region |
| } |
| rule "nsm.OVL.7" { |
| caption "nsm.OVL.7: li cannot overlap nsm or nsm mask" |
| and li_i_not_exempt nsm_or_nsm_mask |
| } |
| rule "nsm.ENC.7" { |
| caption "nsm.ENC.7: li enclosure by frame boundary < 3.0" |
| not li_i exempt_NSM3a_Cells -outputlayer li_i_not_exempt2 |
| enc li_i_not_exempt2 frameBndr -lt 3.0 -measure all -abut -lt 90 -single_point -output region |
| } |
| not LI1Mmk exempt_NSM3_Cells -outputlayer LI1Mmk_not_exempt |
| rule "nsm.SP.8" { |
| caption "nsm.SP.8: nsm or nsm mask space to non-exempt li mask < 1.0" |
| exte LI1Mmk_not_exempt nsm -lt 1.0 -abut -lt 90 -single_point -output region |
| exte LI1Mmk_not_exempt NSMmk -lt 1.0 -abut -lt 90 -single_point -output region |
| } |
| rule "nsm.OVL.8" { |
| caption "nsm.OVL.8: li mask cannot overlap nsm or nsm mask" |
| and LI1Mmk_not_exempt nsm_or_nsm_mask |
| } |
| rule "nsm.ENC.8" { |
| caption "nsm.ENC.8: li mask enclosure by frame boundary < 3.0" |
| not LI1Mmk exempt_NSM3a_Cells -outputlayer LI1Mmk_not_exempt2 |
| enc LI1Mmk_not_exempt2 frameBndr -lt 3.0 -measure all -abut -lt 90 -single_point -output region |
| } |
| not met1i exempt_NSM3_Cells -outputlayer met1i_not_exempt |
| rule "nsm.SP.9" { |
| caption "nsm.SP.9: nsm or nsm mask space to non-exempt met1 < 1.0" |
| exte met1i_not_exempt nsm -lt 1.0 -abut -lt 90 -single_point -output region |
| exte met1i_not_exempt NSMmk -lt 1.0 -abut -lt 90 -single_point -output region |
| } |
| rule "nsm.OVL.9" { |
| caption "nsm.OVL.9: met1 cannot overlap nsm or nsm mask" |
| and met1i_not_exempt nsm_or_nsm_mask |
| } |
| rule "nsm.ENC.9" { |
| caption "nsm.ENC.9: met1 enclosure by frame boundary < 3.0" |
| not met1i exempt_NSM3a_Cells -outputlayer met1i_not_exempt2 |
| enc met1i_not_exempt2 frameBndr -lt 3.0 -measure all -abut -lt 90 -single_point -output region |
| } |
| not MM1mk exempt_NSM3_Cells -outputlayer MM1mk_not_exempt |
| rule "nsm.SP.10" { |
| caption "nsm.SP.10: nsm or nsm mask space to non-exempt met1 mask < 1.0" |
| exte MM1mk_not_exempt nsm -lt 1.0 -abut -lt 90 -single_point -output region |
| exte MM1mk_not_exempt NSMmk -lt 1.0 -abut -lt 90 -single_point -output region |
| } |
| rule "nsm.OVL.10" { |
| caption "nsm.OVL.10: met1 mask cannot overlap nsm or nsm mask" |
| and MM1mk_not_exempt nsm_or_nsm_mask |
| } |
| rule "nsm.ENC.10" { |
| caption "nsm.ENC.10: met1 mask enclosure by frame boundary < 3.0" |
| not MM1mk exempt_NSM3a_Cells -outputlayer MM1mk_not_exempt2 |
| enc MM1mk_not_exempt2 frameBndr -lt 3.0 -measure all -abut -lt 90 -single_point -output region |
| } |
| not met2i exempt_NSM3_Cells -outputlayer met2i_not_exempt |
| rule "nsm.SP.11" { |
| caption "nsm.SP.11: nsm or nsm mask space to non-exempt met2 < 1.0" |
| exte met2i_not_exempt nsm -lt 1.0 -abut -lt 90 -single_point -output region |
| exte met2i_not_exempt NSMmk -lt 1.0 -abut -lt 90 -single_point -output region |
| } |
| rule "nsm.OVL.11" { |
| caption "nsm.OVL.11: met2 cannot overlap nsm or nsm mask" |
| and met2i_not_exempt nsm_or_nsm_mask |
| } |
| rule "nsm.ENC.11" { |
| caption "nsm.ENC.11: met2 enclosure by frame boundary < 3.0" |
| not met2i exempt_NSM3a_Cells -outputlayer met2i_not_exempt2 |
| enc met2i_not_exempt2 frameBndr -lt 3.0 -measure all -abut -lt 90 -single_point -output region |
| } |
| not MM2mk exempt_NSM3_Cells -outputlayer MM2mk_not_exempt |
| rule "nsm.SP.12" { |
| caption "nsm.SP.12: nsm or nsm mask space to non-exempt met2 mask < 1.0" |
| exte MM2mk_not_exempt nsm -lt 1.0 -abut -lt 90 -single_point -output region |
| exte MM2mk_not_exempt NSMmk -lt 1.0 -abut -lt 90 -single_point -output region |
| } |
| rule "nsm.OVL.12" { |
| caption "nsm.OVL.12: met2 mask cannot overlap nsm or nsm mask" |
| and MM2mk_not_exempt nsm_or_nsm_mask |
| } |
| rule "nsm.ENC.12" { |
| caption "nsm.ENC.12: met2 mask enclosure by frame boundary < 3.0" |
| not MM2mk exempt_NSM3a_Cells -outputlayer MM2mk_not_exempt2 |
| enc MM2mk_not_exempt2 frameBndr -lt 3.0 -measure all -abut -lt 90 -single_point -output region |
| } |
| not met3i exempt_NSM3_Cells -outputlayer met3i_not_exempt |
| rule "nsm.SP.13" { |
| caption "nsm.SP.13: nsm or nsm mask space to non-exempt met3 < 1.0" |
| exte met3i_not_exempt nsm -lt 1.0 -abut -lt 90 -single_point -output region |
| exte met3i_not_exempt NSMmk -lt 1.0 -abut -lt 90 -single_point -output region |
| } |
| rule "nsm.OVL.13" { |
| caption "nsm.OVL.13: met3 cannot overlap nsm or nsm mask" |
| and met3i_not_exempt nsm_or_nsm_mask |
| } |
| rule "nsm.ENC.13" { |
| caption "nsm.ENC.13: met3 enclosure by frame boundary < 3.0" |
| not met3i exempt_NSM3a_Cells -outputlayer met3i_not_exempt2 |
| enc met3i_not_exempt2 frameBndr -lt 3.0 -measure all -abut -lt 90 -single_point -output region |
| } |
| not MM3mk exempt_NSM3_Cells -outputlayer MM3mk_not_exempt |
| rule "nsm.SP.14" { |
| caption "nsm.SP.14: nsm or nsm mask space to non-exempt met3 mask < 1.0" |
| exte MM3mk_not_exempt nsm -lt 1.0 -abut -lt 90 -single_point -output region |
| exte MM3mk_not_exempt NSMmk -lt 1.0 -abut -lt 90 -single_point -output region |
| } |
| rule "nsm.OVL.14" { |
| caption "nsm.OVL.14: met3 mask cannot overlap nsm or nsm mask" |
| and MM3mk_not_exempt nsm_or_nsm_mask |
| } |
| rule "nsm.ENC.14" { |
| caption "nsm.ENC.14: met3 mask enclosure by frame boundary < 3.0" |
| not MM3mk exempt_NSM3a_Cells -outputlayer MM3mk_not_exempt2 |
| enc MM3mk_not_exempt2 frameBndr -lt 3.0 -measure all -abut -lt 90 -single_point -output region |
| } |
| not met4i exempt_NSM3_Cells -outputlayer met4i_not_exempt |
| rule "nsm.SP.15" { |
| caption "nsm.SP.15: nsm or nsm mask space to non-exempt met4 < 1.0" |
| exte met4i_not_exempt nsm -lt 1.0 -abut -lt 90 -single_point -output region |
| exte met4i_not_exempt NSMmk -lt 1.0 -abut -lt 90 -single_point -output region |
| } |
| rule "nsm.OVL.15" { |
| caption "nsm.OVL.15: met4 cannot overlap nsm or nsm mask" |
| and met4i_not_exempt nsm_or_nsm_mask |
| } |
| rule "nsm.ENC.15" { |
| caption "nsm.ENC.15: met4 enclosure by frame boundary < 3.0" |
| not met4i exempt_NSM3a_Cells -outputlayer met4i_not_exempt2 |
| enc met4i_not_exempt2 frameBndr -lt 3.0 -measure all -abut -lt 90 -single_point -output region |
| } |
| not MM4mk exempt_NSM3_Cells -outputlayer MM4mk_not_exempt |
| rule "nsm.SP.16" { |
| caption "nsm.SP.16: nsm or nsm mask space to non-exempt met4 mask < 1.0" |
| exte MM4mk_not_exempt nsm -lt 1.0 -abut -lt 90 -single_point -output region |
| exte MM4mk_not_exempt NSMmk -lt 1.0 -abut -lt 90 -single_point -output region |
| } |
| rule "nsm.OVL.16" { |
| caption "nsm.OVL.16: met4 mask cannot overlap nsm or nsm mask" |
| and MM4mk_not_exempt nsm_or_nsm_mask |
| } |
| rule "nsm.ENC.16" { |
| caption "nsm.ENC.16: met4 mask enclosure by frame boundary < 3.0" |
| not MM4mk exempt_NSM3a_Cells -outputlayer MM4mk_not_exempt2 |
| enc MM4mk_not_exempt2 frameBndr -lt 3.0 -measure all -abut -lt 90 -single_point -output region |
| } |
| not met5i exempt_NSM3_Cells -outputlayer met5i_not_exempt |
| rule "nsm.SP.17" { |
| caption "nsm.SP.17: nsm or nsm mask space to non-exempt met5 < 1.0" |
| exte met5i_not_exempt nsm -lt 1.0 -abut -lt 90 -single_point -output region |
| exte met5i_not_exempt NSMmk -lt 1.0 -abut -lt 90 -single_point -output region |
| } |
| rule "nsm.OVL.17" { |
| caption "nsm.OVL.17: met5 cannot overlap nsm or nsm mask" |
| and met5i_not_exempt nsm_or_nsm_mask |
| } |
| rule "nsm.ENC.17" { |
| caption "nsm.ENC.17: met5 enclosure by frame boundary < 3.0" |
| not met5i exempt_NSM3a_Cells -outputlayer met5i_not_exempt2 |
| enc met5i_not_exempt2 frameBndr -lt 3.0 -measure all -abut -lt 90 -single_point -output region |
| } |
| not MM5mk exempt_NSM3_Cells -outputlayer MM5mk_not_exempt |
| rule "nsm.SP.18" { |
| caption "nsm.SP.18: nsm or nsm mask space to non-exempt met5 mask < 1.0" |
| exte MM5mk_not_exempt nsm -lt 1.0 -abut -lt 90 -single_point -output region |
| exte MM5mk_not_exempt NSMmk -lt 1.0 -abut -lt 90 -single_point -output region |
| } |
| rule "nsm.OVL.18" { |
| caption "nsm.OVL.18: met5 mask cannot overlap nsm or nsm mask" |
| and MM5mk_not_exempt nsm_or_nsm_mask |
| } |
| rule "nsm.ENC.18" { |
| caption "nsm.ENC.18: met5 mask enclosure by frame boundary < 3.0" |
| not MM5mk exempt_NSM3a_Cells -outputlayer MM5mk_not_exempt2 |
| enc MM5mk_not_exempt2 frameBndr -lt 3.0 -measure all -abut -lt 90 -single_point -output region |
| } |
| |
| |
| // |
| // NCM checks |
| // |
| |
| |
| |
| not ( and ncm COREID ) exempt_tech_CD -outputlayer ncmCore_drc |
| not ncm ncmCore_drc -outputlayer ncmPeri_drc |
| holes ncm -outputlayer ncm_holes |
| rule "ncm.OVL.1" { |
| caption "ncm.OVL.1: ncm in CORE (not exempt) must not overlap ndiff in periphery" |
| and ncmCore_drc ndiff_PERI |
| } |
| rule "ncm.WID.1" { |
| caption "ncm.WID.1: Min ncm width in periphery < 0.38" |
| inte ncmPeri_drc -lt 0.38 -abut -lt 90 -single_point -output region |
| } |
| rule "ncm.SP.1" { |
| caption "ncm.SP.1: Min ncm spacing/notch < 0.38" |
| exte ncmPeri_drc -lt 0.38 -abut -lt 90 -single_point -output region |
| } |
| rule "ncm.AR.1" { |
| caption "ncm.AR.1: Min ncm area < 0.265" |
| area ncm -lt 0.265 |
| } |
| rule "ncm.AR.2" { |
| caption "ncm.AR.2: Min area of ncm holes < 0.265" |
| area ncm_holes -lt 0.265 |
| } |
| rule "ncm.ENC.1" { |
| caption "ncm.ENC.1: Min enclosure of P+ diff by ncm in areaid:core (not exempt) < 0.235" |
| and ( and diffi psdm ) ncmCore_drc -outputlayer pdiff_in_ncm_core |
| enc pdiff_in_ncm_core ncmCore_drc -lt 0.235 -measure all -abut -lt 90 -single_point -output region |
| } |
| rule "ncm.SP.2" { |
| caption "ncm.SP.2: Min spacing of ncm in areaid:core (not exempt) to ndiff < 0.235" |
| exte ncmCore_drc ( and nsdm diffi ) -lt 0.235 -abut -lt 90 -single_point -output region |
| } |
| rule "ncm.OVL.2" { |
| caption "ncm.OVL.2: ncm in areaid:core (not exempt) must not overlap ndiff" |
| and ncmCore_drc ( and nsdm diffi ) |
| } |
| select -touch -not ( select -outside nwell COREID ) COREID -outputlayer nwellOutCore |
| rule "ncm.SP.3" { |
| caption "ncm.SP.3: Min space of ncm in areaid:core (not exempt) to nwell outside areaid:core < 0.38" |
| exte nwellOutCore ncmCore_drc -lt 0.38 -abut -lt 90 -single_point -output region |
| } |
| |
| |
| // |
| // RPM/URPM checks |
| // |
| |
| |
| |
| and polyi ( and polyres ( and ( or rpm urpm ) psdm ) ) -outputlayer precResistor |
| rule "rpm.WID.1" { |
| caption "rpm.WID.1: Min width rpm < 1.27" |
| inte rpm -lt 1.27 -abut -lt 90 -single_point -output region |
| } |
| rule "rpm.SP.1" { |
| caption "rpm.SP.1: Min space/notch rpm < 0.84" |
| exte rpm -lt 0.84 -abut -lt 90 -single_point -output region |
| } |
| rule "rpm.ENC.1" { |
| caption "rpm.ENC.1: Min enclosure or precision resistor by rpm < 0.2" |
| enc ( and precResistor rpm ) rpm -lt 0.2 -measure all -abut -lt 90 -single_point -output region |
| } |
| rule "rpm.SP.2" { |
| caption "rpm.SP.2: Min spacing of rpm and nsdm < 0.2" |
| exte rpm nsdm -lt 0.2 -abut -lt 90 -single_point -output region |
| } |
| rule "rpm.OVL.1" { |
| caption "rpm.OVL.1: rpm cannot overlap nsdm" |
| and rpm nsdm |
| } |
| rule "rpm.OVL.2" { |
| caption "rpm.OVL.2: poly must not straddle rpm" |
| select -cut poly rpm |
| } |
| rule "urpm.WID.1" { |
| caption "urpm.WID.1: Min width urpm < 1.27" |
| inte urpm -lt 1.27 -abut -lt 90 -single_point -output region |
| } |
| rule "urpm.SP.1" { |
| caption "urpm.SP.1: Min space/notch urpm < 0.84" |
| exte urpm -lt 0.84 -abut -lt 90 -single_point -output region |
| } |
| rule "urpm.ENC.1" { |
| caption "urpm.ENC.1: Min enclosure or precision resistor by rpm < 0.2" |
| enc ( and precResistor urpm ) urpm -lt 0.2 -measure all -abut -lt 90 -single_point -output region |
| } |
| rule "urpm.SP.2" { |
| caption "urpm.SP.2: Min spacing of urpm and nsdm < 0.2" |
| exte urpm nsdm -lt 0.2 -abut -lt 90 -single_point -output region |
| } |
| rule "urpm.OVL.1" { |
| caption "urpm.OVL.1: urpm cannot overlap nsdm" |
| and urpm nsdm |
| } |
| rule "urpm.OVL.2" { |
| caption "urpm.OVL.2: poly must not straddle urpm" |
| select -cut poly urpm |
| } |
| rule "rpm.SP.3" { |
| caption "rpm.SP.3: Min spacing of rpm and poly < 0.2" |
| exte rpm poly -lt 0.2 -abut -lt 90 -single_point -output region |
| } |
| copy rpm -outputlayer rpmNotXmt |
| rule "rpm.SP.4" { |
| caption "rpm.SP.4: Min spacing of rpm and pwell block mask (pwbm) < 2.0" |
| exte rpmNotXmt pwbm -lt 2.0 -single_point -output region |
| } |
| rule "urpm.SP.3" { |
| caption "urpm.SP.3: Min spacing of urpm and poly < 0.2" |
| exte urpm poly -lt 0.2 -abut -lt 90 -single_point -output region |
| } |
| rule "rpm.OVL.3" { |
| caption "rpm.OVL.3: rpm must not overlap pwell block mask (pwbm)" |
| and rpm pwbm |
| } |
| rule "rpm.OVL.4" { |
| caption "rpm.OVL.4: rpm layer must overlap poly" |
| select -interact -not rpm polyi |
| } |
| rule "urpm.OVL.3" { |
| caption "urpm.OVL.3: urpm layer must overlap poly" |
| select -interact -not urpm polyi |
| } |
| |
| |
| // |
| // PRECISION RESISTOR checks |
| // |
| |
| |
| |
| rule "prec_res.ENC.1" { |
| caption "prec_res.ENC.1: Enclosure of precision resistor by psdm < 0.11" |
| enc ( and precResistor psdm ) psdm -lt 0.11 -measure all -abut -lt 90 -single_point -output region |
| } |
| and polyi ( and polyres ( or rpm urpm ) ) -outputlayer precResis |
| rule "prec_res.CON.1" { |
| caption "prec_res.CON.1: Precision resistor must be enclosed by psdm" |
| not precResis psdm |
| } |
| rule "prec_res.ENC.2" { |
| caption "prec_res.ENC.2: Enclosure of precision resitor by npc < 0.095" |
| enc ( and precResistor npc ) npc -lt 0.095 -measure all -abut -lt 90 -single_point -output region |
| } |
| rule "prec_res.CON.2" { |
| caption "prec_res.CON.2: Precision resistor must be enclosed by npc" |
| not precResistor npc |
| } |
| rule "prec_res.SP.1" { |
| caption "prec_res.SP.1: Space of precision resistor to hvntm < 0.185" |
| exte precResistor hvntm -lt 0.185 -abut -lt 90 -single_point -output region |
| } |
| rule "prec_res.OVL.1" { |
| caption "prec_res.OVL.1: Precision resistor must not overlap hvntm" |
| and precResistor hvntm |
| } |
| |
| |
| // |
| // LDNTM checks |
| // |
| |
| |
| |
| and ldntm COREID -outputlayer ldntm_and_core |
| and ldntm_and_core exempt_tech_CD -outputlayer ldntm_and_core_exempt |
| rule "ldntm.WID.1" { |
| caption "ldntm.WID.1: Min width ldntm in areaid:core < 0.7" |
| inte ldntm_and_core -lt 0.7 -abut -lt 90 -single_point -output region |
| } |
| rule "ldntm.SP.1" { |
| caption "ldntm.SP.1: Min space/notch of ldntm in areaid:core < 0.7" |
| exte ldntm_and_core -lt 0.7 -abut -lt 90 -single_point -output region |
| } |
| rule "ldntm.ENC.1" { |
| caption "ldntm.ENC.1: Min enclosure of ndiff by ldntm must be < 0.18" |
| enc ndiff ldntm_and_core -lt 0.18 -single_point -measure all -abut -lt 90 -output positive1 |
| } |
| rule "ldntm.ENC.2" { |
| caption "ldntm.ENC.2: Min enclosure of N+ FET by ldntm in areaid:core < 0.125" |
| enc ( and ngate ldntm_and_core ) ldntm_and_core -lt 0.125 -measure all -abut -lt 90 -single_point -output region |
| } |
| rule "ldntm.OVL.1" { |
| caption "ldntm.OVL.1: ldntm not allowed outside of areaid:core" |
| not ( not ldntm ldntm_and_core ) exempt_tech_CD |
| } |
| rule "ldntm.SP.2" { |
| caption "ldntm.SP.2: Min space between ldntm in areaid:core (exempt) and pdiff < 0.18" |
| exte ldntm_and_core_exempt ( and diffi psdm ) -lt 0.18 -abut -lt 90 -single_point -output region |
| } |
| |
| |
| // |
| // Module Cut checks |
| // |
| |
| |
| |
| extent_cell "*_buildspace" -original -outputlayer build_space |
| with_width met1 -ge 3.0 -outputlayer m1_lrg |
| with_width met2 -ge 3.0 -outputlayer m2_lrg |
| with_width met3 -ge 3.0 -outputlayer m3_lrg |
| with_width met4 -ge 3.0 -outputlayer m4_lrg |
| rule "moduleCut.SP.1" { |
| caption "moduleCut.SP.1: Min spacing of areaid:moduleCut and (nwell NOT build space) < 0.635" |
| exte moduleCutAREA ( not nwell build_space ) -lt 0.635 -abut -lt 90 -single_point -output region |
| } |
| rule "moduleCut.ENC.1" { |
| caption "moduleCut.ENC.1: Min enclosure of (nwell NOT build space) BY areaid:moduleCut < 0.635" |
| enc ( not nwell build_space ) moduleCutArea -lt 0.635 -abut -lt 90 -single_point -output region -exclude_shielded |
| } |
| rule "moduleCut.SP.2" { |
| caption "moduleCut.SP.2: Min spacing of areaid:moduleCut and (diff NOT build space) < 0.135" |
| exte moduleCutAREA ( not diff build_space ) -lt 0.135 -abut -lt 90 -single_point -output region |
| } |
| rule "moduleCut.ENC.2" { |
| caption "moduleCut.ENC.2: Min enclosure of (diff NOT build space) BY areaid:moduleCut < 0.135" |
| enc ( not diff build_space ) moduleCutArea -lt 0.135 -abut -lt 90 -single_point -output region -exclude_shielded |
| } |
| rule "moduleCut.SP.3" { |
| caption "moduleCut.SP.3: Min spacing of areaid:moduleCut and (dnwell NOT build space) < 3.15" |
| exte moduleCutAREA ( not dnwell build_space ) -lt 3.15 -abut -lt 90 -single_point -output region |
| } |
| rule "moduleCut.ENC.3" { |
| caption "moduleCut.ENC.3: Min enclosure of (dnwell NOT build space) BY areaid:moduleCut < 3.15" |
| enc ( not dnwell build_space ) moduleCutArea -lt 3.15 -abut -lt 90 -single_point -output region -exclude_shielded |
| } |
| rule "moduleCut.SP.4" { |
| caption "moduleCut.SP.4: Min spacing of areaid:moduleCut and (lvtn NOT build space) < 0.19" |
| exte moduleCutAREA ( not lvtn build_space ) -lt 0.19 -abut -lt 90 -single_point -output region |
| } |
| rule "moduleCut.ENC.4" { |
| caption "moduleCut.ENC.4: Min enclosure of (lvtn NOT build space) BY areaid:moduleCut < 0.19" |
| enc ( not lvtn build_space ) moduleCutArea -lt 0.19 -abut -lt 90 -single_point -output region -exclude_shielded |
| } |
| rule "moduleCut.SP.5" { |
| caption "moduleCut.SP.5: Min spacing of areaid:moduleCut and (hvtp NOT build space) < 0.19" |
| exte moduleCutAREA ( not hvtp build_space ) -lt 0.19 -abut -lt 90 -single_point -output region |
| } |
| rule "moduleCut.ENC.5" { |
| caption "moduleCut.ENC.5: Min enclosure of (hvtp NOT build space) BY areaid:moduleCut < 0.19" |
| enc ( not hvtp build_space ) moduleCutArea -lt 0.19 -abut -lt 90 -single_point -output region -exclude_shielded |
| } |
| rule "moduleCut.SP.6" { |
| caption "moduleCut.SP.6: Min spacing of areaid:moduleCut and (v5 NOT build space) < 0.35" |
| exte moduleCutAREA ( not v5 build_space ) -lt 0.35 -abut -lt 90 -single_point -output region |
| } |
| rule "moduleCut.ENC.6" { |
| caption "moduleCut.ENC.6: Min enclosure of (v5 NOT build space) BY areaid:moduleCut < 0.35" |
| enc ( not v5 build_space ) moduleCutArea -lt 0.35 -abut -lt 90 -single_point -output region -exclude_shielded |
| } |
| rule "moduleCut.SP.7" { |
| caption "moduleCut.SP.7: Min spacing of areaid:moduleCut and (tunm NOT build space) < 0.25" |
| exte moduleCutAREA ( not tunm build_space ) -lt 0.25 -abut -lt 90 -single_point -output region |
| } |
| rule "moduleCut.ENC.7" { |
| caption "moduleCut.ENC.7: Min enclosure of (tunm NOT build space) BY areaid:moduleCut < 0.25" |
| enc ( not tunm build_space ) moduleCutArea -lt 0.25 -abut -lt 90 -single_point -output region -exclude_shielded |
| } |
| rule "moduleCut.SP.8" { |
| caption "moduleCut.SP.8: Min spacing of areaid:moduleCut and (poly NOT build space) < 0.105" |
| exte moduleCutAREA ( not poly build_space ) -lt 0.105 -abut -lt 90 -single_point -output region |
| } |
| rule "moduleCut.ENC.8" { |
| caption "moduleCut.ENC.8: Min enclosure of (poly NOT build space) BY areaid:moduleCut < 0.105" |
| enc ( not poly build_space ) moduleCutArea -lt 0.105 -abut -lt 90 -single_point -output region -exclude_shielded |
| } |
| rule "moduleCut.SP.9" { |
| caption "moduleCut.SP.9: Min spacing of areaid:moduleCut and (npc NOT build space) < 0.135" |
| exte moduleCutAREA ( not npc build_space ) -lt 0.135 -abut -lt 90 -single_point -output region |
| } |
| rule "moduleCut.ENC.9" { |
| caption "moduleCut.ENC.9: Min enclosure of (npc NOT build space) BY areaid:moduleCut < 0.135" |
| enc ( not npc build_space ) moduleCutArea -lt 0.135 -abut -lt 90 -single_point -output region -exclude_shielded |
| } |
| rule "moduleCut.SP.10" { |
| caption "moduleCut.SP.10: Min spacing of areaid:moduleCut and (nsdm NOT build space) < 0.19" |
| exte moduleCutAREA ( not nsdm build_space ) -lt 0.19 -abut -lt 90 -single_point -output region |
| } |
| rule "moduleCut.ENC.10" { |
| caption "moduleCut.ENC.10: Min enclosure of (nsdm NOT build space) BY areaid:moduleCut < 0.19" |
| enc ( not nsdm build_space ) moduleCutArea -lt 0.19 -abut -lt 90 -single_point -output region -exclude_shielded |
| } |
| rule "moduleCut.SP.11" { |
| caption "moduleCut.SP.11: Min spacing of areaid:moduleCut and (psdm NOT build space) < 0.19" |
| exte moduleCutAREA ( not psdm build_space ) -lt 0.19 -abut -lt 90 -single_point -output region |
| } |
| rule "moduleCut.ENC.11" { |
| caption "moduleCut.ENC.11: Min enclosure of (psdm NOT build space) BY areaid:moduleCut < 0.19" |
| enc ( not psdm build_space ) moduleCutArea -lt 0.19 -abut -lt 90 -single_point -output region -exclude_shielded |
| } |
| rule "moduleCut.SP.12" { |
| caption "moduleCut.SP.12: Min spacing of areaid:moduleCut and (licon NOT build space) < 0.085" |
| exte moduleCutAREA ( not licon build_space ) -lt 0.085 -abut -lt 90 -single_point -output region |
| } |
| rule "moduleCut.ENC.12" { |
| caption "moduleCut.ENC.12: Min enclosure of (licon NOT build space) BY areaid:moduleCut < 0.085" |
| enc ( not licon build_space ) moduleCutArea -lt 0.085 -abut -lt 90 -single_point -output region -exclude_shielded |
| } |
| rule "moduleCut.SP.13" { |
| caption "moduleCut.SP.13: Min spacing of areaid:moduleCut and (li NOT build space) < 0.085" |
| exte moduleCutAREA ( not li build_space ) -lt 0.085 -abut -lt 90 -single_point -output region |
| } |
| rule "moduleCut.ENC.13" { |
| caption "moduleCut.ENC.13: Min enclosure of (li NOT build space) BY areaid:moduleCut < 0.085" |
| enc ( not li build_space ) moduleCutArea -lt 0.085 -abut -lt 90 -single_point -output region -exclude_shielded |
| } |
| rule "moduleCut.SP.14" { |
| caption "moduleCut.SP.14: Min spacing of areaid:moduleCut and (mcon NOT build space) < 0.095" |
| exte moduleCutAREA ( not mcon build_space ) -lt 0.095 -abut -lt 90 -single_point -output region |
| } |
| rule "moduleCut.ENC.14" { |
| caption "moduleCut.ENC.14: Min enclosure of (mcon NOT build space) BY areaid:moduleCut < 0.095" |
| enc ( not mcon build_space ) moduleCutArea -lt 0.095 -abut -lt 90 -single_point -output region -exclude_shielded |
| } |
| rule "moduleCut.SP.15" { |
| caption "moduleCut.SP.15: Min spacing of areaid:moduleCut and (met1 NOT build space) < 0.07" |
| exte moduleCutAREA ( not met1 build_space ) -lt 0.07 -abut -lt 90 -single_point -output region |
| } |
| rule "moduleCut.ENC.15" { |
| caption "moduleCut.ENC.15: Min enclosure of (met1 NOT build space) BY areaid:moduleCut < 0.07" |
| enc ( not met1 build_space ) moduleCutArea -lt 0.07 -abut -lt 90 -single_point -output region -exclude_shielded |
| } |
| rule "moduleCut.SP.16" { |
| caption "moduleCut.SP.16: Min spacing of areaid:moduleCut and (via1 NOT build space) < 0.085" |
| exte moduleCutAREA ( not via1 build_space ) -lt 0.085 -abut -lt 90 -single_point -output region |
| } |
| rule "moduleCut.ENC.16" { |
| caption "moduleCut.ENC.16: Min enclosure of (via1 NOT build space) BY areaid:moduleCut < 0.085" |
| enc ( not via1 build_space ) moduleCutArea -lt 0.085 -abut -lt 90 -single_point -output region -exclude_shielded |
| } |
| rule "moduleCut.SP.17" { |
| caption "moduleCut.SP.17: Min spacing of areaid:moduleCut and (met2 NOT build space) < 0.07" |
| exte moduleCutAREA ( not met2 build_space ) -lt 0.07 -abut -lt 90 -single_point -output region |
| } |
| rule "moduleCut.ENC.17" { |
| caption "moduleCut.ENC.17: Min enclosure of (met2 NOT build space) BY areaid:moduleCut < 0.07" |
| enc ( not met2 build_space ) moduleCutArea -lt 0.07 -abut -lt 90 -single_point -output region -exclude_shielded |
| } |
| rule "moduleCut.SP.18" { |
| caption "moduleCut.SP.18: Min spacing of areaid:moduleCut and (via2 NOT build space) < 0.1" |
| exte moduleCutAREA ( not via2 build_space ) -lt 0.1 -abut -lt 90 -single_point -output region |
| } |
| rule "moduleCut.ENC.18" { |
| caption "moduleCut.ENC.18: Min enclosure of (via2 NOT build space) BY areaid:moduleCut < 0.1" |
| enc ( not via2 build_space ) moduleCutArea -lt 0.1 -abut -lt 90 -single_point -output region -exclude_shielded |
| } |
| rule "moduleCut.SP.19" { |
| caption "moduleCut.SP.19: Min spacing of areaid:moduleCut and (met3 NOT build space) < 0.15" |
| exte moduleCutAREA ( not met3 build_space ) -lt 0.15 -abut -lt 90 -single_point -output region |
| } |
| rule "moduleCut.ENC.19" { |
| caption "moduleCut.ENC.19: Min enclosure of (met3 NOT build space) BY areaid:moduleCut < 0.15" |
| enc ( not met3 build_space ) moduleCutArea -lt 0.15 -abut -lt 90 -single_point -output region -exclude_shielded |
| } |
| rule "moduleCut.SP.20" { |
| caption "moduleCut.SP.20: Min spacing of areaid:moduleCut and (via3 NOT build space) < 0.1" |
| exte moduleCutAREA ( not via3 build_space ) -lt 0.1 -abut -lt 90 -single_point -output region |
| } |
| rule "moduleCut.ENC.20" { |
| caption "moduleCut.ENC.20: Min enclosure of (via3 NOT build space) BY areaid:moduleCut < 0.1" |
| enc ( not via3 build_space ) moduleCutArea -lt 0.1 -abut -lt 90 -single_point -output region -exclude_shielded |
| } |
| rule "moduleCut.SP.21" { |
| caption "moduleCut.SP.21: Min spacing of areaid:moduleCut and (met4 NOT build space) < 0.15" |
| exte moduleCutAREA ( not met4 build_space ) -lt 0.15 -abut -lt 90 -single_point -output region |
| } |
| rule "moduleCut.ENC.21" { |
| caption "moduleCut.ENC.21: Min enclosure of (met4 NOT build space) BY areaid:moduleCut < 0.15" |
| enc ( not met4 build_space ) moduleCutArea -lt 0.15 -abut -lt 90 -single_point -output region -exclude_shielded |
| } |
| rule "moduleCut.SP.22" { |
| caption "moduleCut.SP.22: Min spacing of areaid:moduleCut and (via4 NOT build space) < 0.4" |
| exte moduleCutAREA ( not via4 build_space ) -lt 0.4 -abut -lt 90 -single_point -output region |
| } |
| rule "moduleCut.ENC.22" { |
| caption "moduleCut.ENC.22: Min enclosure of (via4 NOT build space) BY areaid:moduleCut < 0.4" |
| enc ( not via4 build_space ) moduleCutArea -lt 0.4 -abut -lt 90 -single_point -output region -exclude_shielded |
| } |
| rule "moduleCut.SP.23" { |
| caption "moduleCut.SP.23: Min spacing of areaid:moduleCut and (met5 NOT build space) < 0.8" |
| exte moduleCutAREA ( not met5 build_space ) -lt 0.8 -abut -lt 90 -single_point -output region |
| } |
| rule "moduleCut.ENC.23" { |
| caption "moduleCut.ENC.23: Min enclosure of (met5 NOT build space) BY areaid:moduleCut < 0.8" |
| enc ( not met5 build_space ) moduleCutArea -lt 0.8 -abut -lt 90 -single_point -output region -exclude_shielded |
| } |
| rule "moduleCut.SP.24" { |
| caption "moduleCut.SP.24: Min spacing of areaid:moduleCut and (nsm NOT build space) < 2.0" |
| exte moduleCutAREA ( not nsm build_space ) -lt 2.0 -abut -lt 90 -single_point -output region |
| } |
| rule "moduleCut.ENC.24" { |
| caption "moduleCut.ENC.24: Min enclosure of (nsm NOT build space) BY areaid:moduleCut < 2.0" |
| enc ( not nsm build_space ) moduleCutArea -lt 2.0 -abut -lt 90 -single_point -output region -exclude_shielded |
| } |
| rule "moduleCut.SP.25" { |
| caption "moduleCut.SP.25: Min spacing of areaid:moduleCut and (pad NOT build space) < 0.635" |
| exte moduleCutAREA ( not pad build_space ) -lt 0.635 -abut -lt 90 -single_point -output region |
| } |
| rule "moduleCut.ENC.25" { |
| caption "moduleCut.ENC.25: Min enclosure of (pad NOT build space) BY areaid:moduleCut < 0.635" |
| enc ( not pad build_space ) moduleCutArea -lt 0.635 -abut -lt 90 -single_point -output region -exclude_shielded |
| } |
| rule "moduleCut.SP.26" { |
| caption "moduleCut.SP.26: Min spacing of areaid:moduleCut and (ldntm NOT build space) < 0.35" |
| exte moduleCutAREA ( not ldntm build_space ) -lt 0.35 -abut -lt 90 -single_point -output region |
| } |
| rule "moduleCut.ENC.26" { |
| caption "moduleCut.ENC.26: Min enclosure of (ldntm NOT build space) BY areaid:moduleCut < 0.35" |
| enc ( not ldntm build_space ) moduleCutArea -lt 0.35 -abut -lt 90 -single_point -output region -exclude_shielded |
| } |
| rule "moduleCut.SP.27" { |
| caption "moduleCut.SP.27: Min spacing of areaid:moduleCut and (hvntm NOT build space) < 0.19" |
| exte moduleCutAREA ( not hvntm build_space ) -lt 0.19 -abut -lt 90 -single_point -output region |
| } |
| rule "moduleCut.ENC.27" { |
| caption "moduleCut.ENC.27: Min enclosure of (hvntm NOT build space) BY areaid:moduleCut < 0.19" |
| enc ( not hvntm build_space ) moduleCutArea -lt 0.19 -abut -lt 90 -single_point -output region -exclude_shielded |
| } |
| rule "moduleCut.SP.28" { |
| caption "moduleCut.SP.28: Min spacing of areaid:moduleCut and (ncm NOT build space) < 0.19" |
| exte moduleCutAREA ( not ncm build_space ) -lt 0.19 -abut -lt 90 -single_point -output region |
| } |
| rule "moduleCut.ENC.28" { |
| caption "moduleCut.ENC.28: Min enclosure of (ncm NOT build space) BY areaid:moduleCut < 0.19" |
| enc ( not ncm build_space ) moduleCutArea -lt 0.19 -abut -lt 90 -single_point -output region -exclude_shielded |
| } |
| rule "moduleCut.SP.29" { |
| caption "moduleCut.SP.29: Min spacing of areaid:moduleCut and (rdl NOT build space) < 5.0" |
| exte moduleCutAREA ( not rdl build_space ) -lt 5.0 -abut -lt 90 -single_point -output region |
| } |
| rule "moduleCut.ENC.29" { |
| caption "moduleCut.ENC.29: Min enclosure of (rdl NOT build space) BY areaid:moduleCut < 5.0" |
| enc ( not rdl build_space ) moduleCutArea -lt 5.0 -abut -lt 90 -single_point -output region -exclude_shielded |
| } |
| rule "moduleCut.SP.30" { |
| caption "moduleCut.SP.30: Min spacing of areaid:moduleCut and (hvtr NOT build space) < 0.19" |
| exte moduleCutAREA ( not hvtr build_space ) -lt 0.19 -abut -lt 90 -single_point -output region |
| } |
| rule "moduleCut.ENC.30" { |
| caption "moduleCut.ENC.30: Min enclosure of (hvtr NOT build space) BY areaid:moduleCut < 0.19" |
| enc ( not hvtr build_space ) moduleCutArea -lt 0.19 -abut -lt 90 -single_point -output region -exclude_shielded |
| } |
| rule "moduleCut.SP.31" { |
| caption "moduleCut.SP.31: Min spacing of areaid:moduleCut and (large met1 NOT build space) < 0.14" |
| exte moduleCutAREA ( not m1_lrg build_space ) -lt 0.14 -abut -lt 90 -single_point -output region |
| } |
| rule "moduleCut.ENC.31" { |
| caption "moduleCut.ENC.31: Min enclosure of (large met1 NOT build space) BY areaid:moduleCut < 0.14" |
| enc ( not m1_lrg build_space ) moduleCutArea -lt 0.14 -abut -lt 90 -single_point -output region -exclude_shielded |
| } |
| rule "moduleCut.SP.32" { |
| caption "moduleCut.SP.32: Min spacing of areaid:moduleCut and (large met2 NOT build space) < 0.14" |
| exte moduleCutAREA ( not m2_lrg build_space ) -lt 0.14 -abut -lt 90 -single_point -output region |
| } |
| rule "moduleCut.ENC.32" { |
| caption "moduleCut.ENC.32: Min enclosure of (large met2 NOT build space) BY areaid:moduleCut < 0.14" |
| enc ( not m2_lrg build_space ) moduleCutArea -lt 0.14 -abut -lt 90 -single_point -output region -exclude_shielded |
| } |
| rule "moduleCut.SP.33" { |
| caption "moduleCut.SP.33: Min spacing of areaid:moduleCut and (large met3 NOT build space) < 0.20" |
| exte moduleCutAREA ( not m3_lrg build_space ) -lt 0.20 -abut -lt 90 -single_point -output region |
| } |
| rule "moduleCut.ENC.33" { |
| caption "moduleCut.ENC.33: Min enclosure of (large met3 NOT build space) BY areaid:moduleCut < 0.20" |
| enc ( not m3_lrg build_space ) moduleCutArea -lt 0.20 -abut -lt 90 -single_point -output region -exclude_shielded |
| } |
| rule "moduleCut.SP.34" { |
| caption "moduleCut.SP.34: Min spacing of areaid:moduleCut and (large met4 NOT build space) < 0.20" |
| exte moduleCutAREA ( not m4_lrg build_space ) -lt 0.20 -abut -lt 90 -single_point -output region |
| } |
| rule "moduleCut.ENC.34" { |
| caption "moduleCut.ENC.34: Min enclosure of (large met4 NOT build space) BY areaid:moduleCut < 0.20" |
| enc ( not m4_lrg build_space ) moduleCutArea -lt 0.20 -abut -lt 90 -single_point -output region -exclude_shielded |
| } |
| rule "moduleCut.SP.35" { |
| caption "moduleCut.SP.35: Min space of capm BY areaid:moduleCut < 0.42" |
| exte capm moduleCutArea -lt 0.42 -abut -lt 90 -single_point -output region |
| } |
| rule "moduleCut.ENC.35" { |
| caption "moduleCut.ENC.35: Min enclosure of capm BY areaid:moduleCut < 0.42" |
| enc capm moduleCutArea -lt 0.42 -abut -lt 90 -single_point -output region -exclude_shielded |
| } |
| rule "moduleCut.SP.36" { |
| caption "moduleCut.SP.36: Min space of cap2m BY areaid:moduleCut < 0.42" |
| exte cap2m moduleCutArea -lt 0.42 -abut -lt 90 -single_point -output region |
| } |
| rule "moduleCut.ENC.36" { |
| caption "moduleCut.ENC.36: Min enclosure of cap2m BY areaid:moduleCut < 0.42" |
| enc cap2m moduleCutArea -lt 0.42 -abut -lt 90 -single_point -output region -exclude_shielded |
| } |
| rule "moduleCut.SP.37" { |
| caption "moduleCut.SP.37: Min spacing of areaid:moduleCut and (thkox NOT build space) < 0.35" |
| exte moduleCutAREA ( not thkox build_space ) -lt 0.35 -abut -lt 90 -single_point -output region |
| } |
| rule "moduleCut.ENC.37" { |
| caption "moduleCut.ENC.37: Min enclosure of (thkox NOT build space) BY areaid:moduleCut < 0.35" |
| enc ( not thkox build_space ) moduleCutArea -lt 0.35 -abut -lt 90 -single_point -output region -exclude_shielded |
| } |
| |
| |
| // |
| // SEALID checks |
| // |
| |
| |
| |
| rule "sealid.WID.1" { |
| caption "sealid.WID.1: Min width areaid:seal < 6.0" |
| inte SEALID -lt 6.0 -abut -lt 90 -single_point -output region |
| } |
| |
| layer_def quad1_shape 9999 |
| create_polygon 0.000 0.000 0.001 0.001 quad1_shape // create a dummy shape whose south and west edges abut to the x-y axis in quadrant 1 |
| layer_def quad2_shape 9998 |
| create_polygon -0.001 0.000 0.000 0.001 quad2_shape // create a dummy shape whose south and east edges abut to the x-y axis in quadrant 2 |
| layer_def quad3_shape 9997 |
| create_polygon -0.001 -0.001 0.000 0.000 quad3_shape // create a dummy shape whose north and east edges abut to the x-y axis in quadrant 3 |
| layer_def quad4_shape 9996 |
| create_polygon 0.000 -0.001 0.001 0.000 quad4_shape // create a dummy shape whose north and west edges abut to the x-y axis in quadrant 4 |
| extent -layer SEALID -outputlayer SEALIDextent |
| and ( and ( and ( select -enclose SEALIDextent quad1_shape ) ( select -touch SEALIDextent quad2_shape ) ) ( select -touch SEALIDextent quad4_shape ) ) ( select -outside SEALIDextent quad3_shape ) -outputlayer SEALIDextentAtOrigin |
| |
| rule "seal.CON.1" { |
| caption "seal.CON.1: SEAL ring is not at origin (0,0)" |
| not SEALIDextent SEALIDextentAtOrigin |
| } |
| |
| |
| // |
| // SCRIBE checks |
| // |
| |
| |
| |
| and pad ( or FRAMEID moduleCutAREA ) -outputlayer FRAMEPAD |
| select -label FRAMEPAD -textname "e-test" -textlayer padText -outputlayer ETESTPAD |
| select -label FRAMEPAD -textname "u-test" -textlayer padText -outputlayer UTESTPAD |
| select -label FRAMEPAD -textname "RF" -textlayer padText -outputlayer RFTESTPAD |
| or ETESTPAD UTESTPAD RFTESTPAD -outputlayer EUTESTPAD |
| not FRAMEPAD ( or EUTESTPAD laser_targetCells ) -outputlayer FRAMEPADnoTXT |
| or mcon via1 -outputlayer mconOrVia |
| and moduleCutAREA ETESTID -outputlayer ModulecutAndEtest |
| convex_edge dieCut -eq 2 -with_length -ge 150.0 -outputlayer dieCut150 |
| inte dieCut150 -le 150.0 -intersecting ONLY -abut -eq 90 -output positive1 -outputlayer dieCutCorner |
| edge_expand dieCutCorner -inside_by 0.005 -corner_fill -outputlayer dieCutCornerSz |
| edge_expand dieCutCorner -outside_by 150 -corner_fill -outputlayer dieCutCornerSzOut |
| and frameBndr ( not dieCutCornerSzOut ( select -interact dieCut dieCutCornerSz ) ) -outputlayer scribeJunc150 |
| not frameBndr ( select -interact dieCut dieCutCornerSz ) -outputlayer realScribeLine |
| rule "scribe.CON.1" { |
| caption "scribe.CON.1: Wide diff within 150 um of scribe junction" |
| with_width diffi -ge 10.0 -outputlayer wide_diffi |
| and wide_diffi scribeJunc150 |
| } |
| rule "scribe.CON.2" { |
| caption "scribe.CON.2: Wide poly within 150 um of scribe junction" |
| with_width polyi -ge 10.0 -outputlayer wide_polyi |
| and wide_polyi scribeJunc150 |
| } |
| rule "scribe.CON.3" { |
| caption "scribe.CON.3: Wide li within 150 um of scribe junction" |
| with_width li_i -ge 10.0 -outputlayer wide_li_i |
| and wide_li_i scribeJunc150 |
| } |
| rule "scribe.CON.4" { |
| caption "scribe.CON.4: Wide met1 within 150 um of scribe junction" |
| with_width met1i -ge 10.0 -outputlayer wide_met1i |
| and wide_met1i scribeJunc150 |
| } |
| rule "scribe.CON.5" { |
| caption "scribe.CON.5: Wide met2 within 150 um of scribe junction" |
| with_width met2i -ge 10.0 -outputlayer wide_met2i |
| and wide_met2i scribeJunc150 |
| } |
| rule "scribe.CON.6" { |
| caption "scribe.CON.6: Wide met3 within 150 um of scribe junction" |
| with_width met3i -ge 10.0 -outputlayer wide_met3i |
| and wide_met3i scribeJunc150 |
| } |
| rule "scribe.CON.7" { |
| caption "scribe.CON.7: Wide met4 within 150 um of scribe junction" |
| with_width met4i -ge 10.0 -outputlayer wide_met4i |
| and wide_met4i scribeJunc150 |
| } |
| rule "scribe.CON.8" { |
| caption "scribe.CON.8: Wide met5 within 150 um of scribe junction" |
| with_width met5i -ge 10.0 -outputlayer wide_met5i |
| and wide_met5i scribeJunc150 |
| } |
| rule "scribe.CON.9" { |
| caption "scribe.CON.9: Wide mcon within 150 um of scribe junction" |
| with_width mcon -ge 10.0 -outputlayer wide_mcon |
| and wide_mcon scribeJunc150 |
| } |
| rule "scribe.CON.10" { |
| caption "scribe.CON.10: Wide licon within 150 um of scribe junction" |
| with_width licon -ge 10.0 -outputlayer wide_licon |
| and wide_licon scribeJunc150 |
| } |
| rule "scribe.CON.11" { |
| caption "scribe.CON.11: Wide via1 within 150 um of scribe junction" |
| with_width via1 -ge 10.0 -outputlayer wide_via1 |
| and wide_via1 scribeJunc150 |
| } |
| rule "scribe.CON.12" { |
| caption "scribe.CON.12: Wide via2 within 150 um of scribe junction" |
| with_width via2 -ge 10.0 -outputlayer wide_via2 |
| and wide_via2 scribeJunc150 |
| } |
| rule "scribe.CON.13" { |
| caption "scribe.CON.13: Wide via3 within 150 um of scribe junction" |
| with_width via3 -ge 10.0 -outputlayer wide_via3 |
| and wide_via3 scribeJunc150 |
| } |
| rule "scribe.CON.14" { |
| caption "scribe.CON.14: Wide via4 within 150 um of scribe junction" |
| with_width via4 -ge 10.0 -outputlayer wide_via4 |
| and wide_via4 scribeJunc150 |
| } |
| rule "scribe.CON.15" { |
| caption "scribe.CON.15: Wide mm1mk within 150 um of scribe junction" |
| with_width mm1mk -ge 10.0 -outputlayer wide_mm1mk |
| and wide_mm1mk scribeJunc150 |
| } |
| rule "scribe.CON.16" { |
| caption "scribe.CON.16: Wide mm2mk within 150 um of scribe junction" |
| with_width mm2mk -ge 10.0 -outputlayer wide_mm2mk |
| and wide_mm2mk scribeJunc150 |
| } |
| rule "scribe.CON.17" { |
| caption "scribe.CON.17: Wide mm3mk within 150 um of scribe junction" |
| with_width mm3mk -ge 10.0 -outputlayer wide_mm3mk |
| and wide_mm3mk scribeJunc150 |
| } |
| rule "scribe.CON.18" { |
| caption "scribe.CON.18: Wide p1mmk within 150 um of scribe junction" |
| with_width p1mmk -ge 10.0 -outputlayer wide_p1mmk |
| and wide_p1mmk scribeJunc150 |
| } |
| rule "scribe.CON.19" { |
| caption "scribe.CON.19: Wide fommk within 150 um of scribe junction" |
| with_width fommk -ge 10.0 -outputlayer wide_fommk |
| and wide_fommk scribeJunc150 |
| } |
| rule "scribe.CON.20" { |
| caption "scribe.CON.20: Wide ctm1mk within 150 um of scribe junction" |
| with_width ctm1mk -ge 10.0 -outputlayer wide_ctm1mk |
| and wide_ctm1mk scribeJunc150 |
| } |
| rule "scribe.CON.21" { |
| caption "scribe.CON.21: Wide licm1mk within 150 um of scribe junction" |
| with_width licm1mk -ge 10.0 -outputlayer wide_licm1mk |
| and wide_licm1mk scribeJunc150 |
| } |
| rule "scribe.CON.22" { |
| caption "scribe.CON.22: Wide li1mmk within 150 um of scribe junction" |
| with_width li1mmk -ge 10.0 -outputlayer wide_li1mmk |
| and wide_li1mmk scribeJunc150 |
| } |
| rule "scribe.CON.23" { |
| caption "scribe.CON.23: Wide vimmk within 150 um of scribe junction" |
| with_width vimmk -ge 10.0 -outputlayer wide_vimmk |
| and wide_vimmk scribeJunc150 |
| } |
| rule "scribe.CON.24" { |
| caption "scribe.CON.24: Wide vim2mk within 150 um of scribe junction" |
| with_width vim2mk -ge 10.0 -outputlayer wide_vim2mk |
| and wide_vim2mk scribeJunc150 |
| } |
| rule "scribe.CON.25" { |
| caption "scribe.CON.25: Wide mm4mk within 150 um of scribe junction" |
| with_width mm4mk -ge 10.0 -outputlayer wide_mm4mk |
| and wide_mm4mk scribeJunc150 |
| } |
| rule "scribe.CON.26" { |
| caption "scribe.CON.26: Wide mm5mk within 150 um of scribe junction" |
| with_width mm5mk -ge 10.0 -outputlayer wide_mm5mk |
| and wide_mm5mk scribeJunc150 |
| } |
| rule "scribe.CON.27" { |
| caption "scribe.CON.27: Wide vim3mk within 150 um of scribe junction" |
| with_width vim3mk -ge 10.0 -outputlayer wide_vim3mk |
| and wide_vim3mk scribeJunc150 |
| } |
| rule "scribe.CON.28" { |
| caption "scribe.CON.28: Wide vim4mk within 150 um of scribe junction" |
| with_width vim4mk -ge 10.0 -outputlayer wide_vim4mk |
| and wide_vim4mk scribeJunc150 |
| } |
| rule "scribe.WID.1" { |
| caption "scribe.WID.1: Min width of scribe line < 76.0" |
| inte realScribeLine -lt 76.0 -abut -lt 90 -single_point -output region |
| } |
| and ( or pad PDMmk ) realScribeLine -outputlayer padInScribe |
| and padAreaToCheck pad -outputlayer padRing |
| extent_cell "s8Fab_*" "cys8_*" -outputlayer scribe20_xmpt |
| not ( size dieCut -by 13 ) dieCut -outputlayer dieCutSizeLarge |
| not ( size dieCut -by 3 ) dieCut -outputlayer dieCutSizeSmall |
| not dieCutSizeLarge ( or dieCutSizeSmall scribe20_xmpt ) -outputlayer padAreaToCheck |
| rule "scribe.CON.29" { |
| caption "scribe.CON.29: Scribe must not enclose pad scribe protect (drawing nor mask) except for etest pads, die pad rings" |
| not padInScribe ( or padRing moduleCutArea ) |
| } |
| |
| |
| // |
| // CAPM checks |
| // |
| |
| |
| |
| rule "capm.CON.1" { |
| caption "capm.CON.1: ccapm mask should not be used" |
| copy ccapm |
| } |
| rule "capm.CON.2" { |
| caption "capm.CON.2: capm without met3 or met4 is prohibited" |
| not capm met3 |
| not capm met4 |
| } |
| rule "capm.CON.3" { |
| caption "capm.CON.3: capm without via3 is prohibited" |
| select -interact -not capm via3 |
| } |
| rule "capm.WID.1" { |
| caption "capm.WID.1: Min capm width < 1.0" |
| inte capm -lt 1.0 -abut -lt 90 -single_point -output region |
| } |
| rule "capm.SP.1" { |
| caption "capm.SP.1: Min capm space < 0.84" |
| exte capm -lt 0.84 -abut -lt 90 -single_point -output region |
| } |
| rule "capm.SP.2" { |
| caption "capm.SP.2: Min space between capm bottom plates < 1.2" |
| exte m3_bot_plate -lt 1.2 -output region -outputlayer a |
| exte m3_bot_plate met3 -lt 1.2 -output region -outputlayer b |
| select -interact ( or a b ) met3 -gt 1 |
| exte m3_bot_plate -lt 1.2 -abut -lt 90 -single_point -output region -not_connected |
| } |
| rule "capm.ENC.1" { |
| caption "capm.ENC.1: Min enclosure of capm by met3 < 0.14" |
| enc ( and capm met3 ) met3 -lt 0.14 -measure all -abut -lt 90 -single_point -output region |
| } |
| rule "capm.ENC.2" { |
| caption "capm.ENC.2: Min enclosure of via3 by capm < 0.14" |
| enc ( and via3 capm ) capm -lt 0.14 -measure all -abut -lt 90 -single_point -output region |
| } |
| rule "capm.SP.3" { |
| caption "capm.SP.3: Min spacing of capm and via3 < 0.14" |
| exte capm via3 -lt 0.14 -abut -lt 90 -single_point -output region |
| } |
| rule "capm.CON.4" { |
| caption "capm.CON.4: Max capm aspect ratio (L/W) > 20.00" |
| rect_chk capm -aspect -gt 20.00 |
| } |
| rule "capm.CON.5" { |
| caption "capm.CON.5: Only rectangular capm is permitted" |
| rect_chk -not capm |
| } |
| rule "capm.SP.4" { |
| caption "capm.SP.4: Min space of capm to via2 < 0.14" |
| exte capm via2 -lt 0.14 -abut -lt 90 -single_point -output region |
| } |
| rule "capm.SP.5" { |
| caption "capm.SP.5: Min space of capm and met3 not overlapping capm < 0.5" |
| exte capm ( select -interact -not met3 capm ) -lt 0.5 -abut -lt 90 -output region -measure all |
| } |
| rule "capm.CON.6" { |
| caption "capm.CON.6: capm cannot overlap via2" |
| and capm via2 |
| } |
| rule "capm.AR.1" { |
| caption "capm.AR.1: Max area of capm > 10000000.0" |
| area capm -gt 10000000.0 |
| } |
| |
| |
| // |
| // CAP2M checks |
| // |
| |
| |
| |
| rule "cap2m.CON.1" { |
| caption "cap2m.CON.1: cap2m without met4 or met5 is prohibited" |
| not cap2m met4 |
| not cap2m met5 |
| } |
| rule "cap2m.CON.2" { |
| caption "cap2m.CON.2: cap2m without via4 is prohibited" |
| select -interact -not cap2m via4 |
| } |
| rule "cap2m.WID.1" { |
| caption "cap2m.WID.1: Min cap2m width < 1.0" |
| inte cap2m -lt 1.0 -abut -lt 90 -single_point -output region |
| } |
| rule "cap2m.SP.1" { |
| caption "cap2m.SP.1: Min cap2m space < 0.84" |
| exte cap2m -lt 0.84 -abut -lt 90 -single_point -output region |
| } |
| rule "cap2m.SP.2" { |
| caption "cap2m.SP.2: Min space between cap2m bottom plates < 1.2" |
| exte m4_bot_plate -lt 1.2 -abut -lt 90 -single_point -output region -not_connected |
| } |
| rule "cap2m.ENC.1" { |
| caption "cap2m.ENC.1: Min enclosure of cap2m by met4 < 0.14" |
| enc ( and cap2m met4 ) met4 -lt 0.14 -measure all -abut -lt 90 -single_point -output region |
| } |
| rule "cap2m.ENC.2" { |
| caption "cap2m.ENC.2: Min enclosure of via4 by ca2m < 0.20" |
| enc ( and via4 cap2m ) cap2m -lt 0.20 -measure all -abut -lt 90 -single_point -output region |
| } |
| rule "cap2m.SP.3" { |
| caption "cap2m.SP.3: Min spacing of cap2m and via4 < 0.20" |
| exte cap2m via4 -lt 0.20 -abut -lt 90 -single_point -output region |
| } |
| rule "cap2m.CON.3" { |
| caption "cap2m.CON.3: Max cap2m aspect ratio (L/W) > 20.00" |
| rect_chk cap2m -aspect -gt 20.00 |
| } |
| rule "cap2m.CON.4" { |
| caption "cap2m.CON.4: Only rectangular cap2m is permitted" |
| rect_chk -not cap2m |
| } |
| rule "cap2m.SP.4" { |
| caption "cap2m.SP.4: Min space of cap2m to via3 < 0.14" |
| exte cap2m via3 -lt 0.14 -abut -lt 90 -single_point -output region |
| } |
| rule "cap2m.SP.5" { |
| caption "cap2m.SP.5: Min space of cap2m and met4 not overlapping cap2m < 0.5" |
| exte cap2m ( select -interact -not met4 cap2m ) -lt 0.5 -abut -lt 90 -output region -measure all |
| } |
| rule "cap2m.CON.5" { |
| caption "cap2m.CON.5: cap2m cannot overlap via3" |
| and cap2m via3 |
| } |
| rule "cap2m.AR.1" { |
| caption "cap2m.AR.1: Max area of cap2m is 10000000.0" |
| area cap2m -gt 10000000.0 |
| } |
| |
| |
| // |
| // HVTPM checks |
| // |
| |
| |
| |
| select -interact -not nwell ( or v5 v12 v20 ) -outputlayer nw_lv |
| not nw_lv COREID -outputlayer lv_nwell_peri |
| and ( and NTAP poly ) nw_lv -outputlayer varac_channel |
| select -interact nwell varac_channel -outputlayer varac_nwell |
| not nw_lv varac_nwell -outputlayer lv_nwell_not_varac |
| not nw_lv lvtn -outputlayer lv_nwell_not_varac_not_lvtn |
| select -interact nw_lv ( and nw_lv varac_channel ) -outputlayer lv_nwell_over_varac |
| and nw_lv hvtp -outputlayer lv_nwell_over_varac_and_hvtp |
| or lv_nwell_not_varac_not_lvtn lv_nwell_over_varac_and_hvtp -outputlayer clhvtpm_tmp |
| or clhvtpm_tmp chvtpm -outputlayer clhvtpm |
| rule "chvtpm.WID.1" { |
| caption "chvtpm.WID.1: Min width of CLHVTPM < 0.38" |
| inte clhvtpm -lt 0.38 -abut -lt 90 -single_point -output region |
| } |
| rule "chvtpm.SP.1" { |
| caption "chvtpm.SP.1: Min space/notch of CLHVTPM < 0.38" |
| exte clhvtpm -lt 0.38 -abut -lt 90 -single_point -output region |
| } |
| rule "chvtpm.OVL.1" { |
| caption "chvtpm.OVL.1: Min enclosure of low voltage nwell not overlapping varactor channel not lvtn by CLHVTPM is 0" |
| not lv_nwell_not_varac_not_lvtn clhvtpm |
| } |
| rule "chvtpm.OVL.2" { |
| caption "chvtpm.OVL.2: Min enclosure of low voltage nwell not overlapping varactor channel and hvtp by CLHVTPM is 0" |
| not lv_nwell_over_varac_and_hvtp clhvtpm |
| } |
| |
| |
| // |
| // LVTNM checks |
| // |
| |
| |
| |
| and nwell ( or hvtp COREID ) -outputlayer nw_hvtp_core |
| or lvtn nw_hvtp_core lv_nwell_over_varac clvtnm -outputlayer clvtnm_all |
| exte clvtnm_all -lt 0.38 -para ONLY -metric opposite -output region -outputlayer lvtnm_merge |
| or clvtnm_all lvtnm_merge -outputlayer lvtnm_tmp |
| or lvtnm_tmp clvtnm -outputlayer lvtnm_all |
| select -outside lvtnm_all COREID -outputlayer lvtnm_peri |
| rule "clvtnm.WID.1" { |
| caption "clvtnm.WID.1: Min width of clvtnm in periphery < 0.38" |
| inte lvtnm_peri -lt 0.38 -abut -lt 90 -single_point -output region |
| } |
| rule "clvtnm.SP.1" { |
| caption "clvtnm.SP.1: Min space/notch of clvtnm < 0.38" |
| exte lvtnm_peri -lt 0.38 -abut -lt 90 -single_point -output region -para -metric opposite |
| } |
| |
| |
| // |
| // NTM checks |
| // |
| |
| |
| |
| copy nwell -outputlayer nwellTmp |
| // jag changed as thkox is the mask layer not v5 which is only a marker: |
| not thkox COREID -outputlayer v5_tmp |
| copy ldntm -outputlayer ldntm_tmp |
| or NTMdg ( or nwelltmp ( or ldntm_tmp ( or v5_tmp ( or rpm urpm ) ) ) ) -outputlayer ntm_tmp |
| or ntm_tmp ( exte ntm_tmp -lt 0.7 -notch not -metric opposite -para ONLY -output region ) -outputlayer ntm_merged_tmp |
| or ntm_merged_tmp ( exte ntm_merged_tmp -lt 0.7 -notch only -metric opposite -para ONLY -output region ) -outputlayer ntm_merged_tmp2 |
| or ntm_merged_tmp2 ( exte ntm_merged_tmp2 -lt 0.7 -notch only -metric opposite -para ONLY -output region ) -outputlayer ntm_merged |
| copy ntm_merged -outputlayer ntm_all |
| inte ntm_all ( edge_length ntm_all -le 0.0 ) -lt 0.84 -output region -metric opposite -para ONLY -outputlayer ntm_all_0 |
| not ntm_all ( select -outside ntm_all_0 ntm_tmp ) -outputlayer ntm_all_1 |
| copy ntm_all_1 -outputlayer ntm_all_2 |
| inte ntm_all_2 ( edge_length ntm_all_2 -le 0.0 ) -lt 0.84 -output region -metric opposite -para ONLY -outputlayer ntm_all_3 |
| not ntm_all_2 ( select -outside ntm_all_3 ntm_tmp ) -outputlayer ntm_all_4 |
| copy ntm_all_4 -outputlayer ntm_all_5 |
| copy ntm_all_5 -outputlayer clntm_tmp |
| or clntm_tmp NTMdg -outputlayer CLNTM |
| rule "cntm.WID.1" { |
| caption "cntm.WID.1: Min width CLNTM < 0.84" |
| inte CLNTM -lt 0.84 -abut -lt 90 -single_point -output region |
| } |
| rule "cntm.SP.1" { |
| caption "cntm.SP.1: Min space/notch CLNTM < 0.7" |
| exte CLNTM -lt 0.7 -abut -lt 90 -single_point -output region |
| } |
| rule "cntm.ENC.1" { |
| caption "cntm.ENC.1: Layer Nwell must be enclosed by CLNTM" |
| not nwell CLNTM |
| } |
| rule "cntm.ENC.2" { |
| caption "cntm.ENC.2: thkox outside core must be enclosed by CLNTM" |
| not ( not thkox COREID ) CLNTM |
| } |
| rule "cntm.ENC.3" { |
| caption "cntm.ENC.3: ldntm must be enclosed by CLNTM" |
| not ldntm CLNTM |
| } |
| |
| |
| // |
| // RDL checks |
| // |
| |
| |
| |
| rule "rdl.WID.1" { |
| caption "rdl.WID.1: Min width of rdl < 10.0" |
| inte rdl -lt 10.0 -abut -lt 90 -single_point -output region |
| } |
| rule "rdl.SP.1" { |
| caption "rdl.SP.1: Min space of rdl < 10.0" |
| exte rdl -lt 10.0 -output region -corner_edge |
| exte rdl -lt 10.0 -abut -lt 90 -output region -metric opposite -para ONLY |
| } |
| rule "rdl.ENC.1" { |
| caption "rdl.ENC.1: Min enclosure of pad by rdl (outside bump) < 10.75" |
| enc ( and pad ( select -interact -not rdl bump ) ) ( select -interact -not rdl bump ) -lt 10.75 -measure all -abut -lt 90 -single_point -output region |
| } |
| rule "rdl.SP.2" { |
| caption "rdl.SP.2: Min space of rdl to outer edge of scribe line < 15.0" |
| enc rdl ( or sealRing sealHoles ) -lt 15.0 -measure all -abut -lt 90 -single_point -output region |
| } |
| rule "rdl.CON.1" { |
| caption "rdl.CON.1: rdl or ccu1m.mk must not overlap areaid.ft (frame boundary)" |
| not ( and ( or rdl CU1Mmk ) frameBndr ) dieCut |
| } |
| rule "rdl.SP.3" { |
| caption "rdl.SP.3: Min space of rdl (outside bump) and pad < 19.66" |
| exte ( select -interact -not rdl bump ) pad -lt 19.66 -abut -lt 90 -single_point -output region |
| } |
| |
| |
| // |
| // BUMP checks |
| // |
| |
| |
| |
| bbox bump -centers 1.0 -outputlayer bump_ctr |
| exte bump_ctr -eq 399 -abut -lt 90 -metric opposite -para ONLY -output region -outputlayer bump_pitch_400_rect |
| exte bump_ctr -eq 499 -abut -lt 90 -metric opposite -para ONLY -output region -outputlayer bump_pitch_500_rect |
| select -interact bump bump_pitch_400_rect -outputlayer bump_small_pitch |
| or ( select -interact bump bump_pitch_500_rect ) ( select -interact -not bump bump_pitch_400_rect ) -outputlayer bump_large_pitch |
| select -label pad -textname "etest" -textlayer padText -outputlayer ETESTPAD_x |
| rule "bump.CON.1" { |
| caption "bump.CON.1: Bump cannot straddle areaid:ModuleCut" |
| select -cut bump ( select -interact moduleCutAREA ETESTPAD ) |
| } |
| rule "bump.WID.1" { |
| caption "bump.WID.1: Min width of bump ball < 261" |
| inte bump -lt 260.5 -abut -lt 90 -single_point -para ONLY -metric opposite -output region |
| } |
| rule "bump.WID.2" { |
| caption "bump.WID.2: Min width of bump ball for pitch > 400um is < 310" |
| inte bump_large_pitch -lt 309.5 -abut -lt 90 -single_point -para ONLY -metric opposite -output region |
| } |
| rule "bump.SP.1" { |
| caption "bump.SP.1: Min/Max pitch spacing for bump is not 400 or 500" |
| select -interact -not bump ( or bump_pitch_400_rect bump_pitch_500_rect ) |
| } |
| rule "bump.ENC.1" { |
| caption "bump.ENC.1: Min enclosure of bump by scribe_line < 25.0" |
| enc bump ( or SEALID sealHoles ) -lt 25.0 -abut -lt 90 -output region -single_point |
| } |
| rule "bump.CON.2" { |
| caption "bump.CON.2: Min size of chip extent with 500um pitch bumps < 1000" |
| inte ( select -interact sealHoles bump_large_pitch ) -lt 1000 -abut -lt 90 -output region |
| } |
| rule "bump.CON.3" { |
| caption "bump.CON.3: Max size of chip extent with 500um pitch bumps > 6800" |
| rect_chk ( select -interact sealHoles bump_large_pitch ) -gt 6800 |
| } |
| rule "bump.CON.4" { |
| caption "bump.CON.4: Min size of chip extent with 400um pitch bumps < 750 BY 1000" |
| rect_chk ( select -interact sealHoles bump_small_pitch ) -lt 750 -by -lt 1000 |
| } |
| rule "bump.CON.5" { |
| caption "bump.CON.5: Max size of chip extent with 400um pitch bumps > 6800" |
| rect_chk sealHoles -gt 6800 |
| } |
| rule "bump.CON.6" { |
| caption "bump.CON.6: Chip can contain only 400 pitch or 500 pitch bumps but not both" |
| and ( select -interact sealHoles bump_small_pitch ) ( select -interact sealHoles bump_large_pitch ) |
| } |
| |
| |
| // |
| // UBM checks |
| // |
| |
| |
| |
| rule "ubm.CON.1" { |
| caption "ubm.CON.1: ubm drawn layer cannot straddle areaid:ModuleCut layer" |
| select -cut ubm ( select -interact moduleCutAREA ETESTPAD ) |
| } |
| rule "ubm.WID.1" { |
| caption "ubm.WID.1: Min width of ubm on 400 pitch balls (parallel opposite edges) < 215.0" |
| inte ( and ubm bump_small_pitch ) -lt 215.0 -para ONLY -metric opposite |
| } |
| rule "ubm.WID.2" { |
| caption "ubm.WID.2: Min width of ubm on 500 pitch balls (parallel opposite edges) < 250.0" |
| inte ( and ubm bump_large_pitch ) -lt 250.0 -para ONLY -metric opposite |
| } |
| rule "ubm.ENC.1" { |
| caption "ubm.ENC.1: Min enclosure ubm by rdl < 10.0" |
| enc ubm rdl -lt 9.95 -abut -lt 90 -output region -single_point |
| } |
| rule "ubm.CON.2" { |
| caption "ubm.CON.2: ubm must be inside RDL" |
| not ubm rdl |
| } |
| bbox UBM -centers 1 -outputlayer ubm_ctr |
| rule "ubm.SP.1" { |
| caption "ubm.SP.1: Min space between center of 400 pitch UBM to scribe_line < 155.0" |
| enc ( and ubm_ctr bump_small_pitch ) ( or sealHoles SEALID ) -lt 154.5 -abut -lt 90 -output region -single_point |
| } |
| rule "ubm.SP.2" { |
| caption "ubm.SP.2: Min space between center of 500 pitch UBM to scribe_line < 195.0" |
| enc ( and ubm_ctr bump_large_pitch ) ( or sealHoles SEALID ) -lt 194.5 -abut -lt 90 -output region -single_point |
| } |
| |
| |
| // |
| // pwbm checks |
| // |
| |
| |
| |
| and pwbm v20 -outputlayer pwbm_v20 |
| holes pwbm_v20 -outputlayer pwbm_holes |
| or pwbm_v20 pwbm_holes -outputlayer pwbm_or_pwbm_holes |
| rule "pwbm.WID.1" { |
| caption "pwbm.WID.1: Min width of pwbm < 0.84" |
| inte pwbm -lt 0.84 -abut -lt 90 -single_point -output region |
| } |
| rule "pwbm.SP.1" { |
| caption "pwbm.SP.1: Min space/notch of pwbm inside v20 < 1.27" |
| exte pwbm_v20 -lt 1.27 -abut -lt 90 -single_point -output region |
| } |
| rule "pwbm.ENC.1" { |
| caption "pwbm.ENC.1: (dnwell inside v20) must be enclosed by pwbm (exempt for pwbm holes inside dnwell)" |
| not ( and dnwell v20 ) pwbm_or_pwbm_holes |
| } |
| rule "pwbm.SP.2" { |
| caption "pwbm.SP.2: Min spacing of pwbm holes inside v20 < 0.84" |
| exte ( and pwbm_holes v20 ) -lt 0.84 -abut -lt 90 -single_point -output region |
| } |
| rule "pwbm.ENC.2" { |
| caption "pwbm.ENC.2: Min enclosure of dnwell inside v20 by pwbm (exempt for pwbm holes inside dnwell) >= 0" |
| not ( and dnwell v20 ) pwbm_or_pwbm_holes |
| } |
| |
| |
| // |
| // pwde checks |
| // |
| |
| |
| |
| and pwde v20 -outputlayer pwde_v20 |
| exte pwde_v20 -lt 1.27 -abut -lt 90 -single_point -output region -connected -outputlayer pwde_uhvi_samenet |
| rule "pwde.WID.1" { |
| caption "pwde.WID.1: Min width of pwde < 0.84" |
| inte pwde -lt 0.84 -abut -lt 90 -single_point -output region |
| } |
| rule "pwde.SP.1" { |
| caption "pwde.SP.1: Min space of 20v pwde < 1.27" |
| exte pwde_v20 -lt 1.27 -abut -lt 90 -single_point -output region -connected |
| } |
| rule "pwde.ENC.1" { |
| caption "pwde.ENC.1: Layer pwde must be enclosed by v20" |
| not pwde v20 |
| } |
| rule "pwde.ENC.2" { |
| caption "pwde.ENC.2: Layer pwde must be enclosed by pwbm >= 0" |
| not pwde pwbm |
| } |
| rule "pwde.ENC.3" { |
| caption "pwde.ENC.3: Layer pwde must be enclosed by dnwell" |
| not pwde dnwell |
| } |
| rule "pwde.ENC.4" { |
| caption "pwde.ENC.4: Layer pwde enclosure by dnwell in v20 < 1.0" |
| enc pwde_v20 dnwell_v20 -lt 1.0 -measure all -abut -lt 90 -single_point -output region |
| } |
| |
| |
| // |
| // nikon checks |
| // |
| |
| |
| |
| rule "nikon.cfom.CON.1" { |
| caption "nikon.cfom.CON.1: FOMmk in the nikon cross has the wrong polarity" |
| and FOMmk SEALID -outputlayer FOMmk_and_seal |
| select -donut FOMmk_and_seal |
| } |
| rule "nikon.cfom.CON.2" { |
| caption "nikon.cfom.CON.2: FOMmk is missing from the nikon cross in the layout" |
| select -interact SEALID FOMmk -ne 4 |
| } |
| rule "nikon.cdnm.CON.1" { |
| caption "nikon.cdnm.CON.1: DNMmk in the nikon cross has the wrong polarity" |
| and DNMmk SEALID -outputlayer DNMmk_and_seal |
| not DNMmk_and_seal ( select -donut DNMmk_and_seal ) |
| } |
| rule "nikon.cdnm.CON.2" { |
| caption "nikon.cdnm.CON.2: DNMmk is missing from the nikon cross in the layout" |
| select -interact SEALID DNMmk -ne 4 |
| } |
| rule "nikon.cnwm.CON.1" { |
| caption "nikon.cnwm.CON.1: NWMmk in the nikon cross has the wrong polarity" |
| and NWMmk SEALID -outputlayer NWMmk_and_seal |
| select -donut NWMmk_and_seal |
| } |
| rule "nikon.cnwm.CON.2" { |
| caption "nikon.cnwm.CON.2: NWMmk is missing from the nikon cross in the layout" |
| select -interact SEALID NWMmk -ne 4 |
| } |
| rule "nikon.chvtpm.CON.1" { |
| caption "nikon.chvtpm.CON.1: HVTPMmk in the nikon cross has the wrong polarity" |
| and HVTPMmk SEALID -outputlayer HVTPMmk_and_seal |
| select -donut HVTPMmk_and_seal |
| } |
| rule "nikon.chvtpm.CON.2" { |
| caption "nikon.chvtpm.CON.2: HVTPMmk is missing from the nikon cross in the layout" |
| select -interact SEALID HVTPMmk -ne 4 |
| } |
| rule "nikon.clvtnm.CON.1" { |
| caption "nikon.clvtnm.CON.1: LVTNMmk in the nikon cross has the wrong polarity" |
| and LVTNMmk SEALID -outputlayer LVTNMmk_and_seal |
| not LVTNMmk_and_seal ( select -donut LVTNMmk_and_seal ) |
| } |
| rule "nikon.clvtnm.CON.2" { |
| caption "nikon.clvtnm.CON.2: LVTNMmk is missing from the nikon cross in the layout" |
| select -interact SEALID LVTNMmk -ne 4 |
| } |
| rule "nikon.clvom.CON.1" { |
| caption "nikon.clvom.CON.1: LVOMmk in the nikon cross has the wrong polarity" |
| and LVOMmk SEALID -outputlayer LVOMmk_and_seal |
| select -donut LVOMmk_and_seal |
| } |
| rule "nikon.clvom.CON.2" { |
| caption "nikon.clvom.CON.2: LVOMmk is missing from the nikon cross in the layout" |
| select -interact SEALID LVOMmk -ne 4 |
| } |
| rule "nikon.cp1m.CON.1" { |
| caption "nikon.cp1m.CON.1: P1Mmk in the nikon cross has the wrong polarity" |
| and P1Mmk SEALID -outputlayer P1Mmk_and_seal |
| select -donut P1Mmk_and_seal |
| } |
| rule "nikon.cp1m.CON.2" { |
| caption "nikon.cp1m.CON.2: P1Mmk is missing from the nikon cross in the layout" |
| select -interact SEALID P1Mmk -ne 4 |
| } |
| rule "nikon.cntm.CON.1" { |
| caption "nikon.cntm.CON.1: NTMmk in the nikon cross has the wrong polarity" |
| and NTMmk SEALID -outputlayer NTMmk_and_seal |
| select -donut NTMmk_and_seal |
| } |
| rule "nikon.cntm.CON.2" { |
| caption "nikon.cntm.CON.2: NTMmk is missing from the nikon cross in the layout" |
| select -interact SEALID NTMmk -ne 4 |
| } |
| rule "nikon.chvntm.CON.1" { |
| caption "nikon.chvntm.CON.1: HVNTMmk in the nikon cross has the wrong polarity" |
| and HVNTMmk SEALID -outputlayer HVNTMmk_and_seal |
| not HVNTMmk_and_seal ( select -donut HVNTMmk_and_seal ) |
| } |
| rule "nikon.chvntm.CON.2" { |
| caption "nikon.chvntm.CON.2: HVNTMmk is missing from the nikon cross in the layout" |
| select -interact SEALID HVNTMmk -ne 4 |
| } |
| rule "nikon.cldntm.CON.1" { |
| caption "nikon.cldntm.CON.1: LDNTMmk in the nikon cross has the wrong polarity" |
| and LDNTMmk SEALID -outputlayer LDNTMmk_and_seal |
| not LDNTMmk_and_seal ( select -donut LDNTMmk_and_seal ) |
| } |
| rule "nikon.cldntm.CON.2" { |
| caption "nikon.cldntm.CON.2: LDNTMmk is missing from the nikon cross in the layout" |
| select -interact SEALID LDNTMmk -ne 4 |
| } |
| rule "nikon.cnpc.CON.1" { |
| caption "nikon.cnpc.CON.1: NPCMmk in the nikon cross has the wrong polarity" |
| and NPCMmk SEALID -outputlayer NPCMmk_and_seal |
| not NPCMmk_and_seal ( select -donut NPCMmk_and_seal ) |
| } |
| rule "nikon.cnpc.CON.2" { |
| caption "nikon.cnpc.CON.2: NPCMmk is missing from the nikon cross in the layout" |
| select -interact SEALID NPCMmk -ne 4 |
| } |
| rule "nikon.cnsdm.CON.1" { |
| caption "nikon.cnsdm.CON.1: NSDMmk in the nikon cross has the wrong polarity" |
| and NSDMmk SEALID -outputlayer NSDMmk_and_seal |
| select -donut NSDMmk_and_seal |
| } |
| rule "nikon.cnsdm.CON.2" { |
| caption "nikon.cnsdm.CON.2: NSDMmk is missing from the nikon cross in the layout" |
| select -interact SEALID NSDMmk -ne 4 |
| } |
| rule "nikon.cpsdm.CON.1" { |
| caption "nikon.cpsdm.CON.1: PSDMmk in the nikon cross has the wrong polarity" |
| and PSDMmk SEALID -outputlayer PSDMmk_and_seal |
| select -donut PSDMmk_and_seal |
| } |
| rule "nikon.cpsdm.CON.2" { |
| caption "nikon.cpsdm.CON.2: PSDMmk is missing from the nikon cross in the layout" |
| select -interact SEALID PSDMmk -ne 4 |
| } |
| rule "nikon.clicm1.CON.1" { |
| caption "nikon.clicm1.CON.1: LICM1mk in the nikon cross has the wrong polarity" |
| and LICM1mk SEALID -outputlayer LICM1mk_and_seal |
| select -donut LICM1mk_and_seal |
| } |
| rule "nikon.clicm1.CON.2" { |
| caption "nikon.clicm1.CON.2: LICM1mk is missing from the nikon cross in the layout" |
| select -interact SEALID LICM1mk -ne 4 |
| } |
| rule "nikon.cli1m.CON.1" { |
| caption "nikon.cli1m.CON.1: LI1Mmk in the nikon cross has the wrong polarity" |
| and LI1Mmk SEALID -outputlayer LI1Mmk_and_seal |
| select -donut LI1Mmk_and_seal |
| } |
| rule "nikon.cli1m.CON.2" { |
| caption "nikon.cli1m.CON.2: LI1Mmk is missing from the nikon cross in the layout" |
| select -interact SEALID LI1Mmk -ne 4 |
| } |
| rule "nikon.cctm1.CON.1" { |
| caption "nikon.cctm1.CON.1: CTM1mk in the nikon cross has the wrong polarity" |
| and CTM1mk SEALID -outputlayer CTM1mk_and_seal |
| select -donut CTM1mk_and_seal |
| } |
| rule "nikon.cctm1.CON.2" { |
| caption "nikon.cctm1.CON.2: CTM1mk is missing from the nikon cross in the layout" |
| select -interact SEALID CTM1mk -ne 4 |
| } |
| rule "nikon.cmm1.CON.1" { |
| caption "nikon.cmm1.CON.1: MM1mk in the nikon cross has the wrong polarity" |
| and MM1mk SEALID -outputlayer MM1mk_and_seal |
| select -donut MM1mk_and_seal |
| } |
| rule "nikon.cmm1.CON.2" { |
| caption "nikon.cmm1.CON.2: MM1mk is missing from the nikon cross in the layout" |
| select -interact SEALID MM1mk -ne 4 |
| } |
| rule "nikon.cviam.CON.1" { |
| caption "nikon.cviam.CON.1: VIMmk in the nikon cross has the wrong polarity" |
| and VIMmk SEALID -outputlayer VIMmk_and_seal |
| select -donut VIMmk_and_seal |
| } |
| rule "nikon.cviam.CON.2" { |
| caption "nikon.cviam.CON.2: VIMmk is missing from the nikon cross in the layout" |
| select -interact SEALID VIMmk -ne 4 |
| } |
| rule "nikon.cmm2.CON.1" { |
| caption "nikon.cmm2.CON.1: MM2mk in the nikon cross has the wrong polarity" |
| and MM2mk SEALID -outputlayer MM2mk_and_seal |
| select -donut MM2mk_and_seal |
| } |
| rule "nikon.cmm2.CON.2" { |
| caption "nikon.cmm2.CON.2: MM2mk is missing from the nikon cross in the layout" |
| select -interact SEALID MM2mk -ne 4 |
| } |
| rule "nikon.cnsm.CON.1" { |
| caption "nikon.cnsm.CON.1: NSMmk in the nikon cross has the wrong polarity" |
| and NSMmk SEALID -outputlayer NSMmk_and_seal |
| select -donut NSMmk_and_seal |
| } |
| rule "nikon.cnsm.CON.2" { |
| caption "nikon.cnsm.CON.2: NSMmk is missing from the nikon cross in the layout" |
| select -interact SEALID NSMmk -ne 4 |
| } |
| rule "nikon.cpdm.CON.1" { |
| caption "nikon.cpdm.CON.1: PDMmk in the nikon cross has the wrong polarity" |
| and PDMmk SEALID -outputlayer PDMmk_and_seal |
| not PDMmk_and_seal ( select -donut PDMmk_and_seal ) |
| } |
| rule "nikon.cpdm.CON.2" { |
| caption "nikon.cpdm.CON.2: PDMmk is missing from the nikon cross in the layout" |
| select -interact SEALID PDMmk -ne 4 |
| } |
| rule "nikon.cviam2.CON.1" { |
| caption "nikon.cviam2.CON.1: VIM2mk in the nikon cross has the wrong polarity" |
| and VIM2mk SEALID -outputlayer VIM2mk_and_seal |
| select -donut VIM2mk_and_seal |
| } |
| rule "nikon.cviam2.CON.2" { |
| caption "nikon.cviam2.CON.2: VIM2mk is missing from the nikon cross in the layout" |
| select -interact SEALID VIM2mk -ne 4 |
| } |
| rule "nikon.cmm3.CON.1" { |
| caption "nikon.cmm3.CON.1: MM3mk in the nikon cross has the wrong polarity" |
| and MM3mk SEALID -outputlayer MM3mk_and_seal |
| select -donut MM3mk_and_seal |
| } |
| rule "nikon.cmm3.CON.2" { |
| caption "nikon.cmm3.CON.2: MM3mk is missing from the nikon cross in the layout" |
| select -interact SEALID MM3mk -ne 4 |
| } |
| rule "nikon.cviam3.CON.1" { |
| caption "nikon.cviam3.CON.1: VIM3mk in the nikon cross has the wrong polarity" |
| and VIM3mk SEALID -outputlayer VIM3mk_and_seal |
| select -donut VIM3mk_and_seal |
| } |
| rule "nikon.cviam3.CON.2" { |
| caption "nikon.cviam3.CON.2: VIM3mk is missing from the nikon cross in the layout" |
| select -interact SEALID VIM3mk -ne 4 |
| } |
| rule "nikon.cmm4.CON.1" { |
| caption "nikon.cmm4.CON.1: MM4mk in the nikon cross has the wrong polarity" |
| and MM4mk SEALID -outputlayer MM4mk_and_seal |
| select -donut MM4mk_and_seal |
| } |
| rule "nikon.cmm4.CON.2" { |
| caption "nikon.cmm4.CON.2: MM4mk is missing from the nikon cross in the layout" |
| select -interact SEALID MM4mk -ne 4 |
| } |
| rule "nikon.cviam4.CON.1" { |
| caption "nikon.cviam4.CON.1: VIM4mk in the nikon cross has the wrong polarity" |
| and VIM4mk SEALID -outputlayer VIM4mk_and_seal |
| select -donut VIM4mk_and_seal |
| } |
| rule "nikon.cviam4.CON.2" { |
| caption "nikon.cviam4.CON.2: VIM4mk is missing from the nikon cross in the layout" |
| select -interact SEALID VIM4mk -ne 4 |
| } |
| rule "nikon.cmm5.CON.1" { |
| caption "nikon.cmm5.CON.1: MM5mk in the nikon cross has the wrong polarity" |
| and MM5mk SEALID -outputlayer MM5mk_and_seal |
| select -donut MM5mk_and_seal |
| } |
| rule "nikon.cmm5.CON.2" { |
| caption "nikon.cmm5.CON.2: MM5mk is missing from the nikon cross in the layout" |
| select -interact SEALID MM5mk -ne 4 |
| } |
| rule "nikon.crpm.CON.1" { |
| caption "nikon.crpm.CON.1: RPMmk in the nikon cross has the wrong polarity" |
| and RPMmk SEALID -outputlayer RPMmk_and_seal |
| select -donut RPMmk_and_seal |
| } |
| rule "nikon.crpm.CON.2" { |
| caption "nikon.crpm.CON.2: RPMmk is missing from the nikon cross in the layout" |
| select -interact SEALID RPMmk -ne 4 |
| } |
| rule "nikon.CON.3" { |
| caption "nikon.CON.3: Nikon cross cannot be placed outside areaid:seal" |
| not nikon_cross SEALID |
| } |
| |
| |
| // |
| // fuse checks |
| // |
| |
| |
| |
| rule "fuse.CON.1" { |
| caption "fuse.CON.1: Use of the met4/fuse layer is prohibited - contact SkyWater Technology for additional information" |
| copy fuse |
| } |
| rule "target.CON.1" { |
| caption "target.CON.1: Use of the fuse target layer is prohibited - contact SkyWater Technology for additional information" |
| copy target |
| } |
| |
| |
| // |
| // thkox checks |
| // |
| |
| |
| |
| rule "thkox.WID.1" { |
| caption "thkox.WID.1: Min width of thkox outside areaid:core < 0.6" |
| inte ( not thkox COREID ) -lt 0.6 -abut -lt 90 -single_point -output region |
| } |
| rule "thkox.WID.2" { |
| caption "thkox.WID.2: Min width of diff inside thkox in areaid:CORE < 0.15" |
| inte ( and ( and diffi thkox ) COREID ) -lt 0.15 -abut -lt 90 -single_point -output region |
| } |
| rule "thkox.SP.1" { |
| caption "thkox.SP.1: Min space/notch of thkox in periphery < 0.7" |
| exte ( not thkox COREID ) -lt 0.7 -abut -lt 90 -single_point -output region |
| } |
| rule "thkox.OVL.1" { |
| caption "thkox.OVL.1: Layer thkox must not overlap layer tunm" |
| and thkox tunm |
| } |
| rule "thkox.SP.2" { |
| caption "thkox.SP.2: Min spacing of non-butting thkox and nwell < 0.7" |
| edge_boolean -coincident_only -not thkox nwell -outputlayer non_coin_thkox_nwell_edges |
| exte non_coin_thkox_nwell_edges nwell -lt 0.7 -abut -lt 90 -output region |
| } |
| select -interact nwell ( and nwell v20 ) -outputlayer nw_v20 |
| not nwell nw_v20 -outputlayer nw_not_v20 |
| select -interact nw_not_v20 ( and nw_not_v20 v12 ) -outputlayer nw_v12 |
| not nwell ( or nw_v20 nw_v12 ) -outputlayer nw_not_v12_or_v12 |
| select -interact nwell ( and nw_not_v12_or_v12 v5 ) -outputlayer nw_v5 |
| not nwell ( or nw_v20 nw_v12 nw_v5 ) -outputlayer nw_nom |
| |
| // build the 5 volt network starting with v5 markers which can be over nw, diff, ptub, or poly, |
| |
| and nsd v5 -outputlayer nsd_v5 |
| and psd v5 -outputlayer psd_v5 |
| and poly v5 -outputlayer poly_v5 |
| and ptub v5 -outputlayer ptub_v5 |
| |
| // nets connect to v5 nwell |
| antenna nwell nw_v5 -gt 0 -outputlayer v5_net_1a |
| antenna pwell nw_v5 -gt 0 -outputlayer v5_net_1b |
| antenna ptub nw_v5 -gt 0 -outputlayer v5_net_1c |
| antenna nsd nw_v5 -gt 0 -outputlayer v5_net_1d |
| antenna psd nw_v5 -gt 0 -outputlayer v5_net_1e |
| antenna poly nw_v5 -gt 0 -outputlayer v5_net_1f |
| antenna li nw_v5 -gt 0 -outputlayer v5_net_1g |
| antenna met1 nw_v5 -gt 0 -outputlayer v5_net_1h |
| antenna met2 nw_v5 -gt 0 -outputlayer v5_net_1i |
| antenna met3 nw_v5 -gt 0 -outputlayer v5_net_1j |
| antenna met4 nw_v5 -gt 0 -outputlayer v5_net_1k |
| antenna met5 nw_v5 -gt 0 -outputlayer v5_net_1l |
| or v5_net_1a v5_net_1b v5_net_1c v5_net_1d v5_net_1e v5_net_1f v5_net_1g v5_net_1h v5_net_1i v5_net_1j v5_net_1k v5_net_1l -outputlayer v5_net_1 |
| |
| // nets connect to v5 nsd |
| antenna nwell nsd_v5 -gt 0 -outputlayer v5_net_2a |
| antenna pwell nsd_v5 -gt 0 -outputlayer v5_net_2b |
| antenna ptub nsd_v5 -gt 0 -outputlayer v5_net_2c |
| antenna nsd nsd_v5 -gt 0 -outputlayer v5_net_2d |
| antenna psd nsd_v5 -gt 0 -outputlayer v5_net_2e |
| antenna poly nsd_v5 -gt 0 -outputlayer v5_net_2f |
| antenna li nsd_v5 -gt 0 -outputlayer v5_net_2g |
| antenna met1 nsd_v5 -gt 0 -outputlayer v5_net_2h |
| antenna met2 nsd_v5 -gt 0 -outputlayer v5_net_2i |
| antenna met3 nsd_v5 -gt 0 -outputlayer v5_net_2j |
| antenna met4 nsd_v5 -gt 0 -outputlayer v5_net_2k |
| antenna met5 nsd_v5 -gt 0 -outputlayer v5_net_2l |
| or v5_net_2a v5_net_2b v5_net_2c v5_net_2d v5_net_2e v5_net_2f v5_net_2g v5_net_2h v5_net_2i v5_net_2j v5_net_2k v5_net_2l -outputlayer v5_net_2 |
| |
| // nets connect to v5 psd |
| antenna nwell psd_v5 -gt 0 -outputlayer v5_net_3a |
| antenna pwell psd_v5 -gt 0 -outputlayer v5_net_3b |
| antenna ptub psd_v5 -gt 0 -outputlayer v5_net_3c |
| antenna nsd psd_v5 -gt 0 -outputlayer v5_net_3d |
| antenna psd psd_v5 -gt 0 -outputlayer v5_net_3e |
| antenna poly psd_v5 -gt 0 -outputlayer v5_net_3f |
| antenna li psd_v5 -gt 0 -outputlayer v5_net_3g |
| antenna met1 psd_v5 -gt 0 -outputlayer v5_net_3h |
| antenna met2 psd_v5 -gt 0 -outputlayer v5_net_3i |
| antenna met3 psd_v5 -gt 0 -outputlayer v5_net_3j |
| antenna met4 psd_v5 -gt 0 -outputlayer v5_net_3k |
| antenna met5 psd_v5 -gt 0 -outputlayer v5_net_3l |
| or v5_net_3a v5_net_3b v5_net_3c v5_net_3d v5_net_3e v5_net_3f v5_net_3g v5_net_3h v5_net_3i v5_net_3j v5_net_3k v5_net_3l -outputlayer v5_net_3 |
| |
| // nets connect to v5 poly |
| antenna nwell poly_v5 -gt 0 -outputlayer v5_net_4a |
| antenna pwell poly_v5 -gt 0 -outputlayer v5_net_4b |
| antenna ptub poly_v5 -gt 0 -outputlayer v5_net_4c |
| antenna nsd poly_v5 -gt 0 -outputlayer v5_net_4d |
| antenna psd poly_v5 -gt 0 -outputlayer v5_net_4e |
| antenna poly poly_v5 -gt 0 -outputlayer v5_net_4f |
| antenna li poly_v5 -gt 0 -outputlayer v5_net_4g |
| antenna met1 poly_v5 -gt 0 -outputlayer v5_net_4h |
| antenna met2 poly_v5 -gt 0 -outputlayer v5_net_4i |
| antenna met3 poly_v5 -gt 0 -outputlayer v5_net_4j |
| antenna met4 poly_v5 -gt 0 -outputlayer v5_net_4k |
| antenna met5 poly_v5 -gt 0 -outputlayer v5_net_4l |
| or v5_net_4a v5_net_4b v5_net_4c v5_net_4d v5_net_4e v5_net_4f v5_net_4g v5_net_4h v5_net_4i v5_net_4j v5_net_4k v5_net_4l -outputlayer v5_net_4 |
| |
| // nets connect to v5 ptub |
| antenna nwell ptub_v5 -gt 0 -outputlayer v5_net_5a |
| antenna pwell ptub_v5 -gt 0 -outputlayer v5_net_5b |
| antenna ptub ptub_v5 -gt 0 -outputlayer v5_net_5c |
| antenna nsd ptub_v5 -gt 0 -outputlayer v5_net_5d |
| antenna psd ptub_v5 -gt 0 -outputlayer v5_net_5e |
| antenna poly ptub_v5 -gt 0 -outputlayer v5_net_5f |
| antenna li ptub_v5 -gt 0 -outputlayer v5_net_5g |
| antenna met1 ptub_v5 -gt 0 -outputlayer v5_net_5h |
| antenna met2 ptub_v5 -gt 0 -outputlayer v5_net_5i |
| antenna met3 ptub_v5 -gt 0 -outputlayer v5_net_5j |
| antenna met4 ptub_v5 -gt 0 -outputlayer v5_net_5k |
| antenna met5 ptub_v5 -gt 0 -outputlayer v5_net_5l |
| or v5_net_5a v5_net_5b v5_net_5c v5_net_5d v5_net_5e v5_net_5f v5_net_5g v5_net_5h v5_net_5i v5_net_5j v5_net_5k v5_net_5l -outputlayer v5_net_5 |
| |
| or v5_net_1 v5_net_2 v5_net_3 v5_net_4 v5_net_5 -outputlayer v5_net |
| |
| |
| not ( not ( or nsd psd ) ENID ) v5 -outputlayer sd_not_de |
| or v5_net_2 v5_net_3 -outputlayer sd_v5 |
| rule "v5.WID.1" { |
| caption "v5.WID.1: Min width of v5 < 0.02" |
| inte v5 -lt 0.02 -abut -lt 90 -single_point -output region |
| } |
| rule "v5.OVL.1" { |
| caption "v5.OVL.1: Layer v5 must not overlap areaid:core" |
| select -interact v5 ( and v5 COREID ) |
| } |
| rule "v5.OVL.2" { |
| caption "v5.OVL.2: Gate inside v5 must overlap thkox" |
| not ( select -interact ( not ( and poly diff ) ( and npn v5 ) ) v5 ) thkox |
| } |
| rule "v5.OVL.4" { |
| caption "v5.OVL.4: Layer v5 must not straddle v5 src/drn" |
| select -cut ( and sd_v5 diff ) v5 |
| } |
| rule "v5.OVL.5" { |
| caption "v5.OVL.5: Layer v5 must not straddle v5 gate" |
| select -cut ( select -interact ( and poly diff ) v5 ) v5 |
| } |
| rule "v5.OVL.6" { |
| caption "v5.OVL.6: V5 must not straddle nwell" |
| edge_boolean -inside v5 nwell |
| } |
| rule "v5.CON.9" { |
| caption "v5.CON.9: v5 over diff must overlap thkox" |
| not ( and v5 diffi ) thkox |
| } |
| |
| |
| // |
| // V12 checks |
| // |
| |
| |
| |
| // build the 12 v network starting with v12 markers which can be over nw, diff, ptub, or poly |
| and nsd v12 -outputlayer nsd_v12 |
| and psd v12 -outputlayer psd_v12 |
| and poly v12 -outputlayer poly_v12 |
| and ptub v12 -outputlayer ptub_v12 |
| |
| antenna nwell nw_v12 -gt 0 -outputlayer v12_net_1a |
| antenna pwell nw_v12 -gt 0 -outputlayer v12_net_1b |
| antenna ptub nw_v12 -gt 0 -outputlayer v12_net_1c |
| antenna nsd nw_v12 -gt 0 -outputlayer v12_net_1d |
| antenna psd nw_v12 -gt 0 -outputlayer v12_net_1e |
| antenna poly nw_v12 -gt 0 -outputlayer v12_net_1f |
| antenna li nw_v12 -gt 0 -outputlayer v12_net_1g |
| antenna met1 nw_v12 -gt 0 -outputlayer v12_net_1h |
| antenna met2 nw_v12 -gt 0 -outputlayer v12_net_1i |
| antenna met3 nw_v12 -gt 0 -outputlayer v12_net_1j |
| antenna met4 nw_v12 -gt 0 -outputlayer v12_net_1k |
| antenna met5 nw_v12 -gt 0 -outputlayer v12_net_1l |
| or v12_net_1a v12_net_1b v12_net_1c v12_net_1d v12_net_1e v12_net_1f v12_net_1g v12_net_1h v12_net_1i v12_net_1j v12_net_1k v12_net_1l -outputlayer v12_net_1 |
| |
| antenna nwell nsd_v12 -gt 0 -outputlayer v12_net_2a |
| antenna pwell nsd_v12 -gt 0 -outputlayer v12_net_2b |
| antenna ptub nsd_v12 -gt 0 -outputlayer v12_net_2c |
| antenna nsd nsd_v12 -gt 0 -outputlayer v12_net_2d |
| antenna psd nsd_v12 -gt 0 -outputlayer v12_net_2e |
| antenna poly nsd_v12 -gt 0 -outputlayer v12_net_2f |
| antenna li nsd_v12 -gt 0 -outputlayer v12_net_2g |
| antenna met1 nsd_v12 -gt 0 -outputlayer v12_net_2h |
| antenna met2 nsd_v12 -gt 0 -outputlayer v12_net_2i |
| antenna met3 nsd_v12 -gt 0 -outputlayer v12_net_2j |
| antenna met4 nsd_v12 -gt 0 -outputlayer v12_net_2k |
| antenna met5 nsd_v12 -gt 0 -outputlayer v12_net_2l |
| or v12_net_2a v12_net_2b v12_net_2c v12_net_2d v12_net_2e v12_net_2f v12_net_2g v12_net_2h v12_net_2i v12_net_2j v12_net_2k v12_net_2l -outputlayer v12_net_2 |
| |
| antenna nwell psd_v12 -gt 0 -outputlayer v12_net_3a |
| antenna pwell psd_v12 -gt 0 -outputlayer v12_net_3b |
| antenna ptub psd_v12 -gt 0 -outputlayer v12_net_3c |
| antenna nsd psd_v12 -gt 0 -outputlayer v12_net_3d |
| antenna psd psd_v12 -gt 0 -outputlayer v12_net_3e |
| antenna poly psd_v12 -gt 0 -outputlayer v12_net_3f |
| antenna li psd_v12 -gt 0 -outputlayer v12_net_3g |
| antenna met1 psd_v12 -gt 0 -outputlayer v12_net_3h |
| antenna met2 psd_v12 -gt 0 -outputlayer v12_net_3i |
| antenna met3 psd_v12 -gt 0 -outputlayer v12_net_3j |
| antenna met4 psd_v12 -gt 0 -outputlayer v12_net_3k |
| antenna met5 psd_v12 -gt 0 -outputlayer v12_net_3l |
| or v12_net_3a v12_net_3b v12_net_3c v12_net_3d v12_net_3e v12_net_3f v12_net_3g v12_net_3h v12_net_3i v12_net_3j v12_net_3k v12_net_3l -outputlayer v12_net_3 |
| |
| antenna nwell poly_v12 -gt 0 -outputlayer v12_net_4a |
| antenna pwell poly_v12 -gt 0 -outputlayer v12_net_4b |
| antenna ptub poly_v12 -gt 0 -outputlayer v12_net_4c |
| antenna nsd poly_v12 -gt 0 -outputlayer v12_net_4d |
| antenna psd poly_v12 -gt 0 -outputlayer v12_net_4e |
| antenna poly poly_v12 -gt 0 -outputlayer v12_net_4f |
| antenna li poly_v12 -gt 0 -outputlayer v12_net_4g |
| antenna met1 poly_v12 -gt 0 -outputlayer v12_net_4h |
| antenna met2 poly_v12 -gt 0 -outputlayer v12_net_4i |
| antenna met3 poly_v12 -gt 0 -outputlayer v12_net_4j |
| antenna met4 poly_v12 -gt 0 -outputlayer v12_net_4k |
| antenna met5 poly_v12 -gt 0 -outputlayer v12_net_4l |
| or v12_net_4a v12_net_4b v12_net_4c v12_net_4d v12_net_4e v12_net_4f v12_net_4g v12_net_4h v12_net_4i v12_net_4j v12_net_4k v12_net_4l -outputlayer v12_net_4 |
| |
| antenna nwell ptub_v12 -gt 0 -outputlayer v12_net_5a |
| antenna pwell ptub_v12 -gt 0 -outputlayer v12_net_5b |
| antenna ptub ptub_v12 -gt 0 -outputlayer v12_net_5c |
| antenna nsd ptub_v12 -gt 0 -outputlayer v12_net_5d |
| antenna psd ptub_v12 -gt 0 -outputlayer v12_net_5e |
| antenna poly ptub_v12 -gt 0 -outputlayer v12_net_5f |
| antenna li ptub_v12 -gt 0 -outputlayer v12_net_5g |
| antenna met1 ptub_v12 -gt 0 -outputlayer v12_net_5h |
| antenna met2 ptub_v12 -gt 0 -outputlayer v12_net_5i |
| antenna met3 ptub_v12 -gt 0 -outputlayer v12_net_5j |
| antenna met4 ptub_v12 -gt 0 -outputlayer v12_net_5k |
| antenna met5 ptub_v12 -gt 0 -outputlayer v12_net_5l |
| or v12_net_5a v12_net_5b v12_net_5c v12_net_5d v12_net_5e v12_net_5f v12_net_5g v12_net_5h v12_net_5i v12_net_5j v12_net_5k v12_net_5l -outputlayer v12_net_5 |
| |
| |
| or v12_net_2 v12_net_3 -outputlayer sd_v12 |
| rule "v12.CON.1" { |
| caption "v12.CON.1: diff outside areaid:extendedDrain must not be connected to src/drn inside v12" |
| and sd_not_de ( and ( and sd_v12 li ) licon ) |
| } |
| rule "v12.WID.1" { |
| caption "v12.WID.1: Min width of v12 < 0.02" |
| inte v12 -lt 0.02 -abut -lt 90 -single_point -output region |
| } |
| rule "v12.OVL.1" { |
| caption "v12.OVL.1: Layer v12 must not overlap areaid:core" |
| select -interact v12 ( and v12 COREID ) |
| } |
| rule "v12.OVL.2" { |
| caption "v12.OVL.2: A v12 gate must overlap thkox" |
| not ( select -interact ( and poly diff ) v12 ) thkox |
| } |
| rule "v12.OVL.3" { |
| caption "v12.OVL.3: Poly connected to same net as a v12 source/drain must be overlapped by v12" |
| select -interact -not ( and ( or v12_net_3f v12_net_2f ) ( select -interact -not poly polyres ) ) v12 |
| } |
| rule "v12.OVL.4" { |
| caption "v12.OVL.5: Layer v12 must not straddle v12 src/drn (except in V12 extended drain devices)" |
| select -cut ( not v12 ENID ) ( and sd_v12 ( or nsd psd ) ) |
| } |
| rule "v12.OVL.5" { |
| caption "v12.OVL.6: Layer v12 overlapping v12 src/drn must not overlap poly (except in V12 extended drain devices)" |
| and ( select -interact ( not v12 ENID ) sd_v12 ) poly |
| } |
| rule "v12.OVL.6" { |
| caption "v12.OVL.7: Layer v12 must not straddle v12 poly (except in V12 extended drain devices)" |
| select -cut ( select -interact -not v12 ENID ) ( select -interact ( select -inside -not polyi v12 ) v12 ) |
| } |
| rule "v12.CON.6" { |
| caption "v12.CON.6: v12 must not overlap v20" |
| and v12 v20 |
| } |
| rule "v12.CON.9" { |
| caption "v12.CON.9: v12 over diff must overlap thkox" |
| not ( and v12 diffi ) thkox |
| } |
| |
| |
| // |
| // v20 checks |
| // |
| |
| |
| |
| // build the 20 v network starting with v20 markers which can be over nw, diff, ptub or poly |
| and nsd v20 -outputlayer nsd_v20 |
| and psd v20 -outputlayer psd_v20 |
| and poly v20 -outputlayer poly_v20 |
| and ptub v20 -outputlayer ptub_v20 |
| |
| antenna nwell nw_v20 -gt 0 -outputlayer v20_net_1a |
| antenna pwell nw_v20 -gt 0 -outputlayer v20_net_1b |
| antenna ptub nw_v20 -gt 0 -outputlayer v20_net_1c |
| antenna nsd nw_v20 -gt 0 -outputlayer v20_net_1d |
| antenna psd nw_v20 -gt 0 -outputlayer v20_net_1e |
| antenna poly nw_v20 -gt 0 -outputlayer v20_net_1f |
| antenna li nw_v20 -gt 0 -outputlayer v20_net_1g |
| antenna met1 nw_v20 -gt 0 -outputlayer v20_net_1h |
| antenna met2 nw_v20 -gt 0 -outputlayer v20_net_1i |
| antenna met3 nw_v20 -gt 0 -outputlayer v20_net_1j |
| antenna met4 nw_v20 -gt 0 -outputlayer v20_net_1k |
| antenna met5 nw_v20 -gt 0 -outputlayer v20_net_1l |
| or v20_net_1a v20_net_1b v20_net_1c v20_net_1d v20_net_1e v20_net_1f v20_net_1g v20_net_1h v20_net_1i v20_net_1j v20_net_1k v20_net_1l -outputlayer v20_net_1 |
| |
| antenna nwell nsd_v20 -gt 0 -outputlayer v20_net_2a |
| antenna pwell nsd_v20 -gt 0 -outputlayer v20_net_2b |
| antenna ptub nsd_v20 -gt 0 -outputlayer v20_net_2c |
| antenna nsd nsd_v20 -gt 0 -outputlayer v20_net_2d |
| antenna psd nsd_v20 -gt 0 -outputlayer v20_net_2e |
| antenna poly nsd_v20 -gt 0 -outputlayer v20_net_2f |
| antenna li nsd_v20 -gt 0 -outputlayer v20_net_2g |
| antenna met1 nsd_v20 -gt 0 -outputlayer v20_net_2h |
| antenna met2 nsd_v20 -gt 0 -outputlayer v20_net_2i |
| antenna met3 nsd_v20 -gt 0 -outputlayer v20_net_2j |
| antenna met4 nsd_v20 -gt 0 -outputlayer v20_net_2k |
| antenna met5 nsd_v20 -gt 0 -outputlayer v20_net_2l |
| or v20_net_2a v20_net_2b v20_net_2c v20_net_2d v20_net_2e v20_net_2f v20_net_2g v20_net_2h v20_net_2i v20_net_2j v20_net_2k v20_net_2l -outputlayer v20_net_2 |
| |
| antenna nwell psd_v20 -gt 0 -outputlayer v20_net_3a |
| antenna pwell psd_v20 -gt 0 -outputlayer v20_net_3b |
| antenna ptub psd_v20 -gt 0 -outputlayer v20_net_3c |
| antenna nsd psd_v20 -gt 0 -outputlayer v20_net_3d |
| antenna psd psd_v20 -gt 0 -outputlayer v20_net_3e |
| antenna poly psd_v20 -gt 0 -outputlayer v20_net_3f |
| antenna li psd_v20 -gt 0 -outputlayer v20_net_3g |
| antenna met1 psd_v20 -gt 0 -outputlayer v20_net_3h |
| antenna met2 psd_v20 -gt 0 -outputlayer v20_net_3i |
| antenna met3 psd_v20 -gt 0 -outputlayer v20_net_3j |
| antenna met4 psd_v20 -gt 0 -outputlayer v20_net_3k |
| antenna met5 psd_v20 -gt 0 -outputlayer v20_net_3l |
| or v20_net_3a v20_net_3b v20_net_3c v20_net_3d v20_net_3e v20_net_3f v20_net_3g v20_net_3h v20_net_3i v20_net_3j v20_net_3k v20_net_3l -outputlayer v20_net_3 |
| |
| antenna nwell poly_v20 -gt 0 -outputlayer v20_net_4a |
| antenna pwell poly_v20 -gt 0 -outputlayer v20_net_4b |
| antenna ptub poly_v20 -gt 0 -outputlayer v20_net_4c |
| antenna nsd poly_v20 -gt 0 -outputlayer v20_net_4d |
| antenna psd poly_v20 -gt 0 -outputlayer v20_net_4e |
| antenna poly poly_v20 -gt 0 -outputlayer v20_net_4f |
| antenna li poly_v20 -gt 0 -outputlayer v20_net_4g |
| antenna met1 poly_v20 -gt 0 -outputlayer v20_net_4h |
| antenna met2 poly_v20 -gt 0 -outputlayer v20_net_4i |
| antenna met3 poly_v20 -gt 0 -outputlayer v20_net_4j |
| antenna met4 poly_v20 -gt 0 -outputlayer v20_net_4k |
| antenna met5 poly_v20 -gt 0 -outputlayer v20_net_4l |
| or v20_net_4a v20_net_4b v20_net_4c v20_net_4d v20_net_4e v20_net_4f v20_net_4g v20_net_4h v20_net_4i v20_net_4j v20_net_4k v20_net_4l -outputlayer v20_net_4 |
| |
| antenna nwell ptub_v20 -gt 0 -outputlayer v20_net_5a |
| antenna pwell ptub_v20 -gt 0 -outputlayer v20_net_5b |
| antenna ptub ptub_v20 -gt 0 -outputlayer v20_net_5c |
| antenna nsd ptub_v20 -gt 0 -outputlayer v20_net_5d |
| antenna psd ptub_v20 -gt 0 -outputlayer v20_net_5e |
| antenna poly ptub_v20 -gt 0 -outputlayer v20_net_5f |
| antenna li ptub_v20 -gt 0 -outputlayer v20_net_5g |
| antenna met1 ptub_v20 -gt 0 -outputlayer v20_net_5h |
| antenna met2 ptub_v20 -gt 0 -outputlayer v20_net_5i |
| antenna met3 ptub_v20 -gt 0 -outputlayer v20_net_5j |
| antenna met4 ptub_v20 -gt 0 -outputlayer v20_net_5k |
| antenna met5 ptub_v20 -gt 0 -outputlayer v20_net_5l |
| or v20_net_5a v20_net_5b v20_net_5c v20_net_5d v20_net_5e v20_net_5f v20_net_5g v20_net_5h v20_net_5i v20_net_5j v20_net_5k v20_net_5l -outputlayer v20_net_5 |
| |
| or v20_net_1 v20_net_2 v20_net_3 v20_net_4 v20_net_5 -outputlayer v20_net |
| |
| |
| rule "v20.CON.1" { |
| caption "v20.CON.1: diff must not straddle v20" |
| select -cut difftap v20 |
| } |
| rule "v20.CON.2" { |
| caption "v20.CON.2: poly must not straddle v20" |
| select -cut polyi v20 |
| } |
| rule "v20.ENC.1" { |
| caption "v20.ENC.1: pwbm not in areaid:low_vt must be enclosed by v20" |
| not ( not pwbm LOWVTID ) v20 |
| } |
| rule "v20.CON.3" { |
| caption "v20.CON.3: dnwell must not straddle v20" |
| select -cut dnwell v20 |
| } |
| rule "v20.ENC.2" { |
| caption "v20.ENC.2: v20 interacting with dnwell must fully enclose dnwell" |
| not ( select -interact dnwell v20 ) v20 |
| } |
| rule "v20.CON.4" { |
| caption "v20.CON.4: areaid:low_vt must not straddle v20" |
| select -cut LOWVTID v20 |
| } |
| rule "v20.OVL.1" { |
| caption "v20.OVL.1: v20 gate must overlap thkox" |
| not ( select -interact ( and diff poly ) v20 ) thkox |
| } |
| rule "v20.CON.9" { |
| caption "v20.CON.9: v20 over diff must overlap thkox" |
| not ( and v20 diffi ) thkox |
| } |
| |
| |
| // |
| // Stress Checks |
| // |
| |
| |
| rule "stress.CON.8" { |
| caption "stress.CON.8: Layer areaid:notCritSide is an unsupported layer. Contact SkyWater Technologies for more information" |
| copy notCritSideID |
| } |
| #IFNDEF SKIP_STRESS_CHECKS |
| or ( select -donut SEALID ) ( holes SEALID ) -outputlayer chip_area |
| not ( extent ) notCritSideID -outputlayer chipExtNotNcs |
| copy 4000 -outputlayer q0chip_area |
| copy_layer -non_empty chip_area chipExtNotNcs q0chip_area -copy_last -outputlayer critsideNoSl |
| and chip_area critside -outputlayer critsideSl |
| and chip_area ccorner -outputlayer ccornerStree |
| and chip_area deadzoneID -outputlayer deadzone |
| |
| |
| or critsideNoSl critsideSl -outputlayer critsideStress |
| or ( and ( select -interact ( or critsideStress ccornerStree ) SEALID ) chip_area ) critSideNoSl -outputlayer critAreaStress |
| or bondpadCuPillar ( extent_cell "*_logo*" "*_partnum*" "partnum*" "*_trademark*" "*_copy*" "*datecode*" "lazX_*" "lazY_*" "*tech_CD*" "padPLadv*" "padPL*" "*_visid*" "pad_bond*" -original ) -outputlayer exemptCells |
| extent_cell "*_logo*" "*_partnum*" "partnum*" "*_trademark*" "*_copy*" "*datecode*" "lazX_*" "lazY_*" "*tech_CD*" "*_visid*" -original -outputlayer exemptStressCells |
| or ( extent_cell "padPLadv*" "padPL*" "pad_bond*" -original ) bondpadCuPillar -outputlayer padPcells |
| extent_cell "lazX_*" "lazY_*" -original -outputlayer laser_target |
| and ( not deadzone exemptCells ) critAreaStress -outputlayer deadzoneChk |
| select -outside pad ( or SEALID moduleCutAREA fuse FRAMEID laser_target ) -outputlayer BONDPAD2 |
| not critAreaStress exemptStressCells -outputlayer critAreaNoExCells |
| not ccornerStree exemptStressCells -outputlayer ccornerNoExCells |
| not critsideStress exemptStressCells -outputlayer critsideNoExCells |
| or diff ( or tap polyres ) -outputlayer deviceLayers |
| or deviceLayers exemptStressCells -outputlayer exemptLayers |
| select -interact ( and ( and poly critAreaStress ) ( and ( and li critAreaStress ) ( and ( and met1 critAreaStress ) ( and ( and met2 critAreaStress ) ( and ( and met3 critAreaStress ) ( and met4 critAreaStress ) ) ) ) ) ) ( and ( and ( and poly critAreaStress ) ( and ( and li critAreaStress ) ( and ( and met1 critAreaStress ) ( and ( and met2 critAreaStress ) ( and ( and met3 critAreaStress ) ( and met4 critAreaStress ) ) ) ) ) ) critAreaStress ) -outputlayer anchLayersStress |
| and licon anchLayersStress -outputlayer alicon1Stress |
| and mcon anchLayersStress -outputlayer amconStress |
| and via1 anchLayersStress -outputlayer aviaStress |
| and via2 anchLayersStress -outputlayer avia2Stress |
| and via3 anchLayersStress -outputlayer avia3Stress |
| select -outside alicon1 ( or avia3 avia2 avia amcon ) -outputlayer anchlicon1Stress |
| select -outside amcon ( or avia3 avia2 avia alicon1 ) -outputlayer anchmconStress |
| select -outside avia ( or avia3 avia2 amcon alicon1 ) -outputlayer anchviaStress |
| select -outside avia2 ( or avia3 avia amcon alicon1 ) -outputlayer anchvia2Stress |
| select -outside avia3 ( or avia2 avia amcon alicon1 ) -outputlayer anchvia3Stress |
| or alicon1 amcon avia avia2 avia3 -outputlayer acontactsStress |
| or anchlicon1 anchmcon anchvia anchvia2 anchvia3 -outputlayer anchcontactsStress |
| not acontactsStress anchcontactsStress -outputlayer overlapConStress |
| select -enclose ( select -enclose ( select -enclose ( select -enclose ( select -enclose anchLayersStress licon ) mcon ) via1 ) via2 ) via3 -outputlayer anchorTmpStress |
| select -cut poly anchLayersStress -outputlayer falseAnchStress |
| select -outside anchorTmpStress ( or overlapCon falseAnchStress exemptLayers ) -outputlayer anchorStress |
| not ( select -interact met1 ( and met1 critAreaStress ) ) ( or anchorStress ( inside_cell met1ii exemptStressCells ) ) -outputlayer met1OverCA |
| area ( select -interact ( holes met1OverCA -inner -empty ) ( and ( holes met1OverCA -inner -empty ) critAreaStress ) ) -lt 5000 -outputlayer met1Holes |
| or met1Holes met1OverCA -outputlayer filled_met1 |
| with_width filled_met1 -ge 25.0 -outputlayer filled_widemet1 |
| and ( not ( with_width met1Holes -lt 20 ) ( select -interact met1Holes ( and met1Holes met1 ) ) ) filled_widemet1 -outputlayer met1slotAll |
| select -cut met1slotAll padPcells -outputlayer met1slotCutPad |
| or ( not met1slotAll padPcells ) met1slotCutPad -outputlayer met1slot |
| #IFDEF SAVE_CONSTRUCTION_LAYERS |
| rule "keep_met1slotCutPad" { |
| caption "keep: met1slotCutPad" |
| copy met1slotCutPad |
| } |
| rule "keep_met1slot" { |
| caption "keep: met1slot" |
| copy met1slot |
| } |
| rule "keep_met1OverCA" { |
| caption "keep: met1OverCA" |
| copy met1OverCA |
| } |
| #ENDIF |
| not ( select -interact met2 ( and met2 critAreaStress ) ) ( or anchorStress ( inside_cell met2ii exemptStressCells ) ) -outputlayer met2OverCA |
| area ( select -interact ( holes met2OverCA -inner -empty ) ( and ( holes met2OverCA -inner -empty ) critAreaStress ) ) -lt 5000 -outputlayer met2Holes |
| or met2Holes met2OverCA -outputlayer filled_met2 |
| with_width filled_met2 -ge 25.0 -outputlayer filled_widemet2 |
| and ( not ( with_width met2Holes -lt 20 ) ( select -interact met2Holes ( and met2Holes met2 ) ) ) filled_widemet2 -outputlayer met2slotAll |
| select -cut met2slotAll padPcells -outputlayer met2slotCutPad |
| or ( not met2slotAll padPcells ) met2slotCutPad -outputlayer met2slot |
| #IFDEF SAVE_CONSTRUCTION_LAYERS |
| rule "keep_met2slotCutPad" { |
| caption "keep: met2slotCutPad" |
| copy met2slotCutPad |
| } |
| rule "keep_met2slot" { |
| caption "keep: met2slot" |
| copy met2slot |
| } |
| rule "keep_met2OverCA" { |
| caption "keep: met2OverCA" |
| copy met2OverCA |
| } |
| #ENDIF |
| not ( select -interact met3 ( and met3 critAreaStress ) ) ( or anchorStress ( inside_cell met3ii exemptStressCells ) ) -outputlayer met3OverCA |
| area ( select -interact ( holes met3OverCA -inner -empty ) ( and ( holes met3OverCA -inner -empty ) critAreaStress ) ) -lt 5000 -outputlayer met3Holes |
| or met3Holes met3OverCA -outputlayer filled_met3 |
| with_width filled_met3 -ge 25.0 -outputlayer filled_widemet3 |
| and ( not ( with_width met3Holes -lt 20 ) ( select -interact met3Holes ( and met3Holes met3 ) ) ) filled_widemet3 -outputlayer met3slotAll |
| select -cut met3slotAll padPcells -outputlayer met3slotCutPad |
| or ( not met3slotAll padPcells ) met3slotCutPad -outputlayer met3slot |
| #IFDEF SAVE_CONSTRUCTION_LAYERS |
| rule "keep_met3slotCutPad" { |
| caption "keep: met3slotCutPad" |
| copy met3slotCutPad |
| } |
| rule "keep_met3slot" { |
| caption "keep: met3slot" |
| copy met3slot |
| } |
| rule "keep_met3OverCA" { |
| caption "keep: met3OverCA" |
| copy met3OverCA |
| } |
| #ENDIF |
| not ( select -interact met4 ( and met4 critAreaStress ) ) ( or anchorStress ( inside_cell met4ii exemptStressCells ) ) -outputlayer met4OverCA |
| area ( select -interact ( holes met4OverCA -inner -empty ) ( and ( holes met4OverCA -inner -empty ) critAreaStress ) ) -lt 5000 -outputlayer met4Holes |
| or met4Holes met4OverCA -outputlayer filled_met4 |
| with_width filled_met4 -ge 25.0 -outputlayer filled_widemet4 |
| and ( not ( with_width met4Holes -lt 20 ) ( select -interact met4Holes ( and met4Holes met4 ) ) ) filled_widemet4 -outputlayer met4slotAll |
| select -cut met4slotAll padPcells -outputlayer met4slotCutPad |
| or ( not met4slotAll padPcells ) met4slotCutPad -outputlayer met4slot |
| #IFDEF SAVE_CONSTRUCTION_LAYERS |
| rule "keep_met4slotCutPad" { |
| caption "keep: met4slotCutPad" |
| copy met4slotCutPad |
| } |
| rule "keep_met4slot" { |
| caption "keep: met4slot" |
| copy met4slot |
| } |
| rule "keep_met4OverCA" { |
| caption "keep: met4OverCA" |
| copy met4OverCA |
| } |
| #ENDIF |
| not ( select -interact met5 ( and met5 critAreaStress ) ) ( or anchorStress padPcells ( inside_cell met5ii exemptStressCells ) ) -outputlayer met5OverCA |
| area ( select -interact ( holes met5OverCA -inner -empty ) ( and ( holes met5OverCA -inner -empty ) critAreaStress ) ) -lt 5000 -outputlayer met5Holes |
| or met5Holes met5OverCA -outputlayer filled_met5 |
| with_width filled_met5 -ge 25.0 -outputlayer filled_widemet5 |
| and ( not ( with_width met5Holes -lt 20 ) ( select -interact met5Holes ( and met5Holes met5 ) ) ) filled_widemet5 -outputlayer met5slotAll |
| select -cut met5slotAll padPcells -outputlayer met5slotCutPad |
| or ( not met5slotAll padPcells ) met5slotCutPad -outputlayer met5slot |
| #IFDEF SAVE_CONSTRUCTION_LAYERS |
| rule "keep_met5slotCutPad" { |
| caption "keep: met5slotCutPad" |
| copy met5slotCutPad |
| } |
| rule "keep_met5slot" { |
| caption "keep: met5slot" |
| copy met5slot |
| } |
| rule "keep_met5OverCA" { |
| caption "keep: met5OverCA" |
| copy met5OverCA |
| } |
| #ENDIF |
| select -interact met1 deadzoneChk -outputlayer deadmetInit |
| select -interact met2 deadzoneChk -outputlayer q0met2 |
| copy q0met2 -outputlayer q0deadmet |
| select -interact met3 deadzoneChk -outputlayer q0met3 |
| or q0deadmet q0met3 -outputlayer q1deadmet |
| select -interact met4 deadzoneChk -outputlayer q0met4 |
| or q1deadmet q0met4 -outputlayer q2deadmet |
| select -interact met5 deadzoneChk -outputlayer q0met5 |
| or q2deadmet q0met5 -outputlayer q3deadmet |
| copy q3deadmet -outputlayer deadmet_new |
| or deadmetInit deadmet_new -outputlayer deadmet_all |
| not deadmet_all exemptCells -outputlayer deadmetCheck |
| not ( and poly deadzoneChk ) ( or exemptCells anchorStress ) -outputlayer deadpoly |
| and ( with_width ( copy ( not deadmetCheck anchorStress ) -snap 5 ) -lt 8.0 ) deadzoneChk -outputlayer deadmetWidthErr |
| and SEALID ( or ( extent_cell "advSeal_6um*" -original ) ( extent_cell "cuPillarAdvSeal_6um*" -original ) ) -outputlayer SEALID_6um_stress |
| not diff SEALID_6um_stress -outputlayer diffNotSEALID_6um_stress |
| rule "diff.stress.1" { |
| caption "diff.stress.1: diff outside areaid:seal must not overlap areaid:deadZon" |
| and diffNotSEALID_6um_stress deadzoneChk |
| } |
| rule "poly.stress.1" { |
| caption "poly.stress.1: poly not allowed in areaid:deadZon unless poly is within Anchor region" |
| copy deadpoly |
| } |
| rule "met1.stress.WID.1" { |
| caption "met1.stress.WID.1: Min width of met1 in Dead Zone < 8.00" |
| copy ( and deadmetWidthErr met1i ) |
| } |
| rule "met2.stress.WID.1" { |
| caption "met2.stress.WID.1: Min width of met2 in Dead Zone < 8.00" |
| copy ( and deadmetWidthErr met2i ) |
| } |
| rule "met3.stress.WID.1" { |
| caption "met3.stress.WID.1: Min width of met3 in Dead Zone < 8.00" |
| copy ( and deadmetWidthErr met3i ) |
| } |
| rule "met4.stress.WID.1" { |
| caption "met4.stress.WID.1: Min width of met4 in Dead Zone < 8.00" |
| copy ( and deadmetWidthErr met4i ) |
| } |
| rule "met5.stress.WID.1" { |
| caption "met5.stress.WID.1: Min width of met5 in Dead Zone < 8.00" |
| copy ( and deadmetWidthErr met5i ) |
| } |
| select -with_edge met1OverCA ( edge_length met1OverCA -ge 10.0 ) -outputlayer met1GrabEdge |
| and ( and ( with_width met1GrabEdge -ge 5.0 ) critAreaNoExCells ) met1OverCA -outputlayer met1SelectEdgeShapes |
| edge_length met1SelectEdgeShapes -ge 10.0 -outputlayer met1BusReal |
| edge_boolean -coincident_only -not ( edge_boolean -coincident_only -not ( edge_length ( and critAreaStress met1OverCA ) -gt 0 ) met1BusReal ) ( edge_length exemptStressCells -gt 0 ) -outputlayer met1Line |
| rule "met1.stress.SP.1" { |
| caption "met1.stress.SP.1: Min spacing of met1 bus (width >= 5.0 & length >= 10.0) & non-bus met1 < 0.54" |
| exte met1BusReal met1Line -lt 0.54 -abut -eq 0 -output region -para -metric opposite |
| } |
| rule "met1.stress.SP.2" { |
| caption "met1.stress.SP.2: Min spacing of met1 bus (width >= 5.0 & length >= 10.0) < 0.54" |
| exte met1BusReal -lt 0.54 -output region -para -metric opposite |
| } |
| select -with_edge met2OverCA ( edge_length met2OverCA -ge 10.0 ) -outputlayer met2GrabEdge |
| and ( and ( with_width met2GrabEdge -ge 5.0 ) critAreaNoExCells ) met2OverCA -outputlayer met2SelectEdgeShapes |
| edge_length met2SelectEdgeShapes -ge 10.0 -outputlayer met2BusReal |
| edge_boolean -coincident_only -not ( edge_boolean -coincident_only -not ( edge_length ( and critAreaStress met2OverCA ) -gt 0 ) met2BusReal ) ( edge_length exemptStressCells -gt 0 ) -outputlayer met2Line |
| rule "met2.stress.SP.1" { |
| caption "met2.stress.SP.1: Min spacing of met2 bus (width >= 5.0 & length >= 10.0) & non-bus met2 < 0.54" |
| exte met2BusReal met2Line -lt 0.54 -abut -eq 0 -output region -para -metric opposite |
| } |
| rule "met2.stress.SP.2" { |
| caption "met2.stress.SP.2: Min spacing of met2 bus (width >= 5.0 & length >= 10.0) < 0.54" |
| exte met2BusReal -lt 0.54 -output region -para -metric opposite |
| } |
| select -with_edge met3OverCA ( edge_length met3OverCA -ge 10.0 ) -outputlayer met3GrabEdge |
| and ( and ( with_width met3GrabEdge -ge 5.0 ) critAreaNoExCells ) met3OverCA -outputlayer met3SelectEdgeShapes |
| edge_length met3SelectEdgeShapes -ge 10.0 -outputlayer met3BusReal |
| edge_boolean -coincident_only -not ( edge_boolean -coincident_only -not ( edge_length ( and critAreaStress met3OverCA ) -gt 0 ) met3BusReal ) ( edge_length exemptStressCells -gt 0 ) -outputlayer met3Line |
| rule "met3.stress.SP.1" { |
| caption "met3.stress.SP.1: Min spacing of met3 bus (width >= 5.0 & length >= 10.0) & non-bus met3 < 0.54" |
| exte met3BusReal met3Line -lt 0.54 -abut -eq 0 -output region -para -metric opposite |
| } |
| rule "met3.stress.SP.2" { |
| caption "met3.stress.SP.2: Min spacing of met3 bus (width >= 5.0 & length >= 10.0) < 0.54" |
| exte met3BusReal -lt 0.54 -output region -para -metric opposite |
| } |
| select -with_edge met4OverCA ( edge_length met4OverCA -ge 10.0 ) -outputlayer met4GrabEdge |
| and ( and ( with_width met4GrabEdge -ge 5.0 ) critAreaNoExCells ) met4OverCA -outputlayer met4SelectEdgeShapes |
| edge_length met4SelectEdgeShapes -ge 10.0 -outputlayer met4BusReal |
| edge_boolean -coincident_only -not ( edge_boolean -coincident_only -not ( edge_length ( and critAreaStress met4OverCA ) -gt 0 ) met4BusReal ) ( edge_length exemptStressCells -gt 0 ) -outputlayer met4Line |
| rule "met4.stress.SP.1" { |
| caption "met4.stress.SP.1: Min spacing of met4 bus (width >= 5.0 & length >= 10.0) & non-bus met4 < 0.54" |
| exte met4BusReal met4Line -lt 0.54 -abut -eq 0 -output region -para -metric opposite |
| } |
| rule "met4.stress.SP.2" { |
| caption "met4.stress.SP.2: Min spacing of met4 bus (width >= 5.0 & length >= 10.0) < 0.54" |
| exte met4BusReal -lt 0.54 -output region -para -metric opposite |
| } |
| select -with_edge met5OverCA ( edge_length met5OverCA -ge 10.0 ) -outputlayer met5GrabEdge |
| and ( and ( with_width met5GrabEdge -ge 5.0 ) critAreaNoExCells ) met5OverCA -outputlayer met5SelectEdgeShapes |
| edge_length met5SelectEdgeShapes -ge 10.0 -outputlayer met5BusReal |
| edge_boolean -coincident_only -not ( edge_boolean -coincident_only -not ( edge_length ( and critAreaStress met5OverCA ) -gt 0 ) met5BusReal ) ( edge_length exemptStressCells -gt 0 ) -outputlayer met5Line |
| rule "met5.stress.SP.1" { |
| caption "met5.stress.SP.1: Min spacing of met5 bus (width >= 5.0 & length >= 10.0) & non-bus met5 < 0.54" |
| exte met5BusReal met5Line -lt 0.54 -abut -eq 0 -output region -para -metric opposite |
| } |
| rule "met5.stress.SP.2" { |
| caption "met5.stress.SP.2: Min spacing of met5 bus (width >= 5.0 & length >= 10.0) < 0.54" |
| exte met5BusReal -lt 0.54 -output region -para -metric opposite |
| } |
| copy mcon -outputlayer via0 |
| copy met1 -outputlayer met0 |
| copy via1 -outputlayer via1x |
| and ( select -interact ( or critside ccorner ) SEALID ) ( or SEALID ( holes SEALID ) ) -outputlayer stress9Reg |
| and via0 met0 -outputlayer met1lowerLevelContact |
| and via1x met2 -outputlayer met1upperLevelContact |
| not ( and stress9Reg met1OverCA ) exemptStressCells -outputlayer met1OverCA_9 |
| and met1OverCA_9 ( select -interact -not met1 ( or met1lowerLevelContact met1upperLevelContact ) ) -outputlayer met1_LinesStandAlone |
| or ( exte met1_LinesStandAlone -le 10.0 -output region ) met1_LinesStandAlone -outputlayer met1_LinesSA_group |
| not met1OverCA_9 met1_LinesStandAlone -outputlayer met1OverCAnotSA |
| size met1OverCAnotSA -by 10 -inside_of stress9Reg -step 0.1 -outputlayer met1_err_stress_9 |
| and ( select -interact -not met1_LinesSA_group met1_err_stress_9 ) critAreaNoExCells -outputlayer met1_err_stress_9final |
| rule "met1.stress.SP.3" { |
| caption "met1.stress.SP.3: Max spacing between standalone and non-standalone met1 in critical corner/side area = 10.0 um" |
| copy met1_err_stress_9final |
| } |
| and via1x met1 -outputlayer met2lowerLevelContact |
| and via2 met3 -outputlayer met2upperLevelContact |
| not ( and stress9Reg met2OverCA ) exemptStressCells -outputlayer met2OverCA_9 |
| and met2OverCA_9 ( select -interact -not met2 ( or met2lowerLevelContact met2upperLevelContact ) ) -outputlayer met2_LinesStandAlone |
| or ( exte met2_LinesStandAlone -le 10.0 -output region ) met2_LinesStandAlone -outputlayer met2_LinesSA_group |
| not met2OverCA_9 met2_LinesStandAlone -outputlayer met2OverCAnotSA |
| size met2OverCAnotSA -by 10 -inside_of stress9Reg -step 0.1 -outputlayer met2_err_stress_9 |
| and ( select -interact -not met2_LinesSA_group met2_err_stress_9 ) critAreaNoExCells -outputlayer met2_err_stress_9final |
| rule "met2.stress.SP.3" { |
| caption "met2.stress.SP.3: Max spacing between standalone and non-standalone met2 in critical corner/side area = 10.0 um" |
| copy met2_err_stress_9final |
| } |
| and via2 met2 -outputlayer met3lowerLevelContact |
| and via3 met4 -outputlayer met3upperLevelContact |
| not ( and stress9Reg met3OverCA ) exemptStressCells -outputlayer met3OverCA_9 |
| and met3OverCA_9 ( select -interact -not met3 ( or met3lowerLevelContact met3upperLevelContact ) ) -outputlayer met3_LinesStandAlone |
| or ( exte met3_LinesStandAlone -le 10.0 -output region ) met3_LinesStandAlone -outputlayer met3_LinesSA_group |
| not met3OverCA_9 met3_LinesStandAlone -outputlayer met3OverCAnotSA |
| size met3OverCAnotSA -by 10 -inside_of stress9Reg -step 0.1 -outputlayer met3_err_stress_9 |
| and ( select -interact -not met3_LinesSA_group met3_err_stress_9 ) critAreaNoExCells -outputlayer met3_err_stress_9final |
| rule "met3.stress.SP.3" { |
| caption "met3.stress.SP.3: Max spacing between standalone and non-standalone met3 in critical corner/side area = 10.0 um" |
| copy met3_err_stress_9final |
| } |
| and via3 met3 -outputlayer met4lowerLevelContact |
| and via4 met5 -outputlayer met4upperLevelContact |
| not ( and stress9Reg met4OverCA ) exemptStressCells -outputlayer met4OverCA_9 |
| and met4OverCA_9 ( select -interact -not met4 ( or met4lowerLevelContact met4upperLevelContact ) ) -outputlayer met4_LinesStandAlone |
| or ( exte met4_LinesStandAlone -le 10.0 -output region ) met4_LinesStandAlone -outputlayer met4_LinesSA_group |
| not met4OverCA_9 met4_LinesStandAlone -outputlayer met4OverCAnotSA |
| size met4OverCAnotSA -by 10 -inside_of stress9Reg -step 0.1 -outputlayer met4_err_stress_9 |
| and ( select -interact -not met4_LinesSA_group met4_err_stress_9 ) critAreaNoExCells -outputlayer met4_err_stress_9final |
| rule "met4.stress.SP.3" { |
| caption "met4.stress.SP.3: Max spacing between standalone and non-standalone met4 in critical corner/side area = 10.0 um" |
| copy met4_err_stress_9final |
| } |
| and via4 met4 -outputlayer met5lowerLevelContact |
| and via4 met5 -outputlayer met5upperLevelContact |
| not ( and stress9Reg met5OverCA ) exemptStressCells -outputlayer met5OverCA_9 |
| and met5OverCA_9 ( select -interact -not met5 ( or met5lowerLevelContact met5upperLevelContact ) ) -outputlayer met5_LinesStandAlone |
| or ( exte met5_LinesStandAlone -le 10.0 -output region ) met5_LinesStandAlone -outputlayer met5_LinesSA_group |
| not met5OverCA_9 met5_LinesStandAlone -outputlayer met5OverCAnotSA |
| size met5OverCAnotSA -by 10 -inside_of stress9Reg -step 0.1 -outputlayer met5_err_stress_9 |
| and ( select -interact -not met5_LinesSA_group met5_err_stress_9 ) critAreaNoExCells -outputlayer met5_err_stress_9final |
| rule "met5.stress.SP.3" { |
| caption "met5.stress.SP.3: Max spacing between standalone and non-standalone met5 in critical corner/side area = 10.0 um" |
| copy met5_err_stress_9final |
| } |
| or met1OverCA ( and met1 padPcells ) -outputlayer met1Inner90DegCornerTmp |
| exte met1Inner90DegCornerTmp -lt 0.005 -abut -ltgt 89.9 90.1 -single_point -output region -outputlayer met1Inner90DegCorner |
| select -interact -not met1Inner90DegCorner met1slot -outputlayer met1Inner90DegCorNoSlot |
| with_width met1OverCA -ge 5.0 -outputlayer met1Bus |
| size ( and ( select -touch met1Inner90DegCorNoSlot met1Bus ) critsideNoExCells ) -by "(10 * 0.005)" -outputlayer met1BusInner90Deg_errCS |
| size ( and met1Inner90DegCorNoSlot ccornerNoExCells ) -by "(10 * 0.005)" -outputlayer met1Inner90Deg_errCC |
| rule "met1.stress.CON.1" { |
| caption "met1.stress.CON.1: 90-degree bend of inner side of 5um wide met1 in areaid:critSid are prohibited" |
| copy met1BusInner90Deg_errCS |
| } |
| rule "met1.stress.CON.2" { |
| caption "met1.stress.CON.2: 90-degree bends of inner side of met1 in areaid:critCorner are probited" |
| copy met1Inner90Deg_errCC |
| } |
| or met2OverCA ( and met2 padPcells ) -outputlayer met2Inner90DegCornerTmp |
| exte met2Inner90DegCornerTmp -lt 0.005 -abut -ltgt 89.9 90.1 -single_point -output region -outputlayer met2Inner90DegCorner |
| select -interact -not met2Inner90DegCorner met2slot -outputlayer met2Inner90DegCorNoSlot |
| with_width met2OverCA -ge 5.0 -outputlayer met2Bus |
| size ( and ( select -touch met2Inner90DegCorNoSlot met2Bus ) critsideNoExCells ) -by "(10 * 0.005)" -outputlayer met2BusInner90Deg_errCS |
| size ( and met2Inner90DegCorNoSlot ccornerNoExCells ) -by "(10 * 0.005)" -outputlayer met2Inner90Deg_errCC |
| rule "met2.stress.CON.1" { |
| caption "met2.stress.CON.1: 90-degree bend of inner side of 5um wide met2 in areaid:critSid are prohibited" |
| copy met2BusInner90Deg_errCS |
| } |
| rule "met2.stress.CON.2" { |
| caption "met2.stress.CON.2: 90-degree bends of inner side of met2 in areaid:critCorner are probited" |
| copy met2Inner90Deg_errCC |
| } |
| or met3OverCA ( and met3 padPcells ) -outputlayer met3Inner90DegCornerTmp |
| exte met3Inner90DegCornerTmp -lt 0.005 -abut -ltgt 89.9 90.1 -single_point -output region -outputlayer met3Inner90DegCorner |
| select -interact -not met3Inner90DegCorner met3slot -outputlayer met3Inner90DegCorNoSlot |
| with_width met3OverCA -ge 5.0 -outputlayer met3Bus |
| size ( and ( select -touch met3Inner90DegCorNoSlot met3Bus ) critsideNoExCells ) -by "(10 * 0.005)" -outputlayer met3BusInner90Deg_errCS |
| size ( and met3Inner90DegCorNoSlot ccornerNoExCells ) -by "(10 * 0.005)" -outputlayer met3Inner90Deg_errCC |
| rule "met3.stress.CON.1" { |
| caption "met3.stress.CON.1: 90-degree bend of inner side of 5um wide met3 in areaid:critSid are prohibited" |
| copy met3BusInner90Deg_errCS |
| } |
| rule "met3.stress.CON.2" { |
| caption "met3.stress.CON.2: 90-degree bends of inner side of met3 in areaid:critCorner are probited" |
| copy met3Inner90Deg_errCC |
| } |
| or met4OverCA ( and met4 padPcells ) -outputlayer met4Inner90DegCornerTmp |
| exte met4Inner90DegCornerTmp -lt 0.005 -abut -ltgt 89.9 90.1 -single_point -output region -outputlayer met4Inner90DegCorner |
| select -interact -not met4Inner90DegCorner met4slot -outputlayer met4Inner90DegCorNoSlot |
| with_width met4OverCA -ge 5.0 -outputlayer met4Bus |
| size ( and ( select -touch met4Inner90DegCorNoSlot met4Bus ) critsideNoExCells ) -by "(10 * 0.005)" -outputlayer met4BusInner90Deg_errCS |
| size ( and met4Inner90DegCorNoSlot ccornerNoExCells ) -by "(10 * 0.005)" -outputlayer met4Inner90Deg_errCC |
| rule "met4.stress.CON.1" { |
| caption "met4.stress.CON.1: 90-degree bend of inner side of 5um wide met4 in areaid:critSid are prohibited" |
| copy met4BusInner90Deg_errCS |
| } |
| rule "met4.stress.CON.2" { |
| caption "met4.stress.CON.2: 90-degree bends of inner side of met4 in areaid:critCorner are probited" |
| copy met4Inner90Deg_errCC |
| } |
| or met5OverCA ( and met5 padPcells ) -outputlayer met5Inner90DegCornerTmp |
| exte met5Inner90DegCornerTmp -lt 0.005 -abut -ltgt 89.9 90.1 -single_point -output region -outputlayer met5Inner90DegCorner |
| select -interact -not met5Inner90DegCorner met5slot -outputlayer met5Inner90DegCorNoSlot |
| with_width met5OverCA -ge 5.0 -outputlayer met5Bus |
| size ( and ( select -touch met5Inner90DegCorNoSlot met5Bus ) critsideNoExCells ) -by "(10 * 0.005)" -outputlayer met5BusInner90Deg_errCS |
| size ( and met5Inner90DegCorNoSlot ccornerNoExCells ) -by "(10 * 0.005)" -outputlayer met5Inner90Deg_errCC |
| rule "met5.stress.CON.1" { |
| caption "met5.stress.CON.1: 90-degree bend of inner side of 5um wide met5 in areaid:critSid are prohibited" |
| copy met5BusInner90Deg_errCS |
| } |
| rule "met5.stress.CON.2" { |
| caption "met5.stress.CON.2: 90-degree bends of inner side of met5 in areaid:critCorner are probited" |
| copy met5Inner90Deg_errCC |
| } |
| not met1OverCA ( inte met1OverCA -ltgt 0 5.0 -metric opposite -obtuse ALSO -output region ) -outputlayer met1Bus5_tmp |
| not met1Bus5_tmp ( with_width met1Bus5_tmp -lt 5.0 ) -outputlayer met1Bus5 |
| inte met1OverCA -ltge 1.0 5.0 -metric opposite -obtuse ALSO -output region -outputlayer met1Bus1_5_tmp |
| with_width ( and met1Bus1_5_tmp met1OverCA ) -ltge 1.0 5.0 -outputlayer met1Bus1_5_tmp1 |
| copy met1Bus1_5_tmp1 -outputlayer met1Bus1_5 |
| with_width met1OverCA -lt 1.0 -outputlayer met1Busless1 |
| edge_boolean -outside ( convex_edge met1OverCA -angle1 -eq 225 -angle2 -eq 225 ) met1Holes -outputlayer met1_Turn225_225_Edge_tmp1 |
| edge_expand met1_Turn225_225_Edge_tmp1 -inside_by 0.005 -extend_by "(10.0 * 0.005)" -outputlayer met1_Turn225_225_EdgeSz_tmp1 |
| select -inside met1_Turn225_225_EdgeSz_tmp1 met1OverCA -outputlayer met1_Turn225_225_EdgeSz_tmp2 |
| edge_boolean -coincident_only met1_Turn225_225_Edge_tmp1 met1_Turn225_225_EdgeSz_tmp2 -outputlayer met1_Turn225_225_Edge |
| edge_expand ( edge_length met1_Turn225_225_Edge -lt 5.0 ) -inside_by 0.005 -extend_by "(10.0 * 0.005)" -outputlayer met1_Turn225_225_Edgeless5 |
| edge_expand ( edge_length met1_Turn225_225_Edge -lt 1.0 ) -inside_by 0.005 -extend_by "(10.0 * 0.005)" -outputlayer met1_Turn225_225_Edgeless1 |
| edge_expand ( edge_length met1_Turn225_225_Edge -lt 0.17 ) -inside_by 0.005 -extend_by "(10.0 * 0.005)" -outputlayer met1_Turn225_225_Edgeless05 |
| and ( not ( select -interact met1_Turn225_225_Edgeless5 ( and met1_Turn225_225_Edgeless5 met1Bus5 ) ) ( select -interact met1_Turn225_225_Edgeless5 ( and met1_Turn225_225_Edgeless5 ( or met1Bus1_5 met1Busless1 ) ) ) ) critAreaNoExCells -outputlayer met1_TurnLen_bus5Err |
| and ( not ( select -interact met1_Turn225_225_Edgeless1 ( and met1_Turn225_225_Edgeless1 met1Bus1_5 ) ) ( select -interact met1_Turn225_225_Edgeless1 ( and met1_Turn225_225_Edgeless1 met1Busless1 ) ) ) ccornerNoExCells -outputlayer met1_TurnLen_bus1_5Err |
| and ( select -interact met1_Turn225_225_Edgeless05 ( and met1_Turn225_225_Edgeless05 met1Busless1 ) ) ccornerNoExCells -outputlayer met1_TurnLen_busless1Err |
| rule "met1.stress.CON.3" { |
| caption "met1.stress.CON.3: Min inner 45-degree edge length for met1 >= 5.00um wide inside areaid:critCorner area < 5.0" |
| copy met1_TurnLen_bus5Err |
| } |
| rule "met1.stress.CON.4" { |
| caption "met1.stress.CON.4: Min inner 45-degree edge length for met1 > 1.00um & < 5.00um wide inside areaid:critCorner area < 1.0" |
| copy met1_TurnLen_bus1_5Err |
| } |
| rule "met1.stress.CON.5" { |
| caption "met1.stress.CON.5: Min inner 45-degree edge length for met1 < 1.00um wide inside areaid:critCorner < 0.17" |
| copy met1_TurnLen_busless1Err |
| } |
| not met2OverCA ( inte met2OverCA -ltgt 0 5.0 -metric opposite -obtuse ALSO -output region ) -outputlayer met2Bus5_tmp |
| not met2Bus5_tmp ( with_width met2Bus5_tmp -lt 5.0 ) -outputlayer met2Bus5 |
| inte met2OverCA -ltge 1.0 5.0 -metric opposite -obtuse ALSO -output region -outputlayer met2Bus1_5_tmp |
| with_width ( and met2Bus1_5_tmp met2OverCA ) -ltge 1.0 5.0 -outputlayer met2Bus1_5_tmp1 |
| copy met2Bus1_5_tmp1 -outputlayer met2Bus1_5 |
| with_width met2OverCA -lt 1.0 -outputlayer met2Busless1 |
| edge_boolean -outside ( convex_edge met2OverCA -angle1 -eq 225 -angle2 -eq 225 ) met2Holes -outputlayer met2_Turn225_225_Edge_tmp1 |
| edge_expand met2_Turn225_225_Edge_tmp1 -inside_by 0.005 -extend_by "(10.0 * 0.005)" -outputlayer met2_Turn225_225_EdgeSz_tmp1 |
| select -inside met2_Turn225_225_EdgeSz_tmp1 met2OverCA -outputlayer met2_Turn225_225_EdgeSz_tmp2 |
| edge_boolean -coincident_only met2_Turn225_225_Edge_tmp1 met2_Turn225_225_EdgeSz_tmp2 -outputlayer met2_Turn225_225_Edge |
| edge_expand ( edge_length met2_Turn225_225_Edge -lt 5.0 ) -inside_by 0.005 -extend_by "(10.0 * 0.005)" -outputlayer met2_Turn225_225_Edgeless5 |
| edge_expand ( edge_length met2_Turn225_225_Edge -lt 1.0 ) -inside_by 0.005 -extend_by "(10.0 * 0.005)" -outputlayer met2_Turn225_225_Edgeless1 |
| edge_expand ( edge_length met2_Turn225_225_Edge -lt 0.17 ) -inside_by 0.005 -extend_by "(10.0 * 0.005)" -outputlayer met2_Turn225_225_Edgeless05 |
| and ( not ( select -interact met2_Turn225_225_Edgeless5 ( and met2_Turn225_225_Edgeless5 met2Bus5 ) ) ( select -interact met2_Turn225_225_Edgeless5 ( and met2_Turn225_225_Edgeless5 ( or met2Bus1_5 met2Busless1 ) ) ) ) critAreaNoExCells -outputlayer met2_TurnLen_bus5Err |
| and ( not ( select -interact met2_Turn225_225_Edgeless1 ( and met2_Turn225_225_Edgeless1 met2Bus1_5 ) ) ( select -interact met2_Turn225_225_Edgeless1 ( and met2_Turn225_225_Edgeless1 met2Busless1 ) ) ) ccornerNoExCells -outputlayer met2_TurnLen_bus1_5Err |
| and ( select -interact met2_Turn225_225_Edgeless05 ( and met2_Turn225_225_Edgeless05 met2Busless1 ) ) ccornerNoExCells -outputlayer met2_TurnLen_busless1Err |
| rule "met2.stress.CON.3" { |
| caption "met2.stress.CON.3: Min inner 45-degree edge length for met2 >= 5.00um wide inside areaid:critCorner area < 5.0" |
| copy met2_TurnLen_bus5Err |
| } |
| rule "met2.stress.CON.4" { |
| caption "met2.stress.CON.4: Min inner 45-degree edge length for met2 > 1.00um & < 5.00um wide inside areaid:critCorner area < 1.0" |
| copy met2_TurnLen_bus1_5Err |
| } |
| rule "met2.stress.CON.5" { |
| caption "met2.stress.CON.5: Min inner 45-degree edge length for met2 < 1.00um wide inside areaid:critCorner < 0.17" |
| copy met2_TurnLen_busless1Err |
| } |
| not met3OverCA ( inte met3OverCA -ltgt 0 5.0 -metric opposite -obtuse ALSO -output region ) -outputlayer met3Bus5_tmp |
| not met3Bus5_tmp ( with_width met3Bus5_tmp -lt 5.0 ) -outputlayer met3Bus5 |
| inte met3OverCA -ltge 1.0 5.0 -metric opposite -obtuse ALSO -output region -outputlayer met3Bus1_5_tmp |
| with_width ( and met3Bus1_5_tmp met3OverCA ) -ltge 1.0 5.0 -outputlayer met3Bus1_5_tmp1 |
| copy met3Bus1_5_tmp1 -outputlayer met3Bus1_5 |
| with_width met3OverCA -lt 1.0 -outputlayer met3Busless1 |
| edge_boolean -outside ( convex_edge met3OverCA -angle1 -eq 225 -angle2 -eq 225 ) met3Holes -outputlayer met3_Turn225_225_Edge_tmp1 |
| edge_expand met3_Turn225_225_Edge_tmp1 -inside_by 0.005 -extend_by "(10.0 * 0.005)" -outputlayer met3_Turn225_225_EdgeSz_tmp1 |
| select -inside met3_Turn225_225_EdgeSz_tmp1 met3OverCA -outputlayer met3_Turn225_225_EdgeSz_tmp2 |
| edge_boolean -coincident_only met3_Turn225_225_Edge_tmp1 met3_Turn225_225_EdgeSz_tmp2 -outputlayer met3_Turn225_225_Edge |
| edge_expand ( edge_length met3_Turn225_225_Edge -lt 5.0 ) -inside_by 0.005 -extend_by "(10.0 * 0.005)" -outputlayer met3_Turn225_225_Edgeless5 |
| edge_expand ( edge_length met3_Turn225_225_Edge -lt 1.0 ) -inside_by 0.005 -extend_by "(10.0 * 0.005)" -outputlayer met3_Turn225_225_Edgeless1 |
| edge_expand ( edge_length met3_Turn225_225_Edge -lt 0.17 ) -inside_by 0.005 -extend_by "(10.0 * 0.005)" -outputlayer met3_Turn225_225_Edgeless05 |
| and ( not ( select -interact met3_Turn225_225_Edgeless5 ( and met3_Turn225_225_Edgeless5 met3Bus5 ) ) ( select -interact met3_Turn225_225_Edgeless5 ( and met3_Turn225_225_Edgeless5 ( or met3Bus1_5 met3Busless1 ) ) ) ) critAreaNoExCells -outputlayer met3_TurnLen_bus5Err |
| and ( not ( select -interact met3_Turn225_225_Edgeless1 ( and met3_Turn225_225_Edgeless1 met3Bus1_5 ) ) ( select -interact met3_Turn225_225_Edgeless1 ( and met3_Turn225_225_Edgeless1 met3Busless1 ) ) ) ccornerNoExCells -outputlayer met3_TurnLen_bus1_5Err |
| and ( select -interact met3_Turn225_225_Edgeless05 ( and met3_Turn225_225_Edgeless05 met3Busless1 ) ) ccornerNoExCells -outputlayer met3_TurnLen_busless1Err |
| rule "met3.stress.CON.3" { |
| caption "met3.stress.CON.3: Min inner 45-degree edge length for met3 >= 5.00um wide inside areaid:critCorner area < 5.0" |
| copy met3_TurnLen_bus5Err |
| } |
| rule "met3.stress.CON.4" { |
| caption "met3.stress.CON.4: Min inner 45-degree edge length for met3 > 1.00um & < 5.00um wide inside areaid:critCorner area < 1.0" |
| copy met3_TurnLen_bus1_5Err |
| } |
| rule "met3.stress.CON.5" { |
| caption "met3.stress.CON.5: Min inner 45-degree edge length for met3 < 1.00um wide inside areaid:critCorner < 0.17" |
| copy met3_TurnLen_busless1Err |
| } |
| not met4OverCA ( inte met4OverCA -ltgt 0 5.0 -metric opposite -obtuse ALSO -output region ) -outputlayer met4Bus5_tmp |
| not met4Bus5_tmp ( with_width met4Bus5_tmp -lt 5.0 ) -outputlayer met4Bus5 |
| inte met4OverCA -ltge 1.0 5.0 -metric opposite -obtuse ALSO -output region -outputlayer met4Bus1_5_tmp |
| with_width ( and met4Bus1_5_tmp met4OverCA ) -ltge 1.0 5.0 -outputlayer met4Bus1_5_tmp1 |
| copy met4Bus1_5_tmp1 -outputlayer met4Bus1_5 |
| with_width met4OverCA -lt 1.0 -outputlayer met4Busless1 |
| edge_boolean -outside ( convex_edge met4OverCA -angle1 -eq 225 -angle2 -eq 225 ) met4Holes -outputlayer met4_Turn225_225_Edge_tmp1 |
| edge_expand met4_Turn225_225_Edge_tmp1 -inside_by 0.005 -extend_by "(10.0 * 0.005)" -outputlayer met4_Turn225_225_EdgeSz_tmp1 |
| select -inside met4_Turn225_225_EdgeSz_tmp1 met4OverCA -outputlayer met4_Turn225_225_EdgeSz_tmp2 |
| edge_boolean -coincident_only met4_Turn225_225_Edge_tmp1 met4_Turn225_225_EdgeSz_tmp2 -outputlayer met4_Turn225_225_Edge |
| edge_expand ( edge_length met4_Turn225_225_Edge -lt 5.0 ) -inside_by 0.005 -extend_by "(10.0 * 0.005)" -outputlayer met4_Turn225_225_Edgeless5 |
| edge_expand ( edge_length met4_Turn225_225_Edge -lt 1.0 ) -inside_by 0.005 -extend_by "(10.0 * 0.005)" -outputlayer met4_Turn225_225_Edgeless1 |
| edge_expand ( edge_length met4_Turn225_225_Edge -lt 0.17 ) -inside_by 0.005 -extend_by "(10.0 * 0.005)" -outputlayer met4_Turn225_225_Edgeless05 |
| and ( not ( select -interact met4_Turn225_225_Edgeless5 ( and met4_Turn225_225_Edgeless5 met4Bus5 ) ) ( select -interact met4_Turn225_225_Edgeless5 ( and met4_Turn225_225_Edgeless5 ( or met4Bus1_5 met4Busless1 ) ) ) ) critAreaNoExCells -outputlayer met4_TurnLen_bus5Err |
| and ( not ( select -interact met4_Turn225_225_Edgeless1 ( and met4_Turn225_225_Edgeless1 met4Bus1_5 ) ) ( select -interact met4_Turn225_225_Edgeless1 ( and met4_Turn225_225_Edgeless1 met4Busless1 ) ) ) ccornerNoExCells -outputlayer met4_TurnLen_bus1_5Err |
| and ( select -interact met4_Turn225_225_Edgeless05 ( and met4_Turn225_225_Edgeless05 met4Busless1 ) ) ccornerNoExCells -outputlayer met4_TurnLen_busless1Err |
| rule "met4.stress.CON.3" { |
| caption "met4.stress.CON.3: Min inner 45-degree edge length for met4 >= 5.00um wide inside areaid:critCorner area < 5.0" |
| copy met4_TurnLen_bus5Err |
| } |
| rule "met4.stress.CON.4" { |
| caption "met4.stress.CON.4: Min inner 45-degree edge length for met4 > 1.00um & < 5.00um wide inside areaid:critCorner area < 1.0" |
| copy met4_TurnLen_bus1_5Err |
| } |
| rule "met4.stress.CON.5" { |
| caption "met4.stress.CON.5: Min inner 45-degree edge length for met4 < 1.00um wide inside areaid:critCorner < 0.17" |
| copy met4_TurnLen_busless1Err |
| } |
| not met5OverCA ( inte met5OverCA -ltgt 0 5.0 -metric opposite -obtuse ALSO -output region ) -outputlayer met5Bus5_tmp |
| not met5Bus5_tmp ( with_width met5Bus5_tmp -lt 5.0 ) -outputlayer met5Bus5 |
| inte met5OverCA -ltge 1.0 5.0 -metric opposite -obtuse ALSO -output region -outputlayer met5Bus1_5_tmp |
| with_width ( and met5Bus1_5_tmp met5OverCA ) -ltge 1.0 5.0 -outputlayer met5Bus1_5_tmp1 |
| copy met5Bus1_5_tmp1 -outputlayer met5Bus1_5 |
| with_width met5OverCA -lt 1.0 -outputlayer met5Busless1 |
| edge_boolean -outside ( convex_edge met5OverCA -angle1 -eq 225 -angle2 -eq 225 ) met5Holes -outputlayer met5_Turn225_225_Edge_tmp1 |
| edge_expand met5_Turn225_225_Edge_tmp1 -inside_by 0.005 -extend_by "(10.0 * 0.005)" -outputlayer met5_Turn225_225_EdgeSz_tmp1 |
| select -inside met5_Turn225_225_EdgeSz_tmp1 met5OverCA -outputlayer met5_Turn225_225_EdgeSz_tmp2 |
| edge_boolean -coincident_only met5_Turn225_225_Edge_tmp1 met5_Turn225_225_EdgeSz_tmp2 -outputlayer met5_Turn225_225_Edge |
| edge_expand ( edge_length met5_Turn225_225_Edge -lt 5.0 ) -inside_by 0.005 -extend_by "(10.0 * 0.005)" -outputlayer met5_Turn225_225_Edgeless5 |
| edge_expand ( edge_length met5_Turn225_225_Edge -lt 1.0 ) -inside_by 0.005 -extend_by "(10.0 * 0.005)" -outputlayer met5_Turn225_225_Edgeless1 |
| edge_expand ( edge_length met5_Turn225_225_Edge -lt 0.17 ) -inside_by 0.005 -extend_by "(10.0 * 0.005)" -outputlayer met5_Turn225_225_Edgeless05 |
| and ( not ( select -interact met5_Turn225_225_Edgeless5 ( and met5_Turn225_225_Edgeless5 met5Bus5 ) ) ( select -interact met5_Turn225_225_Edgeless5 ( and met5_Turn225_225_Edgeless5 ( or met5Bus1_5 met5Busless1 ) ) ) ) critAreaNoExCells -outputlayer met5_TurnLen_bus5Err |
| and ( not ( select -interact met5_Turn225_225_Edgeless1 ( and met5_Turn225_225_Edgeless1 met5Bus1_5 ) ) ( select -interact met5_Turn225_225_Edgeless1 ( and met5_Turn225_225_Edgeless1 met5Busless1 ) ) ) ccornerNoExCells -outputlayer met5_TurnLen_bus1_5Err |
| and ( select -interact met5_Turn225_225_Edgeless05 ( and met5_Turn225_225_Edgeless05 met5Busless1 ) ) ccornerNoExCells -outputlayer met5_TurnLen_busless1Err |
| rule "met5.stress.CON.3" { |
| caption "met5.stress.CON.3: Min inner 45-degree edge length for met5 >= 5.00um wide inside areaid:critCorner area < 5.0" |
| copy met5_TurnLen_bus5Err |
| } |
| rule "met5.stress.CON.4" { |
| caption "met5.stress.CON.4: Min inner 45-degree edge length for met5 > 1.00um & < 5.00um wide inside areaid:critCorner area < 1.0" |
| copy met5_TurnLen_bus1_5Err |
| } |
| rule "met5.stress.CON.5" { |
| caption "met5.stress.CON.5: Min inner 45-degree edge length for met5 < 1.00um wide inside areaid:critCorner < 0.17" |
| copy met5_TurnLen_busless1Err |
| } |
| or ( extent_cell "padPL*" -original ) bondpadCuPillar -outputlayer bondpadPcelltmp_1 |
| extent_cell "pad_bond*" -original -outputlayer bondpadPcelltmp_2 |
| or bondpadPcelltmp_1 bondpadPcelltmp_2 -outputlayer bondpadPcelltmp |
| extent_cell "padPLadv*" -original -outputlayer bondpadPcellAdv |
| not bondpadPcelltmp bondpadPcellAdv -outputlayer bondpadPcell2 |
| and BONDPAD2 bondpadPcell2 -outputlayer bondpadNormal2 |
| and BONDPAD2 bondpadPcellAdv -outputlayer bondpadAdvan |
| size bondpadNormal2 -by 5 -outputlayer bondPadNormSz |
| size bondpadAdvan -by 2.7 -outputlayer bondPadAdvSz |
| or bondPadNormSz bondPadAdvSz -outputlayer allbondPadSzTmp |
| edge_expand ( angle allbondPadSzTmp -eq 45 ) -outside_by 0.005 -outputlayer degree45edge |
| or allbondPadSzTmp degree45edge -outputlayer allbondPadSz |
| and allbondPadSz met5 -outputlayer allbondPadSz_met5 |
| and met5 ( with_width ( not met5 allbondPadSz_met5 ) -ge 5.0 ) -outputlayer bondPadCon_met5 |
| or ( exte bondPadCon_met5 allbondPadSz_met5 -lt 0.005 -abut -ltgt 89.9 90.1 -single_point -output region ) ( exte allbondPadSz_met5 -lt 0.005 -abut -ltgt 89.9 90.1 -single_point -output region ) -outputlayer met5Bus_PadCor90 |
| size ( and ( select -touch met5Bus_PadCor90 met5 ) critAreaNoExCells ) -by "(10 * 0.025)" -outputlayer met5Bus_PadCor90Sz |
| rule "met5.stress.CON.6" { |
| caption "met5.stress.CON.6: 90-degree turns for met5 bus connecting pad at the point of connection is prohibited" |
| copy met5Bus_PadCor90Sz |
| } |
| and allbondPadSz met4 -outputlayer allbondPadSz_met4 |
| and met4 ( with_width ( not met4 allbondPadSz_met4 ) -ge 5.0 ) -outputlayer bondPadCon_met4 |
| or ( exte bondPadCon_met4 allbondPadSz_met4 -lt 0.005 -abut -ltgt 89.9 90.1 -single_point -output region ) ( exte allbondPadSz_met4 -lt 0.005 -abut -ltgt 89.9 90.1 -single_point -output region ) -outputlayer met4Bus_PadCor90 |
| size ( and ( select -touch met4Bus_PadCor90 met4 ) critAreaNoExCells ) -by "(10 * 0.025)" -outputlayer met4Bus_PadCor90Sz |
| rule "met4.stress.CON.6" { |
| caption "met4.stress.CON.6: 90-degree turns for met4 bus connecting pad at the point of connection is prohibited" |
| copy met4Bus_PadCor90Sz |
| } |
| convex_edge met5 -angle1 -eq 90 -angle2 -eq 270 -outputlayer convexedges_90 |
| convex_edge met5 -angle1 -eq 135 -angle2 -eq 270 -outputlayer convexedges_135 |
| convex_edge met5 -angle1 -gt 0 -angle2 -eq 225 -outputlayer convexedges_45 |
| edge_length convexedges_135 -le 6.4 -outputlayer met_edge_45_225 |
| edge_length convexedges_45 -le 6.4 -outputlayer met_edge_135_225 |
| edge_length convexedges_90 -le 6.4 -outputlayer met_edge_90_270 |
| edge_expand met_edge_45_225 -inside_by 0.005 -outputlayer convexedges_45Sz |
| edge_expand met_edge_135_225 -inside_by 0.005 -outputlayer convexedges_135Sz |
| edge_expand met_edge_90_270 -inside_by 0.005 -outputlayer met_edge_90_270Sz |
| edge_expand ( edge_length met5 -lege 1.6 3.2 ) -inside_by 0.005 -outputlayer all_met_edgesSz |
| not all_met_edgesSz ( or convexedges_45Sz convexedges_135Sz met_edge_90_270Sz ) -outputlayer all_met_edgesNot90_270 |
| edge_expand ( angle met5 -eq 45 ) -inside_by 0.005 -outputlayer topmet45Sz |
| not ( or convexedges_45Sz convexedges_135Sz met_edge_90_270Sz ) topmet45Sz -outputlayer convexedges |
| select -interact -not convexedges all_met_edgesNot90_270 -outputlayer met_edge_90_270Real |
| and ( exte met_edge_90_270Real -le 3.19 -para -metric opposite -output region ) met5 -outputlayer met_edge_90_270Regtmp |
| with_width -not met_edge_90_270Regtmp -eq 0.005 -outputlayer met_edge_90_270Reg |
| select -with_edge met_edge_90_270Real ( edge_boolean -coincident_only -outside met_edge_90_270Real met_edge_90_270Reg ) -outputlayer met_edge_90_270RegChk |
| select -interact met5 ( and met5 met_edge_90_270Reg ) -outputlayer met_turn_90_270 |
| edge_expand ( edge_length ( not met5 met_turn_90_270 ) -le 1.0 ) -inside_by 0.005 -outputlayer met_LineEnd |
| edge_expand met_edge_90_270RegChk -outside_by 1 -outputlayer met_edge_90_270Sz1 |
| select -cut -not met_LineEnd met_edge_90_270Sz1 -outputlayer met_Line_Good |
| angle ( and met5 ( or critsideNoExCells ccornerNoExCells ) ) -ltgt 44.9 45.1 -outputlayer topMet45 |
| not ( edge_expand topMet45 -outside_by 0.005 ) met5slot -outputlayer topMet45szOut |
| select -interact met5 topMet45szOut -outputlayer topMetInt45 |
| edge_expand ( angle topMetInt45 -eq 90 ) -outside_by 0.005 -outputlayer topMet90sz |
| edge_expand ( angle topMetInt45 -eq 0 ) -outside_by 0.005 -outputlayer topMet0sz |
| and ( select -interact topMet45szOut topMet90sz ) ( select -interact topMet45szOut topMet0sz ) -outputlayer topMet45_both |
| select -interact topMet0sz topMet45szOut -eq 2 -outputlayer topMet0_45_2x |
| select -interact topMet90sz topMet45szOut -eq 2 -outputlayer topMet90_45_2x |
| and ( select -interact topmet45szOut topMet0_45_2x ) ( select -interact topmet45szout topMet90_45_2x ) -outputlayer topMet45_3x |
| edge_expand ( edge_length ( edge_boolean -coincident_only topMetInt45 ( select -interact topMet90sz topMet45_3x ) ) -lt 2.3 ) -outside_by 0.005 -outputlayer stress18_err90 |
| edge_expand ( edge_length ( edge_boolean -coincident_only topMetInt45 ( select -interact topMet0sz topMet45_3x ) ) -lt 2.3 ) -outside_by 0.005 -outputlayer stress18_err0 |
| select -interact stress18_err90 ( select -interact topMet45_3x stress18_err0 ) -outputlayer err1 |
| select -interact stress18_err0 ( select -interact topMet45_3x stress18_err90 ) -outputlayer err2 |
| rule "stress.CON.7" { |
| caption "stress.CON.7: Min length of non-touching angled edges for shape containing 3 consecutive 45-degree edges in areaid:cristSid or areaid:critCorner < 2.3" |
| copy err1 |
| copy err2 |
| } |
| rule "met1.slot.WID.1" { |
| caption "met1.slot.WID.1: Min width of met1 slot < 2.3" |
| and ( inte met1slotAll -lt 2.3 -para -metric opposite -output region ) critAreaStress |
| } |
| rule "met1.slot.WID.2" { |
| caption "met1.slot.WID.2: Max width of met1 slot > 10.0" |
| with_width met1slot -gt 10.0 |
| } |
| rule "met1.slot.LEN.1" { |
| caption "met1.slot.LEN.1: Max length of met1 slot = 600.0" |
| edge_length ( select -interact met1slotAll ( and met1slotAll critAreaStress ) ) -gt 600.0 |
| } |
| rule "met2.slot.WID.1" { |
| caption "met2.slot.WID.1: Min width of met2 slot < 2.3" |
| and ( inte met2slotAll -lt 2.3 -para -metric opposite -output region ) critAreaStress |
| } |
| rule "met2.slot.WID.2" { |
| caption "met2.slot.WID.2: Max width of met2 slot > 10.0" |
| with_width met2slot -gt 10.0 |
| } |
| rule "met2.slot.LEN.1" { |
| caption "met2.slot.LEN.1: Max length of met2 slot = 600.0" |
| edge_length ( select -interact met2slotAll ( and met2slotAll critAreaStress ) ) -gt 600.0 |
| } |
| rule "met3.slot.WID.1" { |
| caption "met3.slot.WID.1: Min width of met3 slot < 2.3" |
| and ( inte met3slotAll -lt 2.3 -para -metric opposite -output region ) critAreaStress |
| } |
| rule "met3.slot.WID.2" { |
| caption "met3.slot.WID.2: Max width of met3 slot > 10.0" |
| with_width met3slot -gt 10.0 |
| } |
| rule "met3.slot.LEN.1" { |
| caption "met3.slot.LEN.1: Max length of met3 slot = 600.0" |
| edge_length ( select -interact met3slotAll ( and met3slotAll critAreaStress ) ) -gt 600.0 |
| } |
| rule "met4.slot.WID.1" { |
| caption "met4.slot.WID.1: Min width of met4 slot < 2.3" |
| and ( inte met4slotAll -lt 2.3 -para -metric opposite -output region ) critAreaStress |
| } |
| rule "met4.slot.WID.2" { |
| caption "met4.slot.WID.2: Max width of met4 slot > 10.0" |
| with_width met4slot -gt 10.0 |
| } |
| rule "met4.slot.LEN.1" { |
| caption "met4.slot.LEN.1: Max length of met4 slot = 600.0" |
| edge_length ( select -interact met4slotAll ( and met4slotAll critAreaStress ) ) -gt 600.0 |
| } |
| rule "met5.slot.WID.1" { |
| caption "met5.slot.WID.1: Min width of met5 slot < 2.3" |
| and ( inte met5slotAll -lt 2.3 -para -metric opposite -output region ) critAreaStress |
| } |
| rule "met5.slot.WID.2" { |
| caption "met5.slot.WID.2: Max width of met5 slot > 10.0" |
| with_width met5slot -gt 10.0 |
| } |
| rule "met5.slot.LEN.1" { |
| caption "met5.slot.LEN.1: Max length of met5 slot = 600.0" |
| edge_length ( select -interact met5slotAll ( and met5slotAll critAreaStress ) ) -gt 600.0 |
| } |
| not via1 ( or SEALID ( or exemptStressCells padPcells ) ) -outputlayer rivetvia1 |
| select -interact ( and met1OverCA met2 ) rivetvia1 -outputlayer met1stack |
| with_width met1stack -ge 25.0 -outputlayer met1stackBus |
| and met1stackBus critAreaStress -outputlayer met1stackBusCA |
| not ( with_width met2 -ge 25.0 ) exemptStressCells -outputlayer met1UppBus |
| and met1stackBus met1UppBus -outputlayer met1stack_uppBus |
| and ( not ( enc met1stack met2 -lt 1.0 -abut -lt 89.5 -single_point -output region ) SEALID ) critAreaStress -outputlayer met1stack_encErr_tmp |
| select -interact met1stack_encErr_tmp ( and met1stack_encErr_tmp met1stack_uppBus ) -outputlayer met1stack_encErr |
| edge_boolean -coincident_only -outside ( not met1OverCA met1stack ) met1stack -outputlayer met1stackStrUpp |
| select -cut -not ( edge_expand met1stackStrUpp -inside_by 0.5 ) met1OverCA -outputlayer met1stackStrUppSz05 |
| edge_boolean -coincident_only -outside met1stackStrUppSz05 met1stack -outputlayer met1stackStrUppExempt |
| not met1stack_encErr ( edge_expand met1stackStrUppExempt -outside_by 0.005 ) -outputlayer met1stack_encErrFinal |
| connect met1stackBusCA via1 |
| select -interact ( and ( or met1OverCA met1slot ) ( or met2 met2slot ) ) rivetvia1 -outputlayer met1stackNoSlots |
| with_width met1stackNoSlots -ge 25.0 -outputlayer met1stackBusNoSlots |
| and met1stackBusNoSlots critAreaStress -outputlayer met1stackBusCA_NoSlots |
| and met1slot met1stackBusCA_NoSlots -outputlayer met1Low_slot_stack |
| and met2slot met1stackBusCA_NoSlots -outputlayer met2Upp_slot_stack |
| not ( select -interact ( select -enclose -not met1Low_slot_stack met2Upp_slot_stack ) ( and ( select -enclose -not met1Low_slot_stack met2Upp_slot_stack ) critAreaStress ) ) ( extent_cell "pad_bond*" -original ) -outputlayer err_coin_slots_met1 |
| rule "met1.stress.CON.9" { |
| caption "met1.slot.CON.9: met1 in lower slotted stack should enclose met2 in the upper slotted stack." |
| copy err_coin_slots_met1 |
| } |
| rule "met1.stress.ENC.1" { |
| caption "met1.stress.ENC.1: Min enclosure of met2 in a slotted stack by met1 in slotted stack < 1.0" |
| enc ( and met2Upp_slot_stack met1Low_slot_stack ) met1Low_slot_stack -lt 1.0 -measure all -abut -lt 90 -single_point |
| } |
| rule "met1.stress.ENC.2" { |
| caption "met1.stress.ENC.2: Min enclosure of a met1 stack bus by met2 bus < 1.0" |
| copy met1stack_encErrFinal |
| } |
| rule "met1.stress.DEN.1" { |
| caption "met1.stress.DEN.1: Min via1 density on wide met1 and met2 bus stack is 3.00 percent" |
| antenna met1stackBusCA via1 -lt 0.03 -expr " AREA(via1)/AREA(met1stackBusCA) " -rdb met1.stress.DEN.1.db met1stackBusCA via1 |
| } |
| not via2 ( or SEALID ( or exemptStressCells padPcells ) ) -outputlayer rivetvia2 |
| select -interact ( and met2OverCA met3 ) rivetvia2 -outputlayer met2stack |
| with_width met2stack -ge 25.0 -outputlayer met2stackBus |
| and met2stackBus critAreaStress -outputlayer met2stackBusCA |
| not ( with_width met3 -ge 25.0 ) exemptStressCells -outputlayer met2UppBus |
| and met2stackBus met2UppBus -outputlayer met2stack_uppBus |
| and ( not ( enc met2stack met3 -lt 1.0 -abut -lt 89.5 -single_point -output region ) SEALID ) critAreaStress -outputlayer met2stack_encErr_tmp |
| select -interact met2stack_encErr_tmp ( and met2stack_encErr_tmp met2stack_uppBus ) -outputlayer met2stack_encErr |
| edge_boolean -coincident_only -outside ( not met2OverCA met2stack ) met2stack -outputlayer met2stackStrUpp |
| select -cut -not ( edge_expand met2stackStrUpp -inside_by 0.5 ) met2OverCA -outputlayer met2stackStrUppSz05 |
| edge_boolean -coincident_only -outside met2stackStrUppSz05 met2stack -outputlayer met2stackStrUppExempt |
| not met2stack_encErr ( edge_expand met2stackStrUppExempt -outside_by 0.005 ) -outputlayer met2stack_encErrFinal |
| connect met2stackBusCA via2 |
| select -interact ( and ( or met2OverCA met2slot ) ( or met3 met3slot ) ) rivetvia2 -outputlayer met2stackNoSlots |
| with_width met2stackNoSlots -ge 25.0 -outputlayer met2stackBusNoSlots |
| and met2stackBusNoSlots critAreaStress -outputlayer met2stackBusCA_NoSlots |
| and met2slot met2stackBusCA_NoSlots -outputlayer met2Low_slot_stack |
| and met3slot met2stackBusCA_NoSlots -outputlayer met3Upp_slot_stack |
| not ( select -interact ( select -enclose -not met2Low_slot_stack met3Upp_slot_stack ) ( and ( select -enclose -not met2Low_slot_stack met3Upp_slot_stack ) critAreaStress ) ) ( extent_cell "pad_bond*" -original ) -outputlayer err_coin_slots_met2 |
| rule "met2.stress.CON.9" { |
| caption "met2.slot.CON.9: met2 in lower slotted stack should enclose met3 in the upper slotted stack." |
| copy err_coin_slots_met2 |
| } |
| rule "met2.stress.ENC.1" { |
| caption "met2.stress.ENC.1: Min enclosure of met3 in a slotted stack by met2 in slotted stack < 1.0" |
| enc ( and met3Upp_slot_stack met2Low_slot_stack ) met2Low_slot_stack -lt 1.0 -measure all -abut -lt 90 -single_point |
| } |
| rule "met2.stress.ENC.2" { |
| caption "met2.stress.ENC.2: Min enclosure of a met2 stack bus by met3 bus < 1.0" |
| copy met2stack_encErrFinal |
| } |
| rule "met2.stress.DEN.1" { |
| caption "met2.stress.DEN.1: Min via2 density on wide met2 and met3 bus stack is 3.00 percent" |
| antenna met2stackBusCA via2 -lt 0.03 -expr " AREA(via2)/AREA(met2stackBusCA) " -rdb met2.stress.DEN.1.db met2stackBusCA via2 |
| } |
| not via3 ( or SEALID ( or exemptStressCells padPcells ) ) -outputlayer rivetvia3 |
| select -interact ( and met3OverCA met4 ) rivetvia3 -outputlayer met3stack |
| with_width met3stack -ge 25.0 -outputlayer met3stackBus |
| and met3stackBus critAreaStress -outputlayer met3stackBusCA |
| not ( with_width met4 -ge 25.0 ) exemptStressCells -outputlayer met3UppBus |
| and met3stackBus met3UppBus -outputlayer met3stack_uppBus |
| and ( not ( enc met3stack met4 -lt 1.0 -abut -lt 89.5 -single_point -output region ) SEALID ) critAreaStress -outputlayer met3stack_encErr_tmp |
| select -interact met3stack_encErr_tmp ( and met3stack_encErr_tmp met3stack_uppBus ) -outputlayer met3stack_encErr |
| edge_boolean -coincident_only -outside ( not met3OverCA met3stack ) met3stack -outputlayer met3stackStrUpp |
| select -cut -not ( edge_expand met3stackStrUpp -inside_by 0.5 ) met3OverCA -outputlayer met3stackStrUppSz05 |
| edge_boolean -coincident_only -outside met3stackStrUppSz05 met3stack -outputlayer met3stackStrUppExempt |
| not met3stack_encErr ( edge_expand met3stackStrUppExempt -outside_by 0.005 ) -outputlayer met3stack_encErrFinal |
| connect met3stackBusCA via3 |
| select -interact ( and ( or met3OverCA met3slot ) ( or met4 met4slot ) ) rivetvia3 -outputlayer met3stackNoSlots |
| with_width met3stackNoSlots -ge 25.0 -outputlayer met3stackBusNoSlots |
| and met3stackBusNoSlots critAreaStress -outputlayer met3stackBusCA_NoSlots |
| and met3slot met3stackBusCA_NoSlots -outputlayer met3Low_slot_stack |
| and met4slot met3stackBusCA_NoSlots -outputlayer met4Upp_slot_stack |
| not ( select -interact ( select -enclose -not met3Low_slot_stack met4Upp_slot_stack ) ( and ( select -enclose -not met3Low_slot_stack met4Upp_slot_stack ) critAreaStress ) ) ( extent_cell "pad_bond*" -original ) -outputlayer err_coin_slots_met3 |
| rule "met3.stress.CON.9" { |
| caption "met3.slot.CON.9: met3 in lower slotted stack should enclose met4 in the upper slotted stack." |
| copy err_coin_slots_met3 |
| } |
| rule "met3.stress.ENC.1" { |
| caption "met3.stress.ENC.1: Min enclosure of met4 in a slotted stack by met3 in slotted stack < 1.0" |
| enc ( and met4Upp_slot_stack met3Low_slot_stack ) met3Low_slot_stack -lt 1.0 -measure all -abut -lt 90 -single_point |
| } |
| rule "met3.stress.ENC.2" { |
| caption "met3.stress.ENC.2: Min enclosure of a met3 stack bus by met4 bus < 1.0" |
| copy met3stack_encErrFinal |
| } |
| rule "met3.stress.DEN.1" { |
| caption "met3.stress.DEN.1: Min via3 density on wide met3 and met4 bus stack is 3.00 percent" |
| antenna met3stackBusCA via3 -lt 0.03 -expr " AREA(via3)/AREA(met3stackBusCA) " -rdb met3.stress.DEN.1.db met3stackBusCA via3 |
| } |
| not via4 ( or SEALID ( or exemptStressCells padPcells ) ) -outputlayer rivetvia4 |
| select -interact ( and met4OverCA met5 ) rivetvia4 -outputlayer met4stack |
| with_width met4stack -ge 25.0 -outputlayer met4stackBus |
| and met4stackBus critAreaStress -outputlayer met4stackBusCA |
| not ( with_width met5 -ge 25.0 ) exemptStressCells -outputlayer met4UppBus |
| and met4stackBus met4UppBus -outputlayer met4stack_uppBus |
| and ( not ( enc met4stack met5 -lt 1.0 -abut -lt 89.5 -single_point -output region ) SEALID ) critAreaStress -outputlayer met4stack_encErr_tmp |
| select -interact met4stack_encErr_tmp ( and met4stack_encErr_tmp met4stack_uppBus ) -outputlayer met4stack_encErr |
| edge_boolean -coincident_only -outside ( not met4OverCA met4stack ) met4stack -outputlayer met4stackStrUpp |
| select -cut -not ( edge_expand met4stackStrUpp -inside_by 0.5 ) met4OverCA -outputlayer met4stackStrUppSz05 |
| edge_boolean -coincident_only -outside met4stackStrUppSz05 met4stack -outputlayer met4stackStrUppExempt |
| not met4stack_encErr ( edge_expand met4stackStrUppExempt -outside_by 0.005 ) -outputlayer met4stack_encErrFinal |
| connect met4stackBusCA via4 |
| select -interact ( and ( or met4OverCA met4slot ) ( or met5 met5slot ) ) rivetvia4 -outputlayer met4stackNoSlots |
| with_width met4stackNoSlots -ge 25.0 -outputlayer met4stackBusNoSlots |
| and met4stackBusNoSlots critAreaStress -outputlayer met4stackBusCA_NoSlots |
| and met4slot met4stackBusCA_NoSlots -outputlayer met4Low_slot_stack |
| and met5slot met4stackBusCA_NoSlots -outputlayer met5Upp_slot_stack |
| not ( select -interact ( select -enclose -not met4Low_slot_stack met5Upp_slot_stack ) ( and ( select -enclose -not met4Low_slot_stack met5Upp_slot_stack ) critAreaStress ) ) ( extent_cell "pad_bond*" -original ) -outputlayer err_coin_slots_met4 |
| rule "met4.stress.CON.9" { |
| caption "met4.slot.CON.9: met4 in lower slotted stack should enclose met5 in the upper slotted stack." |
| copy err_coin_slots_met4 |
| } |
| rule "met4.stress.ENC.1" { |
| caption "met4.stress.ENC.1: Min enclosure of met5 in a slotted stack by met4 in slotted stack < 1.0" |
| enc ( and met5Upp_slot_stack met4Low_slot_stack ) met4Low_slot_stack -lt 1.0 -measure all -abut -lt 90 -single_point |
| } |
| rule "met4.stress.ENC.2" { |
| caption "met4.stress.ENC.2: Min enclosure of a met4 stack bus by met5 bus < 1.0" |
| copy met4stack_encErrFinal |
| } |
| rule "met4.stress.DEN.1" { |
| caption "met4.stress.DEN.1: Min via4 density on wide met4 and met5 bus stack is 3.00 percent" |
| antenna met4stackBusCA via4 -lt 0.03 -expr " AREA(via4)/AREA(met4stackBusCA) " -rdb met4.stress.DEN.1.db met4stackBusCA via4 |
| } |
| copy 4004 -outputlayer met1Shielda |
| with_width ( and ( select -interact ( not filled_met1 met1Shielda ) ( and ( not filled_met1 met1Shielda ) met1slotAll ) ) critAreaStress ) -gt 25.0 -outputlayer met1_over_crit_area |
| connect met1_over_crit_area met1slotAll |
| rule "met1.slot.DEN.1" { |
| caption "met1.slot.DEN.1: Min slot density on wide met1 bus < 7.50%" |
| antenna met1_over_crit_area met1slotAll -lt 0.075 -expr " AREA(met1slotAll)/AREA(met1_over_crit_area) " -rdb met1.slot.DEN.1.db met1_over_crit_area met1slotAll |
| } |
| with_width ( and ( select -interact filled_met2 ( and filled_met2 met2slotAll ) ) critAreaStress ) -gt 25.0 -outputlayer met2_over_crit_area |
| connect met2_over_crit_area met2slotAll |
| rule "met2.slot.DEN.1" { |
| caption "met2.slot.DEN.1: Min slot density on wide met2 bus < 7.50%" |
| antenna met2_over_crit_area met2slotAll -lt 0.075 -expr " AREA(met2slotAll)/AREA(met2_over_crit_area) " -rdb met2.slot.DEN.1.db met2_over_crit_area met2slotAll |
| } |
| with_width ( and ( select -interact filled_met3 ( and filled_met3 met3slotAll ) ) critAreaStress ) -gt 25.0 -outputlayer met3_over_crit_area |
| connect met3_over_crit_area met3slotAll |
| rule "met3.slot.DEN.1" { |
| caption "met3.slot.DEN.1: Min slot density on wide met3 bus < 7.50%" |
| antenna met3_over_crit_area met3slotAll -lt 0.075 -expr " AREA(met3slotAll)/AREA(met3_over_crit_area) " -rdb met3.slot.DEN.1.db met3_over_crit_area met3slotAll |
| } |
| with_width ( and ( select -interact filled_met4 ( and filled_met4 met4slotAll ) ) critAreaStress ) -gt 25.0 -outputlayer met4_over_crit_area |
| connect met4_over_crit_area met4slotAll |
| rule "met4.slot.DEN.1" { |
| caption "met4.slot.DEN.1: Min slot density on wide met4 bus < 7.50%" |
| antenna met4_over_crit_area met4slotAll -lt 0.075 -expr " AREA(met4slotAll)/AREA(met4_over_crit_area) " -rdb met4.slot.DEN.1.db met4_over_crit_area met4slotAll |
| } |
| with_width ( and ( select -interact filled_met5 ( and filled_met5 met5slotAll ) ) critAreaStress ) -gt 25.0 -outputlayer met5_over_crit_area |
| connect met5_over_crit_area met5slotAll |
| rule "met5.slot.DEN.1" { |
| caption "met5.slot.DEN.1: Min slot density on wide met5 bus < 7.50%" |
| antenna met5_over_crit_area met5slotAll -lt 0.075 -expr " AREA(met5slotAll)/AREA(met5_over_crit_area) " -rdb met5.slot.DEN.1.db met5_over_crit_area met5slotAll |
| } |
| select -interact ( with_width ( not met1OverCA met1Shielda ) -gt 25.0 ) ( and ( with_width ( not met1OverCA met1Shielda ) -gt 25.0 ) critAreaStress ) -outputlayer met1OverCAnoSlot |
| rule "met1.slot.CON.1" { |
| caption "met1.slot.CON.1: met1 wider than 25um inside areaid:critCorner or areaid:critSid must contain slot" |
| copy met1OverCAnoSlot |
| } |
| rule "met1.slot.SP.1" { |
| caption "met1.slot.SP.1: Min spacing of met1 slot < 2.3" |
| exte met1slot -lt 2.3 -abut -lt 90 -single_point -output region -notch not |
| } |
| select -interact ( with_width met2OverCA -gt 25.0 ) ( and ( with_width met2OverCA -gt 25.0 ) critAreaStress ) -outputlayer met2OverCAnoSlot |
| rule "met2.slot.CON.1" { |
| caption "met2.slot.CON.1: met2 wider than 25um inside areaid:critCorner or areaid:critSid must contain slot" |
| copy met2OverCAnoSlot |
| } |
| rule "met2.slot.SP.1" { |
| caption "met2.slot.SP.1: Min spacing of met2 slot < 2.3" |
| exte met2slot -lt 2.3 -abut -lt 90 -single_point -output region -notch not |
| } |
| select -interact ( with_width met3OverCA -gt 25.0 ) ( and ( with_width met3OverCA -gt 25.0 ) critAreaStress ) -outputlayer met3OverCAnoSlot |
| rule "met3.slot.CON.1" { |
| caption "met3.slot.CON.1: met3 wider than 25um inside areaid:critCorner or areaid:critSid must contain slot" |
| copy met3OverCAnoSlot |
| } |
| rule "met3.slot.SP.1" { |
| caption "met3.slot.SP.1: Min spacing of met3 slot < 2.3" |
| exte met3slot -lt 2.3 -abut -lt 90 -single_point -output region -notch not |
| } |
| select -interact ( with_width met4OverCA -gt 25.0 ) ( and ( with_width met4OverCA -gt 25.0 ) critAreaStress ) -outputlayer met4OverCAnoSlot |
| rule "met4.slot.CON.1" { |
| caption "met4.slot.CON.1: met4 wider than 25um inside areaid:critCorner or areaid:critSid must contain slot" |
| copy met4OverCAnoSlot |
| } |
| rule "met4.slot.SP.1" { |
| caption "met4.slot.SP.1: Min spacing of met4 slot < 2.3" |
| exte met4slot -lt 2.3 -abut -lt 90 -single_point -output region -notch not |
| } |
| and met5 padPcells -outputlayer slotMetXmt |
| select -interact ( with_width ( not met5OverCA slotMetXmt ) -gt 25.0 ) ( and ( with_width ( not met5OverCA slotMetXmt ) -gt 25.0 ) critAreaStress ) -outputlayer met5OverCAnoSlot |
| rule "met5.slot.CON.1" { |
| caption "met5.slot.CON.1: met5 wider than 25um inside areaid:critCorner or areaid:critSid must contain slot" |
| copy met5OverCAnoSlot |
| } |
| rule "met5.slot.SP.1" { |
| caption "met5.slot.SP.1: Min spacing of met5 slot < 2.3" |
| exte met5slot -lt 2.3 -abut -lt 90 -single_point -output region -notch not |
| } |
| edge_length met1slot -lege 2.3 10.0 -outputlayer met1_slotShortLen |
| edge_expand met1_slotShortLen -outside_by 0.005 -outputlayer met1_slotShortLenSz |
| edge_expand ( edge_length met1_slotShortLenSz -eq 0.005 ) -inside_by 0.005 -outputlayer met1_slotShortLen1 |
| exte met1_slotShortLen1 -le 25.0 -para -metric opposite -output region -outputlayer met1_slotShortLenSpc25 |
| select -interact ( not met1_slotShortLenSpc25 ( select -interact met1_slotShortLenSpc25 ( and met1_slotShortLenSpc25 met1slot ) ) ) ( edge_expand ( edge_boolean -coincident_only -outside ( not met1_slotShortLenSpc25 ( select -interact met1_slotShortLenSpc25 ( and met1_slotShortLenSpc25 met1slot ) ) ) met1slot ) -by 0.005 -extend_by 0.005 ) -ge 2 -outputlayer met1_slotShortLen15err1 |
| select -interact ( select -interact met1_slotShortLen15err1 ( and met1_slotShortLen15err1 met1_slotShortLenSz ) -ge 2 ) ( and ( select -interact met1_slotShortLen15err1 ( and met1_slotShortLen15err1 met1_slotShortLenSz ) -ge 2 ) critAreaStress ) -outputlayer met1_slotShortLen15err |
| rule "met1.slot.CON.2" { |
| caption "met1.slot.CON.2: Start and end points of met1 slots spaced <= 25.00um apart in adjacent rows must be offset" |
| copy met1_slotShortLen15err |
| } |
| edge_length met2slot -lege 2.3 10.0 -outputlayer met2_slotShortLen |
| edge_expand met2_slotShortLen -outside_by 0.005 -outputlayer met2_slotShortLenSz |
| edge_expand ( edge_length met2_slotShortLenSz -eq 0.005 ) -inside_by 0.005 -outputlayer met2_slotShortLen1 |
| exte met2_slotShortLen1 -le 25.0 -para -metric opposite -output region -outputlayer met2_slotShortLenSpc25 |
| select -interact ( not met2_slotShortLenSpc25 ( select -interact met2_slotShortLenSpc25 ( and met2_slotShortLenSpc25 met2slot ) ) ) ( edge_expand ( edge_boolean -coincident_only -outside ( not met2_slotShortLenSpc25 ( select -interact met2_slotShortLenSpc25 ( and met2_slotShortLenSpc25 met2slot ) ) ) met2slot ) -by 0.005 -extend_by 0.005 ) -ge 2 -outputlayer met2_slotShortLen15err1 |
| select -interact ( select -interact met2_slotShortLen15err1 ( and met2_slotShortLen15err1 met2_slotShortLenSz ) -ge 2 ) ( and ( select -interact met2_slotShortLen15err1 ( and met2_slotShortLen15err1 met2_slotShortLenSz ) -ge 2 ) critAreaStress ) -outputlayer met2_slotShortLen15err |
| rule "met2.slot.CON.2" { |
| caption "met2.slot.CON.2: Start and end points of met2 slots spaced <= 25.00um apart in adjacent rows must be offset" |
| copy met2_slotShortLen15err |
| } |
| edge_length met3slot -lege 2.3 10.0 -outputlayer met3_slotShortLen |
| edge_expand met3_slotShortLen -outside_by 0.005 -outputlayer met3_slotShortLenSz |
| edge_expand ( edge_length met3_slotShortLenSz -eq 0.005 ) -inside_by 0.005 -outputlayer met3_slotShortLen1 |
| exte met3_slotShortLen1 -le 25.0 -para -metric opposite -output region -outputlayer met3_slotShortLenSpc25 |
| select -interact ( not met3_slotShortLenSpc25 ( select -interact met3_slotShortLenSpc25 ( and met3_slotShortLenSpc25 met3slot ) ) ) ( edge_expand ( edge_boolean -coincident_only -outside ( not met3_slotShortLenSpc25 ( select -interact met3_slotShortLenSpc25 ( and met3_slotShortLenSpc25 met3slot ) ) ) met3slot ) -by 0.005 -extend_by 0.005 ) -ge 2 -outputlayer met3_slotShortLen15err1 |
| select -interact ( select -interact met3_slotShortLen15err1 ( and met3_slotShortLen15err1 met3_slotShortLenSz ) -ge 2 ) ( and ( select -interact met3_slotShortLen15err1 ( and met3_slotShortLen15err1 met3_slotShortLenSz ) -ge 2 ) critAreaStress ) -outputlayer met3_slotShortLen15err |
| rule "met3.slot.CON.2" { |
| caption "met3.slot.CON.2: Start and end points of met3 slots spaced <= 25.00um apart in adjacent rows must be offset" |
| copy met3_slotShortLen15err |
| } |
| edge_length met4slot -lege 2.3 10.0 -outputlayer met4_slotShortLen |
| edge_expand met4_slotShortLen -outside_by 0.005 -outputlayer met4_slotShortLenSz |
| edge_expand ( edge_length met4_slotShortLenSz -eq 0.005 ) -inside_by 0.005 -outputlayer met4_slotShortLen1 |
| exte met4_slotShortLen1 -le 25.0 -para -metric opposite -output region -outputlayer met4_slotShortLenSpc25 |
| select -interact ( not met4_slotShortLenSpc25 ( select -interact met4_slotShortLenSpc25 ( and met4_slotShortLenSpc25 met4slot ) ) ) ( edge_expand ( edge_boolean -coincident_only -outside ( not met4_slotShortLenSpc25 ( select -interact met4_slotShortLenSpc25 ( and met4_slotShortLenSpc25 met4slot ) ) ) met4slot ) -by 0.005 -extend_by 0.005 ) -ge 2 -outputlayer met4_slotShortLen15err1 |
| select -interact ( select -interact met4_slotShortLen15err1 ( and met4_slotShortLen15err1 met4_slotShortLenSz ) -ge 2 ) ( and ( select -interact met4_slotShortLen15err1 ( and met4_slotShortLen15err1 met4_slotShortLenSz ) -ge 2 ) critAreaStress ) -outputlayer met4_slotShortLen15err |
| rule "met4.slot.CON.2" { |
| caption "met4.slot.CON.2: Start and end points of met4 slots spaced <= 25.00um apart in adjacent rows must be offset" |
| copy met4_slotShortLen15err |
| } |
| edge_length met5slot -lege 2.3 10.0 -outputlayer met5_slotShortLen |
| edge_expand met5_slotShortLen -outside_by 0.005 -outputlayer met5_slotShortLenSz |
| edge_expand ( edge_length met5_slotShortLenSz -eq 0.005 ) -inside_by 0.005 -outputlayer met5_slotShortLen1 |
| exte met5_slotShortLen1 -le 25.0 -para -metric opposite -output region -outputlayer met5_slotShortLenSpc25 |
| select -interact ( not met5_slotShortLenSpc25 ( select -interact met5_slotShortLenSpc25 ( and met5_slotShortLenSpc25 met5slot ) ) ) ( edge_expand ( edge_boolean -coincident_only -outside ( not met5_slotShortLenSpc25 ( select -interact met5_slotShortLenSpc25 ( and met5_slotShortLenSpc25 met5slot ) ) ) met5slot ) -by 0.005 -extend_by 0.005 ) -ge 2 -outputlayer met5_slotShortLen15err1 |
| select -interact ( select -interact met5_slotShortLen15err1 ( and met5_slotShortLen15err1 met5_slotShortLenSz ) -ge 2 ) ( and ( select -interact met5_slotShortLen15err1 ( and met5_slotShortLen15err1 met5_slotShortLenSz ) -ge 2 ) critAreaStress ) -outputlayer met5_slotShortLen15err |
| rule "met5.slot.CON.2" { |
| caption "met5.slot.CON.2: Start and end points of met5 slots spaced <= 25.00um apart in adjacent rows must be offset" |
| copy met5_slotShortLen15err |
| } |
| not chip_area critAreaStress -outputlayer allay_first |
| or ( and dnwell critAreaStress ) allay_first -outputlayer q0lay |
| or ( and nwell critAreaStress ) q0lay -outputlayer q1lay |
| or ( and diff critAreaStress ) q1lay -outputlayer q2lay |
| or ( and tap critAreaStress ) q2lay -outputlayer q3lay |
| or ( and lvtn critAreaStress ) q3lay -outputlayer q4lay |
| or ( and hvtp critAreaStress ) q4lay -outputlayer q5lay |
| or ( and v5 critAreaStress ) q5lay -outputlayer q6lay |
| or ( and poly critAreaStress ) q6lay -outputlayer q7lay |
| or ( and npc critAreaStress ) q7lay -outputlayer q8lay |
| or ( and nsdm critAreaStress ) q8lay -outputlayer q9lay |
| or ( and psdm critAreaStress ) q9lay -outputlayer q10lay |
| or ( and tunm critAreaStress ) q10lay -outputlayer q11lay |
| or ( and licon critAreaStress ) q11lay -outputlayer q12lay |
| or ( and li critAreaStress ) q12lay -outputlayer q13lay |
| or ( and mcon critAreaStress ) q13lay -outputlayer q14lay |
| or ( and met1 critAreaStress ) q14lay -outputlayer q15lay |
| or ( and via1 critAreaStress ) q15lay -outputlayer q16lay |
| or ( and met2 critAreaStress ) q16lay -outputlayer q17lay |
| or ( and via2 critAreaStress ) q17lay -outputlayer q18lay |
| or ( and met3 critAreaStress ) q18lay -outputlayer q19lay |
| or ( and via3 critAreaStress ) q19lay -outputlayer q20lay |
| or ( and met4 critAreaStress ) q20lay -outputlayer q21lay |
| or ( and via4 critAreaStress ) q21lay -outputlayer q22lay |
| or ( and met5 critAreaStress ) q22lay -outputlayer q23lay |
| or ( and v12 critAreaStress ) q23lay -outputlayer q24lay |
| or ( and pad critAreaStress ) q24lay -outputlayer q25lay |
| or ( and pnp critAreaStress ) q25lay -outputlayer q26lay |
| copy q26lay -outputlayer allay |
| density allay -le 0 -window 50 -step 25 -rdb anchor.1_density.db -outputlayer openArea |
| with_width ( and openArea ( select -interact critAreaStress ( and critAreaStress SEALID ) ) ) -ge 50.0 -outputlayer openAreaAnc |
| rule "anchor.CON.1" { |
| caption "anchor.CON.1: Open area anchors needed in any open window of 50umx50um in areaid:critCorner or areaid:critSid area" |
| copy openAreaAnc |
| } |
| rule "poly.anchor.WID.1" { |
| caption "poly.anchor.WID.1: Min width of poly overlapping anchor < 3.0" |
| inte ( and poly anchorStress ) -lt 3.0 -abut -lt 90 -single_point -output region |
| } |
| rule "li.anchor.WID.1" { |
| caption "li.anchor.WID.1: Min width of li overlapping anchor < 3.0" |
| inte ( and li anchorStress ) -lt 3.0 -abut -lt 90 -single_point -output region |
| } |
| rule "met1.anchor.WID.1" { |
| caption "met1.anchor.WID.1: Min width of met1 overlapping anchor < 3.0" |
| inte ( and met1 anchorStress ) -lt 3.0 -abut -lt 90 -single_point -output region |
| } |
| rule "met2.anchor.WID.1" { |
| caption "met2.anchor.WID.1: Min width of met2 overlapping anchor < 3.0" |
| inte ( and met2 anchorStress ) -lt 3.0 -abut -lt 90 -single_point -output region |
| } |
| rule "met3.anchor.WID.1" { |
| caption "met3.anchor.WID.1: Min width of met3 overlapping anchor < 3.0" |
| inte ( and met3 anchorStress ) -lt 3.0 -abut -lt 90 -single_point -output region |
| } |
| rule "met4.anchor.WID.1" { |
| caption "met4.anchor.WID.1: Min width of met4 overlapping anchor < 3.0" |
| inte ( and met4 anchorStress ) -lt 3.0 -abut -lt 90 -single_point -output region |
| } |
| rule "met5.anchor.WID.1" { |
| caption "met5.anchor.WID.1: Min width of met5 overlapping anchor < 3.0" |
| inte ( and met5 anchorStress ) -lt 3.0 -abut -lt 90 -single_point -output region |
| } |
| rule "anchor.SP.1" { |
| caption "anchor.SP.1: Min spacing/notch of anchor < 5.0" |
| exte anchorStress -lt 5.0 -abut -lt 90 -single_point -output region |
| } |
| and licon anchorStress -outputlayer licon_anc |
| and via1 anchorStress -outputlayer via1_anc |
| and via2 anchorStress -outputlayer via2_anc |
| and via3 anchorStress -outputlayer via3_anc |
| and via4 anchorStress -outputlayer via4_anc |
| and mcon anchorStress -outputlayer mcon_anc |
| rule "licon.mcon.anchor.CON.2" { |
| caption "licon.mcon.anchor.CON.2: licon in anchor must not overlap mcon in anchor" |
| and licon_anc mcon_anc |
| } |
| rule "licon.via1.anchor.CON.2" { |
| caption "licon.via1.anchor.CON.2: licon in anchor must not overlap via1 in anchor" |
| and licon_anc via1_anc |
| } |
| rule "licon.via2.anchor.CON.2" { |
| caption "licon.via2.anchor.CON.2: licon in anchor must not overlap via2 in anchor" |
| and licon_anc via2_anc |
| } |
| rule "licon.via3.anchor.CON.2" { |
| caption "licon.via3.anchor.CON.2: licon in anchor must not overlap via3 in anchor" |
| and licon_anc via3_anc |
| } |
| rule "licon.via4.anchor.CON.2" { |
| caption "licon.via4.anchor.CON.2: licon in anchor must not overlap via4 in anchor" |
| and licon_anc via4_anc |
| } |
| rule "via1.via2.anchor.CON.2" { |
| caption "via1.via2.anchor.CON.2: via1 in anchor must not overlap via2 in anchor" |
| and via1_anc via2_anc |
| } |
| rule "via1.via3.anchor.CON.2" { |
| caption "via1.via3.anchor.CON.2: via1 in anchor must not overlap via3 in anchor" |
| and via1_anc via3_anc |
| } |
| rule "via1.via4.anchor.CON.2" { |
| caption "via1.via4.anchor.CON.2: via1 in anchor must not overlap via4 in anchor" |
| and via1_anc via4_anc |
| } |
| rule "via1.mcon.anchor.CON.2" { |
| caption "via1.mcon.anchor.CON.2: via1 in anchor must not overlap mcon in anchor" |
| and via1_anc mcon_anc |
| } |
| rule "via2.via3.anchor.CON.2" { |
| caption "via2.via3.anchor.CON.2: via2 in anchor must not overlap via3 in anchor" |
| and via2_anc via3_anc |
| } |
| rule "via2.via4.anchor.CON.2" { |
| caption "via2.via4.anchor.CON.2: via2 in anchor must not overlap via4 in anchor" |
| and via2_anc via4_anc |
| } |
| rule "via2.mcon.anchor.CON.2" { |
| caption "via2.mcon.anchor.CON.2: via2 in anchor must not overlap mcon in anchor" |
| and via2_anc mcon_anc |
| } |
| rule "via3.via4.anchor.CON.2" { |
| caption "via3.via4.anchor.CON.2: via3 in anchor must not overlap via4 in anchor" |
| and via3_anc via4_anc |
| } |
| rule "via3.mcon.anchor.CON.2" { |
| caption "via3.mcon.anchor.CON.2: via3 in anchor must not overlap mcon in anchor" |
| and via3_anc mcon_anc |
| } |
| rule "via4.mcon.anchor.CON.2" { |
| caption "via4.mcon.anchor.CON.2: via4 in anchor must not overlap mcon in anchor" |
| and via4_anc mcon_anc |
| } |
| rule "licon.anchor.SP.1" { |
| caption "licon.anchor.SP.1: Min spacing of licon overlapping anchor < 2.93" |
| exte licon_anc -lt 2.93 -abut -lt 90 -single_point -output region |
| } |
| rule "mcon.anchor.SP.1" { |
| caption "mcon.anchor.SP.1: Min spacing of mcon overlapping anchor < 2.93" |
| exte mcon_anc -lt 2.93 -abut -lt 90 -single_point -output region |
| } |
| rule "via1.anchor.SP.1" { |
| caption "via1.anchor.SP.1: Min spacing of via1 overlapping anchor < 2.95" |
| exte via1_anc -lt 2.95 -abut -lt 90 -single_point -output region |
| } |
| rule "via2.anchor.SP.1" { |
| caption "via2.anchor.SP.1: Min spacing of via2 overlapping anchor < 2.9" |
| exte via2_anc -lt 2.9 -abut -lt 90 -single_point -output region |
| } |
| rule "via3.anchor.SP.1" { |
| caption "via3.anchor.SP.1: Min spacing of via3 overlapping anchor < 2.9" |
| exte via3_anc -lt 2.9 -abut -lt 90 -single_point -output region |
| } |
| rule "via4.anchor.SP.1" { |
| caption "via4.anchor.SP.1: Min spacing of via4 overlapping anchor < 2.3" |
| exte via4_anc -lt 2.3 -abut -lt 90 -single_point -output region |
| } |
| select -cut met1 anchorStress -outputlayer met1CrossAnc |
| select -outside via0 anchorStress -outputlayer via1LowOutsideAnc |
| select -outside via1 anchorStress -outputlayer via1UppOutsideAnc |
| or ( select -interact met1CrossAnc ( and met1CrossAnc via1LowOutsideAnc ) ) ( select -interact met1CrossAnc ( and met1CrossAnc via1UppOutsideAnc ) ) -outputlayer met1CrossAncCon |
| rule "met1.anchor.connect.CON.1" { |
| caption "met1.anchor.connect.CON.1: met1 inside ANCHOR region cannot connect to any other metal bus" |
| copy met1CrossAncCon |
| } |
| select -cut met2 anchorStress -outputlayer met2CrossAnc |
| select -outside via1 anchorStress -outputlayer via2LowOutsideAnc |
| select -outside via2 anchorStress -outputlayer via2UppOutsideAnc |
| or ( select -interact met2CrossAnc ( and met2CrossAnc via2LowOutsideAnc ) ) ( select -interact met2CrossAnc ( and met2CrossAnc via2UppOutsideAnc ) ) -outputlayer met2CrossAncCon |
| rule "met2.anchor.connect.CON.1" { |
| caption "met2.anchor.connect.CON.1: met2 inside ANCHOR region cannot connect to any other metal bus" |
| copy met2CrossAncCon |
| } |
| select -cut met3 anchorStress -outputlayer met3CrossAnc |
| select -outside via2 anchorStress -outputlayer via3LowOutsideAnc |
| select -outside via3 anchorStress -outputlayer via3UppOutsideAnc |
| or ( select -interact met3CrossAnc ( and met3CrossAnc via3LowOutsideAnc ) ) ( select -interact met3CrossAnc ( and met3CrossAnc via3UppOutsideAnc ) ) -outputlayer met3CrossAncCon |
| rule "met3.anchor.connect.CON.1" { |
| caption "met3.anchor.connect.CON.1: met3 inside ANCHOR region cannot connect to any other metal bus" |
| copy met3CrossAncCon |
| } |
| select -cut met4 anchorStress -outputlayer met4CrossAnc |
| select -outside via3 anchorStress -outputlayer via4LowOutsideAnc |
| select -outside via4 anchorStress -outputlayer via4UppOutsideAnc |
| or ( select -interact met4CrossAnc ( and met4CrossAnc via4LowOutsideAnc ) ) ( select -interact met4CrossAnc ( and met4CrossAnc via4UppOutsideAnc ) ) -outputlayer met4CrossAncCon |
| rule "met4.anchor.connect.CON.1" { |
| caption "met4.anchor.connect.CON.1: met4 inside ANCHOR region cannot connect to any other metal bus" |
| copy met4CrossAncCon |
| } |
| select -cut met5 anchorStress -outputlayer met5CrossAnc |
| select -outside via4 anchorStress -outputlayer BONDPADLowOutsideAnc |
| select -interact met5CrossAnc ( and met5CrossAnc BONDPADLowOutsideAnc ) -outputlayer met5CrossAncCon |
| rule "met5.anchor.connect.CON.1" { |
| caption "met5.anchor.connect.CON.1: met5 of ANCHOR cannot connect to any other metal bus" |
| copy met5CrossAncCon |
| } |
| rule "poly.licon.anchor.WARN.1" { |
| caption "poly.licon.anchor.WARN.1: This poly anchor region must contain additional licon" |
| not ( inte ( select -interact poly licon_anc ) -lt 3.5 -abut -lt 90 -metric opposite -para -output region_centerline 0.10 ) ( select -interact licon ( select -interact poly licon_anc ) ) -outputlayer center_anchor |
| edge_boolean -coincident_only -not center_anchor poly -outputlayer center_anchor_edge_len_a |
| edge_boolean -coincident_only -not center_anchor_edge_len_a licon -outputlayer center_anchor_edge_len |
| edge_length center_anchor_edge_len -gt 10 -outputlayer error_anchor |
| and ( edge_expand error_anchor -outside_by 3 ) poly -outputlayer exp_err_anc1 |
| and ( edge_expand error_anchor -inside_by 3 ) poly -outputlayer exp_err_anc2 |
| or exp_err_anc1 exp_err_anc2 |
| } |
| rule "li.licon.anchor.WARN.1" { |
| caption "li.licon.anchor.WARN.1: This li anchor region must contain additional licon" |
| not ( inte ( select -interact li licon_anc ) -lt 3.5 -abut -lt 90 -metric opposite -para -output region_centerline 0.10 ) ( select -interact licon ( select -interact li licon_anc ) ) -outputlayer center_anchor |
| edge_boolean -coincident_only -not center_anchor li -outputlayer center_anchor_edge_len_a |
| edge_boolean -coincident_only -not center_anchor_edge_len_a licon -outputlayer center_anchor_edge_len |
| edge_length center_anchor_edge_len -gt 10 -outputlayer error_anchor |
| and ( edge_expand error_anchor -outside_by 3 ) li -outputlayer exp_err_anc1 |
| and ( edge_expand error_anchor -inside_by 3 ) li -outputlayer exp_err_anc2 |
| or exp_err_anc1 exp_err_anc2 |
| } |
| rule "li.mcon.anchor.WARN.1" { |
| caption "li.mcon.anchor.WARN.1: This li anchor region must contain additional mcon" |
| not ( inte ( select -interact li mcon_anc ) -lt 3.5 -abut -lt 90 -metric opposite -para -output region_centerline 0.10 ) ( select -interact mcon ( select -interact li mcon_anc ) ) -outputlayer center_anchor |
| edge_boolean -coincident_only -not center_anchor li -outputlayer center_anchor_edge_len_a |
| edge_boolean -coincident_only -not center_anchor_edge_len_a mcon -outputlayer center_anchor_edge_len |
| edge_length center_anchor_edge_len -gt 10 -outputlayer error_anchor |
| and ( edge_expand error_anchor -outside_by 3 ) li -outputlayer exp_err_anc1 |
| and ( edge_expand error_anchor -inside_by 3 ) li -outputlayer exp_err_anc2 |
| or exp_err_anc1 exp_err_anc2 |
| } |
| rule "met1.mcon.anchor.WARN.1" { |
| caption "met1.mcon.anchor.WARN.1: This met1 anchor region must contain additional mcon" |
| not ( inte ( select -interact met1 mcon_anc ) -lt 3.5 -abut -lt 90 -metric opposite -para -output region_centerline 0.10 ) ( select -interact mcon ( select -interact met1 mcon_anc ) ) -outputlayer center_anchor |
| edge_boolean -coincident_only -not center_anchor met1 -outputlayer center_anchor_edge_len_a |
| edge_boolean -coincident_only -not center_anchor_edge_len_a mcon -outputlayer center_anchor_edge_len |
| edge_length center_anchor_edge_len -gt 10 -outputlayer error_anchor |
| and ( edge_expand error_anchor -outside_by 3 ) met1 -outputlayer exp_err_anc1 |
| and ( edge_expand error_anchor -inside_by 3 ) met1 -outputlayer exp_err_anc2 |
| or exp_err_anc1 exp_err_anc2 |
| } |
| rule "met1.via1.anchor.WARN.1" { |
| caption "met1.via1.anchor.WARN.1: This met1 anchor region must contain additional via1" |
| not ( inte ( select -interact met1 via1_anc ) -lt 3.5 -abut -lt 90 -metric opposite -para -output region_centerline 0.10 ) ( select -interact via1 ( select -interact met1 via1_anc ) ) -outputlayer center_anchor |
| edge_boolean -coincident_only -not center_anchor met1 -outputlayer center_anchor_edge_len_a |
| edge_boolean -coincident_only -not center_anchor_edge_len_a via1 -outputlayer center_anchor_edge_len |
| edge_length center_anchor_edge_len -gt 10 -outputlayer error_anchor |
| and ( edge_expand error_anchor -outside_by 3 ) met1 -outputlayer exp_err_anc1 |
| and ( edge_expand error_anchor -inside_by 3 ) met1 -outputlayer exp_err_anc2 |
| or exp_err_anc1 exp_err_anc2 |
| } |
| rule "met2.via1.anchor.WARN.1" { |
| caption "met2.via1.anchor.WARN.1: This met2 anchor region must contain additional via1" |
| not ( inte ( select -interact met2 via1_anc ) -lt 3.5 -abut -lt 90 -metric opposite -para -output region_centerline 0.10 ) ( select -interact via1 ( select -interact met2 via1_anc ) ) -outputlayer center_anchor |
| edge_boolean -coincident_only -not center_anchor met2 -outputlayer center_anchor_edge_len_a |
| edge_boolean -coincident_only -not center_anchor_edge_len_a via1 -outputlayer center_anchor_edge_len |
| edge_length center_anchor_edge_len -gt 10 -outputlayer error_anchor |
| and ( edge_expand error_anchor -outside_by 3 ) met2 -outputlayer exp_err_anc1 |
| and ( edge_expand error_anchor -inside_by 3 ) met2 -outputlayer exp_err_anc2 |
| or exp_err_anc1 exp_err_anc2 |
| } |
| rule "met2.via2.anchor.WARN.1" { |
| caption "met2.via2.anchor.WARN.1: This met2 anchor region must contain additional via2" |
| not ( inte ( select -interact met2 via2_anc ) -lt 3.5 -abut -lt 90 -metric opposite -para -output region_centerline 0.10 ) ( select -interact via2 ( select -interact met2 via2_anc ) ) -outputlayer center_anchor |
| edge_boolean -coincident_only -not center_anchor met2 -outputlayer center_anchor_edge_len_a |
| edge_boolean -coincident_only -not center_anchor_edge_len_a via2 -outputlayer center_anchor_edge_len |
| edge_length center_anchor_edge_len -gt 10 -outputlayer error_anchor |
| and ( edge_expand error_anchor -outside_by 3 ) met2 -outputlayer exp_err_anc1 |
| and ( edge_expand error_anchor -inside_by 3 ) met2 -outputlayer exp_err_anc2 |
| or exp_err_anc1 exp_err_anc2 |
| } |
| rule "met3.via2.anchor.WARN.1" { |
| caption "met3.via2.anchor.WARN.1: This met3 anchor region must contain additional via2" |
| not ( inte ( select -interact met3 via2_anc ) -lt 3.5 -abut -lt 90 -metric opposite -para -output region_centerline 0.10 ) ( select -interact via2 ( select -interact met3 via2_anc ) ) -outputlayer center_anchor |
| edge_boolean -coincident_only -not center_anchor met3 -outputlayer center_anchor_edge_len_a |
| edge_boolean -coincident_only -not center_anchor_edge_len_a via2 -outputlayer center_anchor_edge_len |
| edge_length center_anchor_edge_len -gt 10 -outputlayer error_anchor |
| and ( edge_expand error_anchor -outside_by 3 ) met3 -outputlayer exp_err_anc1 |
| and ( edge_expand error_anchor -inside_by 3 ) met3 -outputlayer exp_err_anc2 |
| or exp_err_anc1 exp_err_anc2 |
| } |
| rule "met3.via3.anchor.WARN.1" { |
| caption "met3.via3.anchor.WARN.1: This met3 anchor region must contain additional via3" |
| not ( inte ( select -interact met3 via3_anc ) -lt 3.5 -abut -lt 90 -metric opposite -para -output region_centerline 0.10 ) ( select -interact via3 ( select -interact met3 via3_anc ) ) -outputlayer center_anchor |
| edge_boolean -coincident_only -not center_anchor met3 -outputlayer center_anchor_edge_len_a |
| edge_boolean -coincident_only -not center_anchor_edge_len_a via3 -outputlayer center_anchor_edge_len |
| edge_length center_anchor_edge_len -gt 10 -outputlayer error_anchor |
| and ( edge_expand error_anchor -outside_by 3 ) met3 -outputlayer exp_err_anc1 |
| and ( edge_expand error_anchor -inside_by 3 ) met3 -outputlayer exp_err_anc2 |
| or exp_err_anc1 exp_err_anc2 |
| } |
| rule "met4.via3.anchor.WARN.1" { |
| caption "met4.via3.anchor.WARN.1: This met4 anchor region must contain additional via3" |
| not ( inte ( select -interact met4 via3_anc ) -lt 3.5 -abut -lt 90 -metric opposite -para -output region_centerline 0.10 ) ( select -interact via3 ( select -interact met4 via3_anc ) ) -outputlayer center_anchor |
| edge_boolean -coincident_only -not center_anchor met4 -outputlayer center_anchor_edge_len_a |
| edge_boolean -coincident_only -not center_anchor_edge_len_a via3 -outputlayer center_anchor_edge_len |
| edge_length center_anchor_edge_len -gt 10 -outputlayer error_anchor |
| and ( edge_expand error_anchor -outside_by 3 ) met4 -outputlayer exp_err_anc1 |
| and ( edge_expand error_anchor -inside_by 3 ) met4 -outputlayer exp_err_anc2 |
| or exp_err_anc1 exp_err_anc2 |
| } |
| |
| #ENDIF |
| |
| |
| |
| // |
| // DEEP NWELL (DNWELL) checks |
| // |
| |
| ////DISCONNECT |
| //////npccon = npc AND licon |
| ////CONNECT dnwell nwell |
| ////CONNECT nwell tap BY NTAP |
| ////CONNECT tap li BY licon |
| ////CONNECT poly li BY npccon |
| ////CONNECT li met1 BY mcon |
| ////CONNECT met1 met2 BY via1 |
| ////CONNECT met3 met2 BY via2 |
| ////CONNECT met3 met4 BY via3_c |
| ////CONNECT met4 met5 BY via4_c |
| ////CONNECT met5 pad |
| ////CONNECT rdl pad |
| |
| and dnwell v20 -outputlayer dnwell_in_v20 |
| rule "dnwell.WID.1" { |
| caption "dnwell.WID.1: Min width of deep nwell < 3.0" |
| inte dnwell -lt 3.0 -abut -lt 90 -single_point -output region |
| } |
| rule "dnwell.SP.1" { |
| caption "dnwell.SP.1: Min spacing/notch of deep nwell (exempt inside v20) < 6.3" |
| exte ( select -outside dnwell v20 ) -lt 6.3 -abut -lt 90 -single_point -output region |
| } |
| rule "dnwell.CON.1" { |
| caption "dnwell.CON.1: deep nwell cannot overlap pnp drawing layer" |
| and dnwell pnp |
| } |
| rule "dnwell.CON.2" { |
| caption "dnwell.CON.2: pdiff cannot straddle deep nwell" |
| select -cut ( and diffi psdm ) dnwell |
| } |
| rule "dnwell.CON.3" { |
| caption "dnwell.CON.3: deep nwell cannot straddle areaid:substratecut layer" |
| and ( select -cut dnwell localSub ) localSub |
| } |
| rule "dnwell.CON.4" { |
| caption "dnwell.CON.4: dnwell must interact with nwell" |
| select -interact -not dnwell nwell |
| } |
| rule "dnwell.SP.2" { |
| caption "dnwell.SP.2: Min spacing of dnwell in v20 on same net < 2.5" |
| exte dnwell_in_v20 -lt 2.5 -abut -lt 90 -single_point -output region -connected |
| } |
| rule "dnwell.SP.3" { |
| caption "dnwell.SP.3: Min spacing of dwnell in v20 not on same net < 12.0" |
| exte dnwell_in_v20 -lt 12.0 -abut -lt 90 -single_point -output region -not_connected |
| } |
| rule "dnwell.SP.4" { |
| caption "dnwell.SP.4: Min spacing of dnwell in v20 to dnwell outside v20 < 12.0" |
| exte dnwell_in_v20 ( not dnwell v20 ) -lt 12.0 -abut -lt 90 -single_point -output region |
| } |
| rule "dnwell.SP.5" { |
| caption "dnwell.SP.5: Min spacing of dnwell in v20 to nwell outside v20 < 9.5" |
| exte dnwell_in_v20 ( not nwell v20 ) -lt 9.5 -abut -lt 90 -single_point -output region |
| } |
| |
| |
| // |
| // Nwell checks |
| // |
| |
| |
| |
| extent_cell "*_tech_CD_top*" -outputlayer tech_CD_top_cells |
| not dnwell tech_CD_top_cells -outputlayer dnwellNotTechCD |
| not nwell tech_CD_top_cells -outputlayer nwellNotTechCD |
| or v20 tech_CD_top_cells -outputlayer nwell_exempted_regions |
| select -interact nwell v20 -outputlayer nw_20v_1 |
| stamp nw_20v_1 nwell -outputlayer nw_20v |
| not nwell nw_20v -outputlayer nw_not_20v |
| select -interact nw_not_20v v12 -outputlayer nw_12v_1 |
| stamp nw_12v_1 nwell -outputlayer nw_12v |
| not nwell ( or nw_20v nw_12v ) -outputlayer nw_not_20v_or_12v |
| select -interact nw_not_20v_or_12v v5 -outputlayer nw_5v_1 |
| stamp nw_5v_1 nwell -outputlayer nw_5v |
| select -interact -not nwell ( or v5 v12 v20 ) -outputlayer nw_1p8v_1 |
| stamp nw_1p8v_1 nwell -outputlayer nw_1p8v |
| select -interact -not nwell v20 -outputlayer nwell_outside_v20 |
| rule "nwell.WID.1" { |
| caption "nwell.WID.1: Min width of nwell < 0.84" |
| inte nwell -lt 0.84 -abut -lt 90 -single_point -output region |
| } |
| rule "nwell.SP.1" { |
| caption "nwell.SP.1: Min spacing/notch of 1.8v nwell < 1.27" |
| exte nw_1p8v -lt 1.27 -abut -lt 90 -single_point -output region |
| } |
| rule "nwell.SP.2" { |
| caption "nwell.SP.2: Min spacing of 1.8v nwell to 5v nwell < 1.27" |
| exte nw_1p8v nw_5v -lt 1.27 -abut -lt 90 -single_point -output region |
| } |
| rule "nwell.SP.3" { |
| caption "nwell.SP.3: Min spacing of 1.8v nwell to 12v nwell < 2.0" |
| exte nw_1p8v nw_12v -lt 2.0 -abut -lt 90 -single_point -output region |
| } |
| rule "nwell.SP.4" { |
| caption "nwell.SP.4: Min spacing of 1.8v nwell to 20v nwell < 2.5" |
| exte nw_1p8v nw_20v -lt 2.5 -abut -lt 90 -single_point -output region |
| } |
| rule "nwell.SP.5" { |
| caption "nwell.SP.5: Min spacing/notch of 5v nwell to 5v nwell < 1.27" |
| exte nw_5v -lt 1.27 -abut -lt 90 -single_point -output region |
| } |
| rule "nwell.SP.6" { |
| caption "nwell.SP.6: Min spacing of 5v nwell to 12v nwell < 2.0" |
| exte nw_5v nw_12v -lt 2.0 -abut -lt 90 -single_point -output region |
| } |
| rule "nwell.SP.7" { |
| caption "nwell.SP.7: Min spacing of 5v nwell to 20v nwell < 2.5" |
| exte nw_5v nw_20v -lt 2.5 -abut -lt 90 -single_point -output region |
| } |
| rule "nwell.SP.8" { |
| caption "nwell.SP.8: Min spacing/notch of 12v nwell to 12v nwell < 2.0" |
| exte nw_12v -lt 2.0 -abut -lt 90 -single_point -output region |
| } |
| rule "nwell.SP.9" { |
| caption "nwell.SP.9: Min spacing of 12v nwell to 20v nwell < 2.5" |
| exte nw_12v nw_20v -lt 2.5 -abut -lt 90 -single_point -output region |
| } |
| rule "nwell.SP.10" { |
| caption "nwell.SP.10: Min spacing/notch of 20v nwell < 2.5" |
| exte nw_20v -lt 2.5 -abut -lt 90 -single_point -output region |
| } |
| rule "nwell.OVL.1" { |
| caption "nwell.OVL.1: nwell must connect by ntap at least once" |
| select -enclose -not nwell ntap |
| } |
| rule "nwell.ENC.1" { |
| caption "nwell.ENC.1: Min enclosure of deep nwell by nwell < 0.4 (Rule exempted inside v20 and in cell names with '*_tech_CD_top*')" |
| enc ( not dnwell nwell_exempted_regions ) ( not nwell nwell_exempted_regions ) -lt 0.4 -measure all -abut -lt 90 -single_point -output region |
| } |
| rule "nwell.ENC.2" { |
| caption "nwell.ENC.2: Min enclosure of nwell hole by dnwell outside v20 and in cell names with '*_tech_CD_top*' < 1.03" |
| enc ( select -outside nwellHoles nwell_exempted_regions ) ( select -outside dnwell nwell_exempted_regions ) -lt 1.03 -measure all -abut -lt 90 -single_point -output region |
| } |
| rule "nwell.SP.11" { |
| caption "nwell.SP.11: Min spacing between (nwell AND deep nwell) on separate nets outside of cell names with '*_tech_CD_top*' < 4.5" |
| exte dnwellNotTechCD nwellNotTechCD -lt 4.5 -measure all -not_connected -output region |
| } |
| rule "nwell.ENC.3" { |
| caption "nwell.ENC.3: dnwell must completely enclose nwell inside v20" |
| not nw_v20 dnwell_v20 |
| } |
| rule "nwell.CON.1" { |
| caption "nwell.CON.1: different voltage nwell should not be on the same net" |
| antenna nw_1p8v nw_5v -gt 0 |
| antenna nw_1p8v nw_12v -gt 0 |
| antenna nw_1p8v nw_20v -gt 0 |
| antenna nw_5v nw_1p8v -gt 0 |
| antenna nw_5v nw_12v -gt 0 |
| antenna nw_5v nw_20v -gt 0 |
| antenna nw_12v nw_1p8v -gt 0 |
| antenna nw_12v nw_5v -gt 0 |
| antenna nw_12v nw_20v -gt 0 |
| antenna nw_20v nw_1p8v -gt 0 |
| antenna nw_20v nw_5v -gt 0 |
| antenna nw_20v nw_12v -gt 0 |
| } |
| rule "nwell.CON.2" { |
| caption "hnwell.CON.2: N-well marked with v5, v12 or v20 must be enclosed by thkox" |
| not ( or nw_5v nw_12_20v ) thkox |
| } |
| rule "nwell.CON.3" { |
| caption "hnwell.CON.3: N-well connected to 5v source or drain must have v5 marker" |
| and psd v5 -outputlayer psd_v5 |
| and nsd v5 -outputlayer nsd_v5 |
| select -interact -not ( antenna nwell psd_v5 -gt 0 ) v5 |
| select -interact -not ( antenna nwell nsd_v5 -gt 0 ) v5 |
| } |
| rule "nwell.CON.4" { |
| caption "nwell.CON.4: N-well connected to 12v source or drain must have v12 marker" |
| and psd v12 -outputlayer psd_v12 |
| and nsd v12 -outputlayer nsd_v12 |
| select -interact -not ( antenna nwell psd_v12 -gt 0 ) v12 |
| select -interact -not ( antenna nwell nsd_v12 -gt 0 ) v12 |
| } |
| rule "nwell.CON.5" { |
| caption "nwell.CON.5: N-well connected to 20v source or drain must have v20 marker" |
| and psd v20 -outputlayer psd_v20 |
| and nsd v20 -outputlayer nsd_v20 |
| select -interact -not ( antenna nwell psd_v20 -gt 0 ) v20 |
| select -interact -not ( antenna nwell nsd_v20 -gt 0 ) v20 |
| } |
| |
| |
| // |
| // Antenna checks |
| // |
| |
| #IFNDEF SKIP_ANTENNA_CHECKS |
| disconnect |
| |
| |
| not ( not tap poly ) nwell -outputlayer Ant_short |
| not diffTap poly -outputlayer SRCDRNTAP |
| not SRCDRNTAP Ant_short -outputlayer Ant_diode |
| and poly diffTap -outputlayer Gate_ant |
| |
| |
| connect poly Gate_ant |
| |
| |
| antenna poly Gate_ant -gt 50 -expr " PERIMETER(poly) * 0.180000 / AREA(Gate_ant) " -rdb ar_poly.db poly Gate_ant -by_layer -outputlayer ar_poly |
| rule "poly.ANT.1" { |
| caption "poly.ANT.1: Max ratio poly perimter area/gate area > 50" |
| select -interact Gate_ant ar_poly |
| } |
| |
| |
| connect poly Licon |
| |
| |
| antenna Licon Gate_ant -gt 3 -rdb ar_licon.db Licon Gate_ant -by_layer -outputlayer ar_licon |
| rule "licon.ANT.1" { |
| caption "licon.ANT.1: Max ratio licon area/gate area > 3" |
| select -interact Gate_ant ( select -interact poly ar_licon ) |
| } |
| |
| |
| connect Li poly -by Licon |
| connect Li SRCDRNTAP -by licon |
| connect Li Ant_diode -by licon |
| connect Li Ant_short -by licon |
| |
| |
| antenna Gate_ant Ant_short -eq 0 -outputlayer fgate_1 |
| antenna fgate_1 Li Ant_diode -gt 0.0 -expr " (((PERIMETER(Li) * 0.100000 / AREA(fgate_1))-75)/450)-(AREA(Ant_diode)*!!AREA(fgate_1)) " -rdb ar_Li.db fgate_1 Li Ant_diode -by_layer -outputlayer ar_li |
| rule "li.ANT.1" { |
| caption "li.ANT.1: Max ratio li perimeter/gate area > 75" |
| copy ar_li |
| } |
| |
| |
| connect li mcon |
| |
| |
| antenna Gate_ant Ant_short -eq 0 -outputlayer fgate_2 |
| antenna fgate_2 mcon ANT_diode -gt 0.0 -expr " (((AREA(mcon)/AREA(fgate_2))-3)/18)-(AREA(Ant_diode)*!!AREA(fgate_2)) " -rdb ar_mcon.db fgate_2 mcon ANT_diode -by_layer -outputlayer ar_mcon |
| rule "mcon.ANT.1" { |
| caption "mcon.ANT.1: Max ratio mcon area/gate area > 3" |
| copy ar_mcon |
| } |
| |
| |
| connect met1 li -by mcon |
| |
| |
| antenna Gate_ant Ant_short -eq 0 -outputlayer fgate_3 |
| antenna fgate_3 Met1 Ant_diode -gt 0.0 -expr " ((((PERIMETER(Met1) * 0.350000 / AREA(fgate_3))-400)-(!!AREA(Ant_diode)*2200))/400)-(AREA(Ant_diode)*!!AREA(fgate_3)) " -rdb ar_met1.db fgate_3 Met1 Ant_diode -by_layer -outputlayer ar_met1 |
| rule "met1.ANT.1" { |
| caption "met1.ANT.1: Max ratio met1 perimeter/gate area > 400" |
| copy ar_met1 |
| } |
| |
| |
| connect Met1 Via1 |
| |
| |
| antenna Gate_ant Ant_short -eq 0 -outputlayer fgate_4 |
| antenna fgate_4 Via1 ANT_diode -gt 0.0 -expr " (((AREA(Via1)/AREA(fgate_4))-6)/36)-(AREA(Ant_diode)*!!AREA(fgate_4)) " -rdb ar_via.db fgate_4 Via1 ANT_diode -by_layer -outputlayer ar_via |
| rule "via1.ANT.1" { |
| caption "via1.ANT.1: Max ratio via1 area/gate area > 6" |
| copy ar_via |
| } |
| |
| |
| connect Met2 Met1 -by Via1 |
| |
| |
| antenna Gate_ant Ant_short -eq 0 -outputlayer fgate_5 |
| antenna fgate_5 Met2 Ant_diode -gt 0.0 -expr " ((((PERIMETER(Met2) * 0.350000 / AREA(fgate_5))-400)-(!!AREA(Ant_diode)*2200))/400)-(AREA(Ant_diode)*!!AREA(fgate_5)) " -rdb ar_met2.db fgate_5 Met2 Ant_diode -by_layer -outputlayer ar_met2 |
| rule "met2.ANT.1" { |
| caption "met2.ANT.1: Max ratio met2 perimeter/gate area > 400" |
| copy ar_met2 |
| } |
| |
| |
| connect Met2 Via2 |
| |
| |
| antenna Gate_ant Ant_short -eq 0 -outputlayer fgate_6 |
| antenna fgate_6 Via2 ANT_diode -gt 0.0 -expr " (((AREA(Via2)/AREA(fgate_6))-6)/36)-(AREA(Ant_diode)*!!AREA(fgate_6)) " -rdb ar_via2.db fgate_6 Via2 ANT_diode -by_layer -outputlayer ar_via2 |
| rule "via2.ANT.1" { |
| caption "via2.ANT.1: Max ratio via2 area/gate area > 6" |
| copy ar_via2 |
| } |
| |
| |
| connect Met3 Met2 -by Via2 |
| |
| |
| antenna Gate_ant Ant_short -eq 0 -outputlayer fgate_7 |
| antenna fgate_7 Met3 Ant_diode -gt 0.0 -expr " ((((PERIMETER(Met3) * 0.800000 /AREA(fgate_7))-400)-(!!AREA(Ant_diode)*2200))/400)-(AREA(Ant_diode)*!!AREA(fgate_7)) " -rdb ar_met3.db fgate_7 Met3 Ant_diode -by_layer -outputlayer ar_met3 |
| rule "met3.ANT.1" { |
| caption "met3.ANT.1: Max ratio met3 perimeter/gate area > 400" |
| copy ar_met3 |
| } |
| |
| |
| connect Met3 Via3 |
| |
| |
| antenna Gate_ant Ant_short -eq 0 -outputlayer fgate_8 |
| antenna fgate_8 Via3 ANT_diode -gt 0.0 -expr " (((AREA(Via3)/AREA(fgate_8))-6)/36)-(AREA(Ant_diode)*!!AREA(fgate_8)) " -rdb ar_via3.db fgate_8 Via3 ANT_diode -by_layer -outputlayer ar_via3 |
| rule "via3.ANT.1" { |
| caption "via3.ANT.1: Max ratio via3 area/gate area > 6" |
| copy ar_via3 |
| } |
| |
| |
| connect Met4 Met3 -by Via3 |
| |
| |
| antenna Gate_ant Ant_short -eq 0 -outputlayer fgate_9 |
| antenna fgate_9 Met4 Ant_diode -gt 0.0 -expr " ((((PERIMETER(Met4) * 0.800000 /AREA(fgate_9))-400)-(!!AREA(Ant_diode)*2200))/400)-(AREA(Ant_diode)*!!AREA(fgate_9)) " -rdb ar_met4.db fgate_9 Met4 Ant_diode -by_layer -outputlayer ar_met4 |
| rule "met4.ANT.1" { |
| caption "met4.ANT.1: Max ratio met4 perimeter/gate area > 400" |
| copy ar_met4 |
| } |
| |
| |
| connect Met4 Via4 |
| |
| |
| antenna Gate_ant Ant_short -eq 0 -outputlayer fgate_10 |
| antenna fgate_10 Via4 ANT_diode -gt 0.0 -expr " (((AREA(Via4)/AREA(fgate_10))-6)/36)-(AREA(Ant_diode)*!!AREA(fgate_10)) " -rdb ar_via4.db fgate_10 Via4 ANT_diode -by_layer -outputlayer ar_via4 |
| rule "via4.ANT.1" { |
| caption "via4.ANT.1: Max ratio via4 area/gate area > 6" |
| copy ar_via4 |
| } |
| |
| |
| connect Met5 Met4 -by Via4 |
| |
| |
| antenna Gate_ant Ant_short -eq 0 -outputlayer fgate_11 |
| antenna fgate_11 Met5 Ant_diode -gt 0.0 -expr " ((((PERIMETER(Met5) * 1.200000 /AREA(fgate_11))-400)-(!!AREA(Ant_diode)*2200))/400)-(AREA(Ant_diode)*!!AREA(fgate_11)) " -rdb ar_met5.db fgate_11 Met5 Ant_diode -by_layer -outputlayer ar_met5 |
| rule "met5.ANT.1" { |
| caption "met5.ANT.1: Max ratio met5 perimeter/gate area > 400" |
| copy ar_met5 |
| } |
| #IFNDEF SKIP_RECOMMENDED_CHECKS |
| disconnect |
| connect met5 met4 -by via4 |
| connect met4 met3 -by via3 |
| connect met3 met2 -by via2 |
| connect met2 met1 -by via1 |
| connect met1 li -by mcon |
| connect SRCDRN li -by licon |
| connect tap li -by licon |
| connect ptap li -by licon |
| |
| antenna met2 tap -gt 0 -outputlayer met2Conntap |
| antenna met2 SRCDRN -gt 0 -outputlayer met2Conndiff |
| antenna met2 PTAP -gt 0 -outputlayer met2ConnPtap |
| or met2Conntap met2Conndiff -outputlayer met2Conndifftap |
| not met2 met2Conndifftap -outputlayer met2NotConndifftap |
| select -interact met2NotConndifftap via2 -gt 2 -outputlayer met2NotConnVia |
| or met2ConnPtap met2NotConndifftap -outputlayer met2GroundOrFloat |
| select -interact met2GroundOrFloat via2 -gt 2 -outputlayer met2GroundOrFloatVia |
| select -interact met3 via2 -outputlayer met3_via2 |
| and met3_via2 met2GroundOrFloat -outputlayer met3_over_floatingm2 |
| |
| connect met2NotConnVia met3_over_floatingm2 -by via2 |
| connect met2GroundOrFloatVia met3_over_floatingm2 -by via2 |
| |
| antenna met2NotConnVia via2 -ge 20.0 -expr " (2*AREA(met2NotConnVia)+ PERIMETER(met2NotConnVia) * 0.35)/(AREA(via2)) " -outputlayer AR_MM2_more05 |
| antenna met2GroundOrFloatVia via2 -le 31.25 -expr " (2*AREA(met2GroundOrFloatVia)+PERIMETER(met2GroundOrFloatVia)*0.35)/(AREA(via2)) " -outputlayer AR_MM2_less03 |
| not ( exte AR_MM2_more05 AR_MM2_less03 -eq 0.14 -abut -lt 90 -single_point -output region ) STDCID -outputlayer crater |
| rule "met2.ANT.2" { |
| caption "met2.ANT.2: met2 spacing between (met2 areas with met2-to-via2 surface area ratio >=20.0) and (met2 areas with met2-to-via2 surface area ratio <= 31.25) == 0.14" |
| copy crater |
| } |
| |
| #ENDIF //Recomended |
| #ENDIF //Antenna |
| |
| #IFNDEF SKIP_DENSITY_CHECKS |
| size sealid_hole -by -13 -outputlayer chip_and_seal_hole |
| not boundary chip_and_seal_hole -outputlayer chip_not_sealring_hole |
| or chip_and_seal_hole ( select -interact -not boundary SEALID ) -outputlayer fill_extent |
| #IFDEF GENERATE_PREDICTIVE_FILL |
| size met1i -by 0.3 -outputlayer keepout_1_met1 |
| size capacitor -by 3 -outputlayer keepout_2_met1 |
| size target -by 3.295 -outputlayer keepout_3_met1 |
| size nsm -by 1 -outputlayer keepout_4_met1 |
| size dieCut -by 3 -outputlayer keepout_5_met1 |
| size MM1mk -by 0.3 -outputlayer keepout_6_met1 |
| size ( or met1_block cmm1WaffleDrop ) -by 0.3 -outputlayer keepout_7_met1 |
| or keepout_1_met1 keepout_2_met1 keepout_3_met1 keepout_4_met1 keepout_5_met1 keepout_6_met1 keepout_7_met1 -outputlayer keepout_met1_1st |
| not fill_extent keepout_met1_1st -outputlayer target_fill_area_met1_1st |
| rect_gen -width 2.0 -length 2.0 -spacing 0.2 -inside_of LAYER target_fill_area_met1_1st -outputlayer psuedo_fill_met1_1st |
| not target_fill_area_met1_1st ( size psuedo_fill_met1_1st -by 0.3 ) -outputlayer target_fill_area_met1_2nd |
| rect_gen -width 1.0 -length 1.0 -spacing 0.2 -inside_of LAYER target_fill_area_met1_2nd -outputlayer psuedo_fill_met1_2nd |
| not target_fill_area_met1_2nd ( size psuedo_fill_met1_2nd -by 0.3 ) -outputlayer target_fill_area_met1_3rd |
| rect_gen -width 0.58 -length 0.58 -spacing 0.2 -inside_of LAYER target_fill_area_met1_3rd -outputlayer psuedo_fill_met1_3rd |
| or psuedo_fill_met1_1st psuedo_fill_met1_2nd psuedo_fill_met1_3rd -outputlayer psuedo_fill_met1 |
| rule "view_met1_predictive_fill" { |
| copy psuedo_fill_met1 |
| } |
| #ENDIF //predictive fill |
| #IFDEF GENERATE_PREDICTIVE_FILL |
| or met1i psuedo_fill_met1 MM1mk -outputlayer layer_to_check_met1 |
| #ENDIF //predictive fill |
| #IFNDEF GENERATE_PREDICTIVE_FILL |
| or ( size met1i -by 0.6 ) MM1mk -outputlayer layer_to_check_met1 |
| #ENDIF //predictive fill |
| #IFDEF GENERATE_LOCAL_DENSITY |
| rule "met1.local.low.DEN.1" { |
| caption "met1.local.low.DEN.1: Layer met1 local density (200 square micron window stepped at 100) < 30%" |
| density layer_to_check_met1 -lt .30 -window 200 -step 100 -inside_of layer fill_extent -rdb met1_local_low_density.rdb |
| } |
| rule "met1.local.high.DEN.2" { |
| caption "met1.local.high.DEN.2: Layer met1 local density (200 square micron window stepped at 100) > 80%" |
| density layer_to_check_met1 -gt .80 -window 200 -step 100 -inside_of layer fill_extent -rdb met1_local_high_density.rdb |
| } |
| #ENDIF |
| rule "met1.chip.low.DEN.3" { |
| caption "met1.chip.low.DEN.3: Layer met1 chip density (700 square micron window stepped at 70) < 30%" |
| density layer_to_check_met1 -lt .30 -window 700 -step 70 -inside_of layer fill_extent -rdb met1_chip_low_density.rdb |
| } |
| rule "met1.chip.high.DEN.4" { |
| caption "met1.chip.high.DEN.4: Layer met1 chip density (700) square micron window stepped at 70) > 80%" |
| density layer_to_check_met1 -gt .80 -window 700 -step 70 -inside_of layer fill_extent -rdb met1_chip_high_density.rdb |
| } |
| #IFDEF GENERATE_PREDICTIVE_FILL |
| size met2i -by 0.3 -outputlayer keepout_1_met2 |
| size capacitor -by 3 -outputlayer keepout_2_met2 |
| size target -by 3.295 -outputlayer keepout_3_met2 |
| size nsm -by 1 -outputlayer keepout_4_met2 |
| size dieCut -by 3 -outputlayer keepout_5_met2 |
| size MM2mk -by 0.3 -outputlayer keepout_6_met2 |
| size ( or met2_block cmm2WaffleDrop ) -by 0.3 -outputlayer keepout_7_met2 |
| or keepout_1_met2 keepout_2_met2 keepout_3_met2 keepout_4_met2 keepout_5_met2 keepout_6_met2 keepout_7_met2 -outputlayer keepout_met2_1st |
| not fill_extent keepout_met2_1st -outputlayer target_fill_area_met2_1st |
| rect_gen -width 2.0 -length 2.0 -spacing 0.2 -inside_of LAYER target_fill_area_met2_1st -outputlayer psuedo_fill_met2_1st |
| not target_fill_area_met2_1st ( size psuedo_fill_met2_1st -by 0.3 ) -outputlayer target_fill_area_met2_2nd |
| rect_gen -width 1.0 -length 1.0 -spacing 0.2 -inside_of LAYER target_fill_area_met2_2nd -outputlayer psuedo_fill_met2_2nd |
| not target_fill_area_met2_2nd ( size psuedo_fill_met2_2nd -by 0.3 ) -outputlayer target_fill_area_met2_3rd |
| rect_gen -width 0.58 -length 0.58 -spacing 0.2 -inside_of LAYER target_fill_area_met2_3rd -outputlayer psuedo_fill_met2_3rd |
| or psuedo_fill_met2_1st psuedo_fill_met2_2nd psuedo_fill_met2_3rd -outputlayer psuedo_fill_met2 |
| rule "view_met2_predictive_fill" { |
| copy psuedo_fill_met2 |
| } |
| #ENDIF //predictive fill |
| #IFDEF GENERATE_PREDICTIVE_FILL |
| or met2i psuedo_fill_met2 MM2mk -outputlayer layer_to_check_met2 |
| #ENDIF //predictive fill |
| #IFNDEF GENERATE_PREDICTIVE_FILL |
| or ( size met2i -by 0.6 ) MM2mk -outputlayer layer_to_check_met2 |
| #ENDIF //predictive fill |
| #IFDEF GENERATE_LOCAL_DENSITY |
| rule "met2.local.low.DEN.1" { |
| caption "met2.local.low.DEN.1: Layer met2 local density (200 square micron window stepped at 100) < 30%" |
| density layer_to_check_met2 -lt .30 -window 200 -step 100 -inside_of layer fill_extent -rdb met2_local_low_density.rdb |
| } |
| rule "met2.local.high.DEN.2" { |
| caption "met2.local.high.DEN.2: Layer met2 local density (200 square micron window stepped at 100) > 80%" |
| density layer_to_check_met2 -gt .80 -window 200 -step 100 -inside_of layer fill_extent -rdb met2_local_high_density.rdb |
| } |
| #ENDIF |
| rule "met2.chip.low.DEN.3" { |
| caption "met2.chip.low.DEN.3: Layer met2 chip density (700 square micron window stepped at 70) < 30%" |
| density layer_to_check_met2 -lt .30 -window 700 -step 70 -inside_of layer fill_extent -rdb met2_chip_low_density.rdb |
| } |
| rule "met2.chip.high.DEN.4" { |
| caption "met2.chip.high.DEN.4: Layer met2 chip density (700) square micron window stepped at 70) > 80%" |
| density layer_to_check_met2 -gt .80 -window 700 -step 70 -inside_of layer fill_extent -rdb met2_chip_high_density.rdb |
| } |
| #IFDEF GENERATE_PREDICTIVE_FILL |
| size met3i -by 0.3 -outputlayer keepout_1_met3 |
| size capacitor -by 3 -outputlayer keepout_2_met3 |
| size target -by 3.295 -outputlayer keepout_3_met3 |
| size nsm -by 1 -outputlayer keepout_4_met3 |
| size dieCut -by 3 -outputlayer keepout_5_met3 |
| size MM3mk -by 0.3 -outputlayer keepout_6_met3 |
| size ( or met3_block cmm3WaffleDrop ) -by 0.3 -outputlayer keepout_7_met3 |
| or keepout_1_met3 keepout_2_met3 keepout_3_met3 keepout_4_met3 keepout_5_met3 keepout_6_met3 keepout_7_met3 -outputlayer keepout_met3_1st |
| not fill_extent keepout_met3_1st -outputlayer target_fill_area_met3_1st |
| rect_gen -width 2.0 -length 2.0 -spacing 0.3 -inside_of LAYER target_fill_area_met3_1st -outputlayer psuedo_fill_met3_1st |
| not target_fill_area_met3_1st ( size psuedo_fill_met3_1st -by 0.3 ) -outputlayer target_fill_area_met3_2nd |
| rect_gen -width 1.0 -length 1.0 -spacing 0.3 -inside_of LAYER target_fill_area_met3_2nd -outputlayer psuedo_fill_met3_2nd |
| not target_fill_area_met3_2nd ( size psuedo_fill_met3_2nd -by 0.3 ) -outputlayer target_fill_area_met3_3rd |
| rect_gen -width 0.58 -length 0.58 -spacing 0.3 -inside_of LAYER target_fill_area_met3_3rd -outputlayer psuedo_fill_met3_3rd |
| or psuedo_fill_met3_1st psuedo_fill_met3_2nd psuedo_fill_met3_3rd -outputlayer psuedo_fill_met3 |
| rule "view_met3_predictive_fill" { |
| copy psuedo_fill_met3 |
| } |
| #ENDIF //predictive fill |
| #IFDEF GENERATE_PREDICTIVE_FILL |
| or met3i psuedo_fill_met3 MM3mk -outputlayer layer_to_check_met3 |
| #ENDIF //predictive fill |
| #IFNDEF GENERATE_PREDICTIVE_FILL |
| or ( size met3i -by 1.15 ) MM3mk -outputlayer layer_to_check_met3 |
| #ENDIF //predictive fill |
| #IFDEF GENERATE_LOCAL_DENSITY |
| rule "met3.local.low.DEN.1" { |
| caption "met3.local.low.DEN.1: Layer met3 local density (200 square micron window stepped at 100) < 30%" |
| density layer_to_check_met3 -lt .30 -window 200 -step 100 -inside_of layer fill_extent -rdb met3_local_low_density.rdb |
| } |
| rule "met3.local.high.DEN.2" { |
| caption "met3.local.high.DEN.2: Layer met3 local density (200 square micron window stepped at 100) > 80%" |
| density layer_to_check_met3 -gt .80 -window 200 -step 100 -inside_of layer fill_extent -rdb met3_local_high_density.rdb |
| } |
| #ENDIF |
| rule "met3.chip.low.DEN.3" { |
| caption "met3.chip.low.DEN.3: Layer met3 chip density (700 square micron window stepped at 70) < 30%" |
| density layer_to_check_met3 -lt .30 -window 700 -step 70 -inside_of layer fill_extent -rdb met3_chip_low_density.rdb |
| } |
| rule "met3.chip.high.DEN.4" { |
| caption "met3.chip.high.DEN.4: Layer met3 chip density (700) square micron window stepped at 70) > 80%" |
| density layer_to_check_met3 -gt .80 -window 700 -step 70 -inside_of layer fill_extent -rdb met3_chip_high_density.rdb |
| } |
| #IFDEF GENERATE_PREDICTIVE_FILL |
| size met4i -by 0.3 -outputlayer keepout_1_met4 |
| size capacitor -by 3 -outputlayer keepout_2_met4 |
| size target -by 3.295 -outputlayer keepout_3_met4 |
| size nsm -by 1 -outputlayer keepout_4_met4 |
| size dieCut -by 3 -outputlayer keepout_5_met4 |
| size MM4mk -by 0.3 -outputlayer keepout_6_met4 |
| size ( or met4_block cmm4WaffleDrop ) -by 0.3 -outputlayer keepout_7_met4 |
| or keepout_1_met4 keepout_2_met4 keepout_3_met4 keepout_4_met4 keepout_5_met4 keepout_6_met4 keepout_7_met4 -outputlayer keepout_met4_1st |
| not fill_extent keepout_met4_1st -outputlayer target_fill_area_met4_1st |
| rect_gen -width 2.0 -length 2.0 -spacing 0.3 -inside_of LAYER target_fill_area_met4_1st -outputlayer psuedo_fill_met4_1st |
| not target_fill_area_met4_1st ( size psuedo_fill_met4_1st -by 0.3 ) -outputlayer target_fill_area_met4_2nd |
| rect_gen -width 1.0 -length 1.0 -spacing 0.3 -inside_of LAYER target_fill_area_met4_2nd -outputlayer psuedo_fill_met4_2nd |
| not target_fill_area_met4_2nd ( size psuedo_fill_met4_2nd -by 0.3 ) -outputlayer target_fill_area_met4_3rd |
| rect_gen -width 0.58 -length 0.58 -spacing 0.3 -inside_of LAYER target_fill_area_met4_3rd -outputlayer psuedo_fill_met4_3rd |
| or psuedo_fill_met4_1st psuedo_fill_met4_2nd psuedo_fill_met4_3rd -outputlayer psuedo_fill_met4 |
| rule "view_met4_predictive_fill" { |
| copy psuedo_fill_met4 |
| } |
| #ENDIF //predictive fill |
| #IFDEF GENERATE_PREDICTIVE_FILL |
| or met4i psuedo_fill_met4 MM4mk -outputlayer layer_to_check_met4 |
| #ENDIF //predictive fill |
| #IFNDEF GENERATE_PREDICTIVE_FILL |
| or ( size met4i -by 1.15 ) MM4mk -outputlayer layer_to_check_met4 |
| #ENDIF //predictive fill |
| #IFDEF GENERATE_LOCAL_DENSITY |
| rule "met4.local.low.DEN.1" { |
| caption "met4.local.low.DEN.1: Layer met4 local density (200 square micron window stepped at 100) < 30%" |
| density layer_to_check_met4 -lt .30 -window 200 -step 100 -inside_of layer fill_extent -rdb met4_local_low_density.rdb |
| } |
| rule "met4.local.high.DEN.2" { |
| caption "met4.local.high.DEN.2: Layer met4 local density (200 square micron window stepped at 100) > 80%" |
| density layer_to_check_met4 -gt .80 -window 200 -step 100 -inside_of layer fill_extent -rdb met4_local_high_density.rdb |
| } |
| #ENDIF |
| rule "met4.chip.low.DEN.3" { |
| caption "met4.chip.low.DEN.3: Layer met4 chip density (700 square micron window stepped at 70) < 30%" |
| density layer_to_check_met4 -lt .30 -window 700 -step 70 -inside_of layer fill_extent -rdb met4_chip_low_density.rdb |
| } |
| rule "met4.chip.high.DEN.4" { |
| caption "met4.chip.high.DEN.4: Layer met4 chip density (700) square micron window stepped at 70) > 80%" |
| density layer_to_check_met4 -gt .80 -window 700 -step 70 -inside_of layer fill_extent -rdb met4_chip_high_density.rdb |
| } |
| #IFDEF GENERATE_PREDICTIVE_FILL |
| size met5i -by 3.0 -outputlayer keepout_1_met5 |
| size ( or capm cap2m ) -by 3 -outputlayer keepout_2_met5 |
| size target -by 3.295 -outputlayer keepout_3_met5 |
| size nsm -by 1 -outputlayer keepout_4_met5 |
| size dieCut -by 3 -outputlayer keepout_5_met5 |
| size MM5mk -by 0.3 -outputlayer keepout_6_met5 |
| size ( or met5_block cmm5WaffleDrop ) -by 3.0 -outputlayer keepout_7_met5 |
| or keepout_1_met5 keepout_2_met5 keepout_3_met5 keepout_4_met5 keepout_5_met5 keepout_6_met5 keepout_7_met5 -outputlayer keepout_met5 |
| not fill_extent keepout_met5 -outputlayer target_fill_area_met5 |
| rect_gen -width 3.0 -length 3.0 -spacing 3.0 -inside_of LAYER target_fill_area_met5 -outputlayer psuedo_fill_met5 |
| rule "view_met5_predictive_fill" { |
| copy psuedo_fill_met5 |
| } |
| #ENDIF //predictive fill |
| #IFDEF GENERATE_PREDICTIVE_FILL |
| or met5i psuedo_fill_met5 MM5mk -outputlayer layer_to_check_met5 |
| #ENDIF //predictive fill |
| #IFNDEF GENERATE_PREDICTIVE_FILL |
| or ( size met5i -by 0.0 ) MM5mk -outputlayer layer_to_check_met5 |
| #ENDIF //predictive fill |
| #IFDEF GENERATE_LOCAL_DENSITY |
| rule "met5.local.low.DEN.1" { |
| caption "met5.local.low.DEN.1: Layer met5 local density (200 square micron window stepped at 100) < 19%" |
| density layer_to_check_met5 -lt .19 -window 200 -step 100 -inside_of layer fill_extent -rdb met5_local_low_density.rdb |
| } |
| rule "met5.local.high.DEN.2" { |
| caption "met5.local.high.DEN.2: Layer met5 local density (200 square micron window stepped at 100) > 60%" |
| density layer_to_check_met5 -gt .60 -window 200 -step 100 -inside_of layer fill_extent -rdb met5_local_high_density.rdb |
| } |
| #ENDIF |
| rule "met5.chip.low.DEN.3" { |
| caption "met5.chip.low.DEN.3: Layer met5 chip density (700 square micron window stepped at 70) < 19%" |
| density layer_to_check_met5 -lt .19 -window 700 -step 70 -inside_of layer fill_extent -rdb met5_chip_low_density.rdb |
| } |
| rule "met5.chip.high.DEN.4" { |
| caption "met5.chip.high.DEN.4: Layer met5 chip density (700) square micron window stepped at 70) > 60%" |
| density layer_to_check_met5 -gt .60 -window 700 -step 70 -inside_of layer fill_extent -rdb met5_chip_high_density.rdb |
| } |
| copy boundary -outputlayer chip |
| area chip -gt 40000.0 -outputlayer chipAreaBigEnough |
| select -interact chip sealHoles -outputlayer entireChipForDensity |
| size met1 -by 0.6 -outputlayer met1outOxide_drc |
| density cmm1WaffleDrop -eq 1.0 -window 700 -step 70 -outputlayer waffle1DropDensity70_met1 |
| density met1outOxide_drc -lt 0.7 -window 700 -step 70 -inside_of layer waffle1DropDensity70_met1 -rdb met1.chip.low.DEN_under_100_fill_block.1.rdb -outputlayer met1_DensityUnder70 |
| select -interact met1_DensityUnder70 entireChipForDensity -outputlayer met1_DensityUnder70Chip |
| not met1_DensityUnder70 met1_DensityUnder70Chip -outputlayer met1_DensityUnder70tmp |
| and met1_DensityUnder70tmp chipAreaBigEnough -outputlayer met1_DensityUnder70IP |
| rule "met1.low.DEN_under_100_fill_block.1_IP" { |
| caption "met1.low.DEN_under_100_fill_block.1_IP: <70% met1 density when 700x700 window 100% covered by met1 fill block (IP) < 70%" |
| copy met1_DensityUnder70IP |
| } |
| rule "met1.low.DEN_under_100_fill_block.1_CHIP" { |
| caption "met1.low.DEN_under_100_fill_block.1_CHIP: <70% met1 density when 700x700 window 100% covered by met1 fill block (CHIP) < 70%" |
| copy met1_DensityUnder70Chip |
| } |
| density cmm1WaffleDrop -legt 0.8 1.0 -window 700 -step 70 -outputlayer waffle1DropDensity65_met1 |
| density met1outOxide_drc -lt 0.65 -window 700 -step 70 -inside_of layer waffle1DropDensity65_met1 -rdb met1.chip.low.DEN_under_80_fill_block.1.rdb -outputlayer met1_DensityUnder65 |
| select -interact met1_DensityUnder65 entireChipForDensity -outputlayer met1_DensityUnder65Chip |
| not met1_DensityUnder65 met1_DensityUnder65Chip -outputlayer met1_DensityUnder65tmp |
| and met1_DensityUnder65tmp chipAreaBigEnough -outputlayer met1_DensityUnder65IP |
| rule "met1.low.DEN_under_80_fill_block.1_IP" { |
| caption "met1.low.DEN_under_80_fill_block.1_IP: met1 density when 700x700 window 80-100% covered by met1 fill block (IP) < 65%" |
| copy met1_DensityUnder65IP |
| } |
| rule "met1.low.DEN_under_80_fill_block.1_CHIP" { |
| caption "met1.low.DEN_under_80_fill_block.1_CHIP: met1 density when 700x700 window 80-100% covered by met1 fill block (CHIP) < 65%" |
| copy met1_DensityUnder65Chip |
| } |
| density cmm1WaffleDrop -legt 0.6 0.8 -window 700 -step 70 -outputlayer waffle1DropDensity60_met1 |
| density met1outOxide_drc -lt 0.6 -window 700 -step 70 -inside_of layer waffle1DropDensity60_met1 -rdb met1.chip.low.DEN_under_60_fill_block.1.rdb -outputlayer met1_DensityUnder60 |
| select -interact met1_DensityUnder60 entireChipForDensity -outputlayer met1_DensityUnder60Chip |
| not met1_DensityUnder60 met1_DensityUnder60Chip -outputlayer met1_DensityUnder60tmp |
| and met1_DensityUnder60tmp chipAreaBigEnough -outputlayer met1_DensityUnder60IP |
| rule "met1.low.DEN_under_60_fill_block.1_IP" { |
| caption "met1.low.DEN_under_60_fill_block.1_IP: met1 density when 700x700 window 60-80% covered by met1 fill block (IP) < 60%" |
| copy met1_DensityUnder60IP |
| } |
| rule "met1.low.DEN_under_60_fill_block.1_CHIP" { |
| caption "met1.low.DEN_under_60_fill_block.1_CHIP: met1 density when 700x700 window 60-80% covered by met1 fill block (CHIP) < 60%" |
| copy met1_DensityUnder60Chip |
| } |
| density cmm1WaffleDrop -legt 0.5 0.6 -window 700 -step 70 -outputlayer waffle1DropDensity50_met1 |
| density met1outOxide_drc -lt 0.5 -window 700 -step 70 -inside_of layer waffle1DropDensity50_met1 -rdb met1.chip.low.DEN_under_50_fill_block.1.rdb -outputlayer met1_DensityUnder50 |
| select -interact met1_DensityUnder50 entireChipForDensity -outputlayer met1_DensityUnder50Chip |
| not met1_DensityUnder50 met1_DensityUnder50Chip -outputlayer met1_DensityUnder50tmp |
| and met1_DensityUnder50tmp chipAreaBigEnough -outputlayer met1_DensityUnder50IP |
| rule "met1.low.DEN_under_50_fill_block.1_IP" { |
| caption "met1.low.DEN_under_50_fill_block.1_IP: met1 density when 700x700 window 50-60% covered by met1 fill block (IP) < 50%" |
| copy met1_DensityUnder50IP |
| } |
| rule "met1.low.DEN_under_50_fill_block.1_CHIP" { |
| caption "met1.low.DEN_under_50_fill_block.1_CHIP: met1 density when 700x700 window 50-60% covered by met1 fill block (CHIP)_ < 50%" |
| copy met1_DensityUnder50Chip |
| } |
| density cmm1WaffleDrop -legt 0.4 0.5 -window 700 -step 70 -outputlayer waffle1DropDensity40_met1 |
| density met1outOxide_drc -lt 0.4 -window 700 -step 70 -inside_of layer waffle1DropDensity40_met1 -rdb met1.chip.low.DEN_under_40_fill_block.1.rdb -outputlayer met1_DensityUnder40 |
| select -interact met1_DensityUnder40 entireChipForDensity -outputlayer met1_DensityUnder40Chip |
| not met1_DensityUnder40 met1_DensityUnder40Chip -outputlayer met1_DensityUnder40tmp |
| and met1_DensityUnder40tmp chipAreaBigEnough -outputlayer met1_DensityUnder40IP |
| rule "met1.low.DEN_under_40_fill_block.1_IP" { |
| caption "met1.low.DEN_under_40_fill_block.1_IP: met1 density when 700x700 window 40-50% covered by met1 fill block (IP) < 40%" |
| copy met1_DensityUnder40IP |
| } |
| rule "met1.low.DEN_under_40_fill_block.1_CHIP" { |
| caption "met1.low.DEN_under_40_fill_block.1_CHIP: met1 density when 700x700 window 40-50% covered by met1 fill block (CHIP) < 40%" |
| copy met1_DensityUnder40Chip |
| } |
| density cmm1WaffleDrop -legt 0.3 0.4 -window 700 -step 70 -outputlayer waffle1DropDensity30_met1 |
| density met1outOxide_drc -lt 0.3 -window 700 -step 70 -inside_of layer waffle1DropDensity30_met1 -rdb met1.chip.low.DEN_under_30_fill_block.1.rdb -outputlayer met1_DensityUnder30 |
| select -interact met1_DensityUnder30 entireChipForDensity -outputlayer met1_DensityUnder30Chip |
| not met1_DensityUnder30 met1_DensityUnder30Chip -outputlayer met1_DensityUnder30tmp |
| and met1_DensityUnder30tmp chipAreaBigEnough -outputlayer met1_DensityUnder30IP |
| rule "met1.low.DEN_under_30_fill_block.1_IP" { |
| caption "met1.low.DEN_under_30_fill_block.1_IP: met1 density when 700x700 window 30-40% covered by met1 fill block (IP) < 30%" |
| copy met1_DensityUnder30IP |
| } |
| rule "met1.low.DEN_under_30_fill_block.1_CHIP" { |
| caption "met1.low.DEN_under_30_fill_block.1_CHIP: met1 density when 700x700 window 30-40% covered by met1 fill block (CHIP) < 30%" |
| copy met1_DensityUnder30Chip |
| } |
| size met2 -by 0.6 -outputlayer met2outOxide_drc |
| density cmm2WaffleDrop -eq 1.0 -window 700 -step 70 -outputlayer waffle1DropDensity70_met2 |
| density met2outOxide_drc -lt 0.7 -window 700 -step 70 -inside_of layer waffle1DropDensity70_met2 -rdb met2.chip.low.DEN_under_100_fill_block.1.rdb -outputlayer met2_DensityUnder70 |
| select -interact met2_DensityUnder70 entireChipForDensity -outputlayer met2_DensityUnder70Chip |
| not met2_DensityUnder70 met2_DensityUnder70Chip -outputlayer met2_DensityUnder70tmp |
| and met2_DensityUnder70tmp chipAreaBigEnough -outputlayer met2_DensityUnder70IP |
| rule "met2.low.DEN_under_100_fill_block.1_IP" { |
| caption "met2.low.DEN_under_100_fill_block.1_IP: <70% met2 density when 700x700 window 100% covered by met2 fill block (IP) < 70%" |
| copy met2_DensityUnder70IP |
| } |
| rule "met2.low.DEN_under_100_fill_block.1_CHIP" { |
| caption "met2.low.DEN_under_100_fill_block.1_CHIP: <70% met2 density when 700x700 window 100% covered by met2 fill block (CHIP) < 70%" |
| copy met2_DensityUnder70Chip |
| } |
| density cmm2WaffleDrop -legt 0.8 1.0 -window 700 -step 70 -outputlayer waffle1DropDensity65_met2 |
| density met2outOxide_drc -lt 0.65 -window 700 -step 70 -inside_of layer waffle1DropDensity65_met2 -rdb met2.chip.low.DEN_under_80_fill_block.1.rdb -outputlayer met2_DensityUnder65 |
| select -interact met2_DensityUnder65 entireChipForDensity -outputlayer met2_DensityUnder65Chip |
| not met2_DensityUnder65 met2_DensityUnder65Chip -outputlayer met2_DensityUnder65tmp |
| and met2_DensityUnder65tmp chipAreaBigEnough -outputlayer met2_DensityUnder65IP |
| rule "met2.low.DEN_under_80_fill_block.1_IP" { |
| caption "met2.low.DEN_under_80_fill_block.1_IP: met2 density when 700x700 window 80-100% covered by met2 fill block (IP) < 65%" |
| copy met2_DensityUnder65IP |
| } |
| rule "met2.low.DEN_under_80_fill_block.1_CHIP" { |
| caption "met2.low.DEN_under_80_fill_block.1_CHIP: met2 density when 700x700 window 80-100% covered by met2 fill block (CHIP) < 65%" |
| copy met2_DensityUnder65Chip |
| } |
| density cmm2WaffleDrop -legt 0.6 0.8 -window 700 -step 70 -outputlayer waffle1DropDensity60_met2 |
| density met2outOxide_drc -lt 0.6 -window 700 -step 70 -inside_of layer waffle1DropDensity60_met2 -rdb met2.chip.low.DEN_under_60_fill_block.1.rdb -outputlayer met2_DensityUnder60 |
| select -interact met2_DensityUnder60 entireChipForDensity -outputlayer met2_DensityUnder60Chip |
| not met2_DensityUnder60 met2_DensityUnder60Chip -outputlayer met2_DensityUnder60tmp |
| and met2_DensityUnder60tmp chipAreaBigEnough -outputlayer met2_DensityUnder60IP |
| rule "met2.low.DEN_under_60_fill_block.1_IP" { |
| caption "met2.low.DEN_under_60_fill_block.1_IP: met2 density when 700x700 window 60-80% covered by met2 fill block (IP) < 60%" |
| copy met2_DensityUnder60IP |
| } |
| rule "met2.low.DEN_under_60_fill_block.1_CHIP" { |
| caption "met2.low.DEN_under_60_fill_block.1_CHIP: met2 density when 700x700 window 60-80% covered by met2 fill block (CHIP) < 60%" |
| copy met2_DensityUnder60Chip |
| } |
| density cmm2WaffleDrop -legt 0.5 0.6 -window 700 -step 70 -outputlayer waffle1DropDensity50_met2 |
| density met2outOxide_drc -lt 0.5 -window 700 -step 70 -inside_of layer waffle1DropDensity50_met2 -rdb met2.chip.low.DEN_under_50_fill_block.1.rdb -outputlayer met2_DensityUnder50 |
| select -interact met2_DensityUnder50 entireChipForDensity -outputlayer met2_DensityUnder50Chip |
| not met2_DensityUnder50 met2_DensityUnder50Chip -outputlayer met2_DensityUnder50tmp |
| and met2_DensityUnder50tmp chipAreaBigEnough -outputlayer met2_DensityUnder50IP |
| rule "met2.low.DEN_under_50_fill_block.1_IP" { |
| caption "met2.low.DEN_under_50_fill_block.1_IP: met2 density when 700x700 window 50-60% covered by met2 fill block (IP) < 50%" |
| copy met2_DensityUnder50IP |
| } |
| rule "met2.low.DEN_under_50_fill_block.1_CHIP" { |
| caption "met2.low.DEN_under_50_fill_block.1_CHIP: met2 density when 700x700 window 50-60% covered by met2 fill block (CHIP)_ < 50%" |
| copy met2_DensityUnder50Chip |
| } |
| density cmm2WaffleDrop -legt 0.4 0.5 -window 700 -step 70 -outputlayer waffle1DropDensity40_met2 |
| density met2outOxide_drc -lt 0.4 -window 700 -step 70 -inside_of layer waffle1DropDensity40_met2 -rdb met2.chip.low.DEN_under_40_fill_block.1.rdb -outputlayer met2_DensityUnder40 |
| select -interact met2_DensityUnder40 entireChipForDensity -outputlayer met2_DensityUnder40Chip |
| not met2_DensityUnder40 met2_DensityUnder40Chip -outputlayer met2_DensityUnder40tmp |
| and met2_DensityUnder40tmp chipAreaBigEnough -outputlayer met2_DensityUnder40IP |
| rule "met2.low.DEN_under_40_fill_block.1_IP" { |
| caption "met2.low.DEN_under_40_fill_block.1_IP: met2 density when 700x700 window 40-50% covered by met2 fill block (IP) < 40%" |
| copy met2_DensityUnder40IP |
| } |
| rule "met2.low.DEN_under_40_fill_block.1_CHIP" { |
| caption "met2.low.DEN_under_40_fill_block.1_CHIP: met2 density when 700x700 window 40-50% covered by met2 fill block (CHIP) < 40%" |
| copy met2_DensityUnder40Chip |
| } |
| density cmm2WaffleDrop -legt 0.3 0.4 -window 700 -step 70 -outputlayer waffle1DropDensity30_met2 |
| density met2outOxide_drc -lt 0.3 -window 700 -step 70 -inside_of layer waffle1DropDensity30_met2 -rdb met2.chip.low.DEN_under_30_fill_block.1.rdb -outputlayer met2_DensityUnder30 |
| select -interact met2_DensityUnder30 entireChipForDensity -outputlayer met2_DensityUnder30Chip |
| not met2_DensityUnder30 met2_DensityUnder30Chip -outputlayer met2_DensityUnder30tmp |
| and met2_DensityUnder30tmp chipAreaBigEnough -outputlayer met2_DensityUnder30IP |
| rule "met2.low.DEN_under_30_fill_block.1_IP" { |
| caption "met2.low.DEN_under_30_fill_block.1_IP: met2 density when 700x700 window 30-40% covered by met2 fill block (IP) < 30%" |
| copy met2_DensityUnder30IP |
| } |
| rule "met2.low.DEN_under_30_fill_block.1_CHIP" { |
| caption "met2.low.DEN_under_30_fill_block.1_CHIP: met2 density when 700x700 window 30-40% covered by met2 fill block (CHIP) < 30%" |
| copy met2_DensityUnder30Chip |
| } |
| size met3 -by 0.6 -outputlayer met3outOxide_drc |
| density cmm3WaffleDrop -eq 1.0 -window 700 -step 70 -outputlayer waffle1DropDensity70_met3 |
| density met3outOxide_drc -lt 0.7 -window 700 -step 70 -inside_of layer waffle1DropDensity70_met3 -rdb met3.chip.low.DEN_under_100_fill_block.1.rdb -outputlayer met3_DensityUnder70 |
| select -interact met3_DensityUnder70 entireChipForDensity -outputlayer met3_DensityUnder70Chip |
| not met3_DensityUnder70 met3_DensityUnder70Chip -outputlayer met3_DensityUnder70tmp |
| and met3_DensityUnder70tmp chipAreaBigEnough -outputlayer met3_DensityUnder70IP |
| rule "met3.low.DEN_under_100_fill_block.1_IP" { |
| caption "met3.low.DEN_under_100_fill_block.1_IP: <70% met3 density when 700x700 window 100% covered by met3 fill block (IP) < 70%" |
| copy met3_DensityUnder70IP |
| } |
| rule "met3.low.DEN_under_100_fill_block.1_CHIP" { |
| caption "met3.low.DEN_under_100_fill_block.1_CHIP: <70% met3 density when 700x700 window 100% covered by met3 fill block (CHIP) < 70%" |
| copy met3_DensityUnder70Chip |
| } |
| density cmm3WaffleDrop -legt 0.8 1.0 -window 700 -step 70 -outputlayer waffle1DropDensity65_met3 |
| density met3outOxide_drc -lt 0.65 -window 700 -step 70 -inside_of layer waffle1DropDensity65_met3 -rdb met3.chip.low.DEN_under_80_fill_block.1.rdb -outputlayer met3_DensityUnder65 |
| select -interact met3_DensityUnder65 entireChipForDensity -outputlayer met3_DensityUnder65Chip |
| not met3_DensityUnder65 met3_DensityUnder65Chip -outputlayer met3_DensityUnder65tmp |
| and met3_DensityUnder65tmp chipAreaBigEnough -outputlayer met3_DensityUnder65IP |
| rule "met3.low.DEN_under_80_fill_block.1_IP" { |
| caption "met3.low.DEN_under_80_fill_block.1_IP: met3 density when 700x700 window 80-100% covered by met3 fill block (IP) < 65%" |
| copy met3_DensityUnder65IP |
| } |
| rule "met3.low.DEN_under_80_fill_block.1_CHIP" { |
| caption "met3.low.DEN_under_80_fill_block.1_CHIP: met3 density when 700x700 window 80-100% covered by met3 fill block (CHIP) < 65%" |
| copy met3_DensityUnder65Chip |
| } |
| density cmm3WaffleDrop -legt 0.6 0.8 -window 700 -step 70 -outputlayer waffle1DropDensity60_met3 |
| density met3outOxide_drc -lt 0.6 -window 700 -step 70 -inside_of layer waffle1DropDensity60_met3 -rdb met3.chip.low.DEN_under_60_fill_block.1.rdb -outputlayer met3_DensityUnder60 |
| select -interact met3_DensityUnder60 entireChipForDensity -outputlayer met3_DensityUnder60Chip |
| not met3_DensityUnder60 met3_DensityUnder60Chip -outputlayer met3_DensityUnder60tmp |
| and met3_DensityUnder60tmp chipAreaBigEnough -outputlayer met3_DensityUnder60IP |
| rule "met3.low.DEN_under_60_fill_block.1_IP" { |
| caption "met3.low.DEN_under_60_fill_block.1_IP: met3 density when 700x700 window 60-80% covered by met3 fill block (IP) < 60%" |
| copy met3_DensityUnder60IP |
| } |
| rule "met3.low.DEN_under_60_fill_block.1_CHIP" { |
| caption "met3.low.DEN_under_60_fill_block.1_CHIP: met3 density when 700x700 window 60-80% covered by met3 fill block (CHIP) < 60%" |
| copy met3_DensityUnder60Chip |
| } |
| density cmm3WaffleDrop -legt 0.5 0.6 -window 700 -step 70 -outputlayer waffle1DropDensity50_met3 |
| density met3outOxide_drc -lt 0.5 -window 700 -step 70 -inside_of layer waffle1DropDensity50_met3 -rdb met3.chip.low.DEN_under_50_fill_block.1.rdb -outputlayer met3_DensityUnder50 |
| select -interact met3_DensityUnder50 entireChipForDensity -outputlayer met3_DensityUnder50Chip |
| not met3_DensityUnder50 met3_DensityUnder50Chip -outputlayer met3_DensityUnder50tmp |
| and met3_DensityUnder50tmp chipAreaBigEnough -outputlayer met3_DensityUnder50IP |
| rule "met3.low.DEN_under_50_fill_block.1_IP" { |
| caption "met3.low.DEN_under_50_fill_block.1_IP: met3 density when 700x700 window 50-60% covered by met3 fill block (IP) < 50%" |
| copy met3_DensityUnder50IP |
| } |
| rule "met3.low.DEN_under_50_fill_block.1_CHIP" { |
| caption "met3.low.DEN_under_50_fill_block.1_CHIP: met3 density when 700x700 window 50-60% covered by met3 fill block (CHIP)_ < 50%" |
| copy met3_DensityUnder50Chip |
| } |
| density cmm3WaffleDrop -legt 0.4 0.5 -window 700 -step 70 -outputlayer waffle1DropDensity40_met3 |
| density met3outOxide_drc -lt 0.4 -window 700 -step 70 -inside_of layer waffle1DropDensity40_met3 -rdb met3.chip.low.DEN_under_40_fill_block.1.rdb -outputlayer met3_DensityUnder40 |
| select -interact met3_DensityUnder40 entireChipForDensity -outputlayer met3_DensityUnder40Chip |
| not met3_DensityUnder40 met3_DensityUnder40Chip -outputlayer met3_DensityUnder40tmp |
| and met3_DensityUnder40tmp chipAreaBigEnough -outputlayer met3_DensityUnder40IP |
| rule "met3.low.DEN_under_40_fill_block.1_IP" { |
| caption "met3.low.DEN_under_40_fill_block.1_IP: met3 density when 700x700 window 40-50% covered by met3 fill block (IP) < 40%" |
| copy met3_DensityUnder40IP |
| } |
| rule "met3.low.DEN_under_40_fill_block.1_CHIP" { |
| caption "met3.low.DEN_under_40_fill_block.1_CHIP: met3 density when 700x700 window 40-50% covered by met3 fill block (CHIP) < 40%" |
| copy met3_DensityUnder40Chip |
| } |
| density cmm3WaffleDrop -legt 0.3 0.4 -window 700 -step 70 -outputlayer waffle1DropDensity30_met3 |
| density met3outOxide_drc -lt 0.3 -window 700 -step 70 -inside_of layer waffle1DropDensity30_met3 -rdb met3.chip.low.DEN_under_30_fill_block.1.rdb -outputlayer met3_DensityUnder30 |
| select -interact met3_DensityUnder30 entireChipForDensity -outputlayer met3_DensityUnder30Chip |
| not met3_DensityUnder30 met3_DensityUnder30Chip -outputlayer met3_DensityUnder30tmp |
| and met3_DensityUnder30tmp chipAreaBigEnough -outputlayer met3_DensityUnder30IP |
| rule "met3.low.DEN_under_30_fill_block.1_IP" { |
| caption "met3.low.DEN_under_30_fill_block.1_IP: met3 density when 700x700 window 30-40% covered by met3 fill block (IP) < 30%" |
| copy met3_DensityUnder30IP |
| } |
| rule "met3.low.DEN_under_30_fill_block.1_CHIP" { |
| caption "met3.low.DEN_under_30_fill_block.1_CHIP: met3 density when 700x700 window 30-40% covered by met3 fill block (CHIP) < 30%" |
| copy met3_DensityUnder30Chip |
| } |
| size met4 -by 0.6 -outputlayer met4outOxide_drc |
| density cmm4WaffleDrop -eq 1.0 -window 700 -step 70 -outputlayer waffle1DropDensity70_met4 |
| density met4outOxide_drc -lt 0.7 -window 700 -step 70 -inside_of layer waffle1DropDensity70_met4 -rdb met4.chip.low.DEN_under_100_fill_block.1.rdb -outputlayer met4_DensityUnder70 |
| select -interact met4_DensityUnder70 entireChipForDensity -outputlayer met4_DensityUnder70Chip |
| not met4_DensityUnder70 met4_DensityUnder70Chip -outputlayer met4_DensityUnder70tmp |
| and met4_DensityUnder70tmp chipAreaBigEnough -outputlayer met4_DensityUnder70IP |
| rule "met4.low.DEN_under_100_fill_block.1_IP" { |
| caption "met4.low.DEN_under_100_fill_block.1_IP: <70% met4 density when 700x700 window 100% covered by met4 fill block (IP) < 70%" |
| copy met4_DensityUnder70IP |
| } |
| rule "met4.low.DEN_under_100_fill_block.1_CHIP" { |
| caption "met4.low.DEN_under_100_fill_block.1_CHIP: <70% met4 density when 700x700 window 100% covered by met4 fill block (CHIP) < 70%" |
| copy met4_DensityUnder70Chip |
| } |
| density cmm4WaffleDrop -legt 0.8 1.0 -window 700 -step 70 -outputlayer waffle1DropDensity65_met4 |
| density met4outOxide_drc -lt 0.65 -window 700 -step 70 -inside_of layer waffle1DropDensity65_met4 -rdb met4.chip.low.DEN_under_80_fill_block.1.rdb -outputlayer met4_DensityUnder65 |
| select -interact met4_DensityUnder65 entireChipForDensity -outputlayer met4_DensityUnder65Chip |
| not met4_DensityUnder65 met4_DensityUnder65Chip -outputlayer met4_DensityUnder65tmp |
| and met4_DensityUnder65tmp chipAreaBigEnough -outputlayer met4_DensityUnder65IP |
| rule "met4.low.DEN_under_80_fill_block.1_IP" { |
| caption "met4.low.DEN_under_80_fill_block.1_IP: met4 density when 700x700 window 80-100% covered by met4 fill block (IP) < 65%" |
| copy met4_DensityUnder65IP |
| } |
| rule "met4.low.DEN_under_80_fill_block.1_CHIP" { |
| caption "met4.low.DEN_under_80_fill_block.1_CHIP: met4 density when 700x700 window 80-100% covered by met4 fill block (CHIP) < 65%" |
| copy met4_DensityUnder65Chip |
| } |
| density cmm4WaffleDrop -legt 0.6 0.8 -window 700 -step 70 -outputlayer waffle1DropDensity60_met4 |
| density met4outOxide_drc -lt 0.6 -window 700 -step 70 -inside_of layer waffle1DropDensity60_met4 -rdb met4.chip.low.DEN_under_60_fill_block.1.rdb -outputlayer met4_DensityUnder60 |
| select -interact met4_DensityUnder60 entireChipForDensity -outputlayer met4_DensityUnder60Chip |
| not met4_DensityUnder60 met4_DensityUnder60Chip -outputlayer met4_DensityUnder60tmp |
| and met4_DensityUnder60tmp chipAreaBigEnough -outputlayer met4_DensityUnder60IP |
| rule "met4.low.DEN_under_60_fill_block.1_IP" { |
| caption "met4.low.DEN_under_60_fill_block.1_IP: met4 density when 700x700 window 60-80% covered by met4 fill block (IP) < 60%" |
| copy met4_DensityUnder60IP |
| } |
| rule "met4.low.DEN_under_60_fill_block.1_CHIP" { |
| caption "met4.low.DEN_under_60_fill_block.1_CHIP: met4 density when 700x700 window 60-80% covered by met4 fill block (CHIP) < 60%" |
| copy met4_DensityUnder60Chip |
| } |
| density cmm4WaffleDrop -legt 0.5 0.6 -window 700 -step 70 -outputlayer waffle1DropDensity50_met4 |
| density met4outOxide_drc -lt 0.5 -window 700 -step 70 -inside_of layer waffle1DropDensity50_met4 -rdb met4.chip.low.DEN_under_50_fill_block.1.rdb -outputlayer met4_DensityUnder50 |
| select -interact met4_DensityUnder50 entireChipForDensity -outputlayer met4_DensityUnder50Chip |
| not met4_DensityUnder50 met4_DensityUnder50Chip -outputlayer met4_DensityUnder50tmp |
| and met4_DensityUnder50tmp chipAreaBigEnough -outputlayer met4_DensityUnder50IP |
| rule "met4.low.DEN_under_50_fill_block.1_IP" { |
| caption "met4.low.DEN_under_50_fill_block.1_IP: met4 density when 700x700 window 50-60% covered by met4 fill block (IP) < 50%" |
| copy met4_DensityUnder50IP |
| } |
| rule "met4.low.DEN_under_50_fill_block.1_CHIP" { |
| caption "met4.low.DEN_under_50_fill_block.1_CHIP: met4 density when 700x700 window 50-60% covered by met4 fill block (CHIP)_ < 50%" |
| copy met4_DensityUnder50Chip |
| } |
| density cmm4WaffleDrop -legt 0.4 0.5 -window 700 -step 70 -outputlayer waffle1DropDensity40_met4 |
| density met4outOxide_drc -lt 0.4 -window 700 -step 70 -inside_of layer waffle1DropDensity40_met4 -rdb met4.chip.low.DEN_under_40_fill_block.1.rdb -outputlayer met4_DensityUnder40 |
| select -interact met4_DensityUnder40 entireChipForDensity -outputlayer met4_DensityUnder40Chip |
| not met4_DensityUnder40 met4_DensityUnder40Chip -outputlayer met4_DensityUnder40tmp |
| and met4_DensityUnder40tmp chipAreaBigEnough -outputlayer met4_DensityUnder40IP |
| rule "met4.low.DEN_under_40_fill_block.1_IP" { |
| caption "met4.low.DEN_under_40_fill_block.1_IP: met4 density when 700x700 window 40-50% covered by met4 fill block (IP) < 40%" |
| copy met4_DensityUnder40IP |
| } |
| rule "met4.low.DEN_under_40_fill_block.1_CHIP" { |
| caption "met4.low.DEN_under_40_fill_block.1_CHIP: met4 density when 700x700 window 40-50% covered by met4 fill block (CHIP) < 40%" |
| copy met4_DensityUnder40Chip |
| } |
| density cmm4WaffleDrop -legt 0.3 0.4 -window 700 -step 70 -outputlayer waffle1DropDensity30_met4 |
| density met4outOxide_drc -lt 0.3 -window 700 -step 70 -inside_of layer waffle1DropDensity30_met4 -rdb met4.chip.low.DEN_under_30_fill_block.1.rdb -outputlayer met4_DensityUnder30 |
| select -interact met4_DensityUnder30 entireChipForDensity -outputlayer met4_DensityUnder30Chip |
| not met4_DensityUnder30 met4_DensityUnder30Chip -outputlayer met4_DensityUnder30tmp |
| and met4_DensityUnder30tmp chipAreaBigEnough -outputlayer met4_DensityUnder30IP |
| rule "met4.low.DEN_under_30_fill_block.1_IP" { |
| caption "met4.low.DEN_under_30_fill_block.1_IP: met4 density when 700x700 window 30-40% covered by met4 fill block (IP) < 30%" |
| copy met4_DensityUnder30IP |
| } |
| rule "met4.low.DEN_under_30_fill_block.1_CHIP" { |
| caption "met4.low.DEN_under_30_fill_block.1_CHIP: met4 density when 700x700 window 30-40% covered by met4 fill block (CHIP) < 30%" |
| copy met4_DensityUnder30Chip |
| } |
| #IFDEF GENERATE_PREDICTIVE_FILL |
| not ( size nwell -by 0.34 ) ( size NWELL -by -0.18 ) -outputlayer nwell_diff_keepout_1 |
| not ( size ( holes nwell ) -by 0.34 ) ( size ( holes NWELL ) -by -0.18 ) -outputlayer nwell_diff_keepout_2 |
| or nwell_diff_keepout_1 nwell_diff_keepout_2 -outputlayer nwell_diff_poly_keepout |
| size ( or pwbm pwres PHdiodeID ) -by 0.5 -outputlayer diff_poly_keepout |
| size ( or pwbm pwres PHdiodeID ) -by 0.5 -outputlayer diff_keepout_0 |
| size diffi -by 0.5 -outputlayer diff_keepout_1 |
| size target -by 3.295 -outputlayer diff_keepout_2 |
| size nsm -by 1 -outputlayer diff_keepout_3 |
| size dieCut -by 3 -outputlayer diff_keepout_4 |
| size fomWaffDrop -by 0.4 -outputlayer diff_keepout_5 |
| size ( or diff_block polyi fomWaffDrop P1Mmk ) -by 0.30 -outputlayer diff_keepout_6 |
| or nwell_diff_poly_keepout diff_keepout_0 diff_keepout_1 diff_keepout_2 diff_keepout_3 diff_keepout_4 diff_keepout_5 diff_keepout_6 -outputlayer diff_keepout |
| size polyi -by 0.5 -outputlayer poly_keepout_1 |
| size target -by 3.295 -outputlayer poly_keepout_2 |
| size nsm -by 1 -outputlayer poly_keepout_3 |
| size dieCut -by 3 -outputlayer poly_keepout_4 |
| size ( or poly_block diffi cp1mWaffleDrop P1Mmk cfom ) -by 0.30 -outputlayer poly_keepout_5 |
| or diff_poly_keepout nwell_diff_poly_keepout poly_keepout_1 poly_keepout_2 poly_keepout_3 poly_keepout_4 poly_keepout_5 -outputlayer poly_keepout |
| not fill_extent diff_keepout -outputlayer diff_target_fill_area_1st |
| rect_gen -width 4.08 -length 4.08 -spacing 4.08 -inside_of LAYER diff_target_fill_area_1st -outputlayer diff_psuedo_fill_1st |
| not fill_extent ( or poly_keepout ( size diff_psuedo_fill_1st -by 0.3 ) ) -outputlayer poly_target_fill_area_1st |
| rect_gen -width 0.72 -length 0.72 -spacing 0.8 -inside_of LAYER poly_target_fill_area_1st -offset 1 1 -outputlayer poly_psuedo_fill_1st |
| not diff_target_fill_area_1st ( or ( size diff_psuedo_fill_1st -by 0.3 ) ( size poly_psuedo_fill_1st -by 0.3 ) ) -outputlayer diff_target_fill_area_2nd |
| rect_gen -width 2.05 -length 2.05 -spacing 1.32 -inside_of LAYER diff_target_fill_area_2nd -outputlayer diff_psuedo_fill_2nd |
| not poly_target_fill_area_1st ( or ( size poly_psuedo_fill_1st -by 0.26 ) ( size diff_target_fill_area_2nd -by 0.3 ) ) -outputlayer poly_target_fill_area_2nd |
| rect_gen -width 0.54 -length 0.54 -spacing 0.36 -inside_of LAYER poly_target_fill_area_2nd -offset 1 1 -outputlayer poly_psuedo_fill_2nd |
| not diff_target_fill_area_2nd ( or ( size diff_psuedo_fill_2nd -by 0.3 ) ( size poly_psuedo_fill_2nd -by 0.3 ) ) -outputlayer diff_target_fill_area_3rd |
| rect_gen -width 1.5 -length 1.5 -spacing 1.32 -inside_of LAYER diff_target_fill_area_3rd -offset .5 .5 -outputlayer diff_psuedo_fill_3rd |
| not poly_target_fill_area_2nd ( or ( size poly_psuedo_fill_2nd -by 0.26 ) ( size diff_psuedo_fill_3rd -by 0.3 ) ) -outputlayer poly_target_fill_area_3rd |
| rect_gen -width 0.48 -length 0.48 -spacing 0.36 -inside_of LAYER poly_target_fill_area_3rd -offset 1 1 -outputlayer poly_psuedo_fill_3rd |
| not diff_target_fill_area_3rd ( or ( size diff_psuedo_fill_3rd -by 0.3 ) ( size poly_psuedo_fill_3rd -by 0.3 ) ) -outputlayer diff_target_fill_area_4th |
| rect_gen -width 0.5 -length 0.5 -spacing 0.4 -inside_of LAYER diff_target_fill_area_4th -outputlayer diff_psuedo_fill_4th |
| or diff_psuedo_fill_1st diff_psuedo_fill_2nd diff_psuedo_fill_3rd diff_psuedo_fill_4th -outputlayer diff_psuedo_fill |
| or poly_psuedo_fill_1st poly_psuedo_fill_2nd poly_psuedo_fill_3rd -outputlayer poly_psuedo_fill |
| #ENDIF //predictive fill |
| #IFDEF GENERATE_PREDICTIVE_FILL |
| or diffi diff_psuedo_fill -outputlayer diff_layer_to_check |
| or polyi poly_psuedo_fill -outputlayer poly_layer_to_check |
| rule "view_diff_predictive_fill" { |
| copy diff_psuedo_fill |
| } |
| rule "view_poly_predictive_fill" { |
| copy poly_psuedo_fill |
| } |
| #ENDIF //predictive fill |
| #IFNDEF GENERATE_PREDICTIVE_FILL |
| copy diffi -outputlayer diff_layer_to_check |
| copy polyi -outputlayer poly_layer_to_check |
| #ENDIF //predictive fill |
| #IFDEF GENERATE_LOCAL_DENSITY |
| rule "diff.local.low.DEN.1" { |
| caption "diff.local.low.DEN.1: Layer diff local density (50 square micron window stepped at 25) < 28%" |
| density diff_layer_to_check -lt .28 -window 50 -step 25 -inside_of layer fill_extent -rdb diff_local_low_density.rdb |
| } |
| rule "diff.local.high.DEN.1" { |
| caption "diff.local.high.DEN.1: Layer diff local density (50 square micron window stepped at 25) > 62%" |
| density diff_layer_to_check -gt 0.62 -window 50 -step 25 -inside_of layer fill_extent -rdb diff_local_high_density.rdb |
| } |
| #ENDIF |
| rule "diff.chip.low.DEN.1" { |
| caption "diff.chip.low.DEN.1: Layer diff chip density (500 square micron window stepped at 100) < 28%" |
| density diff_layer_to_check -lt .28 -window 500 -step 100 -inside_of layer fill_extent -rdb diff_chip_low_density.rdb |
| } |
| rule "diff.chip.high.DEN.1" { |
| caption "diff.chip.high.DEN.1: Layer diff chip density (500 square micron window stepped at 100) > 62%" |
| density diff_layer_to_check -gt 0.62 -window 500 -step 100 -inside_of layer fill_extent -rdb diff_chip_high_density.rdb |
| } |
| #IFDEF GENERATE_LOCAL_DENSITY |
| rule "poly.local.low.DEN.1" { |
| caption "poly.local.low.DEN.1: Layer poly local density (50 square micron window stepped at 25) < 30%" |
| density poly_layer_to_check -lt .30 -window 50 -step 25 -inside_of layer fill_extent -rdb poly_local_low_density.rdb |
| } |
| rule "poly.local.high.DEN.1" { |
| caption "poly.local.high.DEN.1: Layer poly local density (50 square micron window stepped at 25) > 40%" |
| density poly_layer_to_check -gt 0.40 -window 50 -step 25 -inside_of layer fill_extent -rdb poly_local_high_density.rdb |
| } |
| #ENDIF |
| rule "poly.chip.low.DEN.1" { |
| caption "poly.chip.low.DEN.1: Layer poly chip density (500 square micron window stepped at 100) < 30%" |
| density poly_layer_to_check -lt .30 -window 500 -step 100 -inside_of layer fill_extent -rdb poly_chip_low_density.rdb |
| } |
| rule "poly.chip.high.DEN.1" { |
| caption "poly.chip.high.DEN.1: Layer poly chip density (500 square micron window stepped at 100) > 52%" |
| density poly_layer_to_check -gt 0.52 -window 500 -step 100 -inside_of layer fill_extent -rdb poly_chip_high_density.rdb |
| } |
| #ENDIF //skip density check |
| |
| #IFNDEF SKIP_LATCHUP_CHECKS |
| rule "latchup.WARN.1" { |
| caption "latchup.WARN.1: No pads have any markers for IO, PWR or GND" |
| size ( select -interact -not boundary ( or ( select -interact pad pad_io ) ( select -interact pad pad_gnd ) ( select -interact pad pad_pwr ) ) ) -by -5.0 |
| } |
| rule "latchup.WARN.2" { |
| caption "latchup.WARN.2: pad does not have a marker for IO, PWR or GND" |
| select -interact -not pad ( or pad_io pad_gnd pad_pwr ) |
| } |
| and diffi nwell -outputlayer diff_and_nw |
| not diffi diff_and_nw -outputlayer diff_not_pdiff |
| and tap nwell -outputlayer tap_and_nw |
| not tap tap_and_nw -outputlayer tap_not_nw |
| not diff_not_pdiff ( or gate diffres ) -outputlayer nsrcdrn_lu |
| not diff_and_nw ( or gate diffres ) -outputlayer psrcdrn_lu |
| not poly polyres -outputlayer poly_no_res |
| and poly polyres -outputlayer poly_res_lu |
| and diff_not_pdiff diffres -outputlayer ndiff_res_lu |
| and diff_and_nw diffres -outputlayer pdiff_res_lu |
| copy met1i -outputlayer metal1 |
| copy met2i -outputlayer metal2 |
| copy met3i -outputlayer metal3 |
| copy met4i -outputlayer metal4 |
| copy met5i -outputlayer metal5 |
| copy m1res -outputlayer met1res |
| copy m2res -outputlayer met2res |
| copy m3res -outputlayer met3res |
| copy m4res -outputlayer met4res |
| copy m5res -outputlayer met5res |
| and ( and metal1 met1res ) ESDID -outputlayer m1_esd_res |
| not metal1 m1_esd_res -outputlayer m1_not_esd_res |
| and ( and metal2 met2res ) ESDID -outputlayer m2_esd_res |
| not metal2 m2_esd_res -outputlayer m2_not_esd_res |
| and ( and metal3 met3res ) ESDID -outputlayer m3_esd_res |
| not metal3 m3_esd_res -outputlayer m3_not_esd_res |
| and ( and metal4 met4res ) ESDID -outputlayer m4_esd_res |
| not metal4 m4_esd_res -outputlayer m4_not_esd_res |
| and ( and metal5 met5res ) ESDID -outputlayer m5_esd_res |
| not metal5 m5_esd_res -outputlayer m5_not_esd_res |
| select -outside Licon diffTap -outputlayer licon_outs_diff |
| not Licon licon_outs_diff -outputlayer licon_not_outs_diff |
| or ( and licon_not_outs_diff diff_not_pdiff ) ( and licon_not_outs_diff tap_and_nw ) -outputlayer licon_nfom |
| or ( and licon_not_outs_diff diff_and_nw ) ( and licon_not_outs_diff tap_not_nw ) -outputlayer licon_pfom |
| and licon_not_outs_diff diff -outputlayer licon_diff |
| not pad ( select -label pad -textname "probe-only" -textlayer textdraw ) -outputlayer pad_not_probe |
| select -label pad -textname "probe-only" -textlayer textdraw -outputlayer probe_pad_not_probe |
| select -label met1 -textname "switched_power" -textlayer textdraw -outputlayer switched_intPower_met1 |
| and dnwell nwell -outputlayer dnw_and_nw |
| not boundary ( or ( not dnwell ( size dnwell -by -0.01 ) ) dnw_and_nw ) -outputlayer iso_sub |
| not localSub ( size localSub -by -0.005 ) -outputlayer local_sub_ring |
| not iso_sub local_sub_ring -outputlayer sub_local2 |
| copy sub_local2 -outputlayer isolated_sub |
| not isolated_sub pwres -outputlayer isolated_sub_no_pwr |
| and tap_not_nw isolated_sub_no_pwr -outputlayer iso_sub_ptap |
| |
| disconnect |
| connect nwell tap_and_nw |
| connect isolated_sub_no_pwr tap_not_nw -by iso_sub_ptap |
| connect li tap_not_nw -by licon_pfom |
| connect li tap_and_nw -by licon_nfom |
| connect li psrcdrn_lu -by licon_pfom |
| connect li nsrcdrn_lu -by licon_nfom |
| connect m1_not_esd_res li -by mcon |
| connect m2_not_esd_res m1_not_esd_res -by via1 |
| connect m3_not_esd_res m2_not_esd_res -by via2 |
| connect m3_not_esd_res met3 |
| connect m2_not_esd_res met2 |
| connect m1_not_esd_res met1 |
| connect nsrcdrn_lu diff |
| connect psrcdrn_lu diff |
| connect switched_intPower_met1 m1_not_esd_res |
| connect li poly_no_res -by licon_outs_diff |
| connect poly_no_res gate |
| connect pad_not_probe m5_not_esd_res |
| connect probe_pad_not_probe m5_not_esd_res |
| connect m5_not_esd_res m4_not_esd_res -by via4_c |
| connect m4_not_esd_res m3_not_esd_res -by via3_c |
| connect rdl pad_not_probe -by pmm |
| connect rdl probe_pad_not_probe -by pmm |
| |
| select_net tap_and_nw "vpwr" "vpwr1" "vpwr3" "vpwr_prb" "vccio" "vpwr2" -outputlayer vccNetstap_and_nw |
| antenna tap_and_nw switched_intPower_met1 -gt 0 -outputlayer vccSiptap_and_nw |
| or vccNetstap_and_nw vccSiptap_and_nw -outputlayer vcctap_and_nw |
| select_net tap_not_nw "vgnd" "vgnd1" "vgnd3" "vgnd_prb" "vgnd_pad" "vssio" -outputlayer vsstap_not_nw |
| select_net tap_not_nw "vpwr" "vpwr1" "vpwr3" "vpwr_prb" "vccio" "vpwr2" -outputlayer vcctap_not_nw |
| select_net nsrcdrn_lu "vgnd" "vgnd1" "vgnd3" "vgnd_prb" "vgnd_pad" "vssio" -outputlayer vssNSD |
| select_net psrcdrn_lu "vgnd" "vgnd1" "vgnd3" "vgnd_prb" "vgnd_pad" "vssio" -outputlayer vssPSD |
| select_net psrcdrn_lu "vpwr" "vpwr1" "vpwr3" "vpwr_prb" "vccio" "vpwr2" -outputlayer vccNetsPSD |
| antenna psrcdrn_lu switched_intPower_met1 -gt 0 -outputlayer vccSipPSD |
| select_net nsrcdrn_lu "vpwr" "vpwr1" "vpwr3" "vpwr_prb" "vccio" "vpwr2" -outputlayer vccNetsNSD |
| antenna nsrcdrn_lu switched_intPower_met1 -gt 0 -outputlayer vccSipNSD |
| or vccNetsPSD vccSipPSD -outputlayer vccPSD |
| or vccNetsNSD vccSipNSD -outputlayer vccNSD |
| select_net nwell "vgnd" "vgnd1" "vgnd3" "vgnd_prb" "vgnd_pad" "vssio" -outputlayer vssNwell |
| copy 4000 -outputlayer lvvccNwell |
| select_net nsrcdrn_lu "io" "io1" "io2" "io4" "io_prb" "pad5v" "io_pad" "pad" -outputlayer ioNSDnet |
| select_net psrcdrn_lu "io" "io1" "io2" "io4" "io_prb" "pad5v" "io_pad" "pad" -outputlayer ioPSDnet |
| select_net tap_and_nw "io" "io1" "io2" "io4" "io_prb" "pad5v" "io_pad" "pad" -outputlayer iotap_and_nwnet |
| select_net tap_not_nw "io" "io1" "io2" "io4" "io_prb" "pad5v" "io_pad" "pad" -outputlayer iotap_not_nwnet |
| select_net pad_not_probe "io" "io1" "io2" "io4" "io_prb" "pad5v" "io_pad" "pad" -outputlayer ioPads |
| antenna nsrcdrn_lu ioPads -gt 0 -outputlayer ioPadConnNSDnet |
| antenna psrcdrn_lu ioPads -gt 0 -outputlayer ioPadConnPSDnet |
| select -inside nsrcdrn_lu SigPadDiff -outputlayer NSDsigPad |
| select -inside psrcdrn_lu SigPadDiff -outputlayer PSDsigPad |
| select -inside SigPadMetNtr SigPadDiff -outputlayer SigPadNtr |
| select -inside nsrcdrn_lu SigPadNtr -outputlayer NSDsigPadNtr |
| select -inside psrcdrn_lu SigPadNtr -outputlayer PSDsigPadNtr |
| select -inside tap_and_nw SigPadDiff -outputlayer tap_and_nwsigPad |
| select -inside tap_not_nw SigPadDiff -outputlayer tap_not_nwsigPad |
| select -inside tap_and_nw SigPadNtr -outputlayer tap_and_nwsigPadNtr |
| select -inside tap_not_nw SigPadNtr -outputlayer tap_not_nwsigPadNtr |
| select -inside SigPadMetNtr SigPadWell -outputlayer SigPadWellNtr |
| select -inside nwell SigPadWellNtr -outputlayer nwellSigPadNtr |
| stamp NSDSigPad nsrcdrn_lu -outputlayer NSDsigPadConn |
| stamp PSDSigPad psrcdrn_lu -outputlayer PSDsigPadConn |
| stamp tap_and_nwSigPad tap_and_nw -outputlayer tap_and_nwsigPadConn |
| stamp tap_not_nwSigPad tap_not_nw -outputlayer tap_not_nwsigPadConn |
| or NSDsigPad ioNSDnet -outputlayer ioNSD |
| or PSDsigPad ioPSDnet -outputlayer ioPSD |
| or tap_and_nwsigPad iotap_and_nwnet -outputlayer iotap_and_nw |
| or tap_not_nwsigPad iotap_not_nwnet -outputlayer iotap_not_nw |
| or NSDsigPadNtr ioPadConnNSDnet -outputlayer ioPadConnNSD |
| or PSDsigPadNtr ioPadConnPSDnet -outputlayer ioPadConnPSD |
| or ( and NSDsigPad sigPadMetNtr ) ioNSDnet -outputlayer ioNSDntr |
| or ( and PSDsigPad sigPadMetNtr ) ioPSDnet -outputlayer ioPSDntr |
| not ( select -donut tap_and_nw ) SEALID -outputlayer ntapRing |
| not ( select -donut tap_not_nw ) SEALID -outputlayer ptapRing |
| holes ptapRing -outputlayer ptapRingFilled |
| and licon tap_not_nw -outputlayer pTaplicon |
| and licon tap_and_nw -outputlayer nTaplicon |
| and licon vsstap_not_nw -outputlayer pTapliconVss |
| not pTaplicon pTapliconVss -outputlayer pTapliconNonVss |
| and licon vcctap_and_nw -outputlayer nTapliconVcc |
| and poly diff_not_pdiff -outputlayer POLYanddiff_not_pdiff |
| and poly diff_and_nw -outputlayer POLYanddiff_and_nw |
| and diff COREID -outputlayer diffCore |
| not diff_not_pdiff diffCore -outputlayer ndiffPeri |
| not diff_and_nw diffCore -outputlayer pdiffPeri |
| and ( size diff_and_nw -by 1.5 ) nwell -outputlayer nwellArea |
| not ( size diff_not_pdiff -by 1.5 ) nwell -outputlayer pwellArea |
| select -outside nwell vcctap_and_nw -outputlayer nonVccNwell |
| not tap_and_nw pnp -outputlayer nonPnpNTap |
| not tap_not_nw pnp -outputlayer nonPnpPTap |
| select -donut diff_not_pdiff -outputlayer nDiffRing |
| holes nDiffRing -outputlayer nDiffHole |
| select -inside nwell tap_and_nw -outputlayer nWellTap |
| select -inside nDiffHole nWellTap -outputlayer nWellTapInHole |
| and nWellTapInHole ESDID -outputlayer ESDnWellTapTmp |
| stamp ESDnWellTapTmp tap_and_nw -outputlayer ESDnWellTap |
| and nwell ( and ESDID DIODEID ) -outputlayer nwellDIOESD |
| select -outside nwellDIOESD ( or ESDnWellTap poly ) -outputlayer ESD_diode |
| and diff ESDID -outputlayer ESD_diff |
| not vssNwell ( inside_cell nwell "s8iom0s8_top_lvc_b2b_wopad" "s8iom0s8_top_lvclamp" "s8atlasana_esd_gnd2gnd_sub_dnwl" "s8fpafeg1_tk_lvc_b2b_wopad" ) -outputlayer vssNwellNoXmtCells |
| not ptapRingFilled ptapRing -outputlayer ptapRingFilledNotRing |
| select -interact ptapRingFilledNotRing vssNwellNoXmtCells -outputlayer ptapRingWithVssNwell |
| select -interact ptapRing ( select -interact -not ptapRingFilledNotRing vssNwellNoXmtCells ) -outputlayer ptapRingNoVssNwell |
| select -outside ( not ptapRing ptapRingNoVssNwell ) ptapRingWithVssNwell -outputlayer vssNwellPtapRing |
| |
| disconnect |
| connect met5 met4 -by via4_c |
| connect met4 met3 -by via3_c |
| connect met4 m4_bot_plate -by cap2m_cont_dmy |
| connect met3 met2 -by via2 |
| |
| |
| connect met3 m3_bot_plate -by capm_cont_dmy |
| connect met2 met1 -by via1 |
| connect met1 li -by mcon |
| connect li nsd -by licon |
| connect li psd -by licon |
| connect li ntap -by licon |
| connect li ptap -by licon |
| connect li ptubtap -by licon |
| connect li poly -by licon |
| |
| connect ntap nwell |
| connect ptap pwell |
| connect ptubtap ptub |
| connect nwell dnwell |
| |
| connect met5 pad |
| connect met5 uprobe_pad |
| connect met5 probe_pad |
| connect rdl pad |
| connect rdl uprobe_pad |
| connect rdl probe_pad |
| |
| select -interact pad pad_gnd -outputlayer gnd_pad |
| antenna met5 gnd_pad -gt 0 -outputlayer pad_gnd_net_m5 |
| antenna met4 gnd_pad -gt 0 -outputlayer pad_gnd_net_m4 |
| antenna met3 gnd_pad -gt 0 -outputlayer pad_gnd_net_m3 |
| antenna met2 gnd_pad -gt 0 -outputlayer pad_gnd_net_m2 |
| antenna met1 gnd_pad -gt 0 -outputlayer pad_gnd_net_m1 |
| antenna li gnd_pad -gt 0 -outputlayer pad_gnd_net_li |
| antenna nsd gnd_pad -gt 0 -outputlayer pad_gnd_net_nsd |
| antenna psd gnd_pad -gt 0 -outputlayer pad_gnd_net_psd |
| antenna poly gnd_pad -gt 0 -outputlayer pad_gnd_net_poly |
| antenna nwell gnd_pad -gt 0 -outputlayer pad_gnd_net_nw |
| antenna dnwell gnd_pad -gt 0 -outputlayer pad_gnd_net_dnw |
| antenna pwell gnd_pad -gt 0 -outputlayer pad_gnd_net_pw |
| antenna ntap gnd_pad -gt 0 -outputlayer pad_gnd_net_ntap |
| antenna ptap gnd_pad -gt 0 -outputlayer pad_gnd_net_ptap |
| or pad_gnd_net_m5 pad_gnd_net_m4 pad_gnd_net_m3 pad_gnd_net_m2 pad_gnd_net_m1 -outputlayer gnd_net_to_pad1 |
| or gnd_net_to_pad1 pad_gnd_net_nsd pad_gnd_net_psd pad_gnd_net_poly -outputlayer gnd_net_to_pad2 |
| or gnd_net_to_pad2 pad_gnd_net_ntap pad_gnd_net_ptap pad_gnd_net_nw pad_gnd_net_pw -outputlayer gnd_net_to_pad |
| select -interact pad pad_io -outputlayer sig_pad |
| antenna met5 sig_pad -gt 0 -outputlayer pad_sig_net_m5 |
| antenna met4 sig_pad -gt 0 -outputlayer pad_sig_net_m4 |
| antenna met3 sig_pad -gt 0 -outputlayer pad_sig_net_m3 |
| antenna met2 sig_pad -gt 0 -outputlayer pad_sig_net_m2 |
| antenna met1 sig_pad -gt 0 -outputlayer pad_sig_net_m1 |
| antenna li sig_pad -gt 0 -outputlayer pad_sig_net_li |
| antenna nsd sig_pad -gt 0 -outputlayer pad_sig_net_nsd |
| antenna psd sig_pad -gt 0 -outputlayer pad_sig_net_psd |
| antenna poly sig_pad -gt 0 -outputlayer pad_sig_net_poly |
| antenna nwell sig_pad -gt 0 -outputlayer pad_sig_net_nw |
| antenna dnwell sig_pad -gt 0 -outputlayer pad_sig_net_dnw |
| antenna pwell sig_pad -gt 0 -outputlayer pad_sig_net_pw |
| antenna ntap sig_pad -gt 0 -outputlayer pad_sig_net_ntap |
| antenna ptap sig_pad -gt 0 -outputlayer pad_sig_net_ptap |
| or pad_sig_net_m5 pad_sig_net_m4 pad_sig_net_m3 pad_sig_net_m2 pad_sig_net_m1 -outputlayer sig_net_to_pad1 |
| or sig_net_to_pad1 pad_sig_net_nsd pad_sig_net_psd pad_sig_net_poly -outputlayer sig_net_to_pad2 |
| or sig_net_to_pad2 pad_sig_net_ntap pad_sig_net_ptap pad_sig_net_nw pad_sig_net_pw -outputlayer sig_net_to_pad |
| select -interact pad pad_pwr -outputlayer pwr_pad |
| antenna met5 pwr_pad -gt 0 -outputlayer pad_pwr_net_m5 |
| antenna met4 pwr_pad -gt 0 -outputlayer pad_pwr_net_m4 |
| antenna met3 pwr_pad -gt 0 -outputlayer pad_pwr_net_m3 |
| antenna met2 pwr_pad -gt 0 -outputlayer pad_pwr_net_m2 |
| antenna met1 pwr_pad -gt 0 -outputlayer pad_pwr_net_m1 |
| antenna li pwr_pad -gt 0 -outputlayer pad_pwr_net_li |
| antenna nsd pwr_pad -gt 0 -outputlayer pad_pwr_net_nsd |
| antenna psd pwr_pad -gt 0 -outputlayer pad_pwr_net_psd |
| antenna ntap pwr_pad -gt 0 -outputlayer pad_pwr_net_ntap |
| antenna ptap pwr_pad -gt 0 -outputlayer pad_pwr_net_ptap |
| antenna poly pwr_pad -gt 0 -outputlayer pad_pwr_net_poly |
| antenna nwell pwr_pad -gt 0 -outputlayer pad_pwr_net_nw |
| antenna pwell pwr_pad -gt 0 -outputlayer pad_pwr_net_pw |
| or pad_pwr_net_m5 pad_pwr_net_m4 pad_pwr_net_m3 pad_pwr_net_m2 pad_pwr_net_m1 -outputlayer pwr_net_to_pad1 |
| or pwr_net_to_pad1 pad_pwr_net_nsd pad_pwr_net_psd pad_pwr_net_poly -outputlayer pwr_net_to_pad2 |
| or pwr_net_to_pad2 pad_pwr_net_ntap pad_pwr_net_ptap pad_pwr_net_nw pad_pwr_net_pw -outputlayer pwr_net_to_pad |
| holes SEALID -outputlayer sealHole |
| or pad_sig_net_nsd pad_sig_net_psd pad_sig_net_ntap pad_sig_net_ptap -outputlayer sig_pad_diff |
| size sig_pad_diff -by 50 -inside_of sealHole -step 5 -outputlayer io_region |
| not ( and ptap licon ) nwell -outputlayer ptap_licon |
| and ( and ntap licon ) ( or nwell dnwell ) -outputlayer ntap_licon |
| size ptap_licon -by 6 -outside_of nwell -step 0.59 -truncate 2.61 -outputlayer ptap_licon_size_6 |
| size ntap_licon -by 6 -inside_of ( or nwell dnwell ) -step 0.59 -truncate 2.61 -outputlayer ntap_licon_size_6 |
| size ptap_licon -by 15 -outside_of nwell -step 0.59 -truncate 2.61 -outputlayer ptap_licon_size_15 |
| size ntap_licon -by 15 -inside_of ( or nwell dnwell ) -step 0.59 -truncate 2.61 -outputlayer ntap_licon_size_15 |
| and nsd io_region -outputlayer ndiff_in_ioregion |
| and psd io_region -outputlayer pdiff_in_ioregion |
| not psd io_region -outputlayer pdiff_not_in_ioregion |
| not nsd io_region -outputlayer ndiff_not_in_ioregion |
| select -enclose ( and ( or pwell ptub ) sealHole ) ptap_licon -outputlayer pwell_has_ptap_licon |
| select -enclose ( and ( or pwell ptub ) sealHole ) ndiff_in_ioregion -outputlayer pwell_has_ptap_io_ndiff |
| select -enclose -not ( and ( or pwell ptub ) sealHole ) ndiff_in_ioregion -outputlayer pwell_has_ptap_no_io_ndiff |
| and pwell_has_ptap_licon pwell_has_ptap_io_ndiff -outputlayer pwell_has_both_io |
| and pwell_has_ptap_licon pwell_has_ptap_no_io_ndiff -outputlayer pwell_has_both_not_io |
| select -enclose ( and ( or nwell dnwell ) sealHole ) ntap_licon -outputlayer nwell_has_ntap_licon |
| select -enclose ( and ( or nwell dnwell ) sealHole ) ndiff_in_ioregion -outputlayer nwell_has_ntap_io_ndiff |
| select -enclose -not ( and ( or nwell dnwell ) sealHole ) ndiff_in_ioregion -outputlayer nwell_has_ntap_no_io_ndiff |
| and nwell_has_ntap_licon nwell_has_ntap_io_ndiff -outputlayer nwell_has_both_io |
| and nwell_has_ntap_licon nwell_has_ntap_no_io_ndiff -outputlayer nwell_has_both_not_io |
| rule "latchup.generic.2a" { |
| caption "latchup.generic.2a: Max spacing from center of ptap licon to any part of ndiff within the same ptub or pwell (< 50u away from diff connected to a signal pad) > 6" |
| select -inside ( not ( not ( and ndiff_in_ioregion nsd ) ESDID ) ptap_licon_size_6 ) pwell_has_both_io |
| } |
| rule "latchup.generic.2b" { |
| caption "latchup.generic.2b: Max spacing from center of ptap licon to any part of ndiff within the same ptub or pwell (>= 50u away from diff connected to a signal pad) > 15" |
| select -inside ( not ( not ( and ndiff_not_in_ioregion nsd ) ESDID ) ptap_licon_size_15 ) pwell_has_both_not_io |
| } |
| and ( or ptap psd ) pwr_net_to_pad -outputlayer pos_pwr_pdiff |
| select -enclose dnwell pos_pwr_pdiff -outputlayer dnw_has_pos_pwr_pdiff |
| select -interact nwell dnw_has_pos_pwr_pdiff -outputlayer nw_has_pos_pwr_pdiff |
| or dnw_has_pos_pwr_pdiff nw_has_pos_pwr_pdiff -outputlayer dnw_or_nw_pwr_pdiff |
| select -enclose -not dnwell pos_pwr_pdiff -outputlayer dnw_no_pos_pwr_pdiff |
| select -interact -not ( select -interact nwell dnwell ) dnw_has_pos_pwr_pdiff -outputlayer nw_no_pos_pwr_pdiff |
| or dnw_no_pos_pwr_pdiff nw_no_pos_pwr_pdiff -outputlayer dnw_or_nw_no_pwr_pdiff |
| rule "latchup.generic.2.1a_b" { |
| caption "latchup.generic.2.1a_b: Max spacing from center of ptap licon to N+ diff within the same pwell where the deep nwell or nwell forming the pwell, does NOT contain a pdiff connected to a power pad > 6" |
| select -inside ( not ( not ( not ( and ndiff_in_ioregion nsd ) ESDID ) COREID ) ptap_licon_size_6 ) dnw_or_nw_no_pwr_pdiff |
| } |
| rule "latchup.generic.3a" { |
| caption "latchup.generic.3a: Max spacing from center of ntap licon to pdiff within the same nwell or dnwell (< 50u away from diff connected to a signal pad ) > 6" |
| not ( not ( not ( not ( and pdiff_in_ioregion psd ) ESDID ) COREID ) ptap ) ntap_licon_size_6 |
| } |
| rule "latchup.generic.3b" { |
| caption "latchup.generic.3a: Max spacing from center of ntap licon pdiff within the same nwell or dnwell (>= 50u away from diff connected signal pad) > 15" |
| not ( not ( not ( not ( and pdiff_not_in_ioregion psd ) ESDID ) COREID ) ptap ) ntap_licon_size_15 |
| } |
| rule "latchup.generic.4" { |
| caption "latchup.generic.4: Min distance from diffusion connected to a signal pad to areaid:core < 50.0" |
| exte ( and COREID sealHole ) ( and pad_sig_net_nsd sealHole ) -lt 50.0 -abut -lt 90 -output region |
| exte ( and COREID sealHole ) ( and pad_sig_net_psd sealHole ) -lt 50.0 -abut -lt 90 -output region |
| exte ( and COREID sealHole ) ( and pad_sig_net_ntap sealHole ) -lt 50.0 -abut -lt 90 -output region |
| select -inside ( exte COREID pad_sig_net_ptap -lt 50.0 -abut -lt 90 -output region ) sealHole |
| } |
| antenna met5 uprobe_pad -gt 0 -outputlayer upad_probe_net_m5 |
| antenna met4 uprobe_pad -gt 0 -outputlayer upad_probe_net_m4 |
| antenna met3 uprobe_pad -gt 0 -outputlayer upad_probe_net_m3 |
| antenna met2 uprobe_pad -gt 0 -outputlayer upad_probe_net_m2 |
| antenna met1 uprobe_pad -gt 0 -outputlayer upad_probe_net_m1 |
| antenna li uprobe_pad -gt 0 -outputlayer upad_probe_net_li |
| antenna nsd uprobe_pad -gt 0 -outputlayer upad_probe_net_nsd |
| antenna psd uprobe_pad -gt 0 -outputlayer upad_probe_net_psd |
| antenna met5 probe_pad -gt 0 -outputlayer ppad_probe_net_m5 |
| antenna met4 probe_pad -gt 0 -outputlayer ppad_probe_net_m4 |
| antenna met3 probe_pad -gt 0 -outputlayer ppad_probe_net_m3 |
| antenna met2 probe_pad -gt 0 -outputlayer ppad_probe_net_m2 |
| antenna met1 probe_pad -gt 0 -outputlayer ppad_probe_net_m1 |
| antenna li probe_pad -gt 0 -outputlayer ppad_probe_net_li |
| antenna nsd probe_pad -gt 0 -outputlayer ppad_probe_net_nsd |
| antenna psd probe_pad -gt 0 -outputlayer ppad_probe_net_psd |
| or upad_probe_net_nsd ppad_probe_net_nsd -outputlayer pad_probe_net_nsd |
| or upad_probe_net_psd ppad_probe_net_psd -outputlayer pad_probe_net_psd |
| rule "latchup.generic.5a" { |
| caption "latchup.generic.5a: Min. space N+ diff to unrelated N+ diff inside a common ptub or common pwell (metallically connected to separate pads or external nets - ground, power or signal) < 3" |
| or ESDID pad_probe_net_nsd -outputlayer exempt |
| select -inside ( exte ( not pad_sig_net_nsd exempt ) ( not pad_pwr_net_nsd exempt ) -lt 3.0 -abut -lt 90 -output region ) pwell |
| select -inside ( exte ( not pad_sig_net_nsd exempt ) ( not pad_gnd_net_nsd exempt ) -lt 3.0 -abut -lt 90 -output region ) pwell |
| select -inside ( exte ( not pad_pwr_net_nsd exempt ) ( not pad_gnd_net_nsd exempt ) -lt 3.0 -abut -lt 90 -output region ) pwell |
| select -inside ( exte ( not pad_sig_net_nsd exempt ) ( not pad_pwr_net_nsd exempt ) -lt 3.0 -abut -lt 90 -output region ) ptub |
| select -inside ( exte ( not pad_sig_net_nsd exempt ) ( not pad_gnd_net_nsd exempt ) -lt 3.0 -abut -lt 90 -output region ) ptub |
| select -inside ( exte ( not pad_pwr_net_nsd exempt ) ( not pad_gnd_net_nsd exempt ) -lt 3.0 -abut -lt 90 -output region ) ptub |
| select -inside ( exte ( not pad_sig_net_nsd exempt ) ( not pad_pwr_net_nsd exempt ) -lt 3.0 -abut -lt 90 -output region ) localSub |
| select -inside ( exte ( not pad_sig_net_nsd exempt ) ( not pad_gnd_net_nsd exempt ) -lt 3.0 -abut -lt 90 -output region ) localSub |
| select -inside ( exte ( not pad_pwr_net_nsd exempt ) ( not pad_gnd_net_nsd exempt ) -lt 3.0 -abut -lt 90 -output region ) localSub |
| } |
| rule "latchup.generic.5b" { |
| caption "latchup.generic.5b: Min. space P+ diff to unrelated P+ diff inside a common nwell or dnwell (metallically connected to separate pads or external nets - ground, power or signal) < 3" |
| or ESDID pad_probe_net_psd -outputlayer exempt |
| select -inside ( exte ( not pad_sig_net_psd exempt ) ( not pad_pwr_net_psd exempt ) -lt 3.0 -abut -lt 90 -output region -not_connected ) ( or nwell ( select -interact -not dnwell ptub ) ) |
| select -inside ( exte ( not pad_sig_net_psd exempt ) ( not pad_gnd_net_psd exempt ) -lt 3.0 -abut -lt 90 -output region -not_connected ) ( or nwell ( select -interact -not dnwell ptub ) ) |
| select -inside ( exte ( not pad_pwr_net_psd exempt ) ( not pad_gnd_net_psd exempt ) -lt 3.0 -abut -lt 90 -output region -not_connected ) ( or nwell ( select -interact -not dnwell ptub ) ) |
| } |
| holes ntap -outputlayer ntap_grd_ring |
| holes ptap -outputlayer ptap_grd_ring |
| rule "latchup.signal.2" { |
| caption "latchup.signal.2: Signal connected nwell must be in a pair of guard rings" |
| select -inside pad_sig_net_nw ntap_grd_ring -outputlayer pass_1 |
| select -inside pass_1 ptap_grd_ring -outputlayer pass_2 |
| not pad_sig_net_nw pass_2 |
| } |
| rule "latchup.signal.2.1a" { |
| caption "latchup.signal.2.1a: Signal pad connected deep nwell is not allowed" |
| copy pad_sig_net_dnw |
| } |
| select -label diffres -textname "250Ohm" -textlayer textdraw -outputlayer diff_res_gt_250ohm |
| select -label diffres -textname "1kOhm" -textlayer textdraw -outputlayer diff_res_gt_1kohm |
| or diff_res_gt_250ohm diff_res_gt_1kohm -outputlayer diff_res_lg_res |
| select -label polyres -textname "250Ohm" -textlayer textdraw -outputlayer poly_res_gt_250ohm |
| select -label polyres -textname "1kOhm" -textlayer textdraw -outputlayer poly_res_gt_1kohm |
| or poly_res_gt_250ohm poly_res_gt_1kohm -outputlayer poly_res_lg_res |
| select -label lires -textname "250Ohm" -textlayer textdraw -outputlayer li_res_gt_250ohm |
| select -label lires -textname "1kOhm" -textlayer textdraw -outputlayer li_res_gt_1kohm |
| or li_res_gt_250ohm li_res_gt_1kohm -outputlayer li_res_lg_res |
| select -label m1res -textname "250Ohm" -textlayer textdraw -outputlayer m1_res_gt_250ohm |
| select -label m1res -textname "1kOhm" -textlayer textdraw -outputlayer m1_res_gt_1kohm |
| or m1_res_gt_250ohm m1_res_gt_1kohm -outputlayer m1_res_lg_res |
| select -label m2res -textname "250Ohm" -textlayer textdraw -outputlayer m2_res_gt_250ohm |
| select -label m2res -textname "1kOhm" -textlayer textdraw -outputlayer m2_res_gt_1kohm |
| or m2_res_gt_250ohm m2_res_gt_1kohm -outputlayer m2_res_lg_res |
| select -label m3res -textname "250Ohm" -textlayer textdraw -outputlayer m3_res_gt_250ohm |
| select -label m3res -textname "1kOhm" -textlayer textdraw -outputlayer m3_res_gt_1kohm |
| or m3_res_gt_250ohm m3_res_gt_1kohm -outputlayer m3_res_lg_res |
| select -label m4res -textname "250Ohm" -textlayer textdraw -outputlayer m4_res_gt_250ohm |
| select -label m4res -textname "1kOhm" -textlayer textdraw -outputlayer m4_res_gt_1kohm |
| or m4_res_gt_250ohm m4_res_gt_1kohm -outputlayer m4_res_lg_res |
| select -label m5res -textname "250Ohm" -textlayer textdraw -outputlayer m5_res_gt_250ohm |
| select -label m5res -textname "1kOhm" -textlayer textdraw -outputlayer m5_res_gt_1kohm |
| or m5_res_gt_250ohm m5_res_gt_1kohm -outputlayer m5_res_lg_res |
| select -label pwres -textname "250Ohm" -textlayer textdraw -outputlayer pw_res_gt_250ohm |
| select -label pwres -textname "1kOhm" -textlayer textdraw -outputlayer pw_res_gt_1kohm |
| or pw_res_gt_250ohm pw_res_gt_1kohm -outputlayer pw_res_lg_res |
| not pwell pw_res_lg_res -outputlayer pw_lu |
| not diffi diff_res_lg_res -outputlayer diff_lu |
| not polyi poly_res_lg_res -outputlayer poly_lu |
| not nsd diff_res_lg_res -outputlayer nsd_lu |
| not psd diff_res_lg_res -outputlayer psd_lu |
| not li_i li_res_lg_res -outputlayer li_lu |
| not met1i m1_res_lg_res -outputlayer m1_lu |
| not met2i m2_res_lg_res -outputlayer m2_lu |
| not met3i m3_res_lg_res -outputlayer m3_lu |
| not met4i m4_res_lg_res -outputlayer m4_lu |
| not met5i m5_res_lg_res -outputlayer m5_lu |
| |
| disconnect |
| connect m5_lu m4_lu -by via4_c |
| connect m4_lu m3_lu -by via3_c |
| connect m3_lu m2_lu -by via2 |
| connect m2_lu m1_lu -by via1 |
| connect m1_lu li_lu -by mcon |
| connect li_lu nsd_lu -by licon |
| connect li_lu psd_lu -by licon |
| connect li_lu ntap -by licon |
| connect li_lu ptap -by licon |
| connect li_lu ptubtap -by licon |
| connect li_lu poly -by licon |
| |
| connect ntap nwell |
| connect ptap pw_lu |
| connect ptubtap ptub |
| connect nwell dnwell |
| |
| connect m5_lu pad |
| connect m5_lu uprobe_pad |
| connect m5_lu probe_pad |
| connect rdl pad |
| connect rdl uprobe_pad |
| connect rdl probe_pad |
| |
| select -interact pad pad_gnd -outputlayer gnd_pad2 |
| antenna dnwell gnd_pad2 -gt 0 -outputlayer pad_gnd2_net_dnw |
| antenna nsd_lu gnd_pad2 -gt 0 -outputlayer pad_gnd2_net_nsd |
| antenna ntap gnd_pad2 -gt 0 -outputlayer pad_gnd2_net_ntap |
| antenna nwell gnd_pad2 -gt 0 -outputlayer pad_gnd2_net_nw |
| rule "latchup.signal.2.1b" { |
| caption "latchup.signal.2.1b: Deep nwell tied to ground through a resistance of < 250 ohm is not allowed" |
| antenna nsd_lu gnd_pad2 -gt 0 -outputlayer exempt_lu_sig_2p1b_a |
| antenna dnwell gnd_pad2 -gt 0 -outputlayer exempt_lu_sig_2p1b_b |
| select -enclose exempt_lu_sig_2p1b_b exempt_lu_sig_2p1b_a -outputlayer exempt_lu_sig_2p1b |
| copy ( not pad_gnd2_net_dnw exempt_lu_sig_2p1b ) |
| } |
| |
| disconnect |
| connect met5 met4 -by via4_c |
| connect met4 met3 -by via3_c |
| connect met4 m4_bot_plate -by cap2m_cont_dmy |
| connect met3 met2 -by via2 |
| |
| |
| connect met3 m3_bot_plate -by capm_cont_dmy |
| connect met2 met1 -by via1 |
| connect met1 li -by mcon |
| connect li nsd -by licon |
| connect li psd -by licon |
| connect li ntap -by licon |
| connect li ptap -by licon |
| connect li ptubtap -by licon |
| connect li poly -by licon |
| |
| connect ntap nwell |
| connect ptap pwell |
| connect ptap localSub |
| connect ptubtap ptub |
| connect nwell dnwell |
| |
| connect met5 pad |
| connect met5 uprobe_pad |
| connect met5 probe_pad |
| connect rdl pad |
| connect rdl uprobe_pad |
| connect rdl probe_pad |
| |
| rule "latchup.signal.3" { |
| caption "latchup.signal.3: All P+ diff or tap connected to signal pad must be in a pair of guard rings" |
| select -inside pad_sig_net_psd ptap_grd_ring -outputlayer pass_1 |
| select -inside pass_1 ntap_grd_ring -outputlayer pass_2 |
| not pad_sig_net_psd pass_2 |
| select -inside pad_sig_net_ptap ptap_grd_ring -outputlayer pass_1a |
| select -inside pass_1a ntap_grd_ring -outputlayer pass_2a |
| not pad_sig_net_ptap pass_2a |
| } |
| select -interact pad pad_pwr -outputlayer pwr2_pad |
| antenna met5 pwr2_pad -gt 0 -outputlayer pad_pwr2_net_m5 |
| antenna met4 pwr2_pad -gt 0 -outputlayer pad_pwr2_net_m4 |
| antenna met3 pwr2_pad -gt 0 -outputlayer pad_pwr2_net_m3 |
| antenna met2 pwr2_pad -gt 0 -outputlayer pad_pwr2_net_m2 |
| antenna met1 pwr2_pad -gt 0 -outputlayer pad_pwr2_net_m1 |
| antenna li pwr2_pad -gt 0 -outputlayer pad_pwr2_net_li |
| antenna nsd pwr2_pad -gt 0 -outputlayer pad_pwr2_net_nsd |
| antenna psd pwr2_pad -gt 0 -outputlayer pad_pwr2_net_psd |
| antenna poly pwr2_pad -gt 0 -outputlayer pad_pwr2_net_poly |
| antenna nwell pwr2_pad -gt 0 -outputlayer pad_pwr2_net_nw |
| antenna pwell pwr2_pad -gt 0 -outputlayer pad_pwr2_net_pw |
| antenna ntap pwr2_pad -gt 0 -outputlayer pad_pwr2_net_ntap |
| antenna ptap pwr2_pad -gt 0 -outputlayer pad_pwr2_net_ptap |
| or pad_pwr2_net_m5 pad_pwr2_net_m4 pad_pwr2_net_m3 pad_pwr2_net_m2 pad_pwr2_net_m1 -outputlayer pwr2_net_to_pad1 |
| or pwr2_net_to_pad1 pad_pwr2_net_nsd pad_pwr2_net_psd pad_pwr2_net_poly -outputlayer pwr2_net_to_pad2 |
| or pwr2_net_to_pad2 pad_pwr2_net_ntap pad_pwr2_net_ptap pad_pwr2_net_nw pad_pwr2_net_pw -outputlayer pwr2_net_to_pad |
| rule "latchup.signal.3.1a" { |
| caption "latchup.signal.3.1a: signal connected ptap must have nwell/N+ guard ring connected to positive power pad" |
| not ( select -interact ntap ( select -interact ntap_grd_ring pad_sig_net_ptap ) ) pad_pwr2_net_ntap |
| } |
| select -interact pad pad_gnd -outputlayer gnd3_pad |
| antenna met5 gnd3_pad -gt 0 -outputlayer pad_gnd3_net_m5 |
| antenna met4 gnd3_pad -gt 0 -outputlayer pad_gnd3_net_m4 |
| antenna met3 gnd3_pad -gt 0 -outputlayer pad_gnd3_net_m3 |
| antenna met2 gnd3_pad -gt 0 -outputlayer pad_gnd3_net_m2 |
| antenna met1 gnd3_pad -gt 0 -outputlayer pad_gnd3_net_m1 |
| antenna li gnd3_pad -gt 0 -outputlayer pad_gnd3_net_li |
| antenna nsd gnd3_pad -gt 0 -outputlayer pad_gnd3_net_nsd |
| antenna psd gnd3_pad -gt 0 -outputlayer pad_gnd3_net_psd |
| antenna poly gnd3_pad -gt 0 -outputlayer pad_gnd3_net_poly |
| antenna nwell gnd3_pad -gt 0 -outputlayer pad_gnd3_net_nw |
| antenna ntap gnd3_pad -gt 0 -outputlayer pad_gnd3_net_ntap |
| antenna ptap gnd3_pad -gt 0 -outputlayer pad_gnd3_net_ptap |
| or pad_gnd3_net_m5 pad_gnd3_net_m4 pad_gnd3_net_m3 pad_gnd3_net_m2 pad_gnd3_net_m1 -outputlayer gnd3_net_to_pad1 |
| or gnd3_net_to_pad1 pad_gnd3_net_nsd pad_gnd3_net_psd pad_gnd3_net_poly -outputlayer gnd3_net_to_pad2 |
| or gnd3_net_to_pad2 pad_gnd3_net_ntap pad_gnd3_net_ptap pad_gnd3_net_nw -outputlayer gnd3_net_to_pad |
| select -interact pad pad_pwr -outputlayer pwr3_pad |
| antenna met5 pwr3_pad -gt 0 -outputlayer pad_pwr3_net_m5 |
| antenna met4 pwr3_pad -gt 0 -outputlayer pad_pwr3_net_m4 |
| antenna met3 pwr3_pad -gt 0 -outputlayer pad_pwr3_net_m3 |
| antenna met2 pwr3_pad -gt 0 -outputlayer pad_pwr3_net_m2 |
| antenna met1 pwr3_pad -gt 0 -outputlayer pad_pwr3_net_m1 |
| antenna li pwr3_pad -gt 0 -outputlayer pad_pwr3_net_li |
| antenna nsd pwr3_pad -gt 0 -outputlayer pad_pwr3_net_nsd |
| antenna psd pwr3_pad -gt 0 -outputlayer pad_pwr3_net_psd |
| antenna poly pwr3_pad -gt 0 -outputlayer pad_pwr3_net_poly |
| antenna nwell pwr3_pad -gt 0 -outputlayer pad_pwr3_net_nw |
| antenna pwell pwr3_pad -gt 0 -outputlayer pad_pwr3_net_pw |
| antenna localSub pwr3_pad -gt 0 -outputlayer pad_pwr3_net_ls |
| antenna ptub pwr3_pad -gt 0 -outputlayer pad_pwr3_net_pt |
| antenna ntap pwr3_pad -gt 0 -outputlayer pad_pwr3_net_ntap |
| antenna ptap pwr3_pad -gt 0 -outputlayer pad_pwr3_net_ptap |
| or pad_pwr3_net_m5 pad_pwr3_net_m4 pad_pwr3_net_m3 pad_pwr3_net_m2 pad_pwr3_net_m1 -outputlayer pwr3_net_to_pad1 |
| or pwr3_net_to_pad1 pad_pwr3_net_nsd pad_pwr3_net_psd pad_pwr3_net_poly -outputlayer pwr3_net_to_pad2 |
| or pwr3_net_to_pad2 pad_pwr3_net_ntap pad_pwr3_net_ptap pad_pwr3_net_nw pad_pwr3_net_pw -outputlayer pwr3_net_to_pad |
| select -interact pad pad_io -outputlayer sig2_pad |
| antenna met5 sig2_pad -gt 0 -outputlayer pad_sig2_net_m5 |
| antenna met4 sig2_pad -gt 0 -outputlayer pad_sig2_net_m4 |
| antenna met3 sig2_pad -gt 0 -outputlayer pad_sig2_net_m3 |
| antenna met2 sig2_pad -gt 0 -outputlayer pad_sig2_net_m2 |
| antenna met1 sig2_pad -gt 0 -outputlayer pad_sig2_net_m1 |
| antenna li sig2_pad -gt 0 -outputlayer pad_sig2_net_li |
| antenna nsd sig2_pad -gt 0 -outputlayer pad_sig2_net_nsd |
| antenna ntap sig2_pad -gt 0 -outputlayer pad_sig2_net_ntap |
| antenna psd sig2_pad -gt 0 -outputlayer pad_sig2_net_psd |
| antenna ptap sig2_pad -gt 0 -outputlayer pad_sig2_net_ptap |
| antenna poly sig2_pad -gt 0 -outputlayer pad_sig2_net_poly |
| antenna nwell sig2_pad -gt 0 -outputlayer pad_sig2_net_nw |
| antenna dnwell sig2_pad -gt 0 -outputlayer pad_sig2_net_dnw |
| antenna pwell sig2_pad -gt 0 -outputlayer pad_sig2_net_pw |
| antenna localSub sig2_pad -gt 0 -outputlayer pad_sig2_net_ls |
| antenna ptub sig2_pad -gt 0 -outputlayer pad_sig2_net_pt |
| or pad_sig2_net_nsd pad_sig2_net_ntap pad_sig2_net_psd pad_sig2_net_ptap -outputlayer pad_sig2_diff_all |
| rule "latchup.signal.3.1b" { |
| caption "latchup.signal.3.1b: signal connected ptap or P+ src/drn must have P+ tap guard ring connected to a ground pad" |
| not ( not ( select -interact ptap ( select -interact ptap_grd_ring pad_sig_net_ptap ) ) pad_gnd3_net_ptap ) pad_sig_net_ptap |
| or ( select -interact pad_sig_net_psd -gt 0 pad_sig2_net_nw -by_net ) ( select -inside pad_sig_net_psd ( not nwell pad_pwr3_net_nw ) ) -outputlayer exempt1 |
| not ( not pad_sig_net_psd ptap_grd_ring ) exempt1 |
| } |
| rule "latchup.signal.12a" { |
| caption "latchup.signal.12a: Minimum spacing between diff metallically connected to signal pad and grounded ndiff < 27.0" |
| select -interact pad_sig_net_psd -gt 0 pad_sig2_net_nw -by_net -outputlayer exempt1 |
| exte ( not pad_sig2_net_psd exempt1 ) pad_gnd3_net_nsd -lt 27.0 -abut -lt 90 -output region |
| } |
| rule "latchup.signal.12b" { |
| caption "latchup.signal.12b: Minimum spacing between pwell metallically connected to signal pad and grounded ndiff < 40.0" |
| exte pad_sig2_net_pw pad_gnd3_net_nsd -lt 40.0 -abut -lt 90 -output region |
| exte pad_sig2_net_ls pad_gnd3_net_nsd -lt 40.0 -abut -lt 90 -output region |
| exte pad_sig2_net_pt pad_gnd3_net_nsd -lt 40.0 -abut -lt 90 -output region |
| } |
| rule "latchup.signal.12c" { |
| caption "latchup.signal.12c: Minimum spacing between pdiff metallically connected to signal pad and grounded nwell < 40.0" |
| select -interact pad_sig_net_psd -gt 0 pad_sig2_net_nw -by_net -outputlayer exempt1 |
| exte ( not pad_sig2_net_psd exempt1 ) pad_gnd3_net_nw -lt 40.0 -abut -lt 90 -output region |
| } |
| rule "latchup.signal.12d" { |
| caption "latchup.signal.12d: Minimum spacing between pwell metallically connected to signal pad and grounded nwell < 40.0" |
| exte pad_sig2_net_pw pad_gnd3_net_nw -lt 40.0 -abut -lt 90 -output region |
| exte pad_sig2_net_ls pad_gnd3_net_nw -lt 40.0 -abut -lt 90 -output region |
| exte pad_sig2_net_pt pad_gnd3_net_nw -lt 40.0 -abut -lt 90 -output region |
| } |
| rule "latchup.signal.12e" { |
| caption "latchup.signal.12e: Minimum spacing between ndiff metallically connected to signal pad and positive power supply connected pdiff < 27.0" |
| select -interact pad_sig_net_nsd -gt 0 pad_sig2_net_pw -by_net -outputlayer exempt1 |
| select -inside pad_sig_net_nsd ptub -outputlayer exempt2 |
| or exempt1 exempt2 -outputlayer exempt |
| exte ( not pad_sig2_net_nsd exempt ) pad_pwr3_net_psd -lt 27.0 -abut -lt 90 -output region |
| } |
| rule "latchup.signal.12f" { |
| caption "latchup.signal.12f: Minimum spacing between nwell metallically connected to signal pad and positive power supply connected pdiff < 40.0" |
| exte pad_sig2_net_nw pad_pwr3_net_psd -lt 40.0 -abut -lt 90 -output region |
| } |
| rule "latchup.signal.12g" { |
| caption "latchup.signal.12g: Minimum spacing between non-isolated ndiff metallically connected to signal pad and positive power supply connected pwell < 40.0" |
| select -interact pad_sig_net_nsd -gt 0 pad_sig2_net_pw -by_net -outputlayer exempt1 |
| and nsd ptub -outputlayer nsd_in_ptub |
| exte ( not ( not pad_sig2_net_nsd nsd_in_ptub ) exempt1 ) pad_pwr3_net_pw -lt 40.0 -abut -lt 90 -output region |
| exte ( not ( not pad_sig2_net_nsd nsd_in_ptub ) exempt1 ) pad_pwr3_net_ls -lt 40.0 -abut -lt 90 -output region |
| exte ( not ( not pad_sig2_net_nsd nsd_in_ptub ) exempt1 ) pad_pwr3_net_pt -lt 40.0 -abut -lt 90 -output region |
| } |
| rule "latchup.signal.12h" { |
| caption "latchup.signal.12h: Minimum spacing between nwell metallically connected to signal pad and positive power supply connected pwell < 40.0" |
| exte pad_sig2_net_nw pad_pwr3_net_pw -lt 40.0 -abut -lt 90 -output region |
| exte pad_sig2_net_nw pad_pwr3_net_ls -lt 40.0 -abut -lt 90 -output region |
| exte pad_sig2_net_nw pad_pwr3_net_pt -lt 40.0 -abut -lt 90 -output region |
| } |
| rule "latchup.signal.12i" { |
| caption "latchup.signal.12i: Minimum spacing between pdiff metallically connected to signal pad and ndiff metallically connected to a different signal pad < 27.0" |
| exte pad_sig2_net_psd pad_sig2_net_nsd -lt 27.0 -abut -lt 90 -output region -not_connected |
| } |
| rule "latchup.signal.12j" { |
| caption "latchup.signal.12j: Minimum spacing between pdiff metallically connected to signal pad and nwell metallically connected to a different signal pad < 40.0" |
| select -interact pad_sig_net_psd -gt 0 pad_sig2_net_nw -by_net -outputlayer exempt1 |
| exte ( not pad_sig2_net_psd exempt1 ) pad_sig2_net_nw -lt 40.0 -abut -lt 90 -output region -not_connected |
| } |
| rule "latchup.signal.12k" { |
| caption "latchup.signal.12k: Minimum spacing between pwell metallically connected to signal pad and ndiff metallically connected to a different signal pad < 40.0" |
| exte pad_sig2_net_pw pad_sig2_net_nsd -lt 40.0 -abut -lt 90 -output region -not_connected |
| exte pad_sig2_net_ls pad_sig2_net_nsd -lt 40.0 -abut -lt 90 -output region -not_connected |
| exte pad_sig2_net_pt pad_sig2_net_nsd -lt 40.0 -abut -lt 90 -output region -not_connected |
| } |
| rule "latchup.signal.12l" { |
| caption "latchup.signal.12l: Minimum spacing between pwell metallically connected to signal pad and nwell metallically connected to a different signal pad < 40.0" |
| exte pad_sig2_net_pw pad_sig2_net_nw -lt 40.0 -abut -lt 90 -output region -not_connected |
| exte pad_sig2_net_ls pad_sig2_net_nw -lt 40.0 -abut -lt 90 -output region -not_connected |
| exte pad_sig2_net_pt pad_sig2_net_nw -lt 40.0 -abut -lt 90 -output region -not_connected |
| } |
| and pad_pwr3_net_psd ( or v5 v12 v20 ) -outputlayer hv_psd |
| select -enclose ( and nwell ( antenna -eq 0 nwell pad_pwr3_net_psd ) ) hv_psd -outputlayer at_risk_non_vcc_nw |
| and at_risk_non_vcc_nw hv_psd -outputlayer at_risk_non_vcc_nw_and_psd |
| select -enclose pad_sig2_net_pw pad_sig2_net_nsd -outputlayer exempt3 |
| select -enclose pad_pwr3_net_nw pad_pwr3_net_psd -outputlayer exempt4 |
| rule "latchup.signal.12m" { |
| caption "latchup.signal.12m: Minimum spacing between ndiff metallically connected to signal pad and pdiff in an At RISK Non_Vcc_nwell < 33.0" |
| exte ( not pad_sig2_net_nsd exempt3 ) ( not at_risk_non_vcc_nw_and_psd exempt4 ) -lt 33.0 -abut -lt 90 -output region |
| } |
| rule "latchup.signal.12n" { |
| caption "latchup.signal.12n: Minimum spacing between ndiff metallically connected to signal pad and At RISK Non_Vcc_nwell < 16.75" |
| exte ( not pad_sig2_net_nsd exempt3 ) ( not at_risk_non_vcc_nw exempt4 ) -lt 16.75 -abut -lt 90 -output region |
| } |
| rule "latchup.signal.12o" { |
| caption "latchup.signal.12o: Minimum spacing between pdiff metallically connected to signal pad and nwell connected to 1.8V (LV) or lower < 27.0" |
| exte pad_sig2_net_psd ( not nwell ( or v5 v12 v20 ) ) -lt 27.0 -abut -lt 90 -output region -measure all |
| } |
| rule "latchup.signal.12p" { |
| caption "latchup.signal.12p: Minimum spacing between pwell metallically connected to signal pad and nwell connected to 1.8V (LV) or lower < 40.0" |
| exte pad_sig2_net_pw ( not nwell ( or v5 v12 v20 ) ) -lt 40.0 -abut -lt 90 -output region -measure all |
| exte pad_sig2_net_ls ( not nwell ( or v5 v12 v20 ) ) -lt 40.0 -abut -lt 90 -output region -measure all |
| exte pad_sig2_net_pt ( not nwell ( or v5 v12 v20 ) ) -lt 40.0 -abut -lt 90 -output region -measure all |
| } |
| holes ptap -outputlayer holes_ptap_ring |
| select -interact ( holes ntap ) ( holes nwell ) -outputlayer holes_ntap_ring |
| select -touch ptap holes_ptap_ring -outputlayer ptap_ring |
| and ( select -interact nwell holes_ntap_ring ) ntap -outputlayer ntap_ring |
| select -touch ptap ( select -enclose ( holes ptap ) ntap_ring ) -outputlayer ptap_is_outer |
| select -interact ntap ( select -enclose ( holes ntap ) ptap_ring ) -outputlayer ntap_is_outer |
| or ptap_is_outer ntap_is_outer -outputlayer outer_ring |
| select -interact ptap ( select -inside ptap_ring ( holes ntap_ring ) ) -outputlayer ptap_is_inner |
| select -interact ntap ( select -inside ntap_ring ( holes ptap_ring ) ) -outputlayer ntap_is_inner |
| or ptap_is_inner ntap_is_inner -outputlayer inner_ring |
| and ( and ( and diff poly ) psdm ) nwell -outputlayer pmos_dev |
| not ( holes outer_ring ) ( or inner_ring ( holes inner_ring ) ) -outputlayer btw_rings |
| select -interact ( holes ntap_is_outer ) pad_sig2_net_nsd -outputlayer hole_is_outer_around_nsd_sig |
| select -interact ( select -donut nwell ) hole_is_outer_around_nsd_sig -outputlayer nw_is_outer_around_nsd_sig |
| select -enclose ( holes nw_is_outer_around_nsd_sig ) ptap_is_inner -outputlayer btw_rings_sig_1 |
| not btw_rings_sig_1 ptap_is_inner -outputlayer btw_rings_sig_2 |
| not btw_rings_sig_2 ( holes ptap_is_inner ) -outputlayer btw_rings_sig |
| rule "latchup.signal.13" { |
| caption "latchup.signal.13: P+ MOS device is not permitted between the inner p+ ring and outer n+/nwell ring or in the shared well of the outer N+/nwell ring" |
| select -interact ( and pmos_dev btw_rings ) ( holes nw_is_outer_around_nsd_sig ) -outputlayer part_1 |
| and ( select -interact nw_is_outer_around_nsd_sig outer_ring ) pmos_dev -outputlayer part_2 |
| merge ( or part_1 part_2 ) |
| } |
| and diffi diffres -outputlayer diff_res |
| rule "latchup.signal.14" { |
| caption "latchup.signal.14: diff:res is not allowed inside diff connected to a signal pad or in the shared well of the outer n+/nwell ring" |
| select -interact ( and diff_res btw_rings ) ( holes nw_is_outer_around_nsd_sig ) -outputlayer part_1 |
| and ( select -interact nw_is_outer_around_nsd_sig outer_ring ) diff_res -outputlayer part_2 |
| merge ( or part_1 part_2 ) |
| } |
| size pad_sig2_diff_all -by 100 -bevel 3 -outputlayer danger_zone |
| and gate danger_zone -outputlayer mos_gate_in_dz |
| select -touch ( or nsd psd ) mos_gate_in_dz -outputlayer mos_sd_in_dz |
| select -inside ptap at_risk_non_vcc_nw -outputlayer ptap_in_at_risk_nw |
| select -inside ntap at_risk_non_vcc_nw -outputlayer ntap_in_at_risk_nw |
| select -touch ptap ( select -enclose ( holes ptap ) at_risk_non_vcc_nw ) -outputlayer at_risk_nw_inner_ring |
| select -touch ntap ( select -enclose ( holes ntap ) at_risk_non_vcc_nw ) -outputlayer at_risk_nw_outer_ring |
| rule "latchup.special.1a.1" { |
| caption "latchup.special.1a.1: At risk non-Vcc nwell must be in an inner P+ tap connected to ground" |
| select -inside -not at_risk_non_vcc_nw ( select -interact at_risk_nw_inner_ring pad_gnd_net_ptap ) |
| } |
| select -enclose li_i ( and ( and licon li_i ) at_risk_nw_inner_ring ) -outputlayer li_in_at_risk_nw_ptap_ring |
| rule "latchup.special.1a.2" { |
| caption "latchup.special.1a.2: P+ tap around at risk Vcc nwell must be continuously strapped in local interconnect" |
| select -inside -not at_risk_non_vcc_nw ( holes li_in_at_risk_nw_ptap_ring ) |
| } |
| rule "latchup.special.1b.1" { |
| caption "latchup.special.1b.1: At risk non-Vcc nwell must be in an outer N+/NW guard ring connected to power" |
| select -interact at_risk_nw_outer_ring pad_pwr_net_ntap -outputlayer nw_outer_inter_gnd_net |
| select -interact at_risk_nw_inner_ring pad_gnd_net_ptap -outputlayer nw_inner_inter_pad_net |
| holes nw_outer_inter_gnd_net -outputlayer holes_outer_gr_gnd |
| select -enclose holes_outer_gr_gnd nw_inner_inter_pad_net -outputlayer outer_gr_enc_inner_gr |
| select -inside -not at_risk_non_vcc_nw outer_gr_enc_inner_gr |
| } |
| rule "latchup.special.1c.1" { |
| caption "latchup.special.1c.1: Maximum space between licons in inner P+ tap around at risk non-Vcc nwell > 2.0" |
| size ( and licon at_risk_nw_inner_ring ) -by 1 -inside_of li_i -outputlayer lic_size_atr_nw |
| not ( and li_i at_risk_nw_inner_ring ) lic_size_atr_nw |
| } |
| rule "latchup.special.1c.2" { |
| caption "latchup.special.1c.2: Maximum space between licons in outer N+ tap around at risk non-Vcc nwell > 2.0" |
| size ( and licon at_risk_nw_outer_ring ) -by 1 -inside_of li_i -outputlayer lic_size_atr_nw |
| not ( and li_i at_risk_nw_outer_ring ) lic_size_atr_nw |
| } |
| select -enclose li_i ( and ( and licon li_i ) at_risk_nw_outer_ring ) -outputlayer li_in_at_risk_nw_ntap_ring |
| rule "latchup.special.1b.2" { |
| caption "latchup.special.1b.2: N+ tap around at risk non-Vcc nwell must be continuously strapped in local interconnect" |
| select -inside -not at_risk_non_vcc_nw ( holes li_in_at_risk_nw_ptap_ring ) |
| } |
| rule "latchup.special.2a" { |
| caption "latchup.special.2a: PNP bipolar transistor must be inside inner P+ guardring tied to ground" |
| select -inside -not pnp ( holes ( select -interact ptap_is_inner pad_gnd_net_ptap ) ) |
| } |
| rule "latchup.special.2b" { |
| caption "latchup.special.2b: PNP bipolar transistor must be inside outer NW/N+ tap guardring tied to power" |
| select -inside -not pnp ( holes ( select -interact ntap_is_outer pad_pwr_net_ntap ) ) |
| } |
| select -touch ptap ( select -enclose ( holes ptap_is_inner ) pnp ) -outputlayer pnp_inner_ring |
| size ( and licon pnp_inner_ring ) -by 1 -inside_of li_i -outputlayer lic_size_inner_pnp |
| select -touch ntap ( select -enclose ( holes ntap_is_outer ) pnp ) -outputlayer pnp_outer_ring |
| size ( and licon pnp_outer_ring ) -by 1 -inside_of li_i -outputlayer lic_size_outer_pnp |
| rule "latchup.special.2c" { |
| caption "latchup.special.2c: Maximum space between licons in inner P+ tap around pnp > 2.0" |
| not ( and li_i pnp_inner_ring ) lic_size_inner_pnp |
| } |
| rule "latchup.special.2d" { |
| caption "latchup.special.2d: Maximum space between licons in outer N+ tap around pnp > 2.0" |
| not ( and li_i pnp_outer_ring ) lic_size_outer_pnp |
| } |
| rule "latchup.special.6" { |
| caption "latchup.special.6: There should not be any N+ diffusion between the P+ diffusion in the At Risk Non-Vcc nwell and the P+ tap ring" |
| select -enclose at_risk_non_vcc_nw ( not nsd ntap ) |
| } |
| rule "latchup.special.7a" { |
| caption "latchup.special.7a: Grounded nwell must be inside a P+ tap ring" |
| select -inside -not pad_gnd3_net_nw ( holes ptap_ring ) |
| } |
| rule "latchup.special.7b" { |
| caption "latchup.special.7b: Grounded nwell's P+ tap ring must be connected to gnd" |
| select -interact -not ( select -enclose ( holes ptap_ring ) pad_gnd3_net_nw ) pad_gnd3_net_ptap |
| } |
| antenna met5 pad -gt 0 -outputlayer pad_net_m5 |
| antenna met4 pad -gt 0 -outputlayer pad_net_m4 |
| antenna met3 pad -gt 0 -outputlayer pad_net_m3 |
| antenna met2 pad -gt 0 -outputlayer pad_net_m2 |
| antenna met1 pad -gt 0 -outputlayer pad_net_m1 |
| antenna li pad -gt 0 -outputlayer pad_net_li |
| antenna nsd pad -gt 0 -outputlayer pad_net_nsd |
| antenna psd pad -gt 0 -outputlayer pad_net_psd |
| select -touch ( not gate ESDID ) pad_net_nsd -outputlayer target_ngate |
| select -interact ( not gate ESDID ) pad_net_nsd -gt 1 -by_net -outputlayer target_ngate_2_pad |
| select -touch ( not gate ESDID ) pad_net_psd -outputlayer target_pgate |
| select -interact ( not gate ESDID ) pad_net_psd -gt 1 -by_net -outputlayer target_pgate_2_pad |
| rule "latchup.misc.4" { |
| caption "latchup.misc.4: Non-ESD nfet or pfet with src connected to one pad and drn connected to different pad min width < 2000.0" |
| edge_length ( edge_boolean -coincident_only -not target_ngate_2_pad nsd ) -lt 2000 -outputlayer mark1 |
| edge_length ( edge_boolean -coincident_only -not target_pgate_2_pad psd ) -lt 2000 -outputlayer mark2 |
| edge_expand mark1 -outside_by 0.005 -outputlayer mark1_exp |
| edge_expand mark2 -outside_by 0.005 -outputlayer mark2_exp |
| select -interact ( not gate ESDID ) ( or mark1_exp mark2_exp ) |
| } |
| not pwell pw_res_gt_1kohm -outputlayer pw_lu_x |
| not diffi diff_res_gt_1kohm -outputlayer diff_lu_x |
| not ( not ( not ( and diffi nsdm ) poly ) nwell ) diff_res_gt_1kohm -outputlayer nsd_lu_x |
| not ( and ( not ( and diffi psdm ) poly ) nwell ) diff_res_gt_1kohm -outputlayer psd_lu_x |
| not polyi poly_res_gt_1kohm -outputlayer poly_lu_x |
| not li_i li_res_gt_1kohm -outputlayer li_lu_x |
| not met1i m1_res_gt_1kohm -outputlayer m1_lu_x |
| not met2i m2_res_gt_1kohm -outputlayer m2_lu_x |
| not met3i m3_res_gt_1kohm -outputlayer m3_lu_x |
| not met4i m4_res_gt_1kohm -outputlayer m4_lu_x |
| not met5i m5_res_gt_1kohm -outputlayer m5_lu_x |
| |
| disconnect |
| connect m5_lu_x m4_lu_x -by via4_c |
| connect m4_lu_x m3_lu_x -by via3_c |
| connect m3_lu_x m2_lu_x -by via2 |
| connect m2_lu_x m1_lu_x -by via1 |
| connect m1_lu_x li_lu_x -by mcon |
| connect li_lu_x nsd_lu_x -by licon |
| connect li_lu_x psd_lu_x -by licon |
| connect li_lu_x ntap -by licon |
| connect li_lu_x ptap -by licon |
| connect li_lu_x ptubtap -by licon |
| connect li_lu_x poly_lu_x -by licon |
| |
| connect ntap nwell |
| connect ptap pw_lu |
| connect ptubtap ptub |
| connect nwell dnwell |
| |
| connect m5_lu_x pad |
| connect m5_lu_x uprobe_pad |
| connect m5_lu_x probe_pad |
| connect rdl pad |
| connect rdl uprobe_pad |
| connect rdl probe_pad |
| |
| |
| select -interact pad pad_gnd -outputlayer gnd_pad2_x |
| and ( and gate ( or v12 v20 ) ) thkox -outputlayer shv_gate |
| select -enclose dnwell shv_gate -outputlayer dnw_with_shv_gate |
| rule "latchup.shv.1" { |
| caption "latchup.shv.1: DNW connected to ground < 1000 ohm is not allowed if the DNW contains super high voltage connected active NFETs or PFETs" |
| antenna dnw_with_shv_gate gnd_pad2_x -gt 0 |
| } |
| select -interact pad pad_pwr -outputlayer pwr2_pad_y |
| antenna m5_lu_x pwr2_pad_y -gt 0 -outputlayer pad_pwr2_net_m5_y |
| antenna m4_lu_x pwr2_pad_y -gt 0 -outputlayer pad_pwr2_net_m4_y |
| antenna m3_lu_x pwr2_pad_y -gt 0 -outputlayer pad_pwr2_net_m3_y |
| antenna m2_lu_x pwr2_pad_y -gt 0 -outputlayer pad_pwr2_net_m2_y |
| antenna m1_lu_x pwr2_pad_y -gt 0 -outputlayer pad_pwr2_net_m1_y |
| antenna li_lu_x pwr2_pad_y -gt 0 -outputlayer pad_pwr2_net_li_y |
| antenna nsd_lu_x pwr2_pad_y -gt 0 -outputlayer pad_pwr2_net_nsd_y |
| antenna ntap pwr2_pad_y -gt 0 -outputlayer pad_pwr2_net_ntap_y |
| antenna psd_lu_x pwr2_pad_y -gt 0 -outputlayer pad_pwr2_net_psd_y |
| antenna ptap pwr2_pad_y -gt 0 -outputlayer pad_pwr2_net_ptap_y |
| antenna poly_lu_x pwr2_pad_y -gt 0 -outputlayer pad_pwr2_net_poly_y |
| antenna pw_lu pwr2_pad_y -gt 0 -outputlayer pad_pwr2_net_pw_y |
| rule "latchup.shv.2" { |
| caption "latchup.shv.2: Minimum distance between NW/DNW connected metallically to SHV signal pad to a P+ diff connected to a positive power supply < 70 um" |
| and pad_sig2_net_dnw ( or v12 v20 ) -outputlayer pad_dnw_sig_v20 |
| and pad_sig2_net_nw ( or v12 v20 ) -outputlayer pad_nw_sig_v20 |
| exte pad_dnw_sig_v20 pad_pwr2_net_psd_y -lt 70.0 -abut -lt 90 -output region |
| exte pad_nw_sig_v20 pad_pwr2_net_psd_y -lt 70.0 -abut -lt 90 -output region |
| exte pad_dnw_sig_v20 pad_pwr2_net_ptap_y -lt 70.0 -abut -lt 90 -output region |
| exte pad_nw_sig_v20 pad_pwr2_net_ptap_y -lt 70.0 -abut -lt 90 -output region |
| exte pad_dnw_sig_v20 pad_pwr2_net_pw_y -lt 70.0 -abut -lt 90 -output region -measure all |
| exte pad_nw_sig_v20 pad_pwr2_net_pw_y -lt 70.0 -abut -lt 90 -output region -measure all |
| } |
| rule "latchup.shv.3" { |
| caption "latchup.shv.3: Minimum distance between PW connected metallically to SHV signal pad to any N+ diff/tap/NW/DNW connected to a ground < 100" |
| and pad_sig2_net_pw ( or v12 v20 ) -outputlayer pad_pw_sig_v20a |
| and pad_sig2_net_ls ( or v12 v20 ) -outputlayer pad_pw_sig_v20b |
| and pad_sig2_net_pt ( or v12 v20 ) -outputlayer pad_pw_sig_v20c |
| or pad_pw_sig_v20a pad_pw_sig_v20b pad_pw_sig_v20c -outputlayer pad_pw_sig_v20 |
| exte pad_pw_sig_v20 pad_gnd2_net_ntap -lt 100 -abut -lt 90 -output region |
| exte pad_pw_sig_v20 pad_gnd2_net_nsd -lt 100 -abut -lt 90 -output region |
| exte pad_pw_sig_v20 pad_gnd2_net_nw -lt 100 -abut -lt 90 -output region |
| exte pad_pw_sig_v20 pad_gnd2_net_dnw -lt 100 -abut -lt 90 -output region |
| } |
| |
| #ENDIF //not skip latchup checks |
| |
| |
| |
| // |
| // LONELY VIA/CONTACT rules |
| // |
| |
| #IFNDEF SKIP_RECOMMENDED_CHECKS |
| |
| //LICON (on poly): |
| // licon size 0.17 |
| // licon space 0.17 |
| // li enc licon 0.08 |
| // poly enc licon 0.05 |
| |
| not ( and li_i polyi ) diffi -outputlayer lipl |
| size licon -by .42 -inside_of lipl -outputlayer lic_size_pl |
| size licon -by .17 -inside_of lipl -outputlayer lic_space_size_pl |
| select -interact -not ( not ( select -enclose lipl lic_size_pl ) lic_space_size_pl ) licon -outputlayer lipl_no_lic |
| with_width lipl_no_lic -gt 0.29 -outputlayer potential_area_for_lic_pl |
| inside_cell polyii "esd*" -outputlayer pl_excl_area |
| inside_cell li_ii "esd*" -outputlayer li_excl_area |
| or pl_excl_area li_excl_area -outputlayer lic_excl_area_pl |
| select -interact -not ( select -enclose ( select -touch ( rect_chk ( not polyii gate ) ) gate -eq 1 ) licon -eq 1 ) met1 -outputlayer poly_gate_stub |
| rule "lonely.poly.licon.R" { |
| caption "lonely.poly.licon.R: There may be room for additional licon(s) in this poly/li area" |
| select -enclose ( select -interact -not ( not ( select -interact lipl potential_area_for_lic_pl ) lic_excl_area_pl ) poly_gate_stub ) -lt 2 licon |
| } |
| not ( and ( select -enclose ( not polyi gate ) licon -eq 1 ) li ) STDCID -outputlayer potential_area_for_more_poly |
| size potential_area_for_more_poly -by 0.51 -outputlayer potential_area_for_more_poly_size |
| size potential_area_for_more_poly_size -by 1 -outputlayer potential_area_for_more_poly_size_halo |
| not ( and potential_area_for_more_poly_size_halo ( or polyi diff1 licon ) ) potential_area_for_more_poly -outputlayer potential_area_for_more_poly_size_block1 |
| size ( and poly potential_area_for_more_poly_size_block1 ) -by 0.34 -outputlayer potential_area_for_more_poly_size_block |
| select -enclose potential_area_for_more_poly_size_block ( and polyi potential_area_for_more_poly_size_block ) -lt 2 -outputlayer potential_area_for_pl_lic_1 |
| select -enclose potential_area_for_more_poly_size_block ( and li potential_area_for_more_poly_size_block ) -lt 2 -outputlayer potential_area_for_pl_lic_2 |
| select -enclose potential_area_for_more_poly_size_block ( and diffi potential_area_for_more_poly_size_block ) -lt 1 -outputlayer potential_area_for_pl_lic_3 |
| not ( and potential_area_for_pl_lic_1 potential_area_for_pl_lic_2 ) potential_area_for_pl_lic_3 -outputlayer potential_area_for_pl_lic_a |
| rect_chk licon -eq 0.17 -by -eq 0.17 -outputlayer sq_licon |
| not licon sq_licon -outputlayer non_sq_licon |
| select -interact -not potential_area_for_pl_lic_a non_sq_licon -outputlayer potential_area_for_pl_lic |
| select -interact ( not polyi gate ) ( inte ( size gate -by 1 -inside_of polyi ) -lt 0.505 -abut -lt 90 -output region ) -outputlayer gate_extension_lt_pt_5 |
| select -interact -not ( select -enclose ( or ( select -interact potential_area_for_pl_lic potential_area_for_more_poly ) potential_area_for_more_poly ) sq_licon -eq 1 ) gate_extension_lt_pt_5 -outputlayer potential_area_for_pl_lonely_yes |
| rule "lonely.poly.licon.a.R" { |
| caption "lonely.poly.licon.a.R: By adding additional poly and/or li, there may be room for additional licons" |
| copy ( merge ( not ( and ( not ( and polyi li ) gate ) potential_area_for_pl_lonely_yes ) poly_gate_stub ) ) |
| } |
| |
| //LICON (on diff): |
| // licon size 0.17 |
| // licon space 0.17 |
| // li enc licon 0.08 |
| // diff enc licon 0.12 |
| |
| |
| not ( and li_i diffi ) polyi -outputlayer lidf |
| size licon -by .54 -inside_of lidf -outputlayer lic_size_df |
| size licon -by .17 -inside_of lidf -outputlayer lic_space_size_df |
| select -interact -not ( not ( select -enclose lidf lic_size_df ) lic_space_size_df ) licon -outputlayer lidf_no_lic |
| with_width lidf_no_lic -gt 0.29 -outputlayer potential_area_for_lic_df |
| inside_cell diffii "esd*" -outputlayer df_excl_area |
| or df_excl_area li_excl_area -outputlayer lic_excl_area_df |
| rule "lonely.diff.licon.R" { |
| caption "lonely.diff.licon.R: There may be room for additional licon(s) in this diff/li area" |
| select -enclose ( not ( select -interact lidf potential_area_for_lic_df ) lic_excl_area_df ) -lt 2 licon |
| } |
| not ( and ( select -enclose ( not diffi gate ) licon -eq 1 ) li ) STDCID -outputlayer potential_area_for_more_diff |
| size potential_area_for_more_diff -by 0.51 -outputlayer potential_area_for_more_diff_size |
| size potential_area_for_more_diff_size -by 1 -outputlayer potential_area_for_more_diff_size_halo |
| not ( and potential_area_for_more_diff_size_halo ( or polyi diff1 licon ) ) potential_area_for_more_diff -outputlayer potential_area_for_more_diff_size_block1 |
| size ( and diffi potential_area_for_more_diff_size_block1 ) -by 0.34 -outputlayer potential_area_for_more_diff_size_block |
| select -enclose potential_area_for_more_diff_size_block ( and diffi potential_area_for_more_diff_size_block ) -lt 2 -outputlayer potential_area_for_df_lic_1 |
| select -enclose potential_area_for_more_diff_size_block ( and li potential_area_for_more_diff_size_block ) -lt 2 -outputlayer potential_area_for_df_lic_2 |
| select -enclose potential_area_for_more_diff_size_block ( and ( size licon -by 0.17 ) potential_area_for_more_diff_size_block ) -lt 1 -outputlayer potential_area_for_df_lic_3 |
| not ( and potential_area_for_df_lic_1 potential_area_for_df_lic_2 ) potential_area_for_df_lic_3 -outputlayer potential_area_for_df_lic_a |
| select -interact -not potential_area_for_df_lic_a non_sq_licon -outputlayer potential_area_for_df_lic |
| select -interact -not ( select -enclose ( or ( select -interact potential_area_for_df_lic potential_area_for_more_diff ) potential_area_for_more_diff ) sq_licon -eq 1 ) gate_extension_lt_pt_5 -outputlayer potential_area_for_df_lonely_yes |
| rule "lonely.diff.licon.a.R" { |
| caption "lonely.diff.licon.a.R: By adding additional diff and/or li, there may be room for additional licons" |
| copy ( merge ( and ( not ( and diffi li ) gate ) potential_area_for_df_lonely_yes ) ) |
| } |
| |
| // MCON: |
| // mcon size 0.17 |
| // mcon space 0.19 |
| // m1 enc mcon 0.03 |
| // li enc mcon 0.0 |
| |
| |
| |
| and met1i li_i -outputlayer m1l1 |
| size mcon -by .39 -inside_of m1l1 -outputlayer mcon_size |
| size mcon -by .19 -inside_of m1l1 -outputlayer mcon_space_size |
| select -interact -not ( not ( select -enclose m1l1 mcon_size ) mcon_space_size ) mcon -outputlayer m1l1_no_mcon |
| with_width m1l1_no_mcon -ge 0.25 -outputlayer potential_area_for_mcon |
| inside_cell met1ii "esd*" -outputlayer mcon_m1_excl_area |
| inside_cell li_ii "esd*" -outputlayer mcon_l1_excl_area |
| or mcon_m1_excl_area mcon_l1_excl_area -outputlayer mcon_excl_area |
| rule "lonely.mcon.R" { |
| caption "lonely.mcon.R: There may be room for additional metal contact(s)" |
| select -enclose ( not ( select -interact m1l1 potential_area_for_mcon ) mcon_excl_area ) -lt 2 mcon |
| } |
| not ( select -enclose ( and met1i li_i ) mcon -eq 1 ) STDCID -outputlayer potential_area_for_more_mcon |
| size potential_area_for_more_mcon -by 0.53 -outputlayer potential_area_for_more_mcon_size |
| size potential_area_for_more_mcon_size -by 1 -outputlayer potential_area_for_more_mcon_size_halo |
| not ( and potential_area_for_more_mcon_size_halo ( or met1i li_i mcon ) ) potential_area_for_more_mcon -outputlayer potential_area_for_more_mcon_size_block1 |
| size ( and met1i potential_area_for_more_mcon_size_block1 ) -by 0.28 -outputlayer potential_area_for_more_mcon_size_block |
| select -enclose potential_area_for_more_mcon_size_block ( and met1i potential_area_for_more_mcon_size_block ) -lt 2 -outputlayer potential_area_for_m1_lic_1 |
| select -enclose potential_area_for_more_mcon_size_block ( and li_i potential_area_for_more_mcon_size_block ) -lt 2 -outputlayer potential_area_for_m1_lic_2 |
| select -enclose potential_area_for_more_mcon_size_block ( and ( size mcon -by 0.19 ) potential_area_for_more_mcon_size_block ) -lt 1 -outputlayer potential_area_for_m1_lic_3 |
| not ( and potential_area_for_m1_lic_1 potential_area_for_m1_lic_2 ) potential_area_for_m1_lic_3 -outputlayer potential_area_for_m1_lic |
| or ( select -interact potential_area_for_m1_lic potential_area_for_more_mcon ) potential_area_for_more_mcon -outputlayer potential_area_for_m1_lonely_yes |
| rule "lonely.mcon.a.R" { |
| caption "lonely.mcon.a.R: By adding additional met1 and/or li, there may be room for additional mcons" |
| copy ( merge ( and ( and met1i li ) potential_area_for_m1_lonely_yes ) ) |
| } |
| |
| // VIA: |
| // via size 0.15 |
| // m1 enc via 0.085 (adj sides) |
| // via space 0.17 |
| // m2 enc via 0.085 (adj sides) |
| |
| |
| and met1i met2i -outputlayer m1m2 |
| size via1 -by .405 -inside_of m1m2 -outputlayer via_size |
| size via1 -by .17 -inside_of m1m2 -outputlayer via_space_size |
| select -interact -not ( not ( select -enclose m1m2 via_size ) via_space_size ) via1 -outputlayer m1m2_no_via |
| with_width m1m2_no_via -ge 0.235 -outputlayer potential_area_for_via |
| inside_cell met1ii "esd*" -outputlayer via_m1_excl_area |
| inside_cell met2ii "esd*" -outputlayer via_m2_excl_area |
| or via_m1_excl_area via_m2_excl_area -outputlayer via_excl_area |
| rule "lonely.via1.R" { |
| caption "lonely.via1.R: There may be room for additional via1(s)" |
| select -enclose ( not ( select -interact m1m2 potential_area_for_via ) via_excl_area ) -lt 2 via1 |
| } |
| not ( select -enclose ( and met1i met2i ) via1 -eq 1 ) STDCID -outputlayer potential_area_for_more_via |
| size potential_area_for_more_via -by 0.49 -outputlayer potential_area_for_more_via_size |
| size potential_area_for_more_via_size -by 1 -outputlayer potential_area_for_more_via_size_halo |
| not ( and potential_area_for_more_via_size_halo ( or met1i via1 met2i ) ) potential_area_for_more_via -outputlayer potential_area_for_more_via_size_block1 |
| size ( and met1i potential_area_for_more_via_size_block1 ) -by 0.28 -outputlayer potential_area_for_more_via_size_block |
| select -enclose potential_area_for_more_via_size_block ( and met1i potential_area_for_more_via_size_block ) -lt 2 -outputlayer potential_area_for_v1_lic_1 |
| select -enclose potential_area_for_more_via_size_block ( and met2i potential_area_for_more_via_size_block ) -lt 2 -outputlayer potential_area_for_v1_lic_2 |
| select -enclose potential_area_for_more_via_size_block ( and ( size via1 -by 0.17 ) potential_area_for_more_via_size_block ) -lt 1 -outputlayer potential_area_for_v1_lic_3 |
| not ( and potential_area_for_v1_lic_1 potential_area_for_v1_lic_2 ) potential_area_for_v1_lic_3 -outputlayer potential_area_for_v1_lic |
| or ( select -interact potential_area_for_v1_lic potential_area_for_more_via ) potential_area_for_more_via -outputlayer potential_area_for_v1_lonely_yes |
| rule "lonely.via1.a.R" { |
| caption "lonely.via1.a.R: By adding additional met1 and/or met2, there may be room for additional via1s" |
| copy ( merge ( and ( and met1i met2i ) potential_area_for_v1_lonely_yes ) ) |
| } |
| |
| // VIA2: |
| // via2 size 0.2 |
| // m2 enc via2 0.065 (adj sides) |
| // via2 space 0.20 |
| // m3 enc via2 0.065 (adj sides) |
| |
| |
| and met2i met3i -outputlayer m2m3 |
| size via2 -by .465 -inside_of m2m3 -outputlayer via2_size |
| size via2 -by .2 -inside_of m2m3 -outputlayer via2_space_size |
| select -interact -not ( not ( select -enclose m2m3 via2_size ) via2_space_size ) via2 -outputlayer m2m3_no_via2 |
| with_width m2m3_no_via2 -ge 0.265 -outputlayer potential_area_for_via2 |
| inside_cell met2ii "esd*" -outputlayer via2_m2_excl_area |
| inside_cell met3ii "esd*" -outputlayer via2_m3_excl_area |
| or via2_m2_excl_area via2_m3_excl_area -outputlayer via2_excl_area |
| rule "lonely.via2.R" { |
| caption "lonely.via2.R: There may be room for additional via2(s)" |
| select -enclose ( not ( select -interact m2m3 potential_area_for_via2 ) via2_excl_area ) -lt 2 via2 |
| } |
| rect_chk via2 -eq 0.2 -by -eq 0.2 -outputlayer small_v2 |
| not ( select -enclose ( and met2i met3i ) small_v2 -eq 1 ) STDCID -outputlayer potential_area_for_more_via2 |
| size potential_area_for_more_via2 -by 0.54 -outputlayer potential_area_for_more_via2_size |
| size potential_area_for_more_via2_size -by 1 -outputlayer potential_area_for_more_via2_size_halo |
| not ( and potential_area_for_more_via2_size_halo ( or met2i via1 met3i ) ) potential_area_for_more_via2 -outputlayer potential_area_for_more_via2_size_block1 |
| size ( and met2i potential_area_for_more_via2_size_block1 ) -by 0.28 -outputlayer potential_area_for_more_via2_size_block |
| select -enclose potential_area_for_more_via2_size_block ( and met2i potential_area_for_more_via2_size_block ) -lt 2 -outputlayer potential_area_for_v2_lic_1 |
| select -enclose potential_area_for_more_via2_size_block ( and met3i potential_area_for_more_via2_size_block ) -lt 2 -outputlayer potential_area_for_v2_lic_2 |
| select -enclose potential_area_for_more_via2_size_block ( and ( size via2 -by 0.17 ) potential_area_for_more_via2_size_block ) -lt 1 -outputlayer potential_area_for_v2_lic_3 |
| not ( and potential_area_for_v2_lic_1 potential_area_for_v2_lic_2 ) potential_area_for_v2_lic_3 -outputlayer potential_area_for_v2_lic |
| or ( select -interact potential_area_for_v2_lic potential_area_for_more_via2 ) potential_area_for_more_via2 -outputlayer potential_area_for_v2_lonely_yes |
| rule "lonely.via2.a.R" { |
| caption "lonely.via2.a.R: By adding additional met2 and/or met3, there may be room for additional via2s" |
| copy ( merge ( and ( and met2i met3i ) potential_area_for_v2_lonely_yes ) ) |
| } |
| |
| // VIA3: |
| // via3 size 0.2 |
| // m3 enc via3 0.09 (adj sides) |
| // via3 space 0.20 |
| // m4 enc via3 0.065 (adj sides) |
| |
| |
| and met3i met4i -outputlayer m3m4 |
| size via3 -by .49 -inside_of m3m4 -outputlayer via3_size |
| size via3 -by .2 -inside_of m3m4 -outputlayer via3_space_size |
| select -interact -not ( not ( select -enclose m3m4 via3_size ) via3_space_size ) via3 -outputlayer m3m4_no_via3 |
| with_width m3m4_no_via3 -ge 0.29 -outputlayer potential_area_for_via3 |
| inside_cell met3ii "esd*" -outputlayer via3_m3_excl_area |
| inside_cell met4ii "esd*" -outputlayer via3_m4_excl_area |
| or via3_m3_excl_area via3_m4_excl_area -outputlayer via3_excl_area |
| rule "lonely.via3.R" { |
| caption "lonely.via3.R: There may be room for additional via3(s)" |
| select -enclose ( not ( select -interact m3m4 potential_area_for_via3 ) via3_excl_area ) -lt 2 via3 |
| } |
| rect_chk via3 -eq 0.2 -by -eq 0.2 -outputlayer small_v3 |
| not ( select -enclose ( and met3i met4i ) small_v3 -eq 1 ) STDCID -outputlayer potential_area_for_more_via3 |
| size potential_area_for_more_via3 -by 0.54 -outputlayer potential_area_for_more_via3_size |
| size potential_area_for_more_via3_size -by 1 -outputlayer potential_area_for_more_via3_size_halo |
| not ( and potential_area_for_more_via3_size_halo ( or met3i via1 met4i ) ) potential_area_for_more_via3 -outputlayer potential_area_for_more_via3_size_block1 |
| size ( and met3i potential_area_for_more_via3_size_block1 ) -by 0.28 -outputlayer potential_area_for_more_via3_size_block |
| select -enclose potential_area_for_more_via3_size_block ( and met3i potential_area_for_more_via3_size_block ) -lt 2 -outputlayer potential_area_for_v3_lic_1 |
| select -enclose potential_area_for_more_via3_size_block ( and met4i potential_area_for_more_via3_size_block ) -lt 2 -outputlayer potential_area_for_v3_lic_2 |
| select -enclose potential_area_for_more_via3_size_block ( and ( size via3 -by 0.17 ) potential_area_for_more_via3_size_block ) -lt 1 -outputlayer potential_area_for_v3_lic_3 |
| not ( and potential_area_for_v3_lic_1 potential_area_for_v3_lic_2 ) potential_area_for_v3_lic_3 -outputlayer potential_area_for_v3_lic |
| or ( select -interact potential_area_for_v3_lic potential_area_for_more_via3 ) potential_area_for_more_via3 -outputlayer potential_area_for_v3_lonely_yes |
| rule "lonely.via3.a.R" { |
| caption "lonely.via3.a.R: By adding additional met3 and/or met4, there may be room for additional via3s" |
| copy ( merge ( and ( and met3i met4i ) potential_area_for_v3_lonely_yes ) ) |
| } |
| |
| // VIA4: |
| // via4 size 0.8 |
| // m4 enc via4 0.06 (adj sides) |
| // via4 space 0.80 |
| // m5 enc via4 0.310 (adj sides) |
| |
| |
| and met4i met5i -outputlayer m4m5 |
| size via4 -by 1.91 -inside_of m4m5 -outputlayer via4_size |
| size via4 -by 0.8 -inside_of m4m5 -outputlayer via4_space_size |
| select -interact -not ( not ( select -enclose m4m5 via4_size ) via4_space_size ) via4 -outputlayer m4m5_no_via4 |
| with_width m4m5_no_via4 -ge 1.11 -outputlayer potential_area_for_via4 |
| inside_cell met4ii "esd*" -outputlayer via4_m4_excl_area |
| inside_cell met5ii "esd*" -outputlayer via4_m5_excl_area |
| or via4_m4_excl_area via4_m5_excl_area -outputlayer via4_excl_area |
| rule "lonely.via4.R" { |
| caption "lonely.via4.R: There may be room for additional via4(s)" |
| select -enclose ( not ( select -interact m4m5 potential_area_for_via4 ) via4_excl_area ) -lt 2 via4 |
| } |
| not ( select -enclose ( and met4i met5i ) via4 -eq 1 ) STDCID -outputlayer potential_area_for_more_via4 |
| size potential_area_for_more_via3 -by 1.6 -outputlayer potential_area_for_more_via4_size |
| size potential_area_for_more_via4_size -by 1.5 -outputlayer potential_area_for_more_via4_size_halo |
| not ( and potential_area_for_more_via4_size_halo ( or met4i via1 met5i ) ) potential_area_for_more_via4 -outputlayer potential_area_for_more_via4_size_block1 |
| size ( and met4i potential_area_for_more_via4_size_block1 ) -by 0.3 -outputlayer potential_area_for_more_via4_size_block |
| select -enclose potential_area_for_more_via4_size_block ( and met4i potential_area_for_more_via4_size_block ) -lt 2 -outputlayer potential_area_for_v4_lic_1 |
| select -enclose potential_area_for_more_via4_size_block ( and met5i potential_area_for_more_via4_size_block ) -lt 2 -outputlayer potential_area_for_v4_lic_2 |
| select -enclose potential_area_for_more_via4_size_block ( and ( size via4 -by 0.8 ) potential_area_for_more_via4_size_block ) -lt 1 -outputlayer potential_area_for_v4_lic_3 |
| not ( and potential_area_for_v4_lic_1 potential_area_for_v4_lic_2 ) potential_area_for_v4_lic_3 -outputlayer potential_area_for_v4_lic |
| or ( select -interact potential_area_for_v4_lic potential_area_for_more_via4 ) potential_area_for_more_via4 -outputlayer potential_area_for_v4_lonely_yes |
| rule "lonely.via4.a.R" { |
| caption "lonely.via4.a.R: By adding additional met4 and/or met5, there may be room for additional via4s" |
| copy ( merge ( and ( and met4i met5i ) potential_area_for_v4_lonely_yes ) ) |
| } |
| |
| #ENDIF |
| |
| |
| |
| // |
| // FLOATING interconnect check |
| // |
| |
| #IFNDEF SKIP_RECOMMENDED_CHECKS |
| not ( not ( not ( and diff psdm ) nwell ) ptub ) ptubtap -outputlayer ptap_1 |
| and ( and diff nsdm ) nwell -outputlayer ntap_1 |
| not ( not ( and diff nsdm ) nwell ) gate -outputlayer nsd1 |
| not ( and ( and diff psdm ) nwell ) gate -outputlayer psd1 |
| not ( and ( not ( and ( and ( and gate nsdm ) v12 ) ENID ) nwell ) thkox ) ( or v5 v20 ESDID LVID pnp npn ) -outputlayer ngate_de_12v_pw |
| and ngate_de_12v_pw poly -outputlayer ngate_de_12v_gate_conn |
| select -interact nsd1 ngate_de_12v_pw -outputlayer nsrc_de_12v |
| and ( not ( not ( select -interact ( select -enclose ENID ntap_1 ) ngate_de_12v_pw ) ngate_de_12v_pw ) nsrc_de_12v ) nwell -outputlayer ndrn_de_12v |
| not ( and ( and ( and ( and ( and gate psdm ) v12 ) ENID ) nwell ) thkox ) ( or v5 v20 ESDID LVID pnp npn ) -outputlayer pgate_de_12v_pw |
| select -interact psd1 pgate_de_12v_pw -outputlayer psrc_de_12v |
| not ( not ( not ( select -enclose ( select -enclose ENID ptap_1 ) pgate_de_12v_pw ) pgate_de_12v_pw ) psrc_de_12v ) nwell -outputlayer pdrn_de_12v |
| and pgate_de_12v_pw poly -outputlayer pgate_de_12v_gate_conn |
| and ( and pwres psdm ) ( and ( holes nwell ) dnwell ) -outputlayer pwres_rec |
| select -touch ( select -enclose ( not psdm pwres ) diff ) pwres_rec -eq 1 -outputlayer pwres_term |
| and poly polyres -outputlayer hp_poly_1 |
| and hp_poly_1 npc -outputlayer hp_poly_2 |
| and hp_poly_2 psdm -outputlayer hp_poly_3 |
| and hp_poly_3 rpm -outputlayer hp_poly |
| and poly polyres -outputlayer hs_poly_1 |
| and hs_poly_1 npc -outputlayer hs_poly_2 |
| and hs_poly_2 psdm -outputlayer hs_poly_3 |
| and hs_poly_3 urpm -outputlayer hs_poly |
| and met4 cap2m -outputlayer m4_cap_m45_con |
| and met5 cap2m -outputlayer m5_cap_m45_con |
| copy m4_cap_m45_con -outputlayer cap45_m4 |
| copy m5_cap_m45_con -outputlayer cap45_m5 |
| and met3 capm -outputlayer m3_cap_m34 |
| and met3 capm -outputlayer m3_cap_m34_con |
| and met4 capm -outputlayer m4_cap_m34_con |
| copy m3_cap_m34_con -outputlayer cap34_m3 |
| copy m4_cap_m34_con -outputlayer cap34_m4 |
| not li_i lires -outputlayer li_1 |
| edge_expand ( edge_boolean -coincident_only -outside li_1 lires ) -inside_by 0.005 -outputlayer li_res_term |
| copy li_res_term -outputlayer li_res_cont |
| not met1 m1res -outputlayer m1 |
| edge_expand ( edge_boolean -coincident_only -outside m1 m1res ) -inside_by 0.005 -outputlayer m1_res_term |
| copy m1_res_term -outputlayer m1_res_cont |
| not met2 m2res -outputlayer m2 |
| edge_expand ( edge_boolean -coincident_only -outside m2 m2res ) -inside_by 0.005 -outputlayer m2_res_term |
| copy m2_res_term -outputlayer m2_res_cont |
| not met3 m3res -outputlayer m3 |
| edge_expand ( edge_boolean -coincident_only -outside m3 m3res ) -inside_by 0.005 -outputlayer m3_res_term |
| copy m3_res_term -outputlayer m3_res_cont |
| not met4 m4res -outputlayer m4 |
| edge_expand ( edge_boolean -coincident_only -outside m4 m4res ) -inside_by 0.005 -outputlayer m4_res_term |
| copy m4_res_term -outputlayer m4_res_cont |
| not met5 m5res -outputlayer m5 |
| edge_expand ( edge_boolean -coincident_only -outside m5 m5res ) -inside_by 0.005 -outputlayer m5_res_term |
| copy m5_res_term -outputlayer m5_res_cont |
| not polyi polyres -outputlayer ply |
| edge_expand ( edge_boolean -coincident_only -outside ply polyres ) -inside_by 0.005 -outputlayer pl_res_term |
| copy pl_res_term -outputlayer pl_res_cont |
| edge_expand ( edge_boolean -coincident_only -outside nsd diffres ) -inside_by 0.005 -outputlayer df_res_nterm |
| edge_expand ( edge_boolean -coincident_only -outside psd diffres ) -inside_by 0.005 -outputlayer df_res_pterm |
| copy df_res_nterm -outputlayer df_res_ncont |
| copy df_res_pterm -outputlayer df_res_pcont |
| |
| disconnect |
| |
| connect rdl pad |
| connect m5 pad |
| connect m5 m4 -by via4_c |
| connect m5 m5_res_term -by m5_res_cont |
| connect m4 m3 -by via3_c |
| connect m4 m4_res_term -by m4_res_cont |
| connect m5 cap45_m5 -by m5_cap_m45_con |
| connect m4 cap45_m4 -by m4_cap_m45_con |
| connect m4 cap34_m4 -by m4_cap_m34_con |
| connect m3 cap34_m3 -by m3_cap_m34_con |
| connect m3 m2 -by via2 |
| connect m3 m3_res_term -by m3_res_cont |
| connect m2 m1 -by via1 |
| connect m2 m2_res_term -by m2_res_cont |
| connect m1 li -by mcon |
| connect m1 m1_res_term -by m1_res_cont |
| connect li li_res_term -by li_res_cont |
| connect li ply -by licon |
| connect li nsd -by licon |
| connect li psd -by licon |
| connect li ntap -by licon |
| connect li ptap -by licon |
| connect li ptubtap -by licon |
| connect li pwres_term -by licon |
| connect li nsrc_de_12v -by licon |
| connect li ndrn_de_12v -by ntap |
| connect li psrc_de_12v -by licon |
| connect li pdrn_de_12v -by ptubtap |
| connect ply pl_res_term -by pl_res_cont |
| connect ply ngate_de_12v_pw -by ngate_de_12v_gate_conn |
| connect ply pgate_de_12v_pw -by pgate_de_12v_gate_conn |
| connect ply gate |
| connect nsd df_res_nterm -by df_res_ncont |
| connect psd df_res_pterm -by df_res_pcont |
| |
| antenna li psd -eq 0 -outputlayer bad_li_1 |
| antenna bad_li_1 nsd -eq 0 -outputlayer bad_li_2 |
| antenna bad_li_2 gate -eq 0 -outputlayer bad_li_3 |
| antenna bad_li_3 ntap -eq 0 -outputlayer bad_li_4 |
| antenna bad_li_4 ptap -eq 0 -outputlayer bad_li_5 |
| antenna bad_li_5 ptubtap -eq 0 -outputlayer bad_li_6 |
| antenna bad_li_6 pwres_term -eq 0 -outputlayer bad_li_7 |
| antenna bad_li_7 nsrc_de_12v -eq 0 -outputlayer bad_li_8 |
| antenna bad_li_8 ndrn_de_12v -eq 0 -outputlayer bad_li_9 |
| antenna bad_li_9 psrc_de_12v -eq 0 -outputlayer bad_li_10 |
| antenna bad_li_10 pdrn_de_12v -eq 0 -outputlayer bad_li_11 |
| antenna bad_li_11 ngate_de_12v_pw -eq 0 -outputlayer bad_li_12 |
| antenna bad_li_12 pgate_de_12v_pw -eq 0 -outputlayer bad_li_13 |
| antenna bad_li_13 cap45_m4 -eq 0 -outputlayer bad_li_14 |
| antenna bad_li_14 cap45_m5 -eq 0 -outputlayer bad_li_15 |
| antenna bad_li_15 cap34_m4 -eq 0 -outputlayer bad_li_16 |
| antenna bad_li_16 cap34_m3 -eq 0 -outputlayer bad_li_17 |
| antenna bad_li_17 li_res_term -eq 0 -outputlayer bad_li_18 |
| antenna bad_li_18 m1_res_term -eq 0 -outputlayer bad_li_19 |
| antenna bad_li_19 m2_res_term -eq 0 -outputlayer bad_li_20 |
| antenna bad_li_20 m3_res_term -eq 0 -outputlayer bad_li_21 |
| antenna bad_li_21 m4_res_term -eq 0 -outputlayer bad_li_22 |
| antenna bad_li_22 m5_res_term -eq 0 -outputlayer bad_li_23 |
| antenna bad_li_23 pl_res_term -eq 0 -outputlayer bad_li_24 |
| antenna bad_li_24 df_res_nterm -eq 0 -outputlayer bad_li_25 |
| antenna bad_li_25 df_res_pterm -eq 0 -outputlayer bad_li |
| antenna ply psd -eq 0 -outputlayer bad_ply_1 |
| antenna bad_ply_1 nsd -eq 0 -outputlayer bad_ply_2 |
| antenna bad_ply_2 gate -eq 0 -outputlayer bad_ply_3 |
| antenna bad_ply_3 ntap -eq 0 -outputlayer bad_ply_4 |
| antenna bad_ply_4 ptap -eq 0 -outputlayer bad_ply_5 |
| antenna bad_ply_5 ptubtap -eq 0 -outputlayer bad_ply_6 |
| antenna bad_ply_6 pwres_term -eq 0 -outputlayer bad_ply_7 |
| antenna bad_ply_7 nsrc_de_12v -eq 0 -outputlayer bad_ply_8 |
| antenna bad_ply_8 ndrn_de_12v -eq 0 -outputlayer bad_ply_9 |
| antenna bad_ply_9 psrc_de_12v -eq 0 -outputlayer bad_ply_10 |
| antenna bad_ply_10 pdrn_de_12v -eq 0 -outputlayer bad_ply_11 |
| antenna bad_ply_11 ngate_de_12v_pw -eq 0 -outputlayer bad_ply_12 |
| antenna bad_ply_12 pgate_de_12v_pw -eq 0 -outputlayer bad_ply_13 |
| antenna bad_ply_13 cap45_m4 -eq 0 -outputlayer bad_ply_14 |
| antenna bad_ply_14 cap45_m5 -eq 0 -outputlayer bad_ply_15 |
| antenna bad_ply_15 cap34_m4 -eq 0 -outputlayer bad_ply_16 |
| antenna bad_ply_16 cap34_m3 -eq 0 -outputlayer bad_ply_17 |
| antenna bad_ply_17 li_res_term -eq 0 -outputlayer bad_ply_18 |
| antenna bad_ply_18 m1_res_term -eq 0 -outputlayer bad_ply_19 |
| antenna bad_ply_19 m2_res_term -eq 0 -outputlayer bad_ply_20 |
| antenna bad_ply_20 m3_res_term -eq 0 -outputlayer bad_ply_21 |
| antenna bad_ply_21 m4_res_term -eq 0 -outputlayer bad_ply_22 |
| antenna bad_ply_22 m5_res_term -eq 0 -outputlayer bad_ply_23 |
| antenna bad_ply_23 pl_res_term -eq 0 -outputlayer bad_ply_24 |
| antenna bad_ply_24 df_res_nterm -eq 0 -outputlayer bad_ply_25 |
| antenna bad_ply_25 df_res_pterm -eq 0 -outputlayer bad_ply |
| antenna m1 psd -eq 0 -outputlayer bad_m1_1 |
| antenna bad_m1_1 nsd -eq 0 -outputlayer bad_m1_2 |
| antenna bad_m1_2 gate -eq 0 -outputlayer bad_m1_3 |
| antenna bad_m1_3 ntap -eq 0 -outputlayer bad_m1_4 |
| antenna bad_m1_4 ptap -eq 0 -outputlayer bad_m1_5 |
| antenna bad_m1_5 ptubtap -eq 0 -outputlayer bad_m1_6 |
| antenna bad_m1_6 pwres_term -eq 0 -outputlayer bad_m1_7 |
| antenna bad_m1_7 nsrc_de_12v -eq 0 -outputlayer bad_m1_8 |
| antenna bad_m1_8 ndrn_de_12v -eq 0 -outputlayer bad_m1_9 |
| antenna bad_m1_9 psrc_de_12v -eq 0 -outputlayer bad_m1_10 |
| antenna bad_m1_10 pdrn_de_12v -eq 0 -outputlayer bad_m1_11 |
| antenna bad_m1_11 ngate_de_12v_pw -eq 0 -outputlayer bad_m1_12 |
| antenna bad_m1_12 pgate_de_12v_pw -eq 0 -outputlayer bad_m1_13 |
| antenna bad_m1_13 cap45_m4 -eq 0 -outputlayer bad_m1_14 |
| antenna bad_m1_14 cap45_m5 -eq 0 -outputlayer bad_m1_15 |
| antenna bad_m1_15 cap34_m4 -eq 0 -outputlayer bad_m1_16 |
| antenna bad_m1_16 cap34_m3 -eq 0 -outputlayer bad_m1_17 |
| antenna bad_m1_17 li_res_term -eq 0 -outputlayer bad_m1_18 |
| antenna bad_m1_18 m1_res_term -eq 0 -outputlayer bad_m1_19 |
| antenna bad_m1_19 m2_res_term -eq 0 -outputlayer bad_m1_20 |
| antenna bad_m1_20 m3_res_term -eq 0 -outputlayer bad_m1_21 |
| antenna bad_m1_21 m4_res_term -eq 0 -outputlayer bad_m1_22 |
| antenna bad_m1_22 m5_res_term -eq 0 -outputlayer bad_m1_23 |
| antenna bad_m1_23 pl_res_term -eq 0 -outputlayer bad_m1_24 |
| antenna bad_m1_24 df_res_nterm -eq 0 -outputlayer bad_m1_25 |
| antenna bad_m1_25 df_res_pterm -eq 0 -outputlayer bad_m1 |
| antenna m2 psd -eq 0 -outputlayer bad_m2_1 |
| antenna bad_m2_1 nsd -eq 0 -outputlayer bad_m2_2 |
| antenna bad_m2_2 gate -eq 0 -outputlayer bad_m2_3 |
| antenna bad_m2_3 ntap -eq 0 -outputlayer bad_m2_4 |
| antenna bad_m2_4 ptap -eq 0 -outputlayer bad_m2_5 |
| antenna bad_m2_5 ptubtap -eq 0 -outputlayer bad_m2_6 |
| antenna bad_m2_6 pwres_term -eq 0 -outputlayer bad_m2_7 |
| antenna bad_m2_7 nsrc_de_12v -eq 0 -outputlayer bad_m2_8 |
| antenna bad_m2_8 ndrn_de_12v -eq 0 -outputlayer bad_m2_9 |
| antenna bad_m2_9 psrc_de_12v -eq 0 -outputlayer bad_m2_10 |
| antenna bad_m2_10 pdrn_de_12v -eq 0 -outputlayer bad_m2_11 |
| antenna bad_m2_11 ngate_de_12v_pw -eq 0 -outputlayer bad_m2_12 |
| antenna bad_m2_12 pgate_de_12v_pw -eq 0 -outputlayer bad_m2_13 |
| antenna bad_m2_13 cap45_m4 -eq 0 -outputlayer bad_m2_14 |
| antenna bad_m2_14 cap45_m5 -eq 0 -outputlayer bad_m2_15 |
| antenna bad_m2_15 cap34_m4 -eq 0 -outputlayer bad_m2_16 |
| antenna bad_m2_16 cap34_m3 -eq 0 -outputlayer bad_m2_17 |
| antenna bad_m2_17 li_res_term -eq 0 -outputlayer bad_m2_18 |
| antenna bad_m2_18 m1_res_term -eq 0 -outputlayer bad_m2_19 |
| antenna bad_m2_19 m2_res_term -eq 0 -outputlayer bad_m2_20 |
| antenna bad_m2_20 m3_res_term -eq 0 -outputlayer bad_m2_21 |
| antenna bad_m2_21 m4_res_term -eq 0 -outputlayer bad_m2_22 |
| antenna bad_m2_22 m5_res_term -eq 0 -outputlayer bad_m2_23 |
| antenna bad_m2_23 pl_res_term -eq 0 -outputlayer bad_m2_24 |
| antenna bad_m2_24 df_res_nterm -eq 0 -outputlayer bad_m2_25 |
| antenna bad_m2_25 df_res_pterm -eq 0 -outputlayer bad_m2 |
| antenna m3 psd -eq 0 -outputlayer bad_m3_1 |
| antenna bad_m3_1 nsd -eq 0 -outputlayer bad_m3_2 |
| antenna bad_m3_2 gate -eq 0 -outputlayer bad_m3_3 |
| antenna bad_m3_3 ntap -eq 0 -outputlayer bad_m3_4 |
| antenna bad_m3_4 ptap -eq 0 -outputlayer bad_m3_5 |
| antenna bad_m3_5 ptubtap -eq 0 -outputlayer bad_m3_6 |
| antenna bad_m3_6 pwres_term -eq 0 -outputlayer bad_m3_7 |
| antenna bad_m3_7 nsrc_de_12v -eq 0 -outputlayer bad_m3_8 |
| antenna bad_m3_8 ndrn_de_12v -eq 0 -outputlayer bad_m3_9 |
| antenna bad_m3_9 psrc_de_12v -eq 0 -outputlayer bad_m3_10 |
| antenna bad_m3_10 pdrn_de_12v -eq 0 -outputlayer bad_m3_11 |
| antenna bad_m3_11 ngate_de_12v_pw -eq 0 -outputlayer bad_m3_12 |
| antenna bad_m3_12 pgate_de_12v_pw -eq 0 -outputlayer bad_m3_13 |
| antenna bad_m3_13 cap45_m4 -eq 0 -outputlayer bad_m3_14 |
| antenna bad_m3_14 cap45_m5 -eq 0 -outputlayer bad_m3_15 |
| antenna bad_m3_15 cap34_m4 -eq 0 -outputlayer bad_m3_16 |
| antenna bad_m3_16 cap34_m3 -eq 0 -outputlayer bad_m3_17 |
| antenna bad_m3_17 li_res_term -eq 0 -outputlayer bad_m3_18 |
| antenna bad_m3_18 m1_res_term -eq 0 -outputlayer bad_m3_19 |
| antenna bad_m3_19 m2_res_term -eq 0 -outputlayer bad_m3_20 |
| antenna bad_m3_20 m3_res_term -eq 0 -outputlayer bad_m3_21 |
| antenna bad_m3_21 m4_res_term -eq 0 -outputlayer bad_m3_22 |
| antenna bad_m3_22 m5_res_term -eq 0 -outputlayer bad_m3_23 |
| antenna bad_m3_23 pl_res_term -eq 0 -outputlayer bad_m3_24 |
| antenna bad_m3_24 df_res_nterm -eq 0 -outputlayer bad_m3_25 |
| antenna bad_m3_25 df_res_pterm -eq 0 -outputlayer bad_m3 |
| antenna m4 psd -eq 0 -outputlayer bad_m4_1 |
| antenna bad_m4_1 nsd -eq 0 -outputlayer bad_m4_2 |
| antenna bad_m4_2 gate -eq 0 -outputlayer bad_m4_3 |
| antenna bad_m4_3 ntap -eq 0 -outputlayer bad_m4_4 |
| antenna bad_m4_4 ptap -eq 0 -outputlayer bad_m4_5 |
| antenna bad_m4_5 ptubtap -eq 0 -outputlayer bad_m4_6 |
| antenna bad_m4_6 pwres_term -eq 0 -outputlayer bad_m4_7 |
| antenna bad_m4_7 nsrc_de_12v -eq 0 -outputlayer bad_m4_8 |
| antenna bad_m4_8 ndrn_de_12v -eq 0 -outputlayer bad_m4_9 |
| antenna bad_m4_9 psrc_de_12v -eq 0 -outputlayer bad_m4_10 |
| antenna bad_m4_10 pdrn_de_12v -eq 0 -outputlayer bad_m4_11 |
| antenna bad_m4_11 ngate_de_12v_pw -eq 0 -outputlayer bad_m4_12 |
| antenna bad_m4_12 pgate_de_12v_pw -eq 0 -outputlayer bad_m4_13 |
| antenna bad_m4_13 cap45_m4 -eq 0 -outputlayer bad_m4_14 |
| antenna bad_m4_14 cap45_m5 -eq 0 -outputlayer bad_m4_15 |
| antenna bad_m4_15 cap34_m4 -eq 0 -outputlayer bad_m4_16 |
| antenna bad_m4_16 cap34_m3 -eq 0 -outputlayer bad_m4_17 |
| antenna bad_m4_17 li_res_term -eq 0 -outputlayer bad_m4_18 |
| antenna bad_m4_18 m1_res_term -eq 0 -outputlayer bad_m4_19 |
| antenna bad_m4_19 m2_res_term -eq 0 -outputlayer bad_m4_20 |
| antenna bad_m4_20 m3_res_term -eq 0 -outputlayer bad_m4_21 |
| antenna bad_m4_21 m4_res_term -eq 0 -outputlayer bad_m4_22 |
| antenna bad_m4_22 m5_res_term -eq 0 -outputlayer bad_m4_23 |
| antenna bad_m4_23 pl_res_term -eq 0 -outputlayer bad_m4_24 |
| antenna bad_m4_24 df_res_nterm -eq 0 -outputlayer bad_m4_25 |
| antenna bad_m4_25 df_res_pterm -eq 0 -outputlayer bad_m4 |
| antenna m5 psd -eq 0 -outputlayer bad_m5_1 |
| antenna bad_m5_1 nsd -eq 0 -outputlayer bad_m5_2 |
| antenna bad_m5_2 gate -eq 0 -outputlayer bad_m5_3 |
| antenna bad_m5_3 ntap -eq 0 -outputlayer bad_m5_4 |
| antenna bad_m5_4 ptap -eq 0 -outputlayer bad_m5_5 |
| antenna bad_m5_5 ptubtap -eq 0 -outputlayer bad_m5_6 |
| antenna bad_m5_6 pwres_term -eq 0 -outputlayer bad_m5_7 |
| antenna bad_m5_7 nsrc_de_12v -eq 0 -outputlayer bad_m5_8 |
| antenna bad_m5_8 ndrn_de_12v -eq 0 -outputlayer bad_m5_9 |
| antenna bad_m5_9 psrc_de_12v -eq 0 -outputlayer bad_m5_10 |
| antenna bad_m5_10 pdrn_de_12v -eq 0 -outputlayer bad_m5_11 |
| antenna bad_m5_11 ngate_de_12v_pw -eq 0 -outputlayer bad_m5_12 |
| antenna bad_m5_12 pgate_de_12v_pw -eq 0 -outputlayer bad_m5_13 |
| antenna bad_m5_13 cap45_m4 -eq 0 -outputlayer bad_m5_14 |
| antenna bad_m5_14 cap45_m5 -eq 0 -outputlayer bad_m5_15 |
| antenna bad_m5_15 cap34_m4 -eq 0 -outputlayer bad_m5_16 |
| antenna bad_m5_16 cap34_m3 -eq 0 -outputlayer bad_m5_17 |
| antenna bad_m5_17 li_res_term -eq 0 -outputlayer bad_m5_18 |
| antenna bad_m5_18 m1_res_term -eq 0 -outputlayer bad_m5_19 |
| antenna bad_m5_19 m2_res_term -eq 0 -outputlayer bad_m5_20 |
| antenna bad_m5_20 m3_res_term -eq 0 -outputlayer bad_m5_21 |
| antenna bad_m5_21 m4_res_term -eq 0 -outputlayer bad_m5_22 |
| antenna bad_m5_22 m5_res_term -eq 0 -outputlayer bad_m5_23 |
| antenna bad_m5_23 pl_res_term -eq 0 -outputlayer bad_m5_24 |
| antenna bad_m5_24 df_res_nterm -eq 0 -outputlayer bad_m5_25 |
| antenna bad_m5_25 df_res_pterm -eq 0 -outputlayer bad_m5 |
| antenna rdl psd -eq 0 -outputlayer bad_rdl_1 |
| antenna bad_rdl_1 nsd -eq 0 -outputlayer bad_rdl_2 |
| antenna bad_rdl_2 gate -eq 0 -outputlayer bad_rdl_3 |
| antenna bad_rdl_3 ntap -eq 0 -outputlayer bad_rdl_4 |
| antenna bad_rdl_4 ptap -eq 0 -outputlayer bad_rdl_5 |
| antenna bad_rdl_5 ptubtap -eq 0 -outputlayer bad_rdl_6 |
| antenna bad_rdl_6 pwres_term -eq 0 -outputlayer bad_rdl_7 |
| antenna bad_rdl_7 nsrc_de_12v -eq 0 -outputlayer bad_rdl_8 |
| antenna bad_rdl_8 ndrn_de_12v -eq 0 -outputlayer bad_rdl_9 |
| antenna bad_rdl_9 psrc_de_12v -eq 0 -outputlayer bad_rdl_10 |
| antenna bad_rdl_10 pdrn_de_12v -eq 0 -outputlayer bad_rdl_11 |
| antenna bad_rdl_11 ngate_de_12v_pw -eq 0 -outputlayer bad_rdl_12 |
| antenna bad_rdl_12 pgate_de_12v_pw -eq 0 -outputlayer bad_rdl_13 |
| antenna bad_rdl_13 cap45_m4 -eq 0 -outputlayer bad_rdl_14 |
| antenna bad_rdl_14 cap45_m5 -eq 0 -outputlayer bad_rdl_15 |
| antenna bad_rdl_15 cap34_m4 -eq 0 -outputlayer bad_rdl_16 |
| antenna bad_rdl_16 cap34_m3 -eq 0 -outputlayer bad_rdl_17 |
| antenna bad_rdl_17 li_res_term -eq 0 -outputlayer bad_rdl_18 |
| antenna bad_rdl_18 m1_res_term -eq 0 -outputlayer bad_rdl_19 |
| antenna bad_rdl_19 m2_res_term -eq 0 -outputlayer bad_rdl_20 |
| antenna bad_rdl_20 m3_res_term -eq 0 -outputlayer bad_rdl_21 |
| antenna bad_rdl_21 m4_res_term -eq 0 -outputlayer bad_rdl_22 |
| antenna bad_rdl_22 m5_res_term -eq 0 -outputlayer bad_rdl_23 |
| antenna bad_rdl_23 pl_res_term -eq 0 -outputlayer bad_rdl_24 |
| antenna bad_rdl_24 df_res_nterm -eq 0 -outputlayer bad_rdl_25 |
| antenna bad_rdl_25 df_res_pterm -eq 0 -outputlayer bad_rdl |
| antenna li psd -gt 0 -outputlayer good_li_1 |
| antenna good_li_1 nsd -gt 0 -outputlayer good_li_2 |
| antenna good_li_2 gate -gt 0 -outputlayer good_li_3 |
| antenna good_li_3 ntap -gt 0 -outputlayer good_li_4 |
| antenna good_li_4 ptap -gt 0 -outputlayer good_li_5 |
| antenna good_li_5 ptubtap -gt 0 -outputlayer good_li_6 |
| antenna good_li_6 pwres_term -gt 0 -outputlayer good_li_7 |
| antenna good_li_7 nsrc_de_12v -gt 0 -outputlayer good_li_8 |
| antenna good_li_8 ndrn_de_12v -gt 0 -outputlayer good_li_9 |
| antenna good_li_9 psrc_de_12v -gt 0 -outputlayer good_li_10 |
| antenna good_li_10 pdrn_de_12v -gt 0 -outputlayer good_li_11 |
| antenna good_li_11 ngate_de_12v_pw -gt 0 -outputlayer good_li_12 |
| antenna good_li_12 pgate_de_12v_pw -gt 0 -outputlayer good_li_13 |
| antenna good_li_13 cap45_m4 -gt 0 -outputlayer good_li_14 |
| antenna good_li_14 cap45_m5 -gt 0 -outputlayer good_li_15 |
| antenna good_li_15 cap34_m4 -gt 0 -outputlayer good_li_16 |
| antenna good_li_16 cap34_m3 -gt 0 -outputlayer good_li_17 |
| antenna good_li_17 li_res_term -gt 0 -outputlayer good_li_18 |
| antenna good_li_18 m1_res_term -gt 0 -outputlayer good_li_19 |
| antenna good_li_19 m2_res_term -gt 0 -outputlayer good_li_20 |
| antenna good_li_20 m3_res_term -gt 0 -outputlayer good_li_21 |
| antenna good_li_21 m4_res_term -gt 0 -outputlayer good_li_22 |
| antenna good_li_22 m5_res_term -gt 0 -outputlayer good_li_23 |
| antenna good_li_23 pl_res_term -gt 0 -outputlayer good_li_24 |
| antenna good_li_24 df_res_nterm -gt 0 -outputlayer good_li_25 |
| antenna good_li_25 df_res_pterm -gt 0 -outputlayer good_li |
| antenna ply psd -gt 0 -outputlayer good_ply_1 |
| antenna good_ply_1 nsd -gt 0 -outputlayer good_ply_2 |
| antenna good_ply_2 gate -gt 0 -outputlayer good_ply_3 |
| antenna good_ply_3 ntap -gt 0 -outputlayer good_ply_4 |
| antenna good_ply_4 ptap -gt 0 -outputlayer good_ply_5 |
| antenna good_ply_5 ptubtap -gt 0 -outputlayer good_ply_6 |
| antenna good_ply_6 pwres_term -gt 0 -outputlayer good_ply_7 |
| antenna good_ply_7 nsrc_de_12v -gt 0 -outputlayer good_ply_8 |
| antenna good_ply_8 ndrn_de_12v -gt 0 -outputlayer good_ply_9 |
| antenna good_ply_9 psrc_de_12v -gt 0 -outputlayer good_ply_10 |
| antenna good_ply_10 pdrn_de_12v -gt 0 -outputlayer good_ply_11 |
| antenna good_ply_11 ngate_de_12v_pw -gt 0 -outputlayer good_ply_12 |
| antenna good_ply_12 pgate_de_12v_pw -gt 0 -outputlayer good_ply_13 |
| antenna good_ply_13 cap45_m4 -gt 0 -outputlayer good_ply_14 |
| antenna good_ply_14 cap45_m5 -gt 0 -outputlayer good_ply_15 |
| antenna good_ply_15 cap34_m4 -gt 0 -outputlayer good_ply_16 |
| antenna good_ply_16 cap34_m3 -gt 0 -outputlayer good_ply_17 |
| antenna good_ply_17 li_res_term -gt 0 -outputlayer good_ply_18 |
| antenna good_ply_18 m1_res_term -gt 0 -outputlayer good_ply_19 |
| antenna good_ply_19 m2_res_term -gt 0 -outputlayer good_ply_20 |
| antenna good_ply_20 m3_res_term -gt 0 -outputlayer good_ply_21 |
| antenna good_ply_21 m4_res_term -gt 0 -outputlayer good_ply_22 |
| antenna good_ply_22 m5_res_term -gt 0 -outputlayer good_ply_23 |
| antenna good_ply_23 pl_res_term -gt 0 -outputlayer good_ply_24 |
| antenna good_ply_24 df_res_nterm -gt 0 -outputlayer good_ply_25 |
| antenna good_ply_25 df_res_pterm -gt 0 -outputlayer good_ply |
| antenna m1 psd -gt 0 -outputlayer good_m1_1 |
| antenna good_m1_1 nsd -gt 0 -outputlayer good_m1_2 |
| antenna good_m1_2 gate -gt 0 -outputlayer good_m1_3 |
| antenna good_m1_3 ntap -gt 0 -outputlayer good_m1_4 |
| antenna good_m1_4 ptap -gt 0 -outputlayer good_m1_5 |
| antenna good_m1_5 ptubtap -gt 0 -outputlayer good_m1_6 |
| antenna good_m1_6 pwres_term -gt 0 -outputlayer good_m1_7 |
| antenna good_m1_7 nsrc_de_12v -gt 0 -outputlayer good_m1_8 |
| antenna good_m1_8 ndrn_de_12v -gt 0 -outputlayer good_m1_9 |
| antenna good_m1_9 psrc_de_12v -gt 0 -outputlayer good_m1_10 |
| antenna good_m1_10 pdrn_de_12v -gt 0 -outputlayer good_m1_11 |
| antenna good_m1_11 ngate_de_12v_pw -gt 0 -outputlayer good_m1_12 |
| antenna good_m1_12 pgate_de_12v_pw -gt 0 -outputlayer good_m1_13 |
| antenna good_m1_13 cap45_m4 -gt 0 -outputlayer good_m1_14 |
| antenna good_m1_14 cap45_m5 -gt 0 -outputlayer good_m1_15 |
| antenna good_m1_15 cap34_m4 -gt 0 -outputlayer good_m1_16 |
| antenna good_m1_16 cap34_m3 -gt 0 -outputlayer good_m1_17 |
| antenna good_m1_17 li_res_term -gt 0 -outputlayer good_m1_18 |
| antenna good_m1_18 m1_res_term -gt 0 -outputlayer good_m1_19 |
| antenna good_m1_19 m2_res_term -gt 0 -outputlayer good_m1_20 |
| antenna good_m1_20 m3_res_term -gt 0 -outputlayer good_m1_21 |
| antenna good_m1_21 m4_res_term -gt 0 -outputlayer good_m1_22 |
| antenna good_m1_22 m5_res_term -gt 0 -outputlayer good_m1_23 |
| antenna good_m1_23 pl_res_term -gt 0 -outputlayer good_m1_24 |
| antenna good_m1_24 df_res_nterm -gt 0 -outputlayer good_m1_25 |
| antenna good_m1_25 df_res_pterm -gt 0 -outputlayer good_m1 |
| antenna m2 psd -gt 0 -outputlayer good_m2_1 |
| antenna good_m2_1 nsd -gt 0 -outputlayer good_m2_2 |
| antenna good_m2_2 gate -gt 0 -outputlayer good_m2_3 |
| antenna good_m2_3 ntap -gt 0 -outputlayer good_m2_4 |
| antenna good_m2_4 ptap -gt 0 -outputlayer good_m2_5 |
| antenna good_m2_5 ptubtap -gt 0 -outputlayer good_m2_6 |
| antenna good_m2_6 pwres_term -gt 0 -outputlayer good_m2_7 |
| antenna good_m2_7 nsrc_de_12v -gt 0 -outputlayer good_m2_8 |
| antenna good_m2_8 ndrn_de_12v -gt 0 -outputlayer good_m2_9 |
| antenna good_m2_9 psrc_de_12v -gt 0 -outputlayer good_m2_10 |
| antenna good_m2_10 pdrn_de_12v -gt 0 -outputlayer good_m2_11 |
| antenna good_m2_11 ngate_de_12v_pw -gt 0 -outputlayer good_m2_12 |
| antenna good_m2_12 pgate_de_12v_pw -gt 0 -outputlayer good_m2_13 |
| antenna good_m2_13 cap45_m4 -gt 0 -outputlayer good_m2_14 |
| antenna good_m2_14 cap45_m5 -gt 0 -outputlayer good_m2_15 |
| antenna good_m2_15 cap34_m4 -gt 0 -outputlayer good_m2_16 |
| antenna good_m2_16 cap34_m3 -gt 0 -outputlayer good_m2_17 |
| antenna good_m2_17 li_res_term -gt 0 -outputlayer good_m2_18 |
| antenna good_m2_18 m1_res_term -gt 0 -outputlayer good_m2_19 |
| antenna good_m2_19 m2_res_term -gt 0 -outputlayer good_m2_20 |
| antenna good_m2_20 m3_res_term -gt 0 -outputlayer good_m2_21 |
| antenna good_m2_21 m4_res_term -gt 0 -outputlayer good_m2_22 |
| antenna good_m2_22 m5_res_term -gt 0 -outputlayer good_m2_23 |
| antenna good_m2_23 pl_res_term -gt 0 -outputlayer good_m2_24 |
| antenna good_m2_24 df_res_nterm -gt 0 -outputlayer good_m2_25 |
| antenna good_m2_25 df_res_pterm -gt 0 -outputlayer good_m2 |
| antenna m3 psd -gt 0 -outputlayer good_m3_1 |
| antenna good_m3_1 nsd -gt 0 -outputlayer good_m3_2 |
| antenna good_m3_2 gate -gt 0 -outputlayer good_m3_3 |
| antenna good_m3_3 ntap -gt 0 -outputlayer good_m3_4 |
| antenna good_m3_4 ptap -gt 0 -outputlayer good_m3_5 |
| antenna good_m3_5 ptubtap -gt 0 -outputlayer good_m3_6 |
| antenna good_m3_6 pwres_term -gt 0 -outputlayer good_m3_7 |
| antenna good_m3_7 nsrc_de_12v -gt 0 -outputlayer good_m3_8 |
| antenna good_m3_8 ndrn_de_12v -gt 0 -outputlayer good_m3_9 |
| antenna good_m3_9 psrc_de_12v -gt 0 -outputlayer good_m3_10 |
| antenna good_m3_10 pdrn_de_12v -gt 0 -outputlayer good_m3_11 |
| antenna good_m3_11 ngate_de_12v_pw -gt 0 -outputlayer good_m3_12 |
| antenna good_m3_12 pgate_de_12v_pw -gt 0 -outputlayer good_m3_13 |
| antenna good_m3_13 cap45_m4 -gt 0 -outputlayer good_m3_14 |
| antenna good_m3_14 cap45_m5 -gt 0 -outputlayer good_m3_15 |
| antenna good_m3_15 cap34_m4 -gt 0 -outputlayer good_m3_16 |
| antenna good_m3_16 cap34_m3 -gt 0 -outputlayer good_m3_17 |
| antenna good_m3_17 li_res_term -gt 0 -outputlayer good_m3_18 |
| antenna good_m3_18 m1_res_term -gt 0 -outputlayer good_m3_19 |
| antenna good_m3_19 m2_res_term -gt 0 -outputlayer good_m3_20 |
| antenna good_m3_20 m3_res_term -gt 0 -outputlayer good_m3_21 |
| antenna good_m3_21 m4_res_term -gt 0 -outputlayer good_m3_22 |
| antenna good_m3_22 m5_res_term -gt 0 -outputlayer good_m3_23 |
| antenna good_m3_23 pl_res_term -gt 0 -outputlayer good_m3_24 |
| antenna good_m3_24 df_res_nterm -gt 0 -outputlayer good_m3_25 |
| antenna good_m3_25 df_res_pterm -gt 0 -outputlayer good_m3 |
| antenna m4 psd -gt 0 -outputlayer good_m4_1 |
| antenna good_m4_1 nsd -gt 0 -outputlayer good_m4_2 |
| antenna good_m4_2 gate -gt 0 -outputlayer good_m4_3 |
| antenna good_m4_3 ntap -gt 0 -outputlayer good_m4_4 |
| antenna good_m4_4 ptap -gt 0 -outputlayer good_m4_5 |
| antenna good_m4_5 ptubtap -gt 0 -outputlayer good_m4_6 |
| antenna good_m4_6 pwres_term -gt 0 -outputlayer good_m4_7 |
| antenna good_m4_7 nsrc_de_12v -gt 0 -outputlayer good_m4_8 |
| antenna good_m4_8 ndrn_de_12v -gt 0 -outputlayer good_m4_9 |
| antenna good_m4_9 psrc_de_12v -gt 0 -outputlayer good_m4_10 |
| antenna good_m4_10 pdrn_de_12v -gt 0 -outputlayer good_m4_11 |
| antenna good_m4_11 ngate_de_12v_pw -gt 0 -outputlayer good_m4_12 |
| antenna good_m4_12 pgate_de_12v_pw -gt 0 -outputlayer good_m4_13 |
| antenna good_m4_13 cap45_m4 -gt 0 -outputlayer good_m4_14 |
| antenna good_m4_14 cap45_m5 -gt 0 -outputlayer good_m4_15 |
| antenna good_m4_15 cap34_m4 -gt 0 -outputlayer good_m4_16 |
| antenna good_m4_16 cap34_m3 -gt 0 -outputlayer good_m4_17 |
| antenna good_m4_17 li_res_term -gt 0 -outputlayer good_m4_18 |
| antenna good_m4_18 m1_res_term -gt 0 -outputlayer good_m4_19 |
| antenna good_m4_19 m2_res_term -gt 0 -outputlayer good_m4_20 |
| antenna good_m4_20 m3_res_term -gt 0 -outputlayer good_m4_21 |
| antenna good_m4_21 m4_res_term -gt 0 -outputlayer good_m4_22 |
| antenna good_m4_22 m5_res_term -gt 0 -outputlayer good_m4_23 |
| antenna good_m4_23 pl_res_term -gt 0 -outputlayer good_m4_24 |
| antenna good_m4_24 df_res_nterm -gt 0 -outputlayer good_m4_25 |
| antenna good_m4_25 df_res_pterm -gt 0 -outputlayer good_m4 |
| antenna m5 psd -gt 0 -outputlayer good_m5_1 |
| antenna good_m5_1 nsd -gt 0 -outputlayer good_m5_2 |
| antenna good_m5_2 gate -gt 0 -outputlayer good_m5_3 |
| antenna good_m5_3 ntap -gt 0 -outputlayer good_m5_4 |
| antenna good_m5_4 ptap -gt 0 -outputlayer good_m5_5 |
| antenna good_m5_5 ptubtap -gt 0 -outputlayer good_m5_6 |
| antenna good_m5_6 pwres_term -gt 0 -outputlayer good_m5_7 |
| antenna good_m5_7 nsrc_de_12v -gt 0 -outputlayer good_m5_8 |
| antenna good_m5_8 ndrn_de_12v -gt 0 -outputlayer good_m5_9 |
| antenna good_m5_9 psrc_de_12v -gt 0 -outputlayer good_m5_10 |
| antenna good_m5_10 pdrn_de_12v -gt 0 -outputlayer good_m5_11 |
| antenna good_m5_11 ngate_de_12v_pw -gt 0 -outputlayer good_m5_12 |
| antenna good_m5_12 pgate_de_12v_pw -gt 0 -outputlayer good_m5_13 |
| antenna good_m5_13 cap45_m4 -gt 0 -outputlayer good_m5_14 |
| antenna good_m5_14 cap45_m5 -gt 0 -outputlayer good_m5_15 |
| antenna good_m5_15 cap34_m4 -gt 0 -outputlayer good_m5_16 |
| antenna good_m5_16 cap34_m3 -gt 0 -outputlayer good_m5_17 |
| antenna good_m5_17 li_res_term -gt 0 -outputlayer good_m5_18 |
| antenna good_m5_18 m1_res_term -gt 0 -outputlayer good_m5_19 |
| antenna good_m5_19 m2_res_term -gt 0 -outputlayer good_m5_20 |
| antenna good_m5_20 m3_res_term -gt 0 -outputlayer good_m5_21 |
| antenna good_m5_21 m4_res_term -gt 0 -outputlayer good_m5_22 |
| antenna good_m5_22 m5_res_term -gt 0 -outputlayer good_m5_23 |
| antenna good_m5_23 pl_res_term -gt 0 -outputlayer good_m5_24 |
| antenna good_m5_24 df_res_nterm -gt 0 -outputlayer good_m5_25 |
| antenna good_m5_25 df_res_pterm -gt 0 -outputlayer good_m5 |
| antenna rdl psd -gt 0 -outputlayer good_rdl_1 |
| antenna good_rdl_1 nsd -gt 0 -outputlayer good_rdl_2 |
| antenna good_rdl_2 gate -gt 0 -outputlayer good_rdl_3 |
| antenna good_rdl_3 ntap -gt 0 -outputlayer good_rdl_4 |
| antenna good_rdl_4 ptap -gt 0 -outputlayer good_rdl_5 |
| antenna good_rdl_5 ptubtap -gt 0 -outputlayer good_rdl_6 |
| antenna good_rdl_6 pwres_term -gt 0 -outputlayer good_rdl_7 |
| antenna good_rdl_7 nsrc_de_12v -gt 0 -outputlayer good_rdl_8 |
| antenna good_rdl_8 ndrn_de_12v -gt 0 -outputlayer good_rdl_9 |
| antenna good_rdl_9 psrc_de_12v -gt 0 -outputlayer good_rdl_10 |
| antenna good_rdl_10 pdrn_de_12v -gt 0 -outputlayer good_rdl_11 |
| antenna good_rdl_11 ngate_de_12v_pw -gt 0 -outputlayer good_rdl_12 |
| antenna good_rdl_12 pgate_de_12v_pw -gt 0 -outputlayer good_rdl_13 |
| antenna good_rdl_13 cap45_m4 -gt 0 -outputlayer good_rdl_14 |
| antenna good_rdl_14 cap45_m5 -gt 0 -outputlayer good_rdl_15 |
| antenna good_rdl_15 cap34_m4 -gt 0 -outputlayer good_rdl_16 |
| antenna good_rdl_16 cap34_m3 -gt 0 -outputlayer good_rdl_17 |
| antenna good_rdl_17 li_res_term -gt 0 -outputlayer good_rdl_18 |
| antenna good_rdl_18 m1_res_term -gt 0 -outputlayer good_rdl_19 |
| antenna good_rdl_19 m2_res_term -gt 0 -outputlayer good_rdl_20 |
| antenna good_rdl_20 m3_res_term -gt 0 -outputlayer good_rdl_21 |
| antenna good_rdl_21 m4_res_term -gt 0 -outputlayer good_rdl_22 |
| antenna good_rdl_22 m5_res_term -gt 0 -outputlayer good_rdl_23 |
| antenna good_rdl_23 pl_res_term -gt 0 -outputlayer good_rdl_24 |
| antenna good_rdl_24 df_res_nterm -gt 0 -outputlayer good_rdl_25 |
| antenna good_rdl_25 df_res_pterm -gt 0 -outputlayer good_rdl |
| or good_ply good_li good_m1 good_m2 good_m3 good_m4 good_m5 good_rdl -outputlayer net_not_float |
| inside_cell li_ii "text_pcell*" -outputlayer exempt_float_li_1 |
| select -interact li_ii ( or critside ccorner ) -outputlayer exempt_float_li_2 |
| or exempt_float_li_1 exempt_float_li_2 -outputlayer exempt_float_li |
| rule "floating.net.li.R" { |
| caption "floating.net.li.R: Floating local interconnect nets - nets which do not connect to a defined device" |
| copy ( not ( not bad_li li_fill ) exempt_float_li ) |
| } |
| inside_cell polyii "text_pcell*" -outputlayer exempt_float_ply_1 |
| select -interact polyii ( or critside ccorner ) -outputlayer exempt_float_ply_2 |
| or exempt_float_ply_1 exempt_float_ply_2 -outputlayer exempt_float_ply |
| rule "floating.net.poly.R" { |
| caption "floating.net.poly.R: Floating poly nets - nets which do not connect to a defined device" |
| copy ( not ( not bad_ply poly_fill ) exempt_float_ply ) |
| } |
| inside_cell met1ii "text_pcell*" -outputlayer exempt_float_m1_1 |
| select -interact met1ii ( or critside ccorner ) -outputlayer exempt_float_m1_2 |
| or exempt_float_m1_1 exempt_float_m1_2 -outputlayer exempt_float_m1 |
| rule "floating.net.met1.R" { |
| caption "floating.net.met1.R: Floating met1 nets - nets which do not connect to a defined device" |
| copy ( not ( not bad_m1 m1_fill ) exempt_float_m1 ) |
| } |
| inside_cell met2ii "text_pcell*" -outputlayer exempt_float_m2_1 |
| select -interact met2ii ( or critside ccorner ) -outputlayer exempt_float_m2_2 |
| or exempt_float_m2_1 exempt_float_m2_2 -outputlayer exempt_float_m2 |
| rule "floating.net.met2.R" { |
| caption "floating.net.met2.R: Floating met2 nets - nets which do not connect to a defined device" |
| copy ( not ( not bad_m2 m2_fill ) exempt_float_m2 ) |
| } |
| inside_cell met3ii "text_pcell*" -outputlayer exempt_float_m3_1 |
| select -interact met3ii ( or critside ccorner ) -outputlayer exempt_float_m3_2 |
| or exempt_float_m3_1 exempt_float_m3_2 -outputlayer exempt_float_m3 |
| rule "floating.net.met3.R" { |
| caption "floating.net.met3.R: Floating met3 nets - nets which do not connect to a defined device" |
| copy ( not ( not bad_m3 m3_fill ) exempt_float_m3 ) |
| } |
| inside_cell met4ii "text_pcell*" -outputlayer exempt_float_m4_1 |
| select -interact met4ii ( or critside ccorner ) -outputlayer exempt_float_m4_2 |
| or exempt_float_m4_1 exempt_float_m4_2 -outputlayer exempt_float_m4 |
| rule "floating.net.met4.R" { |
| caption "floating.net.met4.R: Floating met4 nets - nets which do not connect to a defined device" |
| copy ( not ( not bad_m4 m4_fill ) exempt_float_m4 ) |
| } |
| inside_cell met5ii "text_pcell*" -outputlayer exempt_float_m5 |
| rule "floating.net.met5.R" { |
| caption "floating.net.met5.R: Floating met5 nets - nets which do not connect to a defined device" |
| copy ( not ( not bad_m5 m5_fill ) exempt_float_m5 ) |
| } |
| or gate nsd psd ptap ntap m1res m2res m3res m4res m5res lires npn pnp diodeID capm cap2m pad -outputlayer connect_nets |
| rule "floating.net.ptap.R" { |
| caption "floating.net.ptap.R: possible floating p+ tap - p+ tap not connected to pad" |
| antenna ptap pad -eq 0 |
| } |
| rule "floating.net.ntap.R" { |
| caption "floating.net.ntap.R: possible floating n+ tap - n+ tap not connected to pad" |
| antenna ntap pad -eq 0 |
| } |
| rule "floating.net.pwell.R" { |
| caption "floating.net.pwell.R: substrate not conected by ptap" |
| select -enclose -not ( select -interact -not pwell ( holes pwbm -inner ) ) ptap |
| } |
| rule "floating.net.ptub.R" { |
| caption "floating.net.ptub.R: isolated substrate not connected by ptap" |
| select -enclose -not ptub ptap |
| } |
| rule "floating.net.localsub.R" { |
| caption "floating.net.localsub.R: local substrate (areaid:substrateCut) not connected by ptap" |
| select -enclose -not localSub ptap |
| } |
| |
| #ENDIF |
| |
| |
| |
| // Begin illegal device checks |
| |
| #IFNDEF SKIP_ILLEGAL_DEVICE_CHECKS |
| |
| // 4/14/21 SWT changed to permit active under pad: |
| copy 7000 -outputlayer skip_pad |
| copy 7001 -outputlayer skip_res |
| copy 7002 -outputlayer skip_dnw |
| |
| // NMOS: |
| |
| |
| not diffi ( or pnp npn ENID ) -outputlayer mos_diff |
| not ( and mos_diff polyi ) nwell -outputlayer nmos_gate |
| not ( select -interact diffi nmos_gate ) nmos_gate -outputlayer nmos_sd |
| select -touch nmos_gate nmos_sd -eq 2 -outputlayer nmos_1 |
| not nmos_1 ( or ESDID thkox lvtn ) -outputlayer nmos |
| rule "nmos.OVL.1" { |
| caption "nmos.OVL.1: Illegal nmos device: nmos must not overlap pwbm" |
| and nmos pwbm |
| } |
| rule "nmos.OVL.2" { |
| caption "nmos.OVL.2: Illegal nmos device: nmos must not overlap pwde" |
| and nmos pwde |
| } |
| rule "nmos.OVL.3" { |
| caption "nmos.OVL.3: Illegal nmos device: nmos must not overlap nwell" |
| and nmos nwell |
| } |
| rule "nmos.OVL.4" { |
| caption "nmos.OVL.4: Illegal nmos device: nmos must not overlap hvtp" |
| and nmos hvtp |
| } |
| rule "nmos.OVL.5" { |
| caption "nmos.OVL.5: Illegal nmos device: nmos must not overlap lvtn" |
| and nmos lvtn |
| } |
| rule "nmos.OVL.6" { |
| caption "nmos.OVL.6: Illegal nmos device: nmos must not overlap tunm" |
| and nmos tunm |
| } |
| rule "nmos.OVL.7" { |
| caption "nmos.OVL.7: Illegal nmos device: nmos must not overlap thkox" |
| and nmos thkox |
| } |
| rule "nmos.OVL.8" { |
| caption "nmos.OVL.8: Illegal nmos device: nmos must not overlap rpm" |
| and nmos rpm |
| } |
| rule "nmos.OVL.9" { |
| caption "nmos.OVL.9: Illegal nmos device: nmos must not overlap rrpm" |
| and nmos rrpm |
| } |
| rule "nmos.OVL.10" { |
| caption "nmos.OVL.10: Illegal nmos device: nmos must not overlap urpm" |
| and nmos urpm |
| } |
| rule "nmos.OVL.11" { |
| caption "nmos.OVL.11: Illegal nmos device: nmos must not overlap ldntm" |
| and nmos ldntm |
| } |
| rule "nmos.OVL.12" { |
| caption "nmos.OVL.12: Illegal nmos device: nmos must not overlap npc" |
| and nmos npc |
| } |
| rule "nmos.OVL.13" { |
| caption "nmos.OVL.13: Illegal nmos device: nmos must not overlap psdm" |
| and nmos psdm |
| } |
| rule "nmos.OVL.14" { |
| caption "nmos.OVL.14: Illegal nmos device: nmos must not overlap nsm" |
| and nmos nsm |
| } |
| rule "nmos.OVL.15" { |
| caption "nmos.OVL.15: Illegal nmos device: nmos must not overlap skip_pad" |
| and nmos skip_pad |
| } |
| rule "nmos.OVL.16" { |
| caption "nmos.OVL.16: Illegal nmos device: nmos must not overlap fuse" |
| and nmos fuse |
| } |
| rule "nmos.OVL.17" { |
| caption "nmos.OVL.17: Illegal nmos device: nmos must not overlap diff:res" |
| and nmos diffres |
| } |
| rule "nmos.OVL.18" { |
| caption "nmos.OVL.18: Illegal nmos device: nmos must not overlap pwell:res" |
| and nmos pwres |
| } |
| rule "nmos.OVL.19" { |
| caption "nmos.OVL.19: Illegal nmos device: nmos must not overlap poly:res" |
| and nmos polyres |
| } |
| rule "nmos.OVL.20" { |
| caption "nmos.OVL.20: Illegal nmos device: nmos must not overlap li:res" |
| and nmos lires |
| } |
| rule "nmos.OVL.21" { |
| caption "nmos.OVL.21: Illegal nmos device: nmos must not overlap skip_res" |
| and nmos skip_res |
| } |
| rule "nmos.OVL.22" { |
| caption "nmos.OVL.22: Illegal nmos device: nmos must not overlap skip_res" |
| and nmos skip_res |
| } |
| rule "nmos.OVL.23" { |
| caption "nmos.OVL.23: Illegal nmos device: nmos must not overlap skip_res" |
| and nmos skip_res |
| } |
| rule "nmos.OVL.24" { |
| caption "nmos.OVL.24: Illegal nmos device: nmos must not overlap skip_res" |
| and nmos skip_res |
| } |
| rule "nmos.OVL.25" { |
| caption "nmos.OVL.25: Illegal nmos device: nmos must not overlap skip_res" |
| and nmos skip_res |
| } |
| rule "nmos.OVL.26" { |
| caption "nmos.OVL.26: Illegal nmos device: nmos must not overlap areaid:lvNative" |
| and nmos LVID |
| } |
| rule "nmos.OVL.27" { |
| caption "nmos.OVL.27: Illegal nmos device: nmos must not overlap pnp" |
| and nmos pnp |
| } |
| rule "nmos.OVL.28" { |
| caption "nmos.OVL.28: Illegal nmos device: nmos must not overlap npn" |
| and nmos npn |
| } |
| rule "nmos.OVL.29" { |
| caption "nmos.OVL.29: Illegal nmos device: nmos must not overlap areaid:diode" |
| and nmos DiodeID |
| } |
| rule "nmos.OVL.30" { |
| caption "nmos.OVL.30: Illegal nmos device: nmos must not overlap areaid:photo" |
| and nmos PHdiodeID |
| } |
| rule "nmos.OVL.31" { |
| caption "nmos.OVL.31: Illegal nmos device: nmos must not overlap areaid:core" |
| and nmos COREID |
| } |
| rule "nmos.OVL.32" { |
| caption "nmos.OVL.32: Illegal nmos device: nmos must not overlap areaid:extendedDrain" |
| and nmos ENID |
| } |
| rule "nmos.OVL.33" { |
| caption "nmos.OVL.33: Illegal nmos device: nmos must not overlap areaid:seal" |
| and nmos SEALID |
| } |
| rule "nmos.OVL.34" { |
| caption "nmos.OVL.34: Illegal nmos device: nmos must not overlap v5" |
| and nmos v5 |
| } |
| rule "nmos.OVL.35" { |
| caption "nmos.OVL.35: Illegal nmos device: nmos must not overlap v12" |
| and nmos v12 |
| } |
| rule "nmos.OVL.36" { |
| caption "nmos.OVL.36: Illegal nmos device: nmos must not overlap v20" |
| and nmos v20 |
| } |
| rule "nmos.OVL.37" { |
| caption "nmos.OVL.37: Illegal nmos device: nmos must not overlap poly:model" |
| and nmos polyModel |
| } |
| and ( and ( and nmos_1 COREID ) ldntm ) tunm -outputlayer exempt_sonos |
| not ( not ( not ( and nmos_1 lvtn ) LVID ) thkox ) exempt_sonos -outputlayer nmos_lvt |
| rule "nmos_lvt.OVL.1" { |
| caption "nmos_lvt.OVL.1: Illegal nmos lvt device: nmos_lvt must not overlap pwbm" |
| and nmos_lvt pwbm |
| } |
| rule "nmos_lvt.OVL.2" { |
| caption "nmos_lvt.OVL.2: Illegal nmos lvt device: nmos_lvt must not overlap pwde" |
| and nmos_lvt pwde |
| } |
| rule "nmos_lvt.OVL.3" { |
| caption "nmos_lvt.OVL.3: Illegal nmos lvt device: nmos_lvt must not overlap nwell" |
| and nmos_lvt nwell |
| } |
| rule "nmos_lvt.OVL.4" { |
| caption "nmos_lvt.OVL.4: Illegal nmos lvt device: nmos_lvt must not overlap hvtp" |
| and nmos_lvt hvtp |
| } |
| rule "nmos_lvt.OVL.5" { |
| caption "nmos_lvt.OVL.5: Illegal nmos lvt device: nmos_lvt must not overlap tunm" |
| and nmos_lvt tunm |
| } |
| rule "nmos_lvt.OVL.6" { |
| caption "nmos_lvt.OVL.6: Illegal nmos lvt device: nmos_lvt must not overlap thkox" |
| and nmos_lvt thkox |
| } |
| rule "nmos_lvt.OVL.7" { |
| caption "nmos_lvt.OVL.7: Illegal nmos lvt device: nmos_lvt must not overlap rpm" |
| and nmos_lvt rpm |
| } |
| rule "nmos_lvt.OVL.8" { |
| caption "nmos_lvt.OVL.8: Illegal nmos lvt device: nmos_lvt must not overlap rrpm" |
| and nmos_lvt rrpm |
| } |
| rule "nmos_lvt.OVL.9" { |
| caption "nmos_lvt.OVL.9: Illegal nmos lvt device: nmos_lvt must not overlap urpm" |
| and nmos_lvt urpm |
| } |
| rule "nmos_lvt.OVL.10" { |
| caption "nmos_lvt.OVL.10: Illegal nmos lvt device: nmos_lvt must not overlap ldntm" |
| and nmos_lvt ldntm |
| } |
| rule "nmos_lvt.OVL.11" { |
| caption "nmos_lvt.OVL.11: Illegal nmos lvt device: nmos_lvt must not overlap npc" |
| and nmos_lvt npc |
| } |
| rule "nmos_lvt.OVL.12" { |
| caption "nmos_lvt.OVL.12: Illegal nmos lvt device: nmos_lvt must not overlap psdm" |
| and nmos_lvt psdm |
| } |
| rule "nmos_lvt.OVL.13" { |
| caption "nmos_lvt.OVL.13: Illegal nmos lvt device: nmos_lvt must not overlap nsm" |
| and nmos_lvt nsm |
| } |
| rule "nmos_lvt.OVL.14" { |
| caption "nmos_lvt.OVL.14: Illegal nmos lvt device: nmos_lvt must not overlap skip_pad" |
| and nmos_lvt skip_pad |
| } |
| rule "nmos_lvt.OVL.15" { |
| caption "nmos_lvt.OVL.15: Illegal nmos lvt device: nmos_lvt must not overlap fuse" |
| and nmos_lvt fuse |
| } |
| rule "nmos_lvt.OVL.16" { |
| caption "nmos_lvt.OVL.16: Illegal nmos lvt device: nmos_lvt must not overlap diff:res" |
| and nmos_lvt diffres |
| } |
| rule "nmos_lvt.OVL.17" { |
| caption "nmos_lvt.OVL.17: Illegal nmos lvt device: nmos_lvt must not overlap pwell:res" |
| and nmos_lvt pwres |
| } |
| rule "nmos_lvt.OVL.18" { |
| caption "nmos_lvt.OVL.18: Illegal nmos lvt device: nmos_lvt must not overlap poly:res" |
| and nmos_lvt polyres |
| } |
| rule "nmos_lvt.OVL.19" { |
| caption "nmos_lvt.OVL.19: Illegal nmos lvt device: nmos_lvt must not overlap li:res" |
| and nmos_lvt lires |
| } |
| rule "nmos_lvt.OVL.20" { |
| caption "nmos_lvt.OVL.20: Illegal nmos lvt device: nmos_lvt must not overlap skip_res" |
| and nmos_lvt skip_res |
| } |
| rule "nmos_lvt.OVL.21" { |
| caption "nmos_lvt.OVL.21: Illegal nmos lvt device: nmos_lvt must not overlap skip_res" |
| and nmos_lvt skip_res |
| } |
| rule "nmos_lvt.OVL.22" { |
| caption "nmos_lvt.OVL.22: Illegal nmos lvt device: nmos_lvt must not overlap skip_res" |
| and nmos_lvt skip_res |
| } |
| rule "nmos_lvt.OVL.23" { |
| caption "nmos_lvt.OVL.23: Illegal nmos lvt device: nmos_lvt must not overlap skip_res" |
| and nmos_lvt skip_res |
| } |
| rule "nmos_lvt.OVL.24" { |
| caption "nmos_lvt.OVL.24: Illegal nmos lvt device: nmos_lvt must not overlap skip_res" |
| and nmos_lvt skip_res |
| } |
| rule "nmos_lvt.OVL.25" { |
| caption "nmos_lvt.OVL.25: Illegal nmos lvt device: nmos_lvt must not overlap areaid:lvNative" |
| and nmos_lvt LVID |
| } |
| rule "nmos_lvt.OVL.26" { |
| caption "nmos_lvt.OVL.26: Illegal nmos lvt device: nmos_lvt must not overlap pnp" |
| and nmos_lvt pnp |
| } |
| rule "nmos_lvt.OVL.27" { |
| caption "nmos_lvt.OVL.27: Illegal nmos lvt device: nmos_lvt must not overlap npn" |
| and nmos_lvt npn |
| } |
| rule "nmos_lvt.OVL.28" { |
| caption "nmos_lvt.OVL.28: Illegal nmos lvt device: nmos_lvt must not overlap areaid:diode" |
| and nmos_lvt DiodeID |
| } |
| rule "nmos_lvt.OVL.29" { |
| caption "nmos_lvt.OVL.29: Illegal nmos lvt device: nmos_lvt must not overlap areaid:photo" |
| and nmos_lvt PHdiodeID |
| } |
| rule "nmos_lvt.OVL.30" { |
| caption "nmos_lvt.OVL.30: Illegal nmos lvt device: nmos_lvt must not overlap areaid:core" |
| and nmos_lvt COREID |
| } |
| rule "nmos_lvt.OVL.31" { |
| caption "nmos_lvt.OVL.31: Illegal nmos lvt device: nmos_lvt must not overlap areaid:esd" |
| and nmos_lvt ESDID |
| } |
| rule "nmos_lvt.OVL.32" { |
| caption "nmos_lvt.OVL.32: Illegal nmos lvt device: nmos_lvt must not overlap areaid:extendedDrain" |
| and nmos_lvt ENID |
| } |
| rule "nmos_lvt.OVL.33" { |
| caption "nmos_lvt.OVL.33: Illegal nmos lvt device: nmos_lvt must not overlap areaid:seal" |
| and nmos_lvt SEALID |
| } |
| rule "nmos_lvt.OVL.34" { |
| caption "nmos_lvt.OVL.34: Illegal nmos lvt device: nmos_lvt must not overlap v5" |
| and nmos_lvt v5 |
| } |
| rule "nmos_lvt.OVL.35" { |
| caption "nmos_lvt.OVL.35: Illegal nmos lvt device: nmos_lvt must not overlap v12" |
| and nmos_lvt v12 |
| } |
| rule "nmos_lvt.OVL.36" { |
| caption "nmos_lvt.OVL.36: Illegal nmos lvt device: nmos_lvt must not overlap v20" |
| and nmos_lvt v20 |
| } |
| rule "nmos_lvt.OVL.37" { |
| caption "nmos_lvt.OVL.37: Illegal nmos lvt device: nmos_lvt must not overlap poly:model" |
| and nmos_lvt polyModel |
| } |
| not ( and nmos_1 ( and v5 thkox ) ) ( or LVID lvtn ESDID ) -outputlayer nmos_v5 |
| rule "nmos_v5.OVL.1" { |
| caption "nmos_v5.OVL.1: Illegal nmos_v5 device: nmos_v5 must not overlap pwbm" |
| and nmos_v5 pwbm |
| } |
| rule "nmos_v5.OVL.2" { |
| caption "nmos_v5.OVL.2: Illegal nmos_v5 device: nmos_v5 must not overlap pwde" |
| and nmos_v5 pwde |
| } |
| rule "nmos_v5.OVL.3" { |
| caption "nmos_v5.OVL.3: Illegal nmos_v5 device: nmos_v5 must not overlap nwell" |
| and nmos_v5 nwell |
| } |
| rule "nmos_v5.OVL.4" { |
| caption "nmos_v5.OVL.4: Illegal nmos_v5 device: nmos_v5 must not overlap hvtp" |
| and nmos_v5 hvtp |
| } |
| rule "nmos_v5.OVL.5" { |
| caption "nmos_v5.OVL.5: Illegal nmos_v5 device: nmos_v5 must not overlap lvtn" |
| and nmos_v5 lvtn |
| } |
| rule "nmos_v5.OVL.6" { |
| caption "nmos_v5.OVL.6: Illegal nmos_v5 device: nmos_v5 must not overlap tunm" |
| and nmos_v5 tunm |
| } |
| rule "nmos_v5.OVL.7" { |
| caption "nmos_v5.OVL.7: Illegal nmos_v5 device: nmos_v5 must not overlap rpm" |
| and nmos_v5 rpm |
| } |
| rule "nmos_v5.OVL.8" { |
| caption "nmos_v5.OVL.8: Illegal nmos_v5 device: nmos_v5 must not overlap rrpm" |
| and nmos_v5 rrpm |
| } |
| rule "nmos_v5.OVL.9" { |
| caption "nmos_v5.OVL.9: Illegal nmos_v5 device: nmos_v5 must not overlap urpm" |
| and nmos_v5 urpm |
| } |
| rule "nmos_v5.OVL.10" { |
| caption "nmos_v5.OVL.10: Illegal nmos_v5 device: nmos_v5 must not overlap ldntm" |
| and nmos_v5 ldntm |
| } |
| rule "nmos_v5.OVL.11" { |
| caption "nmos_v5.OVL.11: Illegal nmos_v5 device: nmos_v5 must not overlap npc" |
| and nmos_v5 npc |
| } |
| rule "nmos_v5.OVL.12" { |
| caption "nmos_v5.OVL.12: Illegal nmos_v5 device: nmos_v5 must not overlap psdm" |
| and nmos_v5 psdm |
| } |
| rule "nmos_v5.OVL.13" { |
| caption "nmos_v5.OVL.13: Illegal nmos_v5 device: nmos_v5 must not overlap nsm" |
| and nmos_v5 nsm |
| } |
| rule "nmos_v5.OVL.14" { |
| caption "nmos_v5.OVL.14: Illegal nmos_v5 device: nmos_v5 must not overlap skip_pad" |
| and nmos_v5 skip_pad |
| } |
| rule "nmos_v5.OVL.15" { |
| caption "nmos_v5.OVL.15: Illegal nmos_v5 device: nmos_v5 must not overlap fuse" |
| and nmos_v5 fuse |
| } |
| rule "nmos_v5.OVL.16" { |
| caption "nmos_v5.OVL.16: Illegal nmos_v5 device: nmos_v5 must not overlap diff:res" |
| and nmos_v5 diffres |
| } |
| rule "nmos_v5.OVL.17" { |
| caption "nmos_v5.OVL.17: Illegal nmos_v5 device: nmos_v5 must not overlap pwell:res" |
| and nmos_v5 pwres |
| } |
| rule "nmos_v5.OVL.18" { |
| caption "nmos_v5.OVL.18: Illegal nmos_v5 device: nmos_v5 must not overlap poly:res" |
| and nmos_v5 polyres |
| } |
| rule "nmos_v5.OVL.19" { |
| caption "nmos_v5.OVL.19: Illegal nmos_v5 device: nmos_v5 must not overlap li:res" |
| and nmos_v5 lires |
| } |
| rule "nmos_v5.OVL.20" { |
| caption "nmos_v5.OVL.20: Illegal nmos_v5 device: nmos_v5 must not overlap skip_res" |
| and nmos_v5 skip_res |
| } |
| rule "nmos_v5.OVL.21" { |
| caption "nmos_v5.OVL.21: Illegal nmos_v5 device: nmos_v5 must not overlap skip_res" |
| and nmos_v5 skip_res |
| } |
| rule "nmos_v5.OVL.22" { |
| caption "nmos_v5.OVL.22: Illegal nmos_v5 device: nmos_v5 must not overlap skip_res" |
| and nmos_v5 skip_res |
| } |
| rule "nmos_v5.OVL.23" { |
| caption "nmos_v5.OVL.23: Illegal nmos_v5 device: nmos_v5 must not overlap skip_res" |
| and nmos_v5 skip_res |
| } |
| rule "nmos_v5.OVL.24" { |
| caption "nmos_v5.OVL.24: Illegal nmos_v5 device: nmos_v5 must not overlap skip_res" |
| and nmos_v5 skip_res |
| } |
| rule "nmos_v5.OVL.25" { |
| caption "nmos_v5.OVL.25: Illegal nmos_v5 device: nmos_v5 must not overlap areaid:lvNative" |
| and nmos_v5 LVID |
| } |
| rule "nmos_v5.OVL.26" { |
| caption "nmos_v5.OVL.26: Illegal nmos_v5 device: nmos_v5 must not overlap pnp" |
| and nmos_v5 pnp |
| } |
| rule "nmos_v5.OVL.27" { |
| caption "nmos_v5.OVL.27: Illegal nmos_v5 device: nmos_v5 must not overlap npn" |
| and nmos_v5 npn |
| } |
| rule "nmos_v5.OVL.28" { |
| caption "nmos_v5.OVL.28: Illegal nmos_v5 device: nmos_v5 must not overlap areaid:diode" |
| and nmos_v5 DiodeID |
| } |
| rule "nmos_v5.OVL.29" { |
| caption "nmos_v5.OVL.29: Illegal nmos_v5 device: nmos_v5 must not overlap areaid:photo" |
| and nmos_v5 PHdiodeID |
| } |
| rule "nmos_v5.OVL.30" { |
| caption "nmos_v5.OVL.30: Illegal nmos_v5 device: nmos_v5 must not overlap areaid:core" |
| and nmos_v5 COREID |
| } |
| rule "nmos_v5.OVL.31" { |
| caption "nmos_v5.OVL.31: Illegal nmos_v5 device: nmos_v5 must not overlap areaid:extendedDrain" |
| and nmos_v5 ENID |
| } |
| rule "nmos_v5.OVL.32" { |
| caption "nmos_v5.OVL.32: Illegal nmos_v5 device: nmos_v5 must not overlap areaid:seal" |
| and nmos_v5 SEALID |
| } |
| rule "nmos_v5.OVL.33" { |
| caption "nmos_v5.OVL.33: Illegal nmos_v5 device: nmos_v5 must not overlap v12" |
| and nmos_v5 v12 |
| } |
| rule "nmos_v5.OVL.34" { |
| caption "nmos_v5.OVL.34: Illegal nmos_v5 device: nmos_v5 must not overlap v20" |
| and nmos_v5 v20 |
| } |
| rule "nmos_v5.OVL.35" { |
| caption "nmos_v5.OVL.35: Illegal nmos_v5 device: nmos_v5 must not overlap poly:model" |
| and nmos_v5 polyModel |
| } |
| and ( and nmos_1 ( and ( and v5 thkox ) LVID ) ) lvtn -outputlayer nmos_nat_v3 |
| rule "nmos_nat_v3.OVL.1" { |
| caption "nmos_nat_v3.OVL.1: Illegal nmos_nat_v3 device: nmos_nat_v3 must not overlap pwbm" |
| and nmos_nat_v3 pwbm |
| } |
| rule "nmos_nat_v3.OVL.2" { |
| caption "nmos_nat_v3.OVL.2: Illegal nmos_nat_v3 device: nmos_nat_v3 must not overlap pwde" |
| and nmos_nat_v3 pwde |
| } |
| rule "nmos_nat_v3.OVL.3" { |
| caption "nmos_nat_v3.OVL.3: Illegal nmos_nat_v3 device: nmos_nat_v3 must not overlap nwell" |
| and nmos_nat_v3 nwell |
| } |
| rule "nmos_nat_v3.OVL.4" { |
| caption "nmos_nat_v3.OVL.4: Illegal nmos_nat_v3 device: nmos_nat_v3 must not overlap hvtp" |
| and nmos_nat_v3 hvtp |
| } |
| rule "nmos_nat_v3.OVL.5" { |
| caption "nmos_nat_v3.OVL.5: Illegal nmos_nat_v3 device: nmos_nat_v3 must not overlap tunm" |
| and nmos_nat_v3 tunm |
| } |
| rule "nmos_nat_v3.OVL.6" { |
| caption "nmos_nat_v3.OVL.6: Illegal nmos_nat_v3 device: nmos_nat_v3 must not overlap rpm" |
| and nmos_nat_v3 rpm |
| } |
| rule "nmos_nat_v3.OVL.7" { |
| caption "nmos_nat_v3.OVL.7: Illegal nmos_nat_v3 device: nmos_nat_v3 must not overlap rrpm" |
| and nmos_nat_v3 rrpm |
| } |
| rule "nmos_nat_v3.OVL.8" { |
| caption "nmos_nat_v3.OVL.8: Illegal nmos_nat_v3 device: nmos_nat_v3 must not overlap urpm" |
| and nmos_nat_v3 urpm |
| } |
| rule "nmos_nat_v3.OVL.9" { |
| caption "nmos_nat_v3.OVL.9: Illegal nmos_nat_v3 device: nmos_nat_v3 must not overlap ldntm" |
| and nmos_nat_v3 ldntm |
| } |
| rule "nmos_nat_v3.OVL.10" { |
| caption "nmos_nat_v3.OVL.10: Illegal nmos_nat_v3 device: nmos_nat_v3 must not overlap npc" |
| and nmos_nat_v3 npc |
| } |
| rule "nmos_nat_v3.OVL.11" { |
| caption "nmos_nat_v3.OVL.11: Illegal nmos_nat_v3 device: nmos_nat_v3 must not overlap psdm" |
| and nmos_nat_v3 psdm |
| } |
| rule "nmos_nat_v3.OVL.12" { |
| caption "nmos_nat_v3.OVL.12: Illegal nmos_nat_v3 device: nmos_nat_v3 must not overlap nsm" |
| and nmos_nat_v3 nsm |
| } |
| rule "nmos_nat_v3.OVL.13" { |
| caption "nmos_nat_v3.OVL.13: Illegal nmos_nat_v3 device: nmos_nat_v3 must not overlap skip_pad" |
| and nmos_nat_v3 skip_pad |
| } |
| rule "nmos_nat_v3.OVL.14" { |
| caption "nmos_nat_v3.OVL.14: Illegal nmos_nat_v3 device: nmos_nat_v3 must not overlap fuse" |
| and nmos_nat_v3 fuse |
| } |
| rule "nmos_nat_v3.OVL.15" { |
| caption "nmos_nat_v3.OVL.15: Illegal nmos_nat_v3 device: nmos_nat_v3 must not overlap diff:res" |
| and nmos_nat_v3 diffres |
| } |
| rule "nmos_nat_v3.OVL.16" { |
| caption "nmos_nat_v3.OVL.16: Illegal nmos_nat_v3 device: nmos_nat_v3 must not overlap pwell:res" |
| and nmos_nat_v3 pwres |
| } |
| rule "nmos_nat_v3.OVL.17" { |
| caption "nmos_nat_v3.OVL.17: Illegal nmos_nat_v3 device: nmos_nat_v3 must not overlap poly:res" |
| and nmos_nat_v3 polyres |
| } |
| rule "nmos_nat_v3.OVL.18" { |
| caption "nmos_nat_v3.OVL.18: Illegal nmos_nat_v3 device: nmos_nat_v3 must not overlap li:res" |
| and nmos_nat_v3 lires |
| } |
| rule "nmos_nat_v3.OVL.19" { |
| caption "nmos_nat_v3.OVL.19: Illegal nmos_nat_v3 device: nmos_nat_v3 must not overlap skip_res" |
| and nmos_nat_v3 skip_res |
| } |
| rule "nmos_nat_v3.OVL.20" { |
| caption "nmos_nat_v3.OVL.20: Illegal nmos_nat_v3 device: nmos_nat_v3 must not overlap skip_res" |
| and nmos_nat_v3 skip_res |
| } |
| rule "nmos_nat_v3.OVL.21" { |
| caption "nmos_nat_v3.OVL.21: Illegal nmos_nat_v3 device: nmos_nat_v3 must not overlap skip_res" |
| and nmos_nat_v3 skip_res |
| } |
| rule "nmos_nat_v3.OVL.22" { |
| caption "nmos_nat_v3.OVL.22: Illegal nmos_nat_v3 device: nmos_nat_v3 must not overlap skip_res" |
| and nmos_nat_v3 skip_res |
| } |
| rule "nmos_nat_v3.OVL.23" { |
| caption "nmos_nat_v3.OVL.23: Illegal nmos_nat_v3 device: nmos_nat_v3 must not overlap skip_res" |
| and nmos_nat_v3 skip_res |
| } |
| rule "nmos_nat_v3.OVL.24" { |
| caption "nmos_nat_v3.OVL.24: Illegal nmos_nat_v3 device: nmos_nat_v3 must not overlap pnp" |
| and nmos_nat_v3 pnp |
| } |
| rule "nmos_nat_v3.OVL.25" { |
| caption "nmos_nat_v3.OVL.25: Illegal nmos_nat_v3 device: nmos_nat_v3 must not overlap npn" |
| and nmos_nat_v3 npn |
| } |
| rule "nmos_nat_v3.OVL.26" { |
| caption "nmos_nat_v3.OVL.26: Illegal nmos_nat_v3 device: nmos_nat_v3 must not overlap areaid:diode" |
| and nmos_nat_v3 DiodeID |
| } |
| rule "nmos_nat_v3.OVL.27" { |
| caption "nmos_nat_v3.OVL.27: Illegal nmos_nat_v3 device: nmos_nat_v3 must not overlap areaid:photo" |
| and nmos_nat_v3 PHdiodeID |
| } |
| rule "nmos_nat_v3.OVL.28" { |
| caption "nmos_nat_v3.OVL.28: Illegal nmos_nat_v3 device: nmos_nat_v3 must not overlap areaid:core" |
| and nmos_nat_v3 COREID |
| } |
| rule "nmos_nat_v3.OVL.29" { |
| caption "nmos_nat_v3.OVL.29: Illegal nmos_nat_v3 device: nmos_nat_v3 must not overlap areaid:extendedDrain" |
| and nmos_nat_v3 ENID |
| } |
| rule "nmos_nat_v3.OVL.30" { |
| caption "nmos_nat_v3.OVL.30: Illegal nmos_nat_v3 device: nmos_nat_v3 must not overlap areaid:seal" |
| and nmos_nat_v3 SEALID |
| } |
| rule "nmos_nat_v3.OVL.31" { |
| caption "nmos_nat_v3.OVL.31: Illegal nmos_nat_v3 device: nmos_nat_v3 must not overlap v12" |
| and nmos_nat_v3 v12 |
| } |
| rule "nmos_nat_v3.OVL.32" { |
| caption "nmos_nat_v3.OVL.32: Illegal nmos_nat_v3 device: nmos_nat_v3 must not overlap v20" |
| and nmos_nat_v3 v20 |
| } |
| rule "nmos_nat_v3.OVL.33" { |
| caption "nmos_nat_v3.OVL.33: Illegal nmos_nat_v3 device: nmos_nat_v3 must not overlap areaid:esd" |
| and nmos_nat_v3 ESDID |
| } |
| rule "nmos_nat_v3.OVL.34" { |
| caption "nmos_nat_v3.OVL.34: Illegal nmos_nat_v3 device: nmos_nat_v3 must not overlap poly:model" |
| and nmos_nat_v3 polyModel |
| } |
| not ( and ( and nmos_1 ( not ( and v5 thkox ) LVID ) ) lvtn ) ESDID -outputlayer nmos_nat_v5 |
| rule "nmos_nat_v5.OVL.1" { |
| caption "nmos_nat_v5.OVL.1: Illegal nmos_nat_v5 device: nmos_nat_v5 must not overlap pwbm" |
| and nmos_nat_v5 pwbm |
| } |
| rule "nmos_nat_v5.OVL.2" { |
| caption "nmos_nat_v5.OVL.2: Illegal nmos_nat_v5 device: nmos_nat_v5 must not overlap pwde" |
| and nmos_nat_v5 pwde |
| } |
| rule "nmos_nat_v5.OVL.3" { |
| caption "nmos_nat_v5.OVL.3: Illegal nmos_nat_v5 device: nmos_nat_v5 must not overlap nwell" |
| and nmos_nat_v5 nwell |
| } |
| rule "nmos_nat_v5.OVL.4" { |
| caption "nmos_nat_v5.OVL.4: Illegal nmos_nat_v5 device: nmos_nat_v5 must not overlap hvtp" |
| and nmos_nat_v5 hvtp |
| } |
| rule "nmos_nat_v5.OVL.5" { |
| caption "nmos_nat_v5.OVL.5: Illegal nmos_nat_v5 device: nmos_nat_v5 must not overlap tunm" |
| and nmos_nat_v5 tunm |
| } |
| rule "nmos_nat_v5.OVL.6" { |
| caption "nmos_nat_v5.OVL.6: Illegal nmos_nat_v5 device: nmos_nat_v5 must not overlap rpm" |
| and nmos_nat_v5 rpm |
| } |
| rule "nmos_nat_v5.OVL.7" { |
| caption "nmos_nat_v5.OVL.7: Illegal nmos_nat_v5 device: nmos_nat_v5 must not overlap rrpm" |
| and nmos_nat_v5 rrpm |
| } |
| rule "nmos_nat_v5.OVL.8" { |
| caption "nmos_nat_v5.OVL.8: Illegal nmos_nat_v5 device: nmos_nat_v5 must not overlap urpm" |
| and nmos_nat_v5 urpm |
| } |
| rule "nmos_nat_v5.OVL.9" { |
| caption "nmos_nat_v5.OVL.9: Illegal nmos_nat_v5 device: nmos_nat_v5 must not overlap ldntm" |
| and nmos_nat_v5 ldntm |
| } |
| rule "nmos_nat_v5.OVL.10" { |
| caption "nmos_nat_v5.OVL.10: Illegal nmos_nat_v5 device: nmos_nat_v5 must not overlap npc" |
| and nmos_nat_v5 npc |
| } |
| rule "nmos_nat_v5.OVL.11" { |
| caption "nmos_nat_v5.OVL.11: Illegal nmos_nat_v5 device: nmos_nat_v5 must not overlap psdm" |
| and nmos_nat_v5 psdm |
| } |
| rule "nmos_nat_v5.OVL.12" { |
| caption "nmos_nat_v5.OVL.12: Illegal nmos_nat_v5 device: nmos_nat_v5 must not overlap nsm" |
| and nmos_nat_v5 nsm |
| } |
| rule "nmos_nat_v5.OVL.13" { |
| caption "nmos_nat_v5.OVL.13: Illegal nmos_nat_v5 device: nmos_nat_v5 must not overlap skip_pad" |
| and nmos_nat_v5 skip_pad |
| } |
| rule "nmos_nat_v5.OVL.14" { |
| caption "nmos_nat_v5.OVL.14: Illegal nmos_nat_v5 device: nmos_nat_v5 must not overlap fuse" |
| and nmos_nat_v5 fuse |
| } |
| rule "nmos_nat_v5.OVL.15" { |
| caption "nmos_nat_v5.OVL.15: Illegal nmos_nat_v5 device: nmos_nat_v5 must not overlap diff:res" |
| and nmos_nat_v5 diffres |
| } |
| rule "nmos_nat_v5.OVL.16" { |
| caption "nmos_nat_v5.OVL.16: Illegal nmos_nat_v5 device: nmos_nat_v5 must not overlap pwell:res" |
| and nmos_nat_v5 pwres |
| } |
| rule "nmos_nat_v5.OVL.17" { |
| caption "nmos_nat_v5.OVL.17: Illegal nmos_nat_v5 device: nmos_nat_v5 must not overlap poly:res" |
| and nmos_nat_v5 polyres |
| } |
| rule "nmos_nat_v5.OVL.18" { |
| caption "nmos_nat_v5.OVL.18: Illegal nmos_nat_v5 device: nmos_nat_v5 must not overlap li:res" |
| and nmos_nat_v5 lires |
| } |
| rule "nmos_nat_v5.OVL.19" { |
| caption "nmos_nat_v5.OVL.19: Illegal nmos_nat_v5 device: nmos_nat_v5 must not overlap skip_res" |
| and nmos_nat_v5 skip_res |
| } |
| rule "nmos_nat_v5.OVL.20" { |
| caption "nmos_nat_v5.OVL.20: Illegal nmos_nat_v5 device: nmos_nat_v5 must not overlap skip_res" |
| and nmos_nat_v5 skip_res |
| } |
| rule "nmos_nat_v5.OVL.21" { |
| caption "nmos_nat_v5.OVL.21: Illegal nmos_nat_v5 device: nmos_nat_v5 must not overlap skip_res" |
| and nmos_nat_v5 skip_res |
| } |
| rule "nmos_nat_v5.OVL.22" { |
| caption "nmos_nat_v5.OVL.22: Illegal nmos_nat_v5 device: nmos_nat_v5 must not overlap skip_res" |
| and nmos_nat_v5 skip_res |
| } |
| rule "nmos_nat_v5.OVL.23" { |
| caption "nmos_nat_v5.OVL.23: Illegal nmos_nat_v5 device: nmos_nat_v5 must not overlap skip_res" |
| and nmos_nat_v5 skip_res |
| } |
| rule "nmos_nat_v5.OVL.24" { |
| caption "nmos_nat_v5.OVL.24: Illegal nmos_nat_v5 device: nmos_nat_v5 must not overlap pnp" |
| and nmos_nat_v5 pnp |
| } |
| rule "nmos_nat_v5.OVL.25" { |
| caption "nmos_nat_v5.OVL.25: Illegal nmos_nat_v5 device: nmos_nat_v5 must not overlap npn" |
| and nmos_nat_v5 npn |
| } |
| rule "nmos_nat_v5.OVL.26" { |
| caption "nmos_nat_v5.OVL.26: Illegal nmos_nat_v5 device: nmos_nat_v5 must not overlap areaid:diode" |
| and nmos_nat_v5 DiodeID |
| } |
| rule "nmos_nat_v5.OVL.27" { |
| caption "nmos_nat_v5.OVL.27: Illegal nmos_nat_v5 device: nmos_nat_v5 must not overlap areaid:photo" |
| and nmos_nat_v5 PHdiodeID |
| } |
| rule "nmos_nat_v5.OVL.28" { |
| caption "nmos_nat_v5.OVL.28: Illegal nmos_nat_v5 device: nmos_nat_v5 must not overlap areaid:core" |
| and nmos_nat_v5 COREID |
| } |
| rule "nmos_nat_v5.OVL.29" { |
| caption "nmos_nat_v5.OVL.29: Illegal nmos_nat_v5 device: nmos_nat_v5 must not overlap areaid:extendedDrain" |
| and nmos_nat_v5 ENID |
| } |
| rule "nmos_nat_v5.OVL.30" { |
| caption "nmos_nat_v5.OVL.30: Illegal nmos_nat_v5 device: nmos_nat_v5 must not overlap areaid:seal" |
| and nmos_nat_v5 SEALID |
| } |
| rule "nmos_nat_v5.OVL.31" { |
| caption "nmos_nat_v5.OVL.31: Illegal nmos_nat_v5 device: nmos_nat_v5 must not overlap v12" |
| and nmos_nat_v5 v12 |
| } |
| rule "nmos_nat_v5.OVL.32" { |
| caption "nmos_nat_v5.OVL.32: Illegal nmos_nat_v5 device: nmos_nat_v5 must not overlap v20" |
| and nmos_nat_v5 v20 |
| } |
| rule "nmos_nat_v5.OVL.33" { |
| caption "nmos_nat_v5.OVL.33: Illegal nmos_nat_v5 device: nmos_nat_v5 must not overlap areaid:esd" |
| and nmos_nat_v5 ESDID |
| } |
| rule "nmos_nat_v5.OVL.34" { |
| caption "nmos_nat_v5.OVL.34: Illegal nmos_nat_v5 device: nmos_nat_v5 must not overlap poly:model" |
| and nmos_nat_v5 polyModel |
| } |
| and ( not ( and ( and ( and gate nsdm ) v12 ) ENID ) nwell ) thkox -outputlayer nmos_de_v12 |
| rule "nmos_de_v12.OVL.1" { |
| caption "nmos_de_v12.OVL.1: Illegal nmos_de_v12 device: nmos_de_v12 must not overlap pwbm" |
| and nmos_de_v12 pwbm |
| } |
| rule "nmos_de_v12.OVL.2" { |
| caption "nmos_de_v12.OVL.2: Illegal nmos_de_v12 device: nmos_de_v12 must not overlap pwde" |
| and nmos_de_v12 pwde |
| } |
| rule "nmos_de_v12.OVL.3" { |
| caption "nmos_de_v12.OVL.3: Illegal nmos_de_v12 device: nmos_de_v12 must not overlap hvtp" |
| and nmos_de_v12 hvtp |
| } |
| rule "nmos_de_v12.OVL.4" { |
| caption "nmos_de_v12.OVL.4: Illegal nmos_de_v12 device: nmos_de_v12 must not overlap lvtn" |
| and nmos_de_v12 lvtn |
| } |
| rule "nmos_de_v12.OVL.5" { |
| caption "nmos_de_v12.OVL.5: Illegal nmos_de_v12 device: nmos_de_v12 must not overlap tunm" |
| and nmos_de_v12 tunm |
| } |
| rule "nmos_de_v12.OVL.6" { |
| caption "nmos_de_v12.OVL.6: Illegal nmos_de_v12 device: nmos_de_v12 must not overlap rpm" |
| and nmos_de_v12 rpm |
| } |
| rule "nmos_de_v12.OVL.7" { |
| caption "nmos_de_v12.OVL.7: Illegal nmos_de_v12 device: nmos_de_v12 must not overlap rrpm" |
| and nmos_de_v12 rrpm |
| } |
| rule "nmos_de_v12.OVL.8" { |
| caption "nmos_de_v12.OVL.8: Illegal nmos_de_v12 device: nmos_de_v12 must not overlap urpm" |
| and nmos_de_v12 urpm |
| } |
| rule "nmos_de_v12.OVL.9" { |
| caption "nmos_de_v12.OVL.9: Illegal nmos_de_v12 device: nmos_de_v12 must not overlap ldntm" |
| and nmos_de_v12 ldntm |
| } |
| rule "nmos_de_v12.OVL.10" { |
| caption "nmos_de_v12.OVL.10: Illegal nmos_de_v12 device: nmos_de_v12 must not overlap npc" |
| and nmos_de_v12 npc |
| } |
| rule "nmos_de_v12.OVL.11" { |
| caption "nmos_de_v12.OVL.11: Illegal nmos_de_v12 device: nmos_de_v12 must not overlap psdm" |
| and nmos_de_v12 psdm |
| } |
| rule "nmos_de_v12.OVL.12" { |
| caption "nmos_de_v12.OVL.12: Illegal nmos_de_v12 device: nmos_de_v12 must not overlap nsm" |
| and nmos_de_v12 nsm |
| } |
| rule "nmos_de_v12.OVL.13" { |
| caption "nmos_de_v12.OVL.13: Illegal nmos_de_v12 device: nmos_de_v12 must not overlap skip_pad" |
| and nmos_de_v12 skip_pad |
| } |
| rule "nmos_de_v12.OVL.14" { |
| caption "nmos_de_v12.OVL.14: Illegal nmos_de_v12 device: nmos_de_v12 must not overlap fuse" |
| and nmos_de_v12 fuse |
| } |
| rule "nmos_de_v12.OVL.15" { |
| caption "nmos_de_v12.OVL.15: Illegal nmos_de_v12 device: nmos_de_v12 must not overlap diff:res" |
| and nmos_de_v12 diffres |
| } |
| rule "nmos_de_v12.OVL.16" { |
| caption "nmos_de_v12.OVL.16: Illegal nmos_de_v12 device: nmos_de_v12 must not overlap pwell:res" |
| and nmos_de_v12 pwres |
| } |
| rule "nmos_de_v12.OVL.17" { |
| caption "nmos_de_v12.OVL.17: Illegal nmos_de_v12 device: nmos_de_v12 must not overlap poly:res" |
| and nmos_de_v12 polyres |
| } |
| rule "nmos_de_v12.OVL.18" { |
| caption "nmos_de_v12.OVL.18: Illegal nmos_de_v12 device: nmos_de_v12 must not overlap li:res" |
| and nmos_de_v12 lires |
| } |
| rule "nmos_de_v12.OVL.19" { |
| caption "nmos_de_v12.OVL.19: Illegal nmos_de_v12 device: nmos_de_v12 must not overlap skip_res" |
| and nmos_de_v12 skip_res |
| } |
| rule "nmos_de_v12.OVL.20" { |
| caption "nmos_de_v12.OVL.20: Illegal nmos_de_v12 device: nmos_de_v12 must not overlap skip_res" |
| and nmos_de_v12 skip_res |
| } |
| rule "nmos_de_v12.OVL.21" { |
| caption "nmos_de_v12.OVL.21: Illegal nmos_de_v12 device: nmos_de_v12 must not overlap skip_res" |
| and nmos_de_v12 skip_res |
| } |
| rule "nmos_de_v12.OVL.22" { |
| caption "nmos_de_v12.OVL.22: Illegal nmos_de_v12 device: nmos_de_v12 must not overlap skip_res" |
| and nmos_de_v12 skip_res |
| } |
| rule "nmos_de_v12.OVL.23" { |
| caption "nmos_de_v12.OVL.23: Illegal nmos_de_v12 device: nmos_de_v12 must not overlap skip_res" |
| and nmos_de_v12 skip_res |
| } |
| rule "nmos_de_v12.OVL.24" { |
| caption "nmos_de_v12.OVL.24: Illegal nmos_de_v12 device: nmos_de_v12 must not overlap areaid:lvNative" |
| and nmos_de_v12 LVID |
| } |
| rule "nmos_de_v12.OVL.25" { |
| caption "nmos_de_v12.OVL.25: Illegal nmos_de_v12 device: nmos_de_v12 must not overlap pnp" |
| and nmos_de_v12 pnp |
| } |
| rule "nmos_de_v12.OVL.26" { |
| caption "nmos_de_v12.OVL.26: Illegal nmos_de_v12 device: nmos_de_v12 must not overlap npn" |
| and nmos_de_v12 npn |
| } |
| rule "nmos_de_v12.OVL.27" { |
| caption "nmos_de_v12.OVL.27: Illegal nmos_de_v12 device: nmos_de_v12 must not overlap areaid:diode" |
| and nmos_de_v12 DiodeID |
| } |
| rule "nmos_de_v12.OVL.28" { |
| caption "nmos_de_v12.OVL.28: Illegal nmos_de_v12 device: nmos_de_v12 must not overlap areaid:photo" |
| and nmos_de_v12 PHdiodeID |
| } |
| rule "nmos_de_v12.OVL.29" { |
| caption "nmos_de_v12.OVL.29: Illegal nmos_de_v12 device: nmos_de_v12 must not overlap areaid:core" |
| and nmos_de_v12 COREID |
| } |
| rule "nmos_de_v12.OVL.30" { |
| caption "nmos_de_v12.OVL.30: Illegal nmos_de_v12 device: nmos_de_v12 must not overlap areaid:seal" |
| and nmos_de_v12 SEALID |
| } |
| rule "nmos_de_v12.OVL.31" { |
| caption "nmos_de_v12.OVL.31: Illegal nmos_de_v12 device: nmos_de_v12 must not overlap v5" |
| and nmos_de_v12 v5 |
| } |
| rule "nmos_de_v12.OVL.32" { |
| caption "nmos_de_v12.OVL.32: Illegal nmos_de_v12 device: nmos_de_v12 must not overlap v20" |
| and nmos_de_v12 v20 |
| } |
| rule "nmos_de_v12.OVL.33" { |
| caption "nmos_de_v12.OVL.33: Illegal nmos_de_v12 device: nmos_de_v12 must not overlap dnwell" |
| and nmos_de_v12 dnwell |
| } |
| rule "nmos_de_v12.OVL.34" { |
| caption "nmos_de_v12.OVL.34: Illegal nmos_de_v12 device: nmos_de_v12 must not overlap areaid:esd" |
| and nmos_de_v12 ESDID |
| } |
| rule "nmos_de_v12.OVL.35" { |
| caption "nmos_de_v12.OVL.35: Illegal nmos_de_v12 device: nmos_de_v12 must not overlap poly:model" |
| and nmos_de_v12 polyModel |
| } |
| not ngate_v20 ( select -interact poly ( or ngate_v20_nat ngate_v20_zvt ngate_v20_iso_rec ) ) -outputlayer nmos_de_v20 |
| rule "nmos_de_v20.OVL.1" { |
| caption "nmos_de_v20.OVL.1: Illegal nmos_de_v20 device: nmos_de_v20 must not overlap pwde" |
| and nmos_de_v20 pwde |
| } |
| rule "nmos_de_v20.OVL.2" { |
| caption "nmos_de_v20.OVL.2: Illegal nmos_de_v20 device: nmos_de_v20 must not overlap hvtp" |
| and nmos_de_v20 hvtp |
| } |
| rule "nmos_de_v20.OVL.3" { |
| caption "nmos_de_v20.OVL.3: Illegal nmos_de_v20 device: nmos_de_v20 must not overlap tunm" |
| and nmos_de_v20 tunm |
| } |
| rule "nmos_de_v20.OVL.4" { |
| caption "nmos_de_v20.OVL.4: Illegal nmos_de_v20 device: nmos_de_v20 must not overlap rpm" |
| and nmos_de_v20 rpm |
| } |
| rule "nmos_de_v20.OVL.5" { |
| caption "nmos_de_v20.OVL.5: Illegal nmos_de_v20 device: nmos_de_v20 must not overlap rrpm" |
| and nmos_de_v20 rrpm |
| } |
| rule "nmos_de_v20.OVL.6" { |
| caption "nmos_de_v20.OVL.6: Illegal nmos_de_v20 device: nmos_de_v20 must not overlap urpm" |
| and nmos_de_v20 urpm |
| } |
| rule "nmos_de_v20.OVL.7" { |
| caption "nmos_de_v20.OVL.7: Illegal nmos_de_v20 device: nmos_de_v20 must not overlap ldntm" |
| and nmos_de_v20 ldntm |
| } |
| rule "nmos_de_v20.OVL.8" { |
| caption "nmos_de_v20.OVL.8: Illegal nmos_de_v20 device: nmos_de_v20 must not overlap npc" |
| and nmos_de_v20 npc |
| } |
| rule "nmos_de_v20.OVL.9" { |
| caption "nmos_de_v20.OVL.9: Illegal nmos_de_v20 device: nmos_de_v20 must not overlap psdm" |
| and nmos_de_v20 psdm |
| } |
| rule "nmos_de_v20.OVL.10" { |
| caption "nmos_de_v20.OVL.10: Illegal nmos_de_v20 device: nmos_de_v20 must not overlap nsm" |
| and nmos_de_v20 nsm |
| } |
| rule "nmos_de_v20.OVL.11" { |
| caption "nmos_de_v20.OVL.11: Illegal nmos_de_v20 device: nmos_de_v20 must not overlap skip_pad" |
| and nmos_de_v20 skip_pad |
| } |
| rule "nmos_de_v20.OVL.12" { |
| caption "nmos_de_v20.OVL.12: Illegal nmos_de_v20 device: nmos_de_v20 must not overlap fuse" |
| and nmos_de_v20 fuse |
| } |
| rule "nmos_de_v20.OVL.13" { |
| caption "nmos_de_v20.OVL.13: Illegal nmos_de_v20 device: nmos_de_v20 must not overlap diff:res" |
| and nmos_de_v20 diffres |
| } |
| rule "nmos_de_v20.OVL.14" { |
| caption "nmos_de_v20.OVL.14: Illegal nmos_de_v20 device: nmos_de_v20 must not overlap pwell:res" |
| and nmos_de_v20 pwres |
| } |
| rule "nmos_de_v20.OVL.15" { |
| caption "nmos_de_v20.OVL.15: Illegal nmos_de_v20 device: nmos_de_v20 must not overlap poly:res" |
| and nmos_de_v20 polyres |
| } |
| rule "nmos_de_v20.OVL.16" { |
| caption "nmos_de_v20.OVL.16: Illegal nmos_de_v20 device: nmos_de_v20 must not overlap li:res" |
| and nmos_de_v20 lires |
| } |
| rule "nmos_de_v20.OVL.17" { |
| caption "nmos_de_v20.OVL.17: Illegal nmos_de_v20 device: nmos_de_v20 must not overlap skip_res" |
| and nmos_de_v20 skip_res |
| } |
| rule "nmos_de_v20.OVL.18" { |
| caption "nmos_de_v20.OVL.18: Illegal nmos_de_v20 device: nmos_de_v20 must not overlap skip_res" |
| and nmos_de_v20 skip_res |
| } |
| rule "nmos_de_v20.OVL.19" { |
| caption "nmos_de_v20.OVL.19: Illegal nmos_de_v20 device: nmos_de_v20 must not overlap skip_res" |
| and nmos_de_v20 skip_res |
| } |
| rule "nmos_de_v20.OVL.20" { |
| caption "nmos_de_v20.OVL.20: Illegal nmos_de_v20 device: nmos_de_v20 must not overlap skip_res" |
| and nmos_de_v20 skip_res |
| } |
| rule "nmos_de_v20.OVL.21" { |
| caption "nmos_de_v20.OVL.21: Illegal nmos_de_v20 device: nmos_de_v20 must not overlap skip_res" |
| and nmos_de_v20 skip_res |
| } |
| rule "nmos_de_v20.OVL.22" { |
| caption "nmos_de_v20.OVL.22: Illegal nmos_de_v20 device: nmos_de_v20 must not overlap areaid:lvNative" |
| and nmos_de_v20 LVID |
| } |
| rule "nmos_de_v20.OVL.23" { |
| caption "nmos_de_v20.OVL.23: Illegal nmos_de_v20 device: nmos_de_v20 must not overlap pnp" |
| and nmos_de_v20 pnp |
| } |
| rule "nmos_de_v20.OVL.24" { |
| caption "nmos_de_v20.OVL.24: Illegal nmos_de_v20 device: nmos_de_v20 must not overlap npn" |
| and nmos_de_v20 npn |
| } |
| rule "nmos_de_v20.OVL.25" { |
| caption "nmos_de_v20.OVL.25: Illegal nmos_de_v20 device: nmos_de_v20 must not overlap areaid:diode" |
| and nmos_de_v20 DiodeID |
| } |
| rule "nmos_de_v20.OVL.26" { |
| caption "nmos_de_v20.OVL.26: Illegal nmos_de_v20 device: nmos_de_v20 must not overlap areaid:photo" |
| and nmos_de_v20 PHdiodeID |
| } |
| rule "nmos_de_v20.OVL.27" { |
| caption "nmos_de_v20.OVL.27: Illegal nmos_de_v20 device: nmos_de_v20 must not overlap areaid:core" |
| and nmos_de_v20 COREID |
| } |
| rule "nmos_de_v20.OVL.28" { |
| caption "nmos_de_v20.OVL.28: Illegal nmos_de_v20 device: nmos_de_v20 must not overlap areaid:esd" |
| and nmos_de_v20 ESDID |
| } |
| rule "nmos_de_v20.OVL.29" { |
| caption "nmos_de_v20.OVL.29: Illegal nmos_de_v20 device: nmos_de_v20 must not overlap areaid:seal" |
| and nmos_de_v20 SEALID |
| } |
| rule "nmos_de_v20.OVL.30" { |
| caption "nmos_de_v20.OVL.30: Illegal nmos_de_v20 device: nmos_de_v20 must not overlap v5" |
| and nmos_de_v20 v5 |
| } |
| rule "nmos_de_v20.OVL.31" { |
| caption "nmos_de_v20.OVL.31: Illegal nmos_de_v20 device: nmos_de_v20 must not overlap v12" |
| and nmos_de_v20 v12 |
| } |
| rule "nmos_de_v20.OVL.32" { |
| caption "nmos_de_v20.OVL.32: Illegal nmos_de_v20 device: nmos_de_v20 must not overlap poly:model" |
| and nmos_de_v20 polyModel |
| } |
| select -interact ( and ( not ( and ( and ( and gate nsdm ) v20 ) ENID ) nwell ) thkox ) ( holes pwbm ) -outputlayer nmos_de_iso_v20 |
| rule "nmos_de_iso_v20.OVL.1" { |
| caption "nmos_de_iso_v20.OVL.1: Illegal nmos_de_iso_v20 device: nmos_de_iso_v20 must not overlap pwde" |
| and nmos_de_iso_v20 pwde |
| } |
| rule "nmos_de_iso_v20.OVL.2" { |
| caption "nmos_de_iso_v20.OVL.2: Illegal nmos_de_iso_v20 device: nmos_de_iso_v20 must not overlap hvtp" |
| and nmos_de_iso_v20 hvtp |
| } |
| rule "nmos_de_iso_v20.OVL.3" { |
| caption "nmos_de_iso_v20.OVL.3: Illegal nmos_de_iso_v20 device: nmos_de_iso_v20 must not overlap tunm" |
| and nmos_de_iso_v20 tunm |
| } |
| rule "nmos_de_iso_v20.OVL.4" { |
| caption "nmos_de_iso_v20.OVL.4: Illegal nmos_de_iso_v20 device: nmos_de_iso_v20 must not overlap rpm" |
| and nmos_de_iso_v20 rpm |
| } |
| rule "nmos_de_iso_v20.OVL.5" { |
| caption "nmos_de_iso_v20.OVL.5: Illegal nmos_de_iso_v20 device: nmos_de_iso_v20 must not overlap rrpm" |
| and nmos_de_iso_v20 rrpm |
| } |
| rule "nmos_de_iso_v20.OVL.6" { |
| caption "nmos_de_iso_v20.OVL.6: Illegal nmos_de_iso_v20 device: nmos_de_iso_v20 must not overlap urpm" |
| and nmos_de_iso_v20 urpm |
| } |
| rule "nmos_de_iso_v20.OVL.7" { |
| caption "nmos_de_iso_v20.OVL.7: Illegal nmos_de_iso_v20 device: nmos_de_iso_v20 must not overlap ldntm" |
| and nmos_de_iso_v20 ldntm |
| } |
| rule "nmos_de_iso_v20.OVL.8" { |
| caption "nmos_de_iso_v20.OVL.8: Illegal nmos_de_iso_v20 device: nmos_de_iso_v20 must not overlap npc" |
| and nmos_de_iso_v20 npc |
| } |
| rule "nmos_de_iso_v20.OVL.9" { |
| caption "nmos_de_iso_v20.OVL.9: Illegal nmos_de_iso_v20 device: nmos_de_iso_v20 must not overlap psdm" |
| and nmos_de_iso_v20 psdm |
| } |
| rule "nmos_de_iso_v20.OVL.10" { |
| caption "nmos_de_iso_v20.OVL.10: Illegal nmos_de_iso_v20 device: nmos_de_iso_v20 must not overlap nsm" |
| and nmos_de_iso_v20 nsm |
| } |
| rule "nmos_de_iso_v20.OVL.11" { |
| caption "nmos_de_iso_v20.OVL.11: Illegal nmos_de_iso_v20 device: nmos_de_iso_v20 must not overlap skip_pad" |
| and nmos_de_iso_v20 skip_pad |
| } |
| rule "nmos_de_iso_v20.OVL.12" { |
| caption "nmos_de_iso_v20.OVL.12: Illegal nmos_de_iso_v20 device: nmos_de_iso_v20 must not overlap fuse" |
| and nmos_de_iso_v20 fuse |
| } |
| rule "nmos_de_iso_v20.OVL.13" { |
| caption "nmos_de_iso_v20.OVL.13: Illegal nmos_de_iso_v20 device: nmos_de_iso_v20 must not overlap diff:res" |
| and nmos_de_iso_v20 diffres |
| } |
| rule "nmos_de_iso_v20.OVL.14" { |
| caption "nmos_de_iso_v20.OVL.14: Illegal nmos_de_iso_v20 device: nmos_de_iso_v20 must not overlap pwell:res" |
| and nmos_de_iso_v20 pwres |
| } |
| rule "nmos_de_iso_v20.OVL.15" { |
| caption "nmos_de_iso_v20.OVL.15: Illegal nmos_de_iso_v20 device: nmos_de_iso_v20 must not overlap poly:res" |
| and nmos_de_iso_v20 polyres |
| } |
| rule "nmos_de_iso_v20.OVL.16" { |
| caption "nmos_de_iso_v20.OVL.16: Illegal nmos_de_iso_v20 device: nmos_de_iso_v20 must not overlap li:res" |
| and nmos_de_iso_v20 lires |
| } |
| rule "nmos_de_iso_v20.OVL.17" { |
| caption "nmos_de_iso_v20.OVL.17: Illegal nmos_de_iso_v20 device: nmos_de_iso_v20 must not overlap skip_res" |
| and nmos_de_iso_v20 skip_res |
| } |
| rule "nmos_de_iso_v20.OVL.18" { |
| caption "nmos_de_iso_v20.OVL.18: Illegal nmos_de_iso_v20 device: nmos_de_iso_v20 must not overlap skip_res" |
| and nmos_de_iso_v20 skip_res |
| } |
| rule "nmos_de_iso_v20.OVL.19" { |
| caption "nmos_de_iso_v20.OVL.19: Illegal nmos_de_iso_v20 device: nmos_de_iso_v20 must not overlap skip_res" |
| and nmos_de_iso_v20 skip_res |
| } |
| rule "nmos_de_iso_v20.OVL.20" { |
| caption "nmos_de_iso_v20.OVL.20: Illegal nmos_de_iso_v20 device: nmos_de_iso_v20 must not overlap skip_res" |
| and nmos_de_iso_v20 skip_res |
| } |
| rule "nmos_de_iso_v20.OVL.21" { |
| caption "nmos_de_iso_v20.OVL.21: Illegal nmos_de_iso_v20 device: nmos_de_iso_v20 must not overlap skip_res" |
| and nmos_de_iso_v20 skip_res |
| } |
| rule "nmos_de_iso_v20.OVL.22" { |
| caption "nmos_de_iso_v20.OVL.22: Illegal nmos_de_iso_v20 device: nmos_de_iso_v20 must not overlap areaid:lvNative" |
| and nmos_de_iso_v20 LVID |
| } |
| rule "nmos_de_iso_v20.OVL.23" { |
| caption "nmos_de_iso_v20.OVL.23: Illegal nmos_de_iso_v20 device: nmos_de_iso_v20 must not overlap pnp" |
| and nmos_de_iso_v20 pnp |
| } |
| rule "nmos_de_iso_v20.OVL.24" { |
| caption "nmos_de_iso_v20.OVL.24: Illegal nmos_de_iso_v20 device: nmos_de_iso_v20 must not overlap npn" |
| and nmos_de_iso_v20 npn |
| } |
| rule "nmos_de_iso_v20.OVL.25" { |
| caption "nmos_de_iso_v20.OVL.25: Illegal nmos_de_iso_v20 device: nmos_de_iso_v20 must not overlap areaid:diode" |
| and nmos_de_iso_v20 DiodeID |
| } |
| rule "nmos_de_iso_v20.OVL.26" { |
| caption "nmos_de_iso_v20.OVL.26: Illegal nmos_de_iso_v20 device: nmos_de_iso_v20 must not overlap areaid:photo" |
| and nmos_de_iso_v20 PHdiodeID |
| } |
| rule "nmos_de_iso_v20.OVL.27" { |
| caption "nmos_de_iso_v20.OVL.27: Illegal nmos_de_iso_v20 device: nmos_de_iso_v20 must not overlap areaid:core" |
| and nmos_de_iso_v20 COREID |
| } |
| rule "nmos_de_iso_v20.OVL.28" { |
| caption "nmos_de_iso_v20.OVL.28: Illegal nmos_de_iso_v20 device: nmos_de_iso_v20 must not overlap areaid:esd" |
| and nmos_de_iso_v20 ESDID |
| } |
| rule "nmos_de_iso_v20.OVL.29" { |
| caption "nmos_de_iso_v20.OVL.29: Illegal nmos_de_iso_v20 device: nmos_de_iso_v20 must not overlap areaid:seal" |
| and nmos_de_iso_v20 SEALID |
| } |
| rule "nmos_de_iso_v20.OVL.30" { |
| caption "nmos_de_iso_v20.OVL.30: Illegal nmos_de_iso_v20 device: nmos_de_iso_v20 must not overlap v5" |
| and nmos_de_iso_v20 v5 |
| } |
| rule "nmos_de_iso_v20.OVL.31" { |
| caption "nmos_de_iso_v20.OVL.31: Illegal nmos_de_iso_v20 device: nmos_de_iso_v20 must not overlap v12" |
| and nmos_de_iso_v20 v12 |
| } |
| rule "nmos_de_iso_v20.OVL.32" { |
| caption "nmos_de_iso_v20.OVL.32: Illegal nmos_de_iso_v20 device: nmos_de_iso_v20 must not overlap poly:model" |
| and nmos_de_iso_v20 polyModel |
| } |
| not ( and ( select -enclose lvtn nsdm ) ngate_v20 ) pwbm -outputlayer nmos_de_nat_v20 |
| rule "nmos_de_nat_v20.OVL.1" { |
| caption "nmos_de_nat_v20.OVL.1: Illegal nmos_de_nat_v20 device: nmos_de_nat_v20 must not overlap pwde" |
| and nmos_de_nat_v20 pwde |
| } |
| rule "nmos_de_nat_v20.OVL.2" { |
| caption "nmos_de_nat_v20.OVL.2: Illegal nmos_de_nat_v20 device: nmos_de_nat_v20 must not overlap hvtp" |
| and nmos_de_nat_v20 hvtp |
| } |
| rule "nmos_de_nat_v20.OVL.3" { |
| caption "nmos_de_nat_v20.OVL.3: Illegal nmos_de_nat_v20 device: nmos_de_nat_v20 must not overlap tunm" |
| and nmos_de_nat_v20 tunm |
| } |
| rule "nmos_de_nat_v20.OVL.4" { |
| caption "nmos_de_nat_v20.OVL.4: Illegal nmos_de_nat_v20 device: nmos_de_nat_v20 must not overlap rpm" |
| and nmos_de_nat_v20 rpm |
| } |
| rule "nmos_de_nat_v20.OVL.5" { |
| caption "nmos_de_nat_v20.OVL.5: Illegal nmos_de_nat_v20 device: nmos_de_nat_v20 must not overlap rrpm" |
| and nmos_de_nat_v20 rrpm |
| } |
| rule "nmos_de_nat_v20.OVL.6" { |
| caption "nmos_de_nat_v20.OVL.6: Illegal nmos_de_nat_v20 device: nmos_de_nat_v20 must not overlap urpm" |
| and nmos_de_nat_v20 urpm |
| } |
| rule "nmos_de_nat_v20.OVL.7" { |
| caption "nmos_de_nat_v20.OVL.7: Illegal nmos_de_nat_v20 device: nmos_de_nat_v20 must not overlap ldntm" |
| and nmos_de_nat_v20 ldntm |
| } |
| rule "nmos_de_nat_v20.OVL.8" { |
| caption "nmos_de_nat_v20.OVL.8: Illegal nmos_de_nat_v20 device: nmos_de_nat_v20 must not overlap npc" |
| and nmos_de_nat_v20 npc |
| } |
| rule "nmos_de_nat_v20.OVL.9" { |
| caption "nmos_de_nat_v20.OVL.9: Illegal nmos_de_nat_v20 device: nmos_de_nat_v20 must not overlap psdm" |
| and nmos_de_nat_v20 psdm |
| } |
| rule "nmos_de_nat_v20.OVL.10" { |
| caption "nmos_de_nat_v20.OVL.10: Illegal nmos_de_nat_v20 device: nmos_de_nat_v20 must not overlap nsm" |
| and nmos_de_nat_v20 nsm |
| } |
| rule "nmos_de_nat_v20.OVL.11" { |
| caption "nmos_de_nat_v20.OVL.11: Illegal nmos_de_nat_v20 device: nmos_de_nat_v20 must not overlap skip_pad" |
| and nmos_de_nat_v20 skip_pad |
| } |
| rule "nmos_de_nat_v20.OVL.12" { |
| caption "nmos_de_nat_v20.OVL.12: Illegal nmos_de_nat_v20 device: nmos_de_nat_v20 must not overlap fuse" |
| and nmos_de_nat_v20 fuse |
| } |
| rule "nmos_de_nat_v20.OVL.13" { |
| caption "nmos_de_nat_v20.OVL.13: Illegal nmos_de_nat_v20 device: nmos_de_nat_v20 must not overlap diff:res" |
| and nmos_de_nat_v20 diffres |
| } |
| rule "nmos_de_nat_v20.OVL.14" { |
| caption "nmos_de_nat_v20.OVL.14: Illegal nmos_de_nat_v20 device: nmos_de_nat_v20 must not overlap pwell:res" |
| and nmos_de_nat_v20 pwres |
| } |
| rule "nmos_de_nat_v20.OVL.15" { |
| caption "nmos_de_nat_v20.OVL.15: Illegal nmos_de_nat_v20 device: nmos_de_nat_v20 must not overlap poly:res" |
| and nmos_de_nat_v20 polyres |
| } |
| rule "nmos_de_nat_v20.OVL.16" { |
| caption "nmos_de_nat_v20.OVL.16: Illegal nmos_de_nat_v20 device: nmos_de_nat_v20 must not overlap li:res" |
| and nmos_de_nat_v20 lires |
| } |
| rule "nmos_de_nat_v20.OVL.17" { |
| caption "nmos_de_nat_v20.OVL.17: Illegal nmos_de_nat_v20 device: nmos_de_nat_v20 must not overlap skip_res" |
| and nmos_de_nat_v20 skip_res |
| } |
| rule "nmos_de_nat_v20.OVL.18" { |
| caption "nmos_de_nat_v20.OVL.18: Illegal nmos_de_nat_v20 device: nmos_de_nat_v20 must not overlap skip_res" |
| and nmos_de_nat_v20 skip_res |
| } |
| rule "nmos_de_nat_v20.OVL.19" { |
| caption "nmos_de_nat_v20.OVL.19: Illegal nmos_de_nat_v20 device: nmos_de_nat_v20 must not overlap skip_res" |
| and nmos_de_nat_v20 skip_res |
| } |
| rule "nmos_de_nat_v20.OVL.20" { |
| caption "nmos_de_nat_v20.OVL.20: Illegal nmos_de_nat_v20 device: nmos_de_nat_v20 must not overlap skip_res" |
| and nmos_de_nat_v20 skip_res |
| } |
| rule "nmos_de_nat_v20.OVL.21" { |
| caption "nmos_de_nat_v20.OVL.21: Illegal nmos_de_nat_v20 device: nmos_de_nat_v20 must not overlap skip_res" |
| and nmos_de_nat_v20 skip_res |
| } |
| rule "nmos_de_nat_v20.OVL.22" { |
| caption "nmos_de_nat_v20.OVL.22: Illegal nmos_de_nat_v20 device: nmos_de_nat_v20 must not overlap areaid:lvNative" |
| and nmos_de_nat_v20 LVID |
| } |
| rule "nmos_de_nat_v20.OVL.23" { |
| caption "nmos_de_nat_v20.OVL.23: Illegal nmos_de_nat_v20 device: nmos_de_nat_v20 must not overlap pnp" |
| and nmos_de_nat_v20 pnp |
| } |
| rule "nmos_de_nat_v20.OVL.24" { |
| caption "nmos_de_nat_v20.OVL.24: Illegal nmos_de_nat_v20 device: nmos_de_nat_v20 must not overlap npn" |
| and nmos_de_nat_v20 npn |
| } |
| rule "nmos_de_nat_v20.OVL.25" { |
| caption "nmos_de_nat_v20.OVL.25: Illegal nmos_de_nat_v20 device: nmos_de_nat_v20 must not overlap areaid:diode" |
| and nmos_de_nat_v20 DiodeID |
| } |
| rule "nmos_de_nat_v20.OVL.26" { |
| caption "nmos_de_nat_v20.OVL.26: Illegal nmos_de_nat_v20 device: nmos_de_nat_v20 must not overlap areaid:photo" |
| and nmos_de_nat_v20 PHdiodeID |
| } |
| rule "nmos_de_nat_v20.OVL.27" { |
| caption "nmos_de_nat_v20.OVL.27: Illegal nmos_de_nat_v20 device: nmos_de_nat_v20 must not overlap areaid:core" |
| and nmos_de_nat_v20 COREID |
| } |
| rule "nmos_de_nat_v20.OVL.28" { |
| caption "nmos_de_nat_v20.OVL.28: Illegal nmos_de_nat_v20 device: nmos_de_nat_v20 must not overlap areaid:esd" |
| and nmos_de_nat_v20 ESDID |
| } |
| rule "nmos_de_nat_v20.OVL.29" { |
| caption "nmos_de_nat_v20.OVL.29: Illegal nmos_de_nat_v20 device: nmos_de_nat_v20 must not overlap areaid:seal" |
| and nmos_de_nat_v20 SEALID |
| } |
| rule "nmos_de_nat_v20.OVL.30" { |
| caption "nmos_de_nat_v20.OVL.30: Illegal nmos_de_nat_v20 device: nmos_de_nat_v20 must not overlap v5" |
| and nmos_de_nat_v20 v5 |
| } |
| rule "nmos_de_nat_v20.OVL.31" { |
| caption "nmos_de_nat_v20.OVL.31: Illegal nmos_de_nat_v20 device: nmos_de_nat_v20 must not overlap v12" |
| and nmos_de_nat_v20 v12 |
| } |
| rule "nmos_de_nat_v20.OVL.32" { |
| caption "nmos_de_nat_v20.OVL.32: Illegal nmos_de_nat_v20 device: nmos_de_nat_v20 must not overlap poly:model" |
| and nmos_de_nat_v20 polyModel |
| } |
| not ( and ( not ( select -cut lvtn nsdm ) ( select -enclose lvtn nsdm ) ) ngate_v20 ) ( or ngate_v20_iso_rec ngate_v20_nat ) -outputlayer nmos_de_zvt_v20 |
| rule "nmos_de_zvt_v20.OVL.1" { |
| caption "nmos_de_zvt_v20.OVL.1: Illegal nmos_de_zvt_v20 device: nmos_de_zvt_v20 must not overlap pwde" |
| and nmos_de_zvt_v20 pwde |
| } |
| rule "nmos_de_zvt_v20.OVL.2" { |
| caption "nmos_de_zvt_v20.OVL.2: Illegal nmos_de_zvt_v20 device: nmos_de_zvt_v20 must not overlap hvtp" |
| and nmos_de_zvt_v20 hvtp |
| } |
| rule "nmos_de_zvt_v20.OVL.3" { |
| caption "nmos_de_zvt_v20.OVL.3: Illegal nmos_de_zvt_v20 device: nmos_de_zvt_v20 must not overlap tunm" |
| and nmos_de_zvt_v20 tunm |
| } |
| rule "nmos_de_zvt_v20.OVL.4" { |
| caption "nmos_de_zvt_v20.OVL.4: Illegal nmos_de_zvt_v20 device: nmos_de_zvt_v20 must not overlap rpm" |
| and nmos_de_zvt_v20 rpm |
| } |
| rule "nmos_de_zvt_v20.OVL.5" { |
| caption "nmos_de_zvt_v20.OVL.5: Illegal nmos_de_zvt_v20 device: nmos_de_zvt_v20 must not overlap rrpm" |
| and nmos_de_zvt_v20 rrpm |
| } |
| rule "nmos_de_zvt_v20.OVL.6" { |
| caption "nmos_de_zvt_v20.OVL.6: Illegal nmos_de_zvt_v20 device: nmos_de_zvt_v20 must not overlap urpm" |
| and nmos_de_zvt_v20 urpm |
| } |
| rule "nmos_de_zvt_v20.OVL.7" { |
| caption "nmos_de_zvt_v20.OVL.7: Illegal nmos_de_zvt_v20 device: nmos_de_zvt_v20 must not overlap ldntm" |
| and nmos_de_zvt_v20 ldntm |
| } |
| rule "nmos_de_zvt_v20.OVL.8" { |
| caption "nmos_de_zvt_v20.OVL.8: Illegal nmos_de_zvt_v20 device: nmos_de_zvt_v20 must not overlap npc" |
| and nmos_de_zvt_v20 npc |
| } |
| rule "nmos_de_zvt_v20.OVL.9" { |
| caption "nmos_de_zvt_v20.OVL.9: Illegal nmos_de_zvt_v20 device: nmos_de_zvt_v20 must not overlap psdm" |
| and nmos_de_zvt_v20 psdm |
| } |
| rule "nmos_de_zvt_v20.OVL.10" { |
| caption "nmos_de_zvt_v20.OVL.10: Illegal nmos_de_zvt_v20 device: nmos_de_zvt_v20 must not overlap nsm" |
| and nmos_de_zvt_v20 nsm |
| } |
| rule "nmos_de_zvt_v20.OVL.11" { |
| caption "nmos_de_zvt_v20.OVL.11: Illegal nmos_de_zvt_v20 device: nmos_de_zvt_v20 must not overlap skip_pad" |
| and nmos_de_zvt_v20 skip_pad |
| } |
| rule "nmos_de_zvt_v20.OVL.12" { |
| caption "nmos_de_zvt_v20.OVL.12: Illegal nmos_de_zvt_v20 device: nmos_de_zvt_v20 must not overlap fuse" |
| and nmos_de_zvt_v20 fuse |
| } |
| rule "nmos_de_zvt_v20.OVL.13" { |
| caption "nmos_de_zvt_v20.OVL.13: Illegal nmos_de_zvt_v20 device: nmos_de_zvt_v20 must not overlap diff:res" |
| and nmos_de_zvt_v20 diffres |
| } |
| rule "nmos_de_zvt_v20.OVL.14" { |
| caption "nmos_de_zvt_v20.OVL.14: Illegal nmos_de_zvt_v20 device: nmos_de_zvt_v20 must not overlap pwell:res" |
| and nmos_de_zvt_v20 pwres |
| } |
| rule "nmos_de_zvt_v20.OVL.15" { |
| caption "nmos_de_zvt_v20.OVL.15: Illegal nmos_de_zvt_v20 device: nmos_de_zvt_v20 must not overlap poly:res" |
| and nmos_de_zvt_v20 polyres |
| } |
| rule "nmos_de_zvt_v20.OVL.16" { |
| caption "nmos_de_zvt_v20.OVL.16: Illegal nmos_de_zvt_v20 device: nmos_de_zvt_v20 must not overlap li:res" |
| and nmos_de_zvt_v20 lires |
| } |
| rule "nmos_de_zvt_v20.OVL.17" { |
| caption "nmos_de_zvt_v20.OVL.17: Illegal nmos_de_zvt_v20 device: nmos_de_zvt_v20 must not overlap skip_res" |
| and nmos_de_zvt_v20 skip_res |
| } |
| rule "nmos_de_zvt_v20.OVL.18" { |
| caption "nmos_de_zvt_v20.OVL.18: Illegal nmos_de_zvt_v20 device: nmos_de_zvt_v20 must not overlap skip_res" |
| and nmos_de_zvt_v20 skip_res |
| } |
| rule "nmos_de_zvt_v20.OVL.19" { |
| caption "nmos_de_zvt_v20.OVL.19: Illegal nmos_de_zvt_v20 device: nmos_de_zvt_v20 must not overlap skip_res" |
| and nmos_de_zvt_v20 skip_res |
| } |
| rule "nmos_de_zvt_v20.OVL.20" { |
| caption "nmos_de_zvt_v20.OVL.20: Illegal nmos_de_zvt_v20 device: nmos_de_zvt_v20 must not overlap skip_res" |
| and nmos_de_zvt_v20 skip_res |
| } |
| rule "nmos_de_zvt_v20.OVL.21" { |
| caption "nmos_de_zvt_v20.OVL.21: Illegal nmos_de_zvt_v20 device: nmos_de_zvt_v20 must not overlap skip_res" |
| and nmos_de_zvt_v20 skip_res |
| } |
| rule "nmos_de_zvt_v20.OVL.22" { |
| caption "nmos_de_zvt_v20.OVL.22: Illegal nmos_de_zvt_v20 device: nmos_de_zvt_v20 must not overlap areaid:lvNative" |
| and nmos_de_zvt_v20 LVID |
| } |
| rule "nmos_de_zvt_v20.OVL.23" { |
| caption "nmos_de_zvt_v20.OVL.23: Illegal nmos_de_zvt_v20 device: nmos_de_zvt_v20 must not overlap pnp" |
| and nmos_de_zvt_v20 pnp |
| } |
| rule "nmos_de_zvt_v20.OVL.24" { |
| caption "nmos_de_zvt_v20.OVL.24: Illegal nmos_de_zvt_v20 device: nmos_de_zvt_v20 must not overlap npn" |
| and nmos_de_zvt_v20 npn |
| } |
| rule "nmos_de_zvt_v20.OVL.25" { |
| caption "nmos_de_zvt_v20.OVL.25: Illegal nmos_de_zvt_v20 device: nmos_de_zvt_v20 must not overlap areaid:diode" |
| and nmos_de_zvt_v20 DiodeID |
| } |
| rule "nmos_de_zvt_v20.OVL.26" { |
| caption "nmos_de_zvt_v20.OVL.26: Illegal nmos_de_zvt_v20 device: nmos_de_zvt_v20 must not overlap areaid:photo" |
| and nmos_de_zvt_v20 PHdiodeID |
| } |
| rule "nmos_de_zvt_v20.OVL.27" { |
| caption "nmos_de_zvt_v20.OVL.27: Illegal nmos_de_zvt_v20 device: nmos_de_zvt_v20 must not overlap areaid:core" |
| and nmos_de_zvt_v20 COREID |
| } |
| rule "nmos_de_zvt_v20.OVL.28" { |
| caption "nmos_de_zvt_v20.OVL.28: Illegal nmos_de_zvt_v20 device: nmos_de_zvt_v20 must not overlap areaid:esd" |
| and nmos_de_zvt_v20 ESDID |
| } |
| rule "nmos_de_zvt_v20.OVL.29" { |
| caption "nmos_de_zvt_v20.OVL.29: Illegal nmos_de_zvt_v20 device: nmos_de_zvt_v20 must not overlap areaid:seal" |
| and nmos_de_zvt_v20 SEALID |
| } |
| rule "nmos_de_zvt_v20.OVL.30" { |
| caption "nmos_de_zvt_v20.OVL.30: Illegal nmos_de_zvt_v20 device: nmos_de_zvt_v20 must not overlap v5" |
| and nmos_de_zvt_v20 v5 |
| } |
| rule "nmos_de_zvt_v20.OVL.31" { |
| caption "nmos_de_zvt_v20.OVL.31: Illegal nmos_de_zvt_v20 device: nmos_de_zvt_v20 must not overlap v12" |
| and nmos_de_zvt_v20 v12 |
| } |
| rule "nmos_de_zvt_v20.OVL.32" { |
| caption "nmos_de_zvt_v20.OVL.32: Illegal nmos_de_zvt_v20 device: nmos_de_zvt_v20 must not overlap poly:model" |
| and nmos_de_zvt_v20 polyModel |
| } |
| |
| |
| // PMOS: |
| |
| |
| |
| not ( and ( and mos_diff polyi ) nwell ) ENID -outputlayer pmos_gate |
| not ( select -interact diffi pmos_gate ) pmos_gate -outputlayer pmos_sd |
| select -touch pmos_gate pmos_sd -eq 2 -outputlayer pmos_1 |
| not ( not pmos_1 thkox ) lvtn -outputlayer pmos |
| rule "pmos.OVL.1" { |
| caption "pmos.OVL.1: Illegal low voltage pmos device: pmos must not overlap pwbm" |
| and pmos pwbm |
| } |
| rule "pmos.OVL.2" { |
| caption "pmos.OVL.2: Illegal low voltage pmos device: pmos must not overlap pwde" |
| and pmos pwde |
| } |
| rule "pmos.OVL.3" { |
| caption "pmos.OVL.3: Illegal low voltage pmos device: pmos must not overlap lvtn" |
| and pmos lvtn |
| } |
| rule "pmos.OVL.4" { |
| caption "pmos.OVL.4: Illegal low voltage pmos device: pmos must not overlap tunm" |
| and pmos tunm |
| } |
| rule "pmos.OVL.5" { |
| caption "pmos.OVL.5: Illegal low voltage pmos device: pmos must not overlap thkox" |
| and pmos thkox |
| } |
| rule "pmos.OVL.6" { |
| caption "pmos.OVL.6: Illegal low voltage pmos device: pmos must not overlap rpm" |
| and pmos rpm |
| } |
| rule "pmos.OVL.7" { |
| caption "pmos.OVL.7: Illegal low voltage pmos device: pmos must not overlap rrpm" |
| and pmos rrpm |
| } |
| rule "pmos.OVL.8" { |
| caption "pmos.OVL.8: Illegal low voltage pmos device: pmos must not overlap urpm" |
| and pmos urpm |
| } |
| rule "pmos.OVL.9" { |
| caption "pmos.OVL.9: Illegal low voltage pmos device: pmos must not overlap ldntm" |
| and pmos ldntm |
| } |
| rule "pmos.OVL.10" { |
| caption "pmos.OVL.10: Illegal low voltage pmos device: pmos must not overlap npc" |
| and pmos npc |
| } |
| rule "pmos.OVL.11" { |
| caption "pmos.OVL.11: Illegal low voltage pmos device: pmos must not overlap nsdm" |
| and pmos nsdm |
| } |
| rule "pmos.OVL.12" { |
| caption "pmos.OVL.12: Illegal low voltage pmos device: pmos must not overlap nsm" |
| and pmos nsm |
| } |
| rule "pmos.OVL.13" { |
| caption "pmos.OVL.13: Illegal low voltage pmos device: pmos must not overlap skip_pad" |
| and pmos skip_pad |
| } |
| rule "pmos.OVL.14" { |
| caption "pmos.OVL.14: Illegal low voltage pmos device: pmos must not overlap fuse" |
| and pmos fuse |
| } |
| rule "pmos.OVL.15" { |
| caption "pmos.OVL.15: Illegal low voltage pmos device: pmos must not overlap diff:res" |
| and pmos diffres |
| } |
| rule "pmos.OVL.16" { |
| caption "pmos.OVL.16: Illegal low voltage pmos device: pmos must not overlap pwell:res" |
| and pmos pwres |
| } |
| rule "pmos.OVL.17" { |
| caption "pmos.OVL.17: Illegal low voltage pmos device: pmos must not overlap poly:res" |
| and pmos polyres |
| } |
| rule "pmos.OVL.18" { |
| caption "pmos.OVL.18: Illegal low voltage pmos device: pmos must not overlap li:res" |
| and pmos lires |
| } |
| rule "pmos.OVL.19" { |
| caption "pmos.OVL.19: Illegal low voltage pmos device: pmos must not overlap skip_res" |
| and pmos skip_res |
| } |
| rule "pmos.OVL.20" { |
| caption "pmos.OVL.20: Illegal low voltage pmos device: pmos must not overlap skip_res" |
| and pmos skip_res |
| } |
| rule "pmos.OVL.21" { |
| caption "pmos.OVL.21: Illegal low voltage pmos device: pmos must not overlap skip_res" |
| and pmos skip_res |
| } |
| rule "pmos.OVL.22" { |
| caption "pmos.OVL.22: Illegal low voltage pmos device: pmos must not overlap skip_res" |
| and pmos skip_res |
| } |
| rule "pmos.OVL.23" { |
| caption "pmos.OVL.23: Illegal low voltage pmos device: pmos must not overlap skip_res" |
| and pmos skip_res |
| } |
| rule "pmos.OVL.24" { |
| caption "pmos.OVL.24: Illegal low voltage pmos device: pmos must not overlap areaid:lvNative" |
| and pmos LVID |
| } |
| rule "pmos.OVL.25" { |
| caption "pmos.OVL.25: Illegal low voltage pmos device: pmos must not overlap pnp" |
| and pmos pnp |
| } |
| rule "pmos.OVL.26" { |
| caption "pmos.OVL.26: Illegal low voltage pmos device: pmos must not overlap npn" |
| and pmos npn |
| } |
| rule "pmos.OVL.27" { |
| caption "pmos.OVL.27: Illegal low voltage pmos device: pmos must not overlap areaid:diode" |
| and pmos DiodeID |
| } |
| rule "pmos.OVL.28" { |
| caption "pmos.OVL.28: Illegal low voltage pmos device: pmos must not overlap areaid:photo" |
| and pmos PHdiodeID |
| } |
| rule "pmos.OVL.29" { |
| caption "pmos.OVL.29: Illegal low voltage pmos device: pmos must not overlap areaid:core" |
| and pmos COREID |
| } |
| rule "pmos.OVL.30" { |
| caption "pmos.OVL.30: Illegal low voltage pmos device: pmos must not overlap areaid:seal" |
| and pmos SEALID |
| } |
| rule "pmos.OVL.31" { |
| caption "pmos.OVL.31: Illegal low voltage pmos device: pmos must not overlap v5" |
| and pmos v5 |
| } |
| rule "pmos.OVL.32" { |
| caption "pmos.OVL.32: Illegal low voltage pmos device: pmos must not overlap v12" |
| and pmos v12 |
| } |
| rule "pmos.OVL.33" { |
| caption "pmos.OVL.33: Illegal low voltage pmos device: pmos must not overlap v20" |
| and pmos v20 |
| } |
| rule "pmos.OVL.34" { |
| caption "pmos.OVL.34: Illegal low voltage pmos device: pmos must not overlap areaid:extendedDrain" |
| and pmos ENID |
| } |
| rule "pmos.OVL.35" { |
| caption "pmos.OVL.35: Illegal low voltage pmos device: pmos must not overlap poly:model" |
| and pmos polyModel |
| } |
| and pmos_1 lvtn -outputlayer pmos_lvt |
| rule "pmos_lvt.OVL.1" { |
| caption "pmos_lvt.OVL.1: Illegal pmos_lvt device: pmos_lvt must not overlap pwbm" |
| and pmos_lvt pwbm |
| } |
| rule "pmos_lvt.OVL.2" { |
| caption "pmos_lvt.OVL.2: Illegal pmos_lvt device: pmos_lvt must not overlap pwde" |
| and pmos_lvt pwde |
| } |
| rule "pmos_lvt.OVL.3" { |
| caption "pmos_lvt.OVL.3: Illegal pmos_lvt device: pmos_lvt must not overlap tunm" |
| and pmos_lvt tunm |
| } |
| rule "pmos_lvt.OVL.4" { |
| caption "pmos_lvt.OVL.4: Illegal pmos_lvt device: pmos_lvt must not overlap thkox" |
| and pmos_lvt thkox |
| } |
| rule "pmos_lvt.OVL.5" { |
| caption "pmos_lvt.OVL.5: Illegal pmos_lvt device: pmos_lvt must not overlap rpm" |
| and pmos_lvt rpm |
| } |
| rule "pmos_lvt.OVL.6" { |
| caption "pmos_lvt.OVL.6: Illegal pmos_lvt device: pmos_lvt must not overlap rrpm" |
| and pmos_lvt rrpm |
| } |
| rule "pmos_lvt.OVL.7" { |
| caption "pmos_lvt.OVL.7: Illegal pmos_lvt device: pmos_lvt must not overlap urpm" |
| and pmos_lvt urpm |
| } |
| rule "pmos_lvt.OVL.8" { |
| caption "pmos_lvt.OVL.8: Illegal pmos_lvt device: pmos_lvt must not overlap ldntm" |
| and pmos_lvt ldntm |
| } |
| rule "pmos_lvt.OVL.9" { |
| caption "pmos_lvt.OVL.9: Illegal pmos_lvt device: pmos_lvt must not overlap npc" |
| and pmos_lvt npc |
| } |
| rule "pmos_lvt.OVL.10" { |
| caption "pmos_lvt.OVL.10: Illegal pmos_lvt device: pmos_lvt must not overlap nsdm" |
| and pmos_lvt nsdm |
| } |
| rule "pmos_lvt.OVL.11" { |
| caption "pmos_lvt.OVL.11: Illegal pmos_lvt device: pmos_lvt must not overlap nsm" |
| and pmos_lvt nsm |
| } |
| rule "pmos_lvt.OVL.12" { |
| caption "pmos_lvt.OVL.12: Illegal pmos_lvt device: pmos_lvt must not overlap skip_pad" |
| and pmos_lvt skip_pad |
| } |
| rule "pmos_lvt.OVL.13" { |
| caption "pmos_lvt.OVL.13: Illegal pmos_lvt device: pmos_lvt must not overlap fuse" |
| and pmos_lvt fuse |
| } |
| rule "pmos_lvt.OVL.14" { |
| caption "pmos_lvt.OVL.14: Illegal pmos_lvt device: pmos_lvt must not overlap diff:res" |
| and pmos_lvt diffres |
| } |
| rule "pmos_lvt.OVL.15" { |
| caption "pmos_lvt.OVL.15: Illegal pmos_lvt device: pmos_lvt must not overlap pwell:res" |
| and pmos_lvt pwres |
| } |
| rule "pmos_lvt.OVL.16" { |
| caption "pmos_lvt.OVL.16: Illegal pmos_lvt device: pmos_lvt must not overlap poly:res" |
| and pmos_lvt polyres |
| } |
| rule "pmos_lvt.OVL.17" { |
| caption "pmos_lvt.OVL.17: Illegal pmos_lvt device: pmos_lvt must not overlap li:res" |
| and pmos_lvt lires |
| } |
| rule "pmos_lvt.OVL.18" { |
| caption "pmos_lvt.OVL.18: Illegal pmos_lvt device: pmos_lvt must not overlap skip_res" |
| and pmos_lvt skip_res |
| } |
| rule "pmos_lvt.OVL.19" { |
| caption "pmos_lvt.OVL.19: Illegal pmos_lvt device: pmos_lvt must not overlap skip_res" |
| and pmos_lvt skip_res |
| } |
| rule "pmos_lvt.OVL.20" { |
| caption "pmos_lvt.OVL.20: Illegal pmos_lvt device: pmos_lvt must not overlap skip_res" |
| and pmos_lvt skip_res |
| } |
| rule "pmos_lvt.OVL.21" { |
| caption "pmos_lvt.OVL.21: Illegal pmos_lvt device: pmos_lvt must not overlap skip_res" |
| and pmos_lvt skip_res |
| } |
| rule "pmos_lvt.OVL.22" { |
| caption "pmos_lvt.OVL.22: Illegal pmos_lvt device: pmos_lvt must not overlap skip_res" |
| and pmos_lvt skip_res |
| } |
| rule "pmos_lvt.OVL.23" { |
| caption "pmos_lvt.OVL.23: Illegal pmos_lvt device: pmos_lvt must not overlap areaid:lvNative" |
| and pmos_lvt LVID |
| } |
| rule "pmos_lvt.OVL.24" { |
| caption "pmos_lvt.OVL.24: Illegal pmos_lvt device: pmos_lvt must not overlap pnp" |
| and pmos_lvt pnp |
| } |
| rule "pmos_lvt.OVL.25" { |
| caption "pmos_lvt.OVL.25: Illegal pmos_lvt device: pmos_lvt must not overlap npn" |
| and pmos_lvt npn |
| } |
| rule "pmos_lvt.OVL.26" { |
| caption "pmos_lvt.OVL.26: Illegal pmos_lvt device: pmos_lvt must not overlap areaid:diode" |
| and pmos_lvt DiodeID |
| } |
| rule "pmos_lvt.OVL.27" { |
| caption "pmos_lvt.OVL.27: Illegal pmos_lvt device: pmos_lvt must not overlap areaid:photo" |
| and pmos_lvt PHdiodeID |
| } |
| rule "pmos_lvt.OVL.28" { |
| caption "pmos_lvt.OVL.28: Illegal pmos_lvt device: pmos_lvt must not overlap areaid:core" |
| and pmos_lvt COREID |
| } |
| rule "pmos_lvt.OVL.29" { |
| caption "pmos_lvt.OVL.29: Illegal pmos_lvt device: pmos_lvt must not overlap areaid:esd" |
| and pmos_lvt ESDID |
| } |
| rule "pmos_lvt.OVL.30" { |
| caption "pmos_lvt.OVL.30: Illegal pmos_lvt device: pmos_lvt must not overlap areaid:seal" |
| and pmos_lvt SEALID |
| } |
| rule "pmos_lvt.OVL.31" { |
| caption "pmos_lvt.OVL.31: Illegal pmos_lvt device: pmos_lvt must not overlap v5" |
| and pmos_lvt v5 |
| } |
| rule "pmos_lvt.OVL.32" { |
| caption "pmos_lvt.OVL.32: Illegal pmos_lvt device: pmos_lvt must not overlap v12" |
| and pmos_lvt v12 |
| } |
| rule "pmos_lvt.OVL.33" { |
| caption "pmos_lvt.OVL.33: Illegal pmos_lvt device: pmos_lvt must not overlap v20" |
| and pmos_lvt v20 |
| } |
| rule "pmos_lvt.OVL.34" { |
| caption "pmos_lvt.OVL.34: Illegal pmos_lvt device: pmos_lvt must not overlap hvtp" |
| and pmos_lvt hvtp |
| } |
| rule "pmos_lvt.OVL.35" { |
| caption "pmos_lvt.OVL.35: Illegal pmos_lvt device: pmos_lvt must not overlap areaid:extendedDrain" |
| and pmos_lvt ENID |
| } |
| rule "pmos_lvt.OVL.36" { |
| caption "pmos_lvt.OVL.36: Illegal pmos_lvt device: pmos_lvt must not overlap poly:model" |
| and pmos_lvt polyModel |
| } |
| and pmos_1 hvtp -outputlayer pmos_hvt |
| rule "pmos_hvt.OVL.1" { |
| caption "pmos_hvt.OVL.1: Illegal pmos_hvt device: pmos_hvt must not overlap pwbm" |
| and pmos_hvt pwbm |
| } |
| rule "pmos_hvt.OVL.2" { |
| caption "pmos_hvt.OVL.2: Illegal pmos_hvt device: pmos_hvt must not overlap pwde" |
| and pmos_hvt pwde |
| } |
| rule "pmos_hvt.OVL.3" { |
| caption "pmos_hvt.OVL.3: Illegal pmos_hvt device: pmos_hvt must not overlap tunm" |
| and pmos_hvt tunm |
| } |
| rule "pmos_hvt.OVL.4" { |
| caption "pmos_hvt.OVL.4: Illegal pmos_hvt device: pmos_hvt must not overlap thkox" |
| and pmos_hvt thkox |
| } |
| rule "pmos_hvt.OVL.5" { |
| caption "pmos_hvt.OVL.5: Illegal pmos_hvt device: pmos_hvt must not overlap rpm" |
| and pmos_hvt rpm |
| } |
| rule "pmos_hvt.OVL.6" { |
| caption "pmos_hvt.OVL.6: Illegal pmos_hvt device: pmos_hvt must not overlap rrpm" |
| and pmos_hvt rrpm |
| } |
| rule "pmos_hvt.OVL.7" { |
| caption "pmos_hvt.OVL.7: Illegal pmos_hvt device: pmos_hvt must not overlap urpm" |
| and pmos_hvt urpm |
| } |
| rule "pmos_hvt.OVL.8" { |
| caption "pmos_hvt.OVL.8: Illegal pmos_hvt device: pmos_hvt must not overlap ldntm" |
| and pmos_hvt ldntm |
| } |
| rule "pmos_hvt.OVL.9" { |
| caption "pmos_hvt.OVL.9: Illegal pmos_hvt device: pmos_hvt must not overlap npc" |
| and pmos_hvt npc |
| } |
| rule "pmos_hvt.OVL.10" { |
| caption "pmos_hvt.OVL.10: Illegal pmos_hvt device: pmos_hvt must not overlap nsdm" |
| and pmos_hvt nsdm |
| } |
| rule "pmos_hvt.OVL.11" { |
| caption "pmos_hvt.OVL.11: Illegal pmos_hvt device: pmos_hvt must not overlap nsm" |
| and pmos_hvt nsm |
| } |
| rule "pmos_hvt.OVL.12" { |
| caption "pmos_hvt.OVL.12: Illegal pmos_hvt device: pmos_hvt must not overlap skip_pad" |
| and pmos_hvt skip_pad |
| } |
| rule "pmos_hvt.OVL.13" { |
| caption "pmos_hvt.OVL.13: Illegal pmos_hvt device: pmos_hvt must not overlap fuse" |
| and pmos_hvt fuse |
| } |
| rule "pmos_hvt.OVL.14" { |
| caption "pmos_hvt.OVL.14: Illegal pmos_hvt device: pmos_hvt must not overlap diff:res" |
| and pmos_hvt diffres |
| } |
| rule "pmos_hvt.OVL.15" { |
| caption "pmos_hvt.OVL.15: Illegal pmos_hvt device: pmos_hvt must not overlap pwell:res" |
| and pmos_hvt pwres |
| } |
| rule "pmos_hvt.OVL.16" { |
| caption "pmos_hvt.OVL.16: Illegal pmos_hvt device: pmos_hvt must not overlap poly:res" |
| and pmos_hvt polyres |
| } |
| rule "pmos_hvt.OVL.17" { |
| caption "pmos_hvt.OVL.17: Illegal pmos_hvt device: pmos_hvt must not overlap li:res" |
| and pmos_hvt lires |
| } |
| rule "pmos_hvt.OVL.18" { |
| caption "pmos_hvt.OVL.18: Illegal pmos_hvt device: pmos_hvt must not overlap skip_res" |
| and pmos_hvt skip_res |
| } |
| rule "pmos_hvt.OVL.19" { |
| caption "pmos_hvt.OVL.19: Illegal pmos_hvt device: pmos_hvt must not overlap skip_res" |
| and pmos_hvt skip_res |
| } |
| rule "pmos_hvt.OVL.20" { |
| caption "pmos_hvt.OVL.20: Illegal pmos_hvt device: pmos_hvt must not overlap skip_res" |
| and pmos_hvt skip_res |
| } |
| rule "pmos_hvt.OVL.21" { |
| caption "pmos_hvt.OVL.21: Illegal pmos_hvt device: pmos_hvt must not overlap skip_res" |
| and pmos_hvt skip_res |
| } |
| rule "pmos_hvt.OVL.22" { |
| caption "pmos_hvt.OVL.22: Illegal pmos_hvt device: pmos_hvt must not overlap skip_res" |
| and pmos_hvt skip_res |
| } |
| rule "pmos_hvt.OVL.23" { |
| caption "pmos_hvt.OVL.23: Illegal pmos_hvt device: pmos_hvt must not overlap areaid:lvNative" |
| and pmos_hvt LVID |
| } |
| rule "pmos_hvt.OVL.24" { |
| caption "pmos_hvt.OVL.24: Illegal pmos_hvt device: pmos_hvt must not overlap pnp" |
| and pmos_hvt pnp |
| } |
| rule "pmos_hvt.OVL.25" { |
| caption "pmos_hvt.OVL.25: Illegal pmos_hvt device: pmos_hvt must not overlap npn" |
| and pmos_hvt npn |
| } |
| rule "pmos_hvt.OVL.26" { |
| caption "pmos_hvt.OVL.26: Illegal pmos_hvt device: pmos_hvt must not overlap areaid:diode" |
| and pmos_hvt DiodeID |
| } |
| rule "pmos_hvt.OVL.27" { |
| caption "pmos_hvt.OVL.27: Illegal pmos_hvt device: pmos_hvt must not overlap areaid:photo" |
| and pmos_hvt PHdiodeID |
| } |
| rule "pmos_hvt.OVL.28" { |
| caption "pmos_hvt.OVL.28: Illegal pmos_hvt device: pmos_hvt must not overlap areaid:core" |
| and pmos_hvt COREID |
| } |
| rule "pmos_hvt.OVL.29" { |
| caption "pmos_hvt.OVL.29: Illegal pmos_hvt device: pmos_hvt must not overlap areaid:esd" |
| and pmos_hvt ESDID |
| } |
| rule "pmos_hvt.OVL.30" { |
| caption "pmos_hvt.OVL.30: Illegal pmos_hvt device: pmos_hvt must not overlap areaid:seal" |
| and pmos_hvt SEALID |
| } |
| rule "pmos_hvt.OVL.31" { |
| caption "pmos_hvt.OVL.31: Illegal pmos_hvt device: pmos_hvt must not overlap v5" |
| and pmos_hvt v5 |
| } |
| rule "pmos_hvt.OVL.32" { |
| caption "pmos_hvt.OVL.32: Illegal pmos_hvt device: pmos_hvt must not overlap v12" |
| and pmos_hvt v12 |
| } |
| rule "pmos_hvt.OVL.33" { |
| caption "pmos_hvt.OVL.33: Illegal pmos_hvt device: pmos_hvt must not overlap v20" |
| and pmos_hvt v20 |
| } |
| rule "pmos_hvt.OVL.34" { |
| caption "pmos_hvt.OVL.34: Illegal pmos_hvt device: pmos_hvt must not overlap areaid:extendedDrain" |
| and pmos_hvt ENID |
| } |
| rule "pmos_hvt.OVL.35" { |
| caption "pmos_hvt.OVL.35: Illegal pmos_hvt device: pmos_hvt must not overlap poly:model" |
| and pmos_hvt polyModel |
| } |
| not ( and ( and pmos_1 v5 ) thkox ) ESDID -outputlayer pmos_v5 |
| rule "pmos_v5.OVL.1" { |
| caption "pmos_v5.OVL.1: Illegal pmos_v5 device: pmos_v5 must not overlap pwbm" |
| and pmos_v5 pwbm |
| } |
| rule "pmos_v5.OVL.2" { |
| caption "pmos_v5.OVL.2: Illegal pmos_v5 device: pmos_v5 must not overlap pwde" |
| and pmos_v5 pwde |
| } |
| rule "pmos_v5.OVL.3" { |
| caption "pmos_v5.OVL.3: Illegal pmos_v5 device: pmos_v5 must not overlap hvtp" |
| and pmos_v5 hvtp |
| } |
| rule "pmos_v5.OVL.4" { |
| caption "pmos_v5.OVL.4: Illegal pmos_v5 device: pmos_v5 must not overlap lvtn" |
| and pmos_v5 lvtn |
| } |
| rule "pmos_v5.OVL.5" { |
| caption "pmos_v5.OVL.5: Illegal pmos_v5 device: pmos_v5 must not overlap tunm" |
| and pmos_v5 tunm |
| } |
| rule "pmos_v5.OVL.6" { |
| caption "pmos_v5.OVL.6: Illegal pmos_v5 device: pmos_v5 must not overlap rpm" |
| and pmos_v5 rpm |
| } |
| rule "pmos_v5.OVL.7" { |
| caption "pmos_v5.OVL.7: Illegal pmos_v5 device: pmos_v5 must not overlap rrpm" |
| and pmos_v5 rrpm |
| } |
| rule "pmos_v5.OVL.8" { |
| caption "pmos_v5.OVL.8: Illegal pmos_v5 device: pmos_v5 must not overlap urpm" |
| and pmos_v5 urpm |
| } |
| rule "pmos_v5.OVL.9" { |
| caption "pmos_v5.OVL.9: Illegal pmos_v5 device: pmos_v5 must not overlap ldntm" |
| and pmos_v5 ldntm |
| } |
| rule "pmos_v5.OVL.10" { |
| caption "pmos_v5.OVL.10: Illegal pmos_v5 device: pmos_v5 must not overlap npc" |
| and pmos_v5 npc |
| } |
| rule "pmos_v5.OVL.11" { |
| caption "pmos_v5.OVL.11: Illegal pmos_v5 device: pmos_v5 must not overlap nsdm" |
| and pmos_v5 nsdm |
| } |
| rule "pmos_v5.OVL.12" { |
| caption "pmos_v5.OVL.12: Illegal pmos_v5 device: pmos_v5 must not overlap nsm" |
| and pmos_v5 nsm |
| } |
| rule "pmos_v5.OVL.13" { |
| caption "pmos_v5.OVL.13: Illegal pmos_v5 device: pmos_v5 must not overlap skip_pad" |
| and pmos_v5 skip_pad |
| } |
| rule "pmos_v5.OVL.14" { |
| caption "pmos_v5.OVL.14: Illegal pmos_v5 device: pmos_v5 must not overlap fuse" |
| and pmos_v5 fuse |
| } |
| rule "pmos_v5.OVL.15" { |
| caption "pmos_v5.OVL.15: Illegal pmos_v5 device: pmos_v5 must not overlap diff:res" |
| and pmos_v5 diffres |
| } |
| rule "pmos_v5.OVL.16" { |
| caption "pmos_v5.OVL.16: Illegal pmos_v5 device: pmos_v5 must not overlap pwell:res" |
| and pmos_v5 pwres |
| } |
| rule "pmos_v5.OVL.17" { |
| caption "pmos_v5.OVL.17: Illegal pmos_v5 device: pmos_v5 must not overlap poly:res" |
| and pmos_v5 polyres |
| } |
| rule "pmos_v5.OVL.18" { |
| caption "pmos_v5.OVL.18: Illegal pmos_v5 device: pmos_v5 must not overlap li:res" |
| and pmos_v5 lires |
| } |
| rule "pmos_v5.OVL.19" { |
| caption "pmos_v5.OVL.19: Illegal pmos_v5 device: pmos_v5 must not overlap skip_res" |
| and pmos_v5 skip_res |
| } |
| rule "pmos_v5.OVL.20" { |
| caption "pmos_v5.OVL.20: Illegal pmos_v5 device: pmos_v5 must not overlap skip_res" |
| and pmos_v5 skip_res |
| } |
| rule "pmos_v5.OVL.21" { |
| caption "pmos_v5.OVL.21: Illegal pmos_v5 device: pmos_v5 must not overlap skip_res" |
| and pmos_v5 skip_res |
| } |
| rule "pmos_v5.OVL.22" { |
| caption "pmos_v5.OVL.22: Illegal pmos_v5 device: pmos_v5 must not overlap skip_res" |
| and pmos_v5 skip_res |
| } |
| rule "pmos_v5.OVL.23" { |
| caption "pmos_v5.OVL.23: Illegal pmos_v5 device: pmos_v5 must not overlap skip_res" |
| and pmos_v5 skip_res |
| } |
| rule "pmos_v5.OVL.24" { |
| caption "pmos_v5.OVL.24: Illegal pmos_v5 device: pmos_v5 must not overlap areaid:lvNative" |
| and pmos_v5 LVID |
| } |
| rule "pmos_v5.OVL.25" { |
| caption "pmos_v5.OVL.25: Illegal pmos_v5 device: pmos_v5 must not overlap pnp" |
| and pmos_v5 pnp |
| } |
| rule "pmos_v5.OVL.26" { |
| caption "pmos_v5.OVL.26: Illegal pmos_v5 device: pmos_v5 must not overlap npn" |
| and pmos_v5 npn |
| } |
| rule "pmos_v5.OVL.27" { |
| caption "pmos_v5.OVL.27: Illegal pmos_v5 device: pmos_v5 must not overlap areaid:diode" |
| and pmos_v5 DiodeID |
| } |
| rule "pmos_v5.OVL.28" { |
| caption "pmos_v5.OVL.28: Illegal pmos_v5 device: pmos_v5 must not overlap areaid:photo" |
| and pmos_v5 PHdiodeID |
| } |
| rule "pmos_v5.OVL.29" { |
| caption "pmos_v5.OVL.29: Illegal pmos_v5 device: pmos_v5 must not overlap areaid:core" |
| and pmos_v5 COREID |
| } |
| rule "pmos_v5.OVL.30" { |
| caption "pmos_v5.OVL.30: Illegal pmos_v5 device: pmos_v5 must not overlap areaid:seal" |
| and pmos_v5 SEALID |
| } |
| rule "pmos_v5.OVL.31" { |
| caption "pmos_v5.OVL.31: Illegal pmos_v5 device: pmos_v5 must not overlap v12" |
| and pmos_v5 v12 |
| } |
| rule "pmos_v5.OVL.32" { |
| caption "pmos_v5.OVL.32: Illegal pmos_v5 device: pmos_v5 must not overlap v20" |
| and pmos_v5 v20 |
| } |
| rule "pmos_v5.OVL.33" { |
| caption "pmos_v5.OVL.33: Illegal pmos_v5 device: pmos_v5 must not overlap areaid:extendedDrain" |
| and pmos_v5 ENID |
| } |
| rule "pmos_v5.OVL.34" { |
| caption "pmos_v5.OVL.34: Illegal pmos_v5 device: pmos_v5 must not overlap poly:model" |
| and pmos_v5 polyModel |
| } |
| and ( and ( and gate psdm ) v12 ) ENID -outputlayer pmos_de_v12 |
| rule "pmos_de_v12.OVL.1" { |
| caption "pmos_de_v12.OVL.1: Illegal pmos_de_v12 device: pmos_de_v12 must not overlap pwbm" |
| and pmos_de_v12 pwbm |
| } |
| rule "pmos_de_v12.OVL.2" { |
| caption "pmos_de_v12.OVL.2: Illegal pmos_de_v12 device: pmos_de_v12 must not overlap pwde" |
| and pmos_de_v12 pwde |
| } |
| rule "pmos_de_v12.OVL.3" { |
| caption "pmos_de_v12.OVL.3: Illegal pmos_de_v12 device: pmos_de_v12 must not overlap hvtp" |
| and pmos_de_v12 hvtp |
| } |
| rule "pmos_de_v12.OVL.4" { |
| caption "pmos_de_v12.OVL.4: Illegal pmos_de_v12 device: pmos_de_v12 must not overlap lvtn" |
| and pmos_de_v12 lvtn |
| } |
| rule "pmos_de_v12.OVL.5" { |
| caption "pmos_de_v12.OVL.5: Illegal pmos_de_v12 device: pmos_de_v12 must not overlap tunm" |
| and pmos_de_v12 tunm |
| } |
| rule "pmos_de_v12.OVL.6" { |
| caption "pmos_de_v12.OVL.6: Illegal pmos_de_v12 device: pmos_de_v12 must not overlap rpm" |
| and pmos_de_v12 rpm |
| } |
| rule "pmos_de_v12.OVL.7" { |
| caption "pmos_de_v12.OVL.7: Illegal pmos_de_v12 device: pmos_de_v12 must not overlap rrpm" |
| and pmos_de_v12 rrpm |
| } |
| rule "pmos_de_v12.OVL.8" { |
| caption "pmos_de_v12.OVL.8: Illegal pmos_de_v12 device: pmos_de_v12 must not overlap urpm" |
| and pmos_de_v12 urpm |
| } |
| rule "pmos_de_v12.OVL.9" { |
| caption "pmos_de_v12.OVL.9: Illegal pmos_de_v12 device: pmos_de_v12 must not overlap ldntm" |
| and pmos_de_v12 ldntm |
| } |
| rule "pmos_de_v12.OVL.10" { |
| caption "pmos_de_v12.OVL.10: Illegal pmos_de_v12 device: pmos_de_v12 must not overlap npc" |
| and pmos_de_v12 npc |
| } |
| rule "pmos_de_v12.OVL.11" { |
| caption "pmos_de_v12.OVL.11: Illegal pmos_de_v12 device: pmos_de_v12 must not overlap nsdm" |
| and pmos_de_v12 nsdm |
| } |
| rule "pmos_de_v12.OVL.12" { |
| caption "pmos_de_v12.OVL.12: Illegal pmos_de_v12 device: pmos_de_v12 must not overlap nsm" |
| and pmos_de_v12 nsm |
| } |
| rule "pmos_de_v12.OVL.13" { |
| caption "pmos_de_v12.OVL.13: Illegal pmos_de_v12 device: pmos_de_v12 must not overlap skip_pad" |
| and pmos_de_v12 skip_pad |
| } |
| rule "pmos_de_v12.OVL.14" { |
| caption "pmos_de_v12.OVL.14: Illegal pmos_de_v12 device: pmos_de_v12 must not overlap fuse" |
| and pmos_de_v12 fuse |
| } |
| rule "pmos_de_v12.OVL.15" { |
| caption "pmos_de_v12.OVL.15: Illegal pmos_de_v12 device: pmos_de_v12 must not overlap diff:res" |
| and pmos_de_v12 diffres |
| } |
| rule "pmos_de_v12.OVL.16" { |
| caption "pmos_de_v12.OVL.16: Illegal pmos_de_v12 device: pmos_de_v12 must not overlap pwell:res" |
| and pmos_de_v12 pwres |
| } |
| rule "pmos_de_v12.OVL.17" { |
| caption "pmos_de_v12.OVL.17: Illegal pmos_de_v12 device: pmos_de_v12 must not overlap poly:res" |
| and pmos_de_v12 polyres |
| } |
| rule "pmos_de_v12.OVL.18" { |
| caption "pmos_de_v12.OVL.18: Illegal pmos_de_v12 device: pmos_de_v12 must not overlap li:res" |
| and pmos_de_v12 lires |
| } |
| rule "pmos_de_v12.OVL.19" { |
| caption "pmos_de_v12.OVL.19: Illegal pmos_de_v12 device: pmos_de_v12 must not overlap skip_res" |
| and pmos_de_v12 skip_res |
| } |
| rule "pmos_de_v12.OVL.20" { |
| caption "pmos_de_v12.OVL.20: Illegal pmos_de_v12 device: pmos_de_v12 must not overlap skip_res" |
| and pmos_de_v12 skip_res |
| } |
| rule "pmos_de_v12.OVL.21" { |
| caption "pmos_de_v12.OVL.21: Illegal pmos_de_v12 device: pmos_de_v12 must not overlap skip_res" |
| and pmos_de_v12 skip_res |
| } |
| rule "pmos_de_v12.OVL.22" { |
| caption "pmos_de_v12.OVL.22: Illegal pmos_de_v12 device: pmos_de_v12 must not overlap skip_res" |
| and pmos_de_v12 skip_res |
| } |
| rule "pmos_de_v12.OVL.23" { |
| caption "pmos_de_v12.OVL.23: Illegal pmos_de_v12 device: pmos_de_v12 must not overlap skip_res" |
| and pmos_de_v12 skip_res |
| } |
| rule "pmos_de_v12.OVL.24" { |
| caption "pmos_de_v12.OVL.24: Illegal pmos_de_v12 device: pmos_de_v12 must not overlap areaid:lvNative" |
| and pmos_de_v12 LVID |
| } |
| rule "pmos_de_v12.OVL.25" { |
| caption "pmos_de_v12.OVL.25: Illegal pmos_de_v12 device: pmos_de_v12 must not overlap pnp" |
| and pmos_de_v12 pnp |
| } |
| rule "pmos_de_v12.OVL.26" { |
| caption "pmos_de_v12.OVL.26: Illegal pmos_de_v12 device: pmos_de_v12 must not overlap npn" |
| and pmos_de_v12 npn |
| } |
| rule "pmos_de_v12.OVL.27" { |
| caption "pmos_de_v12.OVL.27: Illegal pmos_de_v12 device: pmos_de_v12 must not overlap areaid:diode" |
| and pmos_de_v12 DiodeID |
| } |
| rule "pmos_de_v12.OVL.28" { |
| caption "pmos_de_v12.OVL.28: Illegal pmos_de_v12 device: pmos_de_v12 must not overlap areaid:photo" |
| and pmos_de_v12 PHdiodeID |
| } |
| rule "pmos_de_v12.OVL.29" { |
| caption "pmos_de_v12.OVL.29: Illegal pmos_de_v12 device: pmos_de_v12 must not overlap areaid:core" |
| and pmos_de_v12 COREID |
| } |
| rule "pmos_de_v12.OVL.30" { |
| caption "pmos_de_v12.OVL.30: Illegal pmos_de_v12 device: pmos_de_v12 must not overlap areaid:esd" |
| and pmos_de_v12 ESDID |
| } |
| rule "pmos_de_v12.OVL.31" { |
| caption "pmos_de_v12.OVL.31: Illegal pmos_de_v12 device: pmos_de_v12 must not overlap areaid:seal" |
| and pmos_de_v12 SEALID |
| } |
| rule "pmos_de_v12.OVL.32" { |
| caption "pmos_de_v12.OVL.32: Illegal pmos_de_v12 device: pmos_de_v12 must not overlap v5" |
| and pmos_de_v12 v5 |
| } |
| rule "pmos_de_v12.OVL.33" { |
| caption "pmos_de_v12.OVL.33: Illegal pmos_de_v12 device: pmos_de_v12 must not overlap v20" |
| and pmos_de_v12 v20 |
| } |
| rule "pmos_de_v12.OVL.34" { |
| caption "pmos_de_v12.OVL.34: Illegal pmos_de_v12 device: pmos_de_v12 must not overlap poly:model" |
| and pmos_de_v12 polyModel |
| } |
| and ( and ( and gate psdm ) v20 ) ENID -outputlayer pmos_de_v20 |
| rule "pmos_de_v20.OVL.1" { |
| caption "pmos_de_v20.OVL.1: Illegal pmos_de_v20 device: pmos_de_v20 must not overlap hvtp" |
| and pmos_de_v20 hvtp |
| } |
| rule "pmos_de_v20.OVL.2" { |
| caption "pmos_de_v20.OVL.2: Illegal pmos_de_v20 device: pmos_de_v20 must not overlap tunm" |
| and pmos_de_v20 tunm |
| } |
| rule "pmos_de_v20.OVL.3" { |
| caption "pmos_de_v20.OVL.3: Illegal pmos_de_v20 device: pmos_de_v20 must not overlap rpm" |
| and pmos_de_v20 rpm |
| } |
| rule "pmos_de_v20.OVL.4" { |
| caption "pmos_de_v20.OVL.4: Illegal pmos_de_v20 device: pmos_de_v20 must not overlap rrpm" |
| and pmos_de_v20 rrpm |
| } |
| rule "pmos_de_v20.OVL.5" { |
| caption "pmos_de_v20.OVL.5: Illegal pmos_de_v20 device: pmos_de_v20 must not overlap urpm" |
| and pmos_de_v20 urpm |
| } |
| rule "pmos_de_v20.OVL.6" { |
| caption "pmos_de_v20.OVL.6: Illegal pmos_de_v20 device: pmos_de_v20 must not overlap ldntm" |
| and pmos_de_v20 ldntm |
| } |
| rule "pmos_de_v20.OVL.7" { |
| caption "pmos_de_v20.OVL.7: Illegal pmos_de_v20 device: pmos_de_v20 must not overlap npc" |
| and pmos_de_v20 npc |
| } |
| rule "pmos_de_v20.OVL.8" { |
| caption "pmos_de_v20.OVL.8: Illegal pmos_de_v20 device: pmos_de_v20 must not overlap nsdm" |
| and pmos_de_v20 nsdm |
| } |
| rule "pmos_de_v20.OVL.9" { |
| caption "pmos_de_v20.OVL.9: Illegal pmos_de_v20 device: pmos_de_v20 must not overlap nsm" |
| and pmos_de_v20 nsm |
| } |
| rule "pmos_de_v20.OVL.10" { |
| caption "pmos_de_v20.OVL.10: Illegal pmos_de_v20 device: pmos_de_v20 must not overlap skip_pad" |
| and pmos_de_v20 skip_pad |
| } |
| rule "pmos_de_v20.OVL.11" { |
| caption "pmos_de_v20.OVL.11: Illegal pmos_de_v20 device: pmos_de_v20 must not overlap fuse" |
| and pmos_de_v20 fuse |
| } |
| rule "pmos_de_v20.OVL.12" { |
| caption "pmos_de_v20.OVL.12: Illegal pmos_de_v20 device: pmos_de_v20 must not overlap diff:res" |
| and pmos_de_v20 diffres |
| } |
| rule "pmos_de_v20.OVL.13" { |
| caption "pmos_de_v20.OVL.13: Illegal pmos_de_v20 device: pmos_de_v20 must not overlap pwell:res" |
| and pmos_de_v20 pwres |
| } |
| rule "pmos_de_v20.OVL.14" { |
| caption "pmos_de_v20.OVL.14: Illegal pmos_de_v20 device: pmos_de_v20 must not overlap poly:res" |
| and pmos_de_v20 polyres |
| } |
| rule "pmos_de_v20.OVL.15" { |
| caption "pmos_de_v20.OVL.15: Illegal pmos_de_v20 device: pmos_de_v20 must not overlap li:res" |
| and pmos_de_v20 lires |
| } |
| rule "pmos_de_v20.OVL.16" { |
| caption "pmos_de_v20.OVL.16: Illegal pmos_de_v20 device: pmos_de_v20 must not overlap skip_res" |
| and pmos_de_v20 skip_res |
| } |
| rule "pmos_de_v20.OVL.17" { |
| caption "pmos_de_v20.OVL.17: Illegal pmos_de_v20 device: pmos_de_v20 must not overlap skip_res" |
| and pmos_de_v20 skip_res |
| } |
| rule "pmos_de_v20.OVL.18" { |
| caption "pmos_de_v20.OVL.18: Illegal pmos_de_v20 device: pmos_de_v20 must not overlap skip_res" |
| and pmos_de_v20 skip_res |
| } |
| rule "pmos_de_v20.OVL.19" { |
| caption "pmos_de_v20.OVL.19: Illegal pmos_de_v20 device: pmos_de_v20 must not overlap skip_res" |
| and pmos_de_v20 skip_res |
| } |
| rule "pmos_de_v20.OVL.20" { |
| caption "pmos_de_v20.OVL.20: Illegal pmos_de_v20 device: pmos_de_v20 must not overlap skip_res" |
| and pmos_de_v20 skip_res |
| } |
| rule "pmos_de_v20.OVL.21" { |
| caption "pmos_de_v20.OVL.21: Illegal pmos_de_v20 device: pmos_de_v20 must not overlap areaid:lvNative" |
| and pmos_de_v20 LVID |
| } |
| rule "pmos_de_v20.OVL.22" { |
| caption "pmos_de_v20.OVL.22: Illegal pmos_de_v20 device: pmos_de_v20 must not overlap pnp" |
| and pmos_de_v20 pnp |
| } |
| rule "pmos_de_v20.OVL.23" { |
| caption "pmos_de_v20.OVL.23: Illegal pmos_de_v20 device: pmos_de_v20 must not overlap npn" |
| and pmos_de_v20 npn |
| } |
| rule "pmos_de_v20.OVL.24" { |
| caption "pmos_de_v20.OVL.24: Illegal pmos_de_v20 device: pmos_de_v20 must not overlap areaid:diode" |
| and pmos_de_v20 DiodeID |
| } |
| rule "pmos_de_v20.OVL.25" { |
| caption "pmos_de_v20.OVL.25: Illegal pmos_de_v20 device: pmos_de_v20 must not overlap areaid:photo" |
| and pmos_de_v20 PHdiodeID |
| } |
| rule "pmos_de_v20.OVL.26" { |
| caption "pmos_de_v20.OVL.26: Illegal pmos_de_v20 device: pmos_de_v20 must not overlap areaid:core" |
| and pmos_de_v20 COREID |
| } |
| rule "pmos_de_v20.OVL.27" { |
| caption "pmos_de_v20.OVL.27: Illegal pmos_de_v20 device: pmos_de_v20 must not overlap areaid:esd" |
| and pmos_de_v20 ESDID |
| } |
| rule "pmos_de_v20.OVL.28" { |
| caption "pmos_de_v20.OVL.28: Illegal pmos_de_v20 device: pmos_de_v20 must not overlap areaid:seal" |
| and pmos_de_v20 SEALID |
| } |
| rule "pmos_de_v20.OVL.29" { |
| caption "pmos_de_v20.OVL.29: Illegal pmos_de_v20 device: pmos_de_v20 must not overlap v5" |
| and pmos_de_v20 v5 |
| } |
| rule "pmos_de_v20.OVL.30" { |
| caption "pmos_de_v20.OVL.30: Illegal pmos_de_v20 device: pmos_de_v20 must not overlap v12" |
| and pmos_de_v20 v12 |
| } |
| rule "pmos_de_v20.OVL.31" { |
| caption "pmos_de_v20.OVL.31: Illegal pmos_de_v20 device: pmos_de_v20 must not overlap poly:model" |
| and pmos_de_v20 polyModel |
| } |
| |
| |
| // RES: |
| |
| |
| |
| and polyi polyres -outputlayer hp_poly_1a |
| and hp_poly_1a npc -outputlayer hp_poly_2a |
| and hp_poly_2a psdm -outputlayer hp_poly_3a |
| and hp_poly_3a rpm -outputlayer hp_polya |
| rule "rpoly_hp.OVL.1" { |
| caption "rpoly_hp.OVL.1: Illegal rpoly_hp device: rpoly_hp must not overlap diff" |
| and hp_polya diffi |
| } |
| rule "rpoly_hp.OVL.2" { |
| caption "rpoly_hp.OVL.2: Illegal rpoly_hp device: rpoly_hp must not overlap tunm" |
| and hp_polya tunm |
| } |
| rule "rpoly_hp.OVL.3" { |
| caption "rpoly_hp.OVL.3: Illegal rpoly_hp device: rpoly_hp must not overlap urpm" |
| and hp_polya urpm |
| } |
| rule "rpoly_hp.OVL.4" { |
| caption "rpoly_hp.OVL.4: Illegal rpoly_hp device: rpoly_hp must not overlap ldntm" |
| and hp_polya ldntm |
| } |
| rule "rpoly_hp.OVL.5" { |
| caption "rpoly_hp.OVL.5: Illegal rpoly_hp device: rpoly_hp must not overlap nsdm" |
| and hp_polya nsdm |
| } |
| rule "rpoly_hp.OVL.6" { |
| caption "rpoly_hp.OVL.6: Illegal rpoly_hp device: rpoly_hp must not overlap nsm" |
| and hp_polya nsm |
| } |
| rule "rpoly_hp.OVL.7" { |
| caption "rpoly_hp.OVL.7: Illegal rpoly_hp device: rpoly_hp must not overlap skip_pad" |
| and hp_polya skip_pad |
| } |
| rule "rpoly_hp.OVL.8" { |
| caption "rpoly_hp.OVL.8: Illegal rpoly_hp device: rpoly_hp must not overlap fuse" |
| and hp_polya fuse |
| } |
| rule "rpoly_hp.OVL.9" { |
| caption "rpoly_hp.OVL.9: Illegal rpoly_hp device: rpoly_hp must not overlap diff:res" |
| and hp_polya diffres |
| } |
| rule "rpoly_hp.OVL.10" { |
| caption "rpoly_hp.OVL.10: Illegal rpoly_hp device: rpoly_hp must not overlap pwell:res" |
| and hp_polya pwres |
| } |
| rule "rpoly_hp.OVL.11" { |
| caption "rpoly_hp.OVL.11: Illegal rpoly_hp device: rpoly_hp must not overlap li:res" |
| and hp_polya lires |
| } |
| rule "rpoly_hp.OVL.12" { |
| caption "rpoly_hp.OVL.12: Illegal rpoly_hp device: rpoly_hp must not overlap skip_res" |
| and hp_polya skip_res |
| } |
| rule "rpoly_hp.OVL.13" { |
| caption "rpoly_hp.OVL.13: Illegal rpoly_hp device: rpoly_hp must not overlap skip_res" |
| and hp_polya skip_res |
| } |
| rule "rpoly_hp.OVL.14" { |
| caption "rpoly_hp.OVL.14: Illegal rpoly_hp device: rpoly_hp must not overlap skip_res" |
| and hp_polya skip_res |
| } |
| rule "rpoly_hp.OVL.15" { |
| caption "rpoly_hp.OVL.15: Illegal rpoly_hp device: rpoly_hp must not overlap skip_res" |
| and hp_polya skip_res |
| } |
| rule "rpoly_hp.OVL.16" { |
| caption "rpoly_hp.OVL.16: Illegal rpoly_hp device: rpoly_hp must not overlap skip_res" |
| and hp_polya skip_res |
| } |
| rule "rpoly_hp.OVL.17" { |
| caption "rpoly_hp.OVL.17: Illegal rpoly_hp device: rpoly_hp must not overlap areaid:lvNative" |
| and hp_polya LVID |
| } |
| rule "rpoly_hp.OVL.18" { |
| caption "rpoly_hp.OVL.18: Illegal rpoly_hp device: rpoly_hp must not overlap pnp" |
| and hp_polya pnp |
| } |
| rule "rpoly_hp.OVL.19" { |
| caption "rpoly_hp.OVL.19: Illegal rpoly_hp device: rpoly_hp must not overlap npn" |
| and hp_polya npn |
| } |
| rule "rpoly_hp.OVL.20" { |
| caption "rpoly_hp.OVL.20: Illegal rpoly_hp device: rpoly_hp must not overlap areaid:diode" |
| and hp_polya DiodeID |
| } |
| rule "rpoly_hp.OVL.21" { |
| caption "rpoly_hp.OVL.21: Illegal rpoly_hp device: rpoly_hp must not overlap areaid:photo" |
| and hp_polya PHdiodeID |
| } |
| rule "rpoly_hp.OVL.22" { |
| caption "rpoly_hp.OVL.22: Illegal rpoly_hp device: rpoly_hp must not overlap areaid:core" |
| and hp_polya COREID |
| } |
| rule "rpoly_hp.OVL.23" { |
| caption "rpoly_hp.OVL.23: Illegal rpoly_hp device: rpoly_hp must not overlap areaid:extendedDrain" |
| and hp_polya ENID |
| } |
| rule "rpoly_hp.OVL.24" { |
| caption "rpoly_hp.OVL.24: Illegal rpoly_hp device: rpoly_hp must not overlap areaid:seal" |
| and hp_polya SEALID |
| } |
| rule "rpoly_hp.OVL.25" { |
| caption "rpoly_hp.OVL.25: Illegal rpoly_hp device: rpoly_hp must not overlap poly:model" |
| and hp_polya polyModel |
| } |
| and polyi polyres -outputlayer hs_poly_1a |
| and hs_poly_1a npc -outputlayer hs_poly_2a |
| and hs_poly_2a psdm -outputlayer hs_poly_3a |
| and hs_poly_3a urpm -outputlayer hs_polya |
| rule "rpoly_hs.OVL.1" { |
| caption "rpoly_hs.OVL.1: Illegal rpoly_hs device: rpoly_hs must not overlap diff" |
| and hs_polya diffi |
| } |
| rule "rpoly_hs.OVL.2" { |
| caption "rpoly_hs.OVL.2: Illegal rpoly_hs device: rpoly_hs must not overlap tunm" |
| and hs_polya tunm |
| } |
| rule "rpoly_hs.OVL.3" { |
| caption "rpoly_hs.OVL.3: Illegal rpoly_hs device: rpoly_hs must not overlap rrpm" |
| and hs_polya rrpm |
| } |
| rule "rpoly_hs.OVL.4" { |
| caption "rpoly_hs.OVL.4: Illegal rpoly_hs device: rpoly_hs must not overlap ldntm" |
| and hs_polya ldntm |
| } |
| rule "rpoly_hs.OVL.5" { |
| caption "rpoly_hs.OVL.5: Illegal rpoly_hs device: rpoly_hs must not overlap nsdm" |
| and hs_polya nsdm |
| } |
| rule "rpoly_hs.OVL.6" { |
| caption "rpoly_hs.OVL.6: Illegal rpoly_hs device: rpoly_hs must not overlap nsm" |
| and hs_polya nsm |
| } |
| rule "rpoly_hs.OVL.7" { |
| caption "rpoly_hs.OVL.7: Illegal rpoly_hs device: rpoly_hs must not overlap skip_pad" |
| and hs_polya skip_pad |
| } |
| rule "rpoly_hs.OVL.8" { |
| caption "rpoly_hs.OVL.8: Illegal rpoly_hs device: rpoly_hs must not overlap fuse" |
| and hs_polya fuse |
| } |
| rule "rpoly_hs.OVL.9" { |
| caption "rpoly_hs.OVL.9: Illegal rpoly_hs device: rpoly_hs must not overlap diff:res" |
| and hs_polya diffres |
| } |
| rule "rpoly_hs.OVL.10" { |
| caption "rpoly_hs.OVL.10: Illegal rpoly_hs device: rpoly_hs must not overlap pwell:res" |
| and hs_polya pwres |
| } |
| rule "rpoly_hs.OVL.11" { |
| caption "rpoly_hs.OVL.11: Illegal rpoly_hs device: rpoly_hs must not overlap li:res" |
| and hs_polya lires |
| } |
| rule "rpoly_hs.OVL.12" { |
| caption "rpoly_hs.OVL.12: Illegal rpoly_hs device: rpoly_hs must not overlap skip_res" |
| and hs_polya skip_res |
| } |
| rule "rpoly_hs.OVL.13" { |
| caption "rpoly_hs.OVL.13: Illegal rpoly_hs device: rpoly_hs must not overlap skip_res" |
| and hs_polya skip_res |
| } |
| rule "rpoly_hs.OVL.14" { |
| caption "rpoly_hs.OVL.14: Illegal rpoly_hs device: rpoly_hs must not overlap skip_res" |
| and hs_polya skip_res |
| } |
| rule "rpoly_hs.OVL.15" { |
| caption "rpoly_hs.OVL.15: Illegal rpoly_hs device: rpoly_hs must not overlap skip_res" |
| and hs_polya skip_res |
| } |
| rule "rpoly_hs.OVL.16" { |
| caption "rpoly_hs.OVL.16: Illegal rpoly_hs device: rpoly_hs must not overlap skip_res" |
| and hs_polya skip_res |
| } |
| rule "rpoly_hs.OVL.17" { |
| caption "rpoly_hs.OVL.17: Illegal rpoly_hs device: rpoly_hs must not overlap areaid:lvNative" |
| and hs_polya LVID |
| } |
| rule "rpoly_hs.OVL.18" { |
| caption "rpoly_hs.OVL.18: Illegal rpoly_hs device: rpoly_hs must not overlap pnp" |
| and hs_polya pnp |
| } |
| rule "rpoly_hs.OVL.19" { |
| caption "rpoly_hs.OVL.19: Illegal rpoly_hs device: rpoly_hs must not overlap npn" |
| and hs_polya npn |
| } |
| rule "rpoly_hs.OVL.20" { |
| caption "rpoly_hs.OVL.20: Illegal rpoly_hs device: rpoly_hs must not overlap areaid:diode" |
| and hs_polya DiodeID |
| } |
| rule "rpoly_hs.OVL.21" { |
| caption "rpoly_hs.OVL.21: Illegal rpoly_hs device: rpoly_hs must not overlap areaid:photo" |
| and hs_polya PHdiodeID |
| } |
| rule "rpoly_hs.OVL.22" { |
| caption "rpoly_hs.OVL.22: Illegal rpoly_hs device: rpoly_hs must not overlap areaid:core" |
| and hs_polya COREID |
| } |
| rule "rpoly_hs.OVL.23" { |
| caption "rpoly_hs.OVL.23: Illegal rpoly_hs device: rpoly_hs must not overlap areaid:extendedDrain" |
| and hs_polya ENID |
| } |
| rule "rpoly_hs.OVL.24" { |
| caption "rpoly_hs.OVL.24: Illegal rpoly_hs device: rpoly_hs must not overlap areaid:seal" |
| and hs_polya SEALID |
| } |
| rule "rpoly_hs.OVL.25" { |
| caption "rpoly_hs.OVL.25: Illegal rpoly_hs device: rpoly_hs must not overlap poly:model" |
| and hs_polya polyModel |
| } |
| not ( and polyi polyres ) ( or hp_polya hs_polya ) -outputlayer rpoly_std |
| rule "rpoly.OVL.1" { |
| caption "rpoly.OVL.1: Illegal rpoly device: rpoly must not overlap diff" |
| and rpoly_std diffi |
| } |
| rule "rpoly.OVL.2" { |
| caption "rpoly.OVL.2: Illegal rpoly device: rpoly must not overlap tunm" |
| and rpoly_std tunm |
| } |
| rule "rpoly.OVL.3" { |
| caption "rpoly.OVL.3: Illegal rpoly device: rpoly must not overlap rpm" |
| and rpoly_std rpm |
| } |
| rule "rpoly.OVL.4" { |
| caption "rpoly.OVL.4: Illegal rpoly device: rpoly must not overlap rrpm" |
| and rpoly_std rrpm |
| } |
| rule "rpoly.OVL.5" { |
| caption "rpoly.OVL.5: Illegal rpoly device: rpoly must not overlap urpm" |
| and rpoly_std urpm |
| } |
| rule "rpoly.OVL.6" { |
| caption "rpoly.OVL.6: Illegal rpoly device: rpoly must not overlap ldntm" |
| and rpoly_std ldntm |
| } |
| rule "rpoly.OVL.7" { |
| caption "rpoly.OVL.7: Illegal rpoly device: rpoly must not overlap psdm" |
| and rpoly_std psdm |
| } |
| rule "rpoly.OVL.8" { |
| caption "rpoly.OVL.8: Illegal rpoly device: rpoly must not overlap nsm" |
| and rpoly_std nsm |
| } |
| rule "rpoly.OVL.9" { |
| caption "rpoly.OVL.9: Illegal rpoly device: rpoly must not overlap skip_pad" |
| and rpoly_std skip_pad |
| } |
| rule "rpoly.OVL.10" { |
| caption "rpoly.OVL.10: Illegal rpoly device: rpoly must not overlap fuse" |
| and rpoly_std fuse |
| } |
| rule "rpoly.OVL.11" { |
| caption "rpoly.OVL.11: Illegal rpoly device: rpoly must not overlap diff:res" |
| and rpoly_std diffres |
| } |
| rule "rpoly.OVL.12" { |
| caption "rpoly.OVL.12: Illegal rpoly device: rpoly must not overlap pwell:res" |
| and rpoly_std pwres |
| } |
| rule "rpoly.OVL.13" { |
| caption "rpoly.OVL.13: Illegal rpoly device: rpoly must not overlap li:res" |
| and rpoly_std lires |
| } |
| rule "rpoly.OVL.14" { |
| caption "rpoly.OVL.14: Illegal rpoly device: rpoly must not overlap skip_res" |
| and rpoly_std skip_res |
| } |
| rule "rpoly.OVL.15" { |
| caption "rpoly.OVL.15: Illegal rpoly device: rpoly must not overlap skip_res" |
| and rpoly_std skip_res |
| } |
| rule "rpoly.OVL.16" { |
| caption "rpoly.OVL.16: Illegal rpoly device: rpoly must not overlap skip_res" |
| and rpoly_std skip_res |
| } |
| rule "rpoly.OVL.17" { |
| caption "rpoly.OVL.17: Illegal rpoly device: rpoly must not overlap skip_res" |
| and rpoly_std skip_res |
| } |
| rule "rpoly.OVL.18" { |
| caption "rpoly.OVL.18: Illegal rpoly device: rpoly must not overlap skip_res" |
| and rpoly_std skip_res |
| } |
| rule "rpoly.OVL.19" { |
| caption "rpoly.OVL.19: Illegal rpoly device: rpoly must not overlap areaid:lvNative" |
| and rpoly_std LVID |
| } |
| rule "rpoly.OVL.20" { |
| caption "rpoly.OVL.20: Illegal rpoly device: rpoly must not overlap pnp" |
| and rpoly_std pnp |
| } |
| rule "rpoly.OVL.21" { |
| caption "rpoly.OVL.21: Illegal rpoly device: rpoly must not overlap npn" |
| and rpoly_std npn |
| } |
| rule "rpoly.OVL.22" { |
| caption "rpoly.OVL.22: Illegal rpoly device: rpoly must not overlap areaid:diode" |
| and rpoly_std DiodeID |
| } |
| rule "rpoly.OVL.23" { |
| caption "rpoly.OVL.23: Illegal rpoly device: rpoly must not overlap areaid:photo" |
| and rpoly_std PHdiodeID |
| } |
| rule "rpoly.OVL.24" { |
| caption "rpoly.OVL.24: Illegal rpoly device: rpoly must not overlap areaid:core" |
| and rpoly_std COREID |
| } |
| rule "rpoly.OVL.25" { |
| caption "rpoly.OVL.25: Illegal rpoly device: rpoly must not overlap areaid:extendedDrain" |
| and rpoly_std ENID |
| } |
| rule "rpoly.OVL.26" { |
| caption "rpoly.OVL.26: Illegal rpoly device: rpoly must not overlap areaid:seal" |
| and rpoly_std SEALID |
| } |
| rule "rpoly.OVL.27" { |
| caption "rpoly.OVL.27: Illegal rpoly device: rpoly must not overlap poly:model" |
| and rpoly_std polyModel |
| } |
| and li_i lires -outputlayer li1r |
| rule "lires.OVL.1" { |
| caption "lires.OVL.1: Illegal lires device: lires must not overlap licon" |
| and li1r licon |
| } |
| rule "lires.OVL.2" { |
| caption "lires.OVL.2: Illegal lires device: lires must not overlap nsm" |
| and li1r nsm |
| } |
| rule "lires.OVL.3" { |
| caption "lires.OVL.3: Illegal lires device: lires must not overlap skip_pad" |
| and li1r skip_pad |
| } |
| rule "lires.OVL.4" { |
| caption "lires.OVL.4: Illegal lires device: lires must not overlap fuse" |
| and li1r fuse |
| } |
| rule "lires.OVL.5" { |
| caption "lires.OVL.5: Illegal lires device: lires must not overlap areaid:photo" |
| and li1r PHdiodeID |
| } |
| rule "lires.OVL.6" { |
| caption "lires.OVL.6: Illegal lires device: lires must not overlap areaid:core" |
| and li1r COREID |
| } |
| rule "lires.OVL.7" { |
| caption "lires.OVL.7: Illegal lires device: lires must not overlap areaid:extendedDrain" |
| and li1r ENID |
| } |
| rule "lires.OVL.8" { |
| caption "lires.OVL.8: Illegal lires device: lires must not overlap areaid:seal" |
| and li1r SEALID |
| } |
| rule "lires.OVL.9" { |
| caption "lires.OVL.9: Illegal lires device: lires must not overlap poly:model" |
| and li1r polyModel |
| } |
| rule "lires.OVL.10" { |
| caption "lires.OVL.10: Illegal lires device: lires must not overlap poly:res" |
| and li1r polyres |
| } |
| and met1i m1res -outputlayer m1r |
| rule "m1res.OVL.1" { |
| caption "m1res.OVL.1: Illegal m1res device: m1res must not overlap nsm" |
| and m1r nsm |
| } |
| rule "m1res.OVL.2" { |
| caption "m1res.OVL.2: Illegal m1res device: m1res must not overlap skip_pad" |
| and m1r skip_pad |
| } |
| rule "m1res.OVL.3" { |
| caption "m1res.OVL.3: Illegal m1res device: m1res must not overlap fuse" |
| and m1r fuse |
| } |
| rule "m1res.OVL.4" { |
| caption "m1res.OVL.4: Illegal m1res device: m1res must not overlap areaid:seal" |
| and m1r SEALID |
| } |
| rule "m1res.OVL.5" { |
| caption "m1res.OVL.5: Illegal m1res device: m1res must not overlap poly:model" |
| and m1r polyModel |
| } |
| rule "m1res.OVL.6" { |
| caption "m1res.OVL.6: Illegal m1res device: m1res must not overlap areaid:extendedDrain" |
| and m1r ENID |
| } |
| and met2i m2res -outputlayer m2r |
| rule "m2res.OVL.1" { |
| caption "m2res.OVL.1: Illegal m2res device: m2res must not overlap nsm" |
| and m2r nsm |
| } |
| rule "m2res.OVL.2" { |
| caption "m2res.OVL.2: Illegal m2res device: m2res must not overlap skip_pad" |
| and m2r skip_pad |
| } |
| rule "m2res.OVL.3" { |
| caption "m2res.OVL.3: Illegal m2res device: m2res must not overlap fuse" |
| and m2r fuse |
| } |
| rule "m2res.OVL.4" { |
| caption "m2res.OVL.4: Illegal m2res device: m2res must not overlap areaid:seal" |
| and m2r SEALID |
| } |
| rule "m2res.OVL.5" { |
| caption "m2res.OVL.5: Illegal m2res device: m2res must not overlap poly:model" |
| and m2r polyModel |
| } |
| rule "m2res.OVL.6" { |
| caption "m2res.OVL.6: Illegal m2res device: m2res must not overlap areaid:extendedDrain" |
| and m2r ENID |
| } |
| and met3i m3res -outputlayer m3r |
| rule "m3res.OVL.1" { |
| caption "m3res.OVL.1: Illegal m3res device: m3res must not overlap nsm" |
| and m3r nsm |
| } |
| rule "m3res.OVL.2" { |
| caption "m3res.OVL.2: Illegal m3res device: m3res must not overlap skip_pad" |
| and m3r skip_pad |
| } |
| rule "m3res.OVL.3" { |
| caption "m3res.OVL.3: Illegal m3res device: m3res must not overlap fuse" |
| and m3r fuse |
| } |
| rule "m3res.OVL.4" { |
| caption "m3res.OVL.4: Illegal m3res device: m3res must not overlap areaid:seal" |
| and m3r SEALID |
| } |
| rule "m3res.OVL.5" { |
| caption "m3res.OVL.5: Illegal m3res device: m3res must not overlap poly:model" |
| and m3r polyModel |
| } |
| rule "m3res.OVL.6" { |
| caption "m3res.OVL.6: Illegal m3res device: m3res must not overlap areaid:extendedDrain" |
| and m3r ENID |
| } |
| and met4i m4res -outputlayer m4r |
| rule "m4res.OVL.1" { |
| caption "m4res.OVL.1: Illegal m4res device: m4res must not overlap nsm" |
| and m4r nsm |
| } |
| rule "m4res.OVL.2" { |
| caption "m4res.OVL.2: Illegal m4res device: m4res must not overlap skip_pad" |
| and m4r skip_pad |
| } |
| rule "m4res.OVL.3" { |
| caption "m4res.OVL.3: Illegal m4res device: m4res must not overlap fuse" |
| and m4r fuse |
| } |
| rule "m4res.OVL.4" { |
| caption "m4res.OVL.4: Illegal m4res device: m4res must not overlap areaid:seal" |
| and m4r SEALID |
| } |
| rule "m4res.OVL.5" { |
| caption "m4res.OVL.5: Illegal m4res device: m4res must not overlap poly:model" |
| and m4r polyModel |
| } |
| rule "m4res.OVL.6" { |
| caption "m4res.OVL.6: Illegal m4res device: m4res must not overlap areaid:extendedDrain" |
| and m4r ENID |
| } |
| and met5i m5res -outputlayer m5r |
| rule "m5res.OVL.1" { |
| caption "m5res.OVL.1: Illegal m5res device: m5res must not overlap nsm" |
| and m5r nsm |
| } |
| rule "m5res.OVL.2" { |
| caption "m5res.OVL.2: Illegal m5res device: m5res must not overlap skip_pad" |
| and m5r skip_pad |
| } |
| rule "m5res.OVL.3" { |
| caption "m5res.OVL.3: Illegal m5res device: m5res must not overlap fuse" |
| and m5r fuse |
| } |
| rule "m5res.OVL.4" { |
| caption "m5res.OVL.4: Illegal m5res device: m5res must not overlap areaid:seal" |
| and m5r SEALID |
| } |
| rule "m5res.OVL.5" { |
| caption "m5res.OVL.5: Illegal m5res device: m5res must not overlap poly:model" |
| and m5r polyModel |
| } |
| rule "m5res.OVL.6" { |
| caption "m5res.OVL.6: Illegal m5res device: m5res must not overlap areaid:extendedDrain" |
| and m5r ENID |
| } |
| not ( and ( and nsdm diffi ) diffres ) v5 -outputlayer rndiff_ill_dev |
| rule "rndiff.OVL.1" { |
| caption "rndiff.OVL.1: Illegal rndiff device: rndiff must not overlap pwbm" |
| and rndiff_ill_dev pwbm |
| } |
| rule "rndiff.OVL.2" { |
| caption "rndiff.OVL.2: Illegal rndiff device: rndiff must not overlap nwell" |
| and rndiff_ill_dev nwell |
| } |
| rule "rndiff.OVL.3" { |
| caption "rndiff.OVL.3: Illegal rndiff device: rndiff must not overlap hvtp" |
| and rndiff_ill_dev hvtp |
| } |
| rule "rndiff.OVL.4" { |
| caption "rndiff.OVL.4: Illegal rndiff device: rndiff must not overlap lvtn" |
| and rndiff_ill_dev lvtn |
| } |
| rule "rndiff.OVL.5" { |
| caption "rndiff.OVL.5: Illegal rndiff device: rndiff must not overlap tunm" |
| and rndiff_ill_dev tunm |
| } |
| rule "rndiff.OVL.6" { |
| caption "rndiff.OVL.6: Illegal rndiff device: rndiff must not overlap thkox" |
| and rndiff_ill_dev thkox |
| } |
| rule "rndiff.OVL.7" { |
| caption "rndiff.OVL.7: Illegal rndiff device: rndiff must not overlap rpm" |
| and rndiff_ill_dev rpm |
| } |
| rule "rndiff.OVL.8" { |
| caption "rndiff.OVL.8: Illegal rndiff device: rndiff must not overlap rrpm" |
| and rndiff_ill_dev rrpm |
| } |
| rule "rndiff.OVL.9" { |
| caption "rndiff.OVL.9: Illegal rndiff device: rndiff must not overlap urpm" |
| and rndiff_ill_dev urpm |
| } |
| rule "rndiff.OVL.10" { |
| caption "rndiff.OVL.10: Illegal rndiff device: rndiff must not overlap ldntm" |
| and rndiff_ill_dev ldntm |
| } |
| rule "rndiff.OVL.11" { |
| caption "rndiff.OVL.11: Illegal rndiff device: rndiff must not overlap psdm" |
| and rndiff_ill_dev psdm |
| } |
| rule "rndiff.OVL.12" { |
| caption "rndiff.OVL.12: Illegal rndiff device: rndiff must not overlap nsm" |
| and rndiff_ill_dev nsm |
| } |
| rule "rndiff.OVL.13" { |
| caption "rndiff.OVL.13: Illegal rndiff device: rndiff must not overlap skip_pad" |
| and rndiff_ill_dev skip_pad |
| } |
| rule "rndiff.OVL.14" { |
| caption "rndiff.OVL.14: Illegal rndiff device: rndiff must not overlap fuse" |
| and rndiff_ill_dev fuse |
| } |
| rule "rndiff.OVL.15" { |
| caption "rndiff.OVL.15: Illegal rndiff device: rndiff must not overlap poly:res" |
| and rndiff_ill_dev polyres |
| } |
| rule "rndiff.OVL.16" { |
| caption "rndiff.OVL.16: Illegal rndiff device: rndiff must not overlap areaid:lvNative" |
| and rndiff_ill_dev LVID |
| } |
| rule "rndiff.OVL.17" { |
| caption "rndiff.OVL.17: Illegal rndiff device: rndiff must not overlap pnp" |
| and rndiff_ill_dev pnp |
| } |
| rule "rndiff.OVL.18" { |
| caption "rndiff.OVL.18: Illegal rndiff device: rndiff must not overlap npn" |
| and rndiff_ill_dev npn |
| } |
| rule "rndiff.OVL.19" { |
| caption "rndiff.OVL.19: Illegal rndiff device: rndiff must not overlap areaid:diode" |
| and rndiff_ill_dev DiodeID |
| } |
| rule "rndiff.OVL.20" { |
| caption "rndiff.OVL.20: Illegal rndiff device: rndiff must not overlap areaid:photo" |
| and rndiff_ill_dev PHdiodeID |
| } |
| rule "rndiff.OVL.21" { |
| caption "rndiff.OVL.21: Illegal rndiff device: rndiff must not overlap areaid:core" |
| and rndiff_ill_dev COREID |
| } |
| rule "rndiff.OVL.22" { |
| caption "rndiff.OVL.22: Illegal rndiff device: rndiff must not overlap areaid:extendedDrain" |
| and rndiff_ill_dev ENID |
| } |
| rule "rndiff.OVL.23" { |
| caption "rndiff.OVL.23: Illegal rndiff device: rndiff must not overlap areaid:seal" |
| and rndiff_ill_dev SEALID |
| } |
| rule "rndiff.OVL.24" { |
| caption "rndiff.OVL.24: Illegal rndiff device: rndiff must not overlap v5" |
| and rndiff_ill_dev v5 |
| } |
| rule "rndiff.OVL.25" { |
| caption "rndiff.OVL.25: Illegal rndiff device: rndiff must not overlap v12" |
| and rndiff_ill_dev v12 |
| } |
| rule "rndiff.OVL.26" { |
| caption "rndiff.OVL.26: Illegal rndiff device: rndiff must not overlap v20" |
| and rndiff_ill_dev v20 |
| } |
| rule "rndiff.OVL.27" { |
| caption "rndiff.OVL.27: Illegal rndiff device: rndiff must not overlap poly:model" |
| and rndiff_ill_dev polyModel |
| } |
| rule "rndiff.OVL.28" { |
| caption "rndiff.OVL.28: Illegal rndiff device: rndiff must not overlap pwde" |
| and rndiff_ill_dev pwde |
| } |
| rule "rndiff.OVL.29" { |
| caption "rndiff.OVL.29: Illegal rndiff device: rndiff must not overlap poly" |
| and rndiff_ill_dev polyi |
| } |
| rule "rndiff.OVL.30" { |
| caption "rndiff.OVL.30: Illegal rndiff device: rndiff must not overlap npc" |
| and rndiff_ill_dev npc |
| } |
| rule "rndiff.OVL.31" { |
| caption "rndiff.OVL.31: Illegal rndiff device: rndiff must not overlap li:res" |
| and rndiff_ill_dev lires |
| } |
| not ( and ( and psdm diffi ) diffres ) v5 -outputlayer rpdiff_ill_dev |
| rule "rpdiff.OVL.1" { |
| caption "rpdiff.OVL.1: Illegal rpdiff device: rpdiff must not overlap pwbm" |
| and rpdiff_ill_dev pwbm |
| } |
| rule "rpdiff.OVL.2" { |
| caption "rpdiff.OVL.2: Illegal rpdiff device: rpdiff must not overlap hvtp" |
| and rpdiff_ill_dev hvtp |
| } |
| rule "rpdiff.OVL.3" { |
| caption "rpdiff.OVL.3: Illegal rpdiff device: rpdiff must not overlap lvtn" |
| and rpdiff_ill_dev lvtn |
| } |
| rule "rpdiff.OVL.4" { |
| caption "rpdiff.OVL.4: Illegal rpdiff device: rpdiff must not overlap tunm" |
| and rpdiff_ill_dev tunm |
| } |
| rule "rpdiff.OVL.5" { |
| caption "rpdiff.OVL.5: Illegal rpdiff device: rpdiff must not overlap thkox" |
| and rpdiff_ill_dev thkox |
| } |
| rule "rpdiff.OVL.6" { |
| caption "rpdiff.OVL.6: Illegal rpdiff device: rpdiff must not overlap rpm" |
| and rpdiff_ill_dev rpm |
| } |
| rule "rpdiff.OVL.7" { |
| caption "rpdiff.OVL.7: Illegal rpdiff device: rpdiff must not overlap rrpm" |
| and rpdiff_ill_dev rrpm |
| } |
| rule "rpdiff.OVL.8" { |
| caption "rpdiff.OVL.8: Illegal rpdiff device: rpdiff must not overlap urpm" |
| and rpdiff_ill_dev urpm |
| } |
| rule "rpdiff.OVL.9" { |
| caption "rpdiff.OVL.9: Illegal rpdiff device: rpdiff must not overlap ldntm" |
| and rpdiff_ill_dev ldntm |
| } |
| rule "rpdiff.OVL.10" { |
| caption "rpdiff.OVL.10: Illegal rpdiff device: rpdiff must not overlap nsdm" |
| and rpdiff_ill_dev nsdm |
| } |
| rule "rpdiff.OVL.11" { |
| caption "rpdiff.OVL.11: Illegal rpdiff device: rpdiff must not overlap nsm" |
| and rpdiff_ill_dev nsm |
| } |
| rule "rpdiff.OVL.12" { |
| caption "rpdiff.OVL.12: Illegal rpdiff device: rpdiff must not overlap skip_pad" |
| and rpdiff_ill_dev skip_pad |
| } |
| rule "rpdiff.OVL.13" { |
| caption "rpdiff.OVL.13: Illegal rpdiff device: rpdiff must not overlap fuse" |
| and rpdiff_ill_dev fuse |
| } |
| rule "rpdiff.OVL.14" { |
| caption "rpdiff.OVL.14: Illegal rpdiff device: rpdiff must not overlap poly:res" |
| and rpdiff_ill_dev polyres |
| } |
| rule "rpdiff.OVL.15" { |
| caption "rpdiff.OVL.15: Illegal rpdiff device: rpdiff must not overlap areaid:lvNative" |
| and rpdiff_ill_dev LVID |
| } |
| rule "rpdiff.OVL.16" { |
| caption "rpdiff.OVL.16: Illegal rpdiff device: rpdiff must not overlap pnp" |
| and rpdiff_ill_dev pnp |
| } |
| rule "rpdiff.OVL.17" { |
| caption "rpdiff.OVL.17: Illegal rpdiff device: rpdiff must not overlap npn" |
| and rpdiff_ill_dev npn |
| } |
| rule "rpdiff.OVL.18" { |
| caption "rpdiff.OVL.18: Illegal rpdiff device: rpdiff must not overlap areaid:diode" |
| and rpdiff_ill_dev DiodeID |
| } |
| rule "rpdiff.OVL.19" { |
| caption "rpdiff.OVL.19: Illegal rpdiff device: rpdiff must not overlap areaid:photo" |
| and rpdiff_ill_dev PHdiodeID |
| } |
| rule "rpdiff.OVL.20" { |
| caption "rpdiff.OVL.20: Illegal rpdiff device: rpdiff must not overlap areaid:core" |
| and rpdiff_ill_dev COREID |
| } |
| rule "rpdiff.OVL.21" { |
| caption "rpdiff.OVL.21: Illegal rpdiff device: rpdiff must not overlap areaid:extendedDrain" |
| and rpdiff_ill_dev ENID |
| } |
| rule "rpdiff.OVL.22" { |
| caption "rpdiff.OVL.22: Illegal rpdiff device: rpdiff must not overlap areaid:seal" |
| and rpdiff_ill_dev SEALID |
| } |
| rule "rpdiff.OVL.23" { |
| caption "rpdiff.OVL.23: Illegal rpdiff device: rpdiff must not overlap v5" |
| and rpdiff_ill_dev v5 |
| } |
| rule "rpdiff.OVL.24" { |
| caption "rpdiff.OVL.24: Illegal rpdiff device: rpdiff must not overlap v12" |
| and rpdiff_ill_dev v12 |
| } |
| rule "rpdiff.OVL.25" { |
| caption "rpdiff.OVL.25: Illegal rpdiff device: rpdiff must not overlap v20" |
| and rpdiff_ill_dev v20 |
| } |
| rule "rpdiff.OVL.26" { |
| caption "rpdiff.OVL.26: Illegal rpdiff device: rpdiff must not overlap poly:model" |
| and rpdiff_ill_dev polyModel |
| } |
| rule "rpdiff.OVL.27" { |
| caption "rpdiff.OVL.27: Illegal rpdiff device: rpdiff must not overlap pwde" |
| and rpdiff_ill_dev pwde |
| } |
| rule "rpdiff.OVL.28" { |
| caption "rpdiff.OVL.28: Illegal rpdiff device: rpdiff must not overlap poly" |
| and rpdiff_ill_dev polyi |
| } |
| rule "rpdiff.OVL.29" { |
| caption "rpdiff.OVL.29: Illegal rpdiff device: rpdiff must not overlap npc" |
| and rpdiff_ill_dev npc |
| } |
| rule "rpdiff.OVL.30" { |
| caption "rpdiff.OVL.30: Illegal rpdiff device: rpdiff must not overlap li:res" |
| and rpdiff_ill_dev lires |
| } |
| and ( and ( and nsdm diffi ) diffres ) v5 -outputlayer rndiff_v5 |
| copy 5000 -outputlayer id_dummy3 |
| rule "rndiff_v5.OVL.1" { |
| caption "rndiff_v5.OVL.1: Illegal rndiff_v5 device: rndiff_v5 must not overlap pwbm" |
| and rndiff_v5 pwbm |
| } |
| rule "rndiff_v5.OVL.2" { |
| caption "rndiff_v5.OVL.2: Illegal rndiff_v5 device: rndiff_v5 must not overlap nwell" |
| and rndiff_v5 nwell |
| } |
| rule "rndiff_v5.OVL.3" { |
| caption "rndiff_v5.OVL.3: Illegal rndiff_v5 device: rndiff_v5 must not overlap hvtp" |
| and rndiff_v5 hvtp |
| } |
| rule "rndiff_v5.OVL.4" { |
| caption "rndiff_v5.OVL.4: Illegal rndiff_v5 device: rndiff_v5 must not overlap lvtn" |
| and rndiff_v5 lvtn |
| } |
| rule "rndiff_v5.OVL.5" { |
| caption "rndiff_v5.OVL.5: Illegal rndiff_v5 device: rndiff_v5 must not overlap tunm" |
| and rndiff_v5 tunm |
| } |
| rule "rndiff_v5.OVL.6" { |
| caption "rndiff_v5.OVL.6: Illegal rndiff_v5 device: rndiff_v5 must not overlap id_dummy3" |
| and rndiff_v5 id_dummy3 |
| } |
| rule "rndiff_v5.OVL.7" { |
| caption "rndiff_v5.OVL.7: Illegal rndiff_v5 device: rndiff_v5 must not overlap rpm" |
| and rndiff_v5 rpm |
| } |
| rule "rndiff_v5.OVL.8" { |
| caption "rndiff_v5.OVL.8: Illegal rndiff_v5 device: rndiff_v5 must not overlap rrpm" |
| and rndiff_v5 rrpm |
| } |
| rule "rndiff_v5.OVL.9" { |
| caption "rndiff_v5.OVL.9: Illegal rndiff_v5 device: rndiff_v5 must not overlap urpm" |
| and rndiff_v5 urpm |
| } |
| rule "rndiff_v5.OVL.10" { |
| caption "rndiff_v5.OVL.10: Illegal rndiff_v5 device: rndiff_v5 must not overlap ldntm" |
| and rndiff_v5 ldntm |
| } |
| rule "rndiff_v5.OVL.11" { |
| caption "rndiff_v5.OVL.11: Illegal rndiff_v5 device: rndiff_v5 must not overlap psdm" |
| and rndiff_v5 psdm |
| } |
| rule "rndiff_v5.OVL.12" { |
| caption "rndiff_v5.OVL.12: Illegal rndiff_v5 device: rndiff_v5 must not overlap nsm" |
| and rndiff_v5 nsm |
| } |
| rule "rndiff_v5.OVL.13" { |
| caption "rndiff_v5.OVL.13: Illegal rndiff_v5 device: rndiff_v5 must not overlap skip_pad" |
| and rndiff_v5 skip_pad |
| } |
| rule "rndiff_v5.OVL.14" { |
| caption "rndiff_v5.OVL.14: Illegal rndiff_v5 device: rndiff_v5 must not overlap fuse" |
| and rndiff_v5 fuse |
| } |
| rule "rndiff_v5.OVL.15" { |
| caption "rndiff_v5.OVL.15: Illegal rndiff_v5 device: rndiff_v5 must not overlap poly:res" |
| and rndiff_v5 polyres |
| } |
| rule "rndiff_v5.OVL.16" { |
| caption "rndiff_v5.OVL.16: Illegal rndiff_v5 device: rndiff_v5 must not overlap areaid:lvNative" |
| and rndiff_v5 LVID |
| } |
| rule "rndiff_v5.OVL.17" { |
| caption "rndiff_v5.OVL.17: Illegal rndiff_v5 device: rndiff_v5 must not overlap pnp" |
| and rndiff_v5 pnp |
| } |
| rule "rndiff_v5.OVL.18" { |
| caption "rndiff_v5.OVL.18: Illegal rndiff_v5 device: rndiff_v5 must not overlap npn" |
| and rndiff_v5 npn |
| } |
| rule "rndiff_v5.OVL.19" { |
| caption "rndiff_v5.OVL.19: Illegal rndiff_v5 device: rndiff_v5 must not overlap areaid:diode" |
| and rndiff_v5 DiodeID |
| } |
| rule "rndiff_v5.OVL.20" { |
| caption "rndiff_v5.OVL.20: Illegal rndiff_v5 device: rndiff_v5 must not overlap areaid:photo" |
| and rndiff_v5 PHdiodeID |
| } |
| rule "rndiff_v5.OVL.21" { |
| caption "rndiff_v5.OVL.21: Illegal rndiff_v5 device: rndiff_v5 must not overlap areaid:core" |
| and rndiff_v5 COREID |
| } |
| rule "rndiff_v5.OVL.22" { |
| caption "rndiff_v5.OVL.22: Illegal rndiff_v5 device: rndiff_v5 must not overlap areaid:extendedDrain" |
| and rndiff_v5 ENID |
| } |
| rule "rndiff_v5.OVL.23" { |
| caption "rndiff_v5.OVL.23: Illegal rndiff_v5 device: rndiff_v5 must not overlap areaid:seal" |
| and rndiff_v5 SEALID |
| } |
| rule "rndiff_v5.OVL.24" { |
| caption "rndiff_v5.OVL.24: Illegal rndiff_v5 device: rndiff_v5 must not overlap v12" |
| and rndiff_v5 v12 |
| } |
| rule "rndiff_v5.OVL.25" { |
| caption "rndiff_v5.OVL.25: Illegal rndiff_v5 device: rndiff_v5 must not overlap v20" |
| and rndiff_v5 v20 |
| } |
| rule "rndiff_v5.OVL.26" { |
| caption "rndiff_v5.OVL.26: Illegal rndiff_v5 device: rndiff_v5 must not overlap poly:model" |
| and rndiff_v5 polyModel |
| } |
| rule "rndiff_v5.OVL.27" { |
| caption "rndiff_v5.OVL.27: Illegal rndiff_v5 device: rndiff_v5 must not overlap pwde" |
| and rndiff_v5 pwde |
| } |
| rule "rndiff_v5.OVL.28" { |
| caption "rndiff_v5.OVL.28: Illegal rndiff_v5 device: rndiff_v5 must not overlap poly" |
| and rndiff_v5 polyi |
| } |
| rule "rndiff_v5.OVL.29" { |
| caption "rndiff_v5.OVL.29: Illegal rndiff_v5 device: rndiff_v5 must not overlap npc" |
| and rndiff_v5 npc |
| } |
| rule "rndiff_v5.OVL.30" { |
| caption "rndiff_v5.OVL.30: Illegal rndiff_v5 device: rndiff_v5 must not overlap li:res" |
| and rndiff_v5 lires |
| } |
| and ( and ( and psdm diffi ) diffres ) v5 -outputlayer rpdiff_v5 |
| rule "rpdiff_v5.OVL.1" { |
| caption "rpdiff_v5.OVL.1: Illegal rpdiff_v5 device: rpdiff_v5 must not overlap pwbm" |
| and rpdiff_v5 pwbm |
| } |
| rule "rpdiff_v5.OVL.2" { |
| caption "rpdiff_v5.OVL.2: Illegal rpdiff_v5 device: rpdiff_v5 must not overlap hvtp" |
| and rpdiff_v5 hvtp |
| } |
| rule "rpdiff_v5.OVL.3" { |
| caption "rpdiff_v5.OVL.3: Illegal rpdiff_v5 device: rpdiff_v5 must not overlap lvtn" |
| and rpdiff_v5 lvtn |
| } |
| rule "rpdiff_v5.OVL.4" { |
| caption "rpdiff_v5.OVL.4: Illegal rpdiff_v5 device: rpdiff_v5 must not overlap tunm" |
| and rpdiff_v5 tunm |
| } |
| rule "rpdiff_v5.OVL.5" { |
| caption "rpdiff_v5.OVL.5: Illegal rpdiff_v5 device: rpdiff_v5 must not overlap id_dummy3" |
| and rpdiff_v5 id_dummy3 |
| } |
| rule "rpdiff_v5.OVL.6" { |
| caption "rpdiff_v5.OVL.6: Illegal rpdiff_v5 device: rpdiff_v5 must not overlap rpm" |
| and rpdiff_v5 rpm |
| } |
| rule "rpdiff_v5.OVL.7" { |
| caption "rpdiff_v5.OVL.7: Illegal rpdiff_v5 device: rpdiff_v5 must not overlap rrpm" |
| and rpdiff_v5 rrpm |
| } |
| rule "rpdiff_v5.OVL.8" { |
| caption "rpdiff_v5.OVL.8: Illegal rpdiff_v5 device: rpdiff_v5 must not overlap urpm" |
| and rpdiff_v5 urpm |
| } |
| rule "rpdiff_v5.OVL.9" { |
| caption "rpdiff_v5.OVL.9: Illegal rpdiff_v5 device: rpdiff_v5 must not overlap ldntm" |
| and rpdiff_v5 ldntm |
| } |
| rule "rpdiff_v5.OVL.10" { |
| caption "rpdiff_v5.OVL.10: Illegal rpdiff_v5 device: rpdiff_v5 must not overlap nsdm" |
| and rpdiff_v5 nsdm |
| } |
| rule "rpdiff_v5.OVL.11" { |
| caption "rpdiff_v5.OVL.11: Illegal rpdiff_v5 device: rpdiff_v5 must not overlap nsm" |
| and rpdiff_v5 nsm |
| } |
| rule "rpdiff_v5.OVL.12" { |
| caption "rpdiff_v5.OVL.12: Illegal rpdiff_v5 device: rpdiff_v5 must not overlap skip_pad" |
| and rpdiff_v5 skip_pad |
| } |
| rule "rpdiff_v5.OVL.13" { |
| caption "rpdiff_v5.OVL.13: Illegal rpdiff_v5 device: rpdiff_v5 must not overlap fuse" |
| and rpdiff_v5 fuse |
| } |
| rule "rpdiff_v5.OVL.14" { |
| caption "rpdiff_v5.OVL.14: Illegal rpdiff_v5 device: rpdiff_v5 must not overlap poly:res" |
| and rpdiff_v5 polyres |
| } |
| rule "rpdiff_v5.OVL.15" { |
| caption "rpdiff_v5.OVL.15: Illegal rpdiff_v5 device: rpdiff_v5 must not overlap areaid:lvNative" |
| and rpdiff_v5 LVID |
| } |
| rule "rpdiff_v5.OVL.16" { |
| caption "rpdiff_v5.OVL.16: Illegal rpdiff_v5 device: rpdiff_v5 must not overlap pnp" |
| and rpdiff_v5 pnp |
| } |
| rule "rpdiff_v5.OVL.17" { |
| caption "rpdiff_v5.OVL.17: Illegal rpdiff_v5 device: rpdiff_v5 must not overlap npn" |
| and rpdiff_v5 npn |
| } |
| rule "rpdiff_v5.OVL.18" { |
| caption "rpdiff_v5.OVL.18: Illegal rpdiff_v5 device: rpdiff_v5 must not overlap areaid:diode" |
| and rpdiff_v5 DiodeID |
| } |
| rule "rpdiff_v5.OVL.19" { |
| caption "rpdiff_v5.OVL.19: Illegal rpdiff_v5 device: rpdiff_v5 must not overlap areaid:photo" |
| and rpdiff_v5 PHdiodeID |
| } |
| rule "rpdiff_v5.OVL.20" { |
| caption "rpdiff_v5.OVL.20: Illegal rpdiff_v5 device: rpdiff_v5 must not overlap areaid:core" |
| and rpdiff_v5 COREID |
| } |
| rule "rpdiff_v5.OVL.21" { |
| caption "rpdiff_v5.OVL.21: Illegal rpdiff_v5 device: rpdiff_v5 must not overlap areaid:extendedDrain" |
| and rpdiff_v5 ENID |
| } |
| rule "rpdiff_v5.OVL.22" { |
| caption "rpdiff_v5.OVL.22: Illegal rpdiff_v5 device: rpdiff_v5 must not overlap areaid:seal" |
| and rpdiff_v5 SEALID |
| } |
| rule "rpdiff_v5.OVL.23" { |
| caption "rpdiff_v5.OVL.23: Illegal rpdiff_v5 device: rpdiff_v5 must not overlap v12" |
| and rpdiff_v5 v12 |
| } |
| rule "rpdiff_v5.OVL.24" { |
| caption "rpdiff_v5.OVL.24: Illegal rpdiff_v5 device: rpdiff_v5 must not overlap v20" |
| and rpdiff_v5 v20 |
| } |
| rule "rpdiff_v5.OVL.25" { |
| caption "rpdiff_v5.OVL.25: Illegal rpdiff_v5 device: rpdiff_v5 must not overlap poly:model" |
| and rpdiff_v5 polyModel |
| } |
| rule "rpdiff_v5.OVL.26" { |
| caption "rpdiff_v5.OVL.26: Illegal rpdiff_v5 device: rpdiff_v5 must not overlap pwde" |
| and rpdiff_v5 pwde |
| } |
| rule "rpdiff_v5.OVL.27" { |
| caption "rpdiff_v5.OVL.27: Illegal rpdiff_v5 device: rpdiff_v5 must not overlap poly" |
| and rpdiff_v5 polyi |
| } |
| rule "rpdiff_v5.OVL.28" { |
| caption "rpdiff_v5.OVL.28: Illegal rpdiff_v5 device: rpdiff_v5 must not overlap npc" |
| and rpdiff_v5 npc |
| } |
| rule "rpdiff_v5.OVL.29" { |
| caption "rpdiff_v5.OVL.29: Illegal rpdiff_v5 device: rpdiff_v5 must not overlap li:res" |
| and rpdiff_v5 lires |
| } |
| and ( and pwres psdm ) ( and ( holes nwell ) dnwell ) -outputlayer rpwell |
| copy 4998 -outputlayer id_dummy2 |
| rule "rpwell.OVL.1" { |
| caption "rpwell.OVL.1: Illegal rpwell device: rpwell must not overlap pwbm" |
| and rpwell pwbm |
| } |
| rule "rpwell.OVL.2" { |
| caption "rpwell.OVL.2: Illegal rpwell device: rpwell must not overlap pwde" |
| and rpwell pwde |
| } |
| rule "rpwell.OVL.3" { |
| caption "rpwell.OVL.3: Illegal rpwell device: rpwell must not overlap hvtp" |
| and rpwell hvtp |
| } |
| rule "rpwell.OVL.4" { |
| caption "rpwell.OVL.4: Illegal rpwell device: rpwell must not overlap lvtn" |
| and rpwell lvtn |
| } |
| rule "rpwell.OVL.5" { |
| caption "rpwell.OVL.5: Illegal rpwell device: rpwell must not overlap tunm" |
| and rpwell tunm |
| } |
| rule "rpwell.OVL.6" { |
| caption "rpwell.OVL.6: Illegal rpwell device: rpwell must not overlap thkox" |
| and rpwell thkox |
| } |
| rule "rpwell.OVL.7" { |
| caption "rpwell.OVL.7: Illegal rpwell device: rpwell must not overlap rpm" |
| and rpwell rpm |
| } |
| rule "rpwell.OVL.8" { |
| caption "rpwell.OVL.8: Illegal rpwell device: rpwell must not overlap rrpm" |
| and rpwell rrpm |
| } |
| rule "rpwell.OVL.9" { |
| caption "rpwell.OVL.9: Illegal rpwell device: rpwell must not overlap urpm" |
| and rpwell urpm |
| } |
| rule "rpwell.OVL.10" { |
| caption "rpwell.OVL.10: Illegal rpwell device: rpwell must not overlap poly" |
| and rpwell polyi |
| } |
| rule "rpwell.OVL.11" { |
| caption "rpwell.OVL.11: Illegal rpwell device: rpwell must not overlap ldntm" |
| and rpwell ldntm |
| } |
| rule "rpwell.OVL.12" { |
| caption "rpwell.OVL.12: Illegal rpwell device: rpwell must not overlap npc" |
| and rpwell npc |
| } |
| rule "rpwell.OVL.13" { |
| caption "rpwell.OVL.13: Illegal rpwell device: rpwell must not overlap nsm" |
| and rpwell nsm |
| } |
| rule "rpwell.OVL.14" { |
| caption "rpwell.OVL.14: Illegal rpwell device: rpwell must not overlap skip_pad" |
| and rpwell skip_pad |
| } |
| rule "rpwell.OVL.15" { |
| caption "rpwell.OVL.15: Illegal rpwell device: rpwell must not overlap fuse" |
| and rpwell fuse |
| } |
| rule "rpwell.OVL.16" { |
| caption "rpwell.OVL.16: Illegal rpwell device: rpwell must not overlap poly:res" |
| and rpwell polyres |
| } |
| rule "rpwell.OVL.17" { |
| caption "rpwell.OVL.17: Illegal rpwell device: rpwell must not overlap areaid:lvNative" |
| and rpwell LVID |
| } |
| rule "rpwell.OVL.18" { |
| caption "rpwell.OVL.18: Illegal rpwell device: rpwell must not overlap id_dummy" |
| and rpwell id_dummy |
| } |
| rule "rpwell.OVL.19" { |
| caption "rpwell.OVL.19: Illegal rpwell device: rpwell must not overlap id_dummy2" |
| and rpwell id_dummy2 |
| } |
| rule "rpwell.OVL.20" { |
| caption "rpwell.OVL.20: Illegal rpwell device: rpwell must not overlap areaid:photo" |
| and rpwell PHdiodeID |
| } |
| rule "rpwell.OVL.21" { |
| caption "rpwell.OVL.21: Illegal rpwell device: rpwell must not overlap areaid:core" |
| and rpwell COREID |
| } |
| rule "rpwell.OVL.22" { |
| caption "rpwell.OVL.22: Illegal rpwell device: rpwell must not overlap areaid:extendedDrain" |
| and rpwell ENID |
| } |
| rule "rpwell.OVL.23" { |
| caption "rpwell.OVL.23: Illegal rpwell device: rpwell must not overlap areaid:seal" |
| and rpwell SEALID |
| } |
| rule "rpwell.OVL.24" { |
| caption "rpwell.OVL.24: Illegal rpwell device: rpwell must not overlap v5" |
| and rpwell v5 |
| } |
| rule "rpwell.OVL.25" { |
| caption "rpwell.OVL.25: Illegal rpwell device: rpwell must not overlap v12" |
| and rpwell v12 |
| } |
| rule "rpwell.OVL.26" { |
| caption "rpwell.OVL.26: Illegal rpwell device: rpwell must not overlap v20" |
| and rpwell v20 |
| } |
| rule "rpwell.OVL.27" { |
| caption "rpwell.OVL.27: Illegal rpwell device: rpwell must not overlap poly:model" |
| and rpwell polyModel |
| } |
| rule "rpwell.OVL.28" { |
| caption "rpwell.OVL.28: Illegal rpwell device: rpwell must not overlap nwell" |
| and rpwell nwell |
| } |
| rule "rpwell.OVL.29" { |
| caption "rpwell.OVL.29: Illegal rpwell device: rpwell must not overlap diff:res" |
| and rpwell diffres |
| } |
| rule "rpwell.OVL.30" { |
| caption "rpwell.OVL.30: Illegal rpwell device: rpwell must not overlap li:res" |
| and rpwell lires |
| } |
| |
| |
| // CAP: |
| |
| |
| |
| and ( and met3 met4 ) capm -outputlayer cap_34a |
| rule "capm3m4.OVL.1" { |
| caption "capm3m4.OVL.1: Illegal capm3m4 device: capm3m4 must not overlap nsm" |
| and cap_34a nsm |
| } |
| rule "capm3m4.OVL.2" { |
| caption "capm3m4.OVL.2: Illegal capm3m4 device: capm3m4 must not overlap skip_pad" |
| and cap_34a skip_pad |
| } |
| rule "capm3m4.OVL.3" { |
| caption "capm3m4.OVL.3: Illegal capm3m4 device: capm3m4 must not overlap areaid:lvNative" |
| and cap_34a LVID |
| } |
| rule "capm3m4.OVL.4" { |
| caption "capm3m4.OVL.4: Illegal capm3m4 device: capm3m4 must not overlap areaid:photo" |
| and cap_34a PHdiodeID |
| } |
| rule "capm3m4.OVL.5" { |
| caption "capm3m4.OVL.5: Illegal capm3m4 device: capm3m4 must not overlap areaid:core" |
| and cap_34a COREID |
| } |
| rule "capm3m4.OVL.6" { |
| caption "capm3m4.OVL.6: Illegal capm3m4 device: capm3m4 must not overlap areaid:extendedDrain" |
| and cap_34a ENID |
| } |
| rule "capm3m4.OVL.7" { |
| caption "capm3m4.OVL.7: Illegal capm3m4 device: capm3m4 must not overlap fuse" |
| and cap_34a fuse |
| } |
| rule "capm3m4.OVL.8" { |
| caption "capm3m4.OVL.8: Illegal capm3m4 device: capm3m4 must not overlap areaid:seal" |
| and cap_34a SEALID |
| } |
| rule "capm3m4.OVL.9" { |
| caption "capm3m4.OVL.9: Illegal capm3m4 device: capm3m4 must not overlap poly:model" |
| and cap_34a polyModel |
| } |
| and ( and met4 met5 ) cap2m -outputlayer cap_45a |
| rule "capm4m5.OVL.1" { |
| caption "capm4m5.OVL.1: Illegal capm4m5 device: capm4m5 must not overlap nsm" |
| and cap_45a nsm |
| } |
| rule "capm4m5.OVL.2" { |
| caption "capm4m5.OVL.2: Illegal capm4m5 device: capm4m5 must not overlap skip_pad" |
| and cap_45a skip_pad |
| } |
| rule "capm4m5.OVL.3" { |
| caption "capm4m5.OVL.3: Illegal capm4m5 device: capm4m5 must not overlap areaid:lvNative" |
| and cap_45a LVID |
| } |
| rule "capm4m5.OVL.4" { |
| caption "capm4m5.OVL.4: Illegal capm4m5 device: capm4m5 must not overlap areaid:photo" |
| and cap_45a PHdiodeID |
| } |
| rule "capm4m5.OVL.5" { |
| caption "capm4m5.OVL.5: Illegal capm4m5 device: capm4m5 must not overlap areaid:core" |
| and cap_45a COREID |
| } |
| rule "capm4m5.OVL.6" { |
| caption "capm4m5.OVL.6: Illegal capm4m5 device: capm4m5 must not overlap areaid:extendedDrain" |
| and cap_45a ENID |
| } |
| rule "capm4m5.OVL.7" { |
| caption "capm4m5.OVL.7: Illegal capm4m5 device: capm4m5 must not overlap fuse" |
| and cap_45a fuse |
| } |
| rule "capm4m5.OVL.8" { |
| caption "capm4m5.OVL.8: Illegal capm4m5 device: capm4m5 must not overlap areaid:seal" |
| and cap_45a SEALID |
| } |
| rule "capm4m5.OVL.9" { |
| caption "capm4m5.OVL.9: Illegal capm4m5 device: capm4m5 must not overlap poly:model" |
| and cap_45a polyModel |
| } |
| |
| |
| // DIO: |
| |
| |
| |
| not ( and ( not ( and diodeID nsdm ) nwell ) diffi ) ( or ESDID v5 v12 v20 lvtn hvtp LVID ) -outputlayer diode_dnsd_pw |
| rule "dnsd_pw.OVL.1" { |
| caption "dnsd_pw.OVL.1: Illegal dnsd_pw device: dnsd_pw must not overlap pwbm" |
| and diode_dnsd_pw pwbm |
| } |
| rule "dnsd_pw.OVL.2" { |
| caption "dnsd_pw.OVL.2: Illegal dnsd_pw device: dnsd_pw must not overlap nwell" |
| and diode_dnsd_pw nwell |
| } |
| rule "dnsd_pw.OVL.3" { |
| caption "dnsd_pw.OVL.3: Illegal dnsd_pw device: dnsd_pw must not overlap hvtp" |
| and diode_dnsd_pw hvtp |
| } |
| rule "dnsd_pw.OVL.4" { |
| caption "dnsd_pw.OVL.4: Illegal dnsd_pw device: dnsd_pw must not overlap lvtn" |
| and diode_dnsd_pw lvtn |
| } |
| rule "dnsd_pw.OVL.5" { |
| caption "dnsd_pw.OVL.5: Illegal dnsd_pw device: dnsd_pw must not overlap tunm" |
| and diode_dnsd_pw tunm |
| } |
| rule "dnsd_pw.OVL.6" { |
| caption "dnsd_pw.OVL.6: Illegal dnsd_pw device: dnsd_pw must not overlap thkox" |
| and diode_dnsd_pw thkox |
| } |
| rule "dnsd_pw.OVL.7" { |
| caption "dnsd_pw.OVL.7: Illegal dnsd_pw device: dnsd_pw must not overlap rpm" |
| and diode_dnsd_pw rpm |
| } |
| rule "dnsd_pw.OVL.8" { |
| caption "dnsd_pw.OVL.8: Illegal dnsd_pw device: dnsd_pw must not overlap rrpm" |
| and diode_dnsd_pw rrpm |
| } |
| rule "dnsd_pw.OVL.9" { |
| caption "dnsd_pw.OVL.9: Illegal dnsd_pw device: dnsd_pw must not overlap urpm" |
| and diode_dnsd_pw urpm |
| } |
| rule "dnsd_pw.OVL.10" { |
| caption "dnsd_pw.OVL.10: Illegal dnsd_pw device: dnsd_pw must not overlap poly" |
| and diode_dnsd_pw polyi |
| } |
| rule "dnsd_pw.OVL.11" { |
| caption "dnsd_pw.OVL.11: Illegal dnsd_pw device: dnsd_pw must not overlap ldntm" |
| and diode_dnsd_pw ldntm |
| } |
| rule "dnsd_pw.OVL.12" { |
| caption "dnsd_pw.OVL.12: Illegal dnsd_pw device: dnsd_pw must not overlap psdm" |
| and diode_dnsd_pw psdm |
| } |
| rule "dnsd_pw.OVL.13" { |
| caption "dnsd_pw.OVL.13: Illegal dnsd_pw device: dnsd_pw must not overlap nsm" |
| and diode_dnsd_pw nsm |
| } |
| rule "dnsd_pw.OVL.14" { |
| caption "dnsd_pw.OVL.14: Illegal dnsd_pw device: dnsd_pw must not overlap skip_pad" |
| and diode_dnsd_pw skip_pad |
| } |
| rule "dnsd_pw.OVL.15" { |
| caption "dnsd_pw.OVL.15: Illegal dnsd_pw device: dnsd_pw must not overlap fuse" |
| and diode_dnsd_pw fuse |
| } |
| rule "dnsd_pw.OVL.16" { |
| caption "dnsd_pw.OVL.16: Illegal dnsd_pw device: dnsd_pw must not overlap diff:res" |
| and diode_dnsd_pw diffres |
| } |
| rule "dnsd_pw.OVL.17" { |
| caption "dnsd_pw.OVL.17: Illegal dnsd_pw device: dnsd_pw must not overlap poly:res" |
| and diode_dnsd_pw polyres |
| } |
| rule "dnsd_pw.OVL.18" { |
| caption "dnsd_pw.OVL.18: Illegal dnsd_pw device: dnsd_pw must not overlap li:res" |
| and diode_dnsd_pw lires |
| } |
| rule "dnsd_pw.OVL.19" { |
| caption "dnsd_pw.OVL.19: Illegal dnsd_pw device: dnsd_pw must not overlap areaid:lvNative" |
| and diode_dnsd_pw LVID |
| } |
| rule "dnsd_pw.OVL.20" { |
| caption "dnsd_pw.OVL.20: Illegal dnsd_pw device: dnsd_pw must not overlap pnp" |
| and diode_dnsd_pw pnp |
| } |
| rule "dnsd_pw.OVL.21" { |
| caption "dnsd_pw.OVL.21: Illegal dnsd_pw device: dnsd_pw must not overlap npn" |
| and diode_dnsd_pw npn |
| } |
| rule "dnsd_pw.OVL.22" { |
| caption "dnsd_pw.OVL.22: Illegal dnsd_pw device: dnsd_pw must not overlap areaid:photo" |
| and diode_dnsd_pw PHdiodeID |
| } |
| rule "dnsd_pw.OVL.23" { |
| caption "dnsd_pw.OVL.23: Illegal dnsd_pw device: dnsd_pw must not overlap areaid:extendedDrain" |
| and diode_dnsd_pw ENID |
| } |
| rule "dnsd_pw.OVL.24" { |
| caption "dnsd_pw.OVL.24: Illegal dnsd_pw device: dnsd_pw must not overlap v5" |
| and diode_dnsd_pw v5 |
| } |
| rule "dnsd_pw.OVL.25" { |
| caption "dnsd_pw.OVL.25: Illegal dnsd_pw device: dnsd_pw must not overlap v12" |
| and diode_dnsd_pw v12 |
| } |
| rule "dnsd_pw.OVL.26" { |
| caption "dnsd_pw.OVL.26: Illegal dnsd_pw device: dnsd_pw must not overlap v20" |
| and diode_dnsd_pw v20 |
| } |
| rule "dnsd_pw.OVL.27" { |
| caption "dnsd_pw.OVL.27: Illegal dnsd_pw device: dnsd_pw must not overlap npc" |
| and diode_dnsd_pw npc |
| } |
| rule "dnsd_pw.OVL.28" { |
| caption "dnsd_pw.OVL.28: Illegal dnsd_pw device: dnsd_pw must not overlap areaid:seal" |
| and diode_dnsd_pw SEALID |
| } |
| rule "dnsd_pw.OVL.29" { |
| caption "dnsd_pw.OVL.29: Illegal dnsd_pw device: dnsd_pw must not overlap poly:model" |
| and diode_dnsd_pw polyModel |
| } |
| not ( and ( and ( and ( not ( and diodeID nsdm ) nwell ) diffi ) v5 ) thkox ) ( or v12 v20 lvtn hvtp ESDID LVID ) -outputlayer diode_dnsd_pw_v5 |
| rule "dnsd_pw_v5.OVL.1" { |
| caption "dnsd_pw_v5.OVL.1: Illegal dnsd_pw_v5 device: dnsd_pw_v5 must not overlap pwbm" |
| and diode_dnsd_pw_v5 pwbm |
| } |
| rule "dnsd_pw_v5.OVL.2" { |
| caption "dnsd_pw_v5.OVL.2: Illegal dnsd_pw_v5 device: dnsd_pw_v5 must not overlap nwell" |
| and diode_dnsd_pw_v5 nwell |
| } |
| rule "dnsd_pw_v5.OVL.3" { |
| caption "dnsd_pw_v5.OVL.3: Illegal dnsd_pw_v5 device: dnsd_pw_v5 must not overlap hvtp" |
| and diode_dnsd_pw_v5 hvtp |
| } |
| rule "dnsd_pw_v5.OVL.4" { |
| caption "dnsd_pw_v5.OVL.4: Illegal dnsd_pw_v5 device: dnsd_pw_v5 must not overlap lvtn" |
| and diode_dnsd_pw_v5 lvtn |
| } |
| rule "dnsd_pw_v5.OVL.5" { |
| caption "dnsd_pw_v5.OVL.5: Illegal dnsd_pw_v5 device: dnsd_pw_v5 must not overlap tunm" |
| and diode_dnsd_pw_v5 tunm |
| } |
| rule "dnsd_pw_v5.OVL.6" { |
| caption "dnsd_pw_v5.OVL.6: Illegal dnsd_pw_v5 device: dnsd_pw_v5 must not overlap rpm" |
| and diode_dnsd_pw_v5 rpm |
| } |
| rule "dnsd_pw_v5.OVL.7" { |
| caption "dnsd_pw_v5.OVL.7: Illegal dnsd_pw_v5 device: dnsd_pw_v5 must not overlap rrpm" |
| and diode_dnsd_pw_v5 rrpm |
| } |
| rule "dnsd_pw_v5.OVL.8" { |
| caption "dnsd_pw_v5.OVL.8: Illegal dnsd_pw_v5 device: dnsd_pw_v5 must not overlap urpm" |
| and diode_dnsd_pw_v5 urpm |
| } |
| rule "dnsd_pw_v5.OVL.9" { |
| caption "dnsd_pw_v5.OVL.9: Illegal dnsd_pw_v5 device: dnsd_pw_v5 must not overlap poly" |
| and diode_dnsd_pw_v5 polyi |
| } |
| rule "dnsd_pw_v5.OVL.10" { |
| caption "dnsd_pw_v5.OVL.10: Illegal dnsd_pw_v5 device: dnsd_pw_v5 must not overlap ldntm" |
| and diode_dnsd_pw_v5 ldntm |
| } |
| rule "dnsd_pw_v5.OVL.11" { |
| caption "dnsd_pw_v5.OVL.11: Illegal dnsd_pw_v5 device: dnsd_pw_v5 must not overlap psdm" |
| and diode_dnsd_pw_v5 psdm |
| } |
| rule "dnsd_pw_v5.OVL.12" { |
| caption "dnsd_pw_v5.OVL.12: Illegal dnsd_pw_v5 device: dnsd_pw_v5 must not overlap nsm" |
| and diode_dnsd_pw_v5 nsm |
| } |
| rule "dnsd_pw_v5.OVL.13" { |
| caption "dnsd_pw_v5.OVL.13: Illegal dnsd_pw_v5 device: dnsd_pw_v5 must not overlap skip_pad" |
| and diode_dnsd_pw_v5 skip_pad |
| } |
| rule "dnsd_pw_v5.OVL.14" { |
| caption "dnsd_pw_v5.OVL.14: Illegal dnsd_pw_v5 device: dnsd_pw_v5 must not overlap fuse" |
| and diode_dnsd_pw_v5 fuse |
| } |
| rule "dnsd_pw_v5.OVL.15" { |
| caption "dnsd_pw_v5.OVL.15: Illegal dnsd_pw_v5 device: dnsd_pw_v5 must not overlap diff:res" |
| and diode_dnsd_pw_v5 diffres |
| } |
| rule "dnsd_pw_v5.OVL.16" { |
| caption "dnsd_pw_v5.OVL.16: Illegal dnsd_pw_v5 device: dnsd_pw_v5 must not overlap poly:res" |
| and diode_dnsd_pw_v5 polyres |
| } |
| rule "dnsd_pw_v5.OVL.17" { |
| caption "dnsd_pw_v5.OVL.17: Illegal dnsd_pw_v5 device: dnsd_pw_v5 must not overlap li:res" |
| and diode_dnsd_pw_v5 lires |
| } |
| rule "dnsd_pw_v5.OVL.18" { |
| caption "dnsd_pw_v5.OVL.18: Illegal dnsd_pw_v5 device: dnsd_pw_v5 must not overlap areaid:lvNative" |
| and diode_dnsd_pw_v5 LVID |
| } |
| rule "dnsd_pw_v5.OVL.19" { |
| caption "dnsd_pw_v5.OVL.19: Illegal dnsd_pw_v5 device: dnsd_pw_v5 must not overlap pnp" |
| and diode_dnsd_pw_v5 pnp |
| } |
| rule "dnsd_pw_v5.OVL.20" { |
| caption "dnsd_pw_v5.OVL.20: Illegal dnsd_pw_v5 device: dnsd_pw_v5 must not overlap npn" |
| and diode_dnsd_pw_v5 npn |
| } |
| rule "dnsd_pw_v5.OVL.21" { |
| caption "dnsd_pw_v5.OVL.21: Illegal dnsd_pw_v5 device: dnsd_pw_v5 must not overlap areaid:photo" |
| and diode_dnsd_pw_v5 PHdiodeID |
| } |
| rule "dnsd_pw_v5.OVL.22" { |
| caption "dnsd_pw_v5.OVL.22: Illegal dnsd_pw_v5 device: dnsd_pw_v5 must not overlap areaid:core" |
| and diode_dnsd_pw_v5 COREID |
| } |
| rule "dnsd_pw_v5.OVL.23" { |
| caption "dnsd_pw_v5.OVL.23: Illegal dnsd_pw_v5 device: dnsd_pw_v5 must not overlap areaid:extendedDrain" |
| and diode_dnsd_pw_v5 ENID |
| } |
| rule "dnsd_pw_v5.OVL.24" { |
| caption "dnsd_pw_v5.OVL.24: Illegal dnsd_pw_v5 device: dnsd_pw_v5 must not overlap v12" |
| and diode_dnsd_pw_v5 v12 |
| } |
| rule "dnsd_pw_v5.OVL.25" { |
| caption "dnsd_pw_v5.OVL.25: Illegal dnsd_pw_v5 device: dnsd_pw_v5 must not overlap v20" |
| and diode_dnsd_pw_v5 v20 |
| } |
| rule "dnsd_pw_v5.OVL.26" { |
| caption "dnsd_pw_v5.OVL.26: Illegal dnsd_pw_v5 device: dnsd_pw_v5 must not overlap npc" |
| and diode_dnsd_pw_v5 npc |
| } |
| rule "dnsd_pw_v5.OVL.27" { |
| caption "dnsd_pw_v5.OVL.27: Illegal dnsd_pw_v5 device: dnsd_pw_v5 must not overlap areaid:seal" |
| and diode_dnsd_pw_v5 SEALID |
| } |
| rule "dnsd_pw_v5.OVL.28" { |
| caption "dnsd_pw_v5.OVL.28: Illegal dnsd_pw_v5 device: dnsd_pw_v5 must not overlap poly:model" |
| and diode_dnsd_pw_v5 polyModel |
| } |
| rule "dnsd_pw_v5.OVL.29" { |
| caption "dnsd_pw_v5.OVL.29: Illegal dnsd_pw_v5 device: dnsd_pw_v5 must not overlap pwde" |
| and diode_dnsd_pw_v5 pwde |
| } |
| rule "dnsd_pw_v5.OVL.30" { |
| caption "dnsd_pw_v5.OVL.30: Illegal dnsd_pw_v5 device: dnsd_pw_v5 must not overlap pwell:res" |
| and diode_dnsd_pw_v5 pwres |
| } |
| rule "dnsd_pw_v5.OVL.31" { |
| caption "dnsd_pw_v5.OVL.31: Illegal dnsd_pw_v5 device: dnsd_pw_v5 must not overlap poly:res" |
| and diode_dnsd_pw_v5 polyres |
| } |
| not ( and ( and ( not ( and diodeID nsdm ) nwell ) diffi ) lvtn ) ( or v5 v12 v20 hvtp ESDID LVID ) -outputlayer diode_dnsd_pw_lvt |
| rule "dnsd_pw_lvt.OVL.1" { |
| caption "dnsd_pw_lvt.OVL.1: Illegal dnsd_pw_lvt device: dnsd_pw_lvt must not overlap pwbm" |
| and diode_dnsd_pw_lvt pwbm |
| } |
| rule "dnsd_pw_lvt.OVL.2" { |
| caption "dnsd_pw_lvt.OVL.2: Illegal dnsd_pw_lvt device: dnsd_pw_lvt must not overlap pwde" |
| and diode_dnsd_pw_lvt pwde |
| } |
| rule "dnsd_pw_lvt.OVL.3" { |
| caption "dnsd_pw_lvt.OVL.3: Illegal dnsd_pw_lvt device: dnsd_pw_lvt must not overlap tunm" |
| and diode_dnsd_pw_lvt tunm |
| } |
| rule "dnsd_pw_lvt.OVL.4" { |
| caption "dnsd_pw_lvt.OVL.4: Illegal dnsd_pw_lvt device: dnsd_pw_lvt must not overlap rpm" |
| and diode_dnsd_pw_lvt rpm |
| } |
| rule "dnsd_pw_lvt.OVL.5" { |
| caption "dnsd_pw_lvt.OVL.5: Illegal dnsd_pw_lvt device: dnsd_pw_lvt must not overlap rrpm" |
| and diode_dnsd_pw_lvt rrpm |
| } |
| rule "dnsd_pw_lvt.OVL.6" { |
| caption "dnsd_pw_lvt.OVL.6: Illegal dnsd_pw_lvt device: dnsd_pw_lvt must not overlap urpm" |
| and diode_dnsd_pw_lvt urpm |
| } |
| rule "dnsd_pw_lvt.OVL.7" { |
| caption "dnsd_pw_lvt.OVL.7: Illegal dnsd_pw_lvt device: dnsd_pw_lvt must not overlap poly" |
| and diode_dnsd_pw_lvt polyi |
| } |
| rule "dnsd_pw_lvt.OVL.8" { |
| caption "dnsd_pw_lvt.OVL.8: Illegal dnsd_pw_lvt device: dnsd_pw_lvt must not overlap ldntm" |
| and diode_dnsd_pw_lvt ldntm |
| } |
| rule "dnsd_pw_lvt.OVL.9" { |
| caption "dnsd_pw_lvt.OVL.9: Illegal dnsd_pw_lvt device: dnsd_pw_lvt must not overlap npc" |
| and diode_dnsd_pw_lvt npc |
| } |
| rule "dnsd_pw_lvt.OVL.10" { |
| caption "dnsd_pw_lvt.OVL.10: Illegal dnsd_pw_lvt device: dnsd_pw_lvt must not overlap psdm" |
| and diode_dnsd_pw_lvt psdm |
| } |
| rule "dnsd_pw_lvt.OVL.11" { |
| caption "dnsd_pw_lvt.OVL.11: Illegal dnsd_pw_lvt device: dnsd_pw_lvt must not overlap nsm" |
| and diode_dnsd_pw_lvt nsm |
| } |
| rule "dnsd_pw_lvt.OVL.12" { |
| caption "dnsd_pw_lvt.OVL.12: Illegal dnsd_pw_lvt device: dnsd_pw_lvt must not overlap skip_pad" |
| and diode_dnsd_pw_lvt skip_pad |
| } |
| rule "dnsd_pw_lvt.OVL.13" { |
| caption "dnsd_pw_lvt.OVL.13: Illegal dnsd_pw_lvt device: dnsd_pw_lvt must not overlap fuse" |
| and diode_dnsd_pw_lvt fuse |
| } |
| rule "dnsd_pw_lvt.OVL.14" { |
| caption "dnsd_pw_lvt.OVL.14: Illegal dnsd_pw_lvt device: dnsd_pw_lvt must not overlap pwell:res" |
| and diode_dnsd_pw_lvt pwres |
| } |
| rule "dnsd_pw_lvt.OVL.15" { |
| caption "dnsd_pw_lvt.OVL.15: Illegal dnsd_pw_lvt device: dnsd_pw_lvt must not overlap poly:res" |
| and diode_dnsd_pw_lvt polyres |
| } |
| rule "dnsd_pw_lvt.OVL.16" { |
| caption "dnsd_pw_lvt.OVL.16: Illegal dnsd_pw_lvt device: dnsd_pw_lvt must not overlap poly:model" |
| and diode_dnsd_pw_lvt polyModel |
| } |
| rule "dnsd_pw_lvt.OVL.17" { |
| caption "dnsd_pw_lvt.OVL.17: Illegal dnsd_pw_lvt device: dnsd_pw_lvt must not overlap PHDiodeID" |
| and diode_dnsd_pw_lvt PHDiodeID |
| } |
| rule "dnsd_pw_lvt.OVL.18" { |
| caption "dnsd_pw_lvt.OVL.18: Illegal dnsd_pw_lvt device: dnsd_pw_lvt must not overlap areaid:extendedDrain" |
| and diode_dnsd_pw_lvt ENID |
| } |
| rule "dnsd_pw_lvt.OVL.19" { |
| caption "dnsd_pw_lvt.OVL.19: Illegal dnsd_pw_lvt device: dnsd_pw_lvt must not overlap areaid:seal" |
| and diode_dnsd_pw_lvt SEALID |
| } |
| rule "dnsd_pw_lvt.OVL.20" { |
| caption "dnsd_pw_lvt.OVL.20: Illegal dnsd_pw_lvt device: dnsd_pw_lvt must not overlap v5" |
| and diode_dnsd_pw_lvt v5 |
| } |
| rule "dnsd_pw_lvt.OVL.21" { |
| caption "dnsd_pw_lvt.OVL.21: Illegal dnsd_pw_lvt device: dnsd_pw_lvt must not overlap V12" |
| and diode_dnsd_pw_lvt V12 |
| } |
| rule "dnsd_pw_lvt.OVL.22" { |
| caption "dnsd_pw_lvt.OVL.22: Illegal dnsd_pw_lvt device: dnsd_pw_lvt must not overlap v20" |
| and diode_dnsd_pw_lvt v20 |
| } |
| not ( and ( and ( and ( not ( and diodeID nsdm ) nwell ) diffi ) LVID ) lvtn ) ( or ESDID v5 v12 v20 hvtp ) -outputlayer diode_dnsd_pw_nat |
| copy 4999 -outputlayer id_dummy |
| rule "dnsd_pw_nat.OVL.1" { |
| caption "dnsd_pw_nat.OVL.1: Illegal dnsd_pw_nat device: dnsd_pw_nat must not overlap pwbm" |
| and diode_dnsd_pw_nat pwbm |
| } |
| rule "dnsd_pw_nat.OVL.2" { |
| caption "dnsd_pw_nat.OVL.2: Illegal dnsd_pw_nat device: dnsd_pw_nat must not overlap tunm" |
| and diode_dnsd_pw_nat tunm |
| } |
| rule "dnsd_pw_nat.OVL.3" { |
| caption "dnsd_pw_nat.OVL.3: Illegal dnsd_pw_nat device: dnsd_pw_nat must not overlap id_dummy" |
| and diode_dnsd_pw_nat id_dummy |
| } |
| rule "dnsd_pw_nat.OVL.4" { |
| caption "dnsd_pw_nat.OVL.4: Illegal dnsd_pw_nat device: dnsd_pw_nat must not overlap rpm" |
| and diode_dnsd_pw_nat rpm |
| } |
| rule "dnsd_pw_nat.OVL.5" { |
| caption "dnsd_pw_nat.OVL.5: Illegal dnsd_pw_nat device: dnsd_pw_nat must not overlap rrpm" |
| and diode_dnsd_pw_nat rrpm |
| } |
| rule "dnsd_pw_nat.OVL.6" { |
| caption "dnsd_pw_nat.OVL.6: Illegal dnsd_pw_nat device: dnsd_pw_nat must not overlap urpm" |
| and diode_dnsd_pw_nat urpm |
| } |
| rule "dnsd_pw_nat.OVL.7" { |
| caption "dnsd_pw_nat.OVL.7: Illegal dnsd_pw_nat device: dnsd_pw_nat must not overlap poly" |
| and diode_dnsd_pw_nat polyi |
| } |
| rule "dnsd_pw_nat.OVL.8" { |
| caption "dnsd_pw_nat.OVL.8: Illegal dnsd_pw_nat device: dnsd_pw_nat must not overlap ldntm" |
| and diode_dnsd_pw_nat ldntm |
| } |
| rule "dnsd_pw_nat.OVL.9" { |
| caption "dnsd_pw_nat.OVL.9: Illegal dnsd_pw_nat device: dnsd_pw_nat must not overlap npc" |
| and diode_dnsd_pw_nat npc |
| } |
| rule "dnsd_pw_nat.OVL.10" { |
| caption "dnsd_pw_nat.OVL.10: Illegal dnsd_pw_nat device: dnsd_pw_nat must not overlap psdm" |
| and diode_dnsd_pw_nat psdm |
| } |
| rule "dnsd_pw_nat.OVL.11" { |
| caption "dnsd_pw_nat.OVL.11: Illegal dnsd_pw_nat device: dnsd_pw_nat must not overlap nsm" |
| and diode_dnsd_pw_nat nsm |
| } |
| rule "dnsd_pw_nat.OVL.12" { |
| caption "dnsd_pw_nat.OVL.12: Illegal dnsd_pw_nat device: dnsd_pw_nat must not overlap skip_pad" |
| and diode_dnsd_pw_nat skip_pad |
| } |
| rule "dnsd_pw_nat.OVL.13" { |
| caption "dnsd_pw_nat.OVL.13: Illegal dnsd_pw_nat device: dnsd_pw_nat must not overlap fuse" |
| and diode_dnsd_pw_nat fuse |
| } |
| rule "dnsd_pw_nat.OVL.14" { |
| caption "dnsd_pw_nat.OVL.14: Illegal dnsd_pw_nat device: dnsd_pw_nat must not overlap areaid:photo" |
| and diode_dnsd_pw_nat PHdiodeID |
| } |
| rule "dnsd_pw_nat.OVL.15" { |
| caption "dnsd_pw_nat.OVL.15: Illegal dnsd_pw_nat device: dnsd_pw_nat must not overlap areaid:extendedDrain" |
| and diode_dnsd_pw_nat ENID |
| } |
| rule "dnsd_pw_nat.OVL.16" { |
| caption "dnsd_pw_nat.OVL.16: Illegal dnsd_pw_nat device: dnsd_pw_nat must not overlap areaid:seal" |
| and diode_dnsd_pw_nat SEALID |
| } |
| rule "dnsd_pw_nat.OVL.17" { |
| caption "dnsd_pw_nat.OVL.17: Illegal dnsd_pw_nat device: dnsd_pw_nat must not overlap v5" |
| and diode_dnsd_pw_nat v5 |
| } |
| rule "dnsd_pw_nat.OVL.18" { |
| caption "dnsd_pw_nat.OVL.18: Illegal dnsd_pw_nat device: dnsd_pw_nat must not overlap v12" |
| and diode_dnsd_pw_nat v12 |
| } |
| rule "dnsd_pw_nat.OVL.19" { |
| caption "dnsd_pw_nat.OVL.19: Illegal dnsd_pw_nat device: dnsd_pw_nat must not overlap v20" |
| and diode_dnsd_pw_nat v20 |
| } |
| rule "dnsd_pw_nat.OVL.20" { |
| caption "dnsd_pw_nat.OVL.20: Illegal dnsd_pw_nat device: dnsd_pw_nat must not overlap poly:model" |
| and diode_dnsd_pw_nat polyModel |
| } |
| rule "dnsd_pw_nat.OVL.21" { |
| caption "dnsd_pw_nat.OVL.21: Illegal dnsd_pw_nat device: dnsd_pw_nat must not overlap pwde" |
| and diode_dnsd_pw_nat pwde |
| } |
| rule "dnsd_pw_nat.OVL.22" { |
| caption "dnsd_pw_nat.OVL.22: Illegal dnsd_pw_nat device: dnsd_pw_nat must not overlap pwell:res" |
| and diode_dnsd_pw_nat pwres |
| } |
| rule "dnsd_pw_nat.OVL.23" { |
| caption "dnsd_pw_nat.OVL.23: Illegal dnsd_pw_nat device: dnsd_pw_nat must not overlap poly:res" |
| and diode_dnsd_pw_nat polyres |
| } |
| not ( and ( and ( and diodeID psdm ) nwell ) diffi ) ( or thkox v5 v12 v20 lvtn hvtp ESDID LVID ) -outputlayer diode_dpsd_nw |
| rule "dpsd_nw.OVL.1" { |
| caption "dpsd_nw.OVL.1: Illegal dpsd_nw device: dpsd_nw must not overlap pwbm" |
| and diode_dpsd_nw pwbm |
| } |
| rule "dpsd_nw.OVL.2" { |
| caption "dpsd_nw.OVL.2: Illegal dpsd_nw device: dpsd_nw must not overlap hvtp" |
| and diode_dpsd_nw hvtp |
| } |
| rule "dpsd_nw.OVL.3" { |
| caption "dpsd_nw.OVL.3: Illegal dpsd_nw device: dpsd_nw must not overlap lvtn" |
| and diode_dpsd_nw lvtn |
| } |
| rule "dpsd_nw.OVL.4" { |
| caption "dpsd_nw.OVL.4: Illegal dpsd_nw device: dpsd_nw must not overlap tunm" |
| and diode_dpsd_nw tunm |
| } |
| rule "dpsd_nw.OVL.5" { |
| caption "dpsd_nw.OVL.5: Illegal dpsd_nw device: dpsd_nw must not overlap thkox" |
| and diode_dpsd_nw thkox |
| } |
| rule "dpsd_nw.OVL.6" { |
| caption "dpsd_nw.OVL.6: Illegal dpsd_nw device: dpsd_nw must not overlap rpm" |
| and diode_dpsd_nw rpm |
| } |
| rule "dpsd_nw.OVL.7" { |
| caption "dpsd_nw.OVL.7: Illegal dpsd_nw device: dpsd_nw must not overlap rrpm" |
| and diode_dpsd_nw rrpm |
| } |
| rule "dpsd_nw.OVL.8" { |
| caption "dpsd_nw.OVL.8: Illegal dpsd_nw device: dpsd_nw must not overlap urpm" |
| and diode_dpsd_nw urpm |
| } |
| rule "dpsd_nw.OVL.9" { |
| caption "dpsd_nw.OVL.9: Illegal dpsd_nw device: dpsd_nw must not overlap poly" |
| and diode_dpsd_nw polyi |
| } |
| rule "dpsd_nw.OVL.10" { |
| caption "dpsd_nw.OVL.10: Illegal dpsd_nw device: dpsd_nw must not overlap ldntm" |
| and diode_dpsd_nw ldntm |
| } |
| rule "dpsd_nw.OVL.11" { |
| caption "dpsd_nw.OVL.11: Illegal dpsd_nw device: dpsd_nw must not overlap npc" |
| and diode_dpsd_nw npc |
| } |
| rule "dpsd_nw.OVL.12" { |
| caption "dpsd_nw.OVL.12: Illegal dpsd_nw device: dpsd_nw must not overlap nsdm" |
| and diode_dpsd_nw nsdm |
| } |
| rule "dpsd_nw.OVL.13" { |
| caption "dpsd_nw.OVL.13: Illegal dpsd_nw device: dpsd_nw must not overlap nsm" |
| and diode_dpsd_nw nsm |
| } |
| rule "dpsd_nw.OVL.14" { |
| caption "dpsd_nw.OVL.14: Illegal dpsd_nw device: dpsd_nw must not overlap skip_pad" |
| and diode_dpsd_nw skip_pad |
| } |
| rule "dpsd_nw.OVL.15" { |
| caption "dpsd_nw.OVL.15: Illegal dpsd_nw device: dpsd_nw must not overlap fuse" |
| and diode_dpsd_nw fuse |
| } |
| rule "dpsd_nw.OVL.16" { |
| caption "dpsd_nw.OVL.16: Illegal dpsd_nw device: dpsd_nw must not overlap diff:res" |
| and diode_dpsd_nw diffres |
| } |
| rule "dpsd_nw.OVL.17" { |
| caption "dpsd_nw.OVL.17: Illegal dpsd_nw device: dpsd_nw must not overlap poly:res" |
| and diode_dpsd_nw polyres |
| } |
| rule "dpsd_nw.OVL.18" { |
| caption "dpsd_nw.OVL.18: Illegal dpsd_nw device: dpsd_nw must not overlap li:res" |
| and diode_dpsd_nw lires |
| } |
| rule "dpsd_nw.OVL.19" { |
| caption "dpsd_nw.OVL.19: Illegal dpsd_nw device: dpsd_nw must not overlap areaid:lvNative" |
| and diode_dpsd_nw LVID |
| } |
| rule "dpsd_nw.OVL.20" { |
| caption "dpsd_nw.OVL.20: Illegal dpsd_nw device: dpsd_nw must not overlap areaid:extendedDrain" |
| and diode_dpsd_nw ENID |
| } |
| rule "dpsd_nw.OVL.21" { |
| caption "dpsd_nw.OVL.21: Illegal dpsd_nw device: dpsd_nw must not overlap areaid:seal" |
| and diode_dpsd_nw SEALID |
| } |
| rule "dpsd_nw.OVL.22" { |
| caption "dpsd_nw.OVL.22: Illegal dpsd_nw device: dpsd_nw must not overlap v5" |
| and diode_dpsd_nw v5 |
| } |
| rule "dpsd_nw.OVL.23" { |
| caption "dpsd_nw.OVL.23: Illegal dpsd_nw device: dpsd_nw must not overlap v12" |
| and diode_dpsd_nw v12 |
| } |
| rule "dpsd_nw.OVL.24" { |
| caption "dpsd_nw.OVL.24: Illegal dpsd_nw device: dpsd_nw must not overlap v20" |
| and diode_dpsd_nw v20 |
| } |
| rule "dpsd_nw.OVL.25" { |
| caption "dpsd_nw.OVL.25: Illegal dpsd_nw device: dpsd_nw must not overlap poly:model" |
| and diode_dpsd_nw polyModel |
| } |
| rule "dpsd_nw.OVL.26" { |
| caption "dpsd_nw.OVL.26: Illegal dpsd_nw device: dpsd_nw must not overlap pwde" |
| and diode_dpsd_nw pwde |
| } |
| rule "dpsd_nw.OVL.27" { |
| caption "dpsd_nw.OVL.27: Illegal dpsd_nw device: dpsd_nw must not overlap pwell:res" |
| and diode_dpsd_nw pwres |
| } |
| rule "dpsd_nw.OVL.28" { |
| caption "dpsd_nw.OVL.28: Illegal dpsd_nw device: dpsd_nw must not overlap poly:res" |
| and diode_dpsd_nw polyres |
| } |
| rule "dpsd_nw.OVL.29" { |
| caption "dpsd_nw.OVL.29: Illegal dpsd_nw device: dpsd_nw must not overlap pnp" |
| and diode_dpsd_nw pnp |
| } |
| rule "dpsd_nw.OVL.30" { |
| caption "dpsd_nw.OVL.30: Illegal dpsd_nw device: dpsd_nw must not overlap npn" |
| and diode_dpsd_nw npn |
| } |
| not ( and ( and ( and ( and ( and diodeID psdm ) nwell ) diffi ) thkox ) v5 ) ( or v12 v20 lvtn hvtp ESDID LVID ) -outputlayer diode_dpsd_nw_v5 |
| rule "dpsd_nw_v5.OVL.1" { |
| caption "dpsd_nw_v5.OVL.1: Illegal dpsd_nw_v5 device: dpsd_nw_v5 must not overlap pwbm" |
| and diode_dpsd_nw_v5 pwbm |
| } |
| rule "dpsd_nw_v5.OVL.2" { |
| caption "dpsd_nw_v5.OVL.2: Illegal dpsd_nw_v5 device: dpsd_nw_v5 must not overlap hvtp" |
| and diode_dpsd_nw_v5 hvtp |
| } |
| rule "dpsd_nw_v5.OVL.3" { |
| caption "dpsd_nw_v5.OVL.3: Illegal dpsd_nw_v5 device: dpsd_nw_v5 must not overlap lvtn" |
| and diode_dpsd_nw_v5 lvtn |
| } |
| rule "dpsd_nw_v5.OVL.4" { |
| caption "dpsd_nw_v5.OVL.4: Illegal dpsd_nw_v5 device: dpsd_nw_v5 must not overlap tunm" |
| and diode_dpsd_nw_v5 tunm |
| } |
| rule "dpsd_nw_v5.OVL.5" { |
| caption "dpsd_nw_v5.OVL.5: Illegal dpsd_nw_v5 device: dpsd_nw_v5 must not overlap rpm" |
| and diode_dpsd_nw_v5 rpm |
| } |
| rule "dpsd_nw_v5.OVL.6" { |
| caption "dpsd_nw_v5.OVL.6: Illegal dpsd_nw_v5 device: dpsd_nw_v5 must not overlap rrpm" |
| and diode_dpsd_nw_v5 rrpm |
| } |
| rule "dpsd_nw_v5.OVL.7" { |
| caption "dpsd_nw_v5.OVL.7: Illegal dpsd_nw_v5 device: dpsd_nw_v5 must not overlap urpm" |
| and diode_dpsd_nw_v5 urpm |
| } |
| rule "dpsd_nw_v5.OVL.8" { |
| caption "dpsd_nw_v5.OVL.8: Illegal dpsd_nw_v5 device: dpsd_nw_v5 must not overlap poly" |
| and diode_dpsd_nw_v5 polyi |
| } |
| rule "dpsd_nw_v5.OVL.9" { |
| caption "dpsd_nw_v5.OVL.9: Illegal dpsd_nw_v5 device: dpsd_nw_v5 must not overlap ldntm" |
| and diode_dpsd_nw_v5 ldntm |
| } |
| rule "dpsd_nw_v5.OVL.10" { |
| caption "dpsd_nw_v5.OVL.10: Illegal dpsd_nw_v5 device: dpsd_nw_v5 must not overlap npc" |
| and diode_dpsd_nw_v5 npc |
| } |
| rule "dpsd_nw_v5.OVL.11" { |
| caption "dpsd_nw_v5.OVL.11: Illegal dpsd_nw_v5 device: dpsd_nw_v5 must not overlap nsdm" |
| and diode_dpsd_nw_v5 nsdm |
| } |
| rule "dpsd_nw_v5.OVL.12" { |
| caption "dpsd_nw_v5.OVL.12: Illegal dpsd_nw_v5 device: dpsd_nw_v5 must not overlap nsm" |
| and diode_dpsd_nw_v5 nsm |
| } |
| rule "dpsd_nw_v5.OVL.13" { |
| caption "dpsd_nw_v5.OVL.13: Illegal dpsd_nw_v5 device: dpsd_nw_v5 must not overlap skip_pad" |
| and diode_dpsd_nw_v5 skip_pad |
| } |
| rule "dpsd_nw_v5.OVL.14" { |
| caption "dpsd_nw_v5.OVL.14: Illegal dpsd_nw_v5 device: dpsd_nw_v5 must not overlap fuse" |
| and diode_dpsd_nw_v5 fuse |
| } |
| rule "dpsd_nw_v5.OVL.15" { |
| caption "dpsd_nw_v5.OVL.15: Illegal dpsd_nw_v5 device: dpsd_nw_v5 must not overlap diff:res" |
| and diode_dpsd_nw_v5 diffres |
| } |
| rule "dpsd_nw_v5.OVL.16" { |
| caption "dpsd_nw_v5.OVL.16: Illegal dpsd_nw_v5 device: dpsd_nw_v5 must not overlap poly:res" |
| and diode_dpsd_nw_v5 polyres |
| } |
| rule "dpsd_nw_v5.OVL.17" { |
| caption "dpsd_nw_v5.OVL.17: Illegal dpsd_nw_v5 device: dpsd_nw_v5 must not overlap li:res" |
| and diode_dpsd_nw_v5 lires |
| } |
| rule "dpsd_nw_v5.OVL.18" { |
| caption "dpsd_nw_v5.OVL.18: Illegal dpsd_nw_v5 device: dpsd_nw_v5 must not overlap areaid:lvNative" |
| and diode_dpsd_nw_v5 LVID |
| } |
| rule "dpsd_nw_v5.OVL.19" { |
| caption "dpsd_nw_v5.OVL.19: Illegal dpsd_nw_v5 device: dpsd_nw_v5 must not overlap areaid:extendedDrain" |
| and diode_dpsd_nw_v5 ENID |
| } |
| rule "dpsd_nw_v5.OVL.20" { |
| caption "dpsd_nw_v5.OVL.20: Illegal dpsd_nw_v5 device: dpsd_nw_v5 must not overlap areaid:seal" |
| and diode_dpsd_nw_v5 SEALID |
| } |
| rule "dpsd_nw_v5.OVL.21" { |
| caption "dpsd_nw_v5.OVL.21: Illegal dpsd_nw_v5 device: dpsd_nw_v5 must not overlap v12" |
| and diode_dpsd_nw_v5 v12 |
| } |
| rule "dpsd_nw_v5.OVL.22" { |
| caption "dpsd_nw_v5.OVL.22: Illegal dpsd_nw_v5 device: dpsd_nw_v5 must not overlap v20" |
| and diode_dpsd_nw_v5 v20 |
| } |
| rule "dpsd_nw_v5.OVL.23" { |
| caption "dpsd_nw_v5.OVL.23: Illegal dpsd_nw_v5 device: dpsd_nw_v5 must not overlap poly:model" |
| and diode_dpsd_nw_v5 polyModel |
| } |
| rule "dpsd_nw_v5.OVL.24" { |
| caption "dpsd_nw_v5.OVL.24: Illegal dpsd_nw_v5 device: dpsd_nw_v5 must not overlap pwde" |
| and diode_dpsd_nw_v5 pwde |
| } |
| rule "dpsd_nw_v5.OVL.25" { |
| caption "dpsd_nw_v5.OVL.25: Illegal dpsd_nw_v5 device: dpsd_nw_v5 must not overlap pwell:res" |
| and diode_dpsd_nw_v5 pwres |
| } |
| rule "dpsd_nw_v5.OVL.26" { |
| caption "dpsd_nw_v5.OVL.26: Illegal dpsd_nw_v5 device: dpsd_nw_v5 must not overlap pnp" |
| and diode_dpsd_nw_v5 pnp |
| } |
| rule "dpsd_nw_v5.OVL.27" { |
| caption "dpsd_nw_v5.OVL.27: Illegal dpsd_nw_v5 device: dpsd_nw_v5 must not overlap npn" |
| and diode_dpsd_nw_v5 npn |
| } |
| rule "dpsd_nw_v5.OVL.28" { |
| caption "dpsd_nw_v5.OVL.28: Illegal dpsd_nw_v5 device: dpsd_nw_v5 must not overlap areaid:photo" |
| and diode_dpsd_nw_v5 PHdiodeID |
| } |
| not ( and ( and ( and ( and diodeID psdm ) nwell ) diffi ) lvtn ) ( or thkox v5 v12 v20 hvtp ESDID LVID ) -outputlayer diode_dpsd_nw_lvt |
| rule "dpsd_nw_lvt.OVL.1" { |
| caption "dpsd_nw_lvt.OVL.1: Illegal dpsd_nw_lvt device: dpsd_nw_lvt must not overlap pwbm" |
| and diode_dpsd_nw_lvt pwbm |
| } |
| rule "dpsd_nw_lvt.OVL.2" { |
| caption "dpsd_nw_lvt.OVL.2: Illegal dpsd_nw_lvt device: dpsd_nw_lvt must not overlap hvtp" |
| and diode_dpsd_nw_lvt hvtp |
| } |
| rule "dpsd_nw_lvt.OVL.3" { |
| caption "dpsd_nw_lvt.OVL.3: Illegal dpsd_nw_lvt device: dpsd_nw_lvt must not overlap tunm" |
| and diode_dpsd_nw_lvt tunm |
| } |
| rule "dpsd_nw_lvt.OVL.4" { |
| caption "dpsd_nw_lvt.OVL.4: Illegal dpsd_nw_lvt device: dpsd_nw_lvt must not overlap rpm" |
| and diode_dpsd_nw_lvt rpm |
| } |
| rule "dpsd_nw_lvt.OVL.5" { |
| caption "dpsd_nw_lvt.OVL.5: Illegal dpsd_nw_lvt device: dpsd_nw_lvt must not overlap rrpm" |
| and diode_dpsd_nw_lvt rrpm |
| } |
| rule "dpsd_nw_lvt.OVL.6" { |
| caption "dpsd_nw_lvt.OVL.6: Illegal dpsd_nw_lvt device: dpsd_nw_lvt must not overlap urpm" |
| and diode_dpsd_nw_lvt urpm |
| } |
| rule "dpsd_nw_lvt.OVL.7" { |
| caption "dpsd_nw_lvt.OVL.7: Illegal dpsd_nw_lvt device: dpsd_nw_lvt must not overlap poly" |
| and diode_dpsd_nw_lvt polyi |
| } |
| rule "dpsd_nw_lvt.OVL.8" { |
| caption "dpsd_nw_lvt.OVL.8: Illegal dpsd_nw_lvt device: dpsd_nw_lvt must not overlap ldntm" |
| and diode_dpsd_nw_lvt ldntm |
| } |
| rule "dpsd_nw_lvt.OVL.9" { |
| caption "dpsd_nw_lvt.OVL.9: Illegal dpsd_nw_lvt device: dpsd_nw_lvt must not overlap npc" |
| and diode_dpsd_nw_lvt npc |
| } |
| rule "dpsd_nw_lvt.OVL.10" { |
| caption "dpsd_nw_lvt.OVL.10: Illegal dpsd_nw_lvt device: dpsd_nw_lvt must not overlap nsdm" |
| and diode_dpsd_nw_lvt nsdm |
| } |
| rule "dpsd_nw_lvt.OVL.11" { |
| caption "dpsd_nw_lvt.OVL.11: Illegal dpsd_nw_lvt device: dpsd_nw_lvt must not overlap nsm" |
| and diode_dpsd_nw_lvt nsm |
| } |
| rule "dpsd_nw_lvt.OVL.12" { |
| caption "dpsd_nw_lvt.OVL.12: Illegal dpsd_nw_lvt device: dpsd_nw_lvt must not overlap skip_pad" |
| and diode_dpsd_nw_lvt skip_pad |
| } |
| rule "dpsd_nw_lvt.OVL.13" { |
| caption "dpsd_nw_lvt.OVL.13: Illegal dpsd_nw_lvt device: dpsd_nw_lvt must not overlap fuse" |
| and diode_dpsd_nw_lvt fuse |
| } |
| rule "dpsd_nw_lvt.OVL.14" { |
| caption "dpsd_nw_lvt.OVL.14: Illegal dpsd_nw_lvt device: dpsd_nw_lvt must not overlap diff:res" |
| and diode_dpsd_nw_lvt diffres |
| } |
| rule "dpsd_nw_lvt.OVL.15" { |
| caption "dpsd_nw_lvt.OVL.15: Illegal dpsd_nw_lvt device: dpsd_nw_lvt must not overlap poly:res" |
| and diode_dpsd_nw_lvt polyres |
| } |
| rule "dpsd_nw_lvt.OVL.16" { |
| caption "dpsd_nw_lvt.OVL.16: Illegal dpsd_nw_lvt device: dpsd_nw_lvt must not overlap li:res" |
| and diode_dpsd_nw_lvt lires |
| } |
| rule "dpsd_nw_lvt.OVL.17" { |
| caption "dpsd_nw_lvt.OVL.17: Illegal dpsd_nw_lvt device: dpsd_nw_lvt must not overlap areaid:lvNative" |
| and diode_dpsd_nw_lvt LVID |
| } |
| rule "dpsd_nw_lvt.OVL.18" { |
| caption "dpsd_nw_lvt.OVL.18: Illegal dpsd_nw_lvt device: dpsd_nw_lvt must not overlap pnp" |
| and diode_dpsd_nw_lvt pnp |
| } |
| rule "dpsd_nw_lvt.OVL.19" { |
| caption "dpsd_nw_lvt.OVL.19: Illegal dpsd_nw_lvt device: dpsd_nw_lvt must not overlap npn" |
| and diode_dpsd_nw_lvt npn |
| } |
| rule "dpsd_nw_lvt.OVL.20" { |
| caption "dpsd_nw_lvt.OVL.20: Illegal dpsd_nw_lvt device: dpsd_nw_lvt must not overlap areaid:photo" |
| and diode_dpsd_nw_lvt PHdiodeID |
| } |
| rule "dpsd_nw_lvt.OVL.21" { |
| caption "dpsd_nw_lvt.OVL.21: Illegal dpsd_nw_lvt device: dpsd_nw_lvt must not overlap areaid:extendedDrain" |
| and diode_dpsd_nw_lvt ENID |
| } |
| rule "dpsd_nw_lvt.OVL.22" { |
| caption "dpsd_nw_lvt.OVL.22: Illegal dpsd_nw_lvt device: dpsd_nw_lvt must not overlap areaid:core" |
| and diode_dpsd_nw_lvt COREID |
| } |
| rule "dpsd_nw_lvt.OVL.23" { |
| caption "dpsd_nw_lvt.OVL.23: Illegal dpsd_nw_lvt device: dpsd_nw_lvt must not overlap areaid:seal" |
| and diode_dpsd_nw_lvt SEALID |
| } |
| rule "dpsd_nw_lvt.OVL.24" { |
| caption "dpsd_nw_lvt.OVL.24: Illegal dpsd_nw_lvt device: dpsd_nw_lvt must not overlap v5" |
| and diode_dpsd_nw_lvt v5 |
| } |
| rule "dpsd_nw_lvt.OVL.25" { |
| caption "dpsd_nw_lvt.OVL.25: Illegal dpsd_nw_lvt device: dpsd_nw_lvt must not overlap v12" |
| and diode_dpsd_nw_lvt v12 |
| } |
| rule "dpsd_nw_lvt.OVL.26" { |
| caption "dpsd_nw_lvt.OVL.26: Illegal dpsd_nw_lvt device: dpsd_nw_lvt must not overlap v20" |
| and diode_dpsd_nw_lvt v20 |
| } |
| rule "dpsd_nw_lvt.OVL.27" { |
| caption "dpsd_nw_lvt.OVL.27: Illegal dpsd_nw_lvt device: dpsd_nw_lvt must not overlap thkox" |
| and diode_dpsd_nw_lvt thkox |
| } |
| rule "dpsd_nw_lvt.OVL.28" { |
| caption "dpsd_nw_lvt.OVL.28: Illegal dpsd_nw_lvt device: dpsd_nw_lvt must not overlap poly:model" |
| and diode_dpsd_nw_lvt polyModel |
| } |
| rule "dpsd_nw_lvt.OVL.29" { |
| caption "dpsd_nw_lvt.OVL.29: Illegal dpsd_nw_lvt device: dpsd_nw_lvt must not overlap pwde" |
| and diode_dpsd_nw_lvt pwde |
| } |
| rule "dpsd_nw_lvt.OVL.30" { |
| caption "dpsd_nw_lvt.OVL.30: Illegal dpsd_nw_lvt device: dpsd_nw_lvt must not overlap pwell:res" |
| and diode_dpsd_nw_lvt pwres |
| } |
| not ( and ( and ( and ( and diodeID psdm ) nwell ) diffi ) hvtp ) ( or thkox v5 v12 v20 lvtn ESDID LVID ) -outputlayer diode_dpsd_nw_hvt |
| rule "dpsd_nw_hvt.OVL.1" { |
| caption "dpsd_nw_hvt.OVL.1: Illegal dpsd_nw_hvt device: dpsd_nw_hvt must not overlap pwbm" |
| and diode_dpsd_nw_hvt pwbm |
| } |
| rule "dpsd_nw_hvt.OVL.2" { |
| caption "dpsd_nw_hvt.OVL.2: Illegal dpsd_nw_hvt device: dpsd_nw_hvt must not overlap tunm" |
| and diode_dpsd_nw_hvt tunm |
| } |
| rule "dpsd_nw_hvt.OVL.3" { |
| caption "dpsd_nw_hvt.OVL.3: Illegal dpsd_nw_hvt device: dpsd_nw_hvt must not overlap thkox" |
| and diode_dpsd_nw_hvt thkox |
| } |
| rule "dpsd_nw_hvt.OVL.4" { |
| caption "dpsd_nw_hvt.OVL.4: Illegal dpsd_nw_hvt device: dpsd_nw_hvt must not overlap rpm" |
| and diode_dpsd_nw_hvt rpm |
| } |
| rule "dpsd_nw_hvt.OVL.5" { |
| caption "dpsd_nw_hvt.OVL.5: Illegal dpsd_nw_hvt device: dpsd_nw_hvt must not overlap rrpm" |
| and diode_dpsd_nw_hvt rrpm |
| } |
| rule "dpsd_nw_hvt.OVL.6" { |
| caption "dpsd_nw_hvt.OVL.6: Illegal dpsd_nw_hvt device: dpsd_nw_hvt must not overlap urpm" |
| and diode_dpsd_nw_hvt urpm |
| } |
| rule "dpsd_nw_hvt.OVL.7" { |
| caption "dpsd_nw_hvt.OVL.7: Illegal dpsd_nw_hvt device: dpsd_nw_hvt must not overlap poly" |
| and diode_dpsd_nw_hvt polyi |
| } |
| rule "dpsd_nw_hvt.OVL.8" { |
| caption "dpsd_nw_hvt.OVL.8: Illegal dpsd_nw_hvt device: dpsd_nw_hvt must not overlap ldntm" |
| and diode_dpsd_nw_hvt ldntm |
| } |
| rule "dpsd_nw_hvt.OVL.9" { |
| caption "dpsd_nw_hvt.OVL.9: Illegal dpsd_nw_hvt device: dpsd_nw_hvt must not overlap npc" |
| and diode_dpsd_nw_hvt npc |
| } |
| rule "dpsd_nw_hvt.OVL.10" { |
| caption "dpsd_nw_hvt.OVL.10: Illegal dpsd_nw_hvt device: dpsd_nw_hvt must not overlap nsdm" |
| and diode_dpsd_nw_hvt nsdm |
| } |
| rule "dpsd_nw_hvt.OVL.11" { |
| caption "dpsd_nw_hvt.OVL.11: Illegal dpsd_nw_hvt device: dpsd_nw_hvt must not overlap nsm" |
| and diode_dpsd_nw_hvt nsm |
| } |
| rule "dpsd_nw_hvt.OVL.12" { |
| caption "dpsd_nw_hvt.OVL.12: Illegal dpsd_nw_hvt device: dpsd_nw_hvt must not overlap skip_pad" |
| and diode_dpsd_nw_hvt skip_pad |
| } |
| rule "dpsd_nw_hvt.OVL.13" { |
| caption "dpsd_nw_hvt.OVL.13: Illegal dpsd_nw_hvt device: dpsd_nw_hvt must not overlap fuse" |
| and diode_dpsd_nw_hvt fuse |
| } |
| rule "dpsd_nw_hvt.OVL.14" { |
| caption "dpsd_nw_hvt.OVL.14: Illegal dpsd_nw_hvt device: dpsd_nw_hvt must not overlap areaid:photo" |
| and diode_dpsd_nw_hvt PHdiodeID |
| } |
| rule "dpsd_nw_hvt.OVL.15" { |
| caption "dpsd_nw_hvt.OVL.15: Illegal dpsd_nw_hvt device: dpsd_nw_hvt must not overlap areaid:extendedDrain" |
| and diode_dpsd_nw_hvt ENID |
| } |
| rule "dpsd_nw_hvt.OVL.16" { |
| caption "dpsd_nw_hvt.OVL.16: Illegal dpsd_nw_hvt device: dpsd_nw_hvt must not overlap areaid:seal" |
| and diode_dpsd_nw_hvt SEALID |
| } |
| rule "dpsd_nw_hvt.OVL.17" { |
| caption "dpsd_nw_hvt.OVL.17: Illegal dpsd_nw_hvt device: dpsd_nw_hvt must not overlap v5" |
| and diode_dpsd_nw_hvt v5 |
| } |
| rule "dpsd_nw_hvt.OVL.18" { |
| caption "dpsd_nw_hvt.OVL.18: Illegal dpsd_nw_hvt device: dpsd_nw_hvt must not overlap v12" |
| and diode_dpsd_nw_hvt v12 |
| } |
| rule "dpsd_nw_hvt.OVL.19" { |
| caption "dpsd_nw_hvt.OVL.19: Illegal dpsd_nw_hvt device: dpsd_nw_hvt must not overlap v20" |
| and diode_dpsd_nw_hvt v20 |
| } |
| rule "dpsd_nw_hvt.OVL.20" { |
| caption "dpsd_nw_hvt.OVL.20: Illegal dpsd_nw_hvt device: dpsd_nw_hvt must not overlap poly:model" |
| and diode_dpsd_nw_hvt polyModel |
| } |
| rule "dpsd_nw_hvt.OVL.21" { |
| caption "dpsd_nw_hvt.OVL.21: Illegal dpsd_nw_hvt device: dpsd_nw_hvt must not overlap pwde" |
| and diode_dpsd_nw_hvt pwde |
| } |
| rule "dpsd_nw_hvt.OVL.22" { |
| caption "dpsd_nw_hvt.OVL.22: Illegal dpsd_nw_hvt device: dpsd_nw_hvt must not overlap diff:res" |
| and diode_dpsd_nw_hvt diffres |
| } |
| rule "dpsd_nw_hvt.OVL.23" { |
| caption "dpsd_nw_hvt.OVL.23: Illegal dpsd_nw_hvt device: dpsd_nw_hvt must not overlap poly:res" |
| and diode_dpsd_nw_hvt polyres |
| } |
| rule "dpsd_nw_hvt.OVL.24" { |
| caption "dpsd_nw_hvt.OVL.24: Illegal dpsd_nw_hvt device: dpsd_nw_hvt must not overlap pwell:res" |
| and diode_dpsd_nw_hvt pwres |
| } |
| rule "dpsd_nw_hvt.OVL.25" { |
| caption "dpsd_nw_hvt.OVL.25: Illegal dpsd_nw_hvt device: dpsd_nw_hvt must not overlap areaid:lvNative" |
| and diode_dpsd_nw_hvt LVID |
| } |
| rule "dpsd_nw_hvt.OVL.26" { |
| caption "dpsd_nw_hvt.OVL.26: Illegal dpsd_nw_hvt device: dpsd_nw_hvt must not overlap pnp" |
| and diode_dpsd_nw_hvt pnp |
| } |
| rule "dpsd_nw_hvt.OVL.27" { |
| caption "dpsd_nw_hvt.OVL.27: Illegal dpsd_nw_hvt device: dpsd_nw_hvt must not overlap npn" |
| and diode_dpsd_nw_hvt npn |
| } |
| rule "dpsd_nw_hvt.OVL.28" { |
| caption "dpsd_nw_hvt.OVL.28: Illegal dpsd_nw_hvt device: dpsd_nw_hvt must not overlap areaid:core" |
| and diode_dpsd_nw_hvt COREID |
| } |
| |
| |
| // BJT: |
| |
| |
| |
| not ( select -interact pnp ( rect_chk ( and pnp diffi ) -eq 0.68 -aspect -eq 1 ) ) ( or thkox v5 v12 v20 ) -outputlayer pnp1x |
| rule "pnp.OVL.1" { |
| caption "pnp.OVL.1: Illegal pnp device: pnp must not overlap dnwell" |
| and pnp1x dnwell |
| } |
| rule "pnp.OVL.2" { |
| caption "pnp.OVL.2: Illegal pnp device: pnp must not overlap pwbm" |
| and pnp1x pwbm |
| } |
| rule "pnp.OVL.3" { |
| caption "pnp.OVL.3: Illegal pnp device: pnp must not overlap pwde" |
| and pnp1x pwde |
| } |
| rule "pnp.OVL.4" { |
| caption "pnp.OVL.4: Illegal pnp device: pnp must not overlap id_dummy" |
| and pnp1x id_dummy |
| } |
| rule "pnp.OVL.5" { |
| caption "pnp.OVL.5: Illegal pnp device: pnp must not overlap lvtn" |
| and pnp1x lvtn |
| } |
| rule "pnp.OVL.6" { |
| caption "pnp.OVL.6: Illegal pnp device: pnp must not overlap tunm" |
| and pnp1x tunm |
| } |
| rule "pnp.OVL.7" { |
| caption "pnp.OVL.7: Illegal pnp device: pnp must not overlap thkox" |
| and pnp1x thkox |
| } |
| rule "pnp.OVL.8" { |
| caption "pnp.OVL.8: Illegal pnp device: pnp must not overlap rpm" |
| and pnp1x rpm |
| } |
| rule "pnp.OVL.9" { |
| caption "pnp.OVL.9: Illegal pnp device: pnp must not overlap rrpm" |
| and pnp1x rrpm |
| } |
| rule "pnp.OVL.10" { |
| caption "pnp.OVL.10: Illegal pnp device: pnp must not overlap urpm" |
| and pnp1x urpm |
| } |
| rule "pnp.OVL.11" { |
| caption "pnp.OVL.11: Illegal pnp device: pnp must not overlap poly" |
| and pnp1x polyi |
| } |
| rule "pnp.OVL.12" { |
| caption "pnp.OVL.12: Illegal pnp device: pnp must not overlap ldntm" |
| and pnp1x ldntm |
| } |
| rule "pnp.OVL.13" { |
| caption "pnp.OVL.13: Illegal pnp device: pnp must not overlap npc" |
| and pnp1x npc |
| } |
| rule "pnp.OVL.14" { |
| caption "pnp.OVL.14: Illegal pnp device: pnp must not overlap nsm" |
| and pnp1x nsm |
| } |
| rule "pnp.OVL.15" { |
| caption "pnp.OVL.15: Illegal pnp device: pnp must not overlap skip_pad" |
| and pnp1x skip_pad |
| } |
| rule "pnp.OVL.16" { |
| caption "pnp.OVL.16: Illegal pnp device: pnp must not overlap fuse" |
| and pnp1x fuse |
| } |
| rule "pnp.OVL.17" { |
| caption "pnp.OVL.17: Illegal pnp device: pnp must not overlap diff:res" |
| and pnp1x diffres |
| } |
| rule "pnp.OVL.18" { |
| caption "pnp.OVL.18: Illegal pnp device: pnp must not overlap pwell:res" |
| and pnp1x pwres |
| } |
| rule "pnp.OVL.19" { |
| caption "pnp.OVL.19: Illegal pnp device: pnp must not overlap poly:res" |
| and pnp1x polyres |
| } |
| rule "pnp.OVL.20" { |
| caption "pnp.OVL.20: Illegal pnp device: pnp must not overlap poly:model" |
| and pnp1x polyModel |
| } |
| rule "pnp.OVL.21" { |
| caption "pnp.OVL.21: Illegal pnp device: pnp must not overlap li:res" |
| and pnp1x lires |
| } |
| rule "pnp.OVL.22" { |
| caption "pnp.OVL.22: Illegal pnp device: pnp must not overlap skip_res" |
| and pnp1x skip_res |
| } |
| rule "pnp.OVL.23" { |
| caption "pnp.OVL.23: Illegal pnp device: pnp must not overlap skip_res" |
| and pnp1x skip_res |
| } |
| rule "pnp.OVL.24" { |
| caption "pnp.OVL.24: Illegal pnp device: pnp must not overlap skip_res" |
| and pnp1x skip_res |
| } |
| rule "pnp.OVL.25" { |
| caption "pnp.OVL.25: Illegal pnp device: pnp must not overlap skip_res" |
| and pnp1x skip_res |
| } |
| rule "pnp.OVL.26" { |
| caption "pnp.OVL.26: Illegal pnp device: pnp must not overlap skip_res" |
| and pnp1x skip_res |
| } |
| rule "pnp.OVL.27" { |
| caption "pnp.OVL.27: Illegal pnp device: pnp must not overlap areaid:lvNative" |
| and pnp1x LVID |
| } |
| rule "pnp.OVL.28" { |
| caption "pnp.OVL.28: Illegal pnp device: pnp must not overlap npn" |
| and pnp1x npn |
| } |
| rule "pnp.OVL.29" { |
| caption "pnp.OVL.29: Illegal pnp device: pnp must not overlap areaid:diode" |
| and pnp1x DiodeID |
| } |
| rule "pnp.OVL.30" { |
| caption "pnp.OVL.30: Illegal pnp device: pnp must not overlap areaid:photo" |
| and pnp1x PHdiodeID |
| } |
| rule "pnp.OVL.31" { |
| caption "pnp.OVL.31: Illegal pnp device: pnp must not overlap areaid:core" |
| and pnp1x COREID |
| } |
| rule "pnp.OVL.32" { |
| caption "pnp.OVL.32: Illegal pnp device: pnp must not overlap areaid:esd" |
| and pnp1x ESDID |
| } |
| rule "pnp.OVL.33" { |
| caption "pnp.OVL.33: Illegal pnp device: pnp must not overlap areaid:extendedDrain" |
| and pnp1x ENID |
| } |
| rule "pnp.OVL.34" { |
| caption "pnp.OVL.34: Illegal pnp device: pnp must not overlap areaid:seal" |
| and pnp1x SEALID |
| } |
| rule "pnp.OVL.35" { |
| caption "pnp.OVL.35: Illegal pnp device: pnp must not overlap v5" |
| and pnp1x v5 |
| } |
| rule "pnp.OVL.36" { |
| caption "pnp.OVL.36: Illegal pnp device: pnp must not overlap v12" |
| and pnp1x v12 |
| } |
| rule "pnp.OVL.37" { |
| caption "pnp.OVL.37: Illegal pnp device: pnp must not overlap v20" |
| and pnp1x v20 |
| } |
| not ( select -interact pnp ( rect_chk ( and pnp diffi ) -eq 3.4 -aspect -eq 1 ) ) ( or thkox v5 v12 v20 ) -outputlayer pnp5x |
| rule "pnp_5x.OVL.1" { |
| caption "pnp.OVL_5x.1: Illegal pnp_5x device: pnp_5x must not overlap dnwell" |
| and pnp5x dnwell |
| } |
| rule "pnp_5x.OVL.2" { |
| caption "pnp.OVL_5x.2: Illegal pnp_5x device: pnp_5x must not overlap pwbm" |
| and pnp5x pwbm |
| } |
| rule "pnp_5x.OVL.3" { |
| caption "pnp.OVL_5x.3: Illegal pnp_5x device: pnp_5x must not overlap pwde" |
| and pnp5x pwde |
| } |
| rule "pnp_5x.OVL.4" { |
| caption "pnp.OVL_5x.4: Illegal pnp_5x device: pnp_5x must not overlap id_dummy" |
| and pnp5x id_dummy |
| } |
| rule "pnp_5x.OVL.5" { |
| caption "pnp.OVL_5x.5: Illegal pnp_5x device: pnp_5x must not overlap lvtn" |
| and pnp5x lvtn |
| } |
| rule "pnp_5x.OVL.6" { |
| caption "pnp.OVL_5x.6: Illegal pnp_5x device: pnp_5x must not overlap tunm" |
| and pnp5x tunm |
| } |
| rule "pnp_5x.OVL.7" { |
| caption "pnp.OVL_5x.7: Illegal pnp_5x device: pnp_5x must not overlap thkox" |
| and pnp5x thkox |
| } |
| rule "pnp_5x.OVL.8" { |
| caption "pnp.OVL_5x.8: Illegal pnp_5x device: pnp_5x must not overlap rpm" |
| and pnp5x rpm |
| } |
| rule "pnp_5x.OVL.9" { |
| caption "pnp.OVL_5x.9: Illegal pnp_5x device: pnp_5x must not overlap rrpm" |
| and pnp5x rrpm |
| } |
| rule "pnp_5x.OVL.10" { |
| caption "pnp.OVL_5x.10: Illegal pnp_5x device: pnp_5x must not overlap urpm" |
| and pnp5x urpm |
| } |
| rule "pnp_5x.OVL.11" { |
| caption "pnp.OVL_5x.11: Illegal pnp_5x device: pnp_5x must not overlap poly" |
| and pnp5x polyi |
| } |
| rule "pnp_5x.OVL.12" { |
| caption "pnp.OVL_5x.12: Illegal pnp_5x device: pnp_5x must not overlap ldntm" |
| and pnp5x ldntm |
| } |
| rule "pnp_5x.OVL.13" { |
| caption "pnp.OVL_5x.13: Illegal pnp_5x device: pnp_5x must not overlap npc" |
| and pnp5x npc |
| } |
| rule "pnp_5x.OVL.14" { |
| caption "pnp.OVL_5x.14: Illegal pnp_5x device: pnp_5x must not overlap nsm" |
| and pnp5x nsm |
| } |
| rule "pnp_5x.OVL.15" { |
| caption "pnp.OVL_5x.15: Illegal pnp_5x device: pnp_5x must not overlap skip_pad" |
| and pnp5x skip_pad |
| } |
| rule "pnp_5x.OVL.16" { |
| caption "pnp.OVL_5x.16: Illegal pnp_5x device: pnp_5x must not overlap fuse" |
| and pnp5x fuse |
| } |
| rule "pnp_5x.OVL.17" { |
| caption "pnp.OVL_5x.17: Illegal pnp_5x device: pnp_5x must not overlap diff:res" |
| and pnp5x diffres |
| } |
| rule "pnp_5x.OVL.18" { |
| caption "pnp.OVL_5x.18: Illegal pnp_5x device: pnp_5x must not overlap pwell:res" |
| and pnp5x pwres |
| } |
| rule "pnp_5x.OVL.19" { |
| caption "pnp.OVL_5x.19: Illegal pnp_5x device: pnp_5x must not overlap poly:res" |
| and pnp5x polyres |
| } |
| rule "pnp_5x.OVL.20" { |
| caption "pnp.OVL_5x.20: Illegal pnp_5x device: pnp_5x must not overlap poly:model" |
| and pnp5x polyModel |
| } |
| rule "pnp_5x.OVL.21" { |
| caption "pnp.OVL_5x.21: Illegal pnp_5x device: pnp_5x must not overlap li:res" |
| and pnp5x lires |
| } |
| rule "pnp_5x.OVL.22" { |
| caption "pnp.OVL_5x.22: Illegal pnp_5x device: pnp_5x must not overlap skip_res" |
| and pnp5x skip_res |
| } |
| rule "pnp_5x.OVL.23" { |
| caption "pnp.OVL_5x.23: Illegal pnp_5x device: pnp_5x must not overlap skip_res" |
| and pnp5x skip_res |
| } |
| rule "pnp_5x.OVL.24" { |
| caption "pnp.OVL_5x.24: Illegal pnp_5x device: pnp_5x must not overlap skip_res" |
| and pnp5x skip_res |
| } |
| rule "pnp_5x.OVL.25" { |
| caption "pnp.OVL_5x.25: Illegal pnp_5x device: pnp_5x must not overlap skip_res" |
| and pnp5x skip_res |
| } |
| rule "pnp_5x.OVL.26" { |
| caption "pnp.OVL_5x.26: Illegal pnp_5x device: pnp_5x must not overlap skip_res" |
| and pnp5x skip_res |
| } |
| rule "pnp_5x.OVL.27" { |
| caption "pnp.OVL_5x.27: Illegal pnp_5x device: pnp_5x must not overlap areaid:lvNative" |
| and pnp5x LVID |
| } |
| rule "pnp_5x.OVL.28" { |
| caption "pnp.OVL_5x.28: Illegal pnp_5x device: pnp_5x must not overlap npn" |
| and pnp5x npn |
| } |
| rule "pnp_5x.OVL.29" { |
| caption "pnp.OVL_5x.29: Illegal pnp_5x device: pnp_5x must not overlap areaid:diode" |
| and pnp5x DiodeID |
| } |
| rule "pnp_5x.OVL.30" { |
| caption "pnp.OVL_5x.30: Illegal pnp_5x device: pnp_5x must not overlap areaid:photo" |
| and pnp5x PHdiodeID |
| } |
| rule "pnp_5x.OVL.31" { |
| caption "pnp.OVL_5x.31: Illegal pnp_5x device: pnp_5x must not overlap areaid:core" |
| and pnp5x COREID |
| } |
| rule "pnp_5x.OVL.32" { |
| caption "pnp.OVL_5x.32: Illegal pnp_5x device: pnp_5x must not overlap areaid:esd" |
| and pnp5x ESDID |
| } |
| rule "pnp_5x.OVL.33" { |
| caption "pnp.OVL_5x.33: Illegal pnp_5x device: pnp_5x must not overlap areaid:extendedDrain" |
| and pnp5x ENID |
| } |
| rule "pnp_5x.OVL.34" { |
| caption "pnp.OVL_5x.34: Illegal pnp_5x device: pnp_5x must not overlap areaid:seal" |
| and pnp5x SEALID |
| } |
| rule "pnp_5x.OVL.35" { |
| caption "pnp.OVL_5x.35: Illegal pnp_5x device: pnp_5x must not overlap v5" |
| and pnp5x v5 |
| } |
| rule "pnp_5x.OVL.36" { |
| caption "pnp.OVL_5x.36: Illegal pnp_5x device: pnp_5x must not overlap v12" |
| and pnp5x v12 |
| } |
| rule "pnp_5x.OVL.37" { |
| caption "pnp.OVL_5x.37: Illegal pnp_5x device: pnp_5x must not overlap v20" |
| and pnp5x v20 |
| } |
| select -inside ( and ( and npn diffi ) nsdm ) npn_1 -outputlayer npn_ndiff |
| not npn_ndiff nwell -outputlayer npn_emit |
| holes nwell -outputlayer donut_nw |
| select -enclose dnwell donut_nw -outputlayer dnw_over_nw_hole |
| select -enclose ( or nwell ( holes nwell ) ) dnw_over_nw_hole -outputlayer npn_1 |
| not ( select -enclose npn_1 ( area npn_emit -eq 1 ) ) ( or thkox v5 v12 v20 ) -outputlayer npn1x |
| rule "npn.OVL.1" { |
| caption "npn.OVL_5x.1: Illegal npn device: npn must not overlap pwbm" |
| and npn1x pwbm |
| } |
| rule "npn.OVL.2" { |
| caption "npn.OVL_5x.2: Illegal npn device: npn must not overlap pwde" |
| and npn1x pwde |
| } |
| rule "npn.OVL.3" { |
| caption "npn.OVL_5x.3: Illegal npn device: npn must not overlap lvtn" |
| and npn1x lvtn |
| } |
| rule "npn.OVL.4" { |
| caption "npn.OVL_5x.4: Illegal npn device: npn must not overlap tunm" |
| and npn1x tunm |
| } |
| rule "npn.OVL.5" { |
| caption "npn.OVL_5x.5: Illegal npn device: npn must not overlap rpm" |
| and npn1x rpm |
| } |
| rule "npn.OVL.6" { |
| caption "npn.OVL_5x.6: Illegal npn device: npn must not overlap rrpm" |
| and npn1x rrpm |
| } |
| rule "npn.OVL.7" { |
| caption "npn.OVL_5x.7: Illegal npn device: npn must not overlap urpm" |
| and npn1x urpm |
| } |
| rule "npn.OVL.8" { |
| caption "npn.OVL_5x.8: Illegal npn device: npn must not overlap nsm" |
| and npn1x nsm |
| } |
| rule "npn.OVL.9" { |
| caption "npn.OVL_5x.9: Illegal npn device: npn must not overlap skip_pad" |
| and npn1x skip_pad |
| } |
| rule "npn.OVL.10" { |
| caption "npn.OVL_5x.10: Illegal npn device: npn must not overlap fuse" |
| and npn1x fuse |
| } |
| rule "npn.OVL.11" { |
| caption "npn.OVL_5x.11: Illegal npn device: npn must not overlap diff:res" |
| and npn1x diffres |
| } |
| rule "npn.OVL.12" { |
| caption "npn.OVL_5x.12: Illegal npn device: npn must not overlap pwell:res" |
| and npn1x pwres |
| } |
| rule "npn.OVL.13" { |
| caption "npn.OVL_5x.13: Illegal npn device: npn must not overlap poly:res" |
| and npn1x polyres |
| } |
| rule "npn.OVL.14" { |
| caption "npn.OVL_5x.14: Illegal npn device: npn must not overlap poly:model" |
| and npn1x polyModel |
| } |
| rule "npn.OVL.15" { |
| caption "npn.OVL_5x.15: Illegal npn device: npn must not overlap li:res" |
| and npn1x lires |
| } |
| rule "npn.OVL.16" { |
| caption "npn.OVL_5x.16: Illegal npn device: npn must not overlap areaid:lvNative" |
| and npn1x LVID |
| } |
| rule "npn.OVL.17" { |
| caption "npn.OVL_5x.17: Illegal npn device: npn must not overlap pnp" |
| and npn1x pnp |
| } |
| rule "npn.OVL.18" { |
| caption "npn.OVL_5x.18: Illegal npn device: npn must not overlap areaid:diode" |
| and npn1x DiodeID |
| } |
| rule "npn.OVL.19" { |
| caption "npn.OVL_5x.19: Illegal npn device: npn must not overlap areaid:photo" |
| and npn1x PHdiodeID |
| } |
| rule "npn.OVL.20" { |
| caption "npn.OVL_5x.20: Illegal npn device: npn must not overlap areaid:core" |
| and npn1x COREID |
| } |
| rule "npn.OVL.21" { |
| caption "npn.OVL_5x.21: Illegal npn device: npn must not overlap areaid:esd" |
| and npn1x ESDID |
| } |
| rule "npn.OVL.22" { |
| caption "npn.OVL_5x.22: Illegal npn device: npn must not overlap areaid:extendedDrain" |
| and npn1x ENID |
| } |
| rule "npn.OVL.23" { |
| caption "npn.OVL_5x.23: Illegal npn device: npn must not overlap areaid:seal" |
| and npn1x SEALID |
| } |
| rule "npn.OVL.24" { |
| caption "npn.OVL_5x.24: Illegal npn device: npn must not overlap v5" |
| and npn1x v5 |
| } |
| rule "npn.OVL.25" { |
| caption "npn.OVL_5x.25: Illegal npn device: npn must not overlap v12" |
| and npn1x v12 |
| } |
| rule "npn.OVL.26" { |
| caption "npn.OVL_5x.26: Illegal npn device: npn must not overlap v20" |
| and npn1x v20 |
| } |
| rule "npn.OVL.27" { |
| caption "npn.OVL_5x.27: Illegal npn device: npn must not overlap thkox" |
| and npn1x thkox |
| } |
| rule "npn.OVL.28" { |
| caption "npn.OVL_5x.28: Illegal npn device: npn must not overlap poly" |
| and npn1x polyi |
| } |
| edge_expand ( angle npn_ndiff -eq 45 ) -outside_by 0.005 -outputlayer npn_ndiff_oct_1 |
| select -interact ( vertex -eq 8 npn_ndiff ) npn_ndiff_oct_1 -eq 4 -outputlayer npn_ndiff_oct |
| and ( select -enclose npn_1 npn_ndiff_oct ) ( and thkox v5 ) -outputlayer npn_v5 |
| rule "npn_v5.OVL.1" { |
| caption "npn.OVL_v5.1: Illegal npn_v5 device: npn_v5 must not overlap pwbm" |
| and npn_v5 pwbm |
| } |
| rule "npn_v5.OVL.2" { |
| caption "npn.OVL_v5.2: Illegal npn_v5 device: npn_v5 must not overlap pwde" |
| and npn_v5 pwde |
| } |
| rule "npn_v5.OVL.3" { |
| caption "npn.OVL_v5.3: Illegal npn_v5 device: npn_v5 must not overlap lvtn" |
| and npn_v5 lvtn |
| } |
| rule "npn_v5.OVL.4" { |
| caption "npn.OVL_v5.4: Illegal npn_v5 device: npn_v5 must not overlap tunm" |
| and npn_v5 tunm |
| } |
| rule "npn_v5.OVL.5" { |
| caption "npn.OVL_v5.5: Illegal npn_v5 device: npn_v5 must not overlap rpm" |
| and npn_v5 rpm |
| } |
| rule "npn_v5.OVL.6" { |
| caption "npn.OVL_v5.6: Illegal npn_v5 device: npn_v5 must not overlap rrpm" |
| and npn_v5 rrpm |
| } |
| rule "npn_v5.OVL.7" { |
| caption "npn.OVL_v5.7: Illegal npn_v5 device: npn_v5 must not overlap urpm" |
| and npn_v5 urpm |
| } |
| rule "npn_v5.OVL.8" { |
| caption "npn.OVL_v5.8: Illegal npn_v5 device: npn_v5 must not overlap nsm" |
| and npn_v5 nsm |
| } |
| rule "npn_v5.OVL.9" { |
| caption "npn.OVL_v5.9: Illegal npn_v5 device: npn_v5 must not overlap skip_pad" |
| and npn_v5 skip_pad |
| } |
| rule "npn_v5.OVL.10" { |
| caption "npn.OVL_v5.10: Illegal npn_v5 device: npn_v5 must not overlap fuse" |
| and npn_v5 fuse |
| } |
| rule "npn_v5.OVL.11" { |
| caption "npn.OVL_v5.11: Illegal npn_v5 device: npn_v5 must not overlap diff:res" |
| and npn_v5 diffres |
| } |
| rule "npn_v5.OVL.12" { |
| caption "npn.OVL_v5.12: Illegal npn_v5 device: npn_v5 must not overlap pwell:res" |
| and npn_v5 pwres |
| } |
| rule "npn_v5.OVL.13" { |
| caption "npn.OVL_v5.13: Illegal npn_v5 device: npn_v5 must not overlap poly:res" |
| and npn_v5 polyres |
| } |
| rule "npn_v5.OVL.14" { |
| caption "npn.OVL_v5.14: Illegal npn_v5 device: npn_v5 must not overlap poly:model" |
| and npn_v5 polyModel |
| } |
| rule "npn_v5.OVL.15" { |
| caption "npn.OVL_v5.15: Illegal npn_v5 device: npn_v5 must not overlap li:res" |
| and npn_v5 lires |
| } |
| rule "npn_v5.OVL.16" { |
| caption "npn.OVL_v5.16: Illegal npn_v5 device: npn_v5 must not overlap areaid:lvNative" |
| and npn_v5 LVID |
| } |
| rule "npn_v5.OVL.17" { |
| caption "npn.OVL_v5.17: Illegal npn_v5 device: npn_v5 must not overlap pnp" |
| and npn_v5 pnp |
| } |
| rule "npn_v5.OVL.18" { |
| caption "npn.OVL_v5.18: Illegal npn_v5 device: npn_v5 must not overlap areaid:diode" |
| and npn_v5 DiodeID |
| } |
| rule "npn_v5.OVL.19" { |
| caption "npn.OVL_v5.19: Illegal npn_v5 device: npn_v5 must not overlap areaid:photo" |
| and npn_v5 PHdiodeID |
| } |
| rule "npn_v5.OVL.20" { |
| caption "npn.OVL_v5.20: Illegal npn_v5 device: npn_v5 must not overlap areaid:core" |
| and npn_v5 COREID |
| } |
| rule "npn_v5.OVL.21" { |
| caption "npn.OVL_v5.21: Illegal npn_v5 device: npn_v5 must not overlap areaid:esd" |
| and npn_v5 ESDID |
| } |
| rule "npn_v5.OVL.22" { |
| caption "npn.OVL_v5.22: Illegal npn_v5 device: npn_v5 must not overlap areaid:extendedDrain" |
| and npn_v5 ENID |
| } |
| rule "npn_v5.OVL.23" { |
| caption "npn.OVL_v5.23: Illegal npn_v5 device: npn_v5 must not overlap areaid:seal" |
| and npn_v5 SEALID |
| } |
| rule "npn_v5.OVL.24" { |
| caption "npn.OVL_v5.24: Illegal npn_v5 device: npn_v5 must not overlap v12" |
| and npn_v5 v12 |
| } |
| rule "npn_v5.OVL.25" { |
| caption "npn.OVL_v5.25: Illegal npn_v5 device: npn_v5 must not overlap v20" |
| and npn_v5 v20 |
| } |
| not ( select -enclose npn_1 ( area npn_emit -eq 2 ) ) ( or thkox v5 v12 v20 ) -outputlayer npn_1x2 |
| rule "npn_1x2.OVL.1" { |
| caption "npn.OVL_1x2.1: Illegal npn_1x2 device: npn_1x2 must not overlap pwbm" |
| and npn_1x2 pwbm |
| } |
| rule "npn_1x2.OVL.2" { |
| caption "npn.OVL_1x2.2: Illegal npn_1x2 device: npn_1x2 must not overlap pwde" |
| and npn_1x2 pwde |
| } |
| rule "npn_1x2.OVL.3" { |
| caption "npn.OVL_1x2.3: Illegal npn_1x2 device: npn_1x2 must not overlap lvtn" |
| and npn_1x2 lvtn |
| } |
| rule "npn_1x2.OVL.4" { |
| caption "npn.OVL_1x2.4: Illegal npn_1x2 device: npn_1x2 must not overlap tunm" |
| and npn_1x2 tunm |
| } |
| rule "npn_1x2.OVL.5" { |
| caption "npn.OVL_1x2.5: Illegal npn_1x2 device: npn_1x2 must not overlap thkox" |
| and npn_1x2 thkox |
| } |
| rule "npn_1x2.OVL.6" { |
| caption "npn.OVL_1x2.6: Illegal npn_1x2 device: npn_1x2 must not overlap poly" |
| and npn_1x2 polyi |
| } |
| rule "npn_1x2.OVL.7" { |
| caption "npn.OVL_1x2.7: Illegal npn_1x2 device: npn_1x2 must not overlap nsm" |
| and npn_1x2 nsm |
| } |
| rule "npn_1x2.OVL.8" { |
| caption "npn.OVL_1x2.8: Illegal npn_1x2 device: npn_1x2 must not overlap skip_pad" |
| and npn_1x2 skip_pad |
| } |
| rule "npn_1x2.OVL.9" { |
| caption "npn.OVL_1x2.9: Illegal npn_1x2 device: npn_1x2 must not overlap fuse" |
| and npn_1x2 fuse |
| } |
| rule "npn_1x2.OVL.10" { |
| caption "npn.OVL_1x2.10: Illegal npn_1x2 device: npn_1x2 must not overlap diff:res" |
| and npn_1x2 diffres |
| } |
| rule "npn_1x2.OVL.11" { |
| caption "npn.OVL_1x2.11: Illegal npn_1x2 device: npn_1x2 must not overlap pwell:res" |
| and npn_1x2 pwres |
| } |
| rule "npn_1x2.OVL.12" { |
| caption "npn.OVL_1x2.12: Illegal npn_1x2 device: npn_1x2 must not overlap poly:res" |
| and npn_1x2 polyres |
| } |
| rule "npn_1x2.OVL.13" { |
| caption "npn.OVL_1x2.13: Illegal npn_1x2 device: npn_1x2 must not overlap poly:model" |
| and npn_1x2 polyModel |
| } |
| rule "npn_1x2.OVL.14" { |
| caption "npn.OVL_1x2.14: Illegal npn_1x2 device: npn_1x2 must not overlap li:res" |
| and npn_1x2 lires |
| } |
| rule "npn_1x2.OVL.15" { |
| caption "npn.OVL_1x2.15: Illegal npn_1x2 device: npn_1x2 must not overlap areaid:lvNative" |
| and npn_1x2 LVID |
| } |
| rule "npn_1x2.OVL.16" { |
| caption "npn.OVL_1x2.16: Illegal npn_1x2 device: npn_1x2 must not overlap pnp" |
| and npn_1x2 pnp |
| } |
| rule "npn_1x2.OVL.17" { |
| caption "npn.OVL_1x2.17: Illegal npn_1x2 device: npn_1x2 must not overlap areaid:diode" |
| and npn_1x2 DiodeID |
| } |
| rule "npn_1x2.OVL.18" { |
| caption "npn.OVL_1x2.18: Illegal npn_1x2 device: npn_1x2 must not overlap areaid:photo" |
| and npn_1x2 PHdiodeID |
| } |
| rule "npn_1x2.OVL.19" { |
| caption "npn.OVL_1x2.19: Illegal npn_1x2 device: npn_1x2 must not overlap areaid:core" |
| and npn_1x2 COREID |
| } |
| rule "npn_1x2.OVL.20" { |
| caption "npn.OVL_1x2.20: Illegal npn_1x2 device: npn_1x2 must not overlap areaid:esd" |
| and npn_1x2 ESDID |
| } |
| rule "npn_1x2.OVL.21" { |
| caption "npn.OVL_1x2.21: Illegal npn_1x2 device: npn_1x2 must not overlap areaid:extendedDrain" |
| and npn_1x2 ENID |
| } |
| rule "npn_1x2.OVL.22" { |
| caption "npn.OVL_1x2.22: Illegal npn_1x2 device: npn_1x2 must not overlap areaid:seal" |
| and npn_1x2 SEALID |
| } |
| rule "npn_1x2.OVL.23" { |
| caption "npn.OVL_1x2.23: Illegal npn_1x2 device: npn_1x2 must not overlap v5" |
| and npn_1x2 v5 |
| } |
| rule "npn_1x2.OVL.24" { |
| caption "npn.OVL_1x2.24: Illegal npn_1x2 device: npn_1x2 must not overlap v12" |
| and npn_1x2 v12 |
| } |
| rule "npn_1x2.OVL.25" { |
| caption "npn.OVL_1x2.25: Illegal npn_1x2 device: npn_1x2 must not overlap v20" |
| and npn_1x2 v20 |
| } |
| rule "npn_1x2.OVL.26" { |
| caption "npn.OVL_1x2.26: Illegal npn_1x2 device: npn_1x2 must not overlap rpm" |
| and npn_1x2 rpm |
| } |
| rule "npn_1x2.OVL.27" { |
| caption "npn.OVL_1x2.27: Illegal npn_1x2 device: npn_1x2 must not overlap rrpm" |
| and npn_1x2 rrpm |
| } |
| rule "npn_1x2.OVL.28" { |
| caption "npn.OVL_1x2.28: Illegal npn_1x2 device: npn_1x2 must not overlap urpm" |
| and npn_1x2 urpm |
| } |
| |
| |
| // PAD: |
| |
| |
| |
| rule "pad.OVL.2" { |
| caption "pad.OVL.2: Illegal pad device: pad must not overlap nsm" |
| and pad nsm |
| } |
| rule "pad.OVL.3" { |
| caption "pad.OVL.3: Illegal pad device: pad must not overlap fuse" |
| and pad fuse |
| } |
| rule "pad.OVL.4" { |
| caption "pad.OVL.4: Illegal pad device: pad must not overlap areaid:seal" |
| and pad SEALID |
| } |
| rule "pad.OVL.5" { |
| caption "pad.OVL.5: Illegal pad device: pad must not overlap met4" |
| and pad met4i |
| } |
| rule "seal.OVL.1" { |
| caption "seal.OVL.1: Illegal seal device: areaid:seal must not overlap dnwell" |
| and SEALID dnwell |
| } |
| rule "seal.OVL.2" { |
| caption "seal.OVL.2: Illegal seal device: areaid:seal must not overlap pwbm" |
| and SEALID pwbm |
| } |
| rule "seal.OVL.3" { |
| caption "seal.OVL.3: Illegal seal device: areaid:seal must not overlap pwde" |
| and SEALID pwde |
| } |
| rule "seal.OVL.4" { |
| caption "seal.OVL.4: Illegal seal device: areaid:seal must not overlap nwell" |
| and SEALID nwell |
| } |
| rule "seal.OVL.5" { |
| caption "seal.OVL.5: Illegal seal device: areaid:seal must not overlap hvtp" |
| and SEALID hvtp |
| } |
| rule "seal.OVL.6" { |
| caption "seal.OVL.6: Illegal seal device: areaid:seal must not overlap lvtn" |
| and SEALID lvtn |
| } |
| rule "seal.OVL.7" { |
| caption "seal.OVL.7: Illegal seal device: areaid:seal must not overlap tunm" |
| and SEALID tunm |
| } |
| rule "seal.OVL.8" { |
| caption "seal.OVL.8: Illegal seal device: areaid:seal must not overlap thkox" |
| and SEALID thkox |
| } |
| rule "seal.OVL.9" { |
| caption "seal.OVL.9: Illegal seal device: areaid:seal must not overlap rpm" |
| and SEALID rpm |
| } |
| rule "seal.OVL.10" { |
| caption "seal.OVL.10: Illegal seal device: areaid:seal must not overlap rrpm" |
| and SEALID rrpm |
| } |
| rule "seal.OVL.11" { |
| caption "seal.OVL.11: Illegal seal device: areaid:seal must not overlap urpm" |
| and SEALID urpm |
| } |
| rule "seal.OVL.12" { |
| caption "seal.OVL.12: Illegal seal device: areaid:seal must not overlap poly" |
| and SEALID polyi |
| } |
| rule "seal.OVL.13" { |
| caption "seal.OVL.13: Illegal seal device: areaid:seal must not overlap ldntm" |
| and SEALID ldntm |
| } |
| rule "seal.OVL.14" { |
| caption "seal.OVL.14: Illegal seal device: areaid:seal must not overlap npc" |
| and SEALID npc |
| } |
| rule "seal.OVL.15" { |
| caption "seal.OVL.15: Illegal seal device: areaid:seal must not overlap nsdm" |
| and SEALID nsdm |
| } |
| rule "seal.OVL.16" { |
| caption "seal.OVL.16: Illegal seal device: areaid:seal must not overlap psdm" |
| and SEALID psdm |
| } |
| rule "seal.OVL.17" { |
| caption "seal.OVL.17: Illegal seal device: areaid:seal must not overlap licon" |
| and SEALID licon |
| } |
| rule "seal.OVL.18" { |
| caption "seal.OVL.18: Illegal seal device: areaid:seal must not overlap li" |
| and SEALID li_i |
| } |
| rule "seal.OVL.19" { |
| caption "seal.OVL.19: Illegal seal device: areaid:seal must not overlap capm" |
| and SEALID capm |
| } |
| rule "seal.OVL.20" { |
| caption "seal.OVL.20: Illegal seal device: areaid:seal must not overlap cap2m" |
| and SEALID cap2m |
| } |
| rule "seal.OVL.21" { |
| caption "seal.OVL.21: Illegal seal device: areaid:seal must not overlap met1" |
| and SEALID met1i |
| } |
| rule "seal.OVL.22" { |
| caption "seal.OVL.22: Illegal seal device: areaid:seal must not overlap met2" |
| and SEALID met2i |
| } |
| rule "seal.OVL.23" { |
| caption "seal.OVL.23: Illegal seal device: areaid:seal must not overlap met3" |
| and SEALID met3i |
| } |
| rule "seal.OVL.24" { |
| caption "seal.OVL.24: Illegal seal device: areaid:seal must not overlap met4" |
| and SEALID met4i |
| } |
| rule "seal.OVL.25" { |
| caption "seal.OVL.25: Illegal seal device: areaid:seal must not overlap met5" |
| and SEALID met5i |
| } |
| rule "seal.OVL.26" { |
| caption "seal.OVL.26: Illegal seal device: areaid:seal must not overlap pad" |
| and SEALID pad |
| } |
| rule "seal.OVL.27" { |
| caption "seal.OVL.27: Illegal seal device: areaid:seal must not overlap rdl" |
| and SEALID rdl |
| } |
| rule "seal.OVL.28" { |
| caption "seal.OVL.28: Illegal seal device: areaid:seal must not overlap fuse" |
| and SEALID fuse |
| } |
| rule "seal.OVL.29" { |
| caption "seal.OVL.29: Illegal seal device: areaid:seal must not overlap diff:res" |
| and SEALID diffres |
| } |
| rule "seal.OVL.30" { |
| caption "seal.OVL.30: Illegal seal device: areaid:seal must not overlap pwell:res" |
| and SEALID pwres |
| } |
| rule "seal.OVL.31" { |
| caption "seal.OVL.31: Illegal seal device: areaid:seal must not overlap poly:res" |
| and SEALID polyres |
| } |
| rule "seal.OVL.32" { |
| caption "seal.OVL.32: Illegal seal device: areaid:seal must not overlap li:res" |
| and SEALID lires |
| } |
| rule "seal.OVL.33" { |
| caption "seal.OVL.33: Illegal seal device: areaid:seal must not overlap met1:res" |
| and SEALID m1res |
| } |
| rule "seal.OVL.34" { |
| caption "seal.OVL.34: Illegal seal device: areaid:seal must not overlap met2:res" |
| and SEALID m2res |
| } |
| rule "seal.OVL.35" { |
| caption "seal.OVL.35: Illegal seal device: areaid:seal must not overlap met3:res" |
| and SEALID m3res |
| } |
| rule "seal.OVL.36" { |
| caption "seal.OVL.36: Illegal seal device: areaid:seal must not overlap met4:res" |
| and SEALID m4res |
| } |
| rule "seal.OVL.37" { |
| caption "seal.OVL.37: Illegal seal device: areaid:seal must not overlap met5:res" |
| and SEALID m5res |
| } |
| rule "seal.OVL.38" { |
| caption "seal.OVL.38: Illegal seal device: areaid:seal must not overlap areaid:lvNative" |
| and SEALID LVID |
| } |
| rule "seal.OVL.39" { |
| caption "seal.OVL.39: Illegal seal device: areaid:seal must not overlap pnp" |
| and SEALID pnp |
| } |
| rule "seal.OVL.40" { |
| caption "seal.OVL.40: Illegal seal device: areaid:seal must not overlap npn" |
| and SEALID npn |
| } |
| rule "seal.OVL.41" { |
| caption "seal.OVL.41: Illegal seal device: areaid:seal must not overlap localSub" |
| and SEALID localSub |
| } |
| rule "seal.OVL.42" { |
| caption "seal.OVL.42: Illegal seal device: areaid:seal must not overlap areaid:diode" |
| and SEALID DiodeID |
| } |
| rule "seal.OVL.43" { |
| caption "seal.OVL.43: Illegal seal device: areaid:seal must not overlap areaid:photo" |
| and SEALID PHdiodeID |
| } |
| rule "seal.OVL.44" { |
| caption "seal.OVL.44: Illegal seal device: areaid:seal must not overlap areaid:core" |
| and SEALID COREID |
| } |
| rule "seal.OVL.45" { |
| caption "seal.OVL.45: Illegal seal device: areaid:seal must not overlap areaid:esd" |
| and SEALID ESDID |
| } |
| rule "seal.OVL.46" { |
| caption "seal.OVL.46: Illegal seal device: areaid:seal must not overlap areaid:extendedDrain" |
| and SEALID ENID |
| } |
| rule "seal.OVL.47" { |
| caption "seal.OVL.47: Illegal seal device: areaid:seal must not overlap v5" |
| and SEALID v5 |
| } |
| rule "seal.OVL.48" { |
| caption "seal.OVL.48: Illegal seal device: areaid:seal must not overlap v12" |
| and SEALID v12 |
| } |
| rule "seal.OVL.49" { |
| caption "seal.OVL.49: Illegal seal device: areaid:seal must not overlap v20" |
| and SEALID v20 |
| } |
| rule "seal.OVL.50" { |
| caption "seal.OVL.50: Illegal seal device: areaid:seal must not overlap poly:model" |
| and SEALID polyModel |
| } |
| |
| |
| // FUSE: |
| |
| |
| |
| |
| // ESD MOS: |
| |
| |
| |
| not ( and ( and ( and ( and gate nsdm ) v5 ) ESDID ) thkox ) ( or v12 v20 lvtn LVID pnp npn ) -outputlayer nmos_esd_5v |
| rule "nmos_esd_5v.OVL.1" { |
| caption "nmos_esd_5v.OVL.1: Illegal nmos_esd_5v device: nmos_esd_5v must not overlap pwbm" |
| and nmos_esd_5v pwbm |
| } |
| rule "nmos_esd_5v.OVL.2" { |
| caption "nmos_esd_5v.OVL.2: Illegal nmos_esd_5v device: nmos_esd_5v must not overlap pwde" |
| and nmos_esd_5v pwde |
| } |
| rule "nmos_esd_5v.OVL.3" { |
| caption "nmos_esd_5v.OVL.3: Illegal nmos_esd_5v device: nmos_esd_5v must not overlap hvtp" |
| and nmos_esd_5v hvtp |
| } |
| rule "nmos_esd_5v.OVL.4" { |
| caption "nmos_esd_5v.OVL.4: Illegal nmos_esd_5v device: nmos_esd_5v must not overlap lvtn" |
| and nmos_esd_5v lvtn |
| } |
| rule "nmos_esd_5v.OVL.5" { |
| caption "nmos_esd_5v.OVL.5: Illegal nmos_esd_5v device: nmos_esd_5v must not overlap tunm" |
| and nmos_esd_5v tunm |
| } |
| rule "nmos_esd_5v.OVL.6" { |
| caption "nmos_esd_5v.OVL.6: Illegal nmos_esd_5v device: nmos_esd_5v must not overlap rpm" |
| and nmos_esd_5v rpm |
| } |
| rule "nmos_esd_5v.OVL.7" { |
| caption "nmos_esd_5v.OVL.7: Illegal nmos_esd_5v device: nmos_esd_5v must not overlap rrpm" |
| and nmos_esd_5v rrpm |
| } |
| rule "nmos_esd_5v.OVL.8" { |
| caption "nmos_esd_5v.OVL.8: Illegal nmos_esd_5v device: nmos_esd_5v must not overlap urpm" |
| and nmos_esd_5v urpm |
| } |
| rule "nmos_esd_5v.OVL.9" { |
| caption "nmos_esd_5v.OVL.9: Illegal nmos_esd_5v device: nmos_esd_5v must not overlap ldntm" |
| and nmos_esd_5v ldntm |
| } |
| rule "nmos_esd_5v.OVL.10" { |
| caption "nmos_esd_5v.OVL.10: Illegal nmos_esd_5v device: nmos_esd_5v must not overlap npc" |
| and nmos_esd_5v npc |
| } |
| rule "nmos_esd_5v.OVL.11" { |
| caption "nmos_esd_5v.OVL.11: Illegal nmos_esd_5v device: nmos_esd_5v must not overlap psdm" |
| and nmos_esd_5v psdm |
| } |
| rule "nmos_esd_5v.OVL.12" { |
| caption "nmos_esd_5v.OVL.12: Illegal nmos_esd_5v device: nmos_esd_5v must not overlap nsm" |
| and nmos_esd_5v nsm |
| } |
| rule "nmos_esd_5v.OVL.13" { |
| caption "nmos_esd_5v.OVL.13: Illegal nmos_esd_5v device: nmos_esd_5v must not overlap skip_pad" |
| and nmos_esd_5v skip_pad |
| } |
| rule "nmos_esd_5v.OVL.14" { |
| caption "nmos_esd_5v.OVL.14: Illegal nmos_esd_5v device: nmos_esd_5v must not overlap fuse" |
| and nmos_esd_5v fuse |
| } |
| rule "nmos_esd_5v.OVL.15" { |
| caption "nmos_esd_5v.OVL.15: Illegal nmos_esd_5v device: nmos_esd_5v must not overlap diff:res" |
| and nmos_esd_5v diffres |
| } |
| rule "nmos_esd_5v.OVL.16" { |
| caption "nmos_esd_5v.OVL.16: Illegal nmos_esd_5v device: nmos_esd_5v must not overlap pwell:res" |
| and nmos_esd_5v pwres |
| } |
| rule "nmos_esd_5v.OVL.17" { |
| caption "nmos_esd_5v.OVL.17: Illegal nmos_esd_5v device: nmos_esd_5v must not overlap poly:res" |
| and nmos_esd_5v polyres |
| } |
| rule "nmos_esd_5v.OVL.18" { |
| caption "nmos_esd_5v.OVL.18: Illegal nmos_esd_5v device: nmos_esd_5v must not overlap li:res" |
| and nmos_esd_5v lires |
| } |
| rule "nmos_esd_5v.OVL.19" { |
| caption "nmos_esd_5v.OVL.19: Illegal nmos_esd_5v device: nmos_esd_5v must not overlap areaid:lvNative" |
| and nmos_esd_5v LVID |
| } |
| rule "nmos_esd_5v.OVL.20" { |
| caption "nmos_esd_5v.OVL.20: Illegal nmos_esd_5v device: nmos_esd_5v must not overlap pnp" |
| and nmos_esd_5v pnp |
| } |
| rule "nmos_esd_5v.OVL.21" { |
| caption "nmos_esd_5v.OVL.21: Illegal nmos_esd_5v device: nmos_esd_5v must not overlap npn" |
| and nmos_esd_5v npn |
| } |
| rule "nmos_esd_5v.OVL.22" { |
| caption "nmos_esd_5v.OVL.22: Illegal nmos_esd_5v device: nmos_esd_5v must not overlap areaid:diode" |
| and nmos_esd_5v DiodeID |
| } |
| rule "nmos_esd_5v.OVL.23" { |
| caption "nmos_esd_5v.OVL.23: Illegal nmos_esd_5v device: nmos_esd_5v must not overlap areaid:photo" |
| and nmos_esd_5v PHdiodeID |
| } |
| rule "nmos_esd_5v.OVL.24" { |
| caption "nmos_esd_5v.OVL.24: Illegal nmos_esd_5v device: nmos_esd_5v must not overlap areaid:core" |
| and nmos_esd_5v COREID |
| } |
| rule "nmos_esd_5v.OVL.25" { |
| caption "nmos_esd_5v.OVL.25: Illegal nmos_esd_5v device: nmos_esd_5v must not overlap areaid:extendedDrain" |
| and nmos_esd_5v ENID |
| } |
| rule "nmos_esd_5v.OVL.26" { |
| caption "nmos_esd_5v.OVL.26: Illegal nmos_esd_5v device: nmos_esd_5v must not overlap areaid:seal" |
| and nmos_esd_5v SEALID |
| } |
| rule "nmos_esd_5v.OVL.27" { |
| caption "nmos_esd_5v.OVL.27: Illegal nmos_esd_5v device: nmos_esd_5v must not overlap v12" |
| and nmos_esd_5v v12 |
| } |
| rule "nmos_esd_5v.OVL.28" { |
| caption "nmos_esd_5v.OVL.28: Illegal nmos_esd_5v device: nmos_esd_5v must not overlap v20" |
| and nmos_esd_5v v20 |
| } |
| rule "nmos_esd_5v.OVL.29" { |
| caption "nmos_esd_5v.OVL.29: Illegal nmos_esd_5v device: nmos_esd_5v must not overlap nwell" |
| and nmos_esd_5v nwell |
| } |
| not ( and ( and ( and ( and gate nsdm ) lvtn ) v5 ) thkox ) ( or v12 v20 LVID pnp npn ) -outputlayer nmos_esd_nat_5v |
| rule "nmos_esd_nat_5v.OVL.1" { |
| caption "nmos_esd_nat_5v.OVL.1: Illegal nmos_esd_nat_5v device: nmos_esd_nat_5v must not overlap pwbm" |
| and nmos_esd_nat_5v pwbm |
| } |
| rule "nmos_esd_nat_5v.OVL.2" { |
| caption "nmos_esd_nat_5v.OVL.2: Illegal nmos_esd_nat_5v device: nmos_esd_nat_5v must not overlap pwde" |
| and nmos_esd_nat_5v pwde |
| } |
| rule "nmos_esd_nat_5v.OVL.3" { |
| caption "nmos_esd_nat_5v.OVL.3: Illegal nmos_esd_nat_5v device: nmos_esd_nat_5v must not overlap nwell" |
| and nmos_esd_nat_5v nwell |
| } |
| rule "nmos_esd_nat_5v.OVL.4" { |
| caption "nmos_esd_nat_5v.OVL.4: Illegal nmos_esd_nat_5v device: nmos_esd_nat_5v must not overlap hvtp" |
| and nmos_esd_nat_5v hvtp |
| } |
| rule "nmos_esd_nat_5v.OVL.5" { |
| caption "nmos_esd_nat_5v.OVL.5: Illegal nmos_esd_nat_5v device: nmos_esd_nat_5v must not overlap tunm" |
| and nmos_esd_nat_5v tunm |
| } |
| rule "nmos_esd_nat_5v.OVL.6" { |
| caption "nmos_esd_nat_5v.OVL.6: Illegal nmos_esd_nat_5v device: nmos_esd_nat_5v must not overlap rpm" |
| and nmos_esd_nat_5v rpm |
| } |
| rule "nmos_esd_nat_5v.OVL.7" { |
| caption "nmos_esd_nat_5v.OVL.7: Illegal nmos_esd_nat_5v device: nmos_esd_nat_5v must not overlap rrpm" |
| and nmos_esd_nat_5v rrpm |
| } |
| rule "nmos_esd_nat_5v.OVL.8" { |
| caption "nmos_esd_nat_5v.OVL.8: Illegal nmos_esd_nat_5v device: nmos_esd_nat_5v must not overlap urpm" |
| and nmos_esd_nat_5v urpm |
| } |
| rule "nmos_esd_nat_5v.OVL.9" { |
| caption "nmos_esd_nat_5v.OVL.9: Illegal nmos_esd_nat_5v device: nmos_esd_nat_5v must not overlap ldntm" |
| and nmos_esd_nat_5v ldntm |
| } |
| rule "nmos_esd_nat_5v.OVL.10" { |
| caption "nmos_esd_nat_5v.OVL.10: Illegal nmos_esd_nat_5v device: nmos_esd_nat_5v must not overlap npc" |
| and nmos_esd_nat_5v npc |
| } |
| rule "nmos_esd_nat_5v.OVL.11" { |
| caption "nmos_esd_nat_5v.OVL.11: Illegal nmos_esd_nat_5v device: nmos_esd_nat_5v must not overlap psdm" |
| and nmos_esd_nat_5v psdm |
| } |
| rule "nmos_esd_nat_5v.OVL.12" { |
| caption "nmos_esd_nat_5v.OVL.12: Illegal nmos_esd_nat_5v device: nmos_esd_nat_5v must not overlap nsm" |
| and nmos_esd_nat_5v nsm |
| } |
| rule "nmos_esd_nat_5v.OVL.13" { |
| caption "nmos_esd_nat_5v.OVL.13: Illegal nmos_esd_nat_5v device: nmos_esd_nat_5v must not overlap skip_pad" |
| and nmos_esd_nat_5v skip_pad |
| } |
| rule "nmos_esd_nat_5v.OVL.14" { |
| caption "nmos_esd_nat_5v.OVL.14: Illegal nmos_esd_nat_5v device: nmos_esd_nat_5v must not overlap fuse" |
| and nmos_esd_nat_5v fuse |
| } |
| rule "nmos_esd_nat_5v.OVL.15" { |
| caption "nmos_esd_nat_5v.OVL.15: Illegal nmos_esd_nat_5v device: nmos_esd_nat_5v must not overlap diff:res" |
| and nmos_esd_nat_5v diffres |
| } |
| rule "nmos_esd_nat_5v.OVL.16" { |
| caption "nmos_esd_nat_5v.OVL.16: Illegal nmos_esd_nat_5v device: nmos_esd_nat_5v must not overlap pwell:res" |
| and nmos_esd_nat_5v pwres |
| } |
| rule "nmos_esd_nat_5v.OVL.17" { |
| caption "nmos_esd_nat_5v.OVL.17: Illegal nmos_esd_nat_5v device: nmos_esd_nat_5v must not overlap poly:res" |
| and nmos_esd_nat_5v polyres |
| } |
| rule "nmos_esd_nat_5v.OVL.18" { |
| caption "nmos_esd_nat_5v.OVL.18: Illegal nmos_esd_nat_5v device: nmos_esd_nat_5v must not overlap li:res" |
| and nmos_esd_nat_5v lires |
| } |
| rule "nmos_esd_nat_5v.OVL.19" { |
| caption "nmos_esd_nat_5v.OVL.19: Illegal nmos_esd_nat_5v device: nmos_esd_nat_5v must not overlap areaid:lvNative" |
| and nmos_esd_nat_5v LVID |
| } |
| rule "nmos_esd_nat_5v.OVL.20" { |
| caption "nmos_esd_nat_5v.OVL.20: Illegal nmos_esd_nat_5v device: nmos_esd_nat_5v must not overlap pnp" |
| and nmos_esd_nat_5v pnp |
| } |
| rule "nmos_esd_nat_5v.OVL.21" { |
| caption "nmos_esd_nat_5v.OVL.21: Illegal nmos_esd_nat_5v device: nmos_esd_nat_5v must not overlap npn" |
| and nmos_esd_nat_5v npn |
| } |
| rule "nmos_esd_nat_5v.OVL.22" { |
| caption "nmos_esd_nat_5v.OVL.22: Illegal nmos_esd_nat_5v device: nmos_esd_nat_5v must not overlap areaid:diode" |
| and nmos_esd_nat_5v DiodeID |
| } |
| rule "nmos_esd_nat_5v.OVL.23" { |
| caption "nmos_esd_nat_5v.OVL.23: Illegal nmos_esd_nat_5v device: nmos_esd_nat_5v must not overlap areaid:photo" |
| and nmos_esd_nat_5v PHdiodeID |
| } |
| rule "nmos_esd_nat_5v.OVL.24" { |
| caption "nmos_esd_nat_5v.OVL.24: Illegal nmos_esd_nat_5v device: nmos_esd_nat_5v must not overlap areaid:core" |
| and nmos_esd_nat_5v COREID |
| } |
| rule "nmos_esd_nat_5v.OVL.25" { |
| caption "nmos_esd_nat_5v.OVL.25: Illegal nmos_esd_nat_5v device: nmos_esd_nat_5v must not overlap areaid:extendedDrain" |
| and nmos_esd_nat_5v ENID |
| } |
| rule "nmos_esd_nat_5v.OVL.26" { |
| caption "nmos_esd_nat_5v.OVL.26: Illegal nmos_esd_nat_5v device: nmos_esd_nat_5v must not overlap areaid:seal" |
| and nmos_esd_nat_5v SEALID |
| } |
| rule "nmos_esd_nat_5v.OVL.27" { |
| caption "nmos_esd_nat_5v.OVL.27: Illegal nmos_esd_nat_5v device: nmos_esd_nat_5v must not overlap v12" |
| and nmos_esd_nat_5v v12 |
| } |
| rule "nmos_esd_nat_5v.OVL.28" { |
| caption "nmos_esd_nat_5v.OVL.28: Illegal nmos_esd_nat_5v device: nmos_esd_nat_5v must not overlap v20" |
| and nmos_esd_nat_5v v20 |
| } |
| not ( and ( and gate nsdm ) ESDID ) ( or v5 v12 v20 LVID pnp npn lvtn ) -outputlayer nmos_esd |
| rule "nmos_esd.OVL.1" { |
| caption "nmos_esd.OVL.1: Illegal nmos_esd device: nmos_esd must not overlap pwbm" |
| and nmos_esd pwbm |
| } |
| rule "nmos_esd.OVL.2" { |
| caption "nmos_esd.OVL.2: Illegal nmos_esd device: nmos_esd must not overlap pwde" |
| and nmos_esd pwde |
| } |
| rule "nmos_esd.OVL.3" { |
| caption "nmos_esd.OVL.3: Illegal nmos_esd device: nmos_esd must not overlap hvtp" |
| and nmos_esd hvtp |
| } |
| rule "nmos_esd.OVL.4" { |
| caption "nmos_esd.OVL.4: Illegal nmos_esd device: nmos_esd must not overlap lvtn" |
| and nmos_esd lvtn |
| } |
| rule "nmos_esd.OVL.5" { |
| caption "nmos_esd.OVL.5: Illegal nmos_esd device: nmos_esd must not overlap tunm" |
| and nmos_esd tunm |
| } |
| rule "nmos_esd.OVL.6" { |
| caption "nmos_esd.OVL.6: Illegal nmos_esd device: nmos_esd must not overlap rpm" |
| and nmos_esd rpm |
| } |
| rule "nmos_esd.OVL.7" { |
| caption "nmos_esd.OVL.7: Illegal nmos_esd device: nmos_esd must not overlap rrpm" |
| and nmos_esd rrpm |
| } |
| rule "nmos_esd.OVL.8" { |
| caption "nmos_esd.OVL.8: Illegal nmos_esd device: nmos_esd must not overlap urpm" |
| and nmos_esd urpm |
| } |
| rule "nmos_esd.OVL.9" { |
| caption "nmos_esd.OVL.9: Illegal nmos_esd device: nmos_esd must not overlap ldntm" |
| and nmos_esd ldntm |
| } |
| rule "nmos_esd.OVL.10" { |
| caption "nmos_esd.OVL.10: Illegal nmos_esd device: nmos_esd must not overlap npc" |
| and nmos_esd npc |
| } |
| rule "nmos_esd.OVL.11" { |
| caption "nmos_esd.OVL.11: Illegal nmos_esd device: nmos_esd must not overlap psdm" |
| and nmos_esd psdm |
| } |
| rule "nmos_esd.OVL.12" { |
| caption "nmos_esd.OVL.12: Illegal nmos_esd device: nmos_esd must not overlap nsm" |
| and nmos_esd nsm |
| } |
| rule "nmos_esd.OVL.13" { |
| caption "nmos_esd.OVL.13: Illegal nmos_esd device: nmos_esd must not overlap skip_pad" |
| and nmos_esd skip_pad |
| } |
| rule "nmos_esd.OVL.14" { |
| caption "nmos_esd.OVL.14: Illegal nmos_esd device: nmos_esd must not overlap fuse" |
| and nmos_esd fuse |
| } |
| rule "nmos_esd.OVL.15" { |
| caption "nmos_esd.OVL.15: Illegal nmos_esd device: nmos_esd must not overlap areaid:lvNative" |
| and nmos_esd LVID |
| } |
| rule "nmos_esd.OVL.16" { |
| caption "nmos_esd.OVL.16: Illegal nmos_esd device: nmos_esd must not overlap pnp" |
| and nmos_esd pnp |
| } |
| rule "nmos_esd.OVL.17" { |
| caption "nmos_esd.OVL.17: Illegal nmos_esd device: nmos_esd must not overlap npn" |
| and nmos_esd npn |
| } |
| rule "nmos_esd.OVL.18" { |
| caption "nmos_esd.OVL.18: Illegal nmos_esd device: nmos_esd must not overlap areaid:diode" |
| and nmos_esd DiodeID |
| } |
| rule "nmos_esd.OVL.19" { |
| caption "nmos_esd.OVL.19: Illegal nmos_esd device: nmos_esd must not overlap areaid:photo" |
| and nmos_esd PHdiodeID |
| } |
| rule "nmos_esd.OVL.20" { |
| caption "nmos_esd.OVL.20: Illegal nmos_esd device: nmos_esd must not overlap areaid:core" |
| and nmos_esd COREID |
| } |
| rule "nmos_esd.OVL.21" { |
| caption "nmos_esd.OVL.21: Illegal nmos_esd device: nmos_esd must not overlap areaid:extendedDrain" |
| and nmos_esd ENID |
| } |
| rule "nmos_esd.OVL.22" { |
| caption "nmos_esd.OVL.22: Illegal nmos_esd device: nmos_esd must not overlap areaid:seal" |
| and nmos_esd SEALID |
| } |
| rule "nmos_esd.OVL.23" { |
| caption "nmos_esd.OVL.23: Illegal nmos_esd device: nmos_esd must not overlap v5" |
| and nmos_esd v5 |
| } |
| rule "nmos_esd.OVL.24" { |
| caption "nmos_esd.OVL.24: Illegal nmos_esd device: nmos_esd must not overlap v12" |
| and nmos_esd v12 |
| } |
| rule "nmos_esd.OVL.25" { |
| caption "nmos_esd.OVL.25: Illegal nmos_esd device: nmos_esd must not overlap v20" |
| and nmos_esd v20 |
| } |
| rule "nmos_esd.OVL.26" { |
| caption "nmos_esd.OVL.26: Illegal nmos_esd device: nmos_esd must not overlap nwell" |
| and nmos_esd nwell |
| } |
| rule "nmos_esd.OVL.27" { |
| caption "nmos_esd.OVL.27: Illegal nmos_esd device: nmos_esd must not overlap thkox" |
| and nmos_esd thkox |
| } |
| not ( and ( and ( and ( and gate psdm ) v5 ) ESDID ) thkox ) ( or v12 v20 LVID npn pnp ENID ) -outputlayer pmos_esd_5v |
| rule "pmos_esd_5v.OVL.1" { |
| caption "pmos_esd_5v.OVL.1: Illegal pmos_esd_5v device: pmos_esd_5v must not overlap pwbm" |
| and pmos_esd_5v pwbm |
| } |
| rule "pmos_esd_5v.OVL.2" { |
| caption "pmos_esd_5v.OVL.2: Illegal pmos_esd_5v device: pmos_esd_5v must not overlap pwde" |
| and pmos_esd_5v pwde |
| } |
| rule "pmos_esd_5v.OVL.3" { |
| caption "pmos_esd_5v.OVL.3: Illegal pmos_esd_5v device: pmos_esd_5v must not overlap hvtp" |
| and pmos_esd_5v hvtp |
| } |
| rule "pmos_esd_5v.OVL.4" { |
| caption "pmos_esd_5v.OVL.4: Illegal pmos_esd_5v device: pmos_esd_5v must not overlap lvtn" |
| and pmos_esd_5v lvtn |
| } |
| rule "pmos_esd_5v.OVL.5" { |
| caption "pmos_esd_5v.OVL.5: Illegal pmos_esd_5v device: pmos_esd_5v must not overlap tunm" |
| and pmos_esd_5v tunm |
| } |
| rule "pmos_esd_5v.OVL.6" { |
| caption "pmos_esd_5v.OVL.6: Illegal pmos_esd_5v device: pmos_esd_5v must not overlap rpm" |
| and pmos_esd_5v rpm |
| } |
| rule "pmos_esd_5v.OVL.7" { |
| caption "pmos_esd_5v.OVL.7: Illegal pmos_esd_5v device: pmos_esd_5v must not overlap rrpm" |
| and pmos_esd_5v rrpm |
| } |
| rule "pmos_esd_5v.OVL.8" { |
| caption "pmos_esd_5v.OVL.8: Illegal pmos_esd_5v device: pmos_esd_5v must not overlap urpm" |
| and pmos_esd_5v urpm |
| } |
| rule "pmos_esd_5v.OVL.9" { |
| caption "pmos_esd_5v.OVL.9: Illegal pmos_esd_5v device: pmos_esd_5v must not overlap ldntm" |
| and pmos_esd_5v ldntm |
| } |
| rule "pmos_esd_5v.OVL.10" { |
| caption "pmos_esd_5v.OVL.10: Illegal pmos_esd_5v device: pmos_esd_5v must not overlap npc" |
| and pmos_esd_5v npc |
| } |
| rule "pmos_esd_5v.OVL.11" { |
| caption "pmos_esd_5v.OVL.11: Illegal pmos_esd_5v device: pmos_esd_5v must not overlap nsdm" |
| and pmos_esd_5v nsdm |
| } |
| rule "pmos_esd_5v.OVL.12" { |
| caption "pmos_esd_5v.OVL.12: Illegal pmos_esd_5v device: pmos_esd_5v must not overlap nsm" |
| and pmos_esd_5v nsm |
| } |
| rule "pmos_esd_5v.OVL.13" { |
| caption "pmos_esd_5v.OVL.13: Illegal pmos_esd_5v device: pmos_esd_5v must not overlap skip_pad" |
| and pmos_esd_5v skip_pad |
| } |
| rule "pmos_esd_5v.OVL.14" { |
| caption "pmos_esd_5v.OVL.14: Illegal pmos_esd_5v device: pmos_esd_5v must not overlap fuse" |
| and pmos_esd_5v fuse |
| } |
| rule "pmos_esd_5v.OVL.15" { |
| caption "pmos_esd_5v.OVL.15: Illegal pmos_esd_5v device: pmos_esd_5v must not overlap diff:res" |
| and pmos_esd_5v diffres |
| } |
| rule "pmos_esd_5v.OVL.16" { |
| caption "pmos_esd_5v.OVL.16: Illegal pmos_esd_5v device: pmos_esd_5v must not overlap pwell:res" |
| and pmos_esd_5v pwres |
| } |
| rule "pmos_esd_5v.OVL.17" { |
| caption "pmos_esd_5v.OVL.17: Illegal pmos_esd_5v device: pmos_esd_5v must not overlap poly:res" |
| and pmos_esd_5v polyres |
| } |
| rule "pmos_esd_5v.OVL.18" { |
| caption "pmos_esd_5v.OVL.18: Illegal pmos_esd_5v device: pmos_esd_5v must not overlap li:res" |
| and pmos_esd_5v lires |
| } |
| rule "pmos_esd_5v.OVL.19" { |
| caption "pmos_esd_5v.OVL.19: Illegal pmos_esd_5v device: pmos_esd_5v must not overlap areaid:lvNative" |
| and pmos_esd_5v LVID |
| } |
| rule "pmos_esd_5v.OVL.20" { |
| caption "pmos_esd_5v.OVL.20: Illegal pmos_esd_5v device: pmos_esd_5v must not overlap pnp" |
| and pmos_esd_5v pnp |
| } |
| rule "pmos_esd_5v.OVL.21" { |
| caption "pmos_esd_5v.OVL.21: Illegal pmos_esd_5v device: pmos_esd_5v must not overlap npn" |
| and pmos_esd_5v npn |
| } |
| rule "pmos_esd_5v.OVL.22" { |
| caption "pmos_esd_5v.OVL.22: Illegal pmos_esd_5v device: pmos_esd_5v must not overlap areaid:diode" |
| and pmos_esd_5v DiodeID |
| } |
| rule "pmos_esd_5v.OVL.23" { |
| caption "pmos_esd_5v.OVL.23: Illegal pmos_esd_5v device: pmos_esd_5v must not overlap areaid:photo" |
| and pmos_esd_5v PHdiodeID |
| } |
| rule "pmos_esd_5v.OVL.24" { |
| caption "pmos_esd_5v.OVL.24: Illegal pmos_esd_5v device: pmos_esd_5v must not overlap areaid:core" |
| and pmos_esd_5v COREID |
| } |
| rule "pmos_esd_5v.OVL.25" { |
| caption "pmos_esd_5v.OVL.25: Illegal pmos_esd_5v device: pmos_esd_5v must not overlap areaid:extendedDrain" |
| and pmos_esd_5v ENID |
| } |
| rule "pmos_esd_5v.OVL.26" { |
| caption "pmos_esd_5v.OVL.26: Illegal pmos_esd_5v device: pmos_esd_5v must not overlap areaid:seal" |
| and pmos_esd_5v SEALID |
| } |
| rule "pmos_esd_5v.OVL.27" { |
| caption "pmos_esd_5v.OVL.27: Illegal pmos_esd_5v device: pmos_esd_5v must not overlap v12" |
| and pmos_esd_5v v12 |
| } |
| rule "pmos_esd_5v.OVL.28" { |
| caption "pmos_esd_5v.OVL.28: Illegal pmos_esd_5v device: pmos_esd_5v must not overlap v20" |
| and pmos_esd_5v v20 |
| } |
| rule "pmos_esd_5v.OVL.29" { |
| caption "pmos_esd_5v.OVL.29: Illegal pmos_esd_5v device: pmos_esd_5v must not overlap poly:model" |
| and pmos_esd_5v polyModel |
| } |
| not ( and ( and ( not ( and diodeID nsdm ) nwell ) diffi ) ESDID ) ( or v5 v12 v20 lvtn hvtp LVID ) -outputlayer nsd_pw_esd |
| rule "dnsd_pw_esd.OVL.1" { |
| caption "nsd_pw_esd.OVL.1: Illegal nsd_pw_esd device: nsd_pw_esd must not overlap pwbm" |
| and nsd_pw_esd pwbm |
| } |
| rule "dnsd_pw_esd.OVL.2" { |
| caption "nsd_pw_esd.OVL.2: Illegal nsd_pw_esd device: nsd_pw_esd must not overlap hvtp" |
| and nsd_pw_esd hvtp |
| } |
| rule "dnsd_pw_esd.OVL.3" { |
| caption "nsd_pw_esd.OVL.3: Illegal nsd_pw_esd device: nsd_pw_esd must not overlap lvtn" |
| and nsd_pw_esd lvtn |
| } |
| rule "dnsd_pw_esd.OVL.4" { |
| caption "nsd_pw_esd.OVL.4: Illegal nsd_pw_esd device: nsd_pw_esd must not overlap tunm" |
| and nsd_pw_esd tunm |
| } |
| rule "dnsd_pw_esd.OVL.5" { |
| caption "nsd_pw_esd.OVL.5: Illegal nsd_pw_esd device: nsd_pw_esd must not overlap thkox" |
| and nsd_pw_esd thkox |
| } |
| rule "dnsd_pw_esd.OVL.6" { |
| caption "nsd_pw_esd.OVL.6: Illegal nsd_pw_esd device: nsd_pw_esd must not overlap psdm" |
| and nsd_pw_esd psdm |
| } |
| rule "dnsd_pw_esd.OVL.7" { |
| caption "nsd_pw_esd.OVL.7: Illegal nsd_pw_esd device: nsd_pw_esd must not overlap nsm" |
| and nsd_pw_esd nsm |
| } |
| rule "dnsd_pw_esd.OVL.8" { |
| caption "nsd_pw_esd.OVL.8: Illegal nsd_pw_esd device: nsd_pw_esd must not overlap skip_pad" |
| and nsd_pw_esd skip_pad |
| } |
| rule "dnsd_pw_esd.OVL.9" { |
| caption "nsd_pw_esd.OVL.9: Illegal nsd_pw_esd device: nsd_pw_esd must not overlap fuse" |
| and nsd_pw_esd fuse |
| } |
| rule "dnsd_pw_esd.OVL.10" { |
| caption "nsd_pw_esd.OVL.10: Illegal nsd_pw_esd device: nsd_pw_esd must not overlap diff:res" |
| and nsd_pw_esd diffres |
| } |
| rule "dnsd_pw_esd.OVL.11" { |
| caption "nsd_pw_esd.OVL.11: Illegal nsd_pw_esd device: nsd_pw_esd must not overlap pwell:res" |
| and nsd_pw_esd pwres |
| } |
| rule "dnsd_pw_esd.OVL.12" { |
| caption "nsd_pw_esd.OVL.12: Illegal nsd_pw_esd device: nsd_pw_esd must not overlap poly:res" |
| and nsd_pw_esd polyres |
| } |
| rule "dnsd_pw_esd.OVL.13" { |
| caption "nsd_pw_esd.OVL.13: Illegal nsd_pw_esd device: nsd_pw_esd must not overlap li:res" |
| and nsd_pw_esd lires |
| } |
| rule "dnsd_pw_esd.OVL.14" { |
| caption "nsd_pw_esd.OVL.14: Illegal nsd_pw_esd device: nsd_pw_esd must not overlap areaid:lvNative" |
| and nsd_pw_esd LVID |
| } |
| rule "dnsd_pw_esd.OVL.15" { |
| caption "nsd_pw_esd.OVL.15: Illegal nsd_pw_esd device: nsd_pw_esd must not overlap pnp" |
| and nsd_pw_esd pnp |
| } |
| rule "dnsd_pw_esd.OVL.16" { |
| caption "nsd_pw_esd.OVL.16: Illegal nsd_pw_esd device: nsd_pw_esd must not overlap npn" |
| and nsd_pw_esd npn |
| } |
| rule "dnsd_pw_esd.OVL.17" { |
| caption "nsd_pw_esd.OVL.17: Illegal nsd_pw_esd device: nsd_pw_esd must not overlap areaid:photo" |
| and nsd_pw_esd PHdiodeID |
| } |
| rule "dnsd_pw_esd.OVL.18" { |
| caption "nsd_pw_esd.OVL.18: Illegal nsd_pw_esd device: nsd_pw_esd must not overlap areaid:core" |
| and nsd_pw_esd COREID |
| } |
| rule "dnsd_pw_esd.OVL.19" { |
| caption "nsd_pw_esd.OVL.19: Illegal nsd_pw_esd device: nsd_pw_esd must not overlap areaid:extendedDrain" |
| and nsd_pw_esd ENID |
| } |
| rule "dnsd_pw_esd.OVL.20" { |
| caption "nsd_pw_esd.OVL.20: Illegal nsd_pw_esd device: nsd_pw_esd must not overlap areaid:seal" |
| and nsd_pw_esd SEALID |
| } |
| rule "dnsd_pw_esd.OVL.21" { |
| caption "nsd_pw_esd.OVL.21: Illegal nsd_pw_esd device: nsd_pw_esd must not overlap v5" |
| and nsd_pw_esd v5 |
| } |
| rule "dnsd_pw_esd.OVL.22" { |
| caption "nsd_pw_esd.OVL.22: Illegal nsd_pw_esd device: nsd_pw_esd must not overlap v12" |
| and nsd_pw_esd v12 |
| } |
| rule "dnsd_pw_esd.OVL.23" { |
| caption "nsd_pw_esd.OVL.23: Illegal nsd_pw_esd device: nsd_pw_esd must not overlap v20" |
| and nsd_pw_esd v20 |
| } |
| rule "dnsd_pw_esd.OVL.24" { |
| caption "nsd_pw_esd.OVL.24: Illegal nsd_pw_esd device: nsd_pw_esd must not overlap nwell" |
| and nsd_pw_esd nwell |
| } |
| rule "dnsd_pw_esd.OVL.25" { |
| caption "nsd_pw_esd.OVL.25: Illegal nsd_pw_esd device: nsd_pw_esd must not overlap poly" |
| and nsd_pw_esd polyi |
| } |
| rule "dnsd_pw_esd.OVL.26" { |
| caption "nsd_pw_esd.OVL.26: Illegal nsd_pw_esd device: nsd_pw_esd must not overlap poly:model" |
| and nsd_pw_esd polyModel |
| } |
| not ( and ( and ( and ( and diodeID psdm ) nwell ) diffi ) ESDID ) ( or v5 v12 v20 lvtn hvtp LVID ) -outputlayer psd_nw_esd |
| rule "dpsd_nw_esd.OVL.1" { |
| caption "psd_nw_esd.OVL.1: Illegal psd_nw_esd device: psd_nw_esd must not overlap pwbm" |
| and psd_nw_esd pwbm |
| } |
| rule "dpsd_nw_esd.OVL.2" { |
| caption "psd_nw_esd.OVL.2: Illegal psd_nw_esd device: psd_nw_esd must not overlap hvtp" |
| and psd_nw_esd hvtp |
| } |
| rule "dpsd_nw_esd.OVL.3" { |
| caption "psd_nw_esd.OVL.3: Illegal psd_nw_esd device: psd_nw_esd must not overlap lvtn" |
| and psd_nw_esd lvtn |
| } |
| rule "dpsd_nw_esd.OVL.4" { |
| caption "psd_nw_esd.OVL.4: Illegal psd_nw_esd device: psd_nw_esd must not overlap tunm" |
| and psd_nw_esd tunm |
| } |
| rule "dpsd_nw_esd.OVL.5" { |
| caption "psd_nw_esd.OVL.5: Illegal psd_nw_esd device: psd_nw_esd must not overlap thkox" |
| and psd_nw_esd thkox |
| } |
| rule "dpsd_nw_esd.OVL.6" { |
| caption "psd_nw_esd.OVL.6: Illegal psd_nw_esd device: psd_nw_esd must not overlap poly" |
| and psd_nw_esd polyi |
| } |
| rule "dpsd_nw_esd.OVL.7" { |
| caption "psd_nw_esd.OVL.7: Illegal psd_nw_esd device: psd_nw_esd must not overlap nsdm" |
| and psd_nw_esd nsdm |
| } |
| rule "dpsd_nw_esd.OVL.8" { |
| caption "psd_nw_esd.OVL.8: Illegal psd_nw_esd device: psd_nw_esd must not overlap nsm" |
| and psd_nw_esd nsm |
| } |
| rule "dpsd_nw_esd.OVL.9" { |
| caption "psd_nw_esd.OVL.9: Illegal psd_nw_esd device: psd_nw_esd must not overlap skip_pad" |
| and psd_nw_esd skip_pad |
| } |
| rule "dpsd_nw_esd.OVL.10" { |
| caption "psd_nw_esd.OVL.10: Illegal psd_nw_esd device: psd_nw_esd must not overlap fuse" |
| and psd_nw_esd fuse |
| } |
| rule "dpsd_nw_esd.OVL.11" { |
| caption "psd_nw_esd.OVL.11: Illegal psd_nw_esd device: psd_nw_esd must not overlap diff:res" |
| and psd_nw_esd diffres |
| } |
| rule "dpsd_nw_esd.OVL.12" { |
| caption "psd_nw_esd.OVL.12: Illegal psd_nw_esd device: psd_nw_esd must not overlap pwell:res" |
| and psd_nw_esd pwres |
| } |
| rule "dpsd_nw_esd.OVL.13" { |
| caption "psd_nw_esd.OVL.13: Illegal psd_nw_esd device: psd_nw_esd must not overlap poly:res" |
| and psd_nw_esd polyres |
| } |
| rule "dpsd_nw_esd.OVL.14" { |
| caption "psd_nw_esd.OVL.14: Illegal psd_nw_esd device: psd_nw_esd must not overlap li:res" |
| and psd_nw_esd lires |
| } |
| rule "dpsd_nw_esd.OVL.15" { |
| caption "psd_nw_esd.OVL.15: Illegal psd_nw_esd device: psd_nw_esd must not overlap areaid:lvNative" |
| and psd_nw_esd LVID |
| } |
| rule "dpsd_nw_esd.OVL.16" { |
| caption "psd_nw_esd.OVL.16: Illegal psd_nw_esd device: psd_nw_esd must not overlap pnp" |
| and psd_nw_esd pnp |
| } |
| rule "dpsd_nw_esd.OVL.17" { |
| caption "psd_nw_esd.OVL.17: Illegal psd_nw_esd device: psd_nw_esd must not overlap npn" |
| and psd_nw_esd npn |
| } |
| rule "dpsd_nw_esd.OVL.18" { |
| caption "psd_nw_esd.OVL.18: Illegal psd_nw_esd device: psd_nw_esd must not overlap areaid:photo" |
| and psd_nw_esd PHdiodeID |
| } |
| rule "dpsd_nw_esd.OVL.19" { |
| caption "psd_nw_esd.OVL.19: Illegal psd_nw_esd device: psd_nw_esd must not overlap areaid:core" |
| and psd_nw_esd COREID |
| } |
| rule "dpsd_nw_esd.OVL.20" { |
| caption "psd_nw_esd.OVL.20: Illegal psd_nw_esd device: psd_nw_esd must not overlap areaid:extendedDrain" |
| and psd_nw_esd ENID |
| } |
| rule "dpsd_nw_esd.OVL.21" { |
| caption "psd_nw_esd.OVL.21: Illegal psd_nw_esd device: psd_nw_esd must not overlap areaid:seal" |
| and psd_nw_esd SEALID |
| } |
| rule "dpsd_nw_esd.OVL.22" { |
| caption "psd_nw_esd.OVL.22: Illegal psd_nw_esd device: psd_nw_esd must not overlap v5" |
| and psd_nw_esd v5 |
| } |
| rule "dpsd_nw_esd.OVL.23" { |
| caption "psd_nw_esd.OVL.23: Illegal psd_nw_esd device: psd_nw_esd must not overlap v12" |
| and psd_nw_esd v12 |
| } |
| rule "dpsd_nw_esd.OVL.24" { |
| caption "psd_nw_esd.OVL.24: Illegal psd_nw_esd device: psd_nw_esd must not overlap v20" |
| and psd_nw_esd v20 |
| } |
| rule "dpsd_nw_esd.OVL.25" { |
| caption "psd_nw_esd.OVL.25: Illegal psd_nw_esd device: psd_nw_esd must not overlap poly:model" |
| and psd_nw_esd polyModel |
| } |
| and diodeID nsdm -outputlayer nsd_pw_esd_v5_a |
| not nsd_pw_esd_v5_a nwell -outputlayer nsd_pw_esd_v5_b |
| and nsd_pw_esd_v5_b diffi -outputlayer nsd_pw_esd_v5_c |
| and nsd_pw_esd_v5_c ESDID -outputlayer nsd_pw_esd_v5_d |
| and nsd_pw_esd_v5_d v5 -outputlayer nsd_pw_esd_v5_e |
| and nsd_pw_esd_v5_e thkox -outputlayer nsd_pw_esd_v5_f |
| not nsd_pw_esd_v5_f ( or v12 v20 lvtn hvtp LVID ) -outputlayer nsd_pw_esd_v5 |
| rule "dnsd_pw_esd_v5.OVL.1" { |
| caption "nsd_pw_esd_v5.OVL.1: Illegal nsd_pw_esd_v5 device: nsd_pw_esd_v5 must not overlap skip_dnw" |
| and nsd_pw_esd_v5 skip_dnw |
| } |
| rule "dnsd_pw_esd_v5.OVL.2" { |
| caption "nsd_pw_esd_v5.OVL.2: Illegal nsd_pw_esd_v5 device: nsd_pw_esd_v5 must not overlap pwbm" |
| and nsd_pw_esd_v5 pwbm |
| } |
| rule "dnsd_pw_esd_v5.OVL.3" { |
| caption "nsd_pw_esd_v5.OVL.3: Illegal nsd_pw_esd_v5 device: nsd_pw_esd_v5 must not overlap nwell" |
| and nsd_pw_esd_v5 nwell |
| } |
| rule "dnsd_pw_esd_v5.OVL.4" { |
| caption "nsd_pw_esd_v5.OVL.4: Illegal nsd_pw_esd_v5 device: nsd_pw_esd_v5 must not overlap hvtp" |
| and nsd_pw_esd_v5 hvtp |
| } |
| rule "dnsd_pw_esd_v5.OVL.5" { |
| caption "nsd_pw_esd_v5.OVL.5: Illegal nsd_pw_esd_v5 device: nsd_pw_esd_v5 must not overlap lvtn" |
| and nsd_pw_esd_v5 lvtn |
| } |
| rule "dnsd_pw_esd_v5.OVL.6" { |
| caption "nsd_pw_esd_v5.OVL.6: Illegal nsd_pw_esd_v5 device: nsd_pw_esd_v5 must not overlap tunm" |
| and nsd_pw_esd_v5 tunm |
| } |
| rule "dnsd_pw_esd_v5.OVL.7" { |
| caption "nsd_pw_esd_v5.OVL.7: Illegal nsd_pw_esd_v5 device: nsd_pw_esd_v5 must not overlap rpm" |
| and nsd_pw_esd_v5 rpm |
| } |
| rule "dnsd_pw_esd_v5.OVL.8" { |
| caption "nsd_pw_esd_v5.OVL.8: Illegal nsd_pw_esd_v5 device: nsd_pw_esd_v5 must not overlap rrpm" |
| and nsd_pw_esd_v5 rrpm |
| } |
| rule "dnsd_pw_esd_v5.OVL.9" { |
| caption "nsd_pw_esd_v5.OVL.9: Illegal nsd_pw_esd_v5 device: nsd_pw_esd_v5 must not overlap urpm" |
| and nsd_pw_esd_v5 urpm |
| } |
| rule "dnsd_pw_esd_v5.OVL.10" { |
| caption "nsd_pw_esd_v5.OVL.10: Illegal nsd_pw_esd_v5 device: nsd_pw_esd_v5 must not overlap poly" |
| and nsd_pw_esd_v5 polyi |
| } |
| rule "dnsd_pw_esd_v5.OVL.11" { |
| caption "nsd_pw_esd_v5.OVL.11: Illegal nsd_pw_esd_v5 device: nsd_pw_esd_v5 must not overlap psdm" |
| and nsd_pw_esd_v5 psdm |
| } |
| rule "dnsd_pw_esd_v5.OVL.12" { |
| caption "nsd_pw_esd_v5.OVL.12: Illegal nsd_pw_esd_v5 device: nsd_pw_esd_v5 must not overlap nsm" |
| and nsd_pw_esd_v5 nsm |
| } |
| rule "dnsd_pw_esd_v5.OVL.13" { |
| caption "nsd_pw_esd_v5.OVL.13: Illegal nsd_pw_esd_v5 device: nsd_pw_esd_v5 must not overlap skip_pad" |
| and nsd_pw_esd_v5 skip_pad |
| } |
| rule "dnsd_pw_esd_v5.OVL.14" { |
| caption "nsd_pw_esd_v5.OVL.14: Illegal nsd_pw_esd_v5 device: nsd_pw_esd_v5 must not overlap fuse" |
| and nsd_pw_esd_v5 fuse |
| } |
| rule "dnsd_pw_esd_v5.OVL.15" { |
| caption "nsd_pw_esd_v5.OVL.15: Illegal nsd_pw_esd_v5 device: nsd_pw_esd_v5 must not overlap diff:res" |
| and nsd_pw_esd_v5 diffres |
| } |
| rule "dnsd_pw_esd_v5.OVL.16" { |
| caption "nsd_pw_esd_v5.OVL.16: Illegal nsd_pw_esd_v5 device: nsd_pw_esd_v5 must not overlap pwell:res" |
| and nsd_pw_esd_v5 pwres |
| } |
| rule "dnsd_pw_esd_v5.OVL.17" { |
| caption "nsd_pw_esd_v5.OVL.17: Illegal nsd_pw_esd_v5 device: nsd_pw_esd_v5 must not overlap poly:res" |
| and nsd_pw_esd_v5 polyres |
| } |
| rule "dnsd_pw_esd_v5.OVL.18" { |
| caption "nsd_pw_esd_v5.OVL.18: Illegal nsd_pw_esd_v5 device: nsd_pw_esd_v5 must not overlap li:res" |
| and nsd_pw_esd_v5 lires |
| } |
| rule "dnsd_pw_esd_v5.OVL.19" { |
| caption "nsd_pw_esd_v5.OVL.19: Illegal nsd_pw_esd_v5 device: nsd_pw_esd_v5 must not overlap areaid:lvNative" |
| and nsd_pw_esd_v5 LVID |
| } |
| rule "dnsd_pw_esd_v5.OVL.20" { |
| caption "nsd_pw_esd_v5.OVL.20: Illegal nsd_pw_esd_v5 device: nsd_pw_esd_v5 must not overlap pnp" |
| and nsd_pw_esd_v5 pnp |
| } |
| rule "dnsd_pw_esd_v5.OVL.21" { |
| caption "nsd_pw_esd_v5.OVL.21: Illegal nsd_pw_esd_v5 device: nsd_pw_esd_v5 must not overlap npn" |
| and nsd_pw_esd_v5 npn |
| } |
| rule "dnsd_pw_esd_v5.OVL.22" { |
| caption "nsd_pw_esd_v5.OVL.22: Illegal nsd_pw_esd_v5 device: nsd_pw_esd_v5 must not overlap areaid:photo" |
| and nsd_pw_esd_v5 PHdiodeID |
| } |
| rule "dnsd_pw_esd_v5.OVL.23" { |
| caption "nsd_pw_esd_v5.OVL.23: Illegal nsd_pw_esd_v5 device: nsd_pw_esd_v5 must not overlap areaid:core" |
| and nsd_pw_esd_v5 COREID |
| } |
| rule "dnsd_pw_esd_v5.OVL.24" { |
| caption "nsd_pw_esd_v5.OVL.24: Illegal nsd_pw_esd_v5 device: nsd_pw_esd_v5 must not overlap areaid:extendedDrain" |
| and nsd_pw_esd_v5 ENID |
| } |
| rule "dnsd_pw_esd_v5.OVL.25" { |
| caption "nsd_pw_esd_v5.OVL.25: Illegal nsd_pw_esd_v5 device: nsd_pw_esd_v5 must not overlap areaid:seal" |
| and nsd_pw_esd_v5 SEALID |
| } |
| rule "dnsd_pw_esd_v5.OVL.26" { |
| caption "nsd_pw_esd_v5.OVL.26: Illegal nsd_pw_esd_v5 device: nsd_pw_esd_v5 must not overlap v12" |
| and nsd_pw_esd_v5 v12 |
| } |
| rule "dnsd_pw_esd_v5.OVL.27" { |
| caption "nsd_pw_esd_v5.OVL.27: Illegal nsd_pw_esd_v5 device: nsd_pw_esd_v5 must not overlap v20" |
| and nsd_pw_esd_v5 v20 |
| } |
| rule "dnsd_pw_esd_v5.OVL.28" { |
| caption "nsd_pw_esd_v5.OVL.28: Illegal nsd_pw_esd_v5 device: nsd_pw_esd_v5 must not overlap poly:model" |
| and nsd_pw_esd_v5 polyModel |
| } |
| and diodeID psdm -outputlayer psd_nw_esd_v5_a |
| and psd_nw_esd_v5_a nwell -outputlayer psd_nw_esd_v5_b |
| and psd_nw_esd_v5_b diffi -outputlayer psd_nw_esd_v5_c |
| and psd_nw_esd_v5_c ESDID -outputlayer psd_nw_esd_v5_d |
| and psd_nw_esd_v5_d v5 -outputlayer psd_nw_esd_v5_e |
| and psd_nw_esd_v5_e thkox -outputlayer psd_nw_esd_v5_f |
| not psd_nw_esd_v5_f ( or v12 v20 lvtn hvtp LVID ) -outputlayer psd_nw_esd_v5 |
| rule "dpsd_nw_esd_v5.OVL.1" { |
| caption "psd_nw_esd_v5.OVL.1: Illegal psd_nw_esd_v5 device: psd_nw_esd_v5 must not overlap pwbm" |
| and psd_nw_esd_v5 pwbm |
| } |
| rule "dpsd_nw_esd_v5.OVL.2" { |
| caption "psd_nw_esd_v5.OVL.2: Illegal psd_nw_esd_v5 device: psd_nw_esd_v5 must not overlap hvtp" |
| and psd_nw_esd_v5 hvtp |
| } |
| rule "dpsd_nw_esd_v5.OVL.3" { |
| caption "psd_nw_esd_v5.OVL.3: Illegal psd_nw_esd_v5 device: psd_nw_esd_v5 must not overlap lvtn" |
| and psd_nw_esd_v5 lvtn |
| } |
| rule "dpsd_nw_esd_v5.OVL.4" { |
| caption "psd_nw_esd_v5.OVL.4: Illegal psd_nw_esd_v5 device: psd_nw_esd_v5 must not overlap tunm" |
| and psd_nw_esd_v5 tunm |
| } |
| rule "dpsd_nw_esd_v5.OVL.5" { |
| caption "psd_nw_esd_v5.OVL.5: Illegal psd_nw_esd_v5 device: psd_nw_esd_v5 must not overlap rpm" |
| and psd_nw_esd_v5 rpm |
| } |
| rule "dpsd_nw_esd_v5.OVL.6" { |
| caption "psd_nw_esd_v5.OVL.6: Illegal psd_nw_esd_v5 device: psd_nw_esd_v5 must not overlap rrpm" |
| and psd_nw_esd_v5 rrpm |
| } |
| rule "dpsd_nw_esd_v5.OVL.7" { |
| caption "psd_nw_esd_v5.OVL.7: Illegal psd_nw_esd_v5 device: psd_nw_esd_v5 must not overlap urpm" |
| and psd_nw_esd_v5 urpm |
| } |
| rule "dpsd_nw_esd_v5.OVL.8" { |
| caption "psd_nw_esd_v5.OVL.8: Illegal psd_nw_esd_v5 device: psd_nw_esd_v5 must not overlap poly" |
| and psd_nw_esd_v5 polyi |
| } |
| rule "dpsd_nw_esd_v5.OVL.9" { |
| caption "psd_nw_esd_v5.OVL.9: Illegal psd_nw_esd_v5 device: psd_nw_esd_v5 must not overlap nsdm" |
| and psd_nw_esd_v5 nsdm |
| } |
| rule "dpsd_nw_esd_v5.OVL.10" { |
| caption "psd_nw_esd_v5.OVL.10: Illegal psd_nw_esd_v5 device: psd_nw_esd_v5 must not overlap nsm" |
| and psd_nw_esd_v5 nsm |
| } |
| rule "dpsd_nw_esd_v5.OVL.11" { |
| caption "psd_nw_esd_v5.OVL.11: Illegal psd_nw_esd_v5 device: psd_nw_esd_v5 must not overlap skip_pad" |
| and psd_nw_esd_v5 skip_pad |
| } |
| rule "dpsd_nw_esd_v5.OVL.12" { |
| caption "psd_nw_esd_v5.OVL.12: Illegal psd_nw_esd_v5 device: psd_nw_esd_v5 must not overlap fuse" |
| and psd_nw_esd_v5 fuse |
| } |
| rule "dpsd_nw_esd_v5.OVL.13" { |
| caption "psd_nw_esd_v5.OVL.13: Illegal psd_nw_esd_v5 device: psd_nw_esd_v5 must not overlap diff:res" |
| and psd_nw_esd_v5 diffres |
| } |
| rule "dpsd_nw_esd_v5.OVL.14" { |
| caption "psd_nw_esd_v5.OVL.14: Illegal psd_nw_esd_v5 device: psd_nw_esd_v5 must not overlap pwell:res" |
| and psd_nw_esd_v5 pwres |
| } |
| rule "dpsd_nw_esd_v5.OVL.15" { |
| caption "psd_nw_esd_v5.OVL.15: Illegal psd_nw_esd_v5 device: psd_nw_esd_v5 must not overlap poly:res" |
| and psd_nw_esd_v5 polyres |
| } |
| rule "dpsd_nw_esd_v5.OVL.16" { |
| caption "psd_nw_esd_v5.OVL.16: Illegal psd_nw_esd_v5 device: psd_nw_esd_v5 must not overlap li:res" |
| and psd_nw_esd_v5 lires |
| } |
| rule "dpsd_nw_esd_v5.OVL.17" { |
| caption "psd_nw_esd_v5.OVL.17: Illegal psd_nw_esd_v5 device: psd_nw_esd_v5 must not overlap areaid:lvNative" |
| and psd_nw_esd_v5 LVID |
| } |
| rule "dpsd_nw_esd_v5.OVL.18" { |
| caption "psd_nw_esd_v5.OVL.18: Illegal psd_nw_esd_v5 device: psd_nw_esd_v5 must not overlap pnp" |
| and psd_nw_esd_v5 pnp |
| } |
| rule "dpsd_nw_esd_v5.OVL.19" { |
| caption "psd_nw_esd_v5.OVL.19: Illegal psd_nw_esd_v5 device: psd_nw_esd_v5 must not overlap npn" |
| and psd_nw_esd_v5 npn |
| } |
| rule "dpsd_nw_esd_v5.OVL.20" { |
| caption "psd_nw_esd_v5.OVL.20: Illegal psd_nw_esd_v5 device: psd_nw_esd_v5 must not overlap areaid:photo" |
| and psd_nw_esd_v5 PHdiodeID |
| } |
| rule "dpsd_nw_esd_v5.OVL.21" { |
| caption "psd_nw_esd_v5.OVL.21: Illegal psd_nw_esd_v5 device: psd_nw_esd_v5 must not overlap areaid:core" |
| and psd_nw_esd_v5 COREID |
| } |
| rule "dpsd_nw_esd_v5.OVL.22" { |
| caption "psd_nw_esd_v5.OVL.22: Illegal psd_nw_esd_v5 device: psd_nw_esd_v5 must not overlap areaid:extendedDrain" |
| and psd_nw_esd_v5 ENID |
| } |
| rule "dpsd_nw_esd_v5.OVL.23" { |
| caption "psd_nw_esd_v5.OVL.23: Illegal psd_nw_esd_v5 device: psd_nw_esd_v5 must not overlap areaid:seal" |
| and psd_nw_esd_v5 SEALID |
| } |
| rule "dpsd_nw_esd_v5.OVL.24" { |
| caption "psd_nw_esd_v5.OVL.24: Illegal psd_nw_esd_v5 device: psd_nw_esd_v5 must not overlap v12" |
| and psd_nw_esd_v5 v12 |
| } |
| rule "dpsd_nw_esd_v5.OVL.25" { |
| caption "psd_nw_esd_v5.OVL.25: Illegal psd_nw_esd_v5 device: psd_nw_esd_v5 must not overlap v20" |
| and psd_nw_esd_v5 v20 |
| } |
| rule "dpsd_nw_esd_v5.OVL.26" { |
| caption "psd_nw_esd_v5.OVL.26: Illegal psd_nw_esd_v5 device: psd_nw_esd_v5 must not overlap poly:model" |
| and psd_nw_esd_v5 polyModel |
| } |
| |
| #ENDIF |
| // end illegal device checks |
| |
| |
| |
| |
| // |
| // Fill checks |
| // |
| |
| rule "fill.OVL.1" { |
| caption "fill.OVL.1: Layer diff_fill must be outside diff/drawing" |
| and diff_fill diffii |
| } |
| rule "fill.OVL.2" { |
| caption "fill.OVL.2: Layer poly_fill must be outside poly/drawing" |
| and poly_fill polyii |
| } |
| rule "fill.OVL.3" { |
| caption "fill.OVL.3: Layer li_fill must be outside poly/drawing" |
| and li_fill polyii |
| } |
| rule "fill.OVL.4" { |
| caption "fill.OVL.4: Layer m1_fill must be outside met1/drawing" |
| and m1_fill met1ii |
| } |
| rule "fill.OVL.5" { |
| caption "fill.OVL.5: Layer m2_fill must be outside met2/drawing" |
| and m2_fill met2ii |
| } |
| rule "fill.OVL.6" { |
| caption "fill.OVL.6: Layer m3_fill must be outside met3/drawing" |
| and m3_fill met3ii |
| } |
| rule "fill.OVL.7" { |
| caption "fill.OVL.7: Layer m4_fill must be outside met4/drawing" |
| and m4_fill met4ii |
| } |
| rule "fill.OVL.8" { |
| caption "fill.OVL.8: Layer m5_fill must be outside met5/drawing" |
| and m5_fill met5ii |
| } |
| rule "fill.CON.1" { |
| caption "fill.CON.1: Layer diff_fill must float" |
| select -interact ( not diff_fill ( or critSide ccorner ) ) licon |
| } |
| rule "fill.CON.2" { |
| caption "fill.CON.2: Layer poly_fill must float" |
| select -interact ( not poly_fill ( or critSide ccorner ) ) licon |
| } |
| rule "fill.CON.3" { |
| caption "fill.CON.3: Layer li_fill must float" |
| select -interact ( not li_fill ( or critSide ccorner ) ) licon |
| select -interact ( not li_fill ( or critSide ccorner ) ) mcon |
| } |
| rule "fill.CON.4" { |
| caption "fill.CON.4: Layer m1_fill must float" |
| select -interact ( not m1_fill ( or critSide ccorner ) ) mcon |
| select -interact ( not m1_fill ( or critSide ccorner ) ) via1 |
| } |
| rule "fill.CON.5" { |
| caption "fill.CON.5: Layer m2_fill must float" |
| select -interact ( not m2_fill ( or critSide ccorner ) ) via1 |
| select -interact ( not m2_fill ( or critSide ccorner ) ) via2 |
| } |
| rule "fill.CON.6" { |
| caption "fill.CON.6: Layer m3_fill must float" |
| select -interact ( not m3_fill ( or critSide ccorner ) ) via2 |
| select -interact ( not m3_fill ( or critSide ccorner ) ) via3 |
| } |
| rule "fill.CON.7" { |
| caption "fill.CON.7: Layer m4_fill must float" |
| select -interact ( not m4_fill ( or critSide ccorner ) ) via3 |
| select -interact ( not m4_fill ( or critSide ccorner ) ) via4 |
| } |
| rule "fill.CON.8" { |
| caption "fill.CON.8: Layer m5_fill must float" |
| select -interact m5_fill via4 |
| } |
