| #!tvf |
| namespace import tvf::* |
| set ::global_num "1" |
| tvf::set_global_variable g_global_num "global_num" |
| set externalChannel [open "calibre_drc.rul.svrf" w] |
| tvf::echo_svrf 1 $externalChannel |
| |
| verbatim { |
| |
| // ******************************************************** |
| // Copyright (c) 2020 by SkyWater Technology |
| // SkyWater Confidential Information |
| // ******************************************************** |
| |
| //////////////////////////////////////////////////////////////////////////////// |
| // |
| // ========================= |
| // Comments / Update Section |
| // ========================= |
| // |
| // ========== ======== ======================================================== |
| // Date Modifier Notes |
| // ========== ======== ======================================================== |
| // 3/24/2020 JAG New DRC runset |
| // & |
| // RY |
| // 6/17/2020 JAG Corrected message for met2.ENC.2 to read 0.085 (was 0.06) |
| // Updated lonely via/contact code to correct errors |
| // Improved latchup error messages |
| // 6/25/2020 JAG Added layer thkox - v5 is now only a marker layer |
| // and thkox is a mask layer for thick oxide. |
| // Adjusted numerous rules for this change. |
| // 6/29/2020 JAG Changed licon.ENC.6 to use polyi rather than poly to |
| // avoid false flag in HP/HS poly res |
| // Changed pwres.CON.5 to use nw_hole rather than pwell to |
| // avoid false flag in pwres pcell |
| // Changed non-manhatten check on poly to ignore poly in |
| // npn to avoid error |
| // Changed poly.OVL.3 to not flag 5v npn |
| // 6/30/2020 JAG Modified nsdm.ENC.1 to avoid checking the 5v npn's |
| // internal octagonal nsdm |
| // Rewrote v5.SP.1 to remove false flags |
| // 7/09/2020 JAG Updated seal ring rules to accomodate new seal ring pcell |
| // 7/10/2020 JAG Updated pad rules |
| // 7/13/2020 JAG Updated valid pads to include S8 definition for backwards |
| // compatibility |
| // 7/20/2020 RY Revamped the DENMOS and DEPMOS checks |
| // 7/20/2020 JAG Changed definition of pwellSigPadNtr to include ptub |
| // 7/23/2020 JAG Removed old latchup rule numbers from latchup rules |
| // 7/24/2020 JAG Added new lonely via contact checks |
| // 7/26/2020 JAG Finished adding supplemental recommended lonely via rules |
| // Fixed some syntax and spelling issues |
| // Standardized many rules with cap first letter and value |
| // following rule text |
| // 7/29/2020 JAG Converted latchup rules from verbatim to TVF |
| // 7/30/2020 JAG Implemented new floating net rule and removed old |
| // floating layer rules (now based on devices from LVS) |
| // 8/04/2020 JAG Removed redundant "difftap.SP.6" from rule message |
| // Removed "m2.3c" from met2.CON.8 message |
| // Added missing message to latchup.1 |
| // Updated definition of bond pad recognition for stress |
| // checks |
| // 8/07/2020 JAG Removed a debug output statement |
| // 8/12/2020 JAG Updated some via enclosure messages to include "by met" |
| // 8/14/2020 JAG Added rule name back to message at request of layout |
| // design |
| // 8/20/2020 JAG Removed use of areaid/extDrain20 and replaced any usage |
| // with ENID as areaid/extDrain20 was removed from the |
| // tech file as obsolete |
| // Corrected rule v20.ENC.2 to correct spelling error |
| // 8/27/2020 JAG Added 20V net identification |
| // Enhanced net idenification by voltage markers |
| // Added some but not all voltage rules |
| // 9/02/2020 JAG Reverted net identification by enclosed marker |
| // 9/04/2020 JAG Started adding new 20v denmos/depmos rules |
| // 9/10/2020 JAG Removed V20.ENC.2 as it is not needed |
| // Removed pad.CON.2 text pad must have text "plastic" |
| // 9/11/2020 JAG Changed definition of diffHV to use diffi not diff |
| // 9/14/2020 JAG Changed v12.OVL.7 to use polyi and avoid poly inside v12 |
| // Added rule to check that v20 doesn't straddle poly |
| // Changed some pad rules to not false flag probe pads |
| // Changed rule v20.ENC.3 to v20.ENC.2 and rewrote to |
| // check for dnw interact v20 must be covered by v20 |
| // 9/15/2020 JAG Rewrote Hdifftap.WID.3/4 as they were not flagging |
| // testcases |
| // 9/23/2020 JAG Added rules to enforce proper use of areaid/pad_io, |
| // pad_pwr and pad_gnd |
| // Added substrateCut softcheck - sub cut with no ptap |
| // 9/24/2020 JAG Changed lvtn.SP.3 from 0.235 to 0.19 per Xena ticket #282 |
| // 10/12/2020 JAG Added illegal device checks originally coded in the LVS |
| // 10/19/2020 JAG Finished updating and testing illegal device code |
| // 11/05/2020 JAG Revised all Latch-Up checks to new document |
| // Removed dnw not over ptub from ptap definition |
| // 11/13/2020 JAG Updated denmos_20.SP.8 to redefine ptap def for iso nmos |
| // 20v |
| // 11/14/2020 JAG Updated the ILLEGAL DEVICE rules (WIP) up to NMOS |
| // The remainder are in dev |
| // 11/24/2020 JAG Updated Device rules from Device Table |
| // 11/30/2020 JAG Updated latch-up rules |
| // 12/01/2020 JAG Changed via to via1 |
| // |
| // ----- |
| // Q4.02 |
| // ----- |
| // 12/03/2020 JAG Updates for Q4.02: |
| // Changed via to via in relevent places |
| // Changed li1 to li |
| // Changed licon1 to licon |
| // Changed illegal device check for dnsd_pw_nat to allow |
| // thkox |
| // Changed illegal device check for pad to disallow met4 |
| // Changed illegal device check for pnp to allow hvtp |
| // Changed illegal device check for npn to allow ldntm |
| // Changed illegal device check for pwres to allow npn/pnp |
| // Added CON rule to insure npn/pnp are only in allowed |
| // cells |
| // Updated rules to use new layer names |
| // Rewrote li.WID.3 to fix false errors |
| // Updated cap2m.SP.2 as it was flagging cap2m to unrelated |
| // met4 |
| // 12/26/2020 JAG Merged in fill layers with dwg layers |
| // --------------------------------------------------------------------------- |
| // 01/04/2021 JAG Corrected met4_block layer number |
| // Added definition for diff/poly block and added to |
| // predicitive fill so it will NOT generate predictive |
| // poly or diff fill inside respective block layers. |
| // 01/07/2021 JAG Added new checks for LVS_exclude layer |
| // 01/08/2021 RY Revamped the diffTap checks to diff checks to remove the |
| // old tap layer references |
| // 01/11/2021 JAG Renamed HdifHtap rules to diff_v5. |
| // 01/18/2021 JAG Added new fill rules |
| // Updated prune.CON.1 and renamed LVS_exclude.OVL.1 |
| // 01/19/2021 JAG Renamed psd/nsd.ENC.4 to psd/nsd.ENC.3 |
| // 01/20/2021 JAG Removed references to pwelliso and pwell_dg |
| // 01/21/2021 JAG Removed licon.SP.13 as duplicate of licon.SP.11 |
| // 01/22/2021 JAG Updated cap/cap2m to prohibit L-shaped capm/cap2m |
| // (modified capm.CON.5 & cap2m.CON.4) |
| // 01/25/2021 JAG Added rule pwbm.OVL.1 |
| // Added rules met2.AR.2 and met1.AR.2 |
| // 01/28/2021 JAG Added urpm.ANG.3 |
| // 02/01/2021 JAG Modified licon.ANG.1 as it referenced li not licon in msg |
| // and changed name from licon_not_seal.ANG.1 to licon.ANG.1 |
| // Removed fuse.CON.4 (check of tap over target as it is checked for diff already) |
| // Changed fuse.SP.1 spacing from 3.295 to 2.75 |
| // 02/03/2021 JAG Added pad.SP.6 and pad.AR.1 |
| // Added v5.OVL.12 |
| // 02/05/2021 JAG Combined rules metx.SP.2a and metxSP.2b into metx.SP.2 |
| // for met1-met4 |
| // 02/09/2021 JAG Renamed all DRC checks with "OVLP" to "OVL" such as: |
| // rule_name.OVLP.num to rule_name.OVL.num |
| // to standardize |
| // Removed rule PAD.AR.1 per Pete and Sam |
| // 02/26/2021 JAG Changed instances of "inside core" or "in core" to areaid:core |
| // Changed instances of "inside seal" or "in seal" to areaid:seal |
| // 03/02/2021 JAG Updated the pad rules to account for Pcell change in |
| // areaid:padLength rect. |
| // 03/02/2021 JAG Renamed rule met2.CON.8 to met2.ANT.2 and moved to antenna |
| // section as a recommended antenna rule. Also inverted the |
| // ratios to improve readibility. |
| // 03/08/2021 JAG Corrected pad.SP.11 as it was checking met1 under pad which |
| // was cut by met1/res - changed to check met1 input |
| // Changed diff_5v definition of hv_diff to be NOT tap |
| // after comparing IO Lib results btw s8 and s130 |
| // Corrected poly res term definition for float checks |
| // 03/09/2021 JAG Rewrote v5.OVL.3 as it was just plain wrong |
| // 03/10/2021 JAG Made same corrections to v12.OVL.3 |
| // Removed rule v5.OVL.3 as it was coded in error. |
| // 03/11/2021 JAG Added poly check for anchor min width |
| // 03/12/2021 JAG Modified two diff_5v rules to remove tap which should not |
| // have been checked after getting false errors in IO Libs |
| // 03/12/2021 JAG Rewrote wide metal spacing checks after consult with SV to verify code |
| // and added a keep layer for wide metal derivation |
| // Renamed metals.WID.stress.1 and created 5 rules as metx_stress.WID.1 |
| // 03/15/2021 JAG Removed thkox from rndiff_v5 rpdiff_v5 illegal device list |
| // Added code to illegal device checks to use areaid names |
| // Combined stress.CON.7 and stress.CON.8 to 1 rule |
| // 03/16/2021 JAG Updated verbiage in messages for stress.SP.1 stress.ENC.2 & stress.CON.9 |
| // Changed viax.viay.stress.CON.1 rules to viax.viay.anchor.CON.2 rules |
| // because it makes more sense as they tested via overlap in anchors |
| // 03/17/2021 JAG Renamed metx.stress.CON.9 to metx.SLOT.CON.9 |
| // 03/18/2021 JAG Removed non-octagonal check for pnp as it is checked to be in pcell |
| // 03/24/2021 JAG Renamed pwbm.OVL.1 as pwbm.ENC.2 after review showed |
| // pwbm.OVL.1 was flagging legal 20v de devices |
| // 03/25/2021 JAG Removed poly endcaps from lonely licon checks |
| // Exempted poly, li, m1-m5 inside text_pcell from |
| // floating net checks |
| // 03/26/2021 JAG Removed checks for poly and diff boundary layer |
| // since these were removed from the tech file |
| // 02/28/2021 JAG Modified poly.SP.7 to only check HP/HP2K res to diff |
| // 03/31/2021 JAG Added missing licon.anchor.SP.1 rule |
| // 04/14/2021 JAG SWT changed device table to allow devices under pad |
| // and other changes (eg met res over other layers) |
| // so created skip_pad, skip_res and skip_dnw to |
| // skip checking some devices and clean up IO Lib. |
| // 04/14/2021 JAG Added nmos_esd to illegal device checks |
| // |
| // ----- |
| // Q5.01 |
| // ----- |
| // |
| // 04/16/2021 JAG Removed old hv checks based on diff:hv marker and put in new |
| // hv checks based on v12 or v20 over diff (src/drn) |
| // 04/20/2021 JAG Removed check npc.ENC.1 per PM |
| // 04/22/2021 JAG Removed core from met1.ENC.1 and 1a |
| // Added licon.SP.13 for poly licon space to diff in core |
| // Added licon.SP.14 licon min space in core |
| // Added licon.CON.12 for core psdm prohibited over poly licon |
| // Added met2.ENC.3 min enclosure of via1 by met2 in core |
| // Changed rule diff_5v.WID.2 to thkox.WID.2 for diff width |
| // inside thkox inside core |
| // Split rule li.WID.1 into two rules li.WID.1/2/3 for |
| // width of li in/out of vpp/core |
| // and moved old li.WID.3 to li.WID.4 |
| // 04/23/2021 JAG Modified v5/v12/v20.CON.9 to include diff in check to |
| // ensure they are over thkox. |
| // Changed via.CON.10 to check all vias and deleted via ring |
| // check in seal ring |
| // Deleted via size in seal ring checks (no via/conts in seal) |
| // Removed construction checks which ensure rings shaped vias |
| // and contacts are only in the seal ring |
| // Renamed npc.ENC.1 as licon.ENC.8 for consistency |
| // 04/28/2021 JAG Exempted LATCHUP.generic.2a/b for areas covered by areaid:ESD |
| // Corrected latchup.misc.4 to removed gates under areaid:ESD |
| // |
| // ----- |
| // Q6.01 |
| // ----- |
| // |
| // 05/03/2021 JAG Updated exemptions for floating metals/poly to include anchor |
| // areas to avoid flagging anchors. |
| // 05/05/2021 JAG Removed nsd in isolated p-substrate from rule latchup.signal.12g |
| // per PM @ SWT |
| // Rewrote latchup.signal.2.1b as it was false flagging the level |
| // shifter design |
| // 05/05/2021 JAG Rewrote latchup.shv.1 based on work done on latchup.signal.2.1b |
| // Changed fill construction checks for non-floating fill to not check |
| // anchor region in the unlikely event that users put in fill layers |
| // rather than drawing layers in for anchors. |
| // 05/10/2021 JAG Modified the v5/v12/v20 nwell derivation to find the highest |
| // voltage marker over an nwell to use it to identify nwell voltage |
| // Added word "WARNING" to nwell of one voltage must not be connected |
| // to nwell of another voltage |
| // 05/17/2021 JAG Removed rule v12.SP.1 NW 12V check for 11.24u per PM |
| // Removed use of DFM commands in pad rules |
| // 05/19/2021 JAG Updated dnwell.CON.2 to check all P+ diff not just P+ src/drns |
| // Added REGION to many ENC checks to improve visibility |
| // 05/20/2021 JAG Removed s8_plowvt exemptions from poly.LEN.1 |
| // Removed M5RDL via pcell exemption from bond pad checks |
| // Removed psoc4*_top exemption from from bond pad checks |
| // Removed tsg5_m_tcg5_top exemption from from bond pad checks |
| // Removed s8hpbtoolkit_dual_rx_2* exemption from from bond pad checks |
| // Removed s8hpbtoolkit_dual_rx_inv* exemption from from bond pad checks |
| // Removed s8bio_top_biocmux_vccio* exemption from from bond pad checks |
| // Removed k2_east_pads_top* & k2_west_pads_top* exemption from from bond pad checks |
| // Removed krypton_io_pframe* & krypton2_toplevel* exemption from from bond pad checks |
| // Removed s8ppscio_top_vca_2*, s8ppscio_top_vcd_2*, s8ppscio_top_vda_2*, |
| // s8ppscio_top_vdd_3*, s8ppscio_top_vssa_2*, s8ppscio_top_vddabuf*, |
| // s8ppscio_top_vio*, s8ppscio_top_vssd_2*, s8ppscio_top_vssio_2*, |
| // s8ppscio_top_vssio_3*, s8ppscio_top_vssio_2*, s8tsg4io_top_vssd_2, |
| // s8ppscio_top_vssabuf*, s8ppscio_top_vusb_2 exemption from from bond pad checks |
| // Removed s8esdg4_net_io_b*, s8ppscio_top_vcd_2*, s8ppscio_top_vdd_2*, |
| // s8tsg4io_top_vio*, s8tsg4io_top_vssio_2*, s8tkm0s8_corner_tp2 |
| // exemption from from bond pad checks |
| // Removed exemptions for s8cell_ee_plus_sseln_a, s8cell_ee_plus_sseln_b, |
| // s8cell_ee_plus_sselp_a, s8cell_ee_plus_sselp_b & s8fpls_pl8 s8fs_cmux4_fm |
| // from met1.ENC.1 |
| // REMOVED s8usbpdv2_csa_top, s8usbpdv2_20vconn_sw_300ma_ovp_ngate_unit |
| // s8usbpdv2_20vconn_sw_300ma_ovp, s8usbpdv2_20sbu_sw_300ma_ovp cell |
| // exemptions from rpm rules |
| // Check coreID.CON.1 needs to be revamped when memory is supported (no change) |
| // 05/23/2021 JAG Updated gate definition for lvtn.ENC.1 |
| // 05/26/2021 JAG Corrected message for ubm.SP.2 (had value for ubm.SP.1) but check was OK |
| // 06/08/2021 JAG Added ptap.FL.1 and ntap.FL.1 to check for p+ tap or n+ tap which is |
| // not connected to a pad to RECOMMENDED rules |
| // 06/14/2021 JAG Fixed issue in latchup where m4 was shorting through caps to m3 and m5 was |
| // shorting through caps to m4. |
| // 06/16/2021 JAG Tightened slot definitions for stress using the following assumptions |
| // due to a design with a ptap ring around the entire chip which caused |
| // false metal slotting errors: |
| // 1. a metal hole of interest will have an area < 5000 sq um |
| // 2. a metal slot will have a width < 20.0 um |
| // 06/24/2021 JAG Added warnings for insufficient vias in anchor cells |
| // JAG Commented out fuse rules and implemented two rules to flag polygons on |
| // fuse and target layers |
| // Commented out illegal device fuse checks |
| // 06/25/2021 JAG Exempted rule latchup.signal.12e for n+ diff inside an isolated ptub |
| // Exempted rule latchup.signal.2.1b for dnw tied to gnd with n+ diff inside |
| // tied to ground (back-to-back diodes protecting separate ground supplies) |
| // 06/29/2021 JAG Removed (commented out) the following fuse related rules: diff_fill.CON.2, |
| // diff_fill.SP.3 and LVS_exclude.CON.15 at request of Linda A. |
| // 07/01/2021 JAG Added rule to output any shapes on areaid:NotCritSide - stress.CON.8 |
| // 07/02/2021 JAG Changed rule name of photo.WID.2 to photo.ENC.2 |
| // Changed rule name of lonely.via to lonely.via1 (2 rules) |
| // 07/08/2021 JAG nwell_missing_tap.1 deleted as duplicate of nwell.OVL.1 |
| // dnwell_missing_nwell.1 deleted as duplicate of dnwell.CON.4 |
| // Moved remaining "SOFT" checks to floating checks: |
| // pwell_missing_tap.1 became floating.net.pwell.R |
| // ptub_missing_tap.1 became floating.net.ptub.R |
| // subcut_missing_tap.1 became floating.net.localsub.R |
| // Renamed ptap.FL.1.R as floating.net.ptap.R for consistancy with other float checks |
| // Renamed ntap.FL.1.R as floating.net.ntap.R for consistancy with other float checks |
| // Removed SKIP_SOFT_CONNECT_CHECKS switch as all rules were moved to recommended rules |
| // 07/09/2021 JAG Rewrote hnwell section to NOT use areaid:hvnwell |
| // Removed v5.SP.1 as it was a duplicate of hnwell.SP.1 |
| // Removed hv.nwell.SP.1 as it was a duplicate of hnwell.SP.1 |
| // 07/15/2021 JAG Moved all nwell checks to nwell section (removed hnwell) |
| // 07/21/2021 RY Removed v20.CON.5 as it was a duplicate of v20.CON.2 |
| // |
| // 09/24/2021 JAG changed value from 0.55 to 0.50 for diff_tap_licon_space_gate_sc_hvtp_15 for |
| // licon.SP.10 per CB and PC |
| //////////////////////////////////////////////////////////////////////////////// |
| |
| // ******************************************************** |
| // Begin control statements |
| // ******************************************************** |
| |
| PRECISION 1000 |
| |
| UNIT LENGTH u |
| |
| DRC INCREMENTAL CONNECT YES |
| |
| DRC MAXIMUM RESULTS ALL |
| |
| // Tolerance for round-off errors on skew edges |
| DRC TOLERANCE FACTOR 0.001 |
| |
| // ******************************************************** |
| // End control statements |
| // ******************************************************** |
| |
| // ******************************************************** |
| // Begin layer definitions |
| // ******************************************************** |
| |
| LAYER nwell 1000 |
| LAYER MAP 64 DATATYPE 20 1000 // nwell drawing |
| |
| LAYER tunm 1001 |
| LAYER MAP 80 DATATYPE 20 1001 // tunm drawing |
| |
| LAYER diffii 1002 |
| LAYER MAP 65 DATATYPE 20 1002 // diff drawing |
| |
| LAYER polyii 1003 |
| LAYER MAP 66 DATATYPE 20 1003 // poly drawing |
| |
| LAYER lvtn 1004 |
| LAYER MAP 125 DATATYPE 44 1004 // lvtn drawing |
| |
| LAYER hvtp 1005 |
| LAYER MAP 78 DATATYPE 44 1005 // hvtp drawing |
| |
| LAYER npc 1006 |
| LAYER MAP 95 DATATYPE 20 1006 // npc drawing |
| |
| LAYER nsdm 1007 |
| LAYER MAP 93 DATATYPE 44 1007 // nsdm drawing |
| |
| LAYER psdm 1008 |
| LAYER MAP 94 DATATYPE 20 1008 // psdm drawing |
| |
| LAYER mcon 1009 |
| LAYER MAP 67 DATATYPE 44 1009 // mcon drawing |
| |
| LAYER met1ii 1010 |
| LAYER MAP 68 DATATYPE 20 1010 // met1 drawing |
| |
| LAYER m1res 1011 |
| LAYER MAP 68 DATATYPE 13 1011 // met1 res |
| |
| LAYER via1 1012 |
| LAYER MAP 68 DATATYPE 44 1012 // via1 drawing |
| |
| LAYER met2ii 1013 |
| LAYER MAP 69 DATATYPE 20 1013 // met2 drawing |
| |
| LAYER m2res 1014 |
| LAYER MAP 69 DATATYPE 13 1014 // met2 res |
| |
| LAYER via2 1015 |
| LAYER MAP 69 DATATYPE 44 1015 // via2 drawing |
| |
| LAYER met3ii 1016 |
| LAYER MAP 70 DATATYPE 20 1016 // met3 drawing |
| |
| LAYER m3res 1017 |
| LAYER MAP 70 DATATYPE 13 1017 // met3 res |
| |
| LAYER via3 1018 |
| LAYER MAP 70 DATATYPE 44 1018 // via3 drawing |
| |
| LAYER met4ii 1019 |
| LAYER MAP 71 DATATYPE 20 1019 // met4 drawing |
| |
| LAYER m4res 1020 |
| LAYER MAP 71 DATATYPE 13 1020 // met4 res |
| |
| LAYER via4 1021 |
| LAYER MAP 71 DATATYPE 44 1021 // via4 drawing |
| |
| LAYER met5ii 1022 |
| LAYER MAP 72 DATATYPE 20 1022 // met5 drawing |
| |
| LAYER m5res 1023 |
| LAYER MAP 72 DATATYPE 13 1023 // met5 res |
| |
| LAYER pad 1024 |
| LAYER MAP 76 DATATYPE 20 1024 // pad drawing |
| |
| LAYER licon 1025 |
| LAYER MAP 66 DATATYPE 44 1025 // licon drawing |
| |
| LAYER li_ii 1026 |
| LAYER MAP 67 DATATYPE 20 1026 // li drawing |
| |
| LAYER pnp 1028 |
| LAYER MAP 82 DATATYPE 44 1028 // pnp drawing |
| |
| LAYER npn 1029 |
| LAYER MAP 82 DATATYPE 20 1029 // npn drawing |
| |
| LAYER v5 1030 |
| LAYER MAP 75 DATATYPE 20 1030 // hvi drawing |
| |
| LAYER ldntm 1031 |
| LAYER MAP 11 DATATYPE 44 1031 // ldntm drawing |
| |
| LAYER capacitor 1032 |
| LAYER MAP 82 DATATYPE 64 1032 // capacitor drawing |
| |
| LAYER ncm 1033 |
| LAYER MAP 92 DATATYPE 44 1033 // ncm drawing |
| |
| LAYER rdl 1034 |
| LAYER MAP 74 DATATYPE 20 1034 // rdl drawing |
| |
| LAYER rpm 1035 |
| LAYER MAP 86 DATATYPE 20 1035 // rpm drawing |
| |
| LAYER inductor 1036 |
| LAYER MAP 82 DATATYPE 24 1036 // inductor drawing |
| |
| LAYER pmm 1037 |
| LAYER MAP 85 DATATYPE 44 1037 // pmm drawing |
| |
| LAYER ubm 1038 |
| LAYER MAP 127 DATATYPE 21 1038 // ubm drawing |
| |
| LAYER bump 1039 |
| LAYER MAP 127 DATATYPE 22 1039 // bump drawing |
| |
| LAYER cviam 1040 |
| LAYER MAP 105 DATATYPE 20 1040 // cviam drawing |
| |
| LAYER cmm1 1041 |
| LAYER MAP 62 DATATYPE 20 1041 // cmm1 drawing |
| |
| LAYER cmm2 1042 |
| LAYER MAP 105 DATATYPE 44 1042 // cmm2 drawing |
| |
| LAYER cmm3 1043 |
| LAYER MAP 107 DATATYPE 20 1043 // cmm3 drawing |
| |
| LAYER metop1 1044 |
| LAYER MAP 70 DATATYPE 32 1044 // met3 option1 |
| |
| LAYER metop2 1045 |
| LAYER MAP 70 DATATYPE 33 1045 // met3 option2 |
| |
| LAYER metop3 1046 |
| LAYER MAP 70 DATATYPE 34 1046 // met3 option3 |
| |
| LAYER metop4 1047 |
| LAYER MAP 70 DATATYPE 35 1047 // met3 option4 |
| |
| LAYER metop5 1048 |
| LAYER MAP 70 DATATYPE 36 1048 // met3 option5 |
| |
| LAYER metop6 1049 |
| LAYER MAP 70 DATATYPE 37 1049 // met3 option6 |
| |
| LAYER metop7 1050 |
| LAYER MAP 70 DATATYPE 38 1050 // met3 option7 |
| |
| LAYER metop8 1051 |
| LAYER MAP 70 DATATYPE 39 1051 // met3 option8 |
| |
| LAYER dnwell 1052 |
| LAYER MAP 64 DATATYPE 18 1052 // dnwell drawing |
| |
| LAYER DiodeID 1053 |
| LAYER MAP 81 DATATYPE 23 1053 // areaid diode |
| |
| LAYER ESDID 1054 |
| LAYER MAP 81 DATATYPE 19 1054 // areaid esd |
| |
| LAYER ENID 1055 |
| LAYER MAP 81 DATATYPE 57 1055 // areaid extendedDrain |
| |
| LAYER COREID 1056 |
| LAYER MAP 81 DATATYPE 2 1056 // areaid core |
| |
| LAYER SEALID 1057 |
| LAYER MAP 81 DATATYPE 1 1057 // areaid seal |
| |
| LAYER FRAMEID 1058 |
| LAYER MAP 81 DATATYPE 3 1058 // areaid frame |
| |
| LAYER LVID 1059 |
| LAYER MAP 81 DATATYPE 60 1059 // areaid lvNative |
| |
| LAYER STDCID 1060 |
| LAYER MAP 81 DATATYPE 4 1060 // areaid standardc |
| |
| LAYER localSub 1061 |
| LAYER MAP 81 DATATYPE 53 1061 // areaid substrateCut |
| |
| LAYER PHdiodeID 1062 |
| LAYER MAP 81 DATATYPE 81 1062 // areaid photo |
| |
| LAYER diffRes 1063 |
| LAYER MAP 65 DATATYPE 13 1063 // diff res |
| |
| LAYER fuse 1064 |
| LAYER MAP 71 DATATYPE 17 1064 // met4 fuse |
| |
| //LAYER padCenter 1065 |
| // LAYER MAP 81 DATATYPE 20 1065 // padCenter drawing |
| |
| //LAYER prune 1066 |
| // LAYER MAP 84 DATATYPE 44 1066 // prune drawing |
| |
| LAYER polyres 1067 |
| LAYER MAP 66 DATATYPE 13 1067 // poly res |
| |
| LAYER lires 1068 |
| LAYER MAP 67 DATATYPE 13 1068 // li res |
| |
| LAYER pwres 1069 |
| LAYER MAP 64 DATATYPE 13 1069 // pwell res |
| |
| LAYER clvom 1070 |
| LAYER MAP 45 DATATYPE 20 1070 // clvom drawing |
| |
| LAYER cntm 1071 |
| LAYER MAP 26 DATATYPE 20 1071 // cntm drawing |
| |
| LAYER chvntm 1072 |
| LAYER MAP 38 DATATYPE 20 1072 // chvntm drawing |
| |
| LAYER cnpc 1073 |
| LAYER MAP 44 DATATYPE 20 1073 // cnpc drawing |
| |
| LAYER cnsdm 1074 |
| LAYER MAP 29 DATATYPE 20 1074 // cnsdm drawing |
| |
| LAYER cpsdm 1075 |
| LAYER MAP 31 DATATYPE 20 1075 // cpsdm drawing |
| |
| LAYER cli1m 1076 |
| LAYER MAP 115 DATATYPE 44 1076 // cli1m drawing |
| |
| LAYER cviam3 1077 |
| LAYER MAP 112 DATATYPE 20 1077 // cviam3 drawing |
| |
| LAYER cviam4 1078 |
| LAYER MAP 117 DATATYPE 20 1078 // cviam4 drawing |
| |
| LAYER pmm2 1079 |
| LAYER MAP 77 DATATYPE 20 1079 // pmm2 drawing |
| |
| LAYER conom 1080 |
| LAYER MAP 87 DATATYPE 44 1080 // conom drawing |
| |
| LAYER chvtpm 1081 |
| LAYER MAP 88 DATATYPE 44 1081 // chvtpm drawing |
| |
| LAYER clvtnm 1082 |
| LAYER MAP 25 DATATYPE 44 1082 |
| |
| LAYER cfom 1083 |
| LAYER MAP 22 DATATYPE 20 1083 |
| |
| LAYER hvtr 1084 |
| LAYER MAP 18 DATATYPE 20 1084 |
| |
| LAYER hvntm 1085 |
| LAYER MAP 125 DATATYPE 20 1085 |
| |
| LAYER nsm 1086 |
| LAYER MAP 61 DATATYPE 20 1086 |
| |
| LAYER padtt 1087 1088 |
| LAYER MAP 76 TEXTTYPE 20 1087 // pad drawing |
| LAYER MAP 76 TEXTTYPE 5 1088 // pad label |
| |
| LAYER rdltt 1089 1090 |
| LAYER MAP 74 TEXTTYPE 20 1089 // rdl drawing |
| LAYER MAP 74 TEXTTYPE 5 1090 // rdl label |
| |
| LAYER met5tt 1091 |
| LAYER MAP 72 TEXTTYPE 5 1091 // met5 label |
| |
| LAYER met4tt 1092 |
| LAYER MAP 71 TEXTTYPE 5 1092 // met4 label |
| |
| LAYER met3tt 1093 |
| LAYER MAP 70 TEXTTYPE 5 1093 // met3 label |
| |
| LAYER met2tt 1094 |
| LAYER MAP 69 TEXTTYPE 5 1094 // met2 label |
| |
| LAYER met1tt 1095 |
| LAYER MAP 68 TEXTTYPE 5 1095 // met1 label |
| |
| LAYER litt 1096 |
| LAYER MAP 67 TEXTTYPE 5 1096 // li label |
| |
| LAYER polytt 1097 |
| LAYER MAP 66 TEXTTYPE 5 1097 // poly label |
| |
| LAYER difftt 1098 |
| LAYER MAP 65 TEXTTYPE 6 1098 // diff label |
| |
| LAYER pwelltt 1099 |
| LAYER MAP 64 TEXTTYPE 59 1099 // pwell label |
| |
| //LAYER pwellisott 1100 |
| // LAYER MAP 44 TEXTTYPE 5 1100 // pwelliso label |
| |
| LAYER nwelltt 1101 |
| LAYER MAP 64 TEXTTYPE 5 1101 // nwell label |
| |
| LAYER textdraw 1102 |
| LAYER MAP 83 TEXTTYPE 44 1102 // text drawing |
| |
| LAYER pwell_pin 1103 |
| LAYER MAP 122 DATATYPE 16 1103 // pwell pin |
| |
| //LAYER pwelliso_pin 1104 |
| // LAYER MAP 44 DATATYPE 16 1104 // pwelliso pin |
| |
| LAYER nwell_pin 1105 |
| LAYER MAP 64 DATATYPE 16 1105 // nwell pin |
| |
| LAYER diff_pin 1106 |
| LAYER MAP 65 DATATYPE 16 1106 // diff pin |
| |
| LAYER poly_pin 1107 |
| LAYER MAP 66 DATATYPE 16 1107 // poly pin |
| |
| LAYER li_pin 1108 |
| LAYER MAP 67 DATATYPE 16 1108 // li pin |
| |
| LAYER met1_pin 1109 |
| LAYER MAP 68 DATATYPE 16 1109 // met1 pin |
| |
| LAYER met2_pin 1110 |
| LAYER MAP 69 DATATYPE 16 1110 // met2 pin |
| |
| LAYER met3_pin 1111 |
| LAYER MAP 70 DATATYPE 16 1111 // met3 pin |
| |
| LAYER met4_pin 1112 |
| LAYER MAP 71 DATATYPE 16 1112 // met4 pin |
| |
| LAYER met5_pin 1113 |
| LAYER MAP 72 DATATYPE 16 1113 // met5 pin |
| |
| LAYER rdl_pin 1114 |
| LAYER MAP 74 DATATYPE 16 1114 // rdl pin |
| |
| LAYER pad_pin 1115 |
| LAYER MAP 76 DATATYPE 16 1115 // pad pin |
| |
| LAYER pwellpt 1116 |
| LAYER MAP 122 TEXTTYPE 16 1116 // pwell pin |
| LAYER MAP 122 TEXTTYPE 0 1116 // pwell pin |
| |
| //LAYER pwellisopt 1117 |
| // LAYER MAP 44 TEXTTYPE 16 1117 // pwelliso pin |
| // LAYER MAP 44 TEXTTYPE 0 1117 // pwelliso pin |
| |
| LAYER nwellpt 1118 |
| LAYER MAP 64 TEXTTYPE 16 1118 // nwell pin |
| LAYER MAP 64 TEXTTYPE 0 1118 // nwell pin |
| |
| LAYER diffpt 1119 |
| LAYER MAP 65 TEXTTYPE 16 1119 // diff pin |
| LAYER MAP 65 TEXTTYPE 0 1119 // diff pin |
| |
| LAYER polypt 1120 |
| LAYER MAP 66 TEXTTYPE 16 1120 // poly pin |
| LAYER MAP 66 TEXTTYPE 0 1120 // poly pin |
| |
| LAYER lipt 1121 |
| LAYER MAP 67 TEXTTYPE 16 1121 // li pin |
| LAYER MAP 67 TEXTTYPE 0 1121 // li pin |
| |
| LAYER met1pt 1122 |
| LAYER MAP 68 TEXTTYPE 16 1122 // met1 pin |
| LAYER MAP 68 TEXTTYPE 0 1122 // met1 pin |
| |
| LAYER met2pt 1123 |
| LAYER MAP 69 TEXTTYPE 16 1123 // met2 pin |
| LAYER MAP 69 TEXTTYPE 0 1123 // met2 pin |
| |
| LAYER met3pt 1124 |
| LAYER MAP 70 TEXTTYPE 16 1124 // met3 pin |
| LAYER MAP 70 TEXTTYPE 0 1124 // met3 pin |
| |
| LAYER met4pt 1125 |
| LAYER MAP 71 TEXTTYPE 16 1125 // met4 pin |
| LAYER MAP 71 TEXTTYPE 0 1125 // met4 pin |
| |
| LAYER met5pt 1126 |
| LAYER MAP 72 TEXTTYPE 16 1126 // met5 pin |
| LAYER MAP 72 TEXTTYPE 0 1126 // met5 pin |
| |
| LAYER rdlpt 1127 |
| LAYER MAP 74 TEXTTYPE 16 1127 // rdl pin |
| LAYER MAP 74 TEXTTYPE 0 1127 // rdl pin |
| |
| LAYER padpt 1128 |
| LAYER MAP 76 TEXTTYPE 16 1128 // pad pin |
| LAYER MAP 76 TEXTTYPE 0 1128 // pad pin |
| |
| LAYER met5probe 1129 |
| LAYER MAP 72 TEXTTYPE 25 1129 // met5 probe |
| |
| LAYER met4probe 1130 |
| LAYER MAP 71 TEXTTYPE 25 1130 // met4 probe |
| |
| LAYER met3probe 1131 |
| LAYER MAP 70 TEXTTYPE 25 1131 // met3 probe |
| |
| LAYER met2probe 1132 |
| LAYER MAP 69 TEXTTYPE 25 1132 // met2 probe |
| |
| LAYER met1probe 1133 |
| LAYER MAP 68 TEXTTYPE 25 1133 // met1 probe |
| |
| LAYER liprobe 1134 |
| LAYER MAP 67 TEXTTYPE 25 1134 // li probe |
| |
| LAYER polyprobe 1135 |
| LAYER MAP 66 TEXTTYPE 25 1135 // poly probe |
| |
| LAYER fomWaffDrop 1136 |
| LAYER MAP 22 DATATYPE 24 1136 // cfom waffleDrop |
| |
| LAYER moduleCutAREA 1137 |
| LAYER MAP 81 DATATYPE 10 1137 // areaid moduleCut |
| |
| LAYER indLabel 1138 |
| LAYER MAP 82 TEXTTYPE 25 1138 // inductor label |
| |
| LAYER indTerm1 1139 |
| LAYER MAP 82 DATATYPE 26 1139 // inductor term1 |
| |
| LAYER indTerm2 1140 |
| LAYER MAP 82 DATATYPE 27 1140 // inductor term2 |
| |
| LAYER indTerm3 1141 |
| LAYER MAP 82 DATATYPE 28 1141 // inductor term3 |
| |
| LAYER capm 1142 |
| LAYER MAP 89 DATATYPE 44 1142 // capm drawing |
| |
| LAYER cap2m 1143 |
| LAYER MAP 97 DATATYPE 44 1143 // cap2m drawing |
| |
| LAYER urpm 1144 |
| LAYER MAP 79 DATATYPE 20 1144 // urpm drawing |
| |
| //LAYER EXTDRAIN20 1145 |
| // LAYER MAP 81 DATATYPE 58 1145 // extd20v drawing |
| |
| LAYER pwbm 1146 |
| LAYER MAP 19 DATATYPE 44 1146 // pwbm drawing |
| |
| LAYER pwde 1147 |
| LAYER MAP 124 DATATYPE 20 1147 // pwbm drawing |
| |
| LAYER LOWVTID 1148 |
| LAYER MAP 81 DATATYPE 108 1148 // areaid low_vt drawing |
| |
| LAYER v20 1149 |
| LAYER MAP 74 DATATYPE 22 1149 // uhvi drawing |
| |
| LAYER v12 1150 |
| LAYER MAP 74 DATATYPE 21 1150 // vhvi drawing |
| |
| LAYER LVTNMdg 1151 |
| // 1151 -> clvtnm drawing |
| |
| LAYER HVTPMdg 1152 |
| // 1152 -> chvtpm drawing |
| |
| LAYER HVNTMdg 1153 |
| // 1153 -> chvntm drawing |
| |
| //LAYER NTMdg 1154 |
| // 1154 -> cntm drawing |
| |
| LAYER NTMdrop 1155 |
| LAYER MAP 26 DATATYPE 22 1155 // cntm maskDrop |
| |
| LAYER LVTNMdrop 1156 |
| LAYER MAP 25 DATATYPE 42 1156 // clvtnm maskDrop |
| |
| LAYER HVTPMdrop 1157 |
| LAYER MAP 97 DATATYPE 42 1157 // chvtpm maskDrop |
| |
| LAYER LI1Mdrop 1158 |
| LAYER MAP 115 DATATYPE 42 1158 // cli1m maskDrop |
| |
| LAYER LICM1drop 1159 |
| LAYER MAP 106 DATATYPE 42 1159 // clicm1 maskDrop |
| |
| LAYER PSDMdrop 1160 |
| LAYER MAP 31 DATATYPE 22 1160 // cpsdm maskDrop |
| |
| LAYER NSDMdrop 1161 |
| LAYER MAP 29 DATATYPE 22 1161 // cnsdm maskDrop |
| |
| LAYER P1Mdrop 1162 |
| LAYER MAP 33 DATATYPE 42 1162 // cp1m maskDrop |
| |
| LAYER FOMdrop 1163 |
| LAYER MAP 22 DATATYPE 22 1163 // cfom maskDrop |
| |
| LAYER NTMadd 1164 |
| LAYER MAP 26 DATATYPE 21 1164 // cntm maskAdd |
| |
| LAYER LVTNMadd 1165 |
| LAYER MAP 25 DATATYPE 43 1165 // clvtnm maskAdd |
| |
| LAYER HVTPMadd 1166 |
| LAYER MAP 97 DATATYPE 43 1166 // chvtpm maskAdd |
| |
| LAYER LI1Madd 1167 |
| LAYER MAP 115 DATATYPE 43 1167 // cli1m maskAdd |
| |
| LAYER LICM1add 1168 |
| LAYER MAP 106 DATATYPE 43 1168 // clicm1 maskAdd |
| |
| LAYER PSDMadd 1169 |
| LAYER MAP 31 DATATYPE 21 1169 // cpsdm maskAdd |
| |
| LAYER NSDMadd 1170 |
| LAYER MAP 29 DATATYPE 21 1170 // cnsdm maskAdd |
| |
| LAYER P1Madd 1171 |
| LAYER MAP 33 DATATYPE 43 1171 // cp1m maskAdd |
| |
| LAYER FOMadd 1172 |
| LAYER MAP 22 DATATYPE 21 1172 // cfom maskAdd |
| |
| LAYER PMM2mk 1173 |
| LAYER MAP 94 DATATYPE 0 1173 // cpmm2 mask |
| |
| LAYER CU1Mmk 1174 |
| LAYER MAP 93 DATATYPE 0 1174 // ccu1m mask |
| |
| LAYER RPMmk 1175 |
| LAYER MAP 96 DATATYPE 0 1175 // crpm mask |
| |
| LAYER PBOmk 1176 |
| LAYER MAP 99 DATATYPE 0 1176 // cpbo mask |
| |
| LAYER PDMmk 1177 |
| LAYER MAP 37 DATATYPE 0 1177 // cpdm mask |
| |
| LAYER NSMmk 1178 |
| LAYER MAP 22 DATATYPE 0 1178 // cnsm mask |
| |
| LAYER MM5mk 1179 |
| LAYER MAP 59 DATATYPE 0 1179 // cmm5 mask |
| |
| LAYER VIM4mk 1180 |
| LAYER MAP 58 DATATYPE 0 1180 // cviam4 mask |
| |
| LAYER MM4mk 1181 |
| LAYER MAP 51 DATATYPE 0 1181 // cmm4 mask |
| |
| LAYER VIM3mk 1182 |
| LAYER MAP 50 DATATYPE 0 1182 // cviam3 mask |
| |
| LAYER MM3mk 1183 |
| LAYER MAP 34 DATATYPE 0 1183 // cmm3 mask |
| |
| LAYER VIM2mk 1184 |
| LAYER MAP 44 DATATYPE 0 1184 // cviam2 mask |
| |
| LAYER MM2mk 1185 |
| LAYER MAP 41 DATATYPE 0 1185 // cmm2 mask |
| |
| LAYER VIMmk 1186 |
| LAYER MAP 40 DATATYPE 0 1186 // cviam mask |
| |
| LAYER MM1mk 1187 |
| LAYER MAP 36 DATATYPE 0 1187 // cmm1 mask |
| |
| LAYER CTM1mk 1188 |
| LAYER MAP 35 DATATYPE 0 1188 // cctm1 mask |
| |
| LAYER LI1Mmk 1189 |
| LAYER MAP 56 DATATYPE 0 1189 // cli1m mask |
| |
| LAYER LICM1mk 1190 |
| LAYER MAP 43 DATATYPE 0 1190 // clicm1 mask |
| |
| LAYER PSDMmk 1191 |
| LAYER MAP 32 DATATYPE 0 1191 // cpsdm mask |
| |
| LAYER NSDMmk 1192 |
| LAYER MAP 30 DATATYPE 0 1192 // cnsdm mask |
| |
| LAYER LDNTMmk 1193 |
| LAYER MAP 11 DATATYPE 0 1193 // cldntm mask |
| |
| LAYER NPCMmk 1194 |
| LAYER MAP 49 DATATYPE 0 1194 // cnpc mask |
| |
| LAYER HVNTMmk 1195 |
| LAYER MAP 39 DATATYPE 0 1195 // chvntm mask |
| |
| LAYER NTMmk 1196 |
| LAYER MAP 27 DATATYPE 0 1196 // cntm mask |
| |
| LAYER P1Mmk 1197 |
| LAYER MAP 28 DATATYPE 0 1197 // cp1m mask |
| |
| LAYER LVOMmk 1198 |
| LAYER MAP 46 DATATYPE 0 1198 // clvom mask |
| |
| LAYER ONOMmk 1199 |
| LAYER MAP 88 DATATYPE 0 1199 // conom mask |
| |
| LAYER TUNMmk 1200 |
| LAYER MAP 20 DATATYPE 0 1200 // ctunm mask |
| |
| LAYER HVTRMmk 1201 |
| LAYER MAP 98 DATATYPE 0 1201 // chvtrm mask |
| |
| LAYER HVTPMmk 1202 |
| LAYER MAP 97 DATATYPE 0 1202 // chvtpm mask |
| |
| LAYER LVTNMmk 1203 |
| LAYER MAP 25 DATATYPE 0 1203 // clvtnm mask |
| |
| LAYER NWMmk 1204 |
| LAYER MAP 21 DATATYPE 0 1204 // cnwm mask |
| |
| LAYER DNMmk 1205 |
| LAYER MAP 48 DATATYPE 0 1205 // cdnm mask |
| |
| LAYER FOMmk 1206 |
| LAYER MAP 23 DATATYPE 0 1206 // cfom mask |
| |
| LAYER met5Pin 1207 // met5 pin |
| LAYER MAP 72 DATATYPE 16 1207 // met5 pin |
| |
| LAYER met4Pin 1208 // met4 pin |
| LAYER MAP 71 DATATYPE 16 1208 // met4 pin |
| |
| LAYER met3Pin 1209 // met3 pin |
| LAYER MAP 70 DATATYPE 16 1209 // met3 pin |
| |
| LAYER met2Pin 1210 // met2 pin |
| LAYER MAP 69 DATATYPE 16 1210 // met2 pin |
| |
| LAYER met1Pin 1211 // met1 pin |
| LAYER MAP 68 DATATYPE 16 1211 // met1 pin |
| |
| LAYER liPin 1212 // li pin |
| LAYER MAP 67 DATATYPE 16 1212 // li pin |
| |
| LAYER polyPin 1213 // poly pin |
| LAYER MAP 66 DATATYPE 16 1213 // poly pin |
| |
| LAYER diffPin 1214 // diff pin |
| LAYER MAP 65 DATATYPE 16 1214 // diff pin |
| |
| LAYER cmm4WaffleDrop 1215 |
| LAYER MAP 112 DATATYPE 4 1215 // cmm4 waffleDrop |
| |
| LAYER cmm3WaffleDrop 1216 |
| LAYER MAP 107 DATATYPE 24 1216 // cmm3 waffleDrop |
| |
| LAYER cmm2WaffleDrop 1217 |
| LAYER MAP 105 DATATYPE 52 1217 // cmm2 waffleDrop |
| |
| LAYER cmm1WaffleDrop 1218 |
| LAYER MAP 62 DATATYPE 24 1218 // cmm1 waffleDrop |
| |
| LAYER cp1mWaffleDrop 1219 |
| LAYER MAP 33 DATATYPE 24 1219 // cp1m waffleDrop |
| |
| LAYER cfomWaffleDrop 1220 |
| LAYER MAP 22 DATATYPE 24 1220 // cfom waffleDrop |
| |
| LAYER pwellLabel 1221 |
| LAYER MAP 64 DATATYPE 5 1221 // pwell label |
| |
| //LAYER fomDummyDRC 1222 |
| // LAYER MAP 22 DATATYPE 23 1222 // fom dummy |
| |
| LAYER viatop 1224 |
| LAYER MAP 203 DATATYPE 2 1224 // viatop drawing |
| |
| LAYER ccorner 1225 |
| LAYER MAP 81 DATATYPE 51 1225 // areaid critCorner |
| |
| LAYER critside 1226 |
| LAYER MAP 81 DATATYPE 52 1226 // areaid critSid |
| |
| LAYER ANALOGID 1227 |
| LAYER MAP 81 DATATYPE 79 1227 // areaid analog |
| |
| //LAYER pwell_dg 1228 // pwell drawing |
| // LAYER MAP 64 DATATYPE 44 1228 |
| |
| LAYER dieCut 1229 // areaid dieCut |
| LAYER MAP 81 DATATYPE 11 1229 |
| |
| LAYER frameBndr 1230 |
| LAYER MAP 81 DATATYPE 12 1230 // areaid frameRect |
| |
| LAYER padText 1231 |
| LAYER MAP 76 TEXTTYPE 5 1231 // pad label |
| |
| LAYER ETESTID 1232 |
| LAYER MAP 81 DATATYPE 101 1232 // areaid etest |
| |
| LAYER ccapm 1233 |
| LAYER MAP 89 DATATYPE 45 1233 // capm mask |
| |
| LAYER target 1234 |
| LAYER MAP 76 DATATYPE 44 1234 // capm mask |
| |
| LAYER HVNID 1235 |
| LAYER MAP 81 DATATYPE 63 1235 // areaid hvnwell |
| |
| LAYER met1_block 1236 |
| LAYER MAP 68 DATATYPE 10 1236 // metal1 blockage |
| |
| LAYER met2_block 1237 |
| LAYER MAP 69 DATATYPE 10 1237 // metal2 blockage |
| |
| LAYER met3_block 1238 |
| LAYER MAP 70 DATATYPE 10 1238 // metal3 blockage |
| |
| LAYER met4_block 1239 |
| LAYER MAP 71 DATATYPE 10 1239 // metal4 blockage |
| |
| LAYER met5_block 1240 |
| LAYER MAP 72 DATATYPE 10 1240 // metal5 blockage |
| |
| LAYER li_block 1241 |
| LAYER MAP 67 DATATYPE 10 1241 // li blockage |
| |
| LAYER cmm5WaffleDrop 1242 |
| LAYER MAP 117 DATATYPE 4 1242 // cmm5 waffleDrop |
| |
| LAYER tap_old 1243 |
| LAYER MAP 65 DATATYPE 44 1243 // read in layer tap from S8 datatbases |
| |
| LAYER diffhvp 1244 |
| LAYER MAP 65 DATATYPE 8 1244 // diff hv |
| |
| LAYER polyGate 1245 |
| LAYER MAP 66 DATATYPE 9 1245 // poly gate |
| |
| LAYER prBndry 1246 |
| LAYER MAP 235 DATATYPE 4 1246 // prBoundary boundary |
| |
| //LAYER polyBndry 1247 |
| // LAYER MAP 66 DATATYPE 4 1247 // poly boundary |
| |
| //LAYER diffBndry 1248 |
| // LAYER MAP 65 DATATYPE 4 1248 // diff boundary |
| |
| LAYER sigPadMetNtr 1249 |
| LAYER MAP 81 DATATYPE 8 1249 // areaid sig_pad_met_not_res |
| |
| LAYER sigPadWell 1250 |
| LAYER MAP 81 DATATYPE 7 1250 // areaid sig_pad_well |
| |
| LAYER sigPadDiff 1251 |
| LAYER MAP 81 DATATYPE 6 1251 // areaid sig_pad_diff |
| |
| LAYER LTDID 1252 |
| LAYER MAP 81 DATATYPE 14 1252 // areaid lowTapDensity |
| |
| LAYER NTMdg 1253 // cntm drawing |
| LAYER MAP 26 DATATYPE 20 1253 |
| |
| LAYER pwcut 1254 // pwell cut |
| LAYER MAP 64 DATATYPE 14 1254 |
| |
| LAYER deadzoneID 1255 |
| LAYER MAP 81 DATATYPE 50 1255 // areaid deadZon |
| |
| LAYER notCritSideID 1256 |
| LAYER MAP 81 DATATYPE 15 1256 // areaid notCritSide |
| |
| LAYER met1Block 1257 |
| LAYER MAP 68 DATATYPE 10 1257 // met1 blockage |
| |
| LAYER met2Block 1258 |
| LAYER MAP 69 DATATYPE 10 1258 // met2 blockage |
| |
| LAYER met3Block 1259 |
| LAYER MAP 70 DATATYPE 10 1259 // met3 blockage |
| |
| LAYER met4Block 1260 |
| LAYER MAP 71 DATATYPE 10 1260 // met4 blockage |
| |
| LAYER met5Block 1261 |
| LAYER MAP 72 DATATYPE 10 1261 // met5 blockage |
| |
| LAYER liBlock 1262 |
| LAYER MAP 67 DATATYPE 10 1262 // li blockage |
| |
| LAYER thkox 1263 |
| LAYER MAP 75 DATATYPE 21 1263 // thick oxide drawing |
| |
| LAYER pad_length 1264 |
| LAYER MAP 81 DATATYPE 67 1264 // pad length marker |
| |
| LAYER polyModeltt 1265 |
| LAYER MAP 66 TEXTTYPE 83 1265 |
| |
| LAYER pad_io 1266 |
| LAYER MAP 81 DATATYPE 70 1266 |
| |
| LAYER pad_pwr 1267 |
| LAYER MAP 81 DATATYPE 71 1267 |
| |
| LAYER pad_gnd 1268 |
| LAYER MAP 81 DATATYPE 72 1268 |
| |
| LAYER polyModel 1269 |
| LAYER MAP 66 DATATYPE 83 1269 |
| |
| LAYER rrpm 1270 |
| LAYER MAP 102 DATATYPE 20 1270 // rrpm drawing |
| |
| LAYER diff_fill 1271 |
| LAYER MAP 65 DATATYPE 99 1271 // diff fill |
| |
| LAYER poly_fill 1272 |
| LAYER MAP 66 DATATYPE 99 1272 // poly fill |
| |
| LAYER li_fill 1273 |
| LAYER MAP 67 DATATYPE 99 1273 // li fill |
| |
| LAYER m1_fill 1274 |
| LAYER MAP 68 DATATYPE 99 1274 // m1 fill |
| |
| LAYER m2_fill 1275 |
| LAYER MAP 69 DATATYPE 99 1275 // m2 fill |
| |
| LAYER m3_fill 1276 |
| LAYER MAP 70 DATATYPE 99 1276 // m3 fill |
| |
| LAYER m4_fill 1277 |
| LAYER MAP 71 DATATYPE 99 1277 // m4 fill |
| |
| LAYER m5_fill 1278 |
| LAYER MAP 72 DATATYPE 99 1278 // m5 fill |
| |
| LAYER LVS_exclude 1279 |
| LAYER MAP 84 DATATYPE 44 1279 // LVS_exclude drawing |
| |
| LAYER poly_block 1280 |
| LAYER MAP 66 DATATYPE 98 1280 // poly fill block |
| |
| LAYER diff_block 1281 |
| LAYER MAP 65 DATATYPE 98 1281 // diff fill block |
| |
| boundary = EXTENT DRAWN ORIGINAL |
| |
| LAYOUT BASE LAYER diffii polyii pnp npn nsdm psdm thkox v5 v12 v20 lvtn hvtp |
| |
| // ******************************************************** |
| // End layer definitions |
| // ******************************************************** |
| |
| // ******************************************************** |
| // Start TVF function definitions |
| // ******************************************************** |
| |
| // If layer1 is empty, return layer2 or return nothing: |
| TVF FUNCTION CALtvfLay2OrEmpty [/* |
| tvf::GET_LAYER_ARGS layer1 layer2 emptyLayer |
| if {[tvf::IS_LAYER_EMPTY $layer1]} { |
| tvf::OUTLAYER "COPY $layer2" |
| } else { |
| tvf::OUTLAYER "COPY $emptyLayer" |
| } |
| */] |
| |
| // ******************************************************** |
| // End TVF function definitions |
| // ******************************************************** |
| |
| // ******************************************************** |
| // Begin merge of fill layers with design layers |
| // ******************************************************** |
| |
| } |
| |
| SETLAYER diffi = "OR diff_fill diffii tap_old" |
| SETLAYER polyi = "poly_fill OR polyii" |
| SETLAYER li_i = "li_fill OR li_ii" |
| SETLAYER met1i = "m1_fill OR met1ii" |
| SETLAYER met2i = "m2_fill OR met2ii" |
| SETLAYER met3i = "m3_fill OR met3ii" |
| SETLAYER met4i = "m4_fill OR met4ii" |
| SETLAYER met5i = "m5_fill OR met5ii" |
| |
| verbatim { |
| |
| // ******************************************************** |
| // Begin base logical operations |
| // ******************************************************** |
| |
| } |
| |
| SETLAYER exempt_tech_CD = "EXTENT CELL \"*_tech_CD_top*\"" |
| |
| # JAG 7/9/20 added to |
| # identify nikon cross for later exclusionary purposes: |
| SETLAYER nikon_1 = HOLES LDNTMmk |
| SETLAYER nikon_2 = LDNTMmk OR nikon_1 |
| SETLAYER nikon_3 = VERTEX nikon_2 == 8 |
| SETLAYER nikon_cross = nikon_3 ENCLOSE (((VIMmk AND VIM2mk) AND VIM3mk) AND VIM4mk) |
| |
| SETLAYER dnwell_touch_pwbm_touch_extd20 = "dnwell AND ((pwbm OR (HOLES pwbm)) INTERACT ENID)" |
| SETLAYER dnwell_not_extended_drain = "dnwell NOT dnwell_touch_pwbm_touch_extd20" |
| SETLAYER localSub_not_size_localSub = "localSub NOT (SIZE localSub BY -0.005)" |
| SETLAYER dnwell_not_dnwell_ext_drain = "dnwell_not_extended_drain AND nwell" |
| SETLAYER sub_iso_other = "boundary NOT ((dnwell_not_extended_drain NOT (SIZE dnwell_not_extended_drain BY -0.01)) OR dnwell_not_dnwell_ext_drain)" |
| SETLAYER sub_local = "sub_iso_other NOT localSub_not_size_localSub" |
| SETLAYER substrate_not_npn = "sub_local NOT npn" |
| SETLAYER pwellresistor = "pwres AND dnwell" |
| SETLAYER pwell1 = "substrate_not_npn NOT pwellresistor" |
| SETLAYER iso_pw_basic = "((dnwell INTERACT nwell) NOT nwell) NOT INTERACT ENID" |
| SETLAYER dnw_not_nw = "dnwell NOT nwell" |
| SETLAYER nw_hole = "HOLES nwell" |
| SETLAYER nw_hole_not_nw = "nw_hole NOT nwell" |
| SETLAYER nw_hole_outside_dnw = "XOR nw_hole_not_nw dnw_not_nw" |
| SETLAYER dnw_to_remove_iso_pw = "dnw_not_nw INTERACT nw_hole_outside_dnw" |
| SETLAYER ptub = "iso_pw_basic NOT dnw_to_remove_iso_pw" |
| SETLAYER pwell = "pwell1 NOT (OR pwbm ptub nwell localSub)" |
| |
| SETLAYER ntap = "((nsdm AND diffi) AND nwell) NOT (polyi AND ENID)" |
| SETLAYER ptap = "(((psdm AND diffi) NOT nwell) NOT (polyi AND ENID)) NOT (dnwell NOT ptub)" |
| SETLAYER tap = "OR ptap ntap" |
| |
| SETLAYER diff1 = "diffi NOT tap" |
| SETLAYER pdiff = "(diffi AND nwell) AND psdm" |
| SETLAYER ndiff = "(diffi NOT nwell) AND nsdm" |
| SETLAYER nsd = "(((diffi AND nsdm) NOT polyi) NOT diffres) NOT ntap" |
| SETLAYER psd = "(((diffi AND psdm) NOT polyi) NOT diffres) NOT ptap" |
| SETLAYER ptubtap = "(diffi and psdm) AND ptub" |
| SETLAYER diffTap = "OR tap diff1" |
| SETLAYER srcdrn = "(OR psd nsd) NOT polyi" |
| |
| # ry |
| SETLAYER nsrcdrn = "srcdrn AND ndiff" |
| SETLAYER psrcdrn = "srcdrn AND pdiff" |
| |
| SETLAYER polyAndDiff = "polyi AND diff1" |
| SETLAYER gate = "COPY POLYandDIFF" |
| SETLAYER ngate = "gate NOT nwell" |
| SETLAYER pgate = "gate AND nwell" |
| SETLAYER gateside = "GATE INSIDE EDGE diff1" |
| SETLAYER gateend = "GATE COINCIDENT INSIDE EDGE diff1" |
| SETLAYER diffTapEdge = "diff1 COINCIDENT OUTSIDE EDGE tap" |
| SETLAYER MOSGATE = "COPY GATE" |
| SETLAYER EMOSGATE = "COPY MOSGATE" |
| SETLAYER nDiffTap = "NDIFF OR NTAP" |
| SETLAYER pDiffTap = "PDIFF OR PTAP" |
| SETLAYER gate_PERI = "GATE NOT COREID" |
| SETLAYER pdiff_PERI = "PDIFF NOT COREID" |
| SETLAYER pdiff_CORE = "PDIFF AND COREID" |
| SETLAYER ndiff_CORE = "NDIFF AND COREID" |
| SETLAYER ndiff_PERI = "NDIFF NOT COREID" |
| SETLAYER emosgate_PERI = "EMOSGATE NOT COREID" |
| SETLAYER emosgate_CORE = "EMOSGATE AND COREID" |
| SETLAYER poly_PERI = "polyi NOT COREID" |
| SETLAYER poly_CORE = "polyi AND COREID" |
| SETLAYER li1_PERI = "li_i NOT COREID" |
| SETLAYER li1_CORE = "li_i AND COREID" |
| SETLAYER licon1_PERI = "licon NOT COREID" |
| SETLAYER licon1_CORE = "licon AND COREID" |
| SETLAYER diff_PERI = "diff1 NOT COREID" |
| SETLAYER diff_CORE = "diff1 AND COREID" |
| SETLAYER tap_PERI = "tap NOT COREID" |
| SETLAYER tap_CORE = "tap AND COREID" |
| SETLAYER diffTap_CORE = "diffTap AND COREID" |
| SETLAYER diffTap_PERI = "diffTap NOT COREID" |
| SETLAYER mcon_PERI = "mcon NOT COREID" |
| SETLAYER mcon_CORE = "mcon AND COREID" |
| SETLAYER hvtp_PERI = "hvtp NOT COREID" |
| SETLAYER hvtp_CORE = "hvtp AND COREID" |
| SETLAYER lvtn_PERI = "lvtn NOT COREID" |
| SETLAYER lvtn_CORE = "lvtn AND COREID" |
| SETLAYER nsdm_PERI = "nsdm NOT COREID" |
| SETLAYER nsdm_CORE = "nsdm AND COREID" |
| SETLAYER psdm_PERI = "psdm NOT COREID" |
| SETLAYER psdm_CORE = "psdm AND COREID" |
| SETLAYER PTAP_PERI = "PTAP NOT COREID" |
| SETLAYER PTAP_CORE = "PTAP AND COREID" |
| SETLAYER NTAP_PERI = "NTAP NOT COREID" |
| SETLAYER NTAP_CORE = "NTAP AND COREID" |
| SETLAYER via_PERI = "via1 NOT COREID" |
| SETLAYER via_CORE = "via1 AND COREID" |
| SETLAYER via2_PERI = "via2 NOT COREID" |
| SETLAYER via2_CORE = "via2 AND COREID" |
| |
| #SETLAYER pwell_res_body = "pwell_dg NOT pwres" |
| SETLAYER diff = "diff1 NOT diffres" |
| SETLAYER poly = "polyi NOT polyres" |
| SETLAYER li = "li_i NOT lires" |
| SETLAYER met1 = "met1i NOT m1res" |
| SETLAYER met2 = "met2i NOT m2res" |
| SETLAYER met3 = "met3i NOT m3res" |
| SETLAYER met4 = "met4i NOT m4res" |
| SETLAYER met5 = "met5i NOT m5res" |
| SETLAYER m3_bot_plate = "SIZE (capm AND met3) BY 0.14" |
| SETLAYER capm_cont_dmy = "capm AND met3" |
| SETLAYER m4_bot_plate = "SIZE (cap2m AND met4) BY 0.14" |
| SETLAYER cap2m_cont_dmy = "cap2m AND met4" |
| |
| ## ry |
| SETLAYER HVSrcDrnProp = "diff NOT (diffres OR poly)" |
| SETLAYER HVSrcDrn = "HVSrcDrnProp INTERACT (HVSrcDrnProp AND diffhvp)" |
| SETLAYER HVnSrcDrn = "HVSrcDrn NOT nwell" |
| SETLAYER HVpolyNotRes = "poly NOT polyres" |
| SETLAYER lcTapnw = "INTERACT licon (licon AND (tap AND nwell))" |
| SETLAYER npccon = "npc AND licon" |
| |
| SETLAYER nwellring = "DONUT nwell" |
| SETLAYER nwellHoles = "HOLES nwell" |
| SETLAYER dnwell_v20 = "AND dnwell v20" |
| |
| SETLAYER rndiff = "(diffi AND nsdm) AND diffres" |
| SETLAYER rpdiff = "(diffi AND psdm) AND diffres" |
| |
| # remove the vias in the capacitors so as not to short the metals in |
| # the caps |
| SETLAYER cap_34 = "(met3 AND met4) AND capm" |
| SETLAYER cap_45 = "(met4 AND met5) AND cap2m" |
| SETLAYER via3_c = "via3 NOT cap_34" |
| SETLAYER via4_c = "via4 NOT cap_45" |
| |
| verbatim { |
| |
| // ******************************************************** |
| // Begin connectivity statements |
| // ******************************************************** |
| |
| CONNECT met5 met4 BY via4_c |
| CONNECT met4 met3 BY via3_c |
| CONNECT met4 m4_bot_plate BY cap2m_cont_dmy |
| CONNECT met3 met2 BY via2 |
| |
| |
| CONNECT met3 m3_bot_plate BY capm_cont_dmy |
| CONNECT met2 met1 BY via1 |
| CONNECT met1 li BY mcon |
| CONNECT li nsd BY licon |
| CONNECT li psd BY licon |
| CONNECT li ntap BY licon |
| CONNECT li ptap BY licon |
| CONNECT li ptubtap BY licon |
| CONNECT li poly BY licon |
| CONNECT gate poly |
| |
| CONNECT ntap nwell |
| CONNECT ptap pwell |
| CONNECT ptubtap ptub |
| CONNECT nwell dnwell |
| |
| CONNECT met5 pad |
| CONNECT rdl pad |
| CONNECT pwde v20 BY ptap |
| |
| // |
| // Off Grid checks |
| // |
| |
| } |
| |
| proc off_grid {lay_list} { |
| set grid_val 0.005 |
| set grid_val2 5 |
| foreach lay $lay_list { |
| |
| set layname ${lay} |
| if {${lay} == "met1i"} { set layname "met1" } |
| if {${lay} == "met2i"} { set layname "met2" } |
| if {${lay} == "met3i"} { set layname "met3" } |
| if {${lay} == "met4i"} { set layname "met4" } |
| if {${lay} == "met5i"} { set layname "met5" } |
| if {${lay} == "diffi"} { set layname "diff" } |
| if {${lay} == "li_i"} { set layname "li" } |
| if {${lay} == "polyi"} { set layname "poly" } |
| |
| RULECHECK ${layname}.GR { |
| @ ${layname}.GR: $layname off ${grid_val} grid vertex |
| OUTPUT "OFFGRID $lay $grid_val2" |
| } |
| } |
| } |
| |
| # changing the order of these calls will affect that rule number and cause |
| # the QA test structure to fail! |
| |
| off_grid [list "nwell" "diffi" "dnwell" "lvtn" "hvtp" "thkox" "v5" "v12" "v20"\ |
| "tunm" "polyi" "npc" "nsdm" "psdm" "licon" "li_i" "mcon" "met1i" "via1"\ |
| "met2i" "via2" "met3i" "via3" "met4i" "via4" "met5i"\ |
| "nsm" "pad" "ldntm" "hvntm" "pnp" "capacitor" "ncm" "inductor"\ |
| "rpm" "hvtr" "NTMdrop" "LVTNMdrop" "HVTPMdrop" "LI1Mdrop" "LICM1drop" "PSDMdrop"\ |
| "NSDMdrop" "FOMdrop" "NTMadd" "LVTNMadd" "HVTPMadd" "LI1Madd" "LICM1add" "PSDMadd"\ |
| "NSDMadd" "FOMadd" "PMM2mk" "CU1Mmk" "RPMmk" "PBOmk" "PDMmk" "NSMmk"\ |
| "MM5mk" "VIM4mk" "MM4mk" "VIM3mk" "MM3mk" "VIM2mk" "CTM1mk" "LI1Mmk"\ |
| "LICM1mk" "PSDMmk" "NSDMmk" "LDNTMmk" "NPCMmk" "HVNTMmk" "NTMmk" "LVOMmk"\ |
| "ONOMmk" "TUNMmk" "HVTRMmk" "HVTPMmk" "LVTNMmk" "NWMmk" "DNMmk" "FOMmk"\ |
| "cfom" "clvtnm" "chvtpm" "conom" "clvom" "cntm" "chvntm" "cnpc" "cnsdm" "cpsdm"\ |
| "cli1m" "cviam3" "cviam4" "pmm" "rdl" "pmm2" "ubm" "bump" "capm" "cap2m"] |
| |
| SETLAYER SEALID_6um_1 = "EXTENT CELL \"advSeal_6um*\" ORIGINAL" |
| SETLAYER SEALID_6um_2 = "EXTENT CELL \"cuPillarAdvSeal_6um*\" ORIGINAL" |
| # jag added 7/9/20 for new sealring pcell: |
| SETLAYER SEALID_6um_3 = "EXTENT CELL \"sealring*\" ORIGINAL" |
| SETLAYER SEALID_6um = "SEALID AND (OR SEALID_6um_1 SEALID_6um_2 SEALID_6um_3)" |
| SETLAYER diffOfA1K = "diffi INTERACT (EXPAND EDGE (LENGTH (DONUT DIFF) > 1000) INSIDE BY 0.005)" |
| SETLAYER diffRingSeal = "(diffi INTERACT (INTERNAL diffOfA1K == 0.3 ABUT < 90 SINGULAR REGION)) INTERACT SEALID" |
| SETLAYER diffNotAdvSeal6um = "diffi NOT (SEALID_6um OR diffRingSeal)" |
| SETLAYER diffNOtSealUHVI = "diffNotAdvSeal6um NOT (OR v5 v12 v20)" |
| |
| SETLAYER polyAnc = "polyi AND anchor" |
| SETLAYER ESDID_sz = "SIZE ESDID BY 0.2" |
| SETLAYER poly_ESD = "polyi AND ESDID_sz" |
| SETLAYER poly_nonESD = "polyi NOT ESDID_sz" |
| SETLAYER gated_npn = "EXTENT CELL \"s8rf_npn_1x1_2p0_HV\" ORIGINAL" |
| #SETLAYER poly_noESD_noAnch = "poly_nonESD NOT (polyAnc OR gated_npn)" |
| SETLAYER poly_noESD_noAnch = "poly_nonESD NOT polyAnc" |
| SETLAYER critArea = "(critside OR ccorner) AND (HOLES SEALID)" |
| |
| SETLAYER p_and_c = "polyi AND critArea" |
| SETLAYER l_and_c = "li_i AND critArea" |
| SETLAYER m1_and_c = "met1i AND critArea" |
| SETLAYER m2_and_c = "met1i AND critArea" |
| SETLAYER m3_and_c = "met3i AND critArea" |
| SETLAYER m4_and_c = "met4i AND critArea" |
| SETLAYER anch1 = "p_and_c AND (l_and_c AND (m1_and_c AND (m2_and_c AND (m3_and_c AND m4_and_c))))" |
| SETLAYER anch2 = "(p_and_c AND (l_and_c AND (m1_and_c AND (m2_and_c AND (m3_and_c AND m4_and_c))))) AND critArea" |
| SETLAYER anchLayers = "anch1 INTERACT anch2" |
| SETLAYER amcon = "mcon AND anchLayers" |
| SETLAYER alicon1 = "licon AND anchLayers" |
| SETLAYER avia = "via1 AND anchLayers" |
| SETLAYER avia2 = "via2 AND anchLayers" |
| SETLAYER avia3 = "via3 AND anchLayers" |
| SETLAYER anchmcon = "amcon OUTSIDE (OR avia3 avia2 avia alicon1)" |
| SETLAYER anchlicon1 = "alicon1 OUTSIDE (OR avia3 avia2 avia amcon)" |
| SETLAYER anchvia = "avia OUTSIDE (OR avia3 avia2 alicon1 amcon)" |
| SETLAYER anchvia2 = "avia2 OUTSIDE (OR avia3 avia alicon1 amcon)" |
| SETLAYER anchvia3 = "avia3 OUTSIDE (OR avia2 avia alicon1 amcon)" |
| SETLAYER acontacts = "OR amcon alicon1 avia avia2 avia3 " |
| SETLAYER anchcontacts = "OR anchmcon anchlicon1 anchvia anchvia2 anchvia3" |
| SETLAYER overlapCon = "acontacts NOT anchcontacts" |
| SETLAYER anchorTmp = "((((anchLayers ENCLOSE mcon) ENCLOSE licon) ENCLOSE via1) ENCLOSE via2) ENCLOSE via3" |
| SETLAYER falseAnch = "CUT poly anchLayers" |
| SETLAYER anchor = "anchorTmp OUTSIDE (overlapCon OR falseAnch)" |
| |
| SETLAYER li1Anc = "li AND anchor" |
| SETLAYER li1_PERI_nonSEAL = "li1_PERI NOT SEALID" |
| SETLAYER li1Peri_noSEAL_noAnch = "li1_PERI_nonSEAL NOT (li1Anc OR falseAnch)" |
| SETLAYER licon_nonSEAL = "licon NOT SEALID" |
| SETLAYER mcon_nonSEAL = "mcon NOT SEALID" |
| SETLAYER via_nonSEAL = "via1 NOT SEALID" |
| SETLAYER via2_nonSEAL = "via2 NOT SEALID" |
| SETLAYER via3_nonSEAL = "via3 NOT SEALID" |
| SETLAYER via4_nonSEAL = "via4 NOT SEALID" |
| SETLAYER tap_SEAL = "tap AND SEALID" |
| SETLAYER tap_ENID = "(tap NOT SEALID) AND ENID" |
| SETLAYER tap_nonSEAL = "tap NOT (SEALID OR ENID)" |
| SETLAYER li_SEAL = "li_i AND SEALID" |
| SETLAYER li_CORE = "li_i AND COREID" |
| SETLAYER licon_SEAL = "licon AND SEALID" |
| SETLAYER mcon_SEAL = "mcon AND SEALID" |
| SETLAYER via1_SEAL = "via1 AND SEALID" |
| SETLAYER via2_SEAL = "via2 AND SEALID" |
| SETLAYER via3_SEAL = "via3 AND SEALID" |
| SETLAYER sealRing = "DONUT SEALID" |
| SETLAYER sealHoles = "HOLES SEALID" |
| SETLAYER FOMdrop_noSeal = "FOMdrop NOT SEALID_6um" |
| |
| verbatim { |
| |
| // |
| // Angle checks |
| // |
| |
| } |
| |
| SETLAYER poly_noESD_noAnch_no_npn = "poly_noESD_noAnch NOT npn" |
| proc non_manhattan {lay_list} { |
| set a 1 |
| foreach lay $lay_list { |
| if {${lay} == "diffNOtSealUHVI"} { |
| set msg_str "diffusion not in areaid:seal or 20v device" |
| set lay_name "diff" |
| } |
| if {${lay} == "poly_noESD_noAnch_no_npn"} { |
| set msg_str "poly not in NPN, ESD or anchor" |
| set lay_name "poly_not_in_ESD" |
| } |
| if {${lay} == "li1Peri_noSEAL_noAnch"} { |
| set msg_str "local interconnect not in areaid:seal or achnor" |
| set lay_name "li" |
| } |
| if {${lay} == "licon_nonSEAL"} { |
| set msg_str "licon interconnect not in areaid:seal" |
| set lay_name "licon" |
| } |
| if {${lay} == "mcon_nonSEAL"} { |
| set msg_str "metal contact not in areaid:seal" |
| set lay_name "mcon" |
| } |
| if {${lay} == "via_nonSEAL"} { |
| set msg_str "via contact not in areaid:seal" |
| set lay_name "via1" |
| } |
| if {${lay} == "via2_nonSEAL"} { |
| set msg_str "via2 contact not in areaid:seal" |
| set lay_name "via2" |
| } |
| if {${lay} == "via3_nonSEAL"} { |
| set msg_str "via3 contact not in areaid:seal" |
| set lay_name "via3" |
| } |
| if {${lay} == "via4_nonSEAL"} { |
| set msg_str "via4 contact not in areaid:seal" |
| set lay_name "via4" |
| } |
| RULECHECK ${lay_name}.ANG.${a} { |
| @ ${lay_name}.ANG.${a}: ${msg_str} non-manhattan edge |
| OUTPUT "ANGLE $lay > 0 < 90" |
| } |
| } |
| } |
| |
| non_manhattan [list "diffNOtSealUHVI" "poly_noESD_noAnch_no_npn" "li1Peri_noSEAL_noAnch"\ |
| "licon_nonSEAL" "mcon_nonSEAL" "via_nonSEAL" "via2_nonSEAL" "via3_nonSEAL" "via4_nonSEAL"] |
| |
| SETLAYER analog_difftap = "diffTap INSIDE ANALOGID" |
| SETLAYER non_ring_difftap = "analog_difftap NOT INTERACT (DONUT analog_difftap)" |
| SETLAYER bad_analog_difftap = "NOT RECTANGLE non_ring_difftap" |
| RULECHECK diff.ANG.2 { |
| @ diff.ANG.2: A diff or tap shape enclosed in areaid:analog must be rectangular |
| OUTPUT "COPY bad_analog_difftap" |
| } |
| |
| proc must_be_rect {lay_list} { |
| set a 2 |
| foreach lay $lay_list { |
| RULECHECK $lay.ANG.${a} { |
| @ $lay.ANG.${a}: $lay must be a rectangle |
| SETLAYER not_donut_lay = "$lay NOT ($lay INTERACT (DONUT $lay))" |
| OUTPUT "NOT RECTANGLE not_donut_lay" |
| } |
| } |
| } |
| |
| must_be_rect [list "licon" "mcon" "via1" "via2" "via3" "via4"] |
| |
| |
| proc non_oct {lay_list} { |
| set a 3 |
| foreach lay $lay_list { |
| |
| set layname ${lay} |
| set rulename ${layname} |
| if {${lay} == "met1i"} { set layname "met1" } |
| if {${lay} == "met2i"} { set layname "met2" } |
| if {${lay} == "met3i"} { set layname "met3" } |
| if {${lay} == "met4i"} { set layname "met4" } |
| if {${lay} == "met5i"} { set layname "met5" } |
| if {${lay} == "diffi"} { set layname "diff" } |
| if {${lay} == "li_i"} { set layname "li" } |
| if {${lay} == "polyi"} { set layname "poly" } |
| if {${lay} == "tap_SEAL"} { set layname "tap in areaid:seal" } |
| if {${lay} == "tap_SEAL"} { set rulename "tap_seal" } |
| if {${lay} == "tap_ENID"} { set layname "tap in areaid:extendedDrain" } |
| if {${lay} == "tap_ENID"} { set rulename "tap_extended_drain" } |
| if {${lay} == "poly_ESD"} { set layname "poly edge inside areaid:esd" } |
| if {${lay} == "poly_ESD"} { set rulename "poly_ESD" } |
| if {${lay} == "li_CORE"} { set layname "li in areaid:core" } |
| if {${lay} == "li_CORE"} { set rulename "li_core" } |
| if {${lay} == "licon_SEAL"} { set layname "licon in areaid:seal" } |
| if {${lay} == "licon_SEAL"} { set rulename "licon_seal" } |
| if {${lay} == "li_SEAL"} { set layname "li in areaid:seal" } |
| if {${lay} == "li_SEAL"} { set rulename "li_seal" } |
| |
| RULECHECK ${rulename}.ANG.${a} { |
| @ ${rulename}.ANG.${a}: $layname non-octagonal edge |
| OUTPUT "ANGLE $lay > 0 < 45" |
| OUTPUT "ANGLE $lay > 45 < 90" |
| } |
| } |
| } |
| |
| non_oct [list "nwell" "diff" "dnwell" "lvtn" "hvtp" "thkox" "tunm" "npc" "nsdm" "psdm" "met1"\ |
| "met2" "v12" "met3" "met4" "met5" "nsm" "pad" "ldntm" "hvntm" "capacitor" "ncm" "inductor"\ |
| "rpm" "urpm" "hvtr" "metop1" "metop2" "metop3" "metop4" "metop5" "metop6" "metop7" "metop8"\ |
| "NTMdrop" "LVTNMdrop" "HVTPMdrop" "LI1Mdrop" "LICM1drop" "PSDMdrop" "NSDMdrop" "P1Mdrop"\ |
| "FOMdrop" "NTMadd" "LVTNMadd" "HVTPMadd" "LI1Madd" "LICM1add" "PSDMadd" "NSDMadd" "P1Madd"\ |
| "FOMadd" "cfom" "clvtnm" "chvtpm" "conom" "clvom" "cntm" "chvntm" "cnpc" "cnsdm" "cpsdm"\ |
| "cli1m" "cviam3" "cviam4" "PMM2mk" "CU1Mmk" "RPMmk" "PBOmk" "PDMmk" "NSMmk" "MM5mk" "VIM4mk"\ |
| "MM4mk" "VIM3mk" "MM3mk" "VIM2mk" "MM2mk" "VIMmk" "MM1mk" "CTM1mk" "LI1Mmk"\ |
| "LICM1mk" "PSDMmk" "NSDMmk" "LDNTMmk" "NPCMmk" "HVNTMmk" "NTMmk" "P1Mmk" "LVOMmk" "ONOMmk"\ |
| "TUNMmk" "HVTRMmk" "HVTPMmk" "LVTNMmk" "NWMmk" "DNMmk" "FOMmk" "tap_SEAL" "tap_ENID"\ |
| "poly_ESD" "li_CORE" "li_SEAL" \ |
| "capm" "cap2m"] |
| |
| verbatim { |
| |
| // |
| // Construction checks |
| // |
| |
| } |
| |
| RULECHECK diff.WARN.1 { |
| @ diff.WARN.1: diffusion without implant |
| OUTPUT "((diffi NOT (nsdm or psdm)) NOT SEALID) NOT npn" |
| } |
| |
| # pins must be inside appropriate layer (CON 1) |
| proc pin_enc {lay_name pin_name} { |
| set a 1 |
| set layname ${lay_name} |
| if {${lay_name} == "met1i"} { set layname "met1" } |
| if {${lay_name} == "met2i"} { set layname "met2" } |
| if {${lay_name} == "met3i"} { set layname "met3" } |
| if {${lay_name} == "met4i"} { set layname "met4" } |
| if {${lay_name} == "met5i"} { set layname "met5" } |
| if {${lay_name} == "diffi"} { set layname "diff" } |
| if {${lay_name} == "li_i"} { set layname "li" } |
| if {${lay_name} == "polyi"} { set layname "poly" } |
| |
| set pinname ${pin_name} |
| if {${pin_name} == "met1Pin"} { set pinname "met1/pin" } |
| if {${pin_name} == "met2Pin"} { set pinname "met2/pin" } |
| if {${pin_name} == "met3Pin"} { set pinname "met3/pin" } |
| if {${pin_name} == "met4Pin"} { set pinname "met4/pin" } |
| if {${pin_name} == "met5Pin"} { set pinname "met5/pin" } |
| if {${pin_name} == "diffPin"} { set pinname "diff/pin" } |
| if {${pin_name} == "liPin"} { set pinname "li/pin" } |
| if {${pin_name} == "polyPin"} { set pinname "poly/pin" } |
| |
| |
| RULECHECK ${pin_name}.CON.${a} { |
| @ ${pin_name}.CON.${a}: $pinname must be enclosed by $layname |
| OUTPUT "NOT $pin_name $lay_name" |
| } |
| } |
| |
| pin_enc "met5i" "met5Pin" |
| pin_enc "met4i" "met4Pin" |
| pin_enc "met3i" "met3Pin" |
| pin_enc "met2i" "met2Pin" |
| pin_enc "met1i" "met1Pin" |
| pin_enc "li_i" "liPin" |
| pin_enc "polyi" "polyPin" |
| pin_enc "diffi" "diffPin" |
| |
| # vias/contacts must be covered top and bottom (CON 2): |
| proc via_ovlp {via_name under_met over_met} { |
| set a 2 |
| |
| set undername ${under_met} |
| set overname ${over_met} |
| if {${under_met} == "met1i"} { set undername "met1" } |
| if {${under_met} == "met2i"} { set undername "met2" } |
| if {${under_met} == "met3i"} { set undername "met3" } |
| if {${under_met} == "met4i"} { set undername "met4" } |
| if {${under_met} == "met5i"} { set undername "met5" } |
| if {${under_met} == "diffi"} { set undername "diff" } |
| if {${under_met} == "li_i"} { set undername "li" } |
| if {${under_met} == "polyi"} { set undername "poly" } |
| if {${over_met} == "met1i"} { set overname "met1" } |
| if {${over_met} == "met2i"} { set overname "met2" } |
| if {${over_met} == "met3i"} { set overname "met3" } |
| if {${over_met} == "met4i"} { set overname "met4" } |
| if {${over_met} == "met5i"} { set overname "met5" } |
| if {${over_met} == "diffi"} { set overname "diff" } |
| if {${over_met} == "li_i"} { set overname "li" } |
| if {${over_met} == "polyi"} { set overname "poly" } |
| |
| RULECHECK ${via_name}.CON.${a} { |
| @ ${via_name}.CON.${a}: ${via_name} must be inside ${overname} and ${undername} |
| OUTPUT "NOT $via_name $under_met" |
| OUTPUT "NOT $via_name $over_met" |
| } |
| } |
| |
| via_ovlp "mcon" "li_i" "met1i" |
| via_ovlp "via1" "met1i" "met2i" |
| via_ovlp "via2" "met2i" "met3i" |
| via_ovlp "via3" "met3i" "met4i" |
| via_ovlp "via4" "met4i" "met5i" |
| |
| RULECHECK licon.CON.2 { |
| @ licon.CON.2: licon must be inside li as well as diff or poly |
| OUTPUT "NOT licon (AND li (OR diffi polyi))" |
| } |
| |
| # layers must be enclosed by COREID (CON 3) |
| proc inside_core {lay_list} { |
| set a 3 |
| foreach lay $lay_list { |
| RULECHECK ${lay}.CON.${a} { |
| @ ${lay}.CON.${a}: $lay must be enclosed by COREID |
| OUTPUT "NOT $lay COREID" |
| } |
| } |
| } |
| |
| inside_core [list "NTMdrop" "LVTNMdrop" "HVTPMdrop" "LI1Mdrop" "LICM1drop" "PSDMdrop" "NSDMdrop"\ |
| "P1Mdrop" "NTMadd" "LVTNMadd" "HVTPMadd" "LI1Madd" "LICM1add" "PSDMadd" "NSDMadd" "P1Madd" "FOMadd"\ |
| "FOMdrop_noSeal"] |
| |
| # layers must not overlap licon (CON 4) |
| proc no_ovlp_licon {lay_list} { |
| set a 4 |
| foreach lay $lay_list { |
| RULECHECK ${lay}.CON.${a} { |
| @ ${lay}.CON.${a}: $lay must not overlap licon |
| OUTPUT "AND $lay licon" |
| } |
| } |
| } |
| |
| no_ovlp_licon [list "diffres" "polyres"] |
| |
| # resistor markers must fit properly inside conductive layers (CON 5) |
| proc res_chk {res_lay conn_lay} { |
| set a 5 |
| set lay_name ${res_lay} |
| if {${res_lay} == "m1res"} { set lay_name "met1res" } |
| if {${res_lay} == "m2res"} { set lay_name "met2res" } |
| if {${res_lay} == "m3res"} { set lay_name "met3res" } |
| if {${res_lay} == "m4res"} { set lay_name "met4res" } |
| if {${res_lay} == "m5res"} { set lay_name "met5res" } |
| RULECHECK ${lay_name}.CON.${a} { |
| set con_name ${conn_lay} |
| if {${conn_lay} == "met1i"} { set con_name "met1" } |
| if {${conn_lay} == "met2i"} { set con_name "met2" } |
| if {${conn_lay} == "met3i"} { set con_name "met3" } |
| if {${conn_lay} == "met4i"} { set con_name "met4" } |
| if {${conn_lay} == "met5i"} { set con_name "met5" } |
| if {${conn_lay} == "diffi"} { set con_name "diff" } |
| if {${conn_lay} == "li_i"} { set con_name "li" } |
| if {${conn_lay} == "polyi"} { set con_name "poly" } |
| |
| @ ${res_lay}.CON.${a}: $res_lay must fit exactly inside $con_name and break it into two nets |
| OUTPUT "NOT $res_lay $conn_lay" |
| SETLAYER conn_lay_not_res_lay = "$conn_lay NOT $res_lay" |
| OUTPUT "$res_lay NOT TOUCH conn_lay_not_res_lay == 2" |
| SETLAYER res_touch_conn = "$res_lay COINCIDENT INSIDE EDGE $conn_lay" |
| SETLAYER res_touch_conn_exp = "EXPAND EDGE res_touch_conn INSIDE BY 0.005" |
| SETLAYER res_touch_conn_exp_size = "SIZE res_touch_conn_exp BY 0.05" |
| SETLAYER good_res = "$res_lay INTERACT res_touch_conn_exp_size == 2" |
| OUTPUT "NOT $res_lay good_res" |
| } |
| } |
| |
| res_chk "pwres" "nw_hole" |
| res_chk "diffres" "diffi" |
| res_chk "polyres" "polyi" |
| res_chk "lires" "li_i" |
| res_chk "m1res" "met1i" |
| res_chk "m2res" "met2i" |
| res_chk "m3res" "met3i" |
| res_chk "m4res" "met4i" |
| res_chk "m5res" "met5i" |
| |
| # layer a cannot overlap layer b (CON 6) |
| proc 2_lay_must_not_ovlp { lay1 lay2 } { |
| set a 6 |
| RULECHECK ${lay1}.CON.${a} { |
| @ ${lay1}.CON.${a}: ${lay1} must not overlap ${lay2} |
| OUTPUT "AND $lay1 $lay2" |
| } |
| } |
| |
| 2_lay_must_not_ovlp "licon" "gate" |
| 2_lay_must_not_ovlp "psdm" "nsdm" |
| #2_lay_must_not_ovlp "nwell" "pwell_dg" |
| #2_lay_must_not_ovlp "v12" "v20" |
| |
| # layer cannot overlap SEALID (CON 7) |
| proc lay_no_ovlp_sealid {lay_list} { |
| set a 7 |
| foreach lay $lay_list { |
| set layname ${lay} |
| set rulename ${layname} |
| if {${lay} == "tap"} { set layname "a tap" } |
| if {${lay} == "tap"} { set rulename "tap" } |
| if {${lay} == "polyi"} { set layname "poly" } |
| if {${lay} == "polyi"} { set layname "poly" } |
| if {${lay} == "polyi"} { set rulename "poly" } |
| if {${lay} == "met1i"} { set layname "met1" } |
| if {${lay} == "met1i"} { set rulename "met1" } |
| if {${lay} == "met2i"} { set layname "met2" } |
| if {${lay} == "met2i"} { set rulename "met2" } |
| if {${lay} == "met3i"} { set layname "met3" } |
| if {${lay} == "met3i"} { set rulename "met3" } |
| if {${lay} == "met4i"} { set layname "met4" } |
| if {${lay} == "met4i"} { set rulename "met4" } |
| if {${lay} == "met5i"} { set layname "met5" } |
| if {${lay} == "met5i"} { set rulename "met5" } |
| if {${lay} == "li_i"} { set layname "li" } |
| if {${lay} == "li_i"} { set rulename "li" } |
| |
| RULECHECK ${rulename}.CON.${a} { |
| @ ${rulename}.CON.${a}: ${layname} must not overlap areaid:seal |
| OUTPUT "AND $lay SEALID" |
| } |
| } |
| } |
| |
| lay_no_ovlp_sealid [list "tap" "polyi" "li_i" "met1i" "met2i" "met3i" "met4i" "met5i"] |
| |
| # layer cannot straddle SEALID (CON 8) |
| RULECHECK diff.CON.8 { |
| @ diff.CON.8: diff must not straddle areaid:seal |
| OUTPUT "CUT diffi SEALID" |
| } |
| |
| # JAG replaced by v5.CON.9, v12.CON.9 and v20.CON.9 |
| # layer a must overlap layer b (CON 9) |
| #proc 2_lay_must_ovlp {lay1 lay2} { |
| # set a 9 |
| # RULECHECK ${lay1}.CON.${a} { |
| # @ ${lay1}.CON.${a}: ${lay1} must overlap ${lay2} when over diff |
| # OUTPUT "($lay1 AND diffi) NOT INTERACT $lay2" |
| # } |
| #} |
| |
| #SETLAYER metals = "OR polyi li met1 met2 met3 met4 met5" |
| #SETLAYER non_met_v5 = "v5 NOT INSIDE metals" |
| ##SETLAYER non_met_v12 = "v12 NOT INSIDE metals" |
| #SETLAYER non_met_v20 = "v20 NOT INSIDE metals" |
| |
| #2_lay_must_ovlp "v5" "thkox" |
| #2_lay_must_ovlp "v12" "thkox" |
| #2_lay_must_ovlp "v20" "thkox" |
| |
| RULECHECK thkox.WARN.1 { |
| @ thkox.WARN.1: Layer thkox doesn't interact with v5, v12 or v20 |
| OUTPUT "thkox NOT INTERACT (OR v5 v12 v20)" |
| } |
| |
| # via/con construction rules (CON 10/11) |
| |
| RULECHECK mcon.CON.10 { |
| @ mcon.CON.10: mcon must be enclosed by li |
| OUTPUT "mcon NOT li" |
| } |
| |
| proc check_via_con {via_list} { |
| foreach via ${via_list} { |
| # SETLAYER cringVIA_${via} = "DONUT ${via}" |
| # SETLAYER cvia_not_ring_${via} = "NOT ${via} cringVIA_${via}" |
| # SETLAYER cvia_not_modulecut_${via} = "NOT cvia_not_ring_${via} moduleCutAREA" |
| # SETLAYER cvia_modulecut_${via} = "AND cvia_not_ring_${via} moduleCutAREA" |
| |
| # rules are obsolete as ringed vias are no longer in the seal ring |
| # changed to check all vias: |
| RULECHECK ${via}.CON.10 { |
| @ ${via}.CON.10: ${via} outside of areaid:moduleCut should be orthogonal rectangle |
| OUTPUT "NOT RECTANGLE ${via} ORTHOGONAL ONLY" |
| } |
| |
| # RULECHECK ${via}.CON.11 { |
| # @ ${via}.CON.11: Ring-shaped ${via} must be enclosed by areaid:sealid |
| # OUTPUT "cringVIA_${via} NOT SEALID" |
| # } |
| } |
| } |
| |
| check_via_con [list "via1" "via2" "via3" "via4"] |
| |
| # mask construction rules (CON 12) |
| |
| proc chk_mask_inside {lay_list} { |
| set a 12 |
| SETLAYER areaid_layers = "OR COREID SEALID moduleCutAREA frameBndr" |
| foreach lay $lay_list { |
| RULECHECK ${lay}.CON.${a} { |
| @ ${lay}.CON.${a}: ${lay} allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only |
| OUTPUT "NOT ${lay} areaid_layers" |
| } |
| } |
| } |
| |
| chk_mask_inside [list "cfom" "clvtnm" "chvtpm" "conom" "clvom" "cntm" "chvntm"\ |
| "cnpc" "cnsdm" "cpsdm" "cli1m" "cviam3" "cviam4" "PMM2mk" "CU1Mmk" "RPMmk" "PBOmk"\ |
| "PDMmk" "NSMmk" "MM5mk" "VIM4mk" "MM4mk" "VIM3mk" "MM3mk" "VIM2mk" "MM2mk" "VIMmk"\ |
| "MM1mk" "CTM1mk" "LI1Mmk" "LICM1mk" "PSDMmk" "NSDMmk" "LDNTMmk" "NPCMmk" "HVNTMmk"\ |
| "NTMmk" "P1Mmk" "LVOMmk" "ONOMmk" "TUNMmk" "HVTRMmk" "HVTPMmk" "LVTNMmk" "NWMmk"\ |
| "DNMmk" "FOMmk"] |
| |
| RULECHECK localsub.CON.1 { |
| @ localsub.CON.1: ptap must not straddle local sub layer |
| OUTPUT "CUT PTAP localSub" |
| } |
| |
| ### new construction check from PM 12/3/2020 - npn and pnp layers cannot |
| ### be placed except inside permitted cells |
| |
| SETLAYER valid_npn = "INSIDE CELL npn \"npn_1x1\" \"npn_1x1_v5\" \"npn_1x2\"" |
| RULECHECK npn.CON.1 { |
| @ npn.CON.1: Layer npn can only be used inside cell npn_1x1, npn_1x1_v5 or npn_1x2 |
| OUTPUT "npn NOT valid_npn" |
| } |
| |
| SETLAYER valid_pnp = "INSIDE CELL pnp \"pnp\" \"pnp_5x\"" |
| RULECHECK pnp.CON.1 { |
| @ pnp.CON.1: Layer pnp can only be used inside cell pnp2 or pnp_5x |
| OUTPUT "pnp NOT valid_pnp" |
| } |
| |
| ## ry |
| |
| verbatim { |
| |
| // |
| // hvtp checks |
| // |
| |
| } |
| |
| set hvtp_min_spc_and_width 0.38 |
| set hvtp_enc_spc 0.18 |
| set hvtp_area 0.265 |
| |
| SETLAYER PFETa = "GATE AND PDIFF" |
| SETLAYER PFET_PERI = "PFETa NOT COREID" |
| |
| RULECHECK hvtp.WID.1 { |
| @ hvtp.WID.1: Min width of hvtp < ${hvtp_min_spc_and_width} |
| OUTPUT "INTERNAL hvtp < ${hvtp_min_spc_and_width} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK hvtp.SP.1 { |
| @ hvtp.SP.1: Min spacing/notch of hvtp < ${hvtp_min_spc_and_width} |
| OUTPUT "EXTERNAL hvtp < ${hvtp_min_spc_and_width} ABUT < 90 SINGULAR REGION" |
| } |
| |
| RULECHECK hvtp.ENC.1 { |
| @ hvtp.ENC.1: Min enclosure of pfet not in areaid:core by hvtp < ${hvtp_enc_spc} |
| OUTPUT "ENCLOSURE (PFET_PERI AND hvtp) hvtp < ${hvtp_enc_spc} MEASURE ALL ABUT < 90 SINGULAR REGION" |
| } |
| |
| RULECHECK hvtp.SP.2 { |
| @ hvtp.SP.2: Min spacing of pfet not in areaid:core to hvtp < ${hvtp_enc_spc} |
| OUTPUT "EXTERNAL PFET_PERI hvtp < ${hvtp_enc_spc} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK hvtp.AR.1 { |
| @ hvtp.AR.1: Min area of hvtp < ${hvtp_area} |
| OUTPUT "AREA hvtp < ${hvtp_area}" |
| } |
| |
| RULECHECK hvtp.AR.2 { |
| @ hvtp.AR.2: Min area of hvtpHole < ${hvtp_area} |
| OUTPUT "AREA (HOLES hvtp) < ${hvtp_area}" |
| } |
| |
| RULECHECK hvtp.ENC.2 { |
| @ hvtp.ENC.2: Min/Max enclosure of nwell by hvtp in areaid:core == 0 |
| OUTPUT "(INTERACT hvtp_CORE (hvtp_CORE AND nwell)) NOT nwell" |
| } |
| |
| verbatim { |
| |
| // |
| // hvtr checks |
| // |
| |
| } |
| |
| set hvtr_width 0.38 |
| set hvtr_to_hvtp_spacing 0.38 |
| set pfet_enc_by_hvtr 0.18 |
| |
| RULECHECK hvtr.WID.1 { |
| @ hvtr.WID.1: Min width of hvtr < ${hvtr_width} |
| OUTPUT "INTERNAL hvtr < ${hvtr_width} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK hvtr.SP.1 { |
| @ hvtr.SP.1: Min. spacing of hvtr to hvtp < ${hvtr_to_hvtp_spacing} |
| OUTPUT "EXTERNAL hvtr hvtp < ${hvtr_to_hvtp_spacing} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK hvtr.CON.1 { |
| @ hvtr.CON.1: hvtr must not overlap hvtp |
| OUTPUT "hvtr AND hvtp" |
| } |
| |
| RULECHECK hvtr.ENC.1 { |
| @ hvtr.ENC.1: Min enclosure of PFET by hvtr < ${pfet_enc_by_hvtr} |
| OUTPUT "ENCLOSURE PFETa hvtr < ${pfet_enc_by_hvtr} MEASURE ALL ABUT < 90 SINGULAR REGION" |
| } |
| |
| verbatim { |
| |
| // |
| // lvtn checks |
| // |
| |
| } |
| |
| set lvtn_min_width_spc 0.38 |
| set lvtn_min_enc 0.18 |
| set lvtn_min_gate_spc 0.18 |
| #set lvtn_min_spc_to_pfet 0.235 |
| set lvtn_min_spc_to_pfet 0.19 |
| set lvtn_exp_edge 0.195 |
| set lvtn_min_area 0.265 |
| |
| SETLAYER lvNwell_drc = "nwell NOT v5" |
| SETLAYER PolyLvNwell = "poly AND lvNwell_drc" |
| SETLAYER lvNtap = "tap AND lvNwell_drc" |
| SETLAYER varChannel_drc = "(PolylvNwell AND lvNtap) NOT COREID" |
| SETLAYER LVnwellnovarChannel = "lvNwell_drc NOT (INTERACT lvNwell_drc (lvNwell_drc AND varChannel_drc))" |
| SETLAYER lvtEncPDiff = "lvtn ENCLOSE PDIFF" |
| SETLAYER periDiffNoLvt = "diff_PERI NOT lvtn_PERI" |
| SETLAYER lvtGate = "lvtn AND GATE" |
| SETLAYER nwellNoVarac = "(nwell NOT (INTERACT nwell (nwell AND varChannel_drc))) NOT INSIDE lvtn" |
| SETLAYER coreNwell = "nwell INSIDE COREID" |
| SETLAYER lvtnHoles = "HOLES lvtn" |
| SETLAYER GATE_PERI_non_v20 = "gate_PERI NOT v20" |
| |
| RULECHECK lvtn.WID.1 { |
| @ lvtn.WID.1: Min width of lvtn < ${lvtn_min_width_spc} |
| OUTPUT "INTERNAL lvtn < ${lvtn_min_width_spc} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK lvtn.SP.1 { |
| @ lvtn.SP.1: Min spacing/notch of lvtn < ${lvtn_min_width_spc} |
| OUTPUT "EXTERNAL lvtn < ${lvtn_min_width_spc} ABUT < 90 SINGULAR REGION" |
| } |
| |
| RULECHECK lvtn.SP.2 { |
| @ lvtn.SP.2: Min spacing of lvtn to gate. Rule exempted inside v20 and outside areaid:core < ${lvtn_min_gate_spc} |
| OUTPUT "EXTERNAL GATE_PERI_non_v20 lvtn_PERI < ${lvtn_min_gate_spc} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK lvtn.SP.3 { |
| @ lvtn.SP.3: Min spacing of lvtn not in areaid:core to pfet along S/D direction < ${lvtn_min_spc_to_pfet} |
| OUTPUT "EXTERNAL (COINCIDENT OUTSIDE EDGE (NOT INTERACT pgate lvtn) psrcdrn) lvtn < ${lvtn_min_spc_to_pfet} ABUT < 90 REGION" |
| } |
| |
| SETLAYER non_20v_gate_peri = "(diffi AND polyi) NOT (COREID OR v20)" |
| RULECHECK lvtn.ENC.1 { |
| @ lvtn.ENC.1: Min enclosure of gate not in areaid:core or v20 by lvtn not in areaid:core < ${lvtn_min_enc} |
| OUTPUT "ENCLOSURE non_20v_gate_peri lvtn_PERI < ${lvtn_min_enc} MEASURE ALL ABUT < 90 SINGULAR REGION" |
| } |
| |
| RULECHECK lvtn.SP.4 { |
| @ lvtn.SP.4: Min spacing of lvtn & hvtp < ${lvtn_min_width_spc} |
| OUTPUT "EXTERNAL lvtn hvtp < ${lvtn_min_width_spc} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK lvtn.OVL.1 { |
| @ lvtn.OVL.1: lvtn must not overlap hvtp |
| OUTPUT "lvtn AND hvtp" |
| } |
| |
| RULECHECK lvtn.ENC.2 { |
| @ lvtn.ENC.2: Min enclosure of lvtn by (nwell not overlapping Var_channel) (exclude coincident edges) < ${lvtn_min_width_spc} |
| OUTPUT "NOT TOUCH (ENCLOSURE lvtn nwellNoVarac < ${lvtn_min_width_spc} REGION) nwellNoVarac" |
| } |
| |
| RULECHECK lvtn.SP.5 { |
| @ lvtn.SP.5: Min spacing of lvtn & nwell in areaid:core < ${lvtn_min_width_spc} |
| OUTPUT "EXTERNAL lvtn coreNwell < ${lvtn_min_width_spc} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK lvtn.AR.1 { |
| @ lvtn.AR.1: Min area of lvtn < ${lvtn_min_area} |
| OUTPUT "AREA lvtn < ${lvtn_min_area}" |
| } |
| |
| RULECHECK lvtn.AR.2 { |
| @ lvtn.AR.2: Min area of lvtn Holes < ${lvtn_min_area} |
| OUTPUT "AREA lvtnHoles < ${lvtn_min_area}" |
| } |
| |
| verbatim { |
| |
| // |
| // diff checks |
| // |
| |
| } |
| |
| set diff_min_width_across_areaid 0.15 |
| set size_diff 0.005 |
| set diff_min_width_inside_coreid 0.14 |
| set min_gate_width_with_no_standardc 0.42 |
| set min_gate_width_with_standardc 0.36 |
| set min_diff_spacing 0.27 |
| set min_tap_width_only_butting_diff 0.29 |
| set min_tap_width_butting_between_diff 0.40 |
| set min_spacing_diff_edge_to_ncoin_edge 0.13 |
| set min_width_tap_in_core 0.38 |
| set min_enc_of_pdiff_sides_in_core 0.18 |
| set min_spacing_of_ndiff_in_core 0.32 |
| set min_enc_of_ndiff_in_core 0.34 |
| set min_spacing_of_diff_to_pwbm_not_in_v20 0.5 |
| |
| SETLAYER tmp1Diff = "INTERNAL diffi < ${diff_min_width_across_areaid} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| SETLAYER tmp2Diff = "INTERNAL (diffi NOT COREID) < ${diff_min_width_across_areaid} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| |
| SETLAYER diffEdge = "diff OUTSIDE EDGE tap" |
| SETLAYER ntapTouchNwell = "ntap INSIDE nwell" |
| SETLAYER nwellTouchNtap = "nwell INSIDE ntap" |
| SETLAYER ntapnwellInNdiff = "(HOLES ndiff) INSIDE (ntapTouchNwell OR nwellTouchNtap)" |
| SETLAYER ESD_nwell_tap = "ESDID AND (ntapTouchNwell AND ntapnwellInNdiff)" |
| SETLAYER nwell_noesd = "nwell NOT ESD_nwell_tap" |
| SETLAYER diff_noesd = "diff NOT ESD_nwell_tap" |
| SETLAYER tap_noesd = "tap NOT ESD_nwell_tap" |
| SETLAYER tabut_edge = "TOUCH EDGE tap_noesd diff_noesd" |
| SETLAYER dabut_edge = "TOUCH EDGE diff_noesd tap_noesd" |
| |
| RULECHECK diff.WID.1 { |
| @ diff.WID.1: Min width of diff crossing areaid:core < ${diff_min_width_across_areaid} |
| OUTPUT "SIZE (tmp2Diff INSIDE (CUT tmp1Diff COREID)) BY ${size_diff} INSIDE OF tmp1Diff STEP ${diff_min_width_across_areaid}" |
| } |
| |
| RULECHECK diff.WID.2 { |
| @ diff.WID.2: Min width of diff inside periphery < ${diff_min_width_across_areaid} |
| OUTPUT "tmp1Diff OUTSIDE COREID" |
| } |
| |
| RULECHECK diff.WID.3 { |
| @ diff.WID.3: Min width of diff inside areaid:core < ${diff_min_width_inside_coreid} |
| OUTPUT "(INTERNAL (AND diffi COREID) < ${diff_min_width_inside_coreid} ABUT < 90 SINGULAR REGION EXCLUDE FALSE) INSIDE COREID" |
| } |
| |
| SETLAYER tmp1DiffTap = "INTERNAL tap < ${diff_min_width_across_areaid} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| |
| RULECHECK diff.WID.4 { |
| @ diff.WID.4: Min width of tap crossing areaid:core < ${diff_min_width_across_areaid} |
| OUTPUT "SIZE ((INTERNAL (tap NOT COREID) < ${diff_min_width_across_areaid} ABUT < 90 SINGULAR REGION EXCLUDE FALSE) INSIDE (CUT tmp1DiffTap COREID)) BY ${size_diff} INSIDE OF tmp1DiffTap STEP ${diff_min_width_across_areaid}" |
| } |
| |
| RULECHECK diff.WID.5 { |
| @ diff.WID.5: Min width of tap inside periphery < ${diff_min_width_across_areaid} |
| OUTPUT "tmp1DiffTap OUTSIDE COREID" |
| } |
| |
| RULECHECK diff.WID.6 { |
| @ diff.WID.6: Min width of tap inside areaid:core < ${diff_min_width_inside_coreid} |
| OUTPUT "(INTERNAL tap < ${diff_min_width_inside_coreid} ABUT < 90 SINGULAR REGION EXCLUDE FALSE) INSIDE COREID" |
| } |
| |
| RULECHECK diff.WID.7 { |
| @ diff.WID.7: Min width of gate outside areaid:standardc < ${min_gate_width_with_no_standardc} |
| OUTPUT "INTERNAL ((GATE_PERI NOT STDCID) COINCIDENT INSIDE EDGE diff) < ${min_gate_width_with_no_standardc} ABUT < 90 REGION OPPOSITE" |
| } |
| |
| RULECHECK diff.WID.8 { |
| @ diff.WID.8: Min width of gate inside areaid:standardc < ${min_gate_width_with_standardc} |
| OUTPUT "INTERNAL ((GATE_PERI AND STDCID) COINCIDENT INSIDE EDGE diff) < ${min_gate_width_with_standardc} ABUT < 90 REGION OPPOSITE" |
| } |
| |
| RULECHECK diff.SP.1 { |
| @ diff.SP.1: Min spacing/notch of diff < ${min_diff_spacing} |
| OUTPUT "EXTERNAL diffi < ${min_diff_spacing} ABUT < 90 SINGULAR REGION" |
| } |
| |
| RULECHECK diff.WID.9 { |
| @ diff.WID.9: Min width of tap butting diff < ${min_tap_width_only_butting_diff} |
| OUTPUT "ENCLOSURE (diff COINCIDENT OUTSIDE EDGE tap) tap < ${min_tap_width_only_butting_diff} ABUT < 90 MEASURE COINCIDENT REGION" |
| } |
| |
| RULECHECK diff.WID.10 { |
| @ diff.WID.10: Min width of tap in periphery butting and between diff < ${min_tap_width_butting_between_diff} |
| OUTPUT "INTERNAL (tap_PERI COINCIDENT OUTSIDE EDGE diff) < ${min_tap_width_butting_between_diff} ABUT < 90 REGION" |
| } |
| |
| RULECHECK diff.WARN.2 { |
| @ diff.WARN.2: diff and tap are not allowed to extend beyond their abutting edge |
| OUTPUT "(EXPAND EDGE ((TOUCH EDGE tap diff) OUTSIDE EDGE diff) OUTSIDE BY ${size_diff}) OR (EXPAND EDGE ((TOUCH EDGE diff tap) OUTSIDE EDGE tap) OUTSIDE BY ${size_diff})" |
| } |
| |
| #SETLAYER expTabutShape = "NOT (EXPAND EDGE tabut_edge OUTSIDE BY 0.005 EXTEND BY 0.13) tap" |
| #SETLAYER expDabutShape = "NOT (EXPAND EDGE dabut_edge OUTSIDE BY 0.005 EXTEND BY 0.13) tap" |
| #SETLAYER nonCoinDiffEdge = "COINCIDENT OUTSIDE EDGE expTabutShape expDabutShape" |
| |
| #RULECHECK diffTap.SP.2 { |
| # @ Min spacing of diff/tap butting edge to non-coincident diff/tap edge < ${min_spacing_diffTap_edge_to_ncoin_edge} |
| # OUTPUT "(EXTERNAL diffEdge tabut_edge < ${min_spacing_diffTap_edge_to_ncoin_edge} ABUT < 90 REGION) OR (EXTERNAL diffEdge dabut_edge < ${min_spacing_diffTap_edge_to_ncoin_edge} ABUT < 90 REGION)" |
| # } |
| |
| #RULECHECK diffTap.SP.2 { |
| # @ Min spacing of diff/tap butting edge to non-coincident diff/tap edge < ${min_spacing_diffTap_edge_to_ncoin_edge} |
| # OUTPUT "EXTERNAL tap nonCoinDiffEdge < ${min_spacing_diffTap_edge_to_ncoin_edge} OPPOSITE PARALLEL ONLY REGION" |
| # } |
| |
| #RULECHECK diffTap.SP.2 { |
| # @ Min spacing of diff/tap butting edge to non-coincident diff/tap edge < ${min_spacing_diffTap_edge_to_ncoin_edge} |
| # OUTPUT "EXTERNAL diffi nonCoinDiffEdge < ${min_spacing_diffTap_edge_to_ncoin_edge} OPPOSITE PARALLEL ONLY REGION" |
| # } |
| |
| #RULECHECK diffTap.SP.2a { |
| # @ Min spacing of diff/tap butting edge to non-coincident diff/tap edge < ${min_spacing_diffTap_edge_to_ncoin_edge} |
| # OUTPUT "EXTERNAL diffi nsdm < ${min_spacing_diffTap_edge_to_ncoin_edge} ABUT < 90 OPPOSITE PARALLEL ONLY REGION" |
| # } |
| |
| #RULECHECK diffTap.SP.2b { |
| # @ Min spacing of diff/tap butting edge to non-coincident diff/tap edge < ${min_spacing_diffTap_edge_to_ncoin_edge} |
| # OUTPUT "EXTERNAL diffi psdm < ${min_spacing_diffTap_edge_to_ncoin_edge} ABUT < 90 OPPOSITE PARALLEL ONLY REGION" |
| # } |
| |
| RULECHECK diff.SP.2 { |
| @ diff.SP.2: Min spacing of diff butting edge to non-coincident diff edge < ${min_spacing_diff_edge_to_ncoin_edge} |
| OUTPUT "(EXTERNAL nsdm (AND diffi psdm) < ${min_spacing_diff_edge_to_ncoin_edge} OPPOSITE PARALLEL ONLY REGION) OR (EXTERNAL psdm (AND diffi nsdm) < ${min_spacing_diff_edge_to_ncoin_edge} OPPOSITE PARALLEL ONLY REGION)" |
| } |
| |
| RULECHECK diff.ENC.1 { |
| @ diff.ENC.1: Min enclosure of pdiff in periphery outside areaid:esd or v20 by nwell < ${min_enc_of_pdiff_sides_in_core} |
| OUTPUT "ENCLOSURE ((PDIFF_PERI NOT ((ESD_nwell_tap OR ENID) OR v20)) AND nwell) nwell < ${min_enc_of_pdiff_sides_in_core} MEASURE ALL ABUT < 90 SINGULAR REGION" |
| } |
| |
| RULECHECK diff.SP.3 { |
| @ diff.SP.3: Min spacing of ndiff outside (areaid:esd or v20) or nwell outside areaid:esd < ${min_enc_of_ndiff_in_core} |
| OUTPUT "EXTERNAL (NDIFF_PERI NOT (ESD_nwell_tap OR ENID)) nwell_noesd < ${min_enc_of_ndiff_in_core} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK diff.ENC.2 { |
| @ diff.ENC.2: Min enclosure of ntap outside areaid:esd or v20 by nwell < ${min_enc_of_pdiff_sides_in_core} |
| OUTPUT "ENCLOSURE ((NTAP_PERI NOT (ESD_nwell_tap OR v20)) AND nwell) nwell < ${min_enc_of_pdiff_sides_in_core} MEASURE ALL ABUT < 90 SINGULAR REGION" |
| } |
| |
| RULECHECK diff.SP.4 { |
| @ diff.SP.4: Min spacing of ptap outside v20 to nwell < ${min_spacing_diff_edge_to_ncoin_edge} |
| OUTPUT "EXTERNAL (PTAP NOT v20) nwell < ${min_spacing_diff_edge_to_ncoin_edge} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK diff.WID.11 { |
| @ diff.WID.11: Min width of gate in areaid:core < ${diff_min_width_inside_coreid} |
| OUTPUT "INTERNAL (emosgate_CORE COINCIDENT INSIDE EDGE diff) < ${diff_min_width_inside_coreid} ABUT < 90 REGION" |
| } |
| |
| RULECHECK diff.WID.12 { |
| @ diff.WID.12: Min width of tap in areaid:core butting & between diff < ${min_width_tap_in_core} |
| OUTPUT "INTERNAL (tap_CORE COINCIDENT OUTSIDE EDGE diff) < ${min_width_tap_in_core} ABUT < 90 REGION" |
| } |
| |
| #Commented out by RY on 15 Jan 2021 - it appears to be a duplicate of rule 'diff.WID.9' |
| #RULECHECK diff.WID.13 { |
| # @ diff.WID.13: Min width of tap butting diff < ${min_tap_width_only_butting_diff} |
| # OUTPUT "ENCLOSURE (diff COINCIDENT OUTSIDE EDGE tap) tap < ${min_tap_width_only_butting_diff} ABUT < 90 MEASURE COINCIDENT REGION" |
| # } |
| |
| RULECHECK diff.ENC.3 { |
| @ diff.ENC.3: Min enclosure of pdiff in areaid:core by nwell < ${diff_min_width_across_areaid} |
| OUTPUT "ENCLOSURE (pdiff_CORE AND nwell) nwell < ${diff_min_width_across_areaid} MEASURE ALL ABUT < 90 SINGULAR REGION" |
| } |
| |
| RULECHECK diff.ENC.4 { |
| @ diff.ENC.4: Min enclosure of ntap in areaid:core by nwell < ${diff_min_width_across_areaid} |
| OUTPUT "ENCLOSURE (NTAP_CORE AND nwell) nwell < ${diff_min_width_across_areaid} MEASURE ALL ABUT < 90 SINGULAR REGION" |
| } |
| |
| RULECHECK diff.ENC.5 { |
| @ diff.ENC.5: Min enclosure of adjacent sides of pdiff in areaid:core by nwell < ${min_enc_of_pdiff_sides_in_core} |
| OUTPUT "NOT RECTANGLE (EXPAND EDGE (ENCLOSURE \[pdiff_CORE\] nwell < ${min_enc_of_pdiff_sides_in_core} ABUT < 90 PARALLEL MEASURE ALL PROJECTING > 0) INSIDE BY ${size_diff}) ORTHOGONAL ONLY" |
| } |
| |
| RULECHECK diff.ENC.6 { |
| @ diff.ENC.6: Min enclosure of adjacent sides of ndiff in areaid:core by pwell < ${min_enc_of_ndiff_in_core} |
| OUTPUT "NOT RECTANGLE (EXPAND EDGE (ENCLOSURE \[ndiff_CORE\] pwell < ${min_enc_of_ndiff_in_core} ABUT < 90 PARALLEL MEASURE ALL PROJECTING > 0) INSIDE BY ${size_diff}) ORTHOGONAL ONLY" |
| } |
| |
| RULECHECK diff.SP.5 { |
| @ diff.SP.5: Min spacing of ndiff in areaid:core & nwell < ${min_spacing_of_ndiff_in_core} |
| OUTPUT "EXTERNAL ndiff_CORE nwell < ${min_spacing_of_ndiff_in_core} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK diff.SP.6 { |
| @ diff.SP.6: Min spacing of pwbm and diff not in v20 < ${min_spacing_of_diff_to_pwbm_not_in_v20} |
| OUTPUT "EXTERNAL pwbm (NOT diff v20) < ${min_spacing_of_diff_to_pwbm_not_in_v20} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| verbatim { |
| |
| // |
| // NSDM and PSDM checks |
| // |
| |
| } |
| |
| SETLAYER ZENERID = "COPY 4002" |
| SETLAYER ENIDgate = "poly AND ENID" |
| SETLAYER ENIDsource = "INTERACT diff ENIDgate" |
| SETLAYER ENIDNsource = "NOT INTERACT NDIFF ENIDgate" |
| SETLAYER pDiffTapNotENIDsource = "pDiffTap NOT (ENIDsource OR ZENERID)" |
| SETLAYER nDiffTapNotENIDsource = "(ndiffTap NOT ENIDsource) NOT SEALID_6um" |
| SETLAYER nDiffTapNotENIDsource_not_gated_npn = "nDiffTapNotENIDsource NOT (gated_npn OR ZENERID)" |
| SETLAYER nsdmFoo = "nsdm NOT ZENERID" |
| SETLAYER psdmFoo = "psdm NOT ZENERID" |
| |
| proc nsdm_psdm_checks {layer_list} { |
| |
| set step_size 0.005 |
| set min_width_not_in_coreid 0.38 |
| set min_width_in_coreid 0.29 |
| set min_spacing 0.38 |
| set min_enclosure 0.125 |
| set min_spacing_opp_diffTap 0.13 |
| set min_area_holes 0.265 |
| set min_spacing_opp_parallel 0.38 |
| set min_spacing_in_core 0.29 |
| set min_width_opp_parallel 0.38 |
| |
| foreach layer $layer_list { |
| |
| if { ${layer} == "nsdm" } { set tapType "n+" |
| set tapLayer "NTAP" |
| set diffLayer "NDIFF" |
| set oppTapLayer "ptap" |
| set oppDiffLayer "pdiff" |
| set scrExtDrnFet "pDiffTapNotENIDsource" |
| set scrExtDrnFetA "nDiffTapNotENIDsource_not_gated_npn" |
| set min_area 0.265 |
| set min_enc_of_tap 0.13 |
| set WID_comment "ndiff/ntap (source of extendedDrain fet and gated_npn exempted) must be enclosed by nsdm covered by ZENERID" |
| set foo "nsdmFoo" |
| } |
| |
| if { ${layer} == "psdm" } { set tapType "p+" |
| set tapLayer "PTAP" |
| set diffLayer "PDIFF" |
| set oppTapLayer "ntap" |
| set oppDiffLayer "ndiff" |
| set scrExtDrnFet "nDiffTapNotENIDsource" |
| set scrExtDrnFetA "pDiffTapNotENIDsource" |
| set min_area 0.255 |
| set min_enc_of_tap 0.12 |
| set WID_comment "pdiff/ptap (source of extendedDrain fet exempted) must be enclosed by psdm not covered by ZENERID" |
| set foo "psdmFoo" |
| } |
| |
| SETLAYER ${layer}_width = "INTERNAL ${layer} < ${min_width_not_in_coreid} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| |
| RULECHECK ${layer}.WID.1 { |
| @ ${layer}.WID.1: Min width of ${layer} across areaid:core < ${min_width_not_in_coreid} |
| if { ${layer} == "nsdm" } { OUTPUT "SIZE ((INTERNAL (${layer} NOT COREID) < ${min_width_not_in_coreid} ABUT < 90 SINGULAR REGION EXCLUDE FALSE) INSIDE (CUT ${layer}_width COREID)) BY ${step_size} INSIDE OF ${layer}_width STEP ${min_width_not_in_coreid}" } |
| if { ${layer} == "psdm" } { OUTPUT "SIZE ((${layer} NOT COREID) INSIDE (CUT ${layer}_width COREID)) BY ${step_size} INSIDE OF ${layer}_width STEP ${min_width_not_in_coreid}" } |
| } |
| |
| RULECHECK ${layer}.WID.2 { |
| @ ${layer}.WID.2: Min width of ${layer} in PERI < ${min_width_not_in_coreid} |
| OUTPUT "${layer}_width OUTSIDE COREID" |
| } |
| |
| RULECHECK ${layer}.WID.3 { |
| @ ${layer}.WID.3: Min width of ${layer} in COREID < ${min_width_in_coreid} |
| OUTPUT "(INTERNAL ${layer} < ${min_width_in_coreid} ABUT < 90 SINGULAR REGION EXCLUDE FALSE) INSIDE COREID" |
| } |
| |
| |
| RULECHECK ${layer}.SP.1 { |
| @ ${layer}.SP.1: Min spacing/notch of "${layer}" in periphery < ${min_spacing} |
| OUTPUT "EXTERNAL ${layer}_PERI < ${min_spacing} ABUT < 90 SINGULAR REGION" |
| } |
| |
| RULECHECK ${layer}.SP.2 { |
| @ ${layer}.SP.2: Min spacing of ${layer} across areaid:core boundary < ${min_spacing} |
| OUTPUT "EXTERNAL ${layer}_CORE ${layer}_PERI > 0 < ${min_spacing} ABUT > 0 < 90 SINGULAR REGION" |
| } |
| |
| # avoid checking the 5v npn's internal octagonal nsdm: |
| if { ${layer} == "nsdm" } { |
| SETLAYER diff2chk = "(nsdm AND diffi) NOT (((diffi AND v5) AND thkox) INSIDE npn)" |
| RULECHECK ${layer}.ENC.1 { |
| @ ${layer}.ENC.1: Min enclosure of ${tapType} diff by ${layer} < ${min_enclosure} |
| #OUTPUT "ENC diff2chk ${layer} < ${min_enclosure} SINGULAR MEASURE ALL ABUT < 90" |
| OUTPUT "(ENC \[diff2chk\] ${layer} < ${min_enclosure} SINGULAR MEASURE ALL ABUT < 90) OUTSIDE EDGE tap" |
| } |
| } else { |
| RULECHECK ${layer}.ENC.1 { |
| @ ${layer}.ENC.1: Min enclosure of ${tapType} diff by ${layer} < ${min_enclosure} |
| OUTPUT "(ENC \[${diffLayer}\] ${layer} < ${min_enclosure} SINGULAR MEASURE ALL ABUT < 90) OUTSIDE EDGE tap" |
| } |
| } |
| |
| RULECHECK ${layer}.ENC.2 { |
| @ ${layer}.ENC.2: Min enclosure of ${tapType} tap in peri by ${layer} < ${min_enclosure} |
| OUTPUT "(ENCLOSURE \[${tapLayer}_PERI\] ${layer} < ${min_enclosure} SINGULAR MEASURE ALL ABUT < 90) OUTSIDE EDGE diff" |
| } |
| |
| RULECHECK ${layer}.SP.3 { |
| @ ${layer}.SP.3: Min spacing of ${layer} & opposite implant diff or tap < ${min_spacing_opp_diffTap} |
| OUTPUT "EXTERNAL ${layer} diffTap < ${min_spacing_opp_diffTap} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK ${layer}.OVL.1 { |
| @ ${layer}.OVL.1: ${layer} must not overlap ${oppDiffLayer}/${oppTapLayer} (source of extendedDrain fet exempted) |
| OUTPUT "${layer} AND ${scrExtDrnFet}" |
| } |
| |
| RULECHECK ${layer}.AR.1 { |
| @ ${layer}.AR.1: Min area of ${layer} < ${min_area} |
| OUTPUT "AREA ${layer} < ${min_area}" |
| } |
| |
| RULECHECK ${layer}.AR.2 { |
| @ ${layer}.AR.2: Min area of ${layer}Hole < ${min_area_holes} |
| OUTPUT "AREA ((HOLES ${layer}) NOT ${layer}) < ${min_area_holes}" |
| } |
| |
| RULECHECK ${layer}.WID.4 { |
| @ ${layer}.WID.4: Min width of ${layer} (opposite parallel) < ${min_width_opp_parallel} |
| OUTPUT "(INTERNAL ${layer} < ${min_width_opp_parallel} OPPOSITE PARALLEL ONLY REGION) INSIDE COREID" |
| } |
| |
| RULECHECK ${layer}.SP.4 { |
| @ ${layer}.SP.4: Min spacing/notch of "${layer}" in areaid:core (opposite parallel) < ${min_spacing_opp_parallel} |
| OUTPUT "EXTERNAL ${layer}_CORE < ${min_spacing_opp_parallel} REGION PARALLEL ONLY OPPOSITE" |
| } |
| |
| RULECHECK ${layer}.SP.5 { |
| @ ${layer}.SP.5: Min spacing/notch of "${layer}" in areaid:core < ${min_spacing_in_core} |
| OUTPUT "EXTERNAL ${layer}_CORE < ${min_spacing_in_core} ABUT < 90 SINGULAR REGION" |
| } |
| |
| RULECHECK ${layer}.ENC.3 { |
| @ ${layer}.ENC.3: Min enclosure of ${tapType} tap in areaid:core by ${layer} < ${min_enc_of_tap} |
| OUTPUT "(ENCLOSURE \[${tapLayer}_CORE\] ${layer} < ${min_enc_of_tap} SINGULAR MEASURE ALL ABUT > 0 < 90) OUTSIDE EDGE diff" |
| } |
| |
| } |
| |
| } |
| |
| nsdm_psdm_checks [list "nsdm" "psdm"] |
| |
| |
| verbatim { |
| |
| // |
| // Poly checks |
| // |
| |
| } |
| |
| set min_hvlt_poly_width 0.5 |
| set min_poly_width 0.15 |
| set min_poly_length 0.35 |
| set min_poly_spacing 0.21 |
| set min_poly_core_length 0.15 |
| set min_poly_gap 0.16 |
| set min_poly_core_gap_spacing 0.175 |
| set min_poly_res_width 0.33 |
| set poly_size_step 0.005 |
| set min_poly_spacing_in_periphery_n_diff 0.075 |
| set min_poly_spacing_in_periphery_n_tap 0.055 |
| set min_diff_ext_butting_tap_beyond_gate 0.3 |
| set min_diff_ext_past_gate_edge 0.25 |
| set min_diff_ext_past_gate_end 0.13 |
| set min_polyres_to_diffTap_spacing 0.48 |
| set min_poly_to_polyres_spacing 0.21 |
| set min_poly_in_core_to_diff_n_tap_spacing 0.03 |
| |
| RULECHECK poly.WID.1 { |
| @ poly.WID.1: Min width of poly over diff inside thkox in periphery < ${min_hvlt_poly_width} |
| OUTPUT "INTERNAL (INTERNAL (poly COINCIDENT EDGE (gate_PERI AND thkox)) < ${min_hvlt_poly_width} OPPOSITE PARALLEL ONLY REGION) < ${min_hvlt_poly_width} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK poly.CON.2 { |
| @ poly.CON.2: gate must not straddle thkox |
| OUTPUT "CUT GATE thkox" |
| } |
| |
| RULECHECK poly.WID.2 { |
| @ poly.WID.2: Min width of poly < ${min_poly_width} |
| OUTPUT "INTERNAL poly < ${min_poly_width} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK poly.LEN.1 { |
| @ poly.LEN.1: Min channel length of pfet overlapping lvtn < ${min_poly_length} |
| # JAG 5/20/21 PM removed these exemptions: |
| #SETLAYER tmp1 = "EXTENT CELL \"s8rf_plowvt_W5p0_L0p50_M4_b\"" |
| #SETLAYER tmp2 = "EXTENT CELL \"s8rf_plowvt_W5p0_L0p35_M4_b\"" |
| #SETLAYER tmp3 = "EXTENT CELL \"s8rf_plowvt_W3p0_L0p35_M2_b\"" |
| #SETLAYER tmp4 = "EXTENT CELL \"s8rf_plowvt_W3p0_L0p50_M2_b\"" |
| #SETLAYER tmp5 = "EXTENT CELL \"s8rf_plowvt_W3p0_L0p35_M4_b\"" |
| #SETLAYER tmp6 = "EXTENT CELL \"s8rf_plowvt_W5p0_L0p50_M2_b\"" |
| #SETLAYER tmp7 = "EXTENT CELL \"s8rf_plowvt_W5p0_L0p35_M2_b\"" |
| #SETLAYER tmp8 = "EXTENT CELL \"s8rf_plowvt_W3p0_L0p50_M4_b\"" |
| #SETLAYER tableH3rfFets = "OR tmp1 tmp2 tmp3 tmp4 tmp5 tmp6 tmp7 tmp8" |
| #OUTPUT "(INTERNAL ((INTERACT PFETa (PFETa AND lvtn)) COINCIDENT OUTSIDE EDGE SRCDRN) < ${min_poly_length} OPPOSITE PARALLEL ONLY REGION) NOT tableH3rfFets" |
| OUTPUT "INTERNAL ((PFETa INTERACT (PFETa AND lvtn)) COINCIDENT OUTSIDE EDGE SRCDRN) < ${min_poly_length} OPPOSITE PARALLEL ONLY REGION" |
| } |
| |
| RULECHECK poly.SP.1 { |
| @ poly.SP.1: Min spacing/notch of "poly" in periphery < ${min_poly_spacing} |
| OUTPUT "EXTERNAL poly_PERI < ${min_poly_spacing} ABUT < 90 SINGULAR REGION" |
| } |
| |
| RULECHECK poly.SP.2 { |
| @ poly.SP.2: Min spacing of poly not covered by cell sr_bltd_eq across areaid:core boundary < ${min_poly_spacing} |
| SETLAYER poly2noXmt = "poly NOT (EXTENT CELL \"sr_bltd_eq\" ORIGINAL)" |
| OUTPUT "EXTERNAL (poly2noXmt AND COREID) (poly2noXmt NOT COREID) > 0 < ${min_poly_spacing} ABUT > 0 < 90 SINGULAR REGION" |
| } |
| |
| SETLAYER polyGapLEedg = "LENGTH poly_CORE <= ${min_poly_core_length}" |
| SETLAYER polyGapGoodSp = "(EXPAND EDGE polyGapLEedg OUTSIDE BY (${min_poly_gap}/2)) INSIDE (EXTERNAL polyGapLEedg <= ${min_poly_gap} OPPOSITE REGION)" |
| |
| RULECHECK poly.SP.3 { |
| @ poly.SP.3: Min spacing of poly (except for poly core gap) < ${min_poly_core_gap_spacing} |
| OUTPUT "(EXTERNAL poly_CORE < ${min_poly_core_gap_spacing} ABUT < 90 REGION SINGULAR) NOT INTERACT polyGapGoodSp" |
| } |
| |
| RULECHECK poly.SP.4 { |
| @ poly.SP.4: Min spacing of poly for poly core gap < ${min_poly_gap} |
| OUTPUT "(EXTERNAL poly_CORE < ${min_poly_gap} ABUT < 90 REGION SINGULAR) INTERACT polyGapGoodSp" |
| } |
| |
| RULECHECK poly.WID.3 { |
| @ poly.WID.3: Min width of poly resistor < ${min_poly_res_width} |
| SETLAYER q0polyAndRes = "poly COINCIDENT OUTSIDE EDGE polyres" |
| SETLAYER q1polyAndRes = "LENGTH q0polyAndRes < ${min_poly_res_width}" |
| SETLAYER q2polyAndRes = "EXPAND EDGE q1polyAndRes OUTSIDE BY 0.005 CORNER FILL" |
| SETLAYER q3polyAndRes = "polyres WITH EDGE (polyres COINCIDENT EDGE q2polyAndRes)" |
| SETLAYER q4polyAndRes = "polyres OUTSIDE EDGE poly" |
| SETLAYER q5polyAndRes = "EXPAND EDGE q4polyAndRes INSIDE BY ${min_poly_gap} CORNER FILL" |
| SETLAYER q6polyAndRes = "polyres NOT q5polyAndRes" |
| SETLAYER q7polyAndRes = "INTERNAL q6polyAndRes < ${poly_size_step} ABUT < 90 REGION" |
| SETLAYER q8polyAndRes = "q6polyAndRes NOT q7polyAndRes" |
| SETLAYER q9polyAndRes = "INTERACT polyres (polyres AND q8polyAndRes) == 1" |
| SETLAYER q10polyAndRes = "polyres NOT q9polyAndRes" |
| OUTPUT "q3polyAndRes OR q10polyAndRes" |
| } |
| |
| RULECHECK poly.SP.5 { |
| @ poly.SP.5: Min spacing of "poly" in periphery & diff < ${min_poly_spacing_in_periphery_n_diff} |
| OUTPUT "EXTERNAL poly_PERI diff < ${min_poly_spacing_in_periphery_n_diff} ABUT == 0 REGION PARALLEL ONLY EXCLUDE FALSE" |
| } |
| |
| RULECHECK poly.SP.6 { |
| @ poly.SP.6: Min spacing of poly in periphery & tap < ${min_poly_spacing_in_periphery_n_tap} |
| OUTPUT "EXTERNAL poly_PERI tap < ${min_poly_spacing_in_periphery_n_tap} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| SETLAYER GATESIDE_PERI = "GATESIDE OUTSIDE EDGE COREID" |
| |
| RULECHECK poly.ENC.1 { |
| @ poly.ENC.1: Min extension of diff edge butting a tap beyond gate edge in periphery < ${min_diff_ext_butting_tap_beyond_gate} |
| OUTPUT "ENCLOSURE GATESIDE_PERI diffTapEdge < ${min_diff_ext_butting_tap_beyond_gate} MEASURE COINCIDENT ABUT < 90 REGION" |
| } |
| |
| RULECHECK poly.ENC.2 { |
| @ poly.ENC.2: Min extension of diff beyond gate edge in periphery < ${min_diff_ext_past_gate_edge} |
| OUTPUT "ENCLOSURE GATESIDE_PERI diff < ${min_diff_ext_past_gate_edge} MEASURE COINCIDENT ABUT < 90 REGION" |
| } |
| |
| RULECHECK poly.ENC.3 { |
| @ poly.ENC.3: Min extension of poly beyond gate end in periphery < ${min_diff_ext_past_gate_end} |
| OUTPUT "ENCLOSURE (GATEEND OUTSIDE EDGE COREID) poly < ${min_diff_ext_past_gate_end} MEASURE COINCIDENT ABUT < 90 REGION" |
| } |
| |
| RULECHECK poly.SP.7 { |
| @ poly.SP.7: Min spacing of high precision or high sheet poly resistor & diff < ${min_polyres_to_diffTap_spacing} |
| OUTPUT "EXTERNAL (polyres INTERACT (rpm OR urpm)) diffTap < ${min_polyres_to_diffTap_spacing} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK poly.OVL.1 { |
| @ poly.OVL.1: poly resistor must not overlap diff or tap |
| OUTPUT "polyres AND diffTap" |
| } |
| |
| RULECHECK poly.SP.8 { |
| @ poly.SP.8: Min spacing of poly resistor & poly < ${min_poly_to_polyres_spacing} |
| OUTPUT "EXTERNAL polyres poly < ${min_poly_to_polyres_spacing} ABUT > 0 < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| SETLAYER q1poly = "NOT RECTANGLE (poly AND diff) ORTHOGONAL ONLY" |
| |
| RULECHECK poly.OVL.2 { |
| @ poly.OVL.2: poly must not overlap any inner corner of diff |
| OUTPUT "(EXTERNAL q1poly <= ${poly_size_step} ABUT REGION) AND poly" |
| } |
| |
| RULECHECK poly.ANG.1 { |
| @ poly.ANG.1: No 90 degree bends of poly on diff |
| SETLAYER q2poly = "INTERNAL q1poly <= ${poly_size_step} ABUT == 90 PERPENDICULAR ONLY REGION" |
| SETLAYER q4poly = "q2poly WITH EDGE (q2poly COINCIDENT INSIDE EDGE diff)" |
| SETLAYER q6poly = "q2poly NOT q4poly" |
| SETLAYER q3poly = "EXTERNAL q1poly <= ${poly_size_step} ABUT == 90 PERPENDICULAR ONLY REGION" |
| SETLAYER q5poly = "TOUCH q3poly diff" |
| SETLAYER q7poly = "q3poly NOT q5poly" |
| SETLAYER q8poly = "q6poly OR q7poly" |
| OUTPUT "COPY q8poly" |
| } |
| |
| RULECHECK poly.OVL.3 { |
| @ poly.OVL.3: poly not in nwell or v20 must not overlap a tap in the periphery |
| SETLAYER exemptNhvnativeCell = "EXTENT CELL \"s8fgvr_fg2n\" ORIGINAL" |
| SETLAYER PolyNotLvNwell = "(poly NOT lvNwell_drc) NOT (exemptNhvnativeCell OR (gated_npn OR v20))" |
| SETLAYER PolyNotLvNwellno_v20 = "PolyNotLvNwell NOT v20" |
| SETLAYER PolyNotLvNwellno_v20_not_npn_5v = "(PolyNotLvNwell NOT v20) NOT (npn AND v5)" |
| OUTPUT "PolyNotLvNwellno_v20_not_npn_5v AND tap_PERI" |
| } |
| |
| RULECHECK poly.OVL.4 { |
| @ poly.OVL.4: poly must not overlap diffres |
| OUTPUT "poly AND diffres" |
| } |
| |
| RULECHECK poly.SP.9 { |
| @ poly.SP.9: Min spacing of poly in areaid:core & diff < ${min_poly_in_core_to_diff_n_tap_spacing} |
| OUTPUT "EXTERNAL poly_CORE diff < ${min_poly_in_core_to_diff_n_tap_spacing} ABUT == 0 REGION PARALLEL ONLY EXCLUDE FALSE" |
| } |
| |
| RULECHECK poly.SP.10 { |
| @ poly.SP.10: Min spacing of poly in areaid:core & tap < ${min_poly_in_core_to_diff_n_tap_spacing} |
| OUTPUT "EXTERNAL poly_CORE tap < ${min_poly_in_core_to_diff_n_tap_spacing} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| verbatim { |
| |
| // |
| // coreID checks |
| // |
| |
| } |
| |
| SETLAYER validCoreID9 = "INSIDE CELL COREID s8cell_ee_bseln s8cell_ee_cellcorn_n s8cell_ee_termcella \ |
| s8cell_ee_bselp s8cell_ee_cellcorn_p s8cell_ee_termcella_int s8cell_ee_cell s8cell_ee_colend_lasta \ |
| s8cell_ee_termcellb s8cell_ee_cell_int s8cell_ee_colend_lastb s8cell_ee_termcellb_int \ |
| s8cell_ee_cell_last s8cell_ee_colenda s8cell_mcell4_last_int s8cell_ee_cell_last_int s8cell_ee_colendb \ |
| s8sram_colenda s8sram_precharge_ce_3x s8sram_colend_cent s8sram_horstrap_opt1_blx_ce s8sram_rowend_hstrap_ce \ |
| s8sram_colend s8sram_cell s8sram_hor_wlstrap_ce s8sram_cornera s8sram_precharge s8sram_precharge_ce \ |
| s8sram_precharge_end_2x s8sram_corner s8sram_precharge_end s8sram_precharge_end_3x s8sram_wlstrap_ce \ |
| s8sram_colenda_cent s8sram_precharge_2x s8sram_rowend_ce s8sram_horstrap_opt1_ce s8sram_precharge_3x \ |
| s8sram_precharge_ce_2x s8sram_precharge_ce_via1 s8sram_precharge_ce_2x_via1 s8sram_precharge_ce_3x_via1 \ |
| s8sram_precharge_end_via1 s8sram_precharge_end_2x_via1 s8sram_precharge_end_3x_via1 \ |
| s8cell_col_precharge s8cell_sp_colend_opt1_ce s8cell_sp_horstrap_opt1_ce \ |
| s8cell_col_precharge_ce s8cell_sp_colend_opt1a_ce s8cell_sp_horstrap_opt3_ce \ |
| s8cell_col_precharge_end s8cell_sp_colend1_ce s8cell_sp_rowend_ce s8cell_sp_cell \ |
| s8cell_sp_corner_ce s8cell_sp_rowend_hstrap_ce s8cell_sp_colend_ce s8cell_sp_hor_wlstrap_ce s8cell_sp_wlstrap_ce \ |
| s8cell_sp_colend_cent_ce s8cell_sp_horstrap_opt1_blx_ce s8cell_tc_tech_CD_top s8cell_tc_tech_CD_lcross \ |
| s8cell_tc_tech_CD_top_pcell s8nvlatch_cell1ux s8nvlatch_lvD s8nvlatch_s8cell_ee_cell s8nvlatch_cell s8nvlatch_lvC \ |
| s8nvlatch_cellg s8nvlatch_cells s8nvlatch_s8cell_ee_cell_back s8cell_nvlfp_cell s8sram16x16_wlstrap_p_ce \ |
| s8sram16x16_colend s8sram16x16_ctl_load_unit s8sram16x16_colend_p_cent s8sram16x16_colenda \ |
| s8sram16x16_wlstrapa2x s8sram16x16_cornerb s8sram16x16_rowend_ce s8sram16x16_wlstrap2x s8sram16x16_cornera \ |
| s8sram16x16_colenda_p_cent s8sram16x16_corner s8sram16x16_ctl_load s8cell_ee_colend_last s8cell_ee_colend s8cell_ee_cell \ |
| s8cell_ee_corner_east s8cell_ee_cell_opt0 s8cell_ee_colend_lastb_opt0 s8cell_ee_cell_last \ |
| s8cell_ee_termcellb_ref s8cell_ee_colendb s8cell_ee_cellcorn_p_ref_opt0 s8cell_ee_termcella_ref \ |
| s8cell_ee_colenda s8cell_ee_colenda_opt0 s8cell_ee_rowend_west s8cell_ee_corner_east_opt0 s8cell_ee_rowend_east_opt0 \ |
| s8cell_ee_cellcorn_n_ref_opt0 s8cell_ee_corner_west_opt0 s8cell_ee_colend_lasta_opt0 s8cell_ee_cell_last_opt0 \ |
| s8cell_ee_cellcorn_p_ref s8cell_ee_rowend_west_opt0 s8cell_ee_termcellb_ref_opt0 s8cell_ee_corner_west \ |
| s8cell_ee_colend_opt0 s8cell_ee_rowend_east s8cell_ee_cellcorn_n_ref s8cell_ee_colend_lastb \ |
| s8cell_ee_termcella_ref_opt0 s8cell_ee_colenda_d s8cell_ee_colend_lasta s8cell_ee_colendb_opt0 \ |
| s8cell_ee_colend_lasta_d s8cell_ee_bseln_enda_d s8cell_ee_bseln_enda_poly_d s8cell_ee_bselp_enda_d \ |
| s8cell_ee_plus_1t_cell s8cell_ee_plus_rowtie_ref s8cell_ee_plus_sselptie_ref s8cell_ee_plus_sselp_ref \ |
| s8cell_ee_plus_sselntie_ref s8cell_ee_plus_sseln_a s8cell_ee_plus_sseln_b s8cell_ee_plus_coltie_ref \ |
| s8cell_ee_plus_corner_tie s8cell_ee_plus_sselp_a s8cell_ee_plus_sselp_b sr_blld sr_mcell_tie up_rom_tie sr_bltd_eq \ |
| sr_tcell up_rom1 sr_mcell sr_tcell_tie up_romref sr_mcell_tie_L sr_mcell_tie_R sr_tcell_tie_L sr_tcell_tie_R \ |
| s8tnvcell_mcell_tie_END_b_cell7 s8tnvcell_mcell_tie_END_t_cell7 s8tnvcell_tcell_END_t_cell7 \ |
| s8tnvcell_tcell_END_b_cell7 s8tnvcell_mcell_tie_END_sub_t_cell7 s8tnvcell_mcell_tie_END_sub_b_cell7 \ |
| s8tnvcell_tcell_tie_Rt_cell7 s8tnvcell_tcell_tie_Rb_cell7 s8tnvcell_mcell_tie_Rt_cell7 s8tnvcell_mcell_tie_Rb_cell7 \ |
| s8tnvcell_mcell_Mt_cell7 s8tnvcell_mcell_Mb_cell7 s8tnvcell_mcell_t_cell7 s8tnvcell_mcell_b_cell7 \ |
| s8tnvcell_tcell_t_cell7 s8tnvcell_tcell_b_cell7 s8tnvcell_mcell_tie_Lt_cell7 s8tnvcell_mcell_tie_Lb_cell7 \ |
| s8tnvcell_tcell_tie_Lb_cell7 s8tnvcell_tcell_tie_Lt_cell7 s8tnvcell_tcell_tie_t_cell7 s8tnvcell_tcell_tie_b_cell7 \ |
| s8tnvcell_mcell_tie_t_cell7 s8tnvcell_mcell_tie_b_cell7 s8tnvssr_bltd_eq s8tnvssr_bltd_tie s8tnvssr_blld_tie \ |
| s8tnvssr_blld s8ovation_atc2_pd_12_6_BiCell" |
| |
| SETLAYER validCoreID1 = "INSIDE CELL COREID ram8_buildspace s8diaet_md3235_a s8diaet_md7301_a s8diaet_md7302_a \ |
| s8diaet_md7303_a s8diaet_md7304_a s8diaet_md7321_a s8diaet_md7322_a s8diaet_md7333_a s8diaet_md7334_a \ |
| s8diaet_s7333_hvpmos_cap_a s8Fab_etch_a s8Fab_etch_b s8Fab_etch_c s8Fab_etch_d s8Fab_etch_e s8Fab_etch_f s8Fab_fab_fomc \ |
| s8Fab_fab_li1mc s8Fab_fab_pimc s8Fab_fabCD_b s8Fab_fabCD_c s8Fab_fabCD_d s8Fab_fabCD_e s8Fab_plot_etch_a \ |
| s8Fab_sem_CDcross s8Fab_tech_CD_drawn_a s8te2et_2t_cell_end01 s8te2et_2t_cell_end01_NoVia s8te2et_2t_cell_end01_sonos_Diff \ |
| s8te2et_2t_cell_end01_sonos_Diff_b s8te2et_2t_cell_end01_sonos_Diff_R s8te2et_2t_cell_end02_opt1_L \ |
| s8te2et_2t_cell_end02_opt1_L_b s8te2et_2t_cell_end02_opt1_R s8te2et_2t_cell_end02_opt1_R01 s8te2et_2t_cell_end02_opt2_L \ |
| s8te2et_2t_cell_end02_opt2_L_b s8te2et_2t_cell_end02_opt2_L_c s8te2et_2t_cell_end02_opt2_R s8te2et_2t_cell_end02_opt2_R01 \ |
| s8te2et_2t_cell_end02_opt3_L s8te2et_2t_cell_end02_opt3_L_b s8te2et_2t_cell_end02_opt3_L_c s8te2et_2t_cell_end02_opt3_R \ |
| s8te2et_2t_cell_end02_opt3_R01 s8te2et_2t_cell_end02_opt4_L s8te2et_2t_cell_end02_opt4_L_c s8te2et_2t_cell_end02_opt4_R \ |
| s8te2et_2t_cell_end02_opt4_R01 s8te2et_2t_cell_end02_sonos_Diff s8te2et_2t_cell_end02_sonos_Diff_b \ |
| s8te2et_2t_cell_end02_sonos_Diff_L s8te2et_2t_cell_end02_sonos_Diff_L_b s8te2et_2t_cell_end02_sonos_Diff_R \ |
| s8te2et_2t_cell_option1_swap s8te2et_2t_cell_option1_swap_b s8te2et_2t_cell_option1_swap_ncBot \ |
| s8te2et_2t_cell_option1_swap_ncBot_b s8te2et_2t_cell_option1_swap_ncTop s8te2et_2t_cell_option1_swap_ncTop_b \ |
| s8te2et_2t_cell_option2_swap s8te2et_2t_cell_option2_swap_b s8te2et_2t_cell_option2_swap_ncBot \ |
| s8te2et_2t_cell_option2_swap_ncBot_b s8te2et_2t_cell_option2_swap_ncTop s8te2et_2t_cell_option2_swap_ncTop_b \ |
| s8te2et_2t_cell_option3_swap s8te2et_2t_cell_option3_swap_b s8te2et_2t_cell_option3_swap_c \ |
| s8te2et_2t_cell_option3_swap_ncTop s8te2et_2t_cell_option3_swap_ncTop_b s8te2et_2t_cell_option3_swap_ncTop_c \ |
| s8te2et_2t_cell_option3_swap1_ncBot s8te2et_2t_cell_option3_swap1_ncBot_b s8te2et_2t_cell_option3_swap1_ncBot_c \ |
| s8te2et_2t_cell_option4_swap s8te2et_2t_cell_option4_swap_c s8te2et_2t_cell_option4_swap_ncBot \ |
| s8te2et_2t_cell_option4_swap_ncBot_c s8te2et_2t_cell_option4_swap_ncTop s8te2et_2t_cell_option4_swap_ncTop_c \ |
| s8te2et_2t_cell_sonos_Diff_swap s8te2et_2t_cell_sonos_Diff_swap_b s8te2et_2t_cell_sonos_Diff_swap_ncTop \ |
| s8te2et_2t_cell_sonos_Diff_swap_ncTop_b s8te2et_2t_cell_sonos_Diff_swap1_ncBot s8te2et_2t_cell_sonos_Diff_swap1_ncBot_b \ |
| s8te2et_2t_cell_sonos_Diff_swapR s8te2et_2t_cell_sonos_Diff_swapR_b s8te2et_2t_cellcrnr_L s8te2et_2t_cellcrnr_R \ |
| s8te2et_md1005_a s8te2et_md1092_a s8te2et_md1701_a" |
| |
| SETLAYER validCoreID2 = "INSIDE CELL COREID s8te2et_md1702_a s8te2et_md1702_b s8te2et_md1703_a s8te2et_md1705_a \ |
| s8te2et_md1773_a s8te2et_md3235_a s8te2et_md3242_b s8te2et_md3244_b s8te2et_md3248_d s8te2et_md3251_b s8te2et_md3277_b \ |
| s8te2et_md3288_b s8te2et_md3288_c s8te2et_md7301_a s8te2et_md7302_a s8te2et_md7303_a s8te2et_md7304_a s8te2et_md8111_a \ |
| s8te2et_md8113_a s8te2et_PassGate_sonos_Fet_novia s8te2et_s_hv_depmos_dieler_opt1 s8te2et_s_hv_depmos_dieler_opt2 \ |
| s8te2et_s_hv_depmos_dieler_opt3 s8te2et_s0755_rowend_1 s8te2et_s0790_cell_1 s8te2et_s0790_cell_2 s8te2et_s0790_colend_1 \ |
| s8te2et_s0791_cell_1 s8te2et_s0791_colend_1 s8te2et_s0791_rowend_1 s8te2et_s1700_hier0_basecell_a \ |
| s8te2et_s1700_hier0_basecell_b s8te2et_s1700_hier0_bot_basecell_a s8te2et_s1700_hier0_corner_a s8te2et_s1700_hier0_elem_a \ |
| s8te2et_s1700_hier0_elem_b s8te2et_s1700_hier0_left_a s8te2et_s1700_hier0_rcorner_a s8te2et_s1700_hier0_right_a \ |
| s8te2et_s1700_hier0_top_basecell_a s8te2et_s1701_hier0_base_cell_a s8te2et_s1701_hier0_bot_con_a \ |
| s8te2et_s1701_hier0_corner_a s8te2et_s1701_hier0_lft_con_a s8te2et_s1701_hier0_rht_con_a s8te2et_s1701_hier0_top_con_a \ |
| s8te2et_s1702_hier0_base_cell_a s8te2et_s1702_hier0_base_cell_b s8te2et_s1702_hier0_bot_a s8te2et_s1702_hier0_corner_l_a \ |
| s8te2et_s1702_hier0_corner_r_a s8te2et_s1702_hier0_left_a s8te2et_s1702_hier0_right_a s8te2et_s1702_hier0_top_a \ |
| s8te2et_s1703_hier0_base_cell_a s8te2et_s1703_hier0_bot_con_a s8te2et_s1703_hier0_corner_a s8te2et_s1703_hier0_lft_con_a \ |
| s8te2et_s1703_hier0_rht_con_a s8te2et_s1703_hier0_top_con_a s8te2et_s1705_hier0_base_cell_a s8te2et_s1709_hier0_base_cell_a \ |
| s8te2et_s1709_hier0_lft_con_a s8te2et_s1709_hier0_rht_con_a s8te2et_s1709_hier0_top_con_a s8te2et_s1726_hier0_base_cell_a \ |
| s8te2et_s1726_hier0_base_cell_b s8te2et_s1726_hier0_lft_con_a s8te2et_s1726_hier0_rht_con_b s8te2et_s1726_hier1_array_b \ |
| s8te2et_s1726_hier1_array_c s8te2et_s1726_hier1_array_d s8te2et_s1726_hier2_array_a s8te2et_s1743_hier0_base_cell_a \ |
| s8te2et_s1743_hier0_sl_a s8te2et_s1743_hier0_sr_a s8te2et_s1743_hier1_array_a s8te2et_s1743_hier1_array_b \ |
| s8te2et_s1744_hstrap_term_a s8te2et_s1744_hstrap_term_n_a s8te2et_s1744_hstrap2_a s8te2et_s1744_npass_a \ |
| s8te2et_s1744_npass_b s8te2et_s1744_npass_cent_a s8te2et_s1744_npass_horiz_term_cent_a \ |
| s8te2et_s1744_npass_vert_a s8te2et_s1744_npd_a s8te2et_s1744_npd_b s8te2et_s1744_npd_cent_a s8te2et_s1744_npd_horiz_a \ |
| s8te2et_s1744_npd_horiz_term_a s8te2et_s1744_npd_horiz_term_cent_a s8te2et_s1744_npd_horiz_term_wl_a \ |
| s8te2et_s1744_npd_vert_a s8te2et_s1744_npd_vert_term_cent_a" |
| |
| SETLAYER validCoreID3 = "INSIDE CELL COREID s8te2et_s1744_ppu_a s8te2et_s1744_ppu_b s8te2et_s1744_ppu_cent_c \ |
| s8te2et_s1744_ppu_corn_a s8te2et_s1744_ppu_cornu_a s8te2et_s1744_ppu_vert_a s8te2et_s1744_ppu_vert_hstrap2_a \ |
| s8te2et_s1744_ppu_vert_term_a s8te2et_s1744_ppu_vert_term_cent_a s8te2et_s1744_topbot_hstrap2_a \ |
| s8te2et_s1756_hier0_base_cell_1_a s8te2et_s1756_hier0_base_cell_1_b s8te2et_s1756_hier0_base_cell_2_a \ |
| s8te2et_s1756_hier0_bot_con_1_a s8te2et_s1756_hier0_bot_con_2_a s8te2et_s1756_hier0_top_con_1_a \ |
| s8te2et_s1756_hier0_top_con_2_a s8te2et_s1756_hier1_array_2_a s8te2et_s1756_npass_bot_term_a \ |
| s8te2et_s1756_npass_top_term_a s8te2et_s1756_npd_4x2_a s8te2et_s1756_npd_4x2_b s8te2et_s1756_npd_a s8te2et_s1756_npd_b \ |
| s8te2et_s1756_npd_bot_term_a s8te2et_s1756_npd_top_term_a s8te2et_s1758_ppu_4x2_a \ |
| s8te2et_s1758_ppu_4x2_c s8te2et_s1758_ppu_a s8te2et_s1758_ppu_bot_term_a s8te2et_s1758_ppu_c s8te2et_s1758_ppu_top_term_a \ |
| s8te2et_s1760_hier1_array_a s8te2et_s1760_hier1_array_b s8te2et_s1761_hier1_array_a s8te2et_s1762_hier0_cell_1 \ |
| s8te2et_s1762_hier0_colend_a s8te2et_s1762_hier0_rowend_2_a s8te2et_s1762_hier1_array_b s8te2et_s1773_hier0_base_cell_a \ |
| s8te2et_s2t_cell_end02 s8te2et_s2t_cell_end02_NoVia s8te2et_s2t_cell_end03 s8te2et_s2t_cell_end03_NoVia s8te2et_s2t_cellcrnr_01_L \ |
| s8te2et_s2t_cellcrnr_01_R s8te2et_s3243_sonos_0p42_0p18 s8te2et_s3243_sonos_0p42_0p18_c s8te2et_s3243_sonos_0p42_0p22 \ |
| s8te2et_s3243_sonos_0p42_0p22_c s8te2et_s3243_sonos_0p42_0p26 s8te2et_s3243_sonos_0p42_0p26_c s8te2et_s3243_sonos_25_0p22 \ |
| s8te2et_s3243_sonos_25_0p22_c s8te2et_s3243_sonos_25_25 s8te2et_s3243_sonos_25_25_c s8te2et_s3248_sonos_2p0_2p0 \ |
| s8te2et_s3248_sonos_2p0_2p0_d s8te2et_s3255_MiniArray_b s8te2et_s3259_2t_cell_end02_opt2_L \ |
| s8te2et_s3259_2t_cellcrnr_L s8te2et_s3262_2t_cell_a s8te2et_s3262_2t_cell_end02_L s8te2et_s3262_2t_cell_end02_R \ |
| s8te2et_s3262_2t_cell_end02_R01 s8te2et_s3262_2t_cell_ncBot s8te2et_s3262_2t_cell_ncTop s8te2et_s3263_2t_cell_a \ |
| s8te2et_s3263_2t_cell_end02_L s8te2et_s3263_2t_cell_end02_R s8te2et_s3263_2t_cell_end02_R01 s8te2et_s3263_2t_cell_ncBot \ |
| s8te2et_s3263_2t_cell_ncTop s8te2et_s3264_2t_2x2_b s8te2et_s3264_2t_2x2_NoVia_b s8te2et_s3264_2t_cell_a s8te2et_s3264_2t_cell_c \ |
| s8te2et_s3264_2t_cell_end02_L s8te2et_s3264_2t_cell_end02_L_b s8te2et_s3264_2t_cell_end02_L_c s8te2et_s3264_2t_cell_end02_R \ |
| s8te2et_s3264_2t_cell_end02_R01 s8te2et_s3264_2t_cell_ncBot s8te2et_s3264_2t_cell_ncBot_c s8te2et_s3264_2t_cell_ncTop \ |
| s8te2et_s3264_2t_cell_ncTop_c s8te2et_s3265_2t_cell_a s8te2et_s3265_2t_cell_b s8te2et_s3265_2t_cell_end01 s8te2et_s3265_2t_cell_end01_NoVia \ |
| s8te2et_s3265_2t_cell_end02_L s8te2et_s3265_2t_cell_end02_L_b s8te2et_s3265_2t_cell_end02_R s8te2et_s3265_2t_cell_end02_R01 s8te2et_s3265_2t_cell_ncBot" |
| |
| SETLAYER validCoreID4 = "INSIDE CELL COREID s8te2et_s3265_2t_cell_ncBot_b s8te2et_s3265_2t_cell_ncTop s8te2et_s3265_2t_cell_ncTop_b \ |
| s8te2et_s3266_2t_cell_a s8te2et_s3266_2t_cell_b s8te2et_s3266_2t_cell_end02_L s8te2et_s3266_2t_cell_end02_L_b s8te2et_s3266_2t_cell_end02_R \ |
| s8te2et_s3266_2t_cell_end02_R01 s8te2et_s3266_2t_cell_ncBot s8te2et_s3266_2t_cell_ncBot_b s8te2et_s3266_2t_cell_ncTop s8te2et_s3266_2t_cell_ncTop_b \ |
| s8te2et_s3267_2t_2x2_a s8te2et_s3267_2t_2x2_b s8te2et_s3267_2t_2x2_c s8te2et_s3267_PassGate_sonos_2x2 s8te2et_s3267_PassGate_sonos_2x2_b \ |
| s8te2et_s3267_PassGate_sonos_2x2_novia s8te2et_s3267_PassGate_sonos_2x2_novia_b s8te2et_s3267_PassGate_sonos_2x2_novia_c s8te2et_s3268_sonos_Fet_novia \ |
| s8te2et_s3268_sonos_Fet_novia_b s8te2et_s3268_sonos_Fet_novia_c s8te2et_s3268_Sonos_soFet_2x2 s8te2et_s3268_Sonos_soFet_2x2_c s8te2et_s3269_2t_2x2_a \ |
| s8te2et_s3269_2t_2x2_b s8te2et_s3269_2t_2x2_c s8te2et_s3269_PassGate_sonos_2x2 s8te2et_s3269_PassGate_sonos_2x2_b s8te2et_s3269_PassGate_sonos_2x2_c \ |
| s8te2et_s3270_2t_2x2_opt3 s8te2et_s3270_2t_2x2_opt3_b s8te2et_s3270_2t_2x2_opt3_c s8te2et_s3270_2x2_NoVia s8te2et_s3270_2x2_NoVia_b \ |
| s8te2et_s3270_2x2_NoVia_c s8te2et_s3270_Sonos_soFet_2x2 s8te2et_s3270_Sonos_soFet_2x2_b s8te2et_s3270_Sonos_soFet_2x2_c s8te2et_s3271_32x32_Array \ |
| s8te2et_s3272_2t_2x2_a s8te2et_s3272_2t_2x2_NoVia s8te2et_s3272_2t_cell_end02_L s8te2et_s3272_2t_cell_end02_R s8te2et_s3272_32x32_Array \ |
| s8te2et_s3273_2t_end02_L s8te2et_s3273_2t_end02_L_b s8te2et_s3273_2t_end02_R s8te2et_s3274_2x2_NoVia s8te2et_s3274_2x2_NoVia_b s8te2et_s3274_32x32_Array \ |
| s8te2et_s3274_32x32_Array_b s8te2et_s3275_2t_cell s8te2et_s3275_2t_cell_a s8te2et_s3275_2t_cell_b s8te2et_s3275_2t_cell_end01 s8te2et_s3275_2t_cell_end01_NoVia \ |
| s8te2et_s3275_2t_cell_ncBot s8te2et_s3275_2t_cell_ncTop s8te2et_s3275_2x2_NoVia s8te2et_s3275_2x2_NoVia_b s8te2et_s3275_32x32_Array \ |
| s8te2et_s3275_32x32_Array_b s8te2et_s3275_cell s8te2et_s3275_cell_end01 s8te2et_s3275_cell_end01_NoVia s8te2et_s3276_W2_L2 \ |
| s8te2et_s3277_W2_L2 s8te2et_s3278_clock_latch s8te2et_s3279_8T_latch s8te2et_s3280_6T_latch s8te2et_s3280_6T_latch_b s8te2et_s3282_2T_Spl_cell2x2 \ |
| s8te2et_s3282_2T_Spl_cell2x2_b s8te2et_s3282_2T_Spl_cell2x2_nc s8te2et_s3282_2T_Spl_cell2x2_nosrc s8te2et_s3282_cellend \ |
| s8te2et_s3282_cellend_cntr s8te2et_s3282_celltop s8te2et_s3282_celltop_nc s8te2et_s3283_3T_Dual_cell2x2_nc s8te2et_s3283_3T_Dual_cell2x2_nc_b \ |
| s8te2et_s3283_3T_Dual_cell2x2_nosrc s8te2et_s3283_3T_Spl_Chanel_cell s8te2et_s3283_cellend s8te2et_s3283_cellend_cntr s8te2et_s3284_1T_SSL_cell2x2 \ |
| s8te2et_s3284_1T_SSL_cell2x2_nc s8te2et_s3284_1T_SSL_cell2x2_nosrc s8te2et_s3284_cellend s8te2et_s3284_cellend_cntr s8te2et_s3284_celltop s8te2et_s3284_celltop_nc" |
| |
| SETLAYER validCoreID5 = "INSIDE CELL COREID s8te2et_s3286_cell2x2 s8te2et_s3286_cell2x2_nc s8te2et_s3286_cell2x2_nosrc \ |
| s8te2et_s3287_2t_cell_end02_opt3_L s8te2et_s3287_2x2 s8te2et_s3287_2x2_Bot s8te2et_s3287_2x2_NoVia \ |
| s8te2et_s3287_2x2_NoViaB s8te2et_s3287_2x2_Top s8te2et_s3287_32x32_Array s8te2et_s3287_32x32_Array_b \ |
| s8te2et_s3287_cell_end01 s8te2et_s3287_cell_end01_NoVia s8te2et_s3289_14T_latch s8te2et_s3t_cell_end \ |
| s8te2et_s3t_cell_end_01 s8te2et_s3t_cell_end_01_NoVia s8te2et_s3t_cell_end_NoVia s8te2et_s3t_cellcrnr_01_L \ |
| s8te2et_s3t_cellcrnr_01_R s8te2et_s3t_cellcrnr_L s8te2et_s3t_cellcrnr_R s8te2et_s4100_2t_cell_end02_opt3_L \ |
| s8te2et_s4100_2t_cell_option3_NP1 s8te2et_s4100_2t_cell_option3_swap_ncTop s8te2et_s4100_2t_cell_option3_swap1_ncBot \ |
| s8te2et_s4100_2t_cellcrnr_01_L s8te2et_s4100_2t_cellend_R s8te2et_s4100_2t_cellend_R01 s8te2et_s4101_2t_cell_option3_IP2 \ |
| s8te2et_s4102_2t_cell_option3_swap_ncTop s8te2et_s4102_2t_cell_option3_swap1_ncBot s8te2et_s4102_2t_cell_STD \ |
| s8te2et_s4102_2t_cellend_L s8te2et_s4102_2t_cellend_R s8te2et_s4102_2t_cellend_R01 s8te2et_s4103_2t_cell_Bot \ |
| s8te2et_s4103_2t_cell_NoLvtn s8te2et_s4103_2t_cell_NP1 s8te2et_s4103_2t_cell_option3_swap_ncTop \ |
| s8te2et_s4103_2t_cell_option3_swap1_ncBot s8te2et_s4103_2t_cell_Top \ |
| s8te2et_s4103_2t_cellend_L s8te2et_s4103_2t_cellend_L_NoLvtn s8te2et_s4103_2t_cellend_R \ |
| s8te2et_s4103_2t_cellend_R01 s8te2et_s4104_2t_cell_Bot s8te2et_s4104_2t_cell_NP2 s8te2et_s4104_2t_cell_Top \ |
| s8te2et_s4104_2t_cellend_L s8te2et_s4105_2t_cell_Bot s8te2et_s4105_2t_cell_NP3 s8te2et_s4105_2t_cell_Top \ |
| s8te2et_s4105_2t_cellend_L s8te2et_s4105_2t_cellend_R s8te2et_s4105_2t_cellend_R01 s8te2et_s4106_2t_cell_Bot \ |
| s8te2et_s4106_2t_cell_NP4 s8te2et_s4106_2t_cell_Top s8te2et_s4106_2t_cellend_L s8te2et_s4106_2t_cellend_R \ |
| s8te2et_s4106_2t_cellend_R01 s8te2et_s4107_2t_cell_Bot s8te2et_s4107_2t_cell_NP5 s8te2et_s4107_2t_cell_Top \ |
| s8te2et_s4107_2t_cellend_L s8te2et_s4107_2t_cellend_R s8te2et_s4107_2t_cellend_R01 s8te2et_s4108_2t_cell_Bot \ |
| s8te2et_s4108_2t_cell_STD s8te2et_s4108_2t_cell_Top s8te2et_s4108_2t_cellend_L \ |
| s8te2et_s4108_2t_cellend_R s8te2et_s4108_2t_cellend_R01 s8te2et_s4109_2t_cell_Bot s8te2et_s4109_2t_cell_NP1 \ |
| s8te2et_s4109_2t_cell_Top s8te2et_s4109_2t_cellend_L s8te2et_s4109_2t_cellend_R s8te2et_s4109_2t_cellend_R01 \ |
| s8te2et_s4110_2t_cell_Bot s8te2et_s4110_2t_cell_NP2 s8te2et_s4110_2t_cell_Top s8te2et_s4110_2t_cellend_L \ |
| s8te2et_s4111_2t_cell_Bot s8te2et_s4111_2t_cell_NP3 s8te2et_s4111_2t_cell_Top s8te2et_s4111_2t_cellend_L \ |
| s8te2et_s4112_2t_cell_Bot s8te2et_s4112_2t_cell_NP4 s8te2et_s4112_2t_cell_Top \ |
| s8te2et_s4112_2t_cellend_L s8te2et_s4112_2t_cellend_R s8te2et_s4112_2t_cellend_R01 s8te2et_s4113_2t_cell_Bot" |
| |
| SETLAYER validCoreID6 = "INSIDE CELL COREID s8te2et_s4113_2t_cell_NP5 s8te2et_s4113_2t_cell_Top s8te2et_s4113_2t_cellend_L s8te2et_s4113_2t_cellend_R s8te2et_s4113_2t_cellend_R01 s8te2et_s4114_2t_cell_Bot s8te2et_s4114_2t_cell_STD s8te2et_s4114_2t_cell_Top s8te2et_s4114_2t_cellend_L s8te2et_s4114_2t_cellend_R s8te2et_s4114_2t_cellend_R01 s8te2et_s4115_2t_cell_Bot s8te2et_s4115_2t_cell_NP1 s8te2et_s4115_2t_cell_Top s8te2et_s4115_2t_cellend_L s8te2et_s4115_2t_cellend_R s8te2et_s4115_2t_cellend_R01 s8te2et_s4116_2t_cell_Bot s8te2et_s4116_2t_cell_NP2 s8te2et_s4116_2t_cell_Top s8te2et_s4116_2t_cellend_L s8te2et_s4117_2t_cell_Bot s8te2et_s4117_2t_cell_NP3 s8te2et_s4117_2t_cell_Top s8te2et_s4117_2t_cellend_L s8te2et_s4118_2t_cell_Bot s8te2et_s4118_2t_cell_NP4 s8te2et_s4118_2t_cell_Top s8te2et_s4118_2t_cellend_L s8te2et_s4118_2t_cellend_R s8te2et_s4118_2t_cellend_R01 s8te2et_s4119_2t_cell_Bot s8te2et_s4119_2t_cell_NP5 s8te2et_s4119_2t_cell_Top s8te2et_s4119_2t_cellend_L s8te2et_s4119_2t_cellend_R s8te2et_s4119_2t_cellend_R01 s8te2et_s4120_2t_cell_Bot s8te2et_s4120_2t_cell_STD s8te2et_s4120_2t_cell_Top s8te2et_s4120_2t_cellend_L s8te2et_s4120_2t_cellend_R s8te2et_s4120_2t_cellend_R01 s8te2et_s4121_2t_cell_Bot s8te2et_s4121_2t_cell_NP1 s8te2et_s4121_2t_cell_Top s8te2et_s4121_2t_cellend_L s8te2et_s4121_2t_cellend_R s8te2et_s4121_2t_cellend_R01 s8te2et_s4122_2t_cell_Bot s8te2et_s4122_2t_cell_NP2 s8te2et_s4122_2t_cell_Top s8te2et_s4122_2t_cellend_L s8te2et_s4123_2t_cell_Bot s8te2et_s4123_2t_cell_NP3 s8te2et_s4123_2t_cell_Top s8te2et_s4123_2t_cellend_L s8te2et_s4124_2t_cell_Bot s8te2et_s4124_2t_cell_NP4 s8te2et_s4124_2t_cell_Top s8te2et_s4124_2t_cellend_L s8te2et_s4124_2t_cellend_R s8te2et_s4124_2t_cellend_R01 s8te2et_s4125_2t_cell_Bot s8te2et_s4125_2t_cell_NP5 s8te2et_s4125_2t_cell_Top s8te2et_s4125_2t_cellend_L s8te2et_s4125_2t_cellend_R s8te2et_s4125_2t_cellend_R01 s8te2et_s4126_2t_cell_Bot s8te2et_s4126_2t_cell_STD s8te2et_s4126_2t_cell_Top s8te2et_s4126_2t_cellend_L s8te2et_s4126_2t_cellend_R s8te2et_s4126_2t_cellend_R01 s8te2et_s4127_2t_cell_Bot s8te2et_s4127_2t_cell_NP1 s8te2et_s4127_2t_cell_Top s8te2et_s4127_2t_cellend_L s8te2et_s4127_2t_cellend_R s8te2et_s4127_2t_cellend_R01 s8te2et_s4128_2t_cell_Bot s8te2et_s4128_2t_cell_NP2 s8te2et_s4128_2t_cell_Top s8te2et_s4128_2t_cellend_L s8te2et_s4128_2t_cellend_R s8te2et_s4128_2t_cellend_R01 s8te2et_s4129_2t_cell_Bot s8te2et_s4129_2t_cell_NP3 s8te2et_s4129_2t_cell_Top s8te2et_s4129_2t_cellend_L s8te2et_s4129_2t_cellend_R s8te2et_s4129_2t_cellend_R01 s8te2et_s4130_2t_cell_Bot s8te2et_s4130_2t_cell_NP4" |
| |
| SETLAYER validCoreID7 = "INSIDE CELL COREID s8te2et_s4130_2t_cell_Top s8te2et_s4130_2t_cellend_L \ |
| s8te2et_s4130_2t_cellend_R s8te2et_s4130_2t_cellend_R01 s8te2et_s4131_2t_cell_Bot s8te2et_s4131_2t_cell_NP5 \ |
| s8te2et_s4131_2t_cell_Top s8te2et_s4131_2t_cellend_L s8te2et_s4131_2t_cellend_R s8te2et_s4131_2t_cellend_R01 \ |
| s8te2et_s4132_2t_cellend_L s8te2et_s4132_3t_cell_Bot s8te2et_s4132_3t_cell_STD s8te2et_s4132_3t_cell_Top \ |
| s8te2et_s4132_3t_cellend_R s8te2et_s4132_3t_cellend_R01 s8te2et_s4133_2t_cellend_L s8te2et_s4133_3t_cell_Bot \ |
| s8te2et_s4133_3t_cell_NP1 s8te2et_s4133_3t_cell_Top s8te2et_s4133_3t_cellend_R s8te2et_s4133_3t_cellend_R01 \ |
| s8te2et_s4135_2t_cellend_L s8te2et_s4135_3t_cell_Bot s8te2et_s4135_3t_cell_NP3 s8te2et_s4135_3t_cell_Top \ |
| s8te2et_s4135_3t_cellend_R s8te2et_s4135_3t_cellend_R01 s8te2et_s4150_2t_cell s8te2et_s4150_2t_cell_Bot \ |
| s8te2et_s4150_2t_cell_Top s8te2et_s4150_2t_cellcrnr_L s8te2et_s4150_2t_cellcrnr_R s8te2et_s4150_2t_cellend_L \ |
| s8te2et_s4150_2t_cellend_R s8te2et_s4150_32x32_Array s8te2et_s4151_2t_2x2_a s8te2et_s4151_2t_cell_end01 \ |
| s8te2et_s4151_2t_cell_end01_no_mcon s8te2et_s4151_2t_cell_end02_L s8te2et_s4151_2t_cell_end02_R \ |
| s8te2et_s4151_2t_cell_end02_R01 s8te2et_s4151_2t_cellcrnr_L s8te2et_s4151_2t_cellcrnr_R \ |
| s8te2et_s4151_PassGate_sonos_2x2 s8te2et_s4151_PassGate_sonos_2x2_no_mcon s8te2et_s4152_2t_2x2_a \ |
| s8te2et_s4152_PassGate_sonos_2x2 s8te2et_s4154_2t_cell_a s8te2et_s4154_2t_cell_end02_L s8te2et_s4154_2t_cell_end02_R \ |
| s8te2et_s4154_2t_cell_end02_R01 s8te2et_s4154_2t_cell_ncBot s8te2et_s4154_2t_cell_ncTop s8te2et_s4155_2t_cell_a \ |
| s8te2et_s4155_2t_cell_end02_L s8te2et_s4155_2t_cell_end02_R s8te2et_s4155_2t_cell_end02_R01 s8te2et_s4155_2t_cell_ncBot \ |
| s8te2et_s4155_2t_cell_ncTop s8te2et_s4156_2t_cell s8te2et_s4156_2t_cell_end s8te2et_s4156_2t_cell_end_no_mcon \ |
| s8te2et_s4156_2t_cell_ncBot s8te2et_s4156_2t_cell_ncTop s8te2et_s7300_DNW_Ring s8te2et_s7300_DNW_Ring_Big \ |
| s8te2et_s7300_DNW_Ring_s s8te2et_s7306_cap_padNFPASS_a s8te2et_sonos_Diff_MiniArray_opt3 \ |
| s8te2et_SONOS_L0p13_Wmin s8te2et_SONOS_L0p15_Wmin s8te2et_SONOS_L0p17_Wmin s8te2et_SONOS_L0p18_Wmin \ |
| s8te2et_sonos_L0p22_W25 s8te2et_SONOS_L0p22_W25 s8te2et_SONOS_L0p22_Wmin s8te2et_SONOS_L0p26_Wmin \ |
| s8te2et_sonos_L25_W25 s8te2et_SONOS_L25_W25 s8te2et_sonos_L25_W25_cntm_ldntm \ |
| s8te2et_SONOS_L25_Wmin s8te2et_sonos_Lmin_W25 s8te2et_SONOS_Lmin_W25 s8te2et_sonos_Lmin_W25_cntm_ldntm \ |
| s8te2et_SONOS_Lmin_Wmin s8te2et_sonos_Lp5_W25 s8te2et_sonos_Lp5_Wp8 s8te2et_Sonos_soFet_2x2 \ |
| s8te2et_sonos_W1_L1 s8te2et_sonos_W1_L1_NoDnw s8te2et_sonos_W1_L25 s8te2et_sonos_W1_L25_NoDnw s8tnvet_md5216_a \ |
| s8tnvet_s9xxx_cyp_cap_padNHLV40" |
| |
| SETLAYER validCoreID8 = "INSIDE CELL COREID s8tnvet_s9xxx_cyp_cap_padNPD40 s8tnvet_s9xxx_cyp_cap_padPPU40 \ |
| s8tnvet_s9xxx_cyp_cap_padS40 s8tnvet_s9xxx_pcm_iso_ppu_14_15 s8tnvet_s9xxx_pcm_iso_ppu_21_15 \ |
| s8tnvet_s9xxx_pcm_iso_ppu_30_15 s8tnvet_s9xxx_pcm_multi_nhlv s8tnvet_s9xxx_pcm_multi_npass s8tnvet_s9xxx_pcm_multi_npd \ |
| s8tnvet_s9xxx_pcm_multi_ppu s8tnvet_s9xxx_sr_mcell s8tnvet_s9xxx_sr_mcell_nTfr_1x s8tnvet_s9xxx_sr_mcell_pLoad_1x \ |
| s8tnvet_s9xxx_sr_mcell_pLoad_1x_2 s8tnvet_s9xxx_sr_mcell_rcl s8tnvet_s9xxx_sr_mcell_rcl_2 \ |
| s8tnvet_s9xxx_sr_mcell_TGvsr_1x_b s8tnvet_s9xxx_sr_mcell_TGvsr_1x_b_2 s8tnvet_s9xxx_sr_mcell_tie \ |
| s8tnvet_s9xxx_sr_mcell_tie_special_L s8tnvet_s9xxx_sr_mcell_tie_special_R s8tnvet_s9xxx_sr_tcell \ |
| s8cell_ee_vcctrk_cell s8cell_ee_vcctrk_cellcorn_p s8cell_ee_vcctrk_termcella s8cell_ee_vcctrk_cellcorn_n \ |
| s8cell_ee_vcctrk_colend s8cell_ee_vcctrk_termcellb s8cell_ee_colenda_d s8cell_ee_colend_lasta_d \"s8sram_tech_CD_top*\" \ |
| s8sram_tech_CD_lcross s8sram_tech_CD_top_pcell \"s8cell_ee_tech_CD_top*\" s8cell_ee_tech_CD_lcross \ |
| s8cell_ee_tech_CD_top_pcell" |
| |
| SETLAYER validCoreID10 = "INSIDE CELL COREID \"s8q_tech_CD_top*\" s8q_tech_CD_lcross s8q_tech_CD_top_pcell" |
| |
| SETLAYER validCoreIDAW = "INSIDE CELL COREID sr_mcell_b_cell7 sr_mcell_tie_Mt_cell7 sr_tcell_tie_b_cell7 \ |
| sr_mcell_t_cell7 sr_mcell_tie_Rb_cell7 sr_tcell_tie_t_cell7 sr_mcell_tie_END_b_cell7 sr_mcell_tie_Rt_cell7 \ |
| sr_tcell_END_b_cell7 sr_mcell_tie_END_t_cell7 sr_tcell_b_cell7 sr_tcell_END_t_cell7 sr_mcell_tie_Lb_cell7 \ |
| sr_tcell_t_cell7 sr_tcell_tie_Rb_cell7 sr_mcell_tie_Lt_cell7 sr_tcell_tie_Lt_cell7 sr_tcell_tie_Rt_cell7 \ |
| sr_mcell_tie_Mb_cell7 sr_tcell_tie_Lb_cell7 sr_blld_tie \"s8sram_s8p_tech_CD_top*\"" |
| |
| SETLAYER validCoreID_TDRrevCA = "INSIDE CELL COREID s8tnvpsr_bltd_eq s8tnvpsr_bltd_tie s8tnvpsr_blld_tie \ |
| s8tnvpsr_blld s8tnvpsr_mcell_tie_END_sub_t_cell7 s8tnvpsr_mcell_tie_Mt_cell7 s8tnvpsr_mcell_tie_Lt_cell7 \ |
| s8tnvpsr_mcell_tie_Rt_cell7 s8tnv64kssr_bltd_eq s8tnv64kssr_bltd_tie s8tnv64kssr_blld_tie s8tnv64kssr_blld" |
| |
| SETLAYER validCoreID_TDRrevCL = "INSIDE CELL COREID s8fmlt64k_cell_cell s8fmlt64k_cell_cell_last \ |
| s8fmlt64k_cell_cellcorn_n s8fmlt64k_cell_cellcorn_p s8fmlt64k_cell_colend_lasta_d s8fmlt64k_cell_colend_lastb \ |
| s8fmlt64k_cell_colenda_d s8fmlt64k_cell_colendb s8fmlt64k_cell_strapn s8fmlt64k_cell_strapp" |
| |
| SETLAYER validCoreID_TDRrevCW = "INSIDE CELL COREID s8rom_rom_wlvnb2 s8rom_romb0 s8rom_romb1" |
| |
| SETLAYER validCoreID_s8fmlt_cell = "INSIDE CELL COREID s8fmlt_cell_cell s8fmlt_cell_cellcorn_p \ |
| s8fmlt_cell_colenda_d s8fmlt_cell_strapp s8fmlt_cell_cell_last s8fmlt_cell_colend_lasta_d \ |
| s8fmlt_cell_colendb s8fmlt_cell_cellcorn_n s8fmlt_cell_colend_lastb s8fmlt_cell_strapn" |
| |
| SETLAYER validCoreID_product_srom = "INSIDE CELL COREID \"*_srom*_rom*\"" |
| |
| SETLAYER validCoreID_s8fs = "INSIDE CELL COREID s8fs_cell_vcctrk_cell s8fs_cell_bseln_endb s8fs_cell_strapn \ |
| s8fs_cell_vcctrk_cellcorn_n s8fs_cell_bselp_enda_d s8fs_cell_strapn_colendb_d s8fs_cell_vcctrk_cellcorn_p \ |
| s8fs_cell_cellcorn_n s8fs_cell_strapp s8fs_cell_vcctrk_colend s8fs_cell_cellcorn_p s8fs_cell_strapp_colenda_d \ |
| s8fs_cell_vcctrk_termcella s8fs_cell_cellcorn_poly s8fs_cell_termcella s8fs_cell_vcctrk_termcellb \ |
| s8fs_cell_colenda_d s8fs_cell_termcellb s8fs_cell_cell s8fs_cell_colendb" |
| |
| SETLAYER validCoreID = "(((validCoreID1 OR validCoreID2) OR (validCoreID3 OR validCoreID4)) OR \ |
| ((validCoreID5 OR validCoreID6) OR (validCoreID7 OR (validCoreID8 OR validCoreID10)))) OR \ |
| (validCoreID9 OR (validCoreIDAW OR (validCoreID_TDRrevCA OR (validCoreID_TDRrevCL OR \ |
| (validCoreID_TDRrevCW OR (validCoreID_s8fmlt_cell OR (validCoreID_product_srom OR validCoreID_s8fs)))))))" |
| |
| SETLAYER inValidCoreID = "COREID NOT validCoreID" |
| |
| RULECHECK coreID.CON.1 { |
| @ coreID.CON.1: Unapproved cells contain areaid:core marker layer |
| COPY inValidCoreID |
| } |
| |
| verbatim { |
| |
| // |
| // denmos checks |
| // |
| |
| } |
| |
| set min_deNFetGate_width 1.055 |
| set min_deNFetSource_width_not_overlapping_poly 0.28 |
| set min_deNFetSource_width_overlapping_poly 0.925 |
| set min_deNFetDrain_width 0.17 |
| set min_max_extension_between_deNFetSource_over_nwell 0.225 |
| set min_max_spacing_between_de_nFET_source_and_de_nFET_drain 1.585 |
| set min_deNFet_channel_gate_length 5.0 |
| set min_enc_of_deNFetDrain_by_nwell 0.66 |
| set min_spacing_of_ptap_to_nwell_over_deNFetDrain 0.86 |
| set min_spacing_of_nwell_over_deNFetDrain 2.4 |
| set min_enc_of_deNFetSource_by_nsdm 0.13 |
| |
| SETLAYER deNFetDevice = "ENCLOSE thkox (INTERACT nwell (NOT ENID dnwell))" |
| SETLAYER deNFetNwell = "INTERACT nwell deNFetDevice" |
| SETLAYER deNFetDiff = "INTERACT diffi deNFetNwell" |
| SETLAYER deNFetGate = "INTERACT (AND poly ENID) deNFetDiff" |
| SETLAYER deNFetSource = "INTERACT deNFetDiff deNFetGate" |
| SETLAYER deNFetSourceOvlPoly = "AND deNFetSource deNFetGate" |
| SETLAYER deNFetSourceNotPoly = "NOT deNFetSource deNFetGate" |
| SETLAYER deNFetDrain = "INSIDE diffi deNFetNwell" |
| SETLAYER deNFetDrainBB = "EXTENTS deNFetDrain" |
| SETLAYER deNFetDrainEdges = "TOUCH EDGE deNFetDrain deNFetDrainBB" |
| SETLAYER deNFetSourceOvlNwell = "AND deNFetSource deNFetNwell" |
| SETLAYER deNFetSourceGood = "INTERNAL deNFetSourceOvlNwell == ${min_max_extension_between_deNFetSource_over_nwell} REGION" |
| SETLAYER deNFetSourceToDrainRegion = "NOT (AND ENID deNFetNwell) (OR deNFetSource deNFetDrainBB)" |
| SETLAYER deNFetSourceToDrainSpacingGood = "INTERNAL deNFetSourceToDrainRegion == ${min_max_spacing_between_de_nFET_source_and_de_nFET_drain} PARALLEL REGION" |
| |
| RULECHECK denmos.WID.1 { |
| @ denmos.WID.1: Min width of de_nFet_gate < ${min_deNFetGate_width} |
| OUTPUT "INTERNAL deNFetGate < ${min_deNFetGate_width} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK denmos.WID.2 { |
| @ denmos.WID.2: Min width of de_nFet_source not overlapping poly < ${min_deNFetSource_width_not_overlapping_poly} |
| OUTPUT "INTERNAL deNFetSourceNotPoly < ${min_deNFetSource_width_not_overlapping_poly} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK denmos.WID.3 { |
| @ denmos.WID.3: Min width of de_nFet_source overlapping poly < ${min_deNFetSource_width_overlapping_poly} |
| OUTPUT "INTERNAL deNFetSourceOvlPoly < ${min_deNFetSource_width_overlapping_poly} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK denmos.WID.4 { |
| @ denmos.WID.4: Min width of the de_nFet_drain < ${min_deNFetDrain_width} |
| OUTPUT "LENGTH deNFetDrainEdges < ${min_deNFetDrain_width}" |
| } |
| |
| RULECHECK denmos.ENC.1 { |
| @ denmos.ENC.1: Min/Max extension between de_nFET_source over nwell = ${min_max_extension_between_deNFetSource_over_nwell} |
| OUTPUT "NOT deNFetSourceOvlNwell deNFetSourceGood" |
| } |
| |
| RULECHECK denmos.SP.1 { |
| @ denmos.SP.1: Min/Max spacing between de_nFET_source and de_nFET_drain = ${min_max_spacing_between_de_nFET_source_and_de_nFET_drain} |
| OUTPUT "NOT deNFetSourceToDrainRegion deNFetSourceToDrainSpacingGood" |
| } |
| |
| RULECHECK denmos.WID.5 { |
| @ denmos.WID.5: Min channel width for de_nFet_gate < ${min_deNFet_channel_gate_length} |
| OUTPUT "LENGTH (deNFetGate INSIDE EDGE deNFetSource) < ${min_deNFet_channel_gate_length}" |
| } |
| |
| RULECHECK denmos.CON.1 { |
| @ denmos.CON.1: 90 degree angles are not permitted for nwell overlapping de_nFET_drain |
| OUTPUT "CONVEX EDGE deNFetNwell ANGLE1 == 90 ANGLE2 > 0" |
| } |
| |
| RULECHECK denmos.ENC.2 { |
| @ denmos.ENC.2: Min enclosure of de_nFet_drain by nwell < ${min_enc_of_deNFetDrain_by_nwell} |
| OUTPUT "ENCLOSURE deNFetDrain deNFetNwell < ${min_enc_of_deNFetDrain_by_nwell} MEASURE ALL ABUT < 90 SINGULAR REGION" |
| } |
| |
| RULECHECK denmos.SP.2 { |
| @ denmos.SP.2: Min spacing between p+ tap and (nwell overlapping de_nFet_drain) < ${min_spacing_of_ptap_to_nwell_over_deNFetDrain} |
| SETLAYER deNFetPtap = "AND (OUTSIDE diffi deNFetNwell) deNFetDevice" |
| OUTPUT "EXTERNAL deNFetPtap deNFetNwell < ${min_spacing_of_ptap_to_nwell_over_deNFetDrain} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK denmos.SP.3 { |
| @ denmos.SP.3: Min spacing between nwells overlapping de_nFET_drain < ${min_spacing_of_nwell_over_deNFetDrain} |
| OUTPUT "EXTERNAL deNFetNwell < ${min_spacing_of_nwell_over_deNFetDrain} ABUT < 90 SINGULAR REGION SPACE EXCLUDE FALSE" |
| } |
| |
| RULECHECK denmos.ENC.3 { |
| @ denmos.ENC.3: Min enclosure of de_nFet_source by nsdm < ${min_enc_of_deNFetSource_by_nsdm} |
| OUTPUT "ENCLOSURE deNFetSource nsdm < ${min_enc_of_deNFetSource_by_nsdm} MEASURE ALL ABUT < 90 SINGULAR REGION" |
| } |
| |
| RULECHECK denmos.CON.2 { |
| @ denmos.CON.2: de_nFet_source must be enclosed by nsdm |
| OUTPUT "NOT deNFetSource nsdm" |
| } |
| |
| verbatim { |
| |
| // |
| // standard denmos 20v checks |
| // |
| |
| } |
| |
| set denmos_20_std_wid_poly 3.0 |
| set denmos_20_std_wid_src 0.29 |
| set denmos_20_std_wid_diff_under_poly 1.5 |
| set denmos_20_std_wid_drn 0.75 |
| set denmos_20_std_extn_dnw_chan 0.5 |
| set denmos_20_std_drn_diff_sp 3.0 |
| set denmos_20_std_chan_wid 0.5 |
| set denmos_20_std_chan_len 30.0 |
| set denmos_20_std_ply_fld_ext 1.0 |
| set denmos_20_std_ptap_sp_src 0.5 |
| set denmos_20_std_well_enc_drn 0.05 |
| set denmos_20_std_dnw_enc_drn 3.5 |
| set denmos_20_std_pwbm_enc_dnw 0.5 |
| |
| SETLAYER ngate_v20a = "(((((gate AND nsdm) AND v20) NOT dnwell) AND thkox) AND lvtn) NOT (OR v5 v12 ESDID LVID pnp npn)" |
| SETLAYER ngate_v20_iso_rec = "((((((gate AND nsdm) AND v20) AND dnwell) AND thkox) NOT lvtn) NOT (OR ngate_v20a v5 v12 ESDID LVID pnp npn)) INTERACT pwbm" |
| SETLAYER ngate_v20_iso_sub = "((HOLES pwbm) INTERACT ngate_v20_iso_rec) AND dnwell" |
| SETLAYER ngate_v20_iso_sub_cont = "(psdm AND diff) AND ngate_v20_iso_sub" |
| SETLAYER ngate_v20_iso_gate = "COPY ngate_v20_iso_rec" |
| SETLAYER ngate_v20 = "OR ngate_v20a ngate_v20_iso_rec" |
| SETLAYER nsd_20v = "(diff AND nsdm) NOT ngate_v20" |
| SETLAYER nsd_20v_src_1 = "EXPAND EDGE ((nsd_20v NOT ngate_v20) COINCIDENT EDGE ENID) OUTSIDE BY 0.05" |
| SETLAYER nsd_20v_src = "(nsd_20v NOT ngate_v20) TOUCH nsd_20v_src_1 == 3" |
| SETLAYER ngate_v20_nat = "((lvtn ENCLOSE nsdm) AND ngate_v20) NOT pwbm" |
| SETLAYER nsd_20v_nat_drn = "((ENID INTERACT ngate_v20_nat) NOT ngate_v20_nat) NOT nsd_20v_src" |
| SETLAYER nsd_20v_drn = "(((ENID INTERACT ngate_v20) NOT ngate_v20) NOT nsd_20v_src) NOT nsd_20v_nat_drn" |
| SETLAYER ngate_v20_zvt = "(((lvtn CUT nsdm) NOT (lvtn ENCLOSE nsdm)) AND ngate_v20) NOT (OR ngate_v20_iso_rec ngate_v20_nat)" |
| SETLAYER ngate_v20_nom = "ngate_v20 NOT (poly INTERACT (OR ngate_v20_nat ngate_v20_zvt ngate_v20_iso_rec))" |
| |
| RULECHECK denmos_20.WID.1 { |
| @ denmos_20.WID.1: Min width of gate poly in standard 20v nmos drain extended device < ${denmos_20_std_wid_poly} |
| OUTPUT "INT (poly INTERACT ngate_v20_nom) < ${denmos_20_std_wid_poly} ABUT<90 REGION" |
| } |
| |
| RULECHECK denmos_20.WID.2 { |
| @ denmos_20.WID.2: Min width of source in standard 20v nmos drain extended device < ${denmos_20_std_wid_src} |
| OUTPUT "INT (nsd_20v_src INTERACT ngate_v20_nom) < ${denmos_20_std_wid_src} ABUT<90 REGION" |
| } |
| |
| RULECHECK denmos_20.WID.3 { |
| @ denmos_20.WID.3: Min width of gate of standard 20v nmos drain extended device < ${denmos_20_std_wid_diff_under_poly} |
| OUTPUT "INT (((diffi AND poly) INTERACT ENID) INTERACT (dnwell INTERACT ngate_v20_nom)) < ${denmos_20_std_wid_diff_under_poly} ABUT<90 REGION" |
| } |
| |
| RULECHECK denmos_20.WID.4 { |
| @ denmos_20.WID.4: Min width of drain of standard 20v nmos drain extended device < ${denmos_20_std_wid_drn} |
| OUTPUT "INT ((nsd_20v_drn AND (dnwell INTERACT ngate_v20_nom)) AND (diffi NOT polyi)) < ${denmos_20_std_wid_drn} ABUT<90 REGION OPPOSITE PARALLEL" |
| } |
| |
| RULECHECK denmos_20.OVL.1 { |
| @ denmos_20.OVL.1: Min extension of deep nwell over channel of standard 20v nmos drain extended device < ${denmos_20_std_extn_dnw_chan} |
| OUTPUT "INT (((dnwell INTERACT ngate_v20_nom) AND diffi) NOT ((nsd_20v_drn AND (dnwell INTERACT ngate_v20_nom)) AND (diffi NOT polyi))) < ${denmos_20_std_extn_dnw_chan} ABUT<90 REGION" |
| } |
| |
| RULECHECK denmos_20.SP.1 { |
| @ denmos_20.SP.1: Min space from drain_diff to gate or src_diff of standard 20v nmos drain extended device < ${denmos_20_std_drn_diff_sp} |
| OUTPUT "EXT ((nsd_20v_drn AND (dnwell INTERACT ngate_v20_nom)) AND (diffi NOT polyi)) (diffi INTERACT ngate_v20_nom) < ${denmos_20_std_drn_diff_sp} ABUT<90 REGION" |
| } |
| |
| RULECHECK denmos_20.LEN.1 { |
| @ denmos_20.LEN.1: Min channel width of standard 20v nmos drain extended device < ${denmos_20_std_chan_len} |
| OUTPUT "EXPAND EDGE (LENGTH (ngate_v20_nom COINCIDENT EDGE nsd_20v_src) < ${denmos_20_std_chan_len}) OUTSIDE BY 0.05" |
| } |
| |
| RULECHECK denmos_20.ANG.1 { |
| @ denmos_20.ANG.1: 90 degree corners are not allowed on the drain_diff of the standard 20v nmos drain extended device |
| OUTPUT "diffi ENCLOSE (INT ((diffi AND (nsd_20v_drn AND (dnwell INTERACT ngate_v20_nom))) NOT INTERACT polyi) < 0.05 ABUT==90 REGION)" |
| } |
| |
| RULECHECK denmos_20.ENC.1 { |
| @ denmos_20.ENC.1: Min enclosure of drain tap by dnwell in the direction of current flow of standard 20v nmos drain extended device < ${denmos_20_std_dnw_enc_drn} |
| OUTPUT "ENC (((diffi AND (nsd_20v_drn AND (dnwell INTERACT ngate_v20_nom))) NOT INTERACT polyi) COINCIDENT EDGE nwell) dnwell < ${denmos_20_std_dnw_enc_drn} ABUT<90 REGION" |
| } |
| |
| RULECHECK denmos_20.ENC.2 { |
| @ denmos_20.ENC.2: Min pwbm enclosure of dnwell of standard 20v nmos drain extended device < ${denmos_20_std_pwbm_enc_dnw} |
| OUTPUT "ENC (dnwell INTERACT ngate_v20_nom) pwbm < ${denmos_20_std_pwbm_enc_dnw} ABUT<90 REGION" |
| } |
| |
| RULECHECK denmos_20.WID.5 { |
| @ denmos_20.WID.5: Min channel length of standard 20v nmos drain extended device < ${denmos_20_std_chan_wid} |
| OUTPUT "INT ngate_v20_nom < ${denmos_20_std_chan_wid} ABUT<90 REGION OPPOSITE PARALLEL" |
| } |
| |
| RULECHECK denmos_20.EXT.1 { |
| @ denmos_20.EXT.1: Min poly field extension past diffusion of standard 20v nmos drain extended device < ${denmos_20_std_ply_fld_ext} |
| OUTPUT "ENC (diffi INTERACT nsd_20v_drn) (polyi INTERACT ngate_v20_nom) < ${denmos_20_std_ply_fld_ext} ABUT<90 REGION" |
| } |
| |
| RULECHECK denmos_20.SP.2 { |
| @ denmos_20.SP.2: Min space from P+ tap to source of standard 20v nmos drain extended device < ${denmos_20_std_ptap_sp_src} |
| OUTPUT "EXT ptap (nsd_20v_src INTERACT (ENID INTERACT ngate_v20_nom)) < ${denmos_20_std_ptap_sp_src} ABUT<90 REGION" |
| } |
| |
| RULECHECK denmos_20.XOR.1 { |
| @ denmos_20.XOR.1: lvtn must be coincident with pwbm of standard 20v nmos drain extended device |
| OUTPUT "XOR ((lvtn INTERACT ENID) INTERACT ngate_v20_nom) ((pwbm INTERACT ENID) INTERACT ngate_v20_nom)" |
| } |
| |
| RULECHECK denmos_20.ENC.3 { |
| @ denmos_20.ENC.3: Min enclosure of drain by nwell of standard 20v nmos drain extended device < ${denmos_20_std_well_enc_drn} |
| SETLAYER dnm_20_drn_not_coin_edge_nw = "LENGTH (NOT COINCIDENT EDGE ((nsd_20v_drn INTERACT (ENID INTERACT ngate_v20_nom)) AND diffi) nwell) > 10" |
| OUTPUT "ENC dnm_20_drn_not_coin_edge_nw nwell < ${denmos_20_std_well_enc_drn} ABUT<90 REGION OPPOSITE PARALLEL" |
| } |
| |
| verbatim { |
| |
| // |
| // native denmos 20v checks |
| // |
| |
| } |
| |
| set denmos_20_nat_wid_poly 3.0 |
| set denmos_20_nat_wid_src 0.29 |
| set denmos_20_nat_wid_diff_under_poly 1.5 |
| set denmos_20_nat_wid_drn 0.75 |
| set denmos_20_nat_extn_dnw_chan 0.5 |
| set denmos_20_nat_drn_diff_sp 3.0 |
| set denmos_20_nat_chan_wid 0.5 |
| set denmos_20_nat_chan_len 30.0 |
| set denmos_20_nat_ply_fld_ext 1.5 |
| set denmos_20_nat_ptap_sp_src 0.5 |
| set denmos_20_nat_well_enc_drn 0.05 |
| set denmos_20_nat_pwbm_enc_dnw 0.5 |
| set denmos_20_nat_dnw_enc_drn 4.0 |
| |
| RULECHECK denmos_20.WID.6 { |
| @ denmos_20.WID.6: Min width of poly gate in native 20v nmos drain extended device < ${denmos_20_nat_wid_poly} |
| OUTPUT "INT (poly INTERACT ngate_v20_nat) < ${denmos_20_nat_wid_poly} ABUT<90 REGION" |
| } |
| |
| RULECHECK denmos_20.WID.7 { |
| @ denmos_20.WID.7: Min width of source in native 20v nmos drain extended device < ${denmos_20_nat_wid_src} |
| OUTPUT "INT (nsd_20v_src INTERACT ngate_v20_nat) < ${denmos_20_nat_wid_src} ABUT<90 REGION" |
| } |
| |
| RULECHECK denmos_20.WID.8 { |
| @ denmos_20.WID.8: Min width of gate of native 20v nmos drain extended device < ${denmos_20_nat_wid_diff_under_poly} |
| OUTPUT "INT (((diffi AND poly) INTERACT ENID) INTERACT (ENID INTERACT ngate_v20_nat)) < ${denmos_20_nat_wid_diff_under_poly} ABUT<90 REGION" |
| } |
| |
| RULECHECK denmos_20.WID.9 { |
| @ denmos_20.WID.9: Min width of drain of native 20v nmos drain extended device < ${denmos_20_nat_wid_drn} |
| OUTPUT "INT ((ENID INTERACT nsd_20v_nat_drn) AND (diffi NOT INTERACT polyi)) < ${denmos_20_nat_wid_drn} ABUT<90 REGION OPPOSITE PARALLEL" |
| } |
| |
| RULECHECK denmos_20.OVL.2 { |
| @ denmos_20.OVL.2: Min extension of deep nwell over channel of native 20v nmos drain extended device < ${denmos_20_nat_extn_dnw_chan} |
| OUTPUT "INT (dnwell AND (diffi INTERACT ngate_v20_nat)) < ${denmos_20_nat_extn_dnw_chan} ABUT<90 REGION" |
| } |
| |
| RULECHECK denmos_20.SP.3 { |
| @ denmos_20.SP.3: Min space from drain_diff to gate or src_diff of native 20v nmos drain extended device < ${denmos_20_nat_drn_diff_sp} |
| OUTPUT "EXT ((ENID INTERACT nsd_20v_nat_drn) AND (diffi NOT INTERACT polyi)) (diffi INTERACT ngate_v20_nat) < ${denmos_20_nat_drn_diff_sp} ABUT<90 REGION" |
| } |
| |
| RULECHECK denmos_20.LEN.2 { |
| @ denmos_20.LEN.2: Min channel width of native 20v nmos drain extended device < ${denmos_20_nat_chan_len} |
| OUTPUT "EXPAND EDGE (LENGTH (ngate_v20_nat COINCIDENT EDGE nsd_20v_src) < ${denmos_20_nat_chan_len}) OUTSIDE BY 0.05" |
| } |
| |
| RULECHECK denmos_20.ANG.2 { |
| @ denmos_20.ANG.2: 90 degree corners are not allowed on the drain_diff of the native 20v nmos drain extended device |
| OUTPUT "diffi ENCLOSE (INT ((diffi AND (nsd_20v_nat_drn AND (ENID INTERACT ngate_v20_nat))) NOT INTERACT polyi) < 0.05 ABUT==90 REGION)" |
| } |
| |
| RULECHECK denmos_20.ENC.4 { |
| @ denmos_20.ENC.4: Min enclosure of drain tap by dnwell in the direction of current flow of native 20v nmos drain extended device < ${denmos_20_std_dnw_enc_drn} |
| OUTPUT "ENC (((diffi AND (nsd_20v_nat_drn AND (ENID INTERACT ngate_v20_nat))) NOT INTERACT polyi) COINCIDENT EDGE nwell) dnwell < ${denmos_20_nat_dnw_enc_drn} ABUT<90 REGION" |
| } |
| |
| RULECHECK denmos_20.ENC.5 { |
| @ denmos_20.ENC.5: Min pwbm enclosure of dnwell of native 20v nmos drain extended device < ${denmos_20_nat_pwbm_enc_dnw} |
| OUTPUT "ENC (dnwell INTERACT (ENID INTERACT ngate_v20_nat)) pwbm < ${denmos_20_nat_pwbm_enc_dnw} ABUT<90 REGION" |
| } |
| |
| RULECHECK denmos_20.WID.10 { |
| @ denmos_20.WID.10: Min channel length of native 20v nmos drain extended device < ${denmos_20_nat_chan_wid} |
| OUTPUT "INT ngate_v20_nat < ${denmos_20_nat_chan_wid} ABUT<90 REGION OPPOSITE PARALLEL" |
| } |
| |
| RULECHECK denmos_20.EXT.2 { |
| @ denmos_20.EXT.2: Min poly field extension past diffusion of native 20v nmos drain extended device < ${denmos_20_nat_ply_fld_ext} |
| OUTPUT "ENC (diffi INTERACT (diffi AND (nsd_20v_nat_drn AND (ENID INTERACT ngate_v20_nat)))) (polyi INTERACT ngate_v20_nat) < ${denmos_20_nat_ply_fld_ext} ABUT<90 REGION" |
| } |
| |
| RULECHECK denmos_20.SP.4 { |
| @ denmos_20.SP.4: Min space from P+ tap to source of native 20v nmos drain extended device < ${denmos_20_nat_ptap_sp_src} |
| OUTPUT "EXT ptap (nsd_20v_src INTERACT (ENID INTERACT ngate_v20_nat)) < ${denmos_20_nat_ptap_sp_src} ABUT<90 REGION" |
| } |
| |
| RULECHECK denmos_20.OVL.3 { |
| @ denmos_20.OVL.3: lvtn must cover entire device of native 20v nmos drain extended device |
| SETLAYER ngate_v20_nat_ovlp3_a = "lvtn INTERACT (EXPAND EDGE (lvtn OUTSIDE EDGE pwbm) OUTSIDE BY 0.05)" |
| SETLAYER all_p = "polyi OR (HOLES polyi)" |
| SETLAYER ngate_v20_nat_ovlp3 = "((all_p OR diffi) INTERACT ngate_v20_nat_ovlp3_a) INTERACT ngate_v20" |
| OUTPUT "ngate_v20_nat_ovlp3 NOT lvtn" |
| } |
| |
| RULECHECK denmos_20.ENC.6 { |
| @ denmos_20.ENC.6: Min enclosure of drain by nwell of native 20v nmos drain extended device < ${denmos_20_nat_well_enc_drn} |
| SETLAYER nat_drn_diff = "(ENID INTERACT nsd_20v_nat_drn) AND (diffi NOT INTERACT polyi)" |
| SETLAYER nat_dnm_20_drn_not_coin_edge_nw = "LENGTH (NOT COINCIDENT EDGE nat_drn_diff nwell) > 10" |
| OUTPUT "ENC nat_dnm_20_drn_not_coin_edge_nw nwell < ${denmos_20_nat_well_enc_drn} ABUT<90 REGION OPPOSITE PARALLEL" |
| } |
| |
| verbatim { |
| |
| // |
| // zvt denmos 20v checks |
| // |
| |
| } |
| |
| set denmos_20_zvt_wid_poly 7.0 |
| set denmos_20_zvt_wid_src 0.29 |
| set denmos_20_zvt_wid_diff_under_poly 6.0 |
| set denmos_20_zvt_wid_drn 0.75 |
| set denmos_20_zvt_extn_dnw_chan 0.5 |
| set denmos_20_zvt_drn_diff_sp 2.0 |
| set denmos_20_zvt_chan_len 30.0 |
| set denmos_20_zvt_dnw_enc_drn 3.0 |
| set denmos_20_zvt_pwbm_enc_dnw 6.0 |
| set denmos_20_zvt_chan_wid 5.5 |
| set denmos_20_zvt_ply_fld_ext 1.0 |
| set denmos_20_zvt_ptap_sp_src 0.5 |
| set denmos_20_zvt_well_enc_drn 0.05 |
| |
| RULECHECK denmos_20.WID.11 { |
| @ denmos_20.WID.11: Min width of poly gate in zvt 20v nmos drain extended device < ${denmos_20_zvt_wid_poly} |
| SETLAYER diff_inter_zvt = diffi INTERACT ngate_v20_zvt |
| SETLAYER dnw_inter_zvt = dnwell INTERACT ngate_v20_zvt |
| SETLAYER ply2chk = (polyi AND (OR diff_inter_zvt dnw_inter_zvt)) AND ENID |
| OUTPUT "INT ply2chk < ${denmos_20_zvt_wid_poly} ABUT<90 REGION" |
| } |
| |
| RULECHECK denmos_20.WID.12 { |
| @ denmos_20.WID.12: Min width of source in zvt 20v nmos drain extended device < ${denmos_20_zvt_wid_src} |
| OUTPUT "INT (nsd_20v_src INTERACT ngate_v20_zvt) < ${denmos_20_zvt_wid_src} ABUT<90 REGION" |
| } |
| |
| RULECHECK denmos_20.WID.13 { |
| @ denmos_20.WID.13: Min width of gate of zvt 20v nmos drain extended device < ${denmos_20_zvt_wid_diff_under_poly} |
| OUTPUT "INT (((diffi AND poly) INTERACT ENID) INTERACT (ENID INTERACT ngate_v20_zvt)) < ${denmos_20_zvt_wid_diff_under_poly} ABUT<90 REGION" |
| } |
| |
| RULECHECK denmos_20.WID.14 { |
| @ denmos_20.WID.14: Min width of drain of zvt 20v nmos drain extended device < ${denmos_20_zvt_wid_drn} |
| OUTPUT "INT ((nsd_20v_drn AND (dnwell INTERACT ngate_v20_zvt)) AND (diffi NOT polyi)) < ${denmos_20_zvt_wid_drn} ABUT<90 REGION OPPOSITE PARALLEL" |
| } |
| |
| RULECHECK denmos_20.OVL.4 { |
| @ denmos_20.OVL.4: Min extension of deep nwell over channel of zvt 20v nmos drain extended device < ${denmos_20_zvt_extn_dnw_chan} |
| OUTPUT "INT (((dnwell INTERACT ngate_v20_zvt) AND diffi) NOT ((nsd_20v_drn AND (dnwell INTERACT ngate_v20_zvt)) AND (diffi NOT polyi))) < ${denmos_20_zvt_extn_dnw_chan} ABUT<90 REGION" |
| } |
| |
| RULECHECK denmos_20.SP.5 { |
| @ denmos_20.SP.5: Min space from drain diffusion to gate/src diffusion of zvt 20v nmos drain extended device < ${denmos_20_zvt_drn_diff_sp} |
| OUTPUT "EXT ((nsd_20v_drn AND (dnwell INTERACT ngate_v20_zvt)) AND (diffi NOT polyi)) (diffi INTERACT ngate_v20_zvt) < ${denmos_20_zvt_drn_diff_sp} ABUT<90 REGION" |
| } |
| |
| RULECHECK denmos_20.LEN.3 { |
| @ denmos_20.LEN.3: Min channel width of zvt 20v nmos drain extended device < ${denmos_20_zvt_chan_len} |
| OUTPUT "EXPAND EDGE (LENGTH (ngate_v20_zvt COINCIDENT EDGE nsd_20v_src) < ${denmos_20_zvt_chan_len}) OUTSIDE BY 0.05" |
| } |
| |
| RULECHECK denmos_20.ANG.3 { |
| @ denmos_20.ANG.3: 90 degree corners are not allowed on the drain_diff of the zvt 20v nmos drain extended device |
| OUTPUT "diffi ENCLOSE (INT ((diffi AND (nsd_20v_drn AND (dnwell INTERACT ngate_v20_zvt))) NOT INTERACT polyi) < 0.05 ABUT==90 REGION)" |
| } |
| |
| RULECHECK denmos_20.ENC.7 { |
| @ denmos_20.ENC.7: Min enclosure of drain tap by dnwell in the direction of current flow of zvt 20v nmos drain extended device < ${denmos_20_zvt_dnw_enc_drn} |
| OUTPUT "ENC (((diffi AND (nsd_20v_drn AND (dnwell INTERACT ngate_v20_zvt))) NOT INTERACT polyi) COINCIDENT EDGE nwell) dnwell < ${denmos_20_zvt_dnw_enc_drn} ABUT<90 REGION" |
| } |
| |
| RULECHECK denmos_20.WID.15 { |
| @ denmos_20.WID.15: Min channel length of zvt 20v nmos drain extended device < ${denmos_20_zvt_chan_wid} |
| OUTPUT "INT ngate_v20_zvt < ${denmos_20_zvt_chan_wid} ABUT<90 REGION OPPOSITE PARALLEL" |
| } |
| |
| RULECHECK denmos_20.EXT.3 { |
| @ denmos_20.EXT.3: Min poly field extension past diffusion of zvt 20v nmos drain extended device < ${denmos_20_zvt_ply_fld_ext} |
| OUTPUT "ENC (diffi INTERACT nsd_20v_drn) (polyi INTERACT ngate_v20_zvt) < ${denmos_20_zvt_ply_fld_ext} ABUT<90 REGION" |
| } |
| |
| RULECHECK denmos_20.SP.6 { |
| @ denmos_20.SP.6: Min space from P+ tap to source of zvt 20v nmos drain extended device < ${denmos_20_zvt_ptap_sp_src} |
| OUTPUT "EXT ptap (nsd_20v_src INTERACT (ENID INTERACT ngate_v20_zvt)) < ${denmos_20_zvt_ptap_sp_src} ABUT<90 REGION" |
| } |
| |
| RULECHECK denmos_20.XOR.2 { |
| @ denmos_20.XOR.2: lvtn must be coincident with pwbm of zvt 20v nmos drain extended device |
| OUTPUT "XOR ((lvtn INTERACT ENID) INTERACT ngate_v20_zvt) ((pwbm INTERACT ENID) INTERACT ngate_v20_zvt)" |
| } |
| |
| RULECHECK denmos_20.ENC.8 { |
| @ denmos_20.ENC.8: Min pwbm enclosure of dnwell of zvt 20v nmos drain extended device < ${denmos_20_zvt_pwbm_enc_dnw} |
| SETLAYER dnw_edge = "dnwell INSIDE EDGE (diffi INTERACT ngate_v20_zvt)" |
| OUTPUT "ENC dnw_edge pwbm < ${denmos_20_zvt_pwbm_enc_dnw} ABUT<90 REGION" |
| } |
| |
| RULECHECK denmos_20.ENC.9 { |
| @ denmos_20.ENC.9: Min enclosure of drain by nwell of zvt 20v nmos drain extended device < ${denmos_20_zvt_well_enc_drn} |
| SETLAYER dnm_20_drn_not_coin_edge_nw = "LENGTH (NOT COINCIDENT EDGE ((nsd_20v_drn INTERACT (ENID INTERACT ngate_v20_zvt)) AND diffi) nwell) > 10" |
| OUTPUT "ENC dnm_20_drn_not_coin_edge_nw nwell < ${denmos_20_zvt_well_enc_drn} ABUT<90 REGION OPPOSITE PARALLEL" |
| } |
| |
| verbatim { |
| |
| // |
| // iso denmos 20v checks |
| // |
| |
| } |
| |
| set denmos_20_iso_wid_poly 2.5 |
| set denmos_20_iso_wid_src 0.63 |
| set denmos_20_iso_wid_diff_under_poly 1.5 |
| set denmos_20_iso_wid_drn 1.5 |
| set denmos_20_iso_extn_pwbm_chan 1.0 |
| set denmos_20_iso_drn_diff_sp 2.0 |
| set denmos_20_iso_chan_len 30.0 |
| set denmos_20_iso_dnw_enc_drn 3.0 |
| set denmos_20_iso_pwbm_enc_dnw 6.0 |
| set denmos_20_iso_chan_wid 0.5 |
| set denmos_20_iso_ply_fld_ext 1.0 |
| set denmos_20_iso_ptap_sp_src 0.5 |
| set denmos_20_iso_well_enc_drn 0.05 |
| |
| RULECHECK denmos_20.WID.16 { |
| @ denmos_20.WID.16: Min width of gate poly in iso 20v nmos drain extended device < ${denmos_20_iso_wid_poly} |
| OUTPUT "INT (poly INTERACT ngate_v20_iso_rec) < ${denmos_20_iso_wid_poly} ABUT<90 REGION" |
| } |
| |
| RULECHECK denmos_20.WID.17 { |
| @ denmos_20.WID.17: Min width of source in iso 20v nmos drain extended device < ${denmos_20_iso_wid_src} |
| OUTPUT "INT (nsd_20v_src INTERACT ngate_v20_iso_rec) < ${denmos_20_iso_wid_src} ABUT<90 REGION" |
| } |
| |
| RULECHECK denmos_20.WID.18 { |
| @ denmos_20.WID.18: Min width of gate of iso 20v nmos drain extended device < ${denmos_20_iso_wid_diff_under_poly} |
| OUTPUT "INT (((diffi AND poly) INTERACT ENID) INTERACT (dnwell INTERACT ngate_v20_iso_rec)) < ${denmos_20_iso_wid_diff_under_poly} ABUT<90 REGION" |
| } |
| |
| RULECHECK denmos_20.WID.19 { |
| @ denmos_20.WID.19: Min width of drain of iso 20v nmos drain extended device < ${denmos_20_iso_wid_drn} |
| OUTPUT "INT ((nsd_20v_drn AND (dnwell INTERACT ngate_v20_iso_rec)) AND (diffi NOT polyi)) < ${denmos_20_iso_wid_drn} ABUT<90 REGION OPPOSITE PARALLEL" |
| } |
| |
| RULECHECK denmos_20.OVL.5 { |
| @ denmos_20.OVL.5: Min extension of pwbm over channel of iso 20v nmos drain extended device < ${denmos_20_iso_extn_pwbm_chan} |
| OUTPUT "INT (((pwbm INTERACT ngate_v20_iso_rec) AND diffi) NOT ((nsd_20v_drn AND (pwbm INTERACT ngate_v20_iso_rec)) AND (diffi NOT polyi))) < ${denmos_20_iso_extn_pwbm_chan} ABUT<90 REGION" |
| } |
| |
| RULECHECK denmos_20.SP.7 { |
| @ denmos_20.SP.7: Min space from drain_diff to gate or src_diff of iso 20v nmos drain extended device < ${denmos_20_iso_drn_diff_sp} |
| OUTPUT "EXT ((nsd_20v_drn AND (dnwell INTERACT ngate_v20_iso_rec)) AND (diffi NOT polyi)) (diffi INTERACT ngate_v20_iso_rec) < ${denmos_20_iso_drn_diff_sp} ABUT<90 REGION" |
| } |
| |
| RULECHECK denmos_20.LEN.4 { |
| @ denmos_20.LEN.4: Min channel width of iso 20v nmos drain extended device < ${denmos_20_iso_chan_len} |
| OUTPUT "EXPAND EDGE (LENGTH (ngate_v20_iso_rec COINCIDENT EDGE nsd_20v_src) < ${denmos_20_iso_chan_len}) OUTSIDE BY 0.05" |
| } |
| |
| RULECHECK denmos_20.ANG.4 { |
| @ denmos_20.ANG.4: 90 degree corners are not allowed on the drain_diff of the iso 20v nmos drain extended device |
| OUTPUT "diffi ENCLOSE (INT ((diffi AND (nsd_20v_drn AND (dnwell INTERACT ngate_v20_iso_rec))) NOT INTERACT polyi) < 0.05 ABUT==90 REGION)" |
| } |
| |
| RULECHECK denmos_20.WID.20 { |
| @ denmos_20.WID.20: Min channel length of iso 20v nmos drain extended device < ${denmos_20_iso_chan_wid} |
| OUTPUT "INT ngate_v20_iso_rec < ${denmos_20_iso_chan_wid} ABUT<90 REGION OPPOSITE PARALLEL" |
| } |
| |
| RULECHECK denmos_20.EXT.4 { |
| @ denmos_20.EXT.4: Min poly field extension past diffusion of iso 20v nmos drain extended device < ${denmos_20_iso_ply_fld_ext} |
| OUTPUT "ENC (diffi INTERACT nsd_20v_drn) (polyi INTERACT ngate_v20_iso_rec) < ${denmos_20_iso_ply_fld_ext} ABUT<90 REGION" |
| } |
| |
| RULECHECK denmos_20.SP.8 { |
| @ denmos_20.SP.8: Min space from P+ tap to source of iso 20v nmos drain extended device < ${denmos_20_iso_ptap_sp_src} |
| SETLAYER n20_iso_ptap = "(((diff AND psdm) NOT pwbm) AND dnwell) AND (HOLES pwbm) " |
| OUTPUT "EXT n20_iso_ptap (nsd_20v_src INTERACT (ENID INTERACT ngate_v20_iso_rec)) < ${denmos_20_iso_ptap_sp_src} ABUT<90 REGION" |
| } |
| |
| RULECHECK denmos_20.XOR.3 { |
| @ denmos_20.XOR.3: lvtn inside poly must be coincident with pwbm inside poly of isolated 20v nmos drain extended device |
| SETLAYER poly_healed = (polyi INTERACT ngate_v20_iso_rec) OR (HOLES (polyi INTERACT ngate_v20_iso_rec)) |
| SETLAYER poly_healed_size = SIZE poly_healed BY -0.5 |
| OUTPUT "XOR (((lvtn INTERACT ENID) INTERACT ngate_v20_iso_rec) AND poly_healed_size) (((pwbm INTERACT ENID) AND poly_healed_size) INTERACT ngate_v20_iso_rec)" |
| } |
| |
| RULECHECK denmos_20.ENC.10 { |
| @ denmos_20.ENC.10: Min enclosure of drain by nwell of iso 20v nmos drain extended device < ${denmos_20_iso_well_enc_drn} |
| SETLAYER dnm_20_drn_not_coin_edge_nw = "LENGTH (NOT COINCIDENT EDGE ((nsd_20v_drn INTERACT (ENID INTERACT ngate_v20_iso_rec)) AND diffi) nwell) > 10" |
| OUTPUT "ENC dnm_20_drn_not_coin_edge_nw nwell < ${denmos_20_iso_well_enc_drn} ABUT<90 REGION OPPOSITE PARALLEL" |
| } |
| |
| verbatim { |
| // |
| // depmos checks |
| // |
| |
| } |
| |
| set min_width_of_gate_of_Drain_Extended_pFET 1.05 |
| set min_width_of_dePFetSourceNotpoly 0.28 |
| set min_width_of_dePFetSource_overlapping_poly 0.92 |
| set min_width_of_drain_of_Drain_Extended_pFET 0.17 |
| set min_max_extension_between_de_pFET_source_beyond_nwell 0.26 |
| set min_max_spacing_between_de_pFET_source_and_de_pFET_drain 1.19 |
| set min_dePFet_channel_gate_length 5.0 |
| set min_enclosure_of_drain_of_Drain_Extended_pFET_by_nwellhole 0.86 |
| set min_spacing_of_ntap_and_dePFetDrainNwellHole 0.66 |
| set min_enclosure_of_source_of_Drain_Extended_pFET_by_psdm 0.13 |
| |
| SETLAYER dePFetDevice = "ENCLOSE thkox (INTERACT nwell (AND ENID dnwell))" |
| SETLAYER dePFetNwell = "INTERACT nwell dePFetDevice" |
| SETLAYER dePFetNwellHole = "HOLES dePFetNwell" |
| SETLAYER dePFetDiff = "INTERACT diffi dePFetNwellHole" |
| SETLAYER dePFetGate = "INTERACT (AND poly ENID) dePFetDiff" |
| SETLAYER dePFetSource = "INTERACT dePFetDiff dePFetGate" |
| SETLAYER dePFetSourceAndPoly = "AND dePFetSource dePFetGate" |
| SETLAYER dePFetSourceNotPoly = "NOT dePFetSource dePFetGate" |
| SETLAYER dePFetDrain = "INSIDE diffi dePFetNwellHole" |
| SETLAYER dePFetDrainBB = "EXTENTS dePFetDrain" |
| SETLAYER dePFetDrainEdges = "TOUCH EDGE dePFetDrain dePFetDrainBB" |
| SETLAYER dePFetSourceOvlNwellHole = "AND (AND dePFetNwellHole ENID) dePFetSource" |
| SETLAYER dePFetSourceGood = "INTERNAL dePFetSourceOvlNwellHole == ${min_max_extension_between_de_pFET_source_beyond_nwell} REGION" |
| SETLAYER dePFetSourceToDrainRegion = "NOT (AND ENID dePFetNwellHole) (OR dePFetSource dePFetDrainBB)" |
| SETLAYER dePFetSourceToDrainSpacingGood = "INTERNAL dePFetSourceToDrainRegion == ${min_max_spacing_between_de_pFET_source_and_de_pFET_drain} PARALLEL REGION" |
| |
| RULECHECK depmos.WID.1 { |
| @ depmos.WID.1: Min width of de_pFet_gate < ${min_width_of_gate_of_Drain_Extended_pFET} |
| OUTPUT "INTERNAL dePFetGate < ${min_width_of_gate_of_Drain_Extended_pFET} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK depmos.WID.2 { |
| @ depmos.WID.2: Min width of de_pFet_source not overlapping poly < ${min_width_of_dePFetSourceNotpoly} |
| OUTPUT "INTERNAL dePFetSourceNotpoly < ${min_width_of_dePFetSourceNotpoly} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK depmos.WID.3 { |
| @ depmos.WID.3: Min width of de_pFet_source overlapping poly < ${min_width_of_dePFetSource_overlapping_poly} |
| OUTPUT "INTERNAL dePFetSourceAndPoly < ${min_width_of_dePFetSource_overlapping_poly} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK depmos.WID.4 { |
| @ depmos.WID.4: Min width of the de_pFet_drain < ${min_width_of_drain_of_Drain_Extended_pFET} |
| OUTPUT "LENGTH dePFetDrainEdges < ${min_width_of_drain_of_Drain_Extended_pFET}" |
| } |
| |
| RULECHECK depmos.EXT.1 { |
| @ depmos.EXT.1: Min/Max extension of de_pFet_source beyond nwell = ${min_max_extension_between_de_pFET_source_beyond_nwell} |
| OUTPUT "(NOT dePFetSourceOvlNwellHole dePFetSourceGood) NOT INTERACT (ENID INTERACT pgate_de_20v)" |
| } |
| |
| RULECHECK depmos.SP.2 { |
| @ depmos.SP.2: Min/Max spacing between de_pFET_source and de_pFET_drain = ${min_max_spacing_between_de_pFET_source_and_de_pFET_drain} |
| OUTPUT "(NOT dePFetSourceToDrainRegion dePFetSourceToDrainSpacingGood) NOT INTERACT (ENID INTERACT pgate_de_20v)" |
| } |
| |
| RULECHECK depmos.WID.5 { |
| @ depmos.WID.5: Min channel width for de_pFet_gate < ${min_dePFet_channel_gate_length} |
| OUTPUT "LENGTH (dePFetGate INSIDE EDGE dePFetSource) < ${min_dePFet_channel_gate_length}" |
| } |
| |
| RULECHECK depmos.CON.1 { |
| @ depmos.CON.1: 90-degree angles are not permitted for nwell hole overlapping de_pFET_drain |
| OUTPUT "(EXPAND EDGE (CONVEX EDGE dePFetNwellHole ANGLE1 == 90 ANGLE2 > 0) OUTSIDE by 0.05) NOT INTERACT (dnwell INTERACT pgate_de_20v)" |
| } |
| |
| RULECHECK depmos.ENC.1 { |
| @ depmos.ENC.1: Min enclosure of de_pFet_drain by nwell hole < ${min_enclosure_of_drain_of_Drain_Extended_pFET_by_nwellhole} |
| OUTPUT "ENCLOSURE dePFetDrain dePFetNwellHole < ${min_enclosure_of_drain_of_Drain_Extended_pFET_by_nwellhole} MEASURE ALL ABUT < 90 SINGULAR REGION" |
| } |
| |
| RULECHECK depmos.SP.3 { |
| @ depmos.SP.3: Min spacing between n+ tap and (nwell hole enclosing de_pFET_drain) < ${min_spacing_of_ntap_and_dePFetDrainNwellHole} |
| SETLAYER dePFetNtap = "AND (OUTSIDE diffi dePFetNwellHole) dePFetDevice" |
| OUTPUT "EXTERNAL dePFetNtap dePFetNwellHole < ${min_spacing_of_ntap_and_dePFetDrainNwellHole} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK depmos.ENC.2 { |
| @ depmos.ENC.2: de_pFet_source must be enclosed by psdm < ${min_enclosure_of_source_of_Drain_Extended_pFET_by_psdm} |
| OUTPUT "ENCLOSURE dePFetSource psdm < ${min_enclosure_of_source_of_Drain_Extended_pFET_by_psdm} MEASURE ALL ABUT < 90 SINGULAR REGION" |
| } |
| |
| RULECHECK depmos.CON.2 { |
| @ depmos.CON.2: de_pFet_source must be enclosed by psdm |
| OUTPUT "dePFetSource NOT psdm" |
| } |
| |
| verbatim { |
| |
| // |
| // denpos 20v checks |
| // |
| |
| } |
| |
| set depmos_20_wid_poly 2.0 |
| set depmos_20_wid_src 0.29 |
| set depmos_20_wid_diff_under_poly 1.5 |
| set depmos_20_wid_drn 0.75 |
| set depmos_20_extn_pwde_chan 0.5 |
| set depmos_20_drn_diff_sp 1.5 |
| set depmos_20_chan_len 30.0 |
| set depmos_20_dnw_enc_drn 3.0 |
| set depmos_20_pwbm_enc_drn 3.0 |
| set depmos_20_pwde_enc_drn 2.5 |
| set depmos_20_pwbm_enc_pwde 0.5 |
| set depmos_20_chan_wid 0.5 |
| set depmos_20_ply_fld_ext 0.5 |
| set depmos_20_ntap_sp_src 0.29 |
| |
| SETLAYER pgate_de_20v = "(((((poly AND v20) AND thkox) AND diff) AND psdm) NOT lvtn) AND (ENID INTERACT pwde)" |
| SETLAYER psd_20v = "((diff AND psdm) NOT pgate_de_20v) INTERACT pgate_de_20v" |
| SETLAYER psd_20v_src_1 = "EXPAND EDGE ((psd_20v NOT pgate_de_20v) COINCIDENT EDGE ENID) OUTSIDE BY 0.05" |
| SETLAYER psrc_de_20v = "(psd_20v NOT pgate_de_20v) TOUCH psd_20v_src_1 == 3" |
| SETLAYER pdrn_de_20v = "(ENID INTERACT pgate_de_20v) NOT (OR pgate_de_20v psrc_de_20v)" |
| |
| RULECHECK depmos_20.WID.1 { |
| @ depmos_20.WID.1: Min width of gate poly in 20v pmos drain extended device < ${depmos_20_wid_poly} |
| OUTPUT "INT (poly INTERACT pgate_de_20v) < ${depmos_20_wid_poly} ABUT<90 REGION" |
| } |
| |
| RULECHECK depmos_20.WID.2 { |
| @ depmos_20.WID.2: Min width of source of 20v pmos drain extended device < ${depmos_20_wid_src} |
| OUTPUT "INT psrc_de_20v < ${depmos_20_wid_src} ABUT<90 REGION" |
| } |
| |
| RULECHECK depmos_20.WID.3 { |
| @ depmos_20.WID.3: Min width of gate of 20v pmos drain extended device < ${depmos_20_wid_diff_under_poly} |
| OUTPUT "INT (((diffi AND poly) INTERACT ENID) INTERACT (dnwell INTERACT pgate_de_20v)) < ${depmos_20_wid_diff_under_poly} ABUT<90 REGION" |
| } |
| |
| RULECHECK depmos_20.WID.4 { |
| @ depmos_20.WID.4: Min width of drain of 20v pmos drain extended device < ${depmos_20_wid_drn} |
| OUTPUT "INT ((pdrn_de_20v AND (dnwell INTERACT pgate_de_20v)) AND (diffi NOT polyi)) < ${depmos_20_wid_drn} ABUT<90 REGION OPPOSITE PARALLEL" |
| } |
| |
| RULECHECK depmos_20.WID.5 { |
| @ depmos_20.WID.5: Min width of pwde AND diff AND poly < ${depmos_20_extn_pwde_chan} |
| OUTPUT "INT ((pwde INTERACT (polyi INTERACT pdrn_de_20v)) AND diffi) < ${depmos_20_extn_pwde_chan} ABUT<90 REGION" |
| } |
| |
| RULECHECK depmos_20.SP.1 { |
| @ depmos_20.SP.1: Min space from drain_diff to gate or src_diff of 20v pmos drain extended device < ${depmos_20_drn_diff_sp} |
| OUTPUT "EXT ((pdrn_de_20v AND (dnwell INTERACT pgate_de_20v)) AND (diffi NOT polyi)) (diffi INTERACT pgate_de_20v) < ${depmos_20_drn_diff_sp} ABUT<90 REGION" |
| } |
| |
| RULECHECK depmos_20.LEN.1 { |
| @ depmos_20.LEN.1: Min channel width of 20v pmos drain extended device < ${depmos_20_chan_len} |
| OUTPUT "EXPAND EDGE (LENGTH (pgate_de_20v COINCIDENT EDGE psrc_de_20v) < ${depmos_20_chan_len}) OUTSIDE BY 0.05" |
| } |
| |
| RULECHECK depmos_20.ANG.1 { |
| @ depmos_20.ANG.1: 90 degree corners are not allowed on the drain_diff of the 20v pmos drain extended device |
| OUTPUT "diffi ENCLOSE (INT ((diffi AND pdrn_de_20v) NOT INTERACT polyi) < 0.05 ABUT==90 REGION)" |
| } |
| |
| RULECHECK depmos_20.ENC.1 { |
| @ depmos_20.ENC.1: Min enclosure of drain tap by pwbm in the direction of current flow of 20v pmos drain extended device < ${depmos_20_pwbm_enc_drn} |
| OUTPUT "ENC (((diffi AND (pdrn_de_20v AND (dnwell INTERACT pgate_de_20v))) NOT INTERACT polyi) COINCIDENT EDGE ENID) pwbm < ${depmos_20_pwbm_enc_drn} ABUT<90 REGION" |
| } |
| |
| RULECHECK depmos_20.ENC.2 { |
| @ depmos_20.ENC.2: Min enclosure of drain tap by pwde in the direction of current flow of 20v pmos drain extended device < ${depmos_20_pwde_enc_drn} |
| OUTPUT "ENC (((diffi AND (pdrn_de_20v AND (dnwell INTERACT pgate_de_20v))) NOT INTERACT polyi) COINCIDENT EDGE ENID) pwde < ${depmos_20_pwde_enc_drn} ABUT<90 REGION" |
| } |
| |
| RULECHECK depmos_20.ENC.3 { |
| @ depmos_20.ENC.3: Min enclosure of pwde by pwdm of 20v pmos drain extended device < ${depmos_20_pwbm_enc_pwde} |
| OUTPUT "ENC (pwde INTERACT (ENID INTERACT pdrn_de_20v)) (pwbm INTERACT (ENID INTERACT pdrn_de_20v)) < ${depmos_20_pwbm_enc_pwde} ABUT<90 REGION" |
| } |
| |
| RULECHECK depmos_20.WID.6 { |
| @ depmos_20.WID.6: Min channel length of 20v pmos drain extended device < ${depmos_20_chan_wid} |
| OUTPUT "INT pgate_de_20v < ${depmos_20_chan_wid} ABUT<90 REGION" |
| } |
| |
| RULECHECK depmos_20.EXT.1 { |
| @ depmos_20.EXT.1: Min poly field extension past diffusion of 20v pmos drain extended device < ${depmos_20_ply_fld_ext} |
| OUTPUT "ENC (diffi INTERACT pdrn_de_20v) (polyi INTERACT pgate_de_20v) < ${depmos_20_ply_fld_ext} ABUT<90 REGION" |
| } |
| |
| RULECHECK depmos_20.SP.2 { |
| @ depmos_20.SP.2: Min space from ntap to source of 20v pmos drain extended device < ${depmos_20_ntap_sp_src} |
| OUTPUT "EXT ntap psrc_de_20v < ${depmos_20_ntap_sp_src} ABUT<90 REGION" |
| } |
| |
| verbatim { |
| |
| // |
| // pwres checks |
| // |
| |
| } |
| |
| set min_max_spacing_of_pwres_tap_to_nwell 0.22 |
| set min_width_pwresTerm 0.53 |
| set min_max_width_of_pwres 2.65 |
| set min_length_of_pwres 26.50 |
| set max_length_of_pwres 265.00 |
| |
| SETLAYER DnwNoRing = "dnwell NOT nwellring" |
| SETLAYER PwresDnw = "pwres AND DnwNoRing" |
| SETLAYER PwresNwell = "PwresDnw COINCIDENT OUTSIDE EDGE nwell" |
| SETLAYER GoodPwresNwell = "PwresDnw WITH EDGE PwresNwell == 2" |
| SETLAYER BadPwresNwell = "PwresDnw NOT GoodPwresNwell" |
| SETLAYER PwresTap = "TOUCH EDGE PwresDnw tap" |
| SETLAYER GoodPwresTap = "PwresDnw WITH EDGE PwresTap == 2" |
| SETLAYER BadPwresTap = "PwresDnw NOT GoodPwresTap" |
| SETLAYER PwresTerm = "tap WITH EDGE (tap COINCIDENT OUTSIDE EDGE GoodPwresTap)" |
| SETLAYER GoodPwTap = "EXTERNAL PwresTerm nwell == ${min_max_spacing_of_pwres_tap_to_nwell} ABUT < 90 SINGULAR REGION" |
| SETLAYER PwresTermOutEdge = "PwresTerm NOT COINCIDENT EDGE PwresDnw" |
| SETLAYER BadPwTap = "PwresTermOutEdge NOT COINCIDENT EDGE GoodPwTap" |
| SETLAYER BadTapW = "SIZE (SIZE PwresTerm BY -(${min_width_pwresTerm}/2)) BY (${min_width_pwresTerm}/2)" |
| SETLAYER GoodTapLicon = "INTERACT PwresTerm (PwresTerm AND Licon) == 12" |
| SETLAYER GoodTapMcon = "INTERACT PwresTerm (PwresTerm AND Mcon) == 12" |
| SETLAYER BadTapLicon = "PwresTerm NOT GoodTapLicon" |
| SETLAYER BadTapMcon_tmp = "PwresTerm NOT GoodTapMcon" |
| SETLAYER BadTapMcon = "BadTapMcon_tmp AND met1" |
| SETLAYER nwellEnclosePwres = "TOUCH nwell PwresDnw" |
| SETLAYER tapRing = "(DONUT tap) AND nwellEnclosePwres" |
| SETLAYER tapRingLicon = "licon AND tapRing" |
| SETLAYER tapRingLi1 = "INTERACT li tapRingLicon" |
| SETLAYER tapRingMcon = "mcon AND tapRingLi1" |
| SETLAYER tapRingMet1 = "INTERACT met1 tapRingMcon" |
| SETLAYER tapRingMetStrap = "INTERACT tapRing tapRingMet1" |
| SETLAYER nonTapwell = "nwellEnclosePwres NOT (INTERACT nwell tapRingMetStrap)" |
| |
| RULECHECK pwres.CON.1 { |
| @ pwres.CON.1: pwres must be inside dnwell and inside an nwell hole |
| OUTPUT "pwres NOT DnwNoRing" |
| } |
| |
| RULECHECK pwres.CON.2 { |
| @ pwres.CON.2: pwres enclosed by dnwell should be rectangular |
| OUTPUT "NOT RECTANGLE PwresDnw ORTHOGONAL ONLY" |
| } |
| |
| RULECHECK pwres.WID.1 { |
| @ pwres.WID.1: Min/Max width of pwres = ${min_max_width_of_pwres} |
| SETLAYER pwresWidth1 = "INTERNAL PwresDnw < ${min_max_width_of_pwres} REGION" |
| SETLAYER pwresWidth2 = "INTERNAL PwresDnw == ${min_max_width_of_pwres} REGION" |
| OUTPUT "pwresWidth1 OR (PwresDnw NOT pwresWidth2)" |
| } |
| |
| RULECHECK pwres.LEN.1 { |
| @ pwres.LEN.1: Min length of pwres < ${min_length_of_pwres} |
| OUTPUT "INTERNAL PwresDnw < ${min_length_of_pwres} PROJECTING < ${min_length_of_pwres} REGION" |
| } |
| |
| RULECHECK pwres.LEN.2 { |
| @ pwres.LEN.2: Max length of pwres = ${max_length_of_pwres} |
| OUTPUT "PwresDnw WITH EDGE (LENGTH PwresDnw > ${max_length_of_pwres})" |
| } |
| |
| RULECHECK pwres.SP.1 { |
| @ pwres.SP.1: Min/Max spacing of a tap inside the pwell resistor to nwell = ${min_max_spacing_of_pwres_tap_to_nwell} |
| OUTPUT "COPY BadPwTap" |
| } |
| |
| RULECHECK pwres.WID.2 { |
| @ pwres.WID.2: Min width of pwres terminal < ${min_width_pwresTerm} |
| OUTPUT "INTERNAL PwresTerm < ${min_width_pwresTerm} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK pwres.CON.3 { |
| @ pwres.CON.3: pwres cannot be wider than width of pwell resistor P+ tap |
| OUTPUT "COPY BadTapW" |
| } |
| |
| RULECHECK pwres.CON.4 { |
| @ pwres.CON.4: P+ tap of pwell resister terminal must enclose 12 licons |
| OUTPUT "BadTapLicon OR BadTapMcon" |
| } |
| |
| RULECHECK pwres.CON.5a { |
| @ pwres.CON.5a: diff or poly is not allowed in the pwell resistor |
| OUTPUT "(OR diff poly) AND PwresDnw" |
| } |
| |
| RULECHECK pwres.CON.6 { |
| @ pwres.CON.6: N+ tap inside nwell ring of pwres must have metal straps |
| OUTPUT "COPY nonTapwell" |
| } |
| |
| RULECHECK pwres.CON.7 { |
| @ pwres.CON.7: pwell:res must abut pwell resistor terminals on opposite and parallel edges |
| OUTPUT "COPY BadPwresTap" |
| } |
| |
| RULECHECK pwres.CON.8 { |
| @ pwres.CON.8: pwell res must abut nwell edges on opposite sides |
| OUTPUT "COPY BadPwresNwell" |
| } |
| |
| verbatim { |
| |
| // |
| // hnwell checks |
| // |
| |
| } |
| |
| set min_spacing_of_5v_nwell_to_nwell 2.0 |
| set min_spacing_of_12v_20v_nwell_to_nwell 2.5 |
| |
| #SETLAYER nw_1p8v = "nwell NOT INTERACT (OR v5 v12 v20)" |
| #SETLAYER nw_5v = "nwell INTERACT (nwell AND v5)" |
| #SETLAYER nw_12v = "nwell INTERACT (nwell AND v12)" |
| SETLAYER nw_12_20v = "((nwell INTERACT v12) OR (nwell INTERACT v20)) NOT exempt_tech_CD" |
| #SETLAYER hv_nwell_1 = "OR nw_5v nw_12v nw_20v" |
| #SETLAYER HV_nwell = "STAMP hv_nwell_1 BY nwell" |
| #SETLAYER LV_nwell = "(nwell NOT INTERACT (OR v5 v12 v20)) NOT exempt_tech_CD" |
| #SETLAYER hvNwellConn = "NET AREA RATIO HV_nwell LV_nwell > 0" |
| #SETLAYER lvNwellConn = "NET AREA RATIO LV_nwell HV_nwell > 0" |
| |
| # JAG 7/14/2021 removed and replaced with new nwell spacing rules |
| #RULECHECK hnwell.SP.1 { |
| #@ hnwell.SP.1: Min spacing of 5 volt nwell & nwell < ${min_spacing_of_5v_nwell_to_nwell} |
| # #OUTPUT "EXTERNAL nw_5v nwell < ${min_spacing_of_5v_nwell_to_nwell} ABUT < 90 SINGULAR REGION NOT CONNECTED EXCLUDE FALSE" |
| # OUTPUT "EXT nw_5v nwell < ${min_spacing_of_5v_nwell_to_nwell} ABUT<90 SINGULAR REGION EXCLUDE FALSE" |
| # } |
| |
| #RULECHECK hnwell.SP.2 { |
| #@ hnwell.SP.2: Min spacing of (12v or 20v nwell) & nwell < ${min_spacing_of_12v_20v_nwell_to_nwell} |
| # OUTPUT "EXT nw_12_20v nwell < ${min_spacing_of_12v_20v_nwell_to_nwell} ABUT<90 SINGULAR REGION EXCLUDE FALSE" |
| # } |
| |
| #RULECHECK hnwell.CON.1 { |
| #@ hnwell.CON.1: N-well marked with v5, v12 or v20 must be enclosed by thkox |
| # OUTPUT "(OR nw_5v nw_12_20v) NOT thkox" |
| # } |
| |
| # JAG moved to nwell checks: |
| #RULECHECK hnwell.CON.2 { |
| #@ hnwell.CON.2: different voltage nwell should not be on the same net |
| ## must first remove nwells with multiple voltage markers: |
| # SETLAYER remove_nw_1 = "(nwell INTERACT nw_1p8v) INTERACT (OR nw_5v nw_12v nw_20v)" |
| # SETLAYER remove_nw_2 = "(nwell INTERACT nw_5v) INTERACT (OR nw_1p8v nw_12v nw_20v)" |
| # SETLAYER remove_nw_3 = "(nwell INTERACT nw_12v) INTERACT (OR nw_1p8v nw_5v nw_20v)" |
| # SETLAYER remove_nw_4 = "(nwell INTERACT nw_20v) INTERACT (OR nw_1p8v nw_5v nw_12v)" |
| # SETLAYER remove_multp_volt_nw = "OR remove_nw_1 remove_nw_2 remove_nw_3 remove_nw_4" |
| # SETLAYER err1 = "NET AREA RATIO nw_1p8v nw_5v > 0" |
| # OUTPUT "err1 NOT remove_multp_volt_nw" |
| # SETLAYER err2 = "NET AREA RATIO nw_1p8v nw_5v > 0" |
| # OUTPUT "err2 NOT remove_multp_volt_nw" |
| # SETLAYER err3 = "NET AREA RATIO nw_1p8v nw_12v > 0" |
| # OUTPUT "err3 NOT remove_multp_volt_nw" |
| # SETLAYER err4 = "NET AREA RATIO nw_1p8v nw_20v > 0" |
| # OUTPUT "err4 NOT remove_multp_volt_nw" |
| # SETLAYER err5 = "NET AREA RATIO nw_5v nw_12v > 0" |
| # OUTPUT "err5 NOT remove_multp_volt_nw" |
| # SETLAYER err6 = "NET AREA RATIO nw_5v nw_20v > 0" |
| # OUTPUT "err6 NOT remove_multp_volt_nw" |
| # SETLAYER err7 = "NET AREA RATIO nw_12v nw_20v > 0" |
| # OUTPUT "err7 NOT remove_multp_volt_nw" |
| # } |
| |
| #RULECHECK hnwell.CON.3 { |
| #@ hnwell.CON.3: N-well connected to 5v source or drain must have v5 marker |
| # SETLAYER psd_v5 = "psd INTERACT v5" |
| # SETLAYER nsd_v5 = "nsd INTERACT v5" |
| # OUTPUT "(NET AREA RATIO nwell psd_v5 > 0) NOT INTERACT v5" |
| # OUTPUT "(NET AREA RATIO nwell nsd_v5 > 0) NOT INTERACT v5" |
| # } |
| |
| #RULECHECK hnwell.CON.4 { |
| #@ hnwell.CON.4: N-well connected to 12v source or drain must have v12 marker |
| # SETLAYER psd_v12 = "psd INTERACT v12" |
| # SETLAYER nsd_v12 = "nsd INTERACT v12" |
| # OUTPUT "(NET AREA RATIO nwell psd_v12 > 0) NOT INTERACT v12" |
| # OUTPUT "(NET AREA RATIO nwell nsd_v12 > 0) NOT INTERACT v12" |
| # } |
| |
| #RULECHECK hnwell.CON.5 { |
| #@ hnwell.CON.5: N-well connected to 20v source or drain must have v20 marker |
| # SETLAYER psd_v20 = "psd INTERACT v20" |
| # SETLAYER nsd_v20 = "nsd INTERACT v20" |
| # OUTPUT "(NET AREA RATIO nwell psd_v20 > 0) NOT INTERACT v20" |
| # OUTPUT "(NET AREA RATIO nwell nsd_v20 > 0) NOT INTERACT v20" |
| # } |
| |
| verbatim { |
| |
| // |
| // hpoly checks |
| // |
| |
| } |
| |
| set min_hpoly_width_over_diff 0.5 |
| |
| SETLAYER gateHV_PERI = "gate_PERI AND v5" |
| SETLAYER gateEdgeHV_PERI = "poly COINCIDENT EDGE gateHV_PERI" |
| SETLAYER gateEdgeHV_PERI_err = "INTERNAL gateEdgeHV_PERI < ${min_hpoly_width_over_diff} OPPOSITE PARALLEL ONLY REGION" |
| |
| RULECHECK hpoly.WID.1 { |
| @ hpoly.WID.1: Min width of poly over diff inside v5 in periphery < 0.5 |
| OUTPUT "INTERNAL gateEdgeHV_PERI_err < ${min_hpoly_width_over_diff} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK hpoly.CON.1 { |
| @ hpoly.CON.1: gate must not straddle v5 |
| OUTPUT "CUT GATE v5" |
| } |
| |
| verbatim { |
| |
| // |
| // extd checks |
| // |
| |
| } |
| |
| set extd_step_size 0.005 |
| |
| SETLAYER deFetPoly = "INTERACT poly (poly AND ENID)" |
| SETLAYER deFetGate = "deFetPoly AND ENID" |
| SETLAYER difftapInsideEnid = "difftap INSIDE ENID" |
| SETLAYER difftapEndidEdg = "difftapInsideEnid COINCIDENT INSIDE EDGE ENID" |
| SETLAYER difftapEndidEdgExp = "EXPAND EDGE difftapEndidEdg OUTSIDE BY ${extd_step_size}" |
| SETLAYER goodHvdifftap = "TOUCH difftapInsideEnid difftapEndidEdgExp >= 2 <= 3" |
| SETLAYER badHvdifftap = "difftapInsideEnid NOT goodHvdifftap" |
| SETLAYER polyGap = "deFetGate NOT difftapInsideEnid" |
| |
| RULECHECK extd.CON.1 { |
| @ extd.CON.1: diff must not straddle areaid:extendedDrain |
| OUTPUT "CUT difftap ENID" |
| } |
| |
| RULECHECK extd.CON.2 { |
| @ extd.CON.2: diff must have two or three coincident edges with areaid:extendedDrain if enclosed by areaid:extendedDrain |
| OUTPUT "COPY badHvdifftap" |
| } |
| |
| RULECHECK extd.CON.3 { |
| @ extd.CON.3: poly must extend beyond overlapping diffusion inside areaid:extendedDrain |
| OUTPUT "deFetPoly OUTSIDE polyGap" |
| } |
| |
| verbatim { |
| |
| // |
| // npc checks |
| // |
| |
| } |
| |
| set min_npc_width 0.270 |
| set min_npc_spacing 0.270 |
| set min_spacing_of_npc_to_gate 0.090 |
| set max_enclosure_of_poly_overlapping_slotted_licon_by_npcm 0.095 |
| set min_enclosure_of_poly_licon_by_npc 0.045 |
| |
| SETLAYER ringLCON1 = "DONUT licon" |
| SETLAYER rectLCON1 = "licon NOT ringLCON1" |
| SETLAYER LCON1AndRpm = "rectLCON1 AND (rpm OR urpm)" |
| SETLAYER slotted_licon = "(WITH WIDTH LCON1AndRpm == 0.19) WITH EDGE (LENGTH LCON1AndRpm == 2.0)" |
| SETLAYER poly_with_slotlicon = "polyi ENCLOSE slotted_licon" |
| SETLAYER npc_no_hrpoly = "NOT INTERACT npc poly_with_slotlicon" |
| SETLAYER poly_edges_horiz = "ANGLE poly_with_slotlicon == 0" |
| SETLAYER poly_edges_vert = "ANGLE poly_with_slotlicon == 90" |
| #SETLAYER hrpoly_horiz = "DFM PROPERTY poly_with_slotlicon poly_edges_horiz poly_edges_vert OVERLAP \[\"-\" = length( poly_edges_horiz ) - length( poly_edges_vert )\] > 0" |
| #SETLAYER hrpoly_vert = "poly_with_slotlicon NOT hrpoly_horiz" |
| #SETLAYER valid_npc = "SIZE poly_with_slotlicon BY ${max_enclosure_of_poly_overlapping_slotted_licon_by_npcm}" |
| #SETLAYER npc_merge = "EXTERNAL valid_npc < ${min_npc_spacing} ABUT < 90 SINGULAR REGION PARALLEL OPPOSITE" |
| #SETLAYER valid_npc_final = "(valid_npc OR npc_merge) OR npc_no_hrpoly" |
| #SETLAYER hrpoly_horiz_edges = "EXPAND EDGE (ANGLE hrpoly_horiz == 0) OUTSIDE BY 0.1" |
| #SETLAYER hrpoly_vert_edges = "EXPAND EDGE (ANGLE hrpoly_vert == 90) OUTSIDE BY 0.1" |
| #SETLAYER npc_no_slot = "((hrpoly_horiz_edges OR hrpoly_vert_edges) AND npc) NOT valid_npc_final" |
| |
| RULECHECK npc.WID.1 { |
| @ npc.WID.1: Min width of npc < ${min_npc_width} |
| OUTPUT "INTERNAL npc < ${min_npc_width} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK npc.SP.1 { |
| @ npc.SP.1: Min spacing/notch of npc < ${min_npc_spacing} |
| OUTPUT "EXTERNAL npc < ${min_npc_spacing} ABUT < 90 SINGULAR REGION" |
| } |
| |
| RULECHECK npc.SP.2 { |
| @ npc.SP.2: Min spacing of npc & gate < ${min_spacing_of_npc_to_gate} |
| OUTPUT "EXTERNAL npc GATE < ${min_spacing_of_npc_to_gate} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK npc.CON.1 { |
| @ npc.CON.1: npc must not overlap gate |
| OUTPUT "npc AND GATE" |
| } |
| |
| # JAG 4/20/21 PM says remove this rule: |
| #RULECHECK npc.ENC.1 { |
| #@ npc.ENC.1: Max enclosure of poly overlapping slotted_licon by npc >= ${max_enclosure_of_poly_overlapping_slotted_licon_by_npcm} |
| # OUTPUT "COPY npc_no_slot" |
| # } |
| |
| |
| verbatim { |
| |
| // |
| // diff dummy (formally fom/dummy) |
| // |
| |
| } |
| |
| set min_fomdmy_width 0.50 |
| set max_fomdmy_width 25.00 |
| set min_fomdmy_spacing 0.40 |
| set min_spacing_of_fomdmy_to_sealid 1.00 |
| set min_spacing_of_fomdmy_to_fuse 3.25 |
| set min_spacing_of_fomdmy_to_nsdm_psdm 0.13 |
| set min_enclosure_of_fomdmy_by_nwell 0.18 |
| set min_spacing_of_fomdmy_to_nwell 0.34 |
| set min_enclosure_of_fom_dummy_by_HVnwell 0.43 |
| set min_spacing_of_fom_dummy_to_HVnwell 0.33 |
| set min_enclosure_of_fom_dummy_by_FRAMEID 0.50 |
| set min_spacing_of_fom_dummy_to_dieCut 0.50 |
| |
| RULECHECK diff_fill.WID.1 { |
| @ diff_fill.WID.1: Min width of diff fill < ${min_fomdmy_width} |
| OUTPUT "INTERNAL diff_fill < ${min_fomdmy_width} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK diff_fill.WID.2 { |
| @ diff_fill.WID.2: Max width of diff fill > ${max_fomdmy_width} |
| OUTPUT "LENGTH diff_fill > ${max_fomdmy_width}" |
| } |
| |
| RULECHECK diff_fill.SP.1 { |
| @ diff_fill.SP.1: Min spacing/notch of diff fill < ${min_fomdmy_spacing} |
| OUTPUT "EXTERNAL diff_fill < ${min_fomdmy_spacing} ABUT < 90 SINGULAR REGION" |
| } |
| |
| RULECHECK diff_fill.SP.2 { |
| @ diff_fill.SP.2: Min spacing of diff fill to areaid:seal < ${min_spacing_of_fomdmy_to_sealid} |
| OUTPUT "EXTERNAL diff_fill SEALID < ${min_spacing_of_fomdmy_to_sealid} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK diff_fill.CON.1 { |
| @ diff_fill.CON.1: diff fill must not overlap areaid:seal |
| OUTPUT "diff_fill AND SEALID" |
| } |
| |
| #RULECHECK diff_fill.SP.3 { |
| #@ diff_fill.SP.3: Min spacing of diff fill & fuse < ${min_spacing_of_fomdmy_to_fuse} |
| # OUTPUT "EXTERNAL diff_fill fuse < ${min_spacing_of_fomdmy_to_fuse} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| # } |
| |
| #RULECHECK diff_fill.CON.2 { |
| #@ diff_fill.CON.2: diff fill must not overlap fuse |
| # OUTPUT "diff_fill AND fuse" |
| # } |
| |
| RULECHECK diff_fill.SP.4 { |
| @ diff_fill.SP.4: Min spacing of diff fill to nsdm < ${min_spacing_of_fomdmy_to_nsdm_psdm} |
| OUTPUT "EXTERNAL diff_fill nsdm < ${min_spacing_of_fomdmy_to_nsdm_psdm} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK diff_fill.CON.3 { |
| @ diff_fill.CON.3: diff fill must not overlap nsdm |
| OUTPUT "diff_fill AND nsdm" |
| } |
| |
| RULECHECK diff_fill.SP.5 { |
| @ diff_fill.SP.5: Min spacing of diff fill to psdm < ${min_spacing_of_fomdmy_to_nsdm_psdm} |
| OUTPUT "EXTERNAL diff_fill psdm < ${min_spacing_of_fomdmy_to_nsdm_psdm} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK diff_fill.CON.4 { |
| @ diff_fill.CON.4: diff fill must not overlap psdm |
| OUTPUT "diff_fill AND psdm" |
| } |
| |
| RULECHECK diff_fill.ENC.1 { |
| @ diff_fill.ENC.1: Min enclosure of diff fill by nwell < ${min_enclosure_of_fomdmy_by_nwell} |
| OUTPUT "ENCLOSURE (diff_fill AND nwell) nwell < ${min_enclosure_of_fomdmy_by_nwell} MEASURE ALL ABUT < 90 SINGULAR" |
| } |
| |
| RULECHECK diff_fill.SP.6 { |
| @ diff_fill.SP.6: Min spacing of diff fill to nwell < ${min_spacing_of_fomdmy_to_nwell} |
| OUTPUT "EXTERNAL diff_fill nwell < ${min_spacing_of_fomdmy_to_nwell} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| SETLAYER five_volt_nw = "(nwell INTERACT v5) NOT INTERACT (OR v12 v20)" |
| RULECHECK diff_fill.ENC.2 { |
| @ diff_fill.ENC.2: Min enclosure of diff fill by 5 volt nwell < ${min_enclosure_of_fom_dummy_by_HVnwell} |
| OUTPUT "ENCLOSURE (diff_fill AND five_volt_nw) five_volt_nw < 0.43 MEASURE ALL ABUT < 90 SINGULAR" |
| } |
| |
| RULECHECK diff_fill.SP.7 { |
| @ diff_fill.SP.7: Min spacing of diff fill to HVnwell < ${min_spacing_of_fom_dummy_to_HVnwell} |
| OUTPUT "EXTERNAL diff_fill five_volt_nw < ${min_spacing_of_fom_dummy_to_HVnwell} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK diff_fill.ENC.3 { |
| @ diff_fill.ENC.3: Min enclosure of diff fill by areaid:frame < ${min_enclosure_of_fom_dummy_by_FRAMEID} |
| OUTPUT "ENCLOSURE (diff_fill AND FRAMEID) FRAMEID < ${min_enclosure_of_fom_dummy_by_FRAMEID} MEASURE ALL ABUT < 90 SINGULAR" |
| } |
| |
| RULECHECK diff_fill.SP.8 { |
| @ diff_fill.SP.8: Min spacing of diff fill to areaid:dieCut < ${min_spacing_of_fom_dummy_to_dieCut} |
| OUTPUT "EXTERNAL diff_fill dieCut < ${min_spacing_of_fom_dummy_to_dieCut} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| verbatim { |
| |
| // |
| // diff_v5 checks |
| // |
| |
| } |
| |
| set min_hdiff_width 0.29 |
| set hdiff_step_size 0.005 |
| set min_HvPdiffRes_width 0.15 |
| set min_spacing_notch_of_Hdiff_in_periphery 0.3 |
| set min_space_of_n+diff_to_non-abutting_p+tap_inside_v5 0.37 |
| set min_width_tap_butting_diff_on_one_or_two_sides_inside_v5 0.7 |
| set min_width_of_tapHV_noV20_butting_and_between_Hdiff 0.7 |
| set min_enclosure_of_p+_Hdiff 0.33 |
| set min_spacing_of_ndiff_nonESDv20_to_HV_nwell 0.43 |
| set min_enclosure_of_n+_Htap 0.33 |
| set min_spacing_of_P+_tap_to_HV_nwell 0.43 |
| set min_enclosure_of_Hdiff_or_Htap_by_v5 0.18 |
| set min_spacing_of_diffTapNoHv_PERI_to_v5 0.18 |
| set min_spacing_of_ndiffHV_nonESDv20_to_nwell 0.43 |
| |
| #SETLAYER diffHV = "((diffi AND v5) NOT tap) AND thkox" |
| SETLAYER diffHV = "(diffi AND v5) AND thkox" |
| SETLAYER diffHV_CORE = "diffHV AND COREID" |
| SETLAYER diffHV_PERI = "diffHV NOT COREID" |
| SETLAYER diffHVpRes_PERI = "diffHV_PERI AND (diffRes AND nwell)" |
| SETLAYER diffHVpResNormSize = "INTERACT diffHVpRes_PERI (EXPAND EDGE (LENGTH (diffHVpRes_PERI INSIDE EDGE diffHV) >= ${min_hdiff_width}) INSIDE BY ${hdiff_step_size})" |
| SETLAYER diffHVnopRes_PERI = "(diffHV_PERI NOT diffHVpRes_PERI) OR diffHVpResNormSize" |
| SETLAYER ndiffHV = "(NDIFF AND v5) AND thkox" |
| SETLAYER ndiffHV_PERI = "ndiffHV NOT COREID" |
| SETLAYER tapHV = "(tap AND v5) and thkox" |
| SETLAYER tapHV_PERI = "tapHV NOT COREID" |
| SETLAYER ptapHV = "(PTAP AND v5) AND thkox" |
| SETLAYER ptapHV_PERI = "ptapHV NOT COREID" |
| SETLAYER diffTapHV = "(diffTap AND v5) INTERACT thkox" |
| SETLAYER diffTapHV_PERI_nonV20 = "diffTapHV NOT (COREID OR v20)" |
| SETLAYER diffTapNoHv = "diffTap NOT (v5 AND thkox)" |
| SETLAYER diffTapNoHv_PERI = "diffTapNoHv NOT COREID" |
| SETLAYER NTAP_nonESD_nonv20 = "NTAP_PERI NOT (ESD_nwell_tap OR v20)" |
| SETLAYER nTapHV_nonESD_v20 = "NTAP_nonESD_nonv20 AND ((v5 AND thkox) OR HVNID)" |
| SETLAYER ptapHV_PERI_noAbut = "NOT TOUCH ptapHV_PERI ndiffHV_PERI" |
| SETLAYER PTAP_noPwellRes = "PTAP NOT (TOUCH PTAP pwres)" |
| SETLAYER ndiffHV_nonESD = "(ndiffHV NOT ESDID) NOT ENID" |
| SETLAYER ndiff_nonESD = "(NDIFF NOT ESD_nwell_tap) NOT ENID" |
| SETLAYER pdiffHV_nonESD = "(((PDIFF NOT ESD_nwell_tap) AND (v5 OR HVNID)) AND thkox) NOT (ENID OR v20)" |
| SETLAYER diffHV_noV20 = "diffHV NOT v20" |
| SETLAYER tapHV_noV20 = "tapHV NOT v20" |
| SETLAYER ndiff_nonESDv20 = "ndiff_nonESD NOT v20" |
| SETLAYER ndiffHV_nonESDv20 = "ndiffHV_nonESD NOT v20" |
| SETLAYER PTAP_noPwellRes_noV20 = "PTAP_noPwellRes NOT v20" |
| |
| RULECHECK diff_5v.WID.1 { |
| @ diff_5v.WID.1: Min width of diff (not tap) in v5 and periphery (exempt for pdiff resistor inside v5) < ${min_hdiff_width} |
| OUTPUT "INTERNAL ((diffHVnopRes_PERI OR (diffres INTERACT diffHVnopRes_PERI)) NOT tap) < ${min_hdiff_width} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK diff_5v.WID.2 { |
| @ diff_5v.WID.2: Min width of pdiff resistor inside v5 in periphery < 0.15 |
| OUTPUT "INTERNAL (NOT (AND (AND (AND nwell diffi) diffRes) v5) COREID) < 0.15 ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK diff_5v.SP.1 { |
| @ diff_5v.SP.1: Min spacing/notch of diff inside v5 and periphery < ${min_spacing_notch_of_Hdiff_in_periphery} |
| OUTPUT "EXTERNAL (diffHV_PERI NOT tap) < ${min_spacing_notch_of_Hdiff_in_periphery} ABUT < 90 SINGULAR REGION" |
| } |
| |
| RULECHECK diff_5v.SP.2 { |
| @ diff_5v.SP.2: Min space of n+diff to non-abutting p+tap inside v5 < ${min_space_of_n+diff_to_non-abutting_p+tap_inside_v5} |
| OUTPUT "EXTERNAL ndiffHV_PERI ptapHV_PERI_noAbut < ${min_space_of_n+diff_to_non-abutting_p+tap_inside_v5} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| SETLAYER butting_edge_marker = "EXPAND EDGE (diffHV_noV20 COINCIDENT EDGE tapHV) OUTSIDE BY 0.05" |
| |
| RULECHECK diff_5v.WID.3 { |
| @ diff_5v.WID.3: Min width tap butting diff on one or two sides inside v5 (rule exempted inside v20) < ${min_width_tap_butting_diff_on_one_or_two_sides_inside_v5} |
| OUTPUT "INT (PTAP TOUCH butting_edge_marker == 3) < ${min_width_tap_butting_diff_on_one_or_two_sides_inside_v5} ABUT < 90 REGION" |
| } |
| |
| RULECHECK diff_5v.WID.4 { |
| @ diff_5v.WID.4: Min width of abutting tap abutting and between diff inside v5 < ${min_width_of_tapHV_noV20_butting_and_between_Hdiff} |
| OUTPUT "INT (PTAP TOUCH butting_edge_marker == 2) < ${min_width_tap_butting_diff_on_one_or_two_sides_inside_v5} ABUT < 90 REGION" |
| } |
| |
| RULECHECK diff_5v.ENC.1 { |
| @ diff_5v.ENC.1: nwell inside v5 min enclosure of (pdiff outside areaid:esd) < ${min_enclosure_of_p+_Hdiff} |
| OUTPUT "ENCLOSURE (pdiffHV_nonESD AND five_volt_nw) five_volt_nw < ${min_enclosure_of_p+_Hdiff} MEASURE ALL ABUT < 90 SINGULAR" |
| } |
| |
| RULECHECK diff_5v.SP.3 { |
| @ diff_5v.SP.3: Min spacing of ndiff (outside areaid:ESD) to nwell inside v5 < ${min_spacing_of_ndiff_nonESDv20_to_HV_nwell} |
| OUTPUT "EXTERNAL ndiff_nonESDv20 five_volt_nw < ${min_spacing_of_ndiff_nonESDv20_to_HV_nwell} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK diff_5v.ENC.2 { |
| @ diff_5v.ENC.2: nwell inside v5 min enclosure of (ntap outside areaid:esd) < ${min_enclosure_of_n+_Htap} |
| OUTPUT "ENCLOSURE (nTapHV_nonESD_v20 AND five_volt_nw) five_volt_nw < ${min_enclosure_of_n+_Htap} MEASURE ALL ABUT < 90 SINGULAR REGION" |
| } |
| |
| RULECHECK diff_5v.SP.4 { |
| @ diff_5v.SP.4: Min spacing of P+ tap to nwell inside v5 (Exempt for p+tap butting pwell resistor and inside v20) < ${min_spacing_of_P+_tap_to_HV_nwell} |
| OUTPUT "EXTERNAL PTAP_noPwellRes_noV20 five_volt_nw < ${min_spacing_of_P+_tap_to_HV_nwell} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK diff_5v.CON.1 { |
| @ diff_5v.CON.1: diff in periphery must not straddle v5 |
| OUTPUT "CUT diffTap_PERI v5" |
| } |
| |
| RULECHECK diff_5v.CON.1a { |
| @ diff_5v.CON.1a: diff in periphery must not straddle thkox |
| OUTPUT "CUT diffTap_PERI thkox" |
| } |
| |
| RULECHECK diff_5v.ENC.3 { |
| @ diff_5v.ENC.3: Min enclosure of diff inside v5 by thkox (exempt inside v20) < ${min_enclosure_of_Hdiff_or_Htap_by_v5} |
| OUTPUT "ENCLOSURE (diffTapHV_PERI_nonV20 AND thkox) thkox < ${min_enclosure_of_Hdiff_or_Htap_by_v5} MEASURE ALL ABUT < 90 SINGULAR REGION" |
| } |
| |
| RULECHECK diff_5v.SP.5 { |
| @ diff_5v.SP.5: Min spacing between diff outside thkox to thkox < ${min_spacing_of_diffTapNoHv_PERI_to_v5} |
| OUTPUT "EXTERNAL diffTapNoHv_PERI thkox < ${min_spacing_of_diffTapNoHv_PERI_to_v5} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK diff_5v.SP.6 { |
| @ diff_5v.SP.6: Min spacing of ndiff inside v5 (outside areaid:ESD and outside v20)) to nwell < ${min_spacing_of_ndiffHV_nonESDv20_to_nwell} |
| OUTPUT "EXTERNAL ndiffHV_nonESDv20 nwell < ${min_spacing_of_ndiffHV_nonESDv20_to_nwell} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| verbatim { |
| |
| // |
| // hv checks |
| // |
| |
| } |
| |
| set min_hvSD_to_diff_n_diodes 0.3 |
| set hv_step_size 0.005 |
| set min_spacing_diff_resistors_to_hv_srcdrc 0.43 |
| set min_spacing_hv_source_to_nwell_diffRes_and_diodes 0.55 |
| set min_spacing_of_hvPoly_on_field_to_diff 0.3 |
| set min_spacing_of_hvPoly_on_field_to_n-well 0.55 |
| set min_enc_of_hvPoly_on_field_by_n-well 0.3 |
| set min_ext_of_poly_beyond_hvFET_gate 0.16 |
| |
| SETLAYER hv_diff_n = "nsd NET AREA RATIO (nsd AND (v12 OR v20)) > 0" |
| SETLAYER hv_diff_p = "psd NET AREA RATIO (psd AND (v12 OR v20)) > 0" |
| SETLAYER hv_diff = "OR hv_diff_n hv_diff_p" |
| SETLAYER hv_diff_not_tap = "hv_diff NOT TOUCH tap" |
| |
| CONNECT li hv_diff_not_tap by licon |
| |
| SETLAYER lv_diff_not_tap = "(diffi NOT tap) NOT (OR v12 v20)" |
| SETLAYER hv_diff_not_butting_tap = "hv_diff_not_tap NOT TOUCH tap" |
| SETLAYER lv_diff_not_butting_tap = "lv_diff_not_tap NOT TOUCH tap" |
| |
| |
| SETLAYER shv_ntap = "ntap AND (OR v12 v20)" |
| SETLAYER shv_nw = "NET AREA RATIO nwell shv_ntap > 0" |
| |
| # JAG 7/12/21 deleted as duplicate of hnwell.SP.1/2: |
| #RULECHECK hv.nwell.SP.1 { |
| # @ hv.nwell.SP.1: Minimum space of 12v or 20v nwell to nwell on different nets < 2.0 |
| # OUTPUT "EXT shv_nw nwell < 2.0 ABUT<90 REGION NOT CONNECTED" |
| # } |
| |
| RULECHECK hv.SP.1 { |
| @ hv.SP.1: Minimum 12v or 20v source/drain spacing to diff for edges of 12v or 20v source/drain diff not butting tap < ${min_hvSD_to_diff_n_diodes} |
| OUTPUT "EXT hv_diff_not_butting_tap diffi < ${min_hvSD_to_diff_n_diodes} ABUT<90 REGION" |
| } |
| |
| SETLAYER nsd_net_hv_diff_1a = "NET AREA RATIO nsd hv_diff_not_tap > 0" |
| SETLAYER psd_net_hv_diff_1b = "NET AREA RATIO psd hv_diff_not_tap > 0" |
| SETLAYER net_conn_hv_diff = "OR nsd_net_hv_diff_1a psd_net_hv_diff_1b" |
| SETLAYER diff_res_term_touch_net_conn_hv_diff = "net_conn_hv_diff TOUCH (OR rndiff rpdiff)" |
| SETLAYER diff_res_body_touch_diff_term_hv_net = "(rpdiff OR rndiff) TOUCH diff_res_term_touch_net_conn_hv_diff" |
| |
| RULECHECK hv.SP.2 { |
| @ hv.SP.2: Minimum spacing of n+/p+ diff resistors connected to 12v or 20v source/drain to diff < ${min_hvSD_to_diff_n_diodes} |
| OUTPUT "EXTERNAL diff_res_body_touch_diff_term_hv_net diffi < ${min_hvSD_to_diff_n_diodes} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| SETLAYER dio_body = "diffi AND DIODEID" |
| SETLAYER dio_body_conn_hv_diff = "dio_body AND net_conn_hv_diff" |
| SETLAYER diff_dio_conn_hv_diff = "dio_body_conn_hv_diff AND diffi" |
| |
| RULECHECK hv.SP.3 { |
| @ hv.SP.3: Minimum spacing of n+/p+ diff diodes connected to 12v or 20v source/drain to diff < ${min_hvSD_to_diff_n_diodes} |
| OUTPUT "EXTERNAL diff_dio_conn_hv_diff diffi < ${min_hvSD_to_diff_n_diodes} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| SETLAYER nw_net_hv_diff = "NET AREA RATIO nwell hv_diff_not_tap > 0" |
| |
| RULECHECK hv.SP.4 { |
| @ hv.SP.4: Minimum spacing of nwell connected to 12v or 20v source/drain to n+ diff < ${min_spacing_diff_resistors_to_hv_srcdrc} |
| OUTPUT "EXTERNAL nw_net_hv_diff (diffi AND nsdm) < ${min_spacing_diff_resistors_to_hv_srcdrc} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK hv.SP.5 { |
| @ hv.SP.5: Minimum N+ 12v or 20v source/drain spacing to nwell < ${min_spacing_hv_source_to_nwell_diffRes_and_diodes} |
| OUTPUT "EXTERNAL hv_diff_not_tap nwell < ${min_spacing_hv_source_to_nwell_diffRes_and_diodes} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| RULECHECK hv.SP.6 { |
| @ hv.SP.6: Minimum spacing of n+ diff resistors connected to 12v or 20v source/drain to nwell < ${min_spacing_hv_source_to_nwell_diffRes_and_diodes} |
| OUTPUT "EXTERNAL (diff_res_body_touch_diff_term_hv_net AND nsdm) nwell < ${min_spacing_hv_source_to_nwell_diffRes_and_diodes} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK hv.SP.7 { |
| @ hv.SP.7: Minimum spacing of n+ diff diodes connected to 12v or 20v source/drain to nwell < ${min_spacing_hv_source_to_nwell_diffRes_and_diodes} |
| OUTPUT "EXTERNAL (diff_dio_conn_hv_diff AND nsdm) nwell < ${min_spacing_hv_source_to_nwell_diffRes_and_diodes} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| SETLAYER hv_gate = "gate AND ((v12 OR v20) AND thkox)" |
| SETLAYER sd = "OR nsd psd" |
| SETLAYER hv_mark = "v12 OR v20" |
| SETLAYER hv_sd = "sd AND hv_mark" |
| SETLAYER hv_poly = "polyi TOUCH (sd AND (hv_mark AND thkox))" |
| SETLAYER poly_touch_nsd_tied = "hv_gate NET INTERACT nsd == 2" |
| SETLAYER poly_touch_psd_tied = "hv_gate NET INTERACT psd == 2" |
| SETLAYER poly_touch_sd_tied = "OR poly_touch_nsd_tied poly_touch_psd_tied" |
| SETLAYER hv_poly_cross_gt_1_diff = "hv_poly INTERACT sd > 2" |
| |
| RULECHECK hv.CON.1 { |
| @ hv.CON.1: 12v or 20v poly must overlap only one diff unless source and drains are tied |
| OUTPUT "hv_poly_cross_gt_1_diff NOT INTERACT poly_touch_sd_tied" |
| } |
| |
| SETLAYER poly_x_nw_exempt = "polyii INSIDE CELL \"pmos_de_v12*\" \"pmos_de_v20*\" \"nmos_de_12\" \"nmos_de_v20\"" |
| |
| RULECHECK hv.CON.2 { |
| @ hv.CON.2: 12v or 20v poly cannot cross nwell boundary except for pmos drain extended devices |
| OUTPUT "(EXPAND EDGE (nwell INSIDE EDGE hv_poly) OUTSIDE BY 0.05) NOT poly_x_nw_exempt" |
| } |
| |
| RULECHECK hv.SP.8 { |
| @ hv.SP.8: Min spacing of 12v or 20v poly to 1.8v, 3.3v or 5v diff (exempt for diff butting v12 or v20 poly) < ${min_spacing_of_hvPoly_on_field_to_diff} |
| SETLAYER diff_butt_poly = "diffi TOUCH hv_poly" |
| OUTPUT "EXT hv_poly (diffi NOT (OR v12 v20 diff_butt_poly)) < ${min_spacing_of_hvPoly_on_field_to_diff} ABUT<90 REGION" |
| } |
| |
| RULECHECK hv.SP.9 { |
| @ hv.SP.9: Min spacing of 12v or 20v poly to nwell (exempt poly stradding nwell in a depmos) < ${min_spacing_of_hvPoly_on_field_to_n-well} |
| OUTPUT "EXTERNAL (hv_poly NOT poly_x_nw_exempt) nwell < ${min_spacing_of_hvPoly_on_field_to_n-well} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK hv.ENC.1 { |
| @ hv.ENC.1: Min enclosure of 12v or 20v poly (including high voltage poly resistor) by nwell (exempt for poly straddling nwell in a depmos) < ${min_enc_of_hvPoly_on_field_by_n-well} |
| OUTPUT "ENC ((hv_poly AND nwell) NOT poly_x_nw_exempt) nwell < ${min_enc_of_hvPoly_on_field_by_n-well} REGION MEASURE ALL ABUT < 90 SINGULAR" |
| } |
| |
| SETLAYER diff_exempt = "diffii INSIDE CELL \"pmos_de_v12*\" \"pmos_de_v20*\" \"nmos_de_v12*\" \"nmos_de_v20*\"" |
| |
| RULECHECK hv.ENC.2 { |
| @ hv.ENC.2: Min extension of poly beyond 12v or 20v gate (exempt poly extending beyond diff along the S/D direction in a denmos/depmos) < ${min_ext_of_poly_beyond_hvFET_gate} |
| OUTPUT "ENC ((diffi NOT diff_exempt) INTERACT hv_sd) polyi < ${min_ext_of_poly_beyond_hvFET_gate} ABUT<90 REGION SINGULAR" |
| } |
| |
| verbatim { |
| |
| // |
| // tunm checks |
| // |
| |
| } |
| |
| set tunm_width 0.41 |
| set tunm_spacing 0.5 |
| set tunn_ext_beyond_gate 0.095 |
| set tunm_spacing_to_gate_not_in_tunm 0.095 |
| set tunm_area 0.672 |
| |
| RULECHECK tunm.WID.1 { |
| @ tunm.WID.1: Min width of tunm < ${tunm_width} |
| OUTPUT "INTERNAL tunm < ${tunm_width} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK tunm.SP.1 { |
| @ tunm.SP.1: Min spacing/notch of tunm to tunm < ${tunm_spacing} |
| OUTPUT "EXTERNAL tunm < ${tunm_spacing} ABUT < 90 SINGULAR REGION" |
| } |
| |
| RULECHECK tunm.ENC.1 { |
| @ tunm.ENC.1: Extension of tunm beyond (poly and diff) < ${tunn_ext_beyond_gate} |
| OUTPUT "ENC GATE tunm < ${tunn_ext_beyond_gate} MEASURE COINCIDENT ABUT < 90 SINGULAR REGION" |
| } |
| |
| RULECHECK tunm.SP.2 { |
| @ tunm.SP.2: Min spacing of tunm to (poly and diff) outside tunm < ${tunm_spacing_to_gate_not_in_tunm} |
| OUTPUT "EXTERNAL (GATE NOT tunm) tunm < ${tunm_spacing_to_gate_not_in_tunm} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK tunm.CON.1 { |
| @ tunm.CON.1: gate (poly and diff) may not straddle tunm |
| OUTPUT "CUT GATE tunm" |
| } |
| |
| RULECHECK tunm.CON.2 { |
| @ tunm.CON.2: tunm outside deep n-well is not allowed |
| OUTPUT "(tunm NOT dnwell) NOT exempt_tech_CD" |
| } |
| |
| RULECHECK tunm.AR.1 { |
| @ tunm.AR.1: Min tunm area < ${tunm_area} |
| OUTPUT "AREA tunm < ${tunm_area}" |
| } |
| |
| RULECHECK tunm.CON.3 { |
| @ tunm.CON.3: tunm must be enclosed by areaid:core |
| OUTPUT "tunm NOT COREID" |
| } |
| |
| verbatim { |
| |
| // |
| // hvntm checks |
| // |
| |
| } |
| |
| set min_width_of_hvntm_in_peri 0.7 |
| set min_spacing_of_hvntm_in_peri 0.7 |
| set min_enc_of_hvntm_over_ndiff_in_v5_outside_COREID 0.185 |
| set min_spacing_of_ndiff_outside_COREID_to_hvntm 0.185 |
| set min_spacing_of_pdiff_to_hvntm 0.185 |
| set min_spacing_between_pdiff_and_hvntm_not_diff_butting_edge 0.185 |
| |
| SETLAYER hvntm_peri = "hvntm NOT COREID" |
| SETLAYER ndiffInV5 = "(NDIFF AND v5) AND thkox" |
| SETLAYER ndiffInV5Peri = "ndiffInV5 NOT (ndiffInV5 AND COREID)" |
| SETLAYER ndiffOutsideV5 = "NDIFF OUTSIDE v5" |
| SETLAYER PDIFF_notENID = "PDIFF NOT ENID" |
| SETLAYER PTAPnoButtDiff = "PTAP OUTSIDE EDGE NDIFF" |
| SETLAYER diffpTapButtEdge_sz = "EXPAND EDGE (NDIFF COINCIDENT OUTSIDE EDGE PTAP) OUTSIDE BY 0.005" |
| SETLAYER ESD_nwell_tap_inside_v5 = "ESD_nwell_tap INSIDE (v5 INTERACT thkox)" |
| |
| RULECHECK hvntm.CON.2 { |
| @ hvntm.CON.2: hvntm must be drawn inside v5 and thkox |
| OUTPUT "hvntm NOT INSIDE (v5 AND thkox)" |
| } |
| |
| RULECHECK hvntm.WID.1 { |
| @ hvntm.WID.1: Min width of hvntm not in areaid:core < ${min_width_of_hvntm_in_peri} |
| OUTPUT "INTERNAL hvntm_peri < ${min_width_of_hvntm_in_peri} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK hvntm.SP.1 { |
| @ hvntm.SP.1: Min spacing/notch of hvntm not in areaid:core < ${min_spacing_of_hvntm_in_peri} |
| OUTPUT "EXTERNAL hvntm_peri < ${min_spacing_of_hvntm_in_peri} ABUT < 90 SINGULAR REGION" |
| } |
| |
| RULECHECK hvntm.ENC.1 { |
| @ hvntm.ENC.1: Min enclosure of (n+_diff inside v5 and thkox) but not overlapping areaid:core by hvntm < ${min_enc_of_hvntm_over_ndiff_in_v5_outside_COREID} |
| OUTPUT "ENCLOSURE (ndiffInV5Peri AND hvntm_peri) hvntm_peri < ${min_enc_of_hvntm_over_ndiff_in_v5_outside_COREID} MEASURE ALL ABUT < 90 SINGULAR REGION" |
| } |
| |
| RULECHECK hvntm.SP.2 { |
| @ hvntm.SP.2: Min spacing between n+_diff outside v5 and thkox and hvntm < ${min_spacing_of_ndiff_outside_COREID_to_hvntm} |
| OUTPUT "EXTERNAL hvntm_peri ndiffOutsideV5 < ${min_spacing_of_ndiff_outside_COREID_to_hvntm} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK hvntm.CON.3 { |
| @ hvntm.CON.3: No overlap between n+_diff outside v5 and thkox and hvntm |
| OUTPUT "hvntm_peri AND ndiffOutsideV5" |
| OUTPUT "hvntm_peri NOT thkox" |
| } |
| |
| RULECHECK hvntm.SP.3 { |
| @ hvntm.SP.3: Min spacing between p+_diff and hvntm < ${min_spacing_of_pdiff_to_hvntm} |
| OUTPUT "EXTERNAL hvntm_peri PDIFF_notENID < ${min_spacing_of_pdiff_to_hvntm} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK hvntm.CON.4 { |
| @ hvntm.CON.4: No overlap between p+_diff and hvntm |
| OUTPUT "hvntm_peri AND PDIFF_notENID" |
| } |
| |
| RULECHECK hvntm.SP.4 { |
| @ hvntm.SP.4: Min spacing between p+_tap and hvntm (except along the diff-butting edge) < ${min_spacing_between_pdiff_and_hvntm_not_diff_butting_edge} |
| OUTPUT "EXTERNAL hvntm_peri PTAPnoButtDiff < ${min_spacing_between_pdiff_and_hvntm_not_diff_butting_edge} ABUT < 90 REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK hvntm.CON.5 { |
| @ hvntm.CON.5: No overlap between p+_tap and hvntm (except along the diff-butting edge) |
| OUTPUT "hvntm_peri AND PTAP" |
| } |
| |
| RULECHECK hvntm.CON.6 { |
| @ hvntm.CON.6: No overlap between p+_tap and hvntm along the diff-butting edge |
| OUTPUT "hvntm_peri AND diffpTapButtEdge_sz" |
| } |
| |
| RULECHECK hvntm.CON.7 { |
| @ hvntm.CON.7: hvntm not in areaid:CORE must enclose ESD nwell n+ tap inside v5 and thkox |
| OUTPUT "(esd_nwell_tap_inside_v5 AND thkox) NOT hvntm_peri" |
| } |
| |
| RULECHECK hvntm.CON.8 { |
| @ hvntm.CON.8: A 5v ESD nwell n+ tap must be enclosed by hvntm when not in areaid:core |
| OUTPUT "ESD_nwell_tap_inside_v5 NOT hvntm_peri" |
| } |
| |
| RULECHECK hvntm.CON.9 { |
| @ hvntm.CON.9: hvntm must not overlap areaid:core |
| OUTPUT "hvntm AND COREID" |
| } |
| |
| verbatim { |
| |
| // |
| // metal blockage checks |
| // |
| |
| } |
| proc metal_blockage_check { layer_name layer_spacing layer_pin_size layer_step blockage_to_routing_spacing } { |
| |
| RULECHECK ${layer_name}_block.SP.1 { |
| @ ${layer_name}_block.SP.1: Min spacing of $layer_name to ${layer_name}_block < ${layer_spacing} |
| OUTPUT "EXTERNAL $layer_name ${layer_name}_block < ${layer_spacing} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK ${layer_name}_block.CON.1 { |
| @ ${layer_name}_block.CON.1: $layer_name must not overlap ${layer_name}_block |
| OUTPUT "$layer_name AND ${layer_name}_block" |
| } |
| |
| RULECHECK ${layer_name}_block.SP.2 { |
| @ ${layer_name}_block.SP.2: Min spacing of ${layer_name}_block to ${layer_name}_routing < ${blockage_to_routing_spacing} |
| OUTPUT "EXTERNAL ${layer_name}_block (SIZE ${layer_name}pin BY ${layer_pin_size} INSIDE OF ${layer_name} STEP ${layer_step}) < ${blockage_to_routing_spacing} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| } |
| |
| metal_blockage_check "met1" "0.14" "0.07" "0.095" "0.145" |
| metal_blockage_check "met2" "0.14" "0.07" "0.095" "0.145" |
| metal_blockage_check "met3" "0.3" "0.15" "0.21" "0.305" |
| metal_blockage_check "met4" "0.3" "0.15" "0.21" "0.305" |
| metal_blockage_check "met5" "1.6" "0.8" "1.13" "1.605" |
| metal_blockage_check "li" "0.17" "0.085" "0.12" "0.17" |
| |
| SETLAYER SEALnoHoles_ORIGIN = "(DONUT SEALID) OR (HOLES SEALID)" |
| |
| proc misc_blockage_check { layer_name type_of_rule } { |
| |
| if { $layer_name == "prBndry" } { |
| set boundary_layer "prBoundary.boundary" |
| if { $type_of_rule == "REQUIRED" } { |
| SETLAYER pr_chip_check_$type_of_rule = "$layer_name AND SEALnoHoles_ORIGIN" |
| SETLAYER pr_ip_check_$type_of_rule = "$layer_name NOT SEALnoHoles_ORIGIN" } |
| if { $type_of_rule == "RECOMMENDED" } { |
| SETLAYER pr_chip_check_$type_of_rule = "$layer_name AND SEALnoHoles_ORIGIN" |
| SETLAYER pr_ip_check_$type_of_rule = "$layer_name NOT SEALnoHoles_ORIGIN" } |
| } |
| |
| if { $layer_name == "polyBndry" } { |
| set boundary_layer "poly.boundary" |
| if { $type_of_rule == "REQUIRED" } { |
| SETLAYER poly_chip_check_$type_of_rule = "INTERACT $layer_name SEALnoHoles_ORIGIN" |
| SETLAYER poly_ip_check_$type_of_rule = "$layer_name NOT poly_chip_check_$type_of_rule" } |
| if { $type_of_rule == "RECOMMENDED" } { |
| SETLAYER poly_chip_check_$type_of_rule = "INTERACT $layer_name SEALnoHoles_ORIGIN" |
| SETLAYER poly_ip_check_$type_of_rule = "$layer_name NOT poly_chip_check_$type_of_rule" } |
| } |
| |
| if { $layer_name == "diffBndry" } { |
| set boundary_layer "diff.boundary" |
| if { $type_of_rule == "REQUIRED" } { |
| SETLAYER diff_chip_check_$type_of_rule = "$layer_name INTERACT SEALnoHoles_ORIGIN" |
| SETLAYER diff_ip_check_$type_of_rule = "$layer_name NOT poly_chip_check_$type_of_rule" } |
| if { $type_of_rule == "RECOMMENDED" } { |
| SETLAYER diff_chip_check_$type_of_rule = "$layer_name INTERACT SEALnoHoles_ORIGIN" |
| SETLAYER diff_ip_check_$type_of_rule = "$layer_name NOT poly_chip_check_$type_of_rule" } |
| } |
| |
| if { $type_of_rule == "REQUIRED" } { |
| RULECHECK $layer_name.CON.1 { |
| @ $layer_name.CON.1: $boundary_layer not allowed in IP layout |
| if { $layer_name == "prBndry" } { OUTPUT "COPY pr_ip_check_$type_of_rule" } |
| #if { $layer_name == "polyBndry" } { OUTPUT "COPY poly_ip_check_$type_of_rule" } |
| #if { $layer_name == "diffBndry" } { OUTPUT "COPY diff_ip_check_$type_of_rule" } |
| } |
| } |
| |
| |
| if { $type_of_rule == "RECOMMENDED" } { |
| RULECHECK $layer_name.CON.2 { |
| @ $layer_name.CON.2: $boundary_layer not allowed in chip layout |
| if { $layer_name == "prBndry" } { OUTPUT "COPY pr_chip_check_$type_of_rule" } |
| if { $layer_name == "polyBndry" } { OUTPUT "COPY poly_chip_check_$type_of_rule" } |
| if { $layer_name == "diffBndry" } { OUTPUT "COPY diff_chip_check_$type_of_rule" } |
| } |
| } |
| |
| } |
| |
| misc_blockage_check "prBndry" "REQUIRED" |
| #misc_blockage_check "polyBndry" "REQUIRED" |
| #misc_blockage_check "diffBndry" "REQUIRED" |
| |
| // |
| // PAD rules |
| // |
| |
| SETLAYER sealid_hole = "HOLES SEALID" |
| SETLAYER dieEdgeHoriz = "ANGLE SEALID == 0" |
| SETLAYER dieEdgePerp = "ANGLE SEALID == 90" |
| SETLAYER dieEdgeHorizSz = "EXPAND EDGE dieEdgeHoriz OUTSIDE BY 0.005" |
| SETLAYER dieEdgePerpSz = "EXPAND EDGE dieEdgePerp OUTSIDE BY 0.005" |
| SETLAYER dieEdgeH = "dieEdgeHorizSz COINCIDENT EDGE sealid_hole" |
| SETLAYER dieEdgeP = "dieEdgePerpSz COINCIDENT EDGE sealid_hole" |
| SETLAYER hoizXaxis = "COPY 4006" |
| SETLAYER perpXaxis = "COPY 4007" |
| SETLAYER padNoSEAL = "pad NOT SEALID" |
| SETLAYER dieEdgStepH41 = "EXPAND EDGE dieEdgeH INSIDE by 41" |
| SETLAYER dieEdgStepHpad41 = "(INTERACT padNoSEAL (padNoSEAL AND dieEdgStepH41)) NOT perpXaxis" |
| SETLAYER allHorizX41 = "hoizXaxis OR dieEdgStepHpad41" |
| SETLAYER dieEdgStepP41 = "EXPAND EDGE dieEdgeP INSIDE by 41" |
| SETLAYER dieEdgStepPpad41 = "(INTERACT padNoSEAL (padNoSEAL AND dieEdgStepP41)) NOT dieEdgStepHpad41" |
| SETLAYER allPerpX41 = "perpXaxis OR dieEdgStepPpad41" |
| SETLAYER newSetPad41 = "padNoSEAL NOT (dieEdgStepHpad41 OR dieEdgStepPpad41)" |
| SETLAYER cornerPads41 = "(INTERACT padNoSEAL (padNoSEAL AND dieEdgStepH41)) AND (INTERACT padNoSEAL (padNoSEAL AND dieEdgStepP41))" |
| SETLAYER horzAndCornPad = "dieEdgStepH41 AND cornerPads41" |
| SETLAYER vertAndCornPad = "dieEdgStepP41 AND cornerPads41" |
| SETLAYER padEdgeHorzErr = " EXTERNAL padCenter horzAndCornPad < 60.0 ABUT < 90 PARALLEL OPPOSITE" |
| SETLAYER padEdgeVertErr = " EXTERNAL padCenter vertAndCornPad < 60.0 ABUT < 90 PARALLEL OPPOSITE" |
| |
| # JAG 5/17/21 removed use of DFM commands for licensing simplification: |
| #SETLAYER dfmVertXedge = "DFM PROPERTY cornerPads41 padEdgeHorzErr padEdgeVertErr OVERLAP \[edgeCheck =MIN(EW(padEdgeHorzErr))-MIN(EW(padEdgeVertErr))\]>0" |
| #SETLAYER dfmHorzXedge = "DFM PROPERTY cornerPads41 padEdgeHorzErr padEdgeVertErr OVERLAP \[edgeCheck =MIN(EW(padEdgeVertErr))-MIN(EW(padEdgeHorzErr))\]>0" |
| SETLAYER pad_length_ang_0 = "ANGLE (cornerPads41 AND pad_length) == 0" |
| SETLAYER pad_length_ang_90 = "ANGLE (cornerPads41 AND pad_length) == 90" |
| SETLAYER dfmVertXedge = "cornerPads41 ENCLOSE (EXPAND EDGE pad_length_ang_90 OUTSIDE by 0.2)" |
| SETLAYER dfmHorzXedge = "cornerPads41 ENCLOSE (EXPAND EDGE pad_length_ang_0 OUTSIDE by 0.2)" |
| |
| SETLAYER dieEdgStepH82 = "EXPAND EDGE dieEdgeH INSIDE by 82" |
| SETLAYER dieEdgStepHpad82 = "(INTERACT padNoSEAL (padNoSEAL AND dieEdgStepH82)) NOT allPerpX41" |
| SETLAYER allHorizX82 = "allHorizX41 OR dieEdgStepHpad82" |
| SETLAYER dieEdgStepP82 = "EXPAND EDGE dieEdgeP INSIDE by 82" |
| SETLAYER dieEdgStepPpad82 = "(INTERACT padNoSEAL (padNoSEAL AND dieEdgStepP82)) NOT dieEdgStepHpad82" |
| SETLAYER allPerpX82 = "allPerpX41 OR dieEdgStepPpad82" |
| SETLAYER newSetPad82 = "padNoSEAL NOT (dieEdgStepHpad82 OR dieEdgStepPpad82)" |
| SETLAYER dieEdgStepH123 = "EXPAND EDGE dieEdgeH INSIDE by 123" |
| SETLAYER dieEdgStepHpad123 = "(INTERACT padNoSEAL (padNoSEAL AND dieEdgStepH123)) NOT allPerpX82" |
| SETLAYER allHorizX123 = "allHorizX82 OR dieEdgStepHpad123" |
| SETLAYER dieEdgStepP123 = "EXPAND EDGE dieEdgeP INSIDE by 123" |
| SETLAYER dieEdgStepPpad123 = "(INTERACT padNoSEAL (padNoSEAL AND dieEdgStepP123)) NOT dieEdgStepHpad123" |
| SETLAYER allPerpX123 = "allPerpX82 OR dieEdgStepPpad123" |
| SETLAYER newSetPad123 = "padNoSEAL NOT (dieEdgStepHpad123 OR dieEdgStepPpad123)" |
| SETLAYER dieEdgStepH164 = "EXPAND EDGE dieEdgeH INSIDE by 164" |
| SETLAYER dieEdgStepHpad164 = "(INTERACT padNoSEAL (padNoSEAL AND dieEdgStepH164)) NOT allPerpX123" |
| SETLAYER allHorizX164 = "allHorizX123 OR dieEdgStepHpad164" |
| SETLAYER dieEdgStepP164 = "EXPAND EDGE dieEdgeP INSIDE by 164" |
| SETLAYER dieEdgStepPpad164 = "(INTERACT padNoSEAL (padNoSEAL AND dieEdgStepP164)) NOT dieEdgStepHpad164" |
| SETLAYER allPerpX164 = "allPerpX123 OR dieEdgStepPpad164" |
| SETLAYER newSetPad164 = "padNoSEAL NOT (dieEdgStepHpad164 OR dieEdgStepPpad164)" |
| SETLAYER dieEdgStepH205 = "EXPAND EDGE dieEdgeH INSIDE by 205" |
| SETLAYER dieEdgStepHpad205 = "(INTERACT padNoSEAL (padNoSEAL AND dieEdgStepH205)) NOT allPerpX164" |
| SETLAYER allHorizX205 = "allHorizX164 OR dieEdgStepHpad205" |
| SETLAYER dieEdgStepP205 = "EXPAND EDGE dieEdgeP INSIDE by 205" |
| SETLAYER dieEdgStepPpad205 = "(INTERACT padNoSEAL (padNoSEAL AND dieEdgStepP205)) NOT dieEdgStepHpad205" |
| SETLAYER allPerpX205 = "allPerpX164 OR dieEdgStepPpad205" |
| SETLAYER newSetPad205 = "padNoSEAL NOT (dieEdgStepHpad205 OR dieEdgStepPpad205)" |
| SETLAYER dieEdgStepH246 = "EXPAND EDGE dieEdgeH INSIDE by 246" |
| SETLAYER dieEdgStepHpad246 = "(INTERACT padNoSEAL (padNoSEAL AND dieEdgStepH246)) NOT allPerpX205" |
| SETLAYER allHorizX246 = "allHorizX205 OR dieEdgStepHpad246" |
| SETLAYER dieEdgStepP246 = "EXPAND EDGE dieEdgeP INSIDE by 246" |
| SETLAYER dieEdgStepPpad246 = "(INTERACT padNoSEAL (padNoSEAL AND dieEdgStepP246)) NOT dieEdgStepHpad246" |
| SETLAYER allPerpX246 = "allPerpX205 OR dieEdgStepPpad246" |
| SETLAYER newSetPad246 = "padNoSEAL NOT (dieEdgStepHpad246 OR dieEdgStepPpad246)" |
| SETLAYER dieEdgStepH287 = "EXPAND EDGE dieEdgeH INSIDE by 287" |
| SETLAYER dieEdgStepHpad287 = "(INTERACT padNoSEAL (padNoSEAL AND dieEdgStepH287)) NOT allPerpX246" |
| SETLAYER allHorizX287 = "allHorizX246 OR dieEdgStepHpad287" |
| SETLAYER dieEdgStepP287 = "EXPAND EDGE dieEdgeP INSIDE by 287" |
| SETLAYER dieEdgStepPpad287 = "(INTERACT padNoSEAL (padNoSEAL AND dieEdgStepP287)) NOT dieEdgStepHpad287" |
| SETLAYER allPerpX287 = "allPerpX246 OR dieEdgStepPpad287" |
| SETLAYER newSetPad287 = "padNoSEAL NOT (dieEdgStepHpad287 OR dieEdgStepPpad287)" |
| SETLAYER dieEdgStepH328 = "EXPAND EDGE dieEdgeH INSIDE by 328" |
| SETLAYER dieEdgStepHpad328 = "(INTERACT padNoSEAL (padNoSEAL AND dieEdgStepH328)) NOT allPerpX287" |
| SETLAYER allHorizX328 = "allHorizX287 OR dieEdgStepHpad328" |
| SETLAYER dieEdgStepP328 = "EXPAND EDGE dieEdgeP INSIDE by 328" |
| SETLAYER dieEdgStepPpad328 = "(INTERACT padNoSEAL (padNoSEAL AND dieEdgStepP328)) NOT dieEdgStepHpad328" |
| SETLAYER allPerpX328 = "allPerpX287 OR dieEdgStepPpad328" |
| SETLAYER newSetPad328 = "padNoSEAL NOT (dieEdgStepHpad328 OR dieEdgStepPpad328)" |
| SETLAYER dieEdgStepH369 = "EXPAND EDGE dieEdgeH INSIDE by 369" |
| SETLAYER dieEdgStepHpad369 = "(INTERACT padNoSEAL (padNoSEAL AND dieEdgStepH369)) NOT allPerpX328" |
| SETLAYER allHorizX369 = "allHorizX328 OR dieEdgStepHpad369" |
| SETLAYER dieEdgStepP369 = "EXPAND EDGE dieEdgeP INSIDE by 369" |
| SETLAYER dieEdgStepPpad369 = "(INTERACT padNoSEAL (padNoSEAL AND dieEdgStepP369)) NOT dieEdgStepHpad369" |
| SETLAYER allPerpX369 = "allPerpX328 OR dieEdgStepPpad369" |
| SETLAYER newSetPad369 = "padNoSEAL NOT (dieEdgStepHpad369 OR dieEdgStepPpad369)" |
| SETLAYER dieEdgStepH410 = "EXPAND EDGE dieEdgeH INSIDE by 410" |
| SETLAYER dieEdgStepHpad410 = "(INTERACT padNoSEAL (padNoSEAL AND dieEdgStepH410)) NOT allPerpX369" |
| SETLAYER allHorizX410 = "allHorizX369 OR dieEdgStepHpad410" |
| SETLAYER dieEdgStepP410 = "EXPAND EDGE dieEdgeP INSIDE by 410" |
| SETLAYER dieEdgStepPpad410 = "(INTERACT padNoSEAL (padNoSEAL AND dieEdgStepP410)) NOT dieEdgStepHpad410" |
| SETLAYER allPerpX410 = "allPerpX369 OR dieEdgStepPpad410" |
| SETLAYER newSetPad410 = "padNoSEAL NOT (dieEdgStepHpad410 OR dieEdgStepPpad410)" |
| SETLAYER dieEdgStepH451 = "EXPAND EDGE dieEdgeH INSIDE by 451" |
| SETLAYER dieEdgStepHpad451 = "(INTERACT padNoSEAL (padNoSEAL AND dieEdgStepH451)) NOT allPerpX410" |
| SETLAYER allHorizX451 = "allHorizX410 OR dieEdgStepHpad451" |
| SETLAYER dieEdgStepP451 = "EXPAND EDGE dieEdgeP INSIDE by 451" |
| SETLAYER dieEdgStepPpad451 = "(INTERACT padNoSEAL (padNoSEAL AND dieEdgStepP451)) NOT dieEdgStepHpad451" |
| SETLAYER allPerpX451 = "allPerpX410 OR dieEdgStepPpad451" |
| SETLAYER newSetPad451 = "padNoSEAL NOT (dieEdgStepHpad451 OR dieEdgStepPpad451)" |
| SETLAYER dieEdgStepH492 = "EXPAND EDGE dieEdgeH INSIDE by 492" |
| SETLAYER dieEdgStepHpad492 = "(INTERACT padNoSEAL (padNoSEAL AND dieEdgStepH492)) NOT allPerpX451" |
| SETLAYER allHorizX492 = "allHorizX451 OR dieEdgStepHpad492" |
| SETLAYER dieEdgStepP492 = "EXPAND EDGE dieEdgeP INSIDE by 492" |
| SETLAYER dieEdgStepPpad492 = "(INTERACT padNoSEAL (padNoSEAL AND dieEdgStepP492)) NOT dieEdgStepHpad492" |
| SETLAYER allPerpX492 = "allPerpX451 OR dieEdgStepPpad492" |
| SETLAYER newSetPad492 = "padNoSEAL NOT (dieEdgStepHpad492 OR dieEdgStepPpad492)" |
| SETLAYER dieEdgStepH533 = "EXPAND EDGE dieEdgeH INSIDE by 533" |
| SETLAYER dieEdgStepHpad533 = "(INTERACT padNoSEAL (padNoSEAL AND dieEdgStepH533)) NOT allPerpX492" |
| SETLAYER allHorizX533 = "allHorizX492 OR dieEdgStepHpad533" |
| SETLAYER dieEdgStepP533 = "EXPAND EDGE dieEdgeP INSIDE by 533" |
| SETLAYER dieEdgStepPpad533 = "(INTERACT padNoSEAL (padNoSEAL AND dieEdgStepP533)) NOT dieEdgStepHpad533" |
| SETLAYER allPerpX533 = "allPerpX492 OR dieEdgStepPpad533" |
| SETLAYER newSetPad533 = "padNoSEAL NOT (dieEdgStepHpad533 OR dieEdgStepPpad533)" |
| SETLAYER padXorg = "COPY allHorizX533" |
| SETLAYER padYorg = "COPY allPerpX533" |
| SETLAYER padCornerXtmp = "COPY dfmHorzXedge" |
| SETLAYER padCornerYtmp = "COPY dfmVertXedge" |
| SETLAYER padCornXpitchPadX = "EXPAND EDGE (ANGLE padCornerXtmp == 90) OUTSIDE BY 7" |
| SETLAYER padCornXpitchPadY = "EXPAND EDGE (ANGLE padCornerXtmp == 0) OUTSIDE BY 7" |
| SETLAYER padCornXtouchPitchInY = "TOUCH padCornXpitchPadY pad == 2" |
| SETLAYER padCornXtouchPitchInX = "TOUCH padCornXpitchPadX pad == 2" |
| SETLAYER padCornerSwapxtoY = "NOT TOUCH (TOUCH padCornerXtmp padCornXtouchPitchInY) padCornXtouchPitchInX" |
| SETLAYER padCornerX = "(padCornerXtmp OR padCornerSwapYtoX) NOT padCornerSwapXtoY" |
| SETLAYER padCornYpitchPadY = "EXPAND EDGE (ANGLE padCornerYtmp == 90) OUTSIDE BY 7" |
| SETLAYER padCornYpitchPadX = "EXPAND EDGE (ANGLE padCornerYtmp == 0) OUTSIDE BY 7" |
| SETLAYER padCornYtouchPitchInY = "TOUCH padCornYpitchPadY pad == 2" |
| SETLAYER padCornYtouchPitchInX = "TOUCH padCornYpitchPadX pad == 2" |
| SETLAYER padCornerSwapYtoX = "NOT TOUCH (TOUCH padCornerYtmp padCornYtouchPitchInY) padCornYtouchPitchInX" |
| SETLAYER padCornerY = "(padCornerYtmp OR padCornerSwapXtoY) NOT padCornerSwapYtoX" |
| SETLAYER padX = "(padXorg OR padCornerX) NOT padCornerY" |
| #Removed by ddDeleteObj: DEFINE s130_test_AG_lib /home/jgreene/projects/proj5/s130_test_AG_lib |
| SETLAYER padY = "(padYorg OR padCornerY) NOT padCornerX" |
| SETLAYER minSpacepadYedges = "EXPAND EDGE (ANGLE padY == 0) INSIDE BY 0.005" |
| SETLAYER minSpacepadYyEdge = "EXPAND EDGE (ANGLE padY == 90) INSIDE BY 0.005" |
| SETLAYER minSpacepadXedges = "EXPAND EDGE (ANGLE padX == 90) INSIDE BY 0.005" |
| SETLAYER minSpacepadXyEdge = "EXPAND EDGE (ANGLE padX == 0) INSIDE BY 0.005" |
| SETLAYER laser_targetCells = "EXTENT CELL \"lazX_*\" \"lazY_*\" ORIGINAL" |
| SETLAYER BONDPAD = "pad OUTSIDE (OR SEALID fuse FRAMEID laser_targetCells)" |
| SETLAYER padInInd = "pad AND inductor" |
| # JAG 5/20/21 removed M5RDL via exemption per PM: |
| #SETLAYER viapcell = "EXTENT CELL \"M5RDL*\" ORIGINAL" |
| SETLAYER bondpadPcell_0 = "(EXTENT CELL \"padPL*\" ORIGINAL) OR bondpadCuPillar" |
| SETLAYER bondpadPcell_1 = "EXTENT CELL \"pad_bond*\" ORIGINAL" |
| SETLAYER bondpadPcell_2 = "EXTENT CELL \"pad_microprobe*\" ORIGINAL" |
| SETLAYER bondpadPcell_3 = "EXTENT CELL \"pad_probe*\" ORIGINAL" |
| SETLAYER bondpadPcell = "OR bondpadPcell_0 bondpadPcell_1 bondpadPcell_2 bondpadPcell_3" |
| SETLAYER plasticPackPad = "WITH TEXT bondpadPcell \"plastic\" textdraw" |
| SETLAYER hermeticPackPad = "WITH TEXT bondpadPcell \"hermetic\" textdraw" |
| SETLAYER PadPLhp = "WITH TEXT BONDPAD \"HP\" textdraw" |
| SETLAYER PadPLfp = "WITH TEXT BONDPAD \"FP\" textdraw" |
| SETLAYER PadPLstg = "WITH TEXT BONDPAD \"STG\" textdraw" |
| SETLAYER PadPLwlbi = "WITH TEXT BONDPAD \"WLBI\" textdraw" |
| |
| SETLAYER bondpadCuPillar = "EXTENT CELL \"s8fpafeg1_io_amkor_pad*\" \"fpg1_amkor_39x39_pad*\" ORIGINAL" |
| SETLAYER notValidbondPad = "BONDPAD NOT (padInInd OR (bondpadPcell OR bondpadCuPillar))" |
| SETLAYER bondpadPcellNoText = "bondpadPcell NOT plasticPackPad" |
| SETLAYER anyPadPlastic = "pad AND plasticPackPad" |
| |
| # pad.1 |
| RULECHECK pad.CON.1 { |
| @ pad.CON.1: pad pcells should be used for bondpad |
| OUTPUT "COPY notValidbondPad" |
| } |
| |
| # removed 9/10/20 JAG |
| #RULECHECK pad.CON.2 { |
| #@ pad.CON.2: pad pcells should have text plastic to be used for bondpad |
| # OUTPUT "COPY bondpadPcellNoText" |
| # } |
| |
| #pad.16 |
| RULECHECK pad.CON.3 { |
| @ pad.CON.3: Hermetic package pads are not supported in this flow |
| OUTPUT "COPY hermeticPackPad" |
| } |
| |
| SETLAYER bondpadNormal = "BONDPAD AND bondpadPcell" |
| SETLAYER bondpadNormalPlastic = "BONDPAD AND plasticPackPad" |
| #high pitch: |
| SETLAYER bondpadHP = "BONDPAD AND PadPLhp" |
| #fine pitch: |
| SETLAYER bondpadFP = "BONDPAD AND PadPLfp" |
| #staggered: |
| SETLAYER bondpadSTG = "BONDPAD AND PadPLstg" |
| # wafer level burrn-in: |
| SETLAYER bondpadWLBI = "BONDPAD AND PadPLwlbi" |
| |
| SETLAYER pad_in_bond = "pad AND ((met5 ENCLOSE pad) INTERACT met4)" |
| SETLAYER probe_pad = "WITH TEXT pad \"e-test\"" |
| SETLAYER uprobe_pad = "WITH TEXT pad \"u-test\"" |
| # pad.4 |
| RULECHECK pad.ENC.1 { |
| @ pad.ENC.1: Min. enclosure of normal bond pad by met5 < 0.27 |
| OUTPUT "ENC (pad_in_bond NOT (OR probe_pad uprobe_pad)) met5 < 2.7 MEASURE ALL ABUT < 90 SINGULAR REGION" |
| } |
| |
| SETLAYER met4_ring = "DONUT (met4 INTERACT pad_in_bond)" |
| # pad.5 |
| # SETLAYER met4_err_ringSpc = "met4_ring INTERACT (met4_ring AND pad_in_bond)" |
| |
| #pad.5 |
| RULECHECK pad.SP.1 { |
| @ pad.SP.1: Metal4 ring in bond pad must be coincident and outside pad layer of pad cell |
| #OUTPUT "COPY met4_err_ringSpc" |
| OUTPUT "met4_ring INTERACT (met4_ring AND pad_in_bond)" |
| } |
| |
| SETLAYER bondpadEdges = "BONDPAD COINCIDENT EDGE (minSpacepadXedges OR minSpacepadYedges)" |
| SETLAYER bondpadEdgesSz = "EXPAND EDGE bondpadEdges INSIDE BY 30" |
| SETLAYER bondpadEdgesSide = "EXPAND EDGE (LENGTH (bondpadEdgesSz INSIDE EDGE BONDPAD) <= 60.0 > (60.0 / 2.0)) INSIDE BY 0.005" |
| SETLAYER SmallBondPad = "BONDPAD INTERACT bondpadEdgesSide" |
| SETLAYER LargeBondPad = "BONDPAD NOT SmallBondPad" |
| SETLAYER padGroupingY = "(BONDPAD INTERACT (BONDPAD AND (padCenter AND padCenterDieY))) OR padCenterDieY" |
| SETLAYER smallGroupingY = "(INTERACT padGroupingY (padGroupingY AND (padCenter AND SmallBondPad))) AND BONDPAD" |
| SETLAYER largeGroupingY = "(padGroupingY NOT smallGroupingY) AND BONDPAD" |
| SETLAYER padGroupingX = "(INTERACT BONDPAD (BONDPAD AND (padCenter AND padCenterDieX))) OR padCenterDieX" |
| SETLAYER smallGroupingX = "(INTERACT padGroupingX (padGroupingX AND (padCenter AND SmallBondPad))) AND BONDPAD" |
| SETLAYER largeGroupingX = "(padGroupingX NOT smallGroupingX) AND BONDPAD" |
| |
| SETLAYER met4OutsidePad = "met4 OUTSIDE bondPadPcell" |
| SETLAYER met5OutsidePad = "met5 OUTSIDE bondPadPcell" |
| |
| # pad.6 |
| RULECHECK pad.SP.2 { |
| @ pad.SP.2: Min. spacing of pad opening inside a group of small bondpads in the Y direction to met4/5 outside the bond pad < 5.0 |
| @ if at least one pad opening across the chip in x-direction is <= 60um |
| OUTPUT "EXT smallGroupingY met5OutsidePad < 5.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| OUTPUT "EXT smallGroupingY met4OutsidePad < 5.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| # pad.7 |
| RULECHECK pad.SP.3 { |
| @ pad.SP.3: Min. spacing of pad opening of inside a group of large bondpads in the Y direction met4/5 outside the bond pad < 10.0 |
| @ if at least one pad opening across the chip in x-direction is > 60um |
| OUTPUT "EXT largeGroupingY met5OutsidePad < 10.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| OUTPUT "EXT largeGroupingY met4OutsidePad < 10.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| # pad.6 |
| RULECHECK pad.SP.4 { |
| @ pad.SP.4: Min. spacing of pad opening of small bondpads in the X direction to met4/5 outside the bond pad < 5.0 |
| @ if at least one pad opening across the chip in x-direction is <= 60um |
| OUTPUT "EXT smallGroupingX met5OutsidePad < 5.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| OUTPUT "EXT smallGroupingX met4OutsidePad < 5.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| # pad.7 |
| RULECHECK pad.SP.5 { |
| @ pad.SP.5: Min. spacing of pad opening inside a group of large bondpads in the X direction to met4/5 outside the bond pad < 10.0 |
| @ if at least one pad opening across the chip in x-direction is > 60um |
| OUTPUT "EXT largeGroupingX met5OutsidePad < 10.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| OUTPUT "EXT largeGroupingX met4OutsidePad < 10.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| SETLAYER bondpadNormalprobe = "WITH TEXT bondpadNormalPlastic \"probe-only\" textdraw" |
| SETLAYER bondpadNormalNoprobe = "bondpadNormalPlastic NOT (cuPillarPadText OR bondpadNormalprobe)" |
| |
| # pad.10 |
| RULECHECK pad.OVL.1 { |
| @ pad.OVL.1: Normal pad opening (not probe) must not overlap met4 |
| OUTPUT "bondpadNormalNoprobe AND met4" |
| } |
| |
| SETLAYER bp_outl1 = "EXPAND EDGE (pad NOT INTERACT (OR uprobe_pad probe_pad)) OUTSIDE BY 0.05" |
| SETLAYER bp_outl = "(pad NOT INTERACT (uprobe_pad OR probe_pad)) COINCIDENT OUTSIDE EDGE bp_outl1" |
| SETLAYER bondpad_45_edges = "ANGLE bp_outl == 45" |
| SETLAYER bondpad_90_edges = "NOT ANGLE bp_outl == 45" |
| SETLAYER bondpad_corner = "INT pad_squared_off < 10 ABUT==90 REGION" |
| |
| #pad.11 |
| RULECHECK pad.CON.4 { |
| @ pad.CON.4: Bondpad should not have 90 degree corner |
| OUTPUT "SIZE (INT bondpadNormalPlastic < 0.005 ABUT == 90 INTERSECTING REGION) BY 0.5 INSIDE OF pad" |
| } |
| |
| #pad.11 |
| RULECHECK pad.CON.5 { |
| @ pad.CON.5: Bondpad missing 45 degree corner |
| OUTPUT "bondpad_corner NOT INTERACT (EXPAND EDGE bondpad_45_edges OUTSIDE BY 0.05)" |
| } |
| |
| #pad.11 |
| RULECHECK pad.CON.6 { |
| @ pad.CON.6: Bondpad does not have 4 chamferred 45 degree corners |
| OUTPUT "(pad NOT (OR uprobe_pad probe_pad)) NOT TOUCH (EXPAND EDGE bondpad_45_edges OUTSIDE BY 0.05) == 4" |
| } |
| |
| #pad.11 |
| RULECHECK pad.CON.7 { |
| @ pad.CON.7: Bondpad should have only 4 orthogonal edges |
| OUTPUT "(pad NOT (OR uprobe_pad probe_pad)) NOT TOUCH (EXPAND EDGE bondpad_90_edges OUTSIDE BY 0.05) == 4" |
| } |
| |
| #pad.12 |
| RULECHECK pad.LEN.1 { |
| @ pad.LEN.1: Min length of 45 degree bevel on Bond pad < 7.0 |
| OUTPUT "LENGTH bondpad_45_edges < 7" |
| } |
| |
| #pad.13 |
| RULECHECK pad.LEN.2 { |
| @ pad.LEN.2: Max length of 45 degree bevel on Bond pad > 8.8 |
| OUTPUT "LENGTH bondpad_45_edges > 8.8" |
| } |
| |
| SETLAYER solid_seal = "(HOLES SEALID) OR (DONUT SEALID)" |
| SETLAYER solid_seal_shrink = "SIZE solid_seal BY -500.0" |
| SETLAYER maxSpcPadSeal = "bondpadNormalPlastic WITH EDGE (bondpadNormalPlastic COINCIDENT INSIDE EDGE solid_seal_shrink)" |
| SETLAYER lessMaxSpcPadSeal = "CUT bondpadNormalPlastic solid_seal_shrink" |
| SETLAYER cuPillarPadText = "INTERACT pad (WITH TEXT pad \"CU-PILLAR-PAD\" textdraw)" |
| SETLAYER aupDummyPadText = "bondpadCuPillar INTERACT (WITH TEXT pad \"AUP-DUMMY-OK\" textdraw)" |
| # JAG 5/20/21 removed psoc4*_top, tsg5_m_tcg5_top exemption per PM: |
| #SETLAYER psoc4xmt = "EXTENT CELL \"psoc4*_top\" ORIGINAL" |
| #SETLAYER cadXmpt = "(EXTENT CELL \"tsg5_m_tcg5_top*\" ORIGINAL) OR (cuPillarPadText OR psoc4xmt)" |
| SETLAYER cadXmpt = "COPY cuPillarPadText" |
| SETLAYER err_pad_15 = "(bondpadNormalPlastic NOT (maxSpcPadSeal OR (lessMaxSpcPadSeal OR cadXmpt))) AND solid_seal_shrink" |
| |
| #pad.14 |
| RULECHECK pad.ENC.2 { |
| @ pad.ENC.2: Min. enclosure of any plastic pad by solid_seal < 16.99 |
| SETLAYER q0anyPadPlasticand = "anyPadPlastic AND solid_seal" |
| OUTPUT "ENCLOSURE q0anyPadPlasticand solid_seal < 16.99 MEASURE ALL ABUT < 90 SINGULAR REGION" |
| } |
| |
| #pad.15 |
| RULECHECK pad.SP.10 { |
| @ pad.SP.10: Max spacing between bondpad opening and edge of scribe line (outer end of seal ring) > 500.0 |
| OUTPUT "COPY err_pad_15" |
| } |
| |
| SETLAYER padMetal = "pad AND (bondPadPcell AND met5)" |
| SETLAYER met1Shield = "COPY 4008" |
| SETLAYER met1UndPadMet = "met1i INTERACT (met1i AND padMetal)" |
| SETLAYER met1UndPadMetOnly = "met1UndPadMet AND (BONDPAD NOT aupDummyPadText)" |
| SETLAYER met1UndPadMetMinW = "INTERNAL met1UndPadMetOnly < 0.14 PARALLEL OPPOSITE REGION" |
| |
| #pad.17 |
| RULECHECK pad.SP.11 { |
| @ pad.SP.11: Min. spacing/notch of met1 under pad metal < 1.5 |
| OUTPUT "EXTERNAL met1UndPadMetOnly < 1.5 ABUT < 90 SINGULAR REGION OPPOSITE" |
| } |
| |
| #pad.18 |
| RULECHECK pad.WID.1 { |
| @ pad.WID.1: Min width of met1 under pad metal < 0.14 |
| OUTPUT "COPY met1UndPadMetMinW" |
| } |
| |
| SETLAYER met2UndPadMet = "INTERACT met2 (met2 AND padMetal)" |
| SETLAYER met2UndPadMetOnly = "met2UndPadMet AND (BONDPAD NOT aupDummyPadText)" |
| SETLAYER met2UndPadMetMinW = "INTERNAL met2UndPadMetOnly < 0.14 PARALLEL OPPOSITE REGION" |
| |
| #pad.17 |
| RULECHECK pad.SP.12 { |
| @ pad.SP.12: Min. spacing/notch of met2 under pad metal < 1.5 |
| OUTPUT "EXTERNAL met2UndPadMetOnly < 1.5 ABUT < 90 SINGULAR REGION OPPOSITE" |
| } |
| |
| #pad.18 |
| RULECHECK pad.WID.2 { |
| @ pad.WID.2: Min width of met2 under pad metal < 0.14 |
| OUTPUT "COPY met2UndPadMetMinW" |
| } |
| |
| SETLAYER met3UndPadMet = "INTERACT met3 (met3 AND padMetal)" |
| SETLAYER met3UndPadMetOnly = "met3UndPadMet AND (BONDPAD NOT aupDummyPadText)" |
| SETLAYER met3UndPadMetMinW = "INTERNAL met3UndPadMetOnly < 0.3 PARALLEL OPPOSITE REGION" |
| |
| #pad.17 |
| RULECHECK pad.SP.13 { |
| @ pad.SP.13: Min. spacing/notch of met3 under pad metal < 1.5 |
| OUTPUT "EXTERNAL met3UndPadMetOnly < 1.5 ABUT < 90 SINGULAR REGION OPPOSITE" |
| } |
| |
| #pad.18 |
| RULECHECK pad.WID.3 { |
| @ pad.WID.3: Min width of met3 under pad metal < 0.3 |
| OUTPUT "COPY met3UndPadMetMinW" |
| } |
| |
| #pad.19 |
| RULECHECK pad.WID.4 { |
| @ pad.WID.4: Max width of met1 under pad metal > 25.0 |
| OUTPUT "WITH WIDTH ((met1 AND padMetal) NOT met1Shield) > 25.0" |
| } |
| |
| #pad.19 |
| RULECHECK pad.WID.5 { |
| @ pad.WID.5: Max width of met2 under pad metal > 25.0 |
| OUTPUT "WITH WIDTH ((met2 AND padMetal) NOT met1Shield) > 25.0" |
| } |
| |
| RULECHECK pad.SP.6 { |
| @ pad.SP.6: Min pad spacing < 1.27 |
| OUTPUT "EXT pad < 1.27 ABUT<90 REGION" |
| } |
| |
| #SETLAYER topmet = "met5 OR MM5mk" |
| #SETLAYER HugePDMmkW = "WITH WIDTH PDMmk > 100.0" |
| #SETLAYER HugePDMmkWsz = "SIZE HugePDMmkW BY 0.005 INSIDE OF PDMmk STEP 0.005" |
| #SETLAYER HugePDMmkA = "HugePDMmkWsz NOT HugePDMmkW" |
| #SETLAYER HugePDMmkB = "HugePDMmkA WITH EDGE (HugePDMmkA COINCIDENT OUTSIDE EDGE HugePDMmkW)" |
| #SETLAYER HugePDMmkC = "HugePDMmkB OR HugePDMmkW" |
| #SETLAYER HugePDMmkD = "SNAP HugePDMmkC 5" |
| #SETLAYER padNotMet3 = "HugePDMmkD NOT topmet" |
| |
| #RULECHECK pad.AR.1 { |
| #@ pad.AR.1 Maximum area of wide pad (width > 100um) not met5 > 30000 |
| #OUTPUT "AREA padNotMet3 > 30000.0" |
| #OUTPUT "AREA (pad WITH WIDTH > 100) > 30000.0" |
| #} |
| |
| # JAG 5/20/21 removed s8hpbtoolkit_dual_rx_2* exemption per PM: |
| #SETLAYER hpb_exemptions = "EXTENT CELL \"hpb_esdTriggerULB_b*\" \"s8hpbtoolkit_dual_rx_2*\" \"s8hpbtoolkit_dual_rx_inv*\" ORIGINAL" |
| SETLAYER hpb_exemptions = "EXTENT CELL \"hpb_esdTriggerULB_b*\" ORIGINAL" |
| # JAG 5/20/21 removed s8bio_top_biocmux_vccio* exemption per PM: |
| #SETLAYER ind_exemptions = "EXTENT CELL \"s8bio_top_biocmux_vccio*\" ORIGINAL" |
| # JAG 5/20/21 removed k2_east_pads_top* k2_west_pads_top* exemption per PM: |
| #SETLAYER k2_exemptions = "EXTENT CELL \"k2_east_pads_top*\" \"k2_west_pads_top*\" ORIGINAL" |
| # JAG 5/20/21 removed krypton* exemption per PM: |
| #SETLAYER kry_exemptions = "EXTENT CELL \"krypton_io_pframe*\" \"krypton2_toplevel\" ORIGINAL" |
| # JAG 5/20/21 removed leo* exemption per PM: |
| #SETLAYER leo_exemptons = "EXTENT CELL \"s8ppscio_top_vca_2*\" \"s8ppscio_top_vcd_2*\" \"s8ppscio_top_vda_2*\" \"s8ppscio_top_vdd_2*\" \"s8ppscio_top_vdd_3*\" \"s8ppscio_top_vddabuf*\" \"s8ppscio_top_vio*\" \"s8ppscio_top_vssa_2*\" \"s8ppscio_top_vssd_2*\" \"s8ppscio_top_vssio_2*\" \"s8ppscio_top_vssio_3*\" \"s8ppscio_top_vssio_2*\" \"s8ppscio_top_vssabuf*\" \"s8ppscio_top_vusb_2\" ORIGINAL" |
| # JAG 5/20/21 removed tsg* exemption per PM: |
| #SETLAYER tsg_exemptions = "EXTENT CELL \"s8esdg4_net_io_b*\" \"s8ppscio_top_vcd_2*\" \"s8ppscio_top_vdd_2*\" \"s8tsg4io_top_vio*\" \"s8tsg4io_top_vssd_2*\" \"s8tsg4io_top_vssio_2*\" \"s8tkm0s8_corner_tp2*\" ORIGINAL" |
| SETLAYER qspi_exemptions = "EXTENT CELL \"s8tnvsio18_io_top\" \"s8tnviso18_io_top_hv\" \"quadspinvsram_top*\" ORIGINAL" |
| #SETLAYER pad_19_exemptions = "OR hpb_exemptions ind_exemptions k2_exemptions kry_exemptions leo_exemptons tsg_exemptions qspi_exemptions" |
| SETLAYER pad_19_exemptions = "OR hpb_exemptions qspi_exemptions" |
| |
| #pad.19 |
| RULECHECK pad.WID.6 { |
| @ pad.WID.6: Max width of met3 under pad metal > 6.0 |
| OUTPUT "(WITH WIDTH (met3 AND padMetal) > 6.0) NOT pad_19_exemptions" |
| } |
| |
| SETLAYER padFPedgX = "bondpadFP COINCIDENT EDGE (minSpacepadXedges OR minSpacepadYedges)" |
| SETLAYER padFPedgXsz = "EXPAND EDGE padFPedgX INSIDE BY 30" |
| SETLAYER badFPwEdg = "LENGTH (padFPedgXsz NOT COINCIDENT EDGE padFPedgX) > 30.0 < 60.0" |
| SETLAYER badFPwEdgSz = "EXPAND EDGE badFPwEdg INSIDE BY 0.005" |
| SETLAYER badFPwidth = "INTERACT (bondpadFP NOT bondpadCuPillar) ((bondpadFP NOT bondpadCuPillar) AND (INTERACT (EXPAND EDGE padFPedgX INSIDE BY 0.005) ((EXPAND EDGE padFPedgX INSIDE BY 0.005) AND badFPwEdgSz) == 2))" |
| SETLAYER padFPedgY = "bondpadFP COINCIDENT EDGE (minSpacepadXyEdge OR minSpacepadYyedge)" |
| SETLAYER padFPedgYsz = "EXPAND EDGE padFPedgY INSIDE BY 30" |
| SETLAYER badFPlEdg = "LENGTH (padFPedgYsz NOT COINCIDENT EDGE padFPedgY) > 30.0 < 60.0" |
| SETLAYER badFPlEdgSz = "EXPAND EDGE badFPlEdg INSIDE BY 0.005" |
| SETLAYER badFPlength = "INTERACT (bondpadFP NOT bondpadCuPillar) ((bondpadFP NOT bondpadCuPillar) AND (INTERACT (EXPAND EDGE padFPedgY INSIDE BY 0.005) ((EXPAND EDGE padFPedgY INSIDE BY 0.005) AND badFPlEdgSz) == 2))" |
| SETLAYER padSTGedgX = "bondpadSTG COINCIDENT EDGE (minSpacepadXedges OR minSpacepadYedges)" |
| SETLAYER padSTGedgXsz = "EXPAND EDGE padSTGedgX INSIDE BY 30" |
| SETLAYER badSTGwEdg = "LENGTH (padSTGedgXsz NOT COINCIDENT EDGE padSTGedgX) > 30.0 < 60.0" |
| SETLAYER badSTGwEdgSz = "EXPAND EDGE badSTGwEdg INSIDE BY 0.005" |
| SETLAYER badSTGwidth = "INTERACT bondpadSTG (bondpadSTG AND (INTERACT (EXPAND EDGE padSTGedgX INSIDE BY 0.005) ((EXPAND EDGE padSTGedgX INSIDE BY 0.005) AND badSTGwEdgSz) == 2))" |
| SETLAYER padSTGedgY = "bondpadSTG COINCIDENT EDGE (minSpacepadXyEdge OR minSpacepadYyedge)" |
| SETLAYER padSTGedgYsz = "EXPAND EDGE padSTGedgY INSIDE BY 30" |
| SETLAYER badSTGlEdg = "LENGTH (padSTGedgYsz NOT COINCIDENT EDGE padSTGedgY) > 30.0 < 60.0" |
| SETLAYER badSTGlEdgSz = "EXPAND EDGE badSTGlEdg INSIDE BY 0.005" |
| SETLAYER badSTGlength = "INTERACT bondpadSTG (bondpadSTG AND (INTERACT (EXPAND EDGE padSTGedgY INSIDE BY 0.005) ((EXPAND EDGE padSTGedgY INSIDE BY 0.005) AND badSTGlEdgSz) == 2))" |
| SETLAYER psoc4cuCells = "EXTENT CELL \"psoc4*_top*\"" |
| SETLAYER bondpadHPcu = "bondpadHP AND psoc4cuCells" |
| SETLAYER bondpadHPorg = "bondpadHP NOT bondpadHPcu" |
| SETLAYER padHPedgX = "bondpadHPorg COINCIDENT EDGE (minSpacepadXedges OR minSpacepadYedges)" |
| SETLAYER padHPedgXsz = "EXPAND EDGE padHPedgX INSIDE BY 30" |
| SETLAYER badHPwEdg = "LENGTH (padHPedgXsz NOT COINCIDENT EDGE padHPedgX) > 30.0 < 60.0" |
| SETLAYER badHPwEdgSz = "EXPAND EDGE badHPwEdg INSIDE BY 0.005" |
| SETLAYER badHPwidth = "INTERACT bondpadHP (bondpadHP AND (INTERACT (EXPAND EDGE padHPedgX INSIDE BY 0.005) ((EXPAND EDGE padHPedgX INSIDE BY 0.005) AND badHPwEdgSz) == 2))" |
| SETLAYER padHPedgY = "bondpadHPorg COINCIDENT EDGE (minSpacepadXyEdge OR minSpacepadYyedge)" |
| SETLAYER padHPedgYsz = "EXPAND EDGE padHPedgY INSIDE BY 30" |
| SETLAYER badHPlEdg = "LENGTH (padHPedgYsz NOT COINCIDENT EDGE padHPedgY) > 30.0 < 60.0" |
| SETLAYER badHPlEdgSz = "EXPAND EDGE badHPlEdg INSIDE BY 0.005" |
| SETLAYER badHPlength = "INTERACT bondpadHP (bondpadHP AND (INTERACT (EXPAND EDGE padHPedgY INSIDE BY 0.005) ((EXPAND EDGE padHPedgY INSIDE BY 0.005) AND badHPlEdgSz) == 2))" |
| SETLAYER padHPcuedgX = "bondpadHPcu COINCIDENT EDGE (minSpacepadXedges OR minSpacepadYedges)" |
| SETLAYER padHPcuedgXsz = "EXPAND EDGE padHPcuedgX INSIDE BY 29" |
| SETLAYER badHPcuwEdg = "LENGTH (padHPcuedgXsz NOT COINCIDENT EDGE padHPcuedgX) > 29.0 < 58.0" |
| SETLAYER badHPcuwEdgSz = "EXPAND EDGE badHPcuwEdg INSIDE BY 0.005" |
| SETLAYER badHPcuwidth = "INTERACT (bondpadHPcu NOT bondpadHPcuSolo) ((bondpadHPcu NOT bondpadHPcuSolo) AND (INTERACT (EXPAND EDGE padHPcuedgX INSIDE BY 0.005) ((EXPAND EDGE padHPcuedgX INSIDE BY 0.005) AND badHPcuwEdgSz) == 2))" |
| SETLAYER padHPcuedgY = "bondpadHPcu COINCIDENT EDGE (minSpacepadXyEdge OR minSpacepadYyedge)" |
| SETLAYER padHPcuedgYsz = "EXPAND EDGE padHPcuedgY INSIDE BY 30" |
| SETLAYER badHPculEdg = "LENGTH (padHPcuedgYsz NOT COINCIDENT EDGE padHPcuedgY) > 30.0 < 60.0" |
| SETLAYER badHPculEdgSz = "EXPAND EDGE badHPculEdg INSIDE BY 0.005" |
| # JAG removed psoc4*_top exemption 5/20/21 per PM |
| # SETLAYER badHPculength = "INTERACT (bondpadHPcu NOT (psoc4xmt OR bondpadHPcuSolo)) ((bondpadHPcu NOT (psoc4xmt OR bondpadHPcuSolo)) AND (INTERACT (EXPAND EDGE padHPcuedgY INSIDE BY 0.005) ((EXPAND EDGE padHPcuedgY INSIDE BY 0.005) AND badHPculEdgSz) == 2))" |
| SETLAYER badHPculength = "INTERACT (bondpadHPcu NOT bondpadHPcuSolo) ((bondpadHPcu NOT bondpadHPcuSolo) AND (INTERACT (EXPAND EDGE padHPcuedgY INSIDE BY 0.005) ((EXPAND EDGE padHPcuedgY INSIDE BY 0.005) AND badHPculEdgSz) == 2))" |
| SETLAYER bondpadHPcuSz = "SIZE bondPadHPcu BY (50.0 / 2)" |
| SETLAYER bondpadHPcuSolo = "bondpadHPcu AND (INTERACT bondpadHPcuSz bondpadHPcu == 1)" |
| SETLAYER bondpadHPcuSoloSz = "SIZE bondPadHPcuSolo BY 10 UNDEROVER" |
| SETLAYER badHPcuSoloWL = "NOT RECTANGLE bondpadHPcuSoloSz >= 58.0 BY >= 60.0" |
| SETLAYER padWLBIedgX = "bondpadWLBI COINCIDENT EDGE (minSpacepadXedges OR minSpacepadYedges)" |
| SETLAYER padWLBIedgXsz = "EXPAND EDGE padWLBIedgX INSIDE BY 25" |
| SETLAYER badWLBIwEdg = "LENGTH (padWLBIedgXsz NOT COINCIDENT EDGE padWLBIedgX) > 25.0 < 50.0" |
| SETLAYER badWLBIwEdgSz = "EXPAND EDGE badWLBIwEdg INSIDE BY 0.005" |
| SETLAYER badWLBIwidth = "INTERACT bondpadWLBI (bondpadWLBI AND (INTERACT (EXPAND EDGE padWLBIedgX INSIDE BY 0.005) ((EXPAND EDGE padWLBIedgX INSIDE BY 0.005) AND badWLBIwEdgSz) == 2))" |
| SETLAYER padWLBIedgY = "bondpadWLBI COINCIDENT EDGE (minSpacepadXyEdge OR minSpacepadYyedge)" |
| SETLAYER padWLBIedgYsz = "EXPAND EDGE padWLBIedgY INSIDE BY 30" |
| SETLAYER badWLBIlEdg = "LENGTH (padWLBIedgYsz NOT COINCIDENT EDGE padWLBIedgY) > 30.0 < 60.0" |
| SETLAYER badWLBIlEdgSz = "EXPAND EDGE badWLBIlEdg INSIDE BY 0.005" |
| SETLAYER badWLBIlength = "INTERACT bondpadWLBI (bondpadWLBI AND (INTERACT (EXPAND EDGE padWLBIedgY INSIDE BY 0.005) ((EXPAND EDGE padWLBIedgY INSIDE BY 0.005) AND badWLBIlEdgSz) == 2))" |
| |
| # JAG 7/9/20 added padCenter definition replacing previously drawn pad center |
| # polygon: |
| SETLAYER pad_squared_off = "SIZE (BONDPAD NOT INTERACT (OR uprobe_pad probe_pad)) BY 10 UNDEROVER" |
| SETLAYER pad_ctr_cross = "INT pad_squared_off < 150 ABUT<90 OPPOSITE PARALLEL REGION CENTERLINE 1" |
| SETLAYER pad_ctr_box = "pad_ctr_cross NOT (INT pad_ctr_cross < 1.005 ABUT<90 OPPOSITE PARALLEL REGION)" |
| SETLAYER padCenter = "EXTENTS pad CENTERS 0.2" |
| |
| SETLAYER pad_cross_not_ctr = "pad_ctr_cross NOT pad_ctr_box" |
| SETLAYER pad_cross_len = "(pad_cross_not_ctr INTERACT pad_length) OR pad_ctr_box" |
| SETLAYER pad_cross_wid = "(pad_cross_not_ctr NOT INTERACT pad_length) OR pad_ctr_box" |
| SETLAYER pad_cross_len_x = ANGLE (LENGTH pad_cross_len > 2) == 0 |
| SETLAYER pad_cross_len_y = ANGLE (LENGTH pad_cross_len > 2) == 90 |
| SETLAYER pad_cross_wid_x = ANGLE (LENGTH pad_cross_wid > 2) == 0 |
| SETLAYER pad_cross_wid_y = ANGLE (LENGTH pad_cross_wid > 2) == 90 |
| |
| # JAG WRT pad.20: based on met1Shield layer which will always be empty |
| # therefore not coded and no test structure. See Xena ticket 276 |
| |
| #pad.2.1 |
| #pad.3.1 |
| RULECHECK pad.WID.7 { |
| @ pad.WID.7: Min width of fine pitch pad in x direction < 60.0 |
| OUTPUT "LENGTH (pad_cross_len_x INSIDE EDGE bondpadFP) < 60" |
| } |
| |
| RULECHECK pad.LEN.3 { |
| @ pad.LEN.3: Min length of fine pitch pad in y direction < 60.0 |
| OUTPUT "LENGTH (pad_cross_len_y INSIDE EDGE bondpadFP) < 60" |
| } |
| |
| #pad.4.1 |
| #pad.5.1 |
| RULECHECK pad.WID.8 { |
| @ pad.WID.8: Min width of staggered pad in x direction < 60.0 |
| OUTPUT "LENGTH (pad_cross_len_x INSIDE EDGE bondpadSTG) < 60" |
| } |
| |
| RULECHECK pad.LEN.4 { |
| @ pad.LEN.4: Min length of staggered pad in y direction < 60.0 |
| OUTPUT "LENGTH (pad_cross_len_y INSIDE EDGE bondpadSTG) < 60" |
| } |
| |
| #pad.6.1 |
| RULECHECK pad.WID.9 { |
| @ pad.WID.9: Min width of high parallel pad in x direction < 60.0 |
| OUTPUT "LENGTH (pad_cross_len_x INSIDE EDGE bondpadHP) < 60" |
| } |
| |
| RULECHECK pad.LEN.5 { |
| @ pad.LEN.5: Min length of high parallel pad in y direction < 60.0 |
| OUTPUT "LENGTH (pad_cross_len_y INSIDE EDGE bondpadHP) < 60" |
| } |
| |
| # JAG pad.6.1a/6.1b? |
| SETLAYER isolated_pad_1 = "EXT pad < 50 ABUT<90 REGION" |
| SETLAYER isolated_pad = "pad NOT INTERACT isolated_pad_1" |
| SETLAYER non_iso_pad = "pad NOT isolated_pad" |
| SETLAYER isolated_pad_x = "EXPAND EDGE (pad_cross_len_x INSIDE EDGE non_iso_pad) OUTSIDE BY 0.05" |
| SETLAYER isolated_pad_y = "EXPAND EDGE (pad_cross_len_y INSIDE EDGE non_iso_pad) OUTSIDE BY 0.05" |
| |
| # psoc (PDR3) cypress part - ignore per Sam 7/10/20: |
| #RULECHECK pad.WID.15 { |
| # @ 59 min width of non-isolated pads in x-direction |
| # OUTPUT "LENGTH (pad_cross_len_x INSIDE EDGE non_iso_pad) < 59" |
| #} |
| |
| # psoc (PDR3) cypress part - ignore per Sam 7/10/20: |
| #RULECHECK pad.WID.16 { |
| # @ 60 min width of non-isolated pads in y-direction |
| # OUTPUT "LENGTH (pad_cross_wid_y INSIDE EDGE non_iso_pad) < 60" |
| #} |
| |
| # JAG 7/8/2020 cu pad not supported: |
| #RULECHECK pad.WID.10 { |
| # @ 58 min width of padPLHPcu in x direction |
| # OUTPUT "COPY badHPcuwidth" |
| # } |
| |
| #RULECHECK pad.LEN.6 { |
| # @ 60 min length of padPLHPcu in y direction |
| # OUTPUT "COPY badHPculength" |
| # } |
| |
| #RULECHECK pad.WID.11 { |
| # @ 58x60 min dimensions of padPLHPcu which are not within 50 of other pad |
| # OUTPUT "COPY badHPcuSoloWL" |
| # } |
| |
| #pad.7.1 |
| #pad.8.1 |
| RULECHECK pad.WID.12 { |
| @ pad.WID.12: Min width of wafer level burn-in pad in x direction < 50.0 |
| OUTPUT "LENGTH (pad_cross_len_x INSIDE EDGE bondpadWLBI) < 50" |
| } |
| |
| RULECHECK pad.LEN.7 { |
| @ pad.LEN.7: Min length of wafer level burn-in pad in y direction < 60.0 |
| OUTPUT "LENGTH (pad_cross_len_y INSIDE EDGE bondpadWLBI) < 60" |
| } |
| |
| # JAG 7/8/2020 cu pad not supported: |
| #SETLAYER bondpadCuPillarSz = "SIZE (pad AND bondpadCuPillar) UNDEROVER BY 10" |
| #SETLAYER q0bondpadCuPillarSz = "NOT RECTANGLE bondpadCuPillarSz ORTHOGONAL ONLY" |
| |
| #RULECHECK pad.CON.8 { |
| # @ bondpadCuPillarSz should be rectangular |
| # OUTPUT "COPY q0bondpadCuPillarSz" |
| # } |
| |
| #SETLAYER q1bondpadCuPillarSz = "INTERNAL bondpadCuPillarSz < 39.0 REGION" |
| |
| #RULECHECK pad.WID.13 { |
| # @ 39 min. width of bondpadCuPillarSz |
| # OUTPUT "COPY q1bondpadCuPillarSz" |
| # } |
| |
| #SETLAYER q2bondpadCuPillarSz = "bondpadCuPillarSz WITH EDGE (LENGTH bondpadCuPillarSz > 39.0)" |
| |
| #RULECHECK pad.LEN.8 { |
| # @ 39 max. length of bondpadCuPillarSz |
| # OUTPUT "COPY q2bondpadCuPillarSz" |
| # } |
| |
| #pad.1.2 |
| RULECHECK pad.SP.14 { |
| @ pad.SP.14: Min space of fine pitch pad in x direction to fine pitch, high pitch, staggered or wafer level burn_in in pad < 8.0 |
| OUTPUT "(EXT bondpadFP (OR bondpadFP bondpadHP bondpadSTG bondpadWLBI) < 8 ABUT<90 REGION OPPOSITE PARALLEL) INTERACT (EXPAND EDGE pad_cross_wid_x BY 0.1)" |
| } |
| |
| #pad.2.2 |
| RULECHECK pad.SP.15 { |
| @ pad.SP.15: Min space of high pitch pad in x direction to high pitch, staggered and wafer level burn in pad < 15.0 |
| OUTPUT "(EXT bondpadHP (OR bondpadHP bondpadSTG bondpadWLBI) < 15 ABUT<90 REGION OPPOSITE PARALLEL) INTERACT (EXPAND EDGE pad_cross_wid_x BY 0.1)" |
| } |
| |
| # JAG pad.2.2a? references PDR3 - Sam said to ignore 7/10/20 |
| |
| # JAG 7/8/2020 cu pad not supported: |
| #RULECHECK pad.SP.16 { |
| # @ 7 min space of padPLHPcu in x direction to padPLHPcu/STG/WLBI |
| # OUTPUT "COPY padHPspaceBadCu" |
| # } |
| |
| # JAG pad.2.2.1? |
| |
| #pad.3.2 |
| RULECHECK pad.SP.17 { |
| @ pad.SP.17: Min space of wafer level burn in pad in x direction to staggered or wafer level burn in pad < 50.0 |
| OUTPUT "(EXT bondpadWLBI (OR bondpadSTG bondpadWLBI) < 50 ABUT<90 REGION OPPOSITE PARALLEL) INTERACT (EXPAND EDGE pad_cross_wid_x BY 0.1)" |
| } |
| |
| #pad.4.2 |
| RULECHECK pad.SP.18 { |
| @ pad.SP.18: Min space of staggered pad in x direction < 30.0 |
| OUTPUT "(EXT bondpadSTG < 30 ABUT<90 REGION OPPOSITE PARALLEL) INTERACT (EXPAND EDGE pad_cross_wid_x BY 0.1)" |
| } |
| |
| RULECHECK pad.LEN.9 { |
| @ pad.LEN.9: Max width/length of bond pad > 150.0 |
| OUTPUT "LENGTH pad_squared_off > 150" |
| } |
| |
| SETLAYER padCenterAllX = "padCenter AND (BONDPAD AND padX)" |
| SETLAYER padCenterAllY = "padCenter AND (BONDPAD AND padY)" |
| SETLAYER padCenterAllxSz = "EXPAND EDGE (ANGLE padCenterAllX == 90) OUTSIDE BY 200000" |
| SETLAYER padCenterAllySz = "EXPAND EDGE (ANGLE padCenterAllY == 0) OUTSIDE BY 200000" |
| SETLAYER padCenterDieX = "(padCenterAllX OR padCenterAllxSz) AND solid_seal" |
| SETLAYER padCenterDieY = "(padCenterAllY OR padCenterAllySz) AND solid_seal" |
| SETLAYER padCenterinDieXw = "INTERNAL padCenterDieX == 0.2 ABUT < 90 OPPOSITE PARALLEL REGION" |
| SETLAYER padCenterinDieYw = "INTERNAL padCenterDieY == 0.2 ABUT < 90 OPPOSITE PARALLEL REGION" |
| SETLAYER padCenterinDieXsp = "EXTERNAL padCenterDieX < 9.0 ABUT < 90 SINGULAR REGION" |
| SETLAYER padCenterinDieYsp = "EXTERNAL padCenterDieY < 9.0 ABUT < 90 SINGULAR REGION" |
| SETLAYER padCenterinDieXwBad = "padCenterDieX NOT padCenterinDieXw" |
| SETLAYER padCenterinDieYwBad = "padCenterDieY NOT padCenterinDieYw" |
| SETLAYER padCenterinDieXspBad = "padCenterinDieXsp OR (INTERACT BONDPAD (BONDPAD AND (INTERACT padCenterAllX padCenterinDieXsp)))" |
| SETLAYER padCenterinDieYspBad = "padCenterinDieYsp OR (INTERACT BONDPAD (BONDPAD AND (INTERACT padCenterAllY padCenterinDieYsp)))" |
| SETLAYER padCenterSTGxySz = "EXPAND EDGE (ANGLE (bondpadSTG AND padCenterAllX) == 0) OUTSIDE BY 5000" |
| SETLAYER padCenterSTGyySz = "EXPAND EDGE (ANGLE (bondpadSTG AND padCenterAllY) == 90) OUTSIDE BY 5000" |
| SETLAYER padCenterSTGinDieXy = "(padCenterAllX OR padCenterSTGxySz) AND solid_seal" |
| SETLAYER padCenterSTGinDieYy = "(padCenterAllY OR padCenterSTGyySz) AND solid_seal" |
| |
| # JAG pad.5.2.1? |
| |
| #pad.6.2 |
| RULECHECK pad.SP.19 { |
| @ pad.SP.19: Min. pitch spacing of staggered pad (adjacent row) in X-direction < 40.0 |
| OUTPUT "(EXT (pad_ctr_box AND bondPadSTG) < 39 ABUT<90 REGION OPPOSITE PARALLEL) INTERACT (EXPAND EDGE pad_cross_len_x BY 0.1)" |
| } |
| |
| RULECHECK pad.SP.20 { |
| @ pad.SP.20: Min. pitch spacing of staggered pad (adjacent row) in Y-direction < 40.0 |
| |
| OUTPUT "(EXT (pad_ctr_box AND bondPadSTG) < 39 ABUT<90 REGION OPPOSITE PARALLEL) INTERACT (EXPAND EDGE pad_cross_len_y BY 0.1)" |
| } |
| |
| SETLAYER padCenterSTGxxSz = "EXPAND EDGE (ANGLE (bondpadSTG AND padCenterAllX) == 90) OUTSIDE BY 5000" |
| SETLAYER padCenterSTGinDieXx = "(padCenterAllX OR padCenterSTGxxSz) AND solid_seal" |
| SETLAYER padCenterinDieXspSTG = "EXTERNAL padCenterSTGinDieXx < 9.0 ABUT < 90 SINGULAR REGION" |
| SETLAYER padCenterinDieXspSTGGood = "padCenterSTGinDieXx NOT padCenterinDieXspSTG" |
| SETLAYER padSTGinDieXsp = "bondPadSTG INTERACT (bondPadSTG AND ((padCenterAllX AND bondPadSTG) INTERACT padCenterinDieXspSTGGood))" |
| |
| #pad.5.2.4 |
| RULECHECK pad.SP.21 { |
| @ pad.SP.21: Min. spacing of staggered pad in adjacent rows in y direction < 9.0 |
| OUTPUT "EXTERNAL padSTGinDieXsp bondPadSTG < 9.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| SETLAYER bondpadSTGscribe = "EXPAND EDGE padSTGedgX OUTSIDE BY 284" |
| SETLAYER bondpadFPscribe = "EXPAND EDGE padFPedgX OUTSIDE BY 200" |
| SETLAYER bondpadHPscribe = "EXPAND EDGE padHPedgX OUTSIDE BY 200" |
| SETLAYER bondpadWLBIscribe = "EXPAND EDGE padWLBIedgX OUTSIDE BY 200" |
| SETLAYER outsideSEALedge = "EXPAND EDGE (solid_seal COINCIDENT EDGE SEALID) OUTSIDE BY 0.005" |
| SETLAYER bondpadSTGscribeBad = "bondpadSTGscribe INTERACT (bondpadSTGscribe AND outsideSEALedge)" |
| SETLAYER bondpadFPscribeBad = "bondpadFPscribe INTERACT (bondpadFPscribe AND outsideSEALedge)" |
| SETLAYER bondpadHPscribeBad = "bondpadHPscribe INTERACT (bondpadHPscribe AND outsideSEALedge)" |
| SETLAYER bondpadWLBIscribeBad = "bondpadWLBIscribe INTERACT (bondpadWLBIscribe AND outsideSEALedge)" |
| |
| # pad.7.2.2 |
| RULECHECK pad.SP.22 { |
| @ pad.SP.22: Min space staggered pad opening to adj. scribe (outer edge of seal) in x direction < 200.0 |
| OUTPUT "COPY bondpadSTGscribeBad" |
| } |
| |
| RULECHECK pad.SP.23 { |
| @ pad.SP.23: Min space fine pitch pad opening to adj. scribe (outer edge of seal) < 200.0 |
| OUTPUT "COPY bondpadFPscribeBad" |
| } |
| |
| RULECHECK pad.SP.24 { |
| @ pad.SP.24: Min space of wafer level burn in pad opening in x direction to adj. scribe in x direction < 200.0 |
| OUTPUT "COPY bondpadWLBIscribeBad" |
| } |
| |
| SETLAYER pmmInInd = "pmm AND inductor" |
| |
| #cupad.1 |
| RULECHECK pad.WID.14 { |
| @ pad.WID.14: Min. width of pad opening inside inductor < 5.0 |
| OUTPUT "INT padInInd < 5.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| #cupad.2 |
| RULECHECK pad.ENC.3 { |
| @ pad.ENC.3: Min. enclosure of pad opening inside inductor by pmm is 0 |
| SETLAYER q0padInIndand = "padInInd AND pmm" |
| OUTPUT "padInInd NOT pmm" |
| } |
| |
| RULECHECK pad.CON.10 { |
| @ pad.CON.10: pad opening inside inductor must be enclosed by pmm |
| OUTPUT "padInInd NOT pmm" |
| } |
| |
| #cupad.3 |
| RULECHECK pad.ENC.4 { |
| @ pad.ENC.4: Min. enclosure of pad opening inside inductor by met5 < 2.7 |
| SETLAYER q1padInIndand = "padInInd AND met5" |
| OUTPUT "ENC q1padInIndand met5 < 2.7 MEASURE ALL ABUT < 90 SINGULAR REGION" |
| } |
| |
| RULECHECK pad.CON.11 { |
| @ pad.CON.11: pad opening inside inductor must be enclosed by met5 |
| OUTPUT "padInInd NOT met5" |
| } |
| |
| #cupad.4 |
| RULECHECK pad.ENC.5 { |
| @ pad.ENC.5: Min. enclosure of pmm inside inductor by rdl < 10.75 |
| SETLAYER q0pmmInIndand = "pmmInInd AND rdl" |
| OUTPUT "ENCLOSURE q0pmmInIndand rdl < 10.75 MEASURE ALL ABUT < 90 SINGULAR" |
| } |
| |
| RULECHECK pad.ENC.6 { |
| @ pad.ENC.6: pmm inside inductor must be enclosed by rdl |
| OUTPUT "pmmInInd NOT rdl" |
| } |
| |
| SETLAYER pad_power = "pad INTERACT pad_pwr" |
| SETLAYER pad_ground = "pad INTERACT pad_gnd" |
| SETLAYER pad_signal = "pad INTERACT pad_io" |
| |
| RULECHECK pad.CON.12 { |
| @ pad.CON.12: Only one layer areaid/pad_pwr, areaid/pad_io and/or areaid/pad_gnd can be used on a single pad |
| OUTPUT "(pad AND pad_power) AND pad_ground" |
| OUTPUT "(pad AND pad_power) AND pad_signal" |
| OUTPUT "(pad AND pad_ground) AND pad_signal" |
| OUTPUT "(pad AND pad_signal) AND pad_power" |
| OUTPUT "(pad AND pad_signal) AND pad_ground" |
| } |
| |
| RULECHECK pad.CON.13 { |
| @ pad.CON.13: Layers areaid/pad_pwr, areaid/pad_io and/or areaid/pad_gnd must be inside layer pad |
| OUTPUT "pad_gnd NOT pad" |
| OUTPUT "pad_pwr NOT pad" |
| OUTPUT "pad_io NOT pad" |
| } |
| |
| RULECHECK pad.CON.14 { |
| @ pad.con.14: Met4 is prohibited inside pad |
| OUTPUT "pad AND met4i" |
| } |
| |
| verbatim { |
| |
| // |
| // LVS Exclude Rules |
| // |
| |
| } |
| |
| RULECHECK LVS_exclude.WARN.1 { |
| @ LVS_exclude.WARN.1: LVS_exclude does not enclose any device |
| OUTPUT "LVS_exclude NOT ENCLOSE (OR diffi polyi capm cap2m npn pnp diffres polyres lires m1res m2res m3res m4res m5res pwres DIODEID PHdiodeID fuse pad)" |
| } |
| |
| proc check_lvs_exclude {lay_list} { |
| set a 1 |
| foreach lay $lay_list { |
| |
| set layname ${lay} |
| if {${lay} == "nsd"} { set layname "N+ source/drain" } |
| if {${lay} == "psd"} { set layname "P+ source/drain" } |
| if {${lay} == "DiodeID"} { set layname "areaid:diode" } |
| if {${lay} == "PHdiodeID"} { set layname "areaid:photo" } |
| if {${lay} == "m1res"} { set layname "met1:res" } |
| if {${lay} == "m2res"} { set layname "met2:res" } |
| if {${lay} == "m3res"} { set layname "met3:res" } |
| if {${lay} == "m4res"} { set layname "met4:res" } |
| if {${lay} == "m5res"} { set layname "met5:res" } |
| if {${lay} == "pwres"} { set layname "pwell:res" } |
| if {${lay} == "diffres"} { set layname "diff:res" } |
| if {${lay} == "polyres"} { set layname "poly:res" } |
| if {${lay} == "lires"} { set layname "li:res" } |
| |
| RULECHECK LVS_exclude.CON.${a} { |
| @ LVS_exclude.CON.${a}: LVS_exclude must not straddle ${layname} |
| OUTPUT "LVS_exclude INSIDE EDGE ${lay}" |
| } |
| |
| incr a |
| } |
| } |
| # JAG 6/23/21 removed fuse: |
| #check_lvs_exclude [list "gate" "nsd" "psd" "capm" "cap2m" "pwres" "diffres" "polyres" "lires" "m1res" "m2res" "m3res" "m4res" "m5res" "fuse" "DiodeID" "pnp" "npn" "PHdiodeID" "pad"] |
| check_lvs_exclude [list "gate" "nsd" "psd" "capm" "cap2m" "pwres" "diffres" "polyres" "lires" "m1res" "m2res" "m3res" "m4res" "m5res" "DiodeID" "pnp" "npn" "PHdiodeID" "pad"] |
| |
| RULECHECK LVS_exclude.OVL.1 { |
| @ LVS_exclude.OVL.1: LVS_exclude must be inside areaid:moduleCut |
| OUTPUT "LVS_exclude NOT moduleCutArea " |
| } |
| |
| verbatim { |
| // |
| // RECOMMENDED RULES |
| // |
| |
| #IFNDEF SKIP_RECOMMENDED_CHECKS |
| |
| } |
| |
| misc_blockage_check "prBndry" "RECOMMENDED" |
| #misc_blockage_check "polyBndry" "RECOMMENDED" |
| #misc_blockage_check "diffBndry" "RECOMMENDED" |
| |
| verbatim { |
| |
| #ENDIF |
| |
| } |
| |
| verbatim { |
| |
| // |
| // photo checks |
| // |
| |
| } |
| |
| set min_max_photo_width 3.0 |
| set min_photo_spacing 5.0 |
| set min_photo_to_dnwell_spacing 5.3 |
| set min_max_width_of_nwell_inside_photo 0.84 |
| set min_max_enc_of_nwell_by_photo 1.08 |
| set min_max_width_of_tap_inside_photo 0.41 |
| set min_max_enc_of_tap_by_nwell_inside_photo 0.215 |
| |
| SETLAYER photoDiode = "dnwell INTERACT (dnwell AND (ntap AND PHdiodeID))" |
| |
| RULECHECK photo.WID.1 { |
| @ photo.WID.1: Min/Max width of areaid:photo = ${min_max_photo_width} |
| OUTPUT "NOT LENGTH photoDiode == ${min_max_photo_width}" |
| } |
| |
| RULECHECK photo.SP.1 { |
| @ photo.SP.1: Min spacing/notch of areaid:photo < ${min_photo_spacing} |
| OUTPUT "EXTERNAL photoDiode < ${min_photo_spacing} ABUT < 90 SINGULAR REGION" |
| } |
| |
| RULECHECK photo.SP.2 { |
| @ photo.SP.2: Min spacing between areaid:photo and deep nwell < ${min_photo_to_dnwell_spacing} |
| OUTPUT "EXTERNAL photoDiode (dnwell NOT photoDiode) < ${min_photo_to_dnwell_spacing} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK photo.CON.1 { |
| @ photo.CON.1: Photo diode edges must be coincident with areaid:photo |
| OUTPUT "photoDiode NOT COINCIDENT INSIDE EDGE PHdiodeID" |
| } |
| |
| RULECHECK photo.CON.2 { |
| @ photo.CON.2: areaid:photo must be enclosed by dnwell ring |
| OUTPUT "photoDiode NOT (HOLES dnwell INNER)" |
| } |
| |
| RULECHECK photo.CON.3 { |
| @ photo.CON.3: areaid:photo must be enclosed by p+tap ring |
| OUTPUT "photoDiode NOT (HOLES PTAP INNER)" |
| } |
| |
| RULECHECK photo.WID.2 { |
| @ photo.WID.2: Min/Max width of nwell inside areaid:photo = ${min_max_width_of_nwell_inside_photo} |
| OUTPUT "NOT LENGTH (photoDiode AND nwell) == ${min_max_width_of_nwell_inside_photo}" |
| } |
| |
| RULECHECK photo.ENC.1 { |
| @ photo.ENC.1: Min/Max enclosure of nwell by areaid:photo = ${min_max_enc_of_nwell_by_photo} |
| SETLAYER photoOutsideNwell = "photoDiode NOT nwell" |
| OUTPUT "photoOutsideNwell NOT (INTERNAL photoOutsideNwell == ${min_max_enc_of_nwell_by_photo} OPPOSITE EXTENDED ${min_max_enc_of_nwell_by_photo} PARALLEL ONLY REGION)" |
| } |
| |
| RULECHECK photo.WID.3 { |
| @ photo.WID.3: Min/Max width of tap inside areaid:photo = ${min_max_width_of_tap_inside_photo} |
| OUTPUT "NOT LENGTH (photoDiode AND tap) == ${min_max_width_of_tap_inside_photo}" |
| } |
| |
| RULECHECK photo.ENC.2 { |
| @ photo.ENC.2: Min/Max enclosure of tap by nwell inside areaid:photo = ${min_max_enc_of_tap_by_nwell_inside_photo} |
| SETLAYER photoNwellBeyondTap = "(photoDiode AND nwell) NOT tap" |
| OUTPUT "photoNwellBeyondTap NOT (INTERNAL photoNwellBeyondTap == ${min_max_enc_of_tap_by_nwell_inside_photo} OPPOSITE EXTENDED ${min_max_enc_of_tap_by_nwell_inside_photo} PARALLEL ONLY REGION)" |
| } |
| |
| verbatim { |
| |
| // |
| // Metal checks |
| // |
| |
| } |
| |
| ### |
| ### Contains metal rule value variable definitions |
| ### |
| |
| proc metal_checks {lay_list} { |
| foreach lay $lay_list { |
| if {${lay} == "met1"} { |
| set m_width 0.14 |
| set m_space 0.14 |
| set m_area 0.083 |
| set m_hole_area 0.14 |
| set m_wide_size 0.28 |
| set m_wide_width 0.275 |
| set m_wide_space 0.28 |
| set wide_met_val 3.0 |
| } |
| if {${lay} == "met2"} { |
| set m_width 0.14 |
| set m_space 0.14 |
| set m_area 0.0676 |
| set m_hole_area 0.14 |
| set m_wide_size 0.28 |
| set m_wide_width 0.275 |
| set m_wide_space 0.28 |
| set wide_met_val 3.0 |
| } |
| if {${lay} == "met3"} { |
| set m_width 0.3 |
| set m_space 0.3 |
| set m_area 0.24 |
| set m_hole_area 0.2 |
| set m_wide_size 0.4 |
| set m_wide_width 0.395 |
| set m_wide_space 0.4 |
| set wide_met_val 3.0 |
| } |
| if {${lay} == "met4"} { |
| set m_width 0.3 |
| set m_space 0.3 |
| set m_area 0.24 |
| set m_hole_area 0.2 |
| set m_wide_size 0.4 |
| set m_wide_width 0.395 |
| set m_wide_space 0.4 |
| set wide_met_val 3.0 |
| } |
| if {${lay} == "met5"} { |
| set m_width 1.6 |
| set m_space 1.6 |
| set m_area 4.0 |
| set m_hole_area 0.14 |
| set m_wide_size 0.4 |
| set m_wide_width 0.395 |
| set m_wide_space 0.4 |
| set wide_met_val 3.0 |
| } |
| #SETLAYER huge_met_0${lay} = "WITH WIDTH ${lay}i > ${wide_met_val}" |
| # SETLAYER huge_met_1${lay} = "SIZE huge_met_0${lay} BY ${m_wide_size} INSIDE OF ${lay} STEP ${m_wide_size}" |
| # SETLAYER huge_met_2${lay} = "huge_met_1${lay} NOT huge_met_0${lay}" |
| # SETLAYER huge_met_3${lay} = "huge_met_2${lay} WITH EDGE (huge_met_2${lay} COINCIDENT OUTSIDE EDGE huge_met_0${lay})" |
| # SETLAYER huge_met_4${lay} = "huge_met_3${lay} OR huge_met_0${lay}" |
| # SETLAYER huge_met_5${lay} = "SNAP huge_met_4${lay} 1" |
| # SETLAYER huge_met_6${lay} = "${lay}i NOT huge_met_5${lay}" |
| # SETLAYER huge_met_7${lay} = "EXTERNAL huge_met_0${lay} huge_met_6${lay} <= ${m_wide_width} REGION" |
| # SETLAYER huge_met_9${lay} = "EXTERNAL huge_met_5${lay} < ${m_wide_space} ABUT < 90 REGION" |
| |
| RULECHECK ${lay}.AR.1 { |
| @ ${lay}.AR.1: Min area of ${lay} < ${m_area} |
| OUTPUT "AREA ${lay}i < ${m_area}" |
| } |
| |
| SETLAYER ${lay}_hole = HOLES ${lay}i |
| SETLAYER ${lay}_hole_empty = HOLES ${lay}i INNER |
| |
| if {${lay} != "met3" || ${lay} != "met4" || ${lay} != "met5"} { |
| RULECHECK ${lay}.AR.2 { |
| @ ${lay}.AR.2: Min area of ${lay} hole < ${m_hole_area} |
| OUTPUT "AREA ${lay}_hole < ${m_hole_area}" |
| OUTPUT "AREA ${lay}_hole_empty < ${m_hole_area}" |
| } |
| } |
| |
| RULECHECK ${lay}.WID.1 { |
| @ ${lay}.WID.1: Min width of ${lay} < ${m_width} |
| OUTPUT "INT ${lay}i < ${m_width} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK ${lay}.SP.1 { |
| @ ${lay}.SP.1: Min space & notch of ${lay} < ${m_space} |
| OUTPUT "EXT ${lay}i < ${m_space} ABUT < 90 SINGULAR REGION" |
| } |
| |
| SETLAYER wide_${lay}a = "WITH WIDTH ${lay}i > ${wide_met_val}" |
| SETLAYER wide_${lay} = "SIZE wide_${lay}a BY 0.28 INSIDE OF ${lay}i STEP 0.07" |
| |
| if {${lay} != "met5"} { |
| RULECHECK ${lay}.SP.2 { |
| @ ${lay}.SP.2: Wide ${lay} (including wide metal extending 0.28 into narrow metal) min spacing to ${lay} < ${m_wide_space} |
| OUTPUT "EXT wide_${lay} ${lay}i < ${m_wide_space} ABUT<90 REGION" |
| # OUTPUT "huge_met_7${lay} NOT (huge_met_7${lay} INSIDE ${lay})" |
| # OUTPUT "huge_met_9${lay} NOT (huge_met_9${lay} INTERACT (huge_met_9${lay} AND ${lay}))" |
| |
| } |
| |
| verbatim {#IFDEF SAVE_CONSTRUCTION_LAYERS} |
| |
| RULECHECK keep_wide_${lay} { |
| @ keep_wide_${lay}: Derived wide ${lay} for reference |
| OUTPUT "COPY wide_${lay}" |
| } |
| |
| verbatim {#ENDIF} |
| |
| } |
| } |
| } |
| |
| metal_checks [list "met1" "met2" "met3" "met4" "met5"] |
| |
| # additional metal/via checks: |
| set mcon_min_enc_m1 0.03 |
| set mcon_min_enc_m1_peri 0.06 |
| set mcon_min_enc_m1_exempt 0.005 |
| set m2_enc_via 0.055 |
| set m2_enc_via_core 0.045 |
| set m2_enc_via_adj_side 0.085 |
| set m3_enc_via2 0.065 |
| set m4_enc_via3 0.065 |
| set m5_enc_via4 0.31 |
| |
| # JAG 5/20/21 remove m1 enclose exemptions per PM: |
| SETLAYER m1_enc_mc_exempt = "EXTENT CELL \"s8cell_ee_plus_sseln_a\" \"s8cell_ee_plus_sseln_b\" \"s8cell_ee_plus_sselp_a\" \"s8cell_ee_plus_sselp_b\" \"s8fpls_pl8\" \"s8fs_cmux4_fm\"" |
| |
| RULECHECK met1.ENC.1 { |
| @ met1.ENC.1: Min enclosure of mcon by met1 (except inside areaid:core) < ${mcon_min_enc_m1} |
| #OUTPUT "ENC ((mcon NOT m1_enc_mc_exempt) NOT COREID) met1i < ${mcon_min_enc_m1} MEASURE ALL ABUT<90 SINGULAR REGION" |
| OUTPUT "ENC (mcon NOT COREID) met1i < ${mcon_min_enc_m1} MEASURE ALL ABUT<90 SINGULAR REGION" |
| } |
| |
| RULECHECK met1.ENC.1a { |
| @ met1.ENC.1a: Min enclosure of mcon by met1 (for exempt cells) < ${mcon_min_enc_m1_exempt} |
| OUTPUT "ENC ((mcon AND m1_enc_mc_exempt) NOT COREID) met1i < ${mcon_min_enc_m1_exempt} MEASURE ALL ABUT<90 SINGULAR REGION" |
| } |
| |
| RULECHECK met1.ENC.2 { |
| @ met1.ENC.2: Min enclosure of adj. sides of "mcon" in periphery by met1 < ${mcon_min_enc_m1_peri} |
| SETLAYER m1_enc_1 = "ENC \[mcon_PERI\] met1i < ${mcon_min_enc_m1_peri} ABUT < 90 PARALLEL MEASURE ALL PROJECTING > 0" |
| OUTPUT "NOT RECTANGLE (EXPAND EDGE m1_enc_1 INSIDE BY 0.005) ORTHOGONAL ONLY" |
| } |
| |
| RULECHECK met2.ENC.1 { |
| @ met2.ENC.1: Min enclosure of via1 by met2 outside areaid:core < ${m2_enc_via} |
| OUTPUT "ENC (via1 NOT COREID) met2 < ${m2_enc_via} ABUT<90 REGION SINGULAR" |
| } |
| |
| RULECHECK met2.ENC.3 { |
| @ met2.ENC.3: Min enclosure of via1 by met2 inside areaid:core < ${m2_enc_via_core} |
| OUTPUT "ENC (via1 AND COREID) met2 < ${m2_enc_via_core} ABUT<90 REGION SINGULAR" |
| } |
| |
| RULECHECK met2.ENC.2 { |
| @ met2.ENC.2: Min enclosure of adj. sides of via1 in periphery by met2 < ${m2_enc_via_adj_side} |
| SETLAYER m2_enc_1 = "ENC \[via1\] met2i < ${m2_enc_via_adj_side} ABUT < 90 PARALLEL MEASURE ALL PROJECTING > 0" |
| OUTPUT "NOT RECTANGLE (EXPAND EDGE m2_enc_1 INSIDE BY 0.005) ORTHOGONAL ONLY" |
| } |
| |
| RULECHECK met3.ENC.1 { |
| @ met3.ENC.1: Min enclosure of via2 by met3 < ${m3_enc_via2} |
| OUTPUT "ENC via2 met3i < ${m3_enc_via2} ABUT<90 REGION SINGULAR" |
| } |
| |
| RULECHECK met4.ENC.1 { |
| @ met4.ENC.1: Min enclosure of via3 by met4 < ${m4_enc_via3} |
| OUTPUT "ENC via3 met4i < ${m4_enc_via3} ABUT<90 REGION SINGULAR" |
| } |
| |
| RULECHECK met5.ENC.1 { |
| @ met5.ENC.1: Min enclosure of via4 by met5 < ${m5_enc_via4} |
| OUTPUT "ENC via4 met5i < ${m5_enc_via4} ABUT<90 REGION SINGULAR" |
| } |
| |
| verbatim { |
| |
| // |
| // Local interconnect checks |
| // |
| |
| } |
| |
| ### |
| ### Contains li rule value variable definitions |
| ### |
| set li_min_width_core 0.14 |
| set li_min_width_peri 0.17 |
| set li_min_space_core 0.165 |
| set li_min_space_vpp 0.14 |
| set li_min_space_peri 0.17 |
| set li_min_area 0.0561 |
| set licon_enc_li_adj_sides 0.08 |
| set li_min_res_wid 0.29 |
| |
| SETLAYER vpp_hd5 = "EXTENT CELL \"vpp*\"" |
| SETLAYER li_in_vpp = "li_i AND vpp_hd5" |
| SETLAYER li_not_vpp = "li_i NOT li_in_vpp" |
| SETLAYER li_not_vpp_cut_or_outside_core = "(li_not_vpp NOT INTERACT COREID) OR (li_not_vpp CUT COREID)" |
| SETLAYER li_in_vpp_or_inside_core = "li_in_vpp OR (li_not_vpp INSIDE COREID)" |
| SETLAYER li_inside_core = "li INSIDE COREID" |
| |
| RULECHECK li.WID.1 { |
| @ li.WID.1: Min width of local interconnect (not vpp) crossing or outside areaid:core < ${li_min_width_peri} |
| OUTPUT "INT (((li_i NOT COREID) NOT vpp_hd5) OR ((li_i CUT COREID) NOT vpp_hd5)) < ${li_min_width_peri} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK li.WID.2 { |
| @ li.WID.2: Min width of local interconnect in vppcap < ${li_min_width_core} |
| OUTPUT "INT (li_i AND vpp_hd5) < ${li_min_width_core} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK li.WID.3 { |
| @ li.WID.3: Min width of local interconnect in areaid:core < ${li_min_width_core} |
| OUTPUT "INT (li_i AND COREID) < ${li_min_width_core} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK li.SP.1 { |
| @ li.SP.1: Min space of local interconnect (not vpp) crossing or outside areaid:core < ${li_min_space_peri} |
| OUTPUT "EXT (li_i NOT COREID) li_i < ${li_min_space_peri} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK li.SP.2 { |
| @ li.SP.2: Min space of local interconnect in vppcap < ${li_min_space_vpp} |
| OUTPUT "EXT li_in_vpp li < ${li_min_space_vpp} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK li.SP.3 { |
| @ li.SP.3: Min space of local interconnect inside areaid:core < ${li_min_space_core} |
| OUTPUT "EXT li_inside_core li < ${li_min_space_core} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| SETLAYER licon_nocore = "licon NOT COREID" |
| RULECHECK li.ENC.1 { |
| @ li.ENC.1: Enclosure of licon by one of two adjacent local interconnect sides < ${licon_enc_li_adj_sides} |
| SETLAYER li_en_1 = "ENC \[licon_nocore\] li < ${licon_enc_li_adj_sides} ABUT<90 PARALLEL MEASURE ALL PROJECTING > 0" |
| OUTPUT "NOT RECTANGLE (EXPAND EDGE li_en_1 INSIDE BY 0.005) ORTHOGONAL ONLY" |
| } |
| |
| RULECHECK li.AR.1 { |
| @ li.AR.1: Min area of local interconnect < ${li_min_area} |
| OUTPUT "AREA li < ${li_min_area}" |
| } |
| |
| RULECHECK li.WID.4 { |
| @ li.WID.3: Min local interconnect resistor width < ${li_min_res_wid} |
| SETLAYER li_and_res = "lires AND li_i" |
| SETLAYER li_and_res_not_esd = "li_and_res NOT ESDID" |
| SETLAYER li_and_res_not_esd_not_li_edge = "EXPAND EDGE (li_and_res_not_esd NOT COIN EDGE li) OUTSIDE by 0.005" |
| OUTPUT "(EXT li_and_res_not_esd_not_li_edge < ${li_min_res_wid} ABUT<90 REGION EXCLUDE FALSE) AND li_and_res_not_esd" |
| } |
| |
| verbatim { |
| |
| // |
| // Via/contact checks |
| // |
| |
| } |
| |
| ## licon: |
| |
| ### |
| ### Contains licon rule value variable definitions |
| ### |
| |
| set licon_min_w 0.17 |
| set licon_max_len 0.17 |
| set licon_min_wid_prec_res 0.19 |
| set licon_max_len_prec_res 2.0 |
| set licon_min_space 0.17 |
| set licon_min_space_core 0.165 |
| set licon_bar_end_min_space 0.35 |
| set licon_bar_len_min_space 0.510 |
| set licon_bar_square_min_space 0.510 |
| set licon_ring_min_wid 0.17 |
| set licon_min_enc_diff 0.04 |
| set licon_tap_diff_butt_space 0.06 |
| set licon_diff_adj_side_enc 0.06 |
| set licon_tap_adj_side_enc 0.12 |
| set licon_min_enc_poly 0.05 |
| set licon_poly_adj_side_enc 0.08 |
| set licon_poly_min_space_psdm 0.110 |
| set licon_tap_lv_nw_space_var_ch 0.25 |
| set diff_tap_licon_space_gate 0.055 |
| set diff_tap_licon_space_gate_sc 0.05 |
| // JAG 9/24/21 changed value from 0.55 to 0.50 per CB and PC: |
| set diff_tap_licon_space_gate_sc_hvtp_15 0.05 |
| set diff_tap_licon_space_htp_peri 0.09 |
| set poly_licon_space_diff 0.19 |
| set poly_licon_space_diff_core 0.13 |
| set poly_licon_enc_npc 0.1 |
| set diff_licon_space_npc 0.09 |
| |
| SETLAYER licon_no_prec_res = "(licon NOT INTERACT (OR rpm urpm)) NOT SEALID" |
| SETLAYER licon_prec_res = "licon INTERACT (OR rpm urpm)" |
| |
| RULECHECK licon.WID.1 { |
| @ licon.WID.1: Min licon width (non-bar) < ${licon_min_w} |
| OUTPUT "INT licon_no_prec_res < ${licon_min_w} ABUT<90 REGION" |
| } |
| |
| RULECHECK licon.LEN.1 { |
| @ licon.LEN.1: Max licon length (non-bar) > ${licon_max_len} |
| OUTPUT "LENGTH licon_no_prec_res > ${licon_max_len}" |
| } |
| |
| RULECHECK licon.WID.2 { |
| @ licon.WID.2: Exact size of bar licon = ${licon_min_wid_prec_res} X ${licon_max_len_prec_res} |
| OUTPUT "NOT RECTANGLE licon_prec_res == ${licon_min_wid_prec_res} BY == ${licon_max_len_prec_res} ORTHOGONAL ONLY" |
| } |
| |
| RULECHECK licon.SP.1 { |
| @ licon.SP.1: Min licon space (non-bar) outside areaid:core < ${licon_min_space} |
| OUTPUT "EXT (licon_no_prec_res NOT COREID) < ${licon_min_space} ABUT<90 SINGULAR REGION" |
| } |
| |
| RULECHECK licon.SP.2 { |
| @ licon.SP.2: Min end-to-end space of bar licon < ${licon_bar_end_min_space} |
| SETLAYER bar_licon_end = "LENGTH licon_prec_res < ${licon_max_len_prec_res}" |
| OUTPUT "EXT bar_licon_end < ${licon_bar_end_min_space} ABUT<90 REGION" |
| } |
| |
| RULECHECK licon.SP.3 { |
| @ licon.SP.3: Min side-to-side spacing of bar licon < ${licon_bar_len_min_space} |
| SETLAYER bar_licon_side = "LENGTH licon_prec_res > ${licon_min_wid_prec_res}" |
| OUTPUT "EXT bar_licon_side < ${licon_bar_len_min_space} ABUT<90 REGION" |
| } |
| |
| RULECHECK licon.SP.4 { |
| @ licon.SP.4: Min space from bar licon to square licon < ${licon_bar_square_min_space} |
| OUTPUT "EXT licon_no_prec_res licon_prec_res < ${licon_bar_square_min_space} ABUT<90 REGION SINGULAR" |
| } |
| |
| RULECHECK licon.WID.3 { |
| @ licon.WID.3: Min width licon in areaid:seal < ${licon_ring_min_wid} |
| OUTPUT "INT (licon AND SEALID) < ${licon_ring_min_wid} ABUT<90 REGION" |
| } |
| |
| RULECHECK licon.WID.4 { |
| @ licon.WID.4: Max width of licon in areaid:seal > ${licon_ring_min_wid}+0.005 |
| OUTPUT "WITH WIDTH (licon AND SEALID) > ${licon_ring_min_wid}+0.005" |
| } |
| |
| RULECHECK licon.ENC.1 { |
| @ licon.ENC.1: Min enclosure of licon by diff (not tap) < ${licon_min_enc_diff} |
| OUTPUT "ENC (licon_nocore NOT tap) diffi < ${licon_min_enc_diff} MEASURE ALL ABUT<90 REGION SINGULAR" |
| } |
| |
| RULECHECK licon.SP.5 { |
| @ licon.SP.5: Min space from tap licon to diff-abutting tap edge > ${licon_tap_diff_butt_space} |
| OUTPUT "EXT (licon_nocore and tap) (diff COINCIDENT OUTSIDE EDGE tap) < ${licon_tap_diff_butt_space} ABUT<90 REGION" |
| } |
| |
| RULECHECK licon.ENC.2 { |
| @ licon.ENC.2: Min enclosure of licon by diff on one of two adjacent sides < ${licon_diff_adj_side_enc} |
| SETLAYER li_enc_2 = "ENC \[licon_nocore\] diff < ${licon_diff_adj_side_enc} ABUT<90 PARALLEL MEASURE ALL PROJECTING > 0" |
| OUTPUT "NOT RECTANGLE (EXPAND EDGE li_enc_2 INSIDE BY 0.005) ORTHOGONAL ONLY" |
| } |
| |
| RULECHECK licon.CON.7 { |
| @ licon.CON.7: Layer licon cannot straddle tap |
| OUTPUT "licon_nocore cut tap" |
| } |
| |
| RULECHECK licon.ENC.4 { |
| @ licon.ENC.4: Min enclosure of licon by isolated tap on one of two adjacent sides < ${licon_tap_adj_side_enc} |
| SETLAYER non_isolated_tap = "tap WITH EDGE (tap COINCIDENT OUTSIDE EDGE diff)" |
| SETLAYER isolated_tap = "tap NOT non_isolated_tap" |
| SETLAYER li_enc_4 = "ENC \[licon_nocore\] isolated_tap < ${licon_tap_adj_side_enc} ABUT<90 PARALLEL MEASURE ALL PROJECTING > 0" |
| OUTPUT "NOT RECTANGLE (EXPAND EDGE li_enc_4 INSIDE BY 0.005) ORTHOGONAL ONLY" |
| } |
| |
| RULECHECK licon.ENC.5 { |
| @ licon.ENC.5: Min enclosure of licon by poly < ${licon_min_enc_poly} |
| OUTPUT "ENC licon_nocore polyi < ${licon_min_enc_poly} ABUT<90 REGION SINGULAR" |
| } |
| |
| RULECHECK licon.ENC.6 { |
| @ licon.ENC.6: Min enclosure of licon by poly on one of two adjacent sides < ${licon_poly_adj_side_enc} |
| SETLAYER li_enc_6 = "ENC \[licon_nocore\] polyi < ${licon_poly_adj_side_enc} ABUT<90 PARALLEL MEASURE ALL PROJECTING > 0" |
| OUTPUT "NOT RECTANGLE (EXPAND EDGE li_enc_6 INSIDE BY 0.005) ORTHOGONAL ONLY" |
| } |
| |
| RULECHECK licon.SP.6 { |
| @ licon.SP.6: Min space from poly licon to psdm (no overlap alowed) < ${licon_poly_min_space_psdm} |
| OUTPUT "EXT ((licon_nocore AND poly) OUTSIDE (rpm OR urpm)) psdm < ${licon_poly_min_space_psdm} ABUT<90 SINGULAR REGION" |
| OUTPUT "((poly AND licon_nocore) OUTSIDE (rpm OR urpm)) AND psdm" |
| } |
| |
| RULECHECK licon.SP.7 { |
| @ licon.SP.7: Min space from licon on (tap in low voltage nwell) to varactor channel < ${licon_tap_lv_nw_space_var_ch} |
| SETLAYER poly_in_lv_nw = "poly AND (nwell NOT INTERACT (OR v5 v12 v20))" |
| SETLAYER var_ch = "poly_in_lv_nw AND (tap AND (nwell NOT INTERACT (OR v5 v12 v20)))" |
| SETLAYER var_licon = "(licon_nocore AND (nwell NOT INTERACT (OR v5 v12 v20))) AND tap" |
| OUTPUT "EXT var_licon var_ch < ${licon_tap_lv_nw_space_var_ch} ABUT<90 REGION SINGULAR" |
| } |
| |
| SETLAYER MOSDIFFandPOLY = "diffi AND polyi" |
| SETLAYER userGate = "MOSDIFFandPOLY AND polyGate" |
| SETLAYER derivedGate = "MOSDIFFandPOLY OUTSIDE polyGate" |
| SETLAYER allGatetmp = "(derivedGate OR userGate) NOT ENID" |
| SETLAYER remGate = "allGatetmp TOUCH drainGate == 1" |
| SETLAYER allGate = "allGatetmp NOT remGate" |
| SETLAYER drainGate = "EXPAND EDGE (MOSDIFFandPOLY COINCIDENT INSIDE EDGE poly) OUTSIDE BY 0.005" |
| |
| RULECHECK licon.SP.8 { |
| @ licon.SP.8: Min space and no overlap from licon on diff to poly on diff (except standard cells) < ${diff_tap_licon_space_gate} |
| #SETLAYER licon11cGateCell = "INSIDE CELL polyii s8fs_gwdlvx4 s8fs_gwdlvx8 s8fs_hvrsw_x4 s8fs_hvrsw8 s8fs_hvrsw264 s8fs_hvrsw520" |
| #SETLAYER licon11dGateCell = "INSIDE CELL polyii s8fs_rdecdrv s8fs_rdec8 s8fs_rdec32 s8fs_rdec264 s8fs_rdec520" |
| SETLAYER esdGate = "allGate AND ESDID" |
| SETLAYER pesd = "esdGate AND nwell" |
| SETLAYER phvesd = "pesd INTERACT v5" |
| SETLAYER allENIDgate = "ENID AND (poly AND v5)" |
| SETLAYER nwellENID = "INTERACT nwell ENID" |
| SETLAYER pfetExtDrTmp = "allENIDgate AND dnwell" |
| SETLAYER pfetExtDr = "pfetExtDrTmp AND nwellENID" |
| SETLAYER pvhv = "COPY pfetExtDr" |
| SETLAYER fetGate = "allGate NOT esdGate" |
| SETLAYER pfet_dev = "fetGate AND nwell" |
| SETLAYER phv = "(pfet_dev INTERACT v5) NOT (pvhv OR phvesd)" |
| #SETLAYER licon11cGate = "licon11cGateCell INTERACT (EXPAND EDGE (LENGTH (phv COINCIDENT INSIDE EDGE diff) == 0.5) INSIDE BY 0.005)" |
| #SETLAYER licon11dGate = "licon11dGateCell AND (WITH WIDTH ngate == 0.15)" |
| # JAG 5/20/21 removed exemptions per PM: |
| #SETLAYER gate_not_std_cell = "gate NOT (STDCID OR (licon11cGate OR licon11dGate))" |
| SETLAYER gate_not_std_cell = "gate NOT STDCID" |
| SETLAYER xfom = "diff NOT poly" |
| SETLAYER licon1ToXfom = "licon INTERACT (licon AND xfom)" |
| SETLAYER licon1ToXfom_PERI = "licon1ToXfom NOT COREID" |
| OUTPUT "EXT licon1ToXfom_PERI gate_not_std_cell < ${diff_tap_licon_space_gate} ABUT<90 REGION SINGULAR" |
| OUTPUT "licon1ToXfom_PERI AND gate_not_std_cell" |
| } |
| |
| SETLAYER phvt_15_gate = "INT (((poly AND diff) AND psdm) AND hvtp) == 0.15 REGION ABUT<90" |
| |
| RULECHECK licon.SP.9 { |
| @ licon.SP.9: Min space from licon on diff to poly on diff in standard cells (except 0.15um p+ high vt) < ${diff_tap_licon_space_gate_sc} |
| OUTPUT "EXT ((licon_nocore AND diff) AND STDCID) ((poly AND diff) NOT phvt_15_gate) < ${diff_tap_licon_space_gate_sc} ABUT<90 REGION SINGULAR" |
| } |
| |
| RULECHECK licon.SP.10 { |
| @ licon.SP.10: Min space from licon on diff to poly on diff in standard cells for p+ high vt < ${diff_tap_licon_space_gate_sc_hvtp_15} |
| OUTPUT "EXT (phvt_15_gate AND STDCID) ((licon_nocore AND diff) AND STDCID) < ${diff_tap_licon_space_gate_sc_hvtp_15} ABUT<90 REGION SINGULAR" |
| } |
| |
| RULECHECK licon.SP.11 { |
| @ licon.SP.11: Min space (no overlap) from licon on diff to npc < ${diff_tap_licon_space_htp_peri} |
| OUTPUT "EXT ((diffi and licon_nocore) NOT COREID) npc < ${diff_tap_licon_space_htp_peri} ABUT<90 SINGULAR REGION" |
| OUTPUT "(diffi and licon_nocore) AND npc" |
| } |
| |
| RULECHECK licon.SP.12 { |
| @ licon.SP.12: Min space from poly licon to diff < ${poly_licon_space_diff} |
| OUTPUT "EXT ((polyi AND licon) NOT COREID) diffi < ${poly_licon_space_diff} ABUT<90 REGION SINGULAR" |
| } |
| |
| RULECHECK licon.SP.13 { |
| @ licon.SP.13: Min space from poly licon to diff in core < ${poly_licon_space_diff_core} |
| OUTPUT "EXT ((polyi AND licon) AND COREID) diffi < ${poly_licon_space_diff_core} ABUT<90 REGION SINGULAR" |
| } |
| |
| RULECHECK licon.SP.14 { |
| @ licon.SP.14: Min licon space (non-bar) inside areaid:core < ${licon_min_space_core} |
| OUTPUT "EXT (licon_no_prec_res AND COREID) < ${licon_min_space_core} ABUT<90 SINGULAR REGION" |
| } |
| |
| # Duplicate rule to licon.SP.11 - commented out JAG 1/21/21 |
| #RULECHECK licon.SP.13 { |
| #@ licon.SP.13: Min space from licon on diff to npc (no overlap) < ${diff_licon_space_npc} |
| # OUTPUT "EXT ((diffi AND licon) NOT COREID) npc < ${diff_licon_space_npc} ABUT<90 REGION SINGULAR" |
| # OUTPUT "((diffi AND licon) NOT COREID) AND npc" |
| # } |
| |
| RULECHECK licon.ENC.7 { |
| @ licon.ENC.7: Min enclosure of poly licon by npc outside areaid:core < ${poly_licon_enc_npc} |
| OUTPUT "ENC ((polyi AND licon) NOT COREID) npc < ${poly_licon_enc_npc} ABUT<90 REGION SINGULAR" |
| #covered by licon.CON.11: |
| #OUTPUT "((polyi AND licon) NOT COREID) NOT npc" |
| } |
| |
| # JAG 4/22/21 new |
| RULECHECK licon.ENC.8 { |
| @ licon.ENC.8: Min enclosure of poly licon by npc inside areaid:core >= ${min_enclosure_of_poly_licon_by_npc} |
| OUTPUT "ENC ((polyi AND licon) AND COREID) npc < ${min_enclosure_of_poly_licon_by_npc} ABUT<90 REGION SINGULAR" |
| } |
| |
| RULECHECK licon.CON.8 { |
| @ licon.CON.8: Every source or drain diff must enclose at least 1 licon (except in v20) |
| SETLAYER nsrcdrn = "(diff NOT poly) and nsdm" |
| SETLAYER psrcdrn = "(diff NOT poly) and psdm" |
| SETLAYER source_diffusion = "(nsrcdrn WITH EDGE (nsrcdrn COINCIDENT OUTSIDE EDGE ptap)) OR (psrcdrn WITH EDGE (psrcdrn COINCIDENT OUTSIDE EDGE ntap))" |
| SETLAYER source_diffusion_peri = "source_diffusion NOT COREID" |
| SETLAYER licon_in_source = "licon INSIDE source_diffusion_peri" |
| OUTPUT "(source_diffusion_peri OUTSIDE licon_in_source) NOT V20" |
| } |
| RULECHECK licon.CON.9 { |
| @ licon.CON.9: Every tap must enclose at least 1 licon (except in v20) |
| SETLAYER tap_PERI = "tap NOT COREID" |
| SETLAYER npcon_tap = "tap_PERI OR (tap CUT COREID)" |
| OUTPUT "(npcon_tap NOT ENCLOSE licon) NOT v20" |
| } |
| |
| RULECHECK licon.CON.10 { |
| @ licon.CON.10: Layer licon must not overlap both poly and diff |
| OUTPUT "(poly and licon) AND diff" |
| } |
| |
| RULECHECK licon.CON.11 { |
| @ licon.CON.11: Poly licon must be inside npc |
| OUTPUT "(poly AND licon) NOT npc" |
| } |
| |
| RULECHECK licon.CON.12 { |
| @ licon.CON.12: psdm overlapping poly and licon is prohibited inside areaid:core |
| OUTPUT "((poly AND licon) AND psdm) AND COREID" |
| } |
| |
| #RULECHECK licon.CON.12 { |
| # @ poly of the HV varactor must not interact with licon |
| # poly_in_fgr = poly AND exemptNhvnativeCell |
| # "licon AND poly_in_fgr" |
| # } |
| |
| |
| ## mcon: |
| |
| ### |
| ### Contains mcon rule value variable definitions |
| ### |
| |
| set mcon_min_w 0.17 |
| set mcon_max_l 0.17 |
| set mcon_space 0.19 |
| |
| |
| SETLAYER mcon_donut = "DONUT mcon" |
| SETLAYER non_ring_mcon = "mcon NOT mcon_donut" |
| |
| RULECHECK mcon.WID.1 { |
| @ mcon.WID.1: Min width of mcon < ${mcon_min_w} |
| OUTPUT "INT mcon < ${mcon_min_w} REGION" |
| } |
| |
| RULECHECK mcon.LEN.1 { |
| @ mcon.LEN.1: Max width of mcon > ${mcon_max_l} |
| OUTPUT "non_ring_mcon WITH EDGE (LENGTH non_ring_mcon > ${mcon_max_l})" |
| } |
| |
| RULECHECK mcon.SP.1 { |
| @ mcon.SP.1: Min spacing of mcon < ${mcon_space} |
| OUTPUT "EXT mcon < ${mcon_space} ABUT < 90 SINGULAR REGION" |
| } |
| |
| # deleted obsolete - no via/contacts in seal ring: |
| #RULECHECK mcon.WID.2 { |
| #@ mcon.WID.2: Min width of ring-shaped mcon < ${mcon_min_ring_width} |
| # OUTPUT "INT mcon_donut < ${mcon_min_ring_width} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| # } |
| |
| #RULECHECK mcon.WID.3 { |
| #@ mcon.WID.3: Max width of ring-shaped mcon > ${mcon_max_ring_width} |
| # OUTPUT "WITH WIDTH mcon_donut > ${mcon_max_ring_width}" |
| # } |
| |
| #RULECHECK mcon.CON.11 { |
| #@ mcon.CON.11: ring-shapped mcon must overlap areaid:seal |
| # OUTPUT "mcon_donut NOT SEALID" |
| # } |
| |
| ## via1: |
| |
| ### |
| ### Contains via1 rule value variable definitions |
| ### |
| |
| ### V1: |
| |
| |
| set min_wid_via_outs_mt 0.15 |
| set max_len_via_outs_mt 0.15 |
| set exact_via_size_ins_mt_1 0.15 |
| set exact_via_size_ins_mt_2 0.23 |
| set exact_via_size_ins_mt_3 0.28 |
| set min_via_space 0.17 |
| set min_m1_enc_via 0.055 |
| set min_m1_enc_via_adj_side 0.085 |
| set min_m1_enc_via_23_mt 0.03 |
| set min_m1_enc_via_23_adj_side 0.06 |
| |
| RULECHECK via1.WID.1 { |
| @ via1.WID.1: Min width of via1 outside areaid:moduleCut < ${min_wid_via_outs_mt} |
| OUTPUT "INT (via1 NOT moduleCutAREA) < ${min_wid_via_outs_mt} ABUT<90 REGION" |
| } |
| |
| RULECHECK via1.LEN.1 { |
| @ via1.LEN.1: Max length of via1 outside areaid:moduleCut > ${max_len_via_outs_mt} |
| OUTPUT "LENGTH (via1 NOT moduleCutAREA) > ${max_len_via_outs_mt}" |
| } |
| |
| SETLAYER via_in_mc_good_1 = "RECTANGLE (via1 AND moduleCutAREA) == ${exact_via_size_ins_mt_1} BY == ${exact_via_size_ins_mt_1} ORTHOGONAL ONLY" |
| SETLAYER via_in_mc_good_2 = "RECTANGLE (via1 AND moduleCutAREA) == ${exact_via_size_ins_mt_2} BY == ${exact_via_size_ins_mt_2} ORTHOGONAL ONLY" |
| SETLAYER via_in_mc_good_3 = "RECTANGLE (via1 AND moduleCutAREA) == ${exact_via_size_ins_mt_3} BY == ${exact_via_size_ins_mt_3} ORTHOGONAL ONLY" |
| |
| RULECHECK via1.WID.2 { |
| @ via1.WID.2: Only three size of square via1s allowed inside areaid:moduleCut: ${exact_via_size_ins_mt_1}, ${exact_via_size_ins_mt_2} or ${exact_via_size_ins_mt_3} |
| OUTPUT "(via1 AND moduleCutAREA) NOT (OR via_in_mc_good_1 via_in_mc_good_2 via_in_mc_good_3)" |
| } |
| |
| RULECHECK via1.SP.1 { |
| @ via1.SP.1: Min space of via1 < ${min_via_space} |
| OUTPUT "EXT via1 < ${min_via_space} ABUT<90 REGION SINGULAR EXCLUDE FALSE" |
| } |
| |
| # deleted obsolete - no via/contacts in seal ring: |
| #RULECHECK via1.WID.3 { |
| #@ via1.WID.3: Min width of ring shaped via1s < ${min_wid_ring_via} |
| # OUTPUT "INT ((via1 INTERACT (HOLES via1)) AND SEALID) < ${min_wid_ring_via} ABUT<90 REGION" |
| # } |
| # |
| #RULECHECK via1.WID.4 { |
| #@ via1.WID.4: Max width of ring shaped via1s > ${max_wid_ring_via} |
| # OUTPUT "SIZE ((via1 INTERACT (HOLES via1)) AND SEALID) BY ${max_wid_ring_via}/2+0.0005 UNDEROVER" |
| # } |
| |
| RULECHECK via1.ENC.1 { |
| @ via1.ENC.1: Min enclosure of via1 by metal 1 outside module cut area < ${min_m1_enc_via} |
| OUTPUT "ENC (via1 NOT moduleCutAREA) met1i < ${min_m1_enc_via} MEASURE ALL ABUT<90 SINGULAR REGION" |
| } |
| |
| RULECHECK via1.ENC.2 { |
| @ via1.ENC.2: Min enclosure of ${exact_via_size_ins_mt_2}um via1 by met1 inside module cut area < ${min_m1_enc_via_23_mt} |
| OUTPUT "ENC via_in_mc_good_2 met1i < ${min_m1_enc_via_23_mt} MEASURE ALL ABUT<90 SINGULAR REGION" |
| } |
| |
| RULECHECK via1.ENC.3 { |
| @ via1.ENC.3: Min enclosure of ${exact_via_size_ins_mt_3} um via by met1 inside module cut area < 0 |
| OUTPUT "via_in_mc_good_3 NOT met1i" |
| } |
| |
| RULECHECK via1.ENC.4 { |
| @ via1.ENC.4: Min enclosure of ${exact_via_size_ins_mt_1}um via by met1 on one of two adjacent sides < ${min_m1_enc_via_adj_side} |
| SETLAYER via_15 = "RECTANGLE via1 == ${exact_via_size_ins_mt_1} BY == ${exact_via_size_ins_mt_1} ORTHOGONAL ONLY" |
| SETLAYER via_enc_5 = "ENC \[via_15\] met1i < ${min_m1_enc_via_adj_side} ABUT<90 PARALLEL MEASURE ALL PROJECTING > 0" |
| OUTPUT "NOT RECTANGLE (EXPAND EDGE via_enc_5 INSIDE BY 0.005) ORTHOGONAL ONLY" |
| } |
| |
| RULECHECK via1.ENC.5 { |
| @ via1.ENC.5: Min enclosure of ${exact_via_size_ins_mt_2}um via by met1 on one of two adjacent sides < ${min_m1_enc_via_adj_side} |
| SETLAYER via_23 = "RECTANGLE via1 == ${exact_via_size_ins_mt_2} BY == ${exact_via_size_ins_mt_2} ORTHOGONAL ONLY" |
| SETLAYER via_enc_5 = "ENC \[via_23\] met1i < ${min_m1_enc_via_23_adj_side} ABUT<90 PARALLEL MEASURE ALL PROJECTING > 0" |
| OUTPUT "NOT RECTANGLE (EXPAND EDGE via_enc_5 INSIDE BY 0.005) ORTHOGONAL ONLY" |
| } |
| |
| ### V2: |
| |
| set min_wid_via2_outs_mt 0.2 |
| set max_len_via2_outs_mt 0.2 |
| set exact_via2_size_ins_mt_1 0.2 |
| set exact_via2_size_ins_mt_2 0.28 |
| set exact_via2_size_ins_mt_3 1.2 |
| set exact_via2_size_ins_mt_4 1.5 |
| set min_via2_space 0.2 |
| set min_m2_enc_via2 0.04 |
| set min_m2_enc_via2_1p5_ins_mt 0.14 |
| set min_m2_enc_via2_adj_side 0.085 |
| |
| RULECHECK via2.WID.1 { |
| @ via2.WID.1: Min via2 width outside areaid:moduleCut < ${min_wid_via2_outs_mt} |
| OUTPUT "INT (via2 NOT moduleCutAREA) < ${min_wid_via2_outs_mt} ABUT<90 REGION" |
| } |
| |
| RULECHECK via2.LEN.1 { |
| @ via2.LEN.1: Max length via2 outside areaid:moduleCut > ${max_len_via2_outs_mt} |
| OUTPUT "LENGTH (via2 NOT moduleCutAREA) > ${max_len_via2_outs_mt}" |
| } |
| |
| SETLAYER via2_in_mc_good_1 = "RECTANGLE (via2 AND moduleCutAREA) == ${exact_via2_size_ins_mt_1} BY == ${exact_via2_size_ins_mt_1} ORTHOGONAL ONLY" |
| SETLAYER via2_in_mc_good_2 = "RECTANGLE (via2 AND moduleCutAREA) == ${exact_via2_size_ins_mt_2} BY == ${exact_via2_size_ins_mt_2} ORTHOGONAL ONLY" |
| SETLAYER via2_in_mc_good_3 = "RECTANGLE (via2 AND moduleCutAREA) == ${exact_via2_size_ins_mt_3} BY == ${exact_via2_size_ins_mt_3} ORTHOGONAL ONLY" |
| SETLAYER via2_in_mc_good_4 = "RECTANGLE (via2 AND moduleCutAREA) == ${exact_via2_size_ins_mt_4} BY == ${exact_via2_size_ins_mt_4} ORTHOGONAL ONLY" |
| |
| RULECHECK via2.WID.2 { |
| @ via2.WID.2: Only four sizes of square via2s allowed inside areaid:moduleCut: ${exact_via2_size_ins_mt_1}, ${exact_via2_size_ins_mt_2}, ${exact_via2_size_ins_mt_3} or ${exact_via2_size_ins_mt_4} |
| OUTPUT "(via2 AND moduleCutAREA) NOT (OR via2_in_mc_good_1 via2_in_mc_good_2 via2_in_mc_good_3 via2_in_mc_good_4)" |
| } |
| |
| RULECHECK via2.SP.1 { |
| @ via2.SP.1: Min space of via2 < ${min_via2_space} |
| OUTPUT "EXT via2 < ${min_via2_space} ABUT<90 REGION SINGULAR EXCLUDE FALSE" |
| } |
| |
| # deleted obsolete - no via/contacts in seal ring: |
| #RULECHECK via2.WID.3 { |
| #@ via2.WID.3: Max width of via2 in die seal ring > ${max_wid_via2_ins_seal} |
| # OUTPUT "SIZE (via2 INSIDE SEALID) BY ${max_wid_via2_ins_seal}/2+0.0005 UNDEROVER" |
| # } |
| |
| RULECHECK via2.ENC.1 { |
| @ via2.ENC.1: Min enclosure of via2 by met2 < ${min_m2_enc_via2} |
| OUTPUT "ENC via2 met2 < ${min_m2_enc_via2} ABUT<90 MEASURE ALL SINGULAR REGION" |
| } |
| |
| RULECHECK via2.ENC.2 { |
| @ via2.ENC.2: Min enclosure of ${exact_via2_size_ins_mt_4}um via2 by met2 inside module cut area < ${min_m2_enc_via2_1p5_ins_mt} |
| OUTPUT "ENC via2_in_mc_good_4 met2i < ${min_m2_enc_via2_1p5_ins_mt} ABUT<90 MEASURE ALL SINGULAR REGION" |
| } |
| |
| RULECHECK via2.ENC.3 { |
| @ via2.ENC.3: Min enclosure of via2 by met2 on one of two adjacent sides < ${min_m2_enc_via2_adj_side} |
| SETLAYER via2_enc_5 = "ENC \[via2\] met2i < ${min_m2_enc_via2_adj_side} ABUT<90 PARALLEL MEASURE ALL PROJECTING > 0" |
| OUTPUT "NOT RECTANGLE (EXPAND EDGE via2_enc_5 INSIDE BY 0.005) ORTHOGONAL ONLY" |
| } |
| |
| ### V3: |
| |
| set min_wid_via3_outs_mc 0.20 |
| set max_len_via3_outs_mc 0.20 |
| set exact_via3_size_ins_mc_1 0.20 |
| set exact_via3_size_ins_mc_2 0.80 |
| set min_space_via3 0.20 |
| set min_enc_via3_met3 0.06 |
| set min_m3_enc_via3_adj_side 0.09 |
| |
| SETLAYER ring_via3 = "DONUT via3" |
| SETLAYER non_ring_via3 = "via3 NOT ring_via3" |
| SETLAYER via3_not_modulecut = "via3 NOT moduleCutAREA" |
| SETLAYER via3_and_modulecut = "via3 AND moduleCutAREA" |
| |
| RULECHECK via3.WID.1 { |
| @ via3.WID.1: Min width of via3 outside areaid:moduleCut < ${min_wid_via3_outs_mc} |
| OUTPUT "INT via3_not_modulecut < ${min_wid_via3_outs_mc} REGION" |
| } |
| |
| RULECHECK via3.LEN.1 { |
| @ via3.LEN.1: Max length via3 outside areaid:moduleCut > ${max_len_via3_outs_mc} |
| OUTPUT "via3_not_modulecut WITH EDGE (LENGTH via3_not_modulecut > ${max_len_via3_outs_mc})" |
| } |
| |
| RULECHECK via3.WID.2 { |
| @ via3.WID.2: via3 size inside areaid:moduleCut must be ${exact_via3_size_ins_mc_1} or ${exact_via3_size_ins_mc_2} |
| SETLAYER good_a_v3 = "RECTANGLE via3_and_modulecut == ${exact_via3_size_ins_mc_1} BY == ${exact_via3_size_ins_mc_1} ORTHOGONAL ONLY" |
| SETLAYER good_b_v3 = "RECTANGLE via3_and_modulecut == ${exact_via3_size_ins_mc_2} BY == ${exact_via3_size_ins_mc_2} ORTHOGONAL ONLY" |
| SETLAYER all_good_v3 = "good_a_v3 OR good_b_v3" |
| OUTPUT "via3_and_modulecut NOT all_good_v3" |
| } |
| |
| RULECHECK via3.SP.1 { |
| @ via3.SP.1: Min space of via3 < ${min_space_via3} |
| OUTPUT "EXT via3 < ${min_space_via3} ABUT < 90 SINGULAR REGION" |
| } |
| |
| # deleted obsolete - no via/contacts in seal ring: |
| #RULECHECK via3.WID.3 { |
| #@ via3.WID.3: Max width of ring-shaped via3 > ${max_wid_via3_ring} |
| # OUTPUT "WITH WIDTH ring_via3 > ${max_wid_via3_ring}" |
| # } |
| |
| RULECHECK via3.ENC.1 { |
| @ via3.ENC.1: Min enclosure of via3 by met3 < ${min_enc_via3_met3} |
| OUTPUT "ENC via3 met3i < ${min_enc_via3_met3} MEASURE ALL ABUT<90 SINGULAR" |
| } |
| |
| RULECHECK via3.ENC.2 { |
| @ via3.ENC.2: Min enclosure of adjacent sides of via3 by met3 < ${min_m3_enc_via3_adj_side} |
| SETLAYER via3_enc_2 = "ENC \[via3\] met3i < ${min_m3_enc_via3_adj_side} ABUT < 90 PARALLEL MEASURE ALL PROJECTING > 0" |
| OUTPUT "NOT RECTANGLE (EXPAND EDGE via3_enc_2 INSIDE BY 0.005) ORTHOGONAL ONLY" |
| } |
| |
| ### V4: |
| |
| set min_wid_via4 0.80 |
| set max_len_via4 0.80 |
| set min_space_via4 0.80 |
| set min_enc_via4_met4 0.06 |
| |
| SETLAYER ring_via4 = "DONUT via4" |
| SETLAYER non_ring_via4 = "via4 NOT ring_via4" |
| SETLAYER via4_not_modulecut = "non_ring_via4 NOT moduleCutAREA" |
| SETLAYER via4_and_modulecut = "non_ring_via4 AND moduleCutAREA" |
| |
| RULECHECK via4.WID.1 { |
| @ via4.WID.1: Min width via4 outside areaid:moduleCut < ${min_wid_via4} |
| OUTPUT "INT non_ring_via4 < ${min_wid_via4} REGION" |
| } |
| |
| RULECHECK via4.LEN.1 { |
| @ via4.LEN.1: Max length via4 outside areaid:moduleCut > ${max_len_via4} |
| OUTPUT "non_ring_via4 WITH EDGE (LENGTH non_ring_via4 > ${max_len_via4})" |
| } |
| |
| RULECHECK via4.SP.1 { |
| @ via4.SP.1: Min space of via4 < ${min_space_via4} |
| OUTPUT "EXT via4 < ${min_space_via4} ABUT < 90 SINGULAR REGION" |
| } |
| |
| # deleted obsolete - no via/contacts in seal ring: |
| #RULECHECK via4.WID.2 { |
| #@ via4.WID.2: Min width of ring-shaped via4 < ${min_wid_via4_ring} |
| # OUTPUT "INT ring_via4 < ${min_wid_via4_ring} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| # } |
| |
| #RULECHECK via4.WID.3 { |
| #@ via4.WID.3: Max width of ring-shaped via4 > ${max_wid_via4_ring} |
| # OUTPUT "WITH WIDTH ring_via4 > ${max_wid_via4_ring}" |
| # } |
| |
| RULECHECK via4.ENC.1 { |
| @ via4.ENC.1: Min enclosure of via4 by met4 < ${min_enc_via4_met4} |
| OUTPUT "ENC via4 met4i < ${min_enc_via4_met4} ABUT<90 MEASURE ALL REGION SINGULAR" |
| } |
| verbatim { |
| |
| // |
| // NSM checks |
| // |
| |
| } |
| |
| ### nsm: |
| |
| ### |
| ### Contains nitride seal mask rule value variable definitions |
| ### |
| |
| set min_wid_nsm 3.0 |
| set min_sp_nsm 4.0 |
| |
| RULECHECK nsm.WID.1 { |
| @ nsm.WID.1: Min width nsm < ${min_wid_nsm} |
| OUTPUT "INT nsm < ${min_wid_nsm} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK nsm.SP.1 { |
| @ nsm.SP.1: Min space nsm < ${min_sp_nsm} |
| OUTPUT "EXT nsm < ${min_sp_nsm} ABUT < 90 SINGULAR REGION" |
| } |
| |
| SETLAYER nsm_or_nsm_mask = "nsm OR NSMmk" |
| # JAG Added 7/9/20 |
| #SETLAYER exempt_NSM3_Cells = "(SEALID AND (DONUT diff)) OR (EXTENT CELL \"nikon*\")" |
| SETLAYER exempt_NSM3_Cells = "(SEALID AND (DONUT diff)) OR ((EXTENT CELL \"nikon*\") OR nikon_cross)" |
| SETLAYER exempt_NSM3a_Cells = "(EXTENT CELL \"s8Fab_crntic*\") OR dieCut" |
| |
| proc check_nsm_sp_ovl_enc {lay lay_name rule_num} { |
| |
| set min_nsm_sp_nonexempt_lay 1.0 |
| set min_nsm_enc_nonexempt_framebdy 3.0 |
| |
| SETLAYER ${lay}_not_exempt = "${lay} NOT exempt_NSM3_Cells" |
| |
| RULECHECK nsm.SP.${rule_num} { |
| @ nsm.SP.${rule_num}: nsm or nsm mask space to non-exempt ${lay_name} < ${min_nsm_sp_nonexempt_lay} |
| OUTPUT "EXT ${lay}_not_exempt nsm < ${min_nsm_sp_nonexempt_lay} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| OUTPUT "EXT ${lay}_not_exempt NSMmk < ${min_nsm_sp_nonexempt_lay} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK nsm.OVL.${rule_num} { |
| @ nsm.OVL.${rule_num}: $lay_name cannot overlap nsm or nsm mask |
| OUTPUT "${lay}_not_exempt AND nsm_or_nsm_mask" |
| } |
| RULECHECK nsm.ENC.${rule_num} { |
| @ nsm.ENC.${rule_num}: $lay_name enclosure by frame boundary < ${min_nsm_enc_nonexempt_framebdy} |
| SETLAYER ${lay}_not_exempt2 = "${lay} NOT exempt_NSM3a_Cells" |
| OUTPUT "ENC ${lay}_not_exempt2 frameBndr < ${min_nsm_enc_nonexempt_framebdy} MEASURE ALL ABUT < 90 SINGULAR REGION" |
| } |
| |
| } |
| |
| check_nsm_sp_ovl_enc "diffi" "diff" "2" |
| check_nsm_sp_ovl_enc "diff_fill" "diff fill" "3" |
| check_nsm_sp_ovl_enc "FOMmk" "cfom mask" "4" |
| check_nsm_sp_ovl_enc "polyi" "poly" "5" |
| check_nsm_sp_ovl_enc "P1Mmk" "poly mask" "6" |
| check_nsm_sp_ovl_enc "li_i" "li" "7" |
| check_nsm_sp_ovl_enc "LI1Mmk" "li mask" "8" |
| check_nsm_sp_ovl_enc "met1i" "met1" "9" |
| check_nsm_sp_ovl_enc "MM1mk" "met1 mask" "10" |
| check_nsm_sp_ovl_enc "met2i" "met2" "11" |
| check_nsm_sp_ovl_enc "MM2mk" "met2 mask" "12" |
| check_nsm_sp_ovl_enc "met3i" "met3" "13" |
| check_nsm_sp_ovl_enc "MM3mk" "met3 mask" "14" |
| check_nsm_sp_ovl_enc "met4i" "met4" "15" |
| check_nsm_sp_ovl_enc "MM4mk" "met4 mask" "16" |
| check_nsm_sp_ovl_enc "met5i" "met5" "17" |
| check_nsm_sp_ovl_enc "MM5mk" "met5 mask" "18" |
| |
| |
| verbatim { |
| |
| // |
| // NCM checks |
| // |
| |
| } |
| |
| ### ncm: |
| |
| ### |
| ### Contains N-Core implant rule value variable definitions |
| ### |
| |
| set ncm_peri_width 0.38 |
| set ncm_peri_space 0.38 |
| set ncm_area 0.265 |
| set ncm_holes_area 0.265 |
| set ncm_enc_pdiff 0.235 |
| set ncm_space_ndiff 0.235 |
| set ncm_space_nwell 0.38 |
| |
| SETLAYER ncmCore_drc = "(ncm AND COREID) NOT exempt_tech_CD" |
| SETLAYER ncmPeri_drc = "ncm NOT ncmCore_drc" |
| SETLAYER ncm_holes = "HOLES ncm" |
| |
| ### note rule below will never flag anything since the definition |
| ### of ndiff in peri is ndiff NOT core and the definition of |
| ### ncmCore_drc is ncm AND core: |
| |
| RULECHECK ncm.OVL.1 { |
| @ ncm.OVL.1: ncm in CORE (not exempt) must not overlap ndiff in periphery |
| OUTPUT "ncmCore_drc AND ndiff_PERI" |
| } |
| |
| RULECHECK ncm.WID.1 { |
| @ ncm.WID.1: Min ncm width in periphery < ${ncm_peri_width} |
| OUTPUT "INT ncmPeri_drc < ${ncm_peri_width} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK ncm.SP.1 { |
| @ ncm.SP.1: Min ncm spacing/notch < ${ncm_peri_space} |
| OUTPUT "EXT ncmPeri_drc < ${ncm_peri_space} ABUT < 90 SINGULAR REGION" |
| } |
| |
| RULECHECK ncm.AR.1 { |
| @ ncm.AR.1: Min ncm area < ${ncm_area} |
| OUTPUT "AREA ncm < ${ncm_area}" |
| } |
| |
| RULECHECK ncm.AR.2 { |
| @ ncm.AR.2: Min area of ncm holes < ${ncm_holes_area} |
| OUTPUT "AREA ncm_holes < ${ncm_holes_area}" |
| } |
| |
| RULECHECK ncm.ENC.1 { |
| @ ncm.ENC.1: Min enclosure of P+ diff by ncm in areaid:core (not exempt) < ${ncm_enc_pdiff} |
| SETLAYER pdiff_in_ncm_core = "(diffi AND psdm) AND ncmCore_drc" |
| OUTPUT "ENC pdiff_in_ncm_core ncmCore_drc < ${ncm_enc_pdiff} MEASURE ALL ABUT < 90 SINGULAR REGION" |
| } |
| |
| RULECHECK ncm.SP.2 { |
| @ ncm.SP.2: Min spacing of ncm in areaid:core (not exempt) to ndiff < ${ncm_space_ndiff} |
| OUTPUT "EXT ncmCore_drc (nsdm AND diffi) < ${ncm_space_ndiff} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK ncm.OVL.2 { |
| @ ncm.OVL.2: ncm in areaid:core (not exempt) must not overlap ndiff |
| OUTPUT "ncmCore_drc AND (nsdm AND diffi)" |
| } |
| |
| SETLAYER nwellOutCore = "(nwell OUTSIDE COREID) NOT TOUCH COREID" |
| |
| RULECHECK ncm.SP.3 { |
| @ ncm.SP.3: Min space of ncm in areaid:core (not exempt) to nwell outside areaid:core < ${ncm_space_nwell} |
| OUTPUT "EXT nwellOutCore ncmCore_drc < ${ncm_space_nwell} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| verbatim { |
| |
| // |
| // RPM/URPM checks |
| // |
| |
| } |
| |
| ### rpm/urpm: |
| # |
| #### |
| #### Contains resistor protect (rpm and urpm) rule value variable definitions |
| #### |
| |
| set min_space_rpm_pwbm 2.0 |
| |
| SETLAYER precResistor = "polyi AND (polyres AND ((rpm OR urpm) AND psdm))" |
| |
| set min_space_rpm_poly 0.2 |
| set min_space_urpm_poly 0.2 |
| |
| proc chk_rpm_urpm {lay} { |
| |
| set min_wid_rpm 1.27 |
| set min_space_rpm 0.84 |
| set min_enc_rpm_poly 0.2 |
| set min_space_rpm_nsdm 0.2 |
| |
| RULECHECK ${lay}.WID.1 { |
| @ ${lay}.WID.1: Min width ${lay} < ${min_wid_rpm} |
| OUTPUT "INT ${lay} < ${min_wid_rpm} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK ${lay}.SP.1 { |
| @ ${lay}.SP.1: Min space/notch ${lay} < ${min_space_rpm} |
| OUTPUT "EXT ${lay} < ${min_space_rpm} ABUT < 90 SINGULAR REGION" |
| } |
| |
| RULECHECK ${lay}.ENC.1 { |
| @ ${lay}.ENC.1: Min enclosure or precision resistor by rpm < ${min_enc_rpm_poly} |
| OUTPUT "ENC (precResistor AND ${lay}) ${lay} < ${min_enc_rpm_poly} MEASURE ALL ABUT < 90 SINGULAR REGION" |
| } |
| |
| RULECHECK ${lay}.SP.2 { |
| @ ${lay}.SP.2: Min spacing of ${lay} and nsdm < ${min_space_rpm_nsdm} |
| OUTPUT "EXT ${lay} nsdm < ${min_space_rpm_nsdm} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK ${lay}.OVL.1 { |
| @ ${lay}.OVL.1: ${lay} cannot overlap nsdm |
| OUTPUT "${lay} AND nsdm" |
| } |
| |
| RULECHECK ${lay}.OVL.2 { |
| @ ${lay}.OVL.2: poly must not straddle ${lay} |
| OUTPUT "poly CUT ${lay}" |
| } |
| } |
| |
| chk_rpm_urpm "rpm" |
| chk_rpm_urpm "urpm" |
| |
| RULECHECK rpm.SP.3 { |
| @ rpm.SP.3: Min spacing of rpm and poly < ${min_space_rpm_poly} |
| OUTPUT "EXT rpm poly < ${min_space_rpm_poly} ABUT<90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| # 5/20/21 removed exemption per PM: |
| #SETLAYER rpmExempt = "EXTENT CELL \"s8usbpdv2_csa_top\" \"s8usbpdv2_20vconn_sw_300ma_ovp_ngate_unit\" \"s8usbpdv2_20vconn_sw_300ma_ovp\" \"s8usbpdv2_20sbu_sw_300ma_ovp\" ORIGINAL" |
| #SETLAYER rpmNotXmt = "rpm NOT rpmExempt" |
| SETLAYER rpmNotXmt = "COPY rpm" |
| |
| RULECHECK rpm.SP.4 { |
| @ rpm.SP.4: Min spacing of rpm and pwell block mask (pwbm) < ${min_space_rpm_pwbm} |
| OUTPUT "EXT rpmNotXmt pwbm < ${min_space_rpm_pwbm} SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK urpm.SP.3 { |
| @ urpm.SP.3: Min spacing of urpm and poly < ${min_space_urpm_poly} |
| OUTPUT "EXT urpm poly < ${min_space_urpm_poly} ABUT<90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK rpm.OVL.3 { |
| @ rpm.OVL.3: rpm must not overlap pwell block mask (pwbm) |
| OUTPUT "rpm AND pwbm" |
| } |
| |
| RULECHECK rpm.OVL.4 { |
| @ rpm.OVL.4: rpm layer must overlap poly |
| OUTPUT "rpm NOT INTERACT polyi" |
| } |
| |
| RULECHECK urpm.OVL.3 { |
| @ urpm.OVL.3: urpm layer must overlap poly |
| OUTPUT "urpm NOT INTERACT polyi" |
| } |
| |
| |
| verbatim { |
| |
| // |
| // PRECISION RESISTOR checks |
| // |
| |
| } |
| |
| ### precision resistor: |
| # |
| #### |
| #### Contains resistor protect rule value variable definitions |
| #### |
| |
| set min_enc_prr_psdm 0.11 |
| set min_enc_prr_npc 0.095 |
| set min_space_rpm_hvtm 0.185 |
| set min_space_rpm_pwbm 2.0 |
| |
| RULECHECK prec_res.ENC.1 { |
| @ prec_res.ENC.1: Enclosure of precision resistor by psdm < ${min_enc_prr_psdm} |
| OUTPUT "ENC (precResistor AND psdm) psdm < ${min_enc_prr_psdm} MEASURE ALL ABUT < 90 SINGULAR REGION" |
| } |
| |
| SETLAYER precResis = "polyi AND (polyres AND (rpm OR urpm))" |
| |
| RULECHECK prec_res.CON.1 { |
| @ prec_res.CON.1: Precision resistor must be enclosed by psdm |
| OUTPUT "precResis NOT psdm" |
| } |
| |
| RULECHECK prec_res.ENC.2 { |
| @ prec_res.ENC.2: Enclosure of precision resitor by npc < ${min_enc_prr_npc} |
| OUTPUT "ENC (precResistor AND npc) npc < ${min_enc_prr_npc} MEASURE ALL ABUT < 90 SINGULAR REGION" |
| } |
| |
| RULECHECK prec_res.CON.2 { |
| @ prec_res.CON.2: Precision resistor must be enclosed by npc |
| OUTPUT "precResistor NOT npc" |
| } |
| |
| RULECHECK prec_res.SP.1 { |
| @ prec_res.SP.1: Space of precision resistor to hvntm < ${min_space_rpm_hvtm} |
| OUTPUT "EXT precResistor hvntm < ${min_space_rpm_hvtm} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK prec_res.OVL.1 { |
| @ prec_res.OVL.1: Precision resistor must not overlap hvntm |
| OUTPUT "precResistor AND hvntm" |
| } |
| |
| verbatim { |
| |
| // |
| // LDNTM checks |
| // |
| |
| } |
| |
| ### ldntm: |
| |
| ### |
| ### Contains lightly doped N_ tip rule value variable definitions |
| ### |
| |
| set ldntm_core_width 0.7 |
| set ldntm_core_space 0.7 |
| set ldntm_enc_ndiff 0.18 |
| set ldntm_enc_ngate 0.125 |
| set ldntm_core_space_pdiff 0.18 |
| |
| SETLAYER ldntm_and_core = "ldntm AND COREID" |
| SETLAYER ldntm_and_core_exempt = "ldntm_and_core AND exempt_tech_CD" |
| |
| RULECHECK ldntm.WID.1 { |
| @ ldntm.WID.1: Min width ldntm in areaid:core < ${ldntm_core_width} |
| OUTPUT "INT ldntm_and_core < ${ldntm_core_width} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK ldntm.SP.1 { |
| @ ldntm.SP.1: Min space/notch of ldntm in areaid:core < ${ldntm_core_space} |
| OUTPUT "EXT ldntm_and_core < ${ldntm_core_space} ABUT < 90 SINGULAR REGION" |
| } |
| |
| RULECHECK ldntm.ENC.1 { |
| @ ldntm.ENC.1: Min enclosure of ndiff by ldntm must be < ${ldntm_enc_ndiff} |
| OUTPUT "ENC \[ndiff\] ldntm_and_core < ${ldntm_enc_ndiff} SINGULAR MEASURE ALL ABUT < 90" |
| } |
| |
| RULECHECK ldntm.ENC.2 { |
| @ ldntm.ENC.2: Min enclosure of N+ FET by ldntm in areaid:core < ${ldntm_enc_ngate} |
| OUTPUT "ENC (ngate AND ldntm_and_core) ldntm_and_core < ${ldntm_enc_ngate} MEASURE ALL ABUT < 90 SINGULAR REGION" |
| } |
| |
| RULECHECK ldntm.OVL.1 { |
| @ ldntm.OVL.1: ldntm not allowed outside of areaid:core |
| OUTPUT "(ldntm NOT ldntm_and_core) NOT exempt_tech_CD" |
| } |
| |
| RULECHECK ldntm.SP.2 { |
| @ ldntm.SP.2: Min space between ldntm in areaid:core (exempt) and pdiff < ${ldntm_core_space_pdiff} |
| OUTPUT "EXT ldntm_and_core_exempt (diffi AND psdm) < ${ldntm_core_space_pdiff} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| verbatim { |
| |
| // |
| // Module Cut checks |
| // |
| |
| } |
| |
| ### moduleCut: |
| |
| ### |
| ### Contains e-test module cut rule value variable definitions |
| ### |
| set mc_space_enc_nw 0.635 |
| set mc_space_enc_diff 0.135 |
| set mc_space_enc_dnwell 3.15 |
| set mc_space_enc_lvtn 0.19 |
| set mc_space_enc_hvtp 0.19 |
| set mc_space_enc_v5 0.35 |
| set mc_space_enc_tunm 0.25 |
| set mc_space_enc_poly 0.105 |
| set mc_space_enc_npc 0.135 |
| set mc_space_enc_nsdm 0.19 |
| set mc_space_enc_psdm 0.19 |
| set mc_space_enc_licon 0.085 |
| set mc_space_enc_li 0.085 |
| set mc_space_enc_mcon 0.095 |
| set mc_space_enc_met1 0.07 |
| set mc_space_enc_lrg_met1 0.14 |
| set mc_space_enc_via 0.085 |
| set mc_space_enc_met2 0.07 |
| set mc_space_enc_lrg_met2 0.14 |
| set mc_space_enc_via2 0.1 |
| set mc_space_enc_met3 0.15 |
| set mc_space_enc_lrg_met3 0.20 |
| set mc_space_enc_via3 0.1 |
| set mc_space_enc_met4 0.15 |
| set mc_space_enc_lrg_met4 0.20 |
| set mc_space_enc_via4 0.4 |
| set mc_space_enc_met5 0.8 |
| set mc_space_enc_nsm 2.0 |
| set mc_space_enc_pad 0.635 |
| set mc_space_enc_ldntm 0.35 |
| set mc_space_enc_hvntm 0.19 |
| set mc_space_enc_ncm 0.19 |
| set mc_space_enc_rdl 5.0 |
| set mc_space_enc_hvtr 0.19 |
| set mc_space_enc_capm 0.42 |
| set mc_space_enc_cap2m 0.42 |
| |
| SETLAYER build_space = "EXTENT CELL \"*_buildspace\" ORIGINAL" |
| SETLAYER m1_lrg = "met1 WITH WIDTH >= 3.0" |
| SETLAYER m2_lrg = "met2 WITH WIDTH >= 3.0" |
| SETLAYER m3_lrg = "met3 WITH WIDTH >= 3.0" |
| SETLAYER m4_lrg = "met4 WITH WIDTH >= 3.0" |
| |
| set ::global_num 1 |
| |
| proc chk_mod_cut {layer value} { |
| |
| set layname ${layer} |
| if {${layer} == "m1_lrg"} { set layname "large met1" } |
| if {${layer} == "m2_lrg"} { set layname "large met2" } |
| if {${layer} == "m3_lrg"} { set layname "large met3" } |
| if {${layer} == "m4_lrg"} { set layname "large met4" } |
| |
| RULECHECK moduleCut.SP.${::global_num} { |
| @ moduleCut.SP.${::global_num}: Min spacing of areaid:moduleCut and (${layname} NOT build space) < ${value} |
| OUTPUT "EXT moduleCutAREA (${layer} NOT build_space) < ${value} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK moduleCut.ENC.${::global_num} { |
| @ moduleCut.ENC.${::global_num}: Min enclosure of (${layname} NOT build space) BY areaid:moduleCut < ${value} |
| OUTPUT "ENC (${layer} NOT build_space) moduleCutArea < ${value} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| incr ::global_num |
| } |
| |
| proc chk_mod_cut2 {layer value} { |
| RULECHECK moduleCut.SP.${::global_num} { |
| @ moduleCut.SP.${::global_num}: Min space of $layer BY areaid:moduleCut < ${value} |
| OUTPUT "EXT ${layer} moduleCutArea < ${value} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK moduleCut.ENC.${::global_num} { |
| @ moduleCut.ENC.${::global_num}: Min enclosure of $layer BY areaid:moduleCut < ${value} |
| OUTPUT "ENC ${layer} moduleCutArea < ${value} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| incr ::global_num |
| |
| } |
| |
| |
| chk_mod_cut "nwell" "${mc_space_enc_nw}" |
| chk_mod_cut "diff" "${mc_space_enc_diff}" |
| chk_mod_cut "dnwell" "${mc_space_enc_dnwell}" |
| chk_mod_cut "lvtn" "${mc_space_enc_lvtn}" |
| chk_mod_cut "hvtp" "${mc_space_enc_hvtp}" |
| chk_mod_cut "v5" "${mc_space_enc_v5}" |
| chk_mod_cut "tunm" "${mc_space_enc_tunm}" |
| chk_mod_cut "poly" "${mc_space_enc_poly}" |
| chk_mod_cut "npc" "${mc_space_enc_npc}" |
| chk_mod_cut "nsdm" "${mc_space_enc_nsdm}" |
| chk_mod_cut "psdm" "${mc_space_enc_psdm}" |
| chk_mod_cut "licon" "${mc_space_enc_licon}" |
| chk_mod_cut "li" "${mc_space_enc_li}" |
| chk_mod_cut "mcon" "${mc_space_enc_mcon}" |
| chk_mod_cut "met1" "${mc_space_enc_met1}" |
| chk_mod_cut "via1" "${mc_space_enc_via}" |
| chk_mod_cut "met2" "${mc_space_enc_met2}" |
| chk_mod_cut "via2" "${mc_space_enc_via2}" |
| chk_mod_cut "met3" "${mc_space_enc_met3}" |
| chk_mod_cut "via3" "${mc_space_enc_via3}" |
| chk_mod_cut "met4" "${mc_space_enc_met4}" |
| chk_mod_cut "via4" "${mc_space_enc_via4}" |
| chk_mod_cut "met5" "${mc_space_enc_met5}" |
| chk_mod_cut "nsm" "${mc_space_enc_nsm}" |
| chk_mod_cut "pad" "${mc_space_enc_pad}" |
| chk_mod_cut "ldntm" "${mc_space_enc_ldntm}" |
| chk_mod_cut "hvntm" "${mc_space_enc_hvntm}" |
| chk_mod_cut "ncm" "${mc_space_enc_ncm}" |
| chk_mod_cut "rdl" "${mc_space_enc_rdl}" |
| chk_mod_cut "hvtr" "${mc_space_enc_hvtr}" |
| chk_mod_cut "m1_lrg" "${mc_space_enc_lrg_met1}" |
| chk_mod_cut "m2_lrg" "${mc_space_enc_lrg_met2}" |
| chk_mod_cut "m3_lrg" "${mc_space_enc_lrg_met3}" |
| chk_mod_cut "m4_lrg" "${mc_space_enc_lrg_met4}" |
| chk_mod_cut2 "capm" "${mc_space_enc_capm}" |
| chk_mod_cut2 "cap2m" "${mc_space_enc_cap2m}" |
| chk_mod_cut "thkox" "${mc_space_enc_v5}" |
| |
| verbatim { |
| |
| // |
| // SEALID checks |
| // |
| |
| } |
| |
| ### SEALID: |
| |
| ### |
| ### Contains SEALID rule value variable definitions |
| ### |
| |
| set sealid_wid 6.0 |
| |
| RULECHECK sealid.WID.1 { |
| @ sealid.WID.1: Min width areaid:seal < ${sealid_wid} |
| OUTPUT "INT SEALID < ${sealid_wid} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| verbatim { |
| LAYER quad1_shape 9999 |
| POLYGON 0.000 0.000 0.001 0.001 quad1_shape // create a dummy shape whose south and west edges abut to the x-y axis in quadrant 1 |
| LAYER quad2_shape 9998 |
| POLYGON -0.001 0.000 0.000 0.001 quad2_shape // create a dummy shape whose south and east edges abut to the x-y axis in quadrant 2 |
| LAYER quad3_shape 9997 |
| POLYGON -0.001 -0.001 0.000 0.000 quad3_shape // create a dummy shape whose north and east edges abut to the x-y axis in quadrant 3 |
| LAYER quad4_shape 9996 |
| POLYGON 0.000 -0.001 0.001 0.000 quad4_shape // create a dummy shape whose north and west edges abut to the x-y axis in quadrant 4 |
| SEALIDextent = EXTENT SEALID |
| SEALIDextentAtOrigin = ( ( (SEALIDextent ENCLOSE quad1_shape) AND (SEALIDextent TOUCH quad2_shape) ) AND (SEALIDextent TOUCH quad4_shape) ) AND (SEALIDextent OUTSIDE quad3_shape) |
| } |
| |
| RULECHECK seal.CON.1 { |
| @ seal.CON.1: SEAL ring is not at origin (0,0) |
| OUTPUT "SEALIDextent NOT SEALIDextentAtOrigin" |
| } |
| |
| verbatim { |
| |
| // |
| // SCRIBE checks |
| // |
| |
| } |
| |
| ### SCRIBE: |
| |
| ### |
| ### Contains SCRIBE rule value variable definitions |
| ### |
| |
| set scribe_width 76.0 |
| |
| SETLAYER FRAMEPAD = "pad AND (FRAMEID OR moduleCutAREA)" |
| SETLAYER ETESTPAD = "WITH TEXT FRAMEPAD \"e-test\" padText" |
| SETLAYER UTESTPAD = "WITH TEXT FRAMEPAD \"u-test\" padText" |
| SETLAYER RFTESTPAD = "WITH TEXT FRAMEPAD \"RF\" padText" |
| SETLAYER EUTESTPAD = "OR ETESTPAD UTESTPAD RFTESTPAD" |
| SETLAYER FRAMEPADnoTXT = "FRAMEPAD NOT (EUTESTPAD OR laser_targetCells)" |
| SETLAYER mconOrVia = "mcon OR via1" |
| SETLAYER ModulecutAndEtest = "moduleCutAREA AND ETESTID" |
| SETLAYER dieCut150 = "CONVEX EDGE dieCut == 2 WITH LENGTH >= 150.0" |
| SETLAYER dieCutCorner = "INTERNAL \[dieCut150\] <= 150.0 INTERSECTING ONLY ABUT == 90" |
| SETLAYER dieCutCornerSz = "EXPAND EDGE dieCutCorner INSIDE BY 0.005 CORNER FILL" |
| SETLAYER dieCutCornerSzOut = "EXPAND EDGE dieCutCorner OUTSIDE BY 150 CORNER FILL" |
| SETLAYER scribeJunc150 = "frameBndr AND (dieCutCornerSzOut NOT (INTERACT dieCut dieCutCornerSz))" |
| SETLAYER realScribeLine = "frameBndr NOT (INTERACT dieCut dieCutCornerSz)" |
| |
| proc wide_layer_near_scribe {lay_list} { |
| set a 1 |
| foreach lay $lay_list { |
| set layname ${lay} |
| if {${lay} == "met1i"} { set layname "met1" } |
| if {${lay} == "met2i"} { set layname "met2" } |
| if {${lay} == "met3i"} { set layname "met3" } |
| if {${lay} == "met4i"} { set layname "met4" } |
| if {${lay} == "met5i"} { set layname "met5" } |
| if {${lay} == "diffi"} { set layname "diff" } |
| if {${lay} == "li_i"} { set layname "li" } |
| if {${lay} == "polyi"} { set layname "poly" } |
| RULECHECK scribe.CON.${a} { |
| @ scribe.CON.${a}: Wide ${layname} within 150 um of scribe junction |
| SETLAYER wide_${lay} = "WITH WIDTH ${lay} >= 10.0" |
| OUTPUT "wide_${lay} AND scribeJunc150" |
| } |
| incr a |
| } |
| } |
| |
| wide_layer_near_scribe [list "diffi" "polyi" "li_i" "met1i" "met2i" "met3i" "met4i"\ |
| "met5i" "mcon" "licon" "via1" "via2" "via3" "via4" "mm1mk" "mm2mk" "mm3mk"\ |
| "p1mmk" "fommk" "ctm1mk" "licm1mk" "li1mmk" "vimmk" "vim2mk" "mm4mk" "mm5mk" "vim3mk"\ |
| "vim4mk"] |
| |
| RULECHECK scribe.WID.1 { |
| @ scribe.WID.1: Min width of scribe line < ${scribe_width} |
| OUTPUT "INT realScribeLine < ${scribe_width} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| SETLAYER padInScribe = "(pad OR PDMmk) AND realScribeLine" |
| SETLAYER padRing = "padAreaToCheck AND pad" |
| SETLAYER scribe20_xmpt = "EXTENT CELL \"s8Fab_*\" \"cys8_*\"" |
| SETLAYER dieCutSizeLarge = "(SIZE dieCut BY 13) NOT dieCut" |
| SETLAYER dieCutSizeSmall = "(SIZE dieCut BY 3) NOT dieCut" |
| SETLAYER padAreaToCheck = "dieCutSizeLarge NOT (dieCutSizeSmall OR scribe20_xmpt)" |
| |
| RULECHECK scribe.CON.29 { |
| @ scribe.CON.29: Scribe must not enclose pad scribe protect (drawing nor mask) except for etest pads, die pad rings |
| OUTPUT "padInScribe NOT (padRing OR moduleCutArea)" |
| } |
| |
| verbatim { |
| |
| // |
| // CAPM checks |
| // |
| |
| } |
| |
| ### CAPM: |
| |
| ### |
| ### Contains CAPM rule value variable definitions |
| ### |
| |
| set wid_capm 1.0 |
| set space_capm 0.84 |
| set space_capm_bot 1.2 |
| set enc_capm_m3 0.14 |
| set enc_v3_capm 0.14 |
| set space_capm_v3 0.14 |
| set capm_aspect_ratio 20.00 |
| set space_capm_v2 0.14 |
| set space_capm_m3 0.5 |
| set area_max_capm 10000000.0 |
| |
| RULECHECK capm.CON.1 { |
| @ capm.CON.1: ccapm mask should not be used |
| OUTPUT "COPY ccapm" |
| } |
| |
| RULECHECK capm.CON.2 { |
| @ capm.CON.2: capm without met3 or met4 is prohibited |
| OUTPUT "capm NOT met3" |
| OUTPUT "capm NOT met4" |
| } |
| |
| RULECHECK capm.CON.3 { |
| @ capm.CON.3: capm without via3 is prohibited |
| OUTPUT "capm NOT INTERACT via3" |
| } |
| |
| RULECHECK capm.WID.1 { |
| @ capm.WID.1: Min capm width < ${wid_capm} |
| OUTPUT "INT capm < ${wid_capm} ABUT < 90 SINGULAR REGION" |
| } |
| |
| RULECHECK capm.SP.1 { |
| @ capm.SP.1: Min capm space < ${space_capm} |
| OUTPUT "EXT capm < ${space_capm} ABUT < 90 SINGULAR REGION" |
| } |
| |
| RULECHECK capm.SP.2 { |
| @ capm.SP.2: Min space between capm bottom plates < ${space_capm_bot} |
| SETLAYER a = "EXTERNAL m3_bot_plate < 1.2 REGION" |
| SETLAYER b = "EXTERNAL m3_bot_plate met3 < 1.2 REGION" |
| OUTPUT "(a or b) INTERACT met3 > 1" |
| OUTPUT "EXT m3_bot_plate < ${space_capm_bot} ABUT < 90 SINGULAR REGION NOT CONNECTED" |
| } |
| |
| RULECHECK capm.ENC.1 { |
| @ capm.ENC.1: Min enclosure of capm by met3 < ${enc_capm_m3} |
| OUTPUT "ENC (capm AND met3) met3 < ${enc_capm_m3} MEASURE ALL ABUT < 90 SINGULAR REGION" |
| } |
| |
| RULECHECK capm.ENC.2 { |
| @ capm.ENC.2: Min enclosure of via3 by capm < ${enc_v3_capm} |
| OUTPUT "ENC (via3 AND capm) capm < ${enc_v3_capm} MEASURE ALL ABUT < 90 SINGULAR REGION" |
| } |
| |
| RULECHECK capm.SP.3 { |
| @ capm.SP.3: Min spacing of capm and via3 < ${space_capm_v3} |
| OUTPUT "EXT capm via3 < ${space_capm_v3} ABUT < 90 SINGULAR REGION" |
| } |
| |
| RULECHECK capm.CON.4 { |
| @ capm.CON.4: Max capm aspect ratio (L/W) > ${capm_aspect_ratio} |
| OUTPUT "RECTANGLE capm ASPECT > ${capm_aspect_ratio}" |
| } |
| |
| RULECHECK capm.CON.5 { |
| @ capm.CON.5: Only rectangular capm is permitted |
| OUTPUT "NOT RECTANGLE capm" |
| } |
| |
| RULECHECK capm.SP.4 { |
| @ capm.SP.4: Min space of capm to via2 < ${space_capm_v2} |
| OUTPUT "EXT capm via2 < ${space_capm_v2} ABUT < 90 SINGULAR REGION" |
| } |
| |
| RULECHECK capm.SP.5 { |
| @ capm.SP.5: Min space of capm and met3 not overlapping capm < ${space_capm_m3} |
| OUTPUT "EXT capm (met3 NOT INTERACT capm) < ${space_capm_m3} ABUT < 90 REGION MEASURE ALL" |
| } |
| |
| RULECHECK capm.CON.6 { |
| @ capm.CON.6: capm cannot overlap via2 |
| OUTPUT "capm AND via2" |
| } |
| |
| RULECHECK capm.AR.1 { |
| @ capm.AR.1: Max area of capm > ${area_max_capm} |
| OUTPUT "AREA capm > ${area_max_capm}" |
| } |
| |
| verbatim { |
| |
| // |
| // CAP2M checks |
| // |
| |
| } |
| |
| ### CAP2M: |
| |
| ### |
| ### Contains CAP2M rule value variable definitions |
| ### |
| |
| set wid_cap2m 1.0 |
| set space_cap2m 0.84 |
| set space_cap2m_bot 1.2 |
| set enc_cap2m_m4 0.14 |
| set enc_v4_cap2m 0.20 |
| set space_cap2m_v4 0.20 |
| set cap2m_aspect_ratio 20.00 |
| set space_cap2m_v3 0.14 |
| set space_cap2m_m4 0.5 |
| set area_max_cap2m 10000000.0 |
| |
| RULECHECK cap2m.CON.1 { |
| @ cap2m.CON.1: cap2m without met4 or met5 is prohibited |
| OUTPUT "cap2m NOT met4" |
| OUTPUT "cap2m NOT met5" |
| } |
| |
| RULECHECK cap2m.CON.2 { |
| @ cap2m.CON.2: cap2m without via4 is prohibited |
| OUTPUT "cap2m NOT INTERACT via4" |
| } |
| |
| RULECHECK cap2m.WID.1 { |
| @ cap2m.WID.1: Min cap2m width < ${wid_cap2m} |
| OUTPUT "INT cap2m < ${wid_cap2m} ABUT < 90 SINGULAR REGION" |
| } |
| |
| RULECHECK cap2m.SP.1 { |
| @ cap2m.SP.1: Min cap2m space < ${space_cap2m} |
| OUTPUT "EXT cap2m < ${space_cap2m} ABUT < 90 SINGULAR REGION" |
| } |
| |
| RULECHECK cap2m.SP.2 { |
| @ cap2m.SP.2: Min space between cap2m bottom plates < ${space_cap2m_bot} |
| #SETLAYER a = "EXTERNAL m4_bot_plate < 1.2 REGION" |
| #SETLAYER b = "EXTERNAL m4_bot_plate met4 < 1.2 REGION" |
| #OUTPUT "(a or b) INTERACT met4 > 1" |
| OUTPUT "EXT m4_bot_plate < ${space_cap2m_bot} ABUT < 90 SINGULAR REGION NOT CONNECTED" |
| } |
| |
| RULECHECK cap2m.ENC.1 { |
| @ cap2m.ENC.1: Min enclosure of cap2m by met4 < ${enc_cap2m_m4} |
| OUTPUT "ENC (cap2m AND met4) met4 < ${enc_cap2m_m4} MEASURE ALL ABUT < 90 SINGULAR REGION" |
| } |
| |
| RULECHECK cap2m.ENC.2 { |
| @ cap2m.ENC.2: Min enclosure of via4 by ca2m < ${enc_v4_cap2m} |
| OUTPUT "ENC (via4 AND cap2m) cap2m < ${enc_v4_cap2m} MEASURE ALL ABUT < 90 SINGULAR REGION" |
| } |
| |
| RULECHECK cap2m.SP.3 { |
| @ cap2m.SP.3: Min spacing of cap2m and via4 < ${space_cap2m_v4} |
| OUTPUT "EXT cap2m via4 < ${space_cap2m_v4} ABUT < 90 SINGULAR REGION" |
| } |
| |
| RULECHECK cap2m.CON.3 { |
| @ cap2m.CON.3: Max cap2m aspect ratio (L/W) > ${cap2m_aspect_ratio} |
| OUTPUT "RECTANGLE cap2m ASPECT > ${cap2m_aspect_ratio}" |
| } |
| |
| RULECHECK cap2m.CON.4 { |
| @ cap2m.CON.4: Only rectangular cap2m is permitted |
| OUTPUT "NOT RECTANGLE cap2m" |
| } |
| |
| RULECHECK cap2m.SP.4 { |
| @ cap2m.SP.4: Min space of cap2m to via3 < ${space_cap2m_v3} |
| OUTPUT "EXT cap2m via3 < ${space_cap2m_v3} ABUT < 90 SINGULAR REGION" |
| } |
| |
| RULECHECK cap2m.SP.5 { |
| @ cap2m.SP.5: Min space of cap2m and met4 not overlapping cap2m < ${space_cap2m_m4} |
| OUTPUT "EXT cap2m (met4 NOT INTERACT cap2m) < ${space_cap2m_m4} ABUT < 90 REGION MEASURE ALL" |
| } |
| |
| RULECHECK cap2m.CON.5 { |
| @ cap2m.CON.5: cap2m cannot overlap via3 |
| OUTPUT "cap2m AND via3" |
| } |
| |
| RULECHECK cap2m.AR.1 { |
| @ cap2m.AR.1: Max area of cap2m is ${area_max_cap2m} |
| OUTPUT "AREA cap2m > ${area_max_cap2m}" |
| } |
| |
| verbatim { |
| |
| // |
| // HVTPM checks |
| // |
| |
| } |
| |
| ### HVTPM: |
| |
| ### |
| ### Contains chvtpm rule value variable definitions |
| ### |
| |
| set wid_chvtpm 0.38 |
| set space_chvtpm 0.38 |
| |
| SETLAYER nw_lv = "nwell NOT INTERACT (OR v5 v12 v20)" |
| SETLAYER lv_nwell_peri = "nw_lv NOT COREID" |
| SETLAYER varac_channel = "(NTAP AND poly) AND nw_lv" |
| SETLAYER varac_nwell = "INTERACT nwell varac_channel" |
| SETLAYER lv_nwell_not_varac = "nw_lv NOT varac_nwell" |
| SETLAYER lv_nwell_not_varac_not_lvtn = "nw_lv NOT lvtn" |
| SETLAYER lv_nwell_over_varac = "INTERACT nw_lv (nw_lv AND varac_channel)" |
| SETLAYER lv_nwell_over_varac_and_hvtp = "nw_lv AND hvtp" |
| SETLAYER clhvtpm_tmp = "lv_nwell_not_varac_not_lvtn OR lv_nwell_over_varac_and_hvtp" |
| SETLAYER clhvtpm = "clhvtpm_tmp OR chvtpm" |
| |
| RULECHECK chvtpm.WID.1 { |
| @ chvtpm.WID.1: Min width of CLHVTPM < ${wid_chvtpm} |
| OUTPUT "INT clhvtpm < ${wid_chvtpm} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK chvtpm.SP.1 { |
| @ chvtpm.SP.1: Min space/notch of CLHVTPM < ${space_chvtpm} |
| OUTPUT "EXT clhvtpm < ${space_chvtpm} ABUT < 90 SINGULAR REGION" |
| } |
| |
| RULECHECK chvtpm.OVL.1 { |
| @ chvtpm.OVL.1: Min enclosure of low voltage nwell not overlapping varactor channel not lvtn by CLHVTPM is 0 |
| OUTPUT "lv_nwell_not_varac_not_lvtn NOT clhvtpm" |
| } |
| |
| RULECHECK chvtpm.OVL.2 { |
| @ chvtpm.OVL.2: Min enclosure of low voltage nwell not overlapping varactor channel and hvtp by CLHVTPM is 0 |
| OUTPUT "lv_nwell_over_varac_and_hvtp NOT clhvtpm" |
| } |
| |
| verbatim { |
| |
| // |
| // LVTNM checks |
| // |
| |
| } |
| |
| ### LVTNM: |
| |
| ### |
| ### Contains clvtnm rule value variable definitions |
| ### |
| |
| set wid_lvtnm 0.38 |
| set space_lvtnm 0.38 |
| |
| SETLAYER nw_hvtp_core = "nwell AND (hvtp OR COREID)" |
| SETLAYER clvtnm_all = "OR lvtn nw_hvtp_core lv_nwell_over_varac clvtnm" |
| SETLAYER lvtnm_merge = "EXTERNAL clvtnm_all < 0.38 PARALLEL ONLY OPPOSITE REGION" |
| SETLAYER lvtnm_tmp = "clvtnm_all OR lvtnm_merge" |
| SETLAYER lvtnm_all = "lvtnm_tmp OR clvtnm" |
| SETLAYER lvtnm_peri = "lvtnm_all OUTSIDE COREID" |
| |
| RULECHECK clvtnm.WID.1 { |
| @ clvtnm.WID.1: Min width of clvtnm in periphery < ${wid_lvtnm} |
| OUTPUT "INT lvtnm_peri < ${wid_lvtnm} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK clvtnm.SP.1 { |
| @ clvtnm.SP.1: Min space/notch of clvtnm < ${space_lvtnm} |
| OUTPUT "EXT lvtnm_peri < ${space_lvtnm} ABUT < 90 SINGULAR REGION PARALLEL OPPOSITE" |
| } |
| |
| |
| verbatim { |
| |
| // |
| // NTM checks |
| // |
| |
| } |
| |
| ### NTM: |
| |
| ### |
| ### Contains cntm rule value variable definitions |
| ### |
| |
| set wid_ntm 0.84 |
| set space_ntm 0.7 |
| |
| SETLAYER nwellTmp = "COPY nwell" |
| // jag changed as thkox is the mask layer not v5 which is only a marker: |
| #SETLAYER v5_tmp = "v5 NOT COREID" |
| SETLAYER v5_tmp = "thkox NOT COREID" |
| SETLAYER ldntm_tmp = "COPY ldntm" |
| SETLAYER ntm_tmp = "NTMdg OR (nwelltmp OR (ldntm_tmp OR (v5_tmp OR (rpm OR urpm))))" |
| SETLAYER ntm_merged_tmp = "ntm_tmp OR (EXTERNAL ntm_tmp < ${space_ntm} SPACE OPPOSITE PARALLEL ONLY REGION)" |
| SETLAYER ntm_merged_tmp2 = "ntm_merged_tmp OR (EXTERNAL ntm_merged_tmp < ${space_ntm} NOTCH OPPOSITE PARALLEL ONLY REGION)" |
| SETLAYER ntm_merged = "ntm_merged_tmp2 OR (EXTERNAL ntm_merged_tmp2 < ${space_ntm} NOTCH OPPOSITE PARALLEL ONLY REGION)" |
| SETLAYER ntm_all = "COPY ntm_merged" |
| SETLAYER ntm_all_0 = "INTERNAL ntm_all (LENGTH ntm_all <= 0.0) < ${wid_ntm} REGION OPPOSITE PARALLEL ONLY" |
| SETLAYER ntm_all_1 = "ntm_all NOT (ntm_all_0 OUTSIDE ntm_tmp)" |
| SETLAYER ntm_all_2 = "COPY ntm_all_1" |
| SETLAYER ntm_all_3 = "INTERNAL ntm_all_2 (LENGTH ntm_all_2 <= 0.0) < ${wid_ntm} REGION OPPOSITE PARALLEL ONLY" |
| SETLAYER ntm_all_4 = "ntm_all_2 NOT (ntm_all_3 OUTSIDE ntm_tmp)" |
| SETLAYER ntm_all_5 = "COPY ntm_all_4" |
| SETLAYER clntm_tmp = "COPY ntm_all_5" |
| SETLAYER CLNTM = "clntm_tmp OR NTMdg" |
| |
| RULECHECK cntm.WID.1 { |
| @ cntm.WID.1: Min width CLNTM < ${wid_ntm} |
| OUTPUT "INT CLNTM < ${wid_ntm} ABUT<90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK cntm.SP.1 { |
| @ cntm.SP.1: Min space/notch CLNTM < ${space_ntm} |
| OUTPUT "EXT CLNTM < ${space_ntm} ABUT<90 SINGULAR REGION" |
| } |
| |
| RULECHECK cntm.ENC.1 { |
| @ cntm.ENC.1: Layer Nwell must be enclosed by CLNTM |
| OUTPUT "nwell NOT CLNTM" |
| } |
| |
| RULECHECK cntm.ENC.2 { |
| @ cntm.ENC.2: thkox outside core must be enclosed by CLNTM |
| OUTPUT "(thkox NOT COREID) NOT CLNTM" |
| } |
| |
| RULECHECK cntm.ENC.3 { |
| @ cntm.ENC.3: ldntm must be enclosed by CLNTM |
| OUTPUT "ldntm NOT CLNTM" |
| } |
| |
| verbatim { |
| |
| // |
| // RDL checks |
| // |
| |
| } |
| |
| ### RDL: |
| |
| ### |
| ### Contains rdl rules |
| ### |
| |
| set min_wid_rdl 10.0 |
| set min_sp_rdl 10.0 |
| set min_sp_rdl_pad 19.66 |
| set min_enc_pad_rdl 10.75 |
| set min_space_rdl_seal 15.0 |
| set min_space_rdl_pad 19.66 |
| |
| RULECHECK rdl.WID.1 { |
| @ rdl.WID.1: Min width of rdl < ${min_wid_rdl} |
| OUTPUT "INT rdl < ${min_wid_rdl} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK rdl.SP.1 { |
| @ rdl.SP.1: Min space of rdl < ${min_sp_rdl} |
| OUTPUT "EXT rdl < ${min_sp_rdl} REGION CORNER TO EDGE" |
| OUTPUT "EXT rdl < ${min_sp_rdl} ABUT < 90 REGION OPPOSITE PARALLEL ONLY" |
| } |
| |
| RULECHECK rdl.ENC.1 { |
| @ rdl.ENC.1: Min enclosure of pad by rdl (outside bump) < ${min_enc_pad_rdl} |
| OUTPUT "ENC (pad AND (rdl NOT INTERACT bump)) (rdl NOT INTERACT bump) < ${min_enc_pad_rdl} MEASURE ALL ABUT < 90 SINGULAR REGION" |
| } |
| |
| RULECHECK rdl.SP.2 { |
| @ rdl.SP.2: Min space of rdl to outer edge of scribe line < ${min_space_rdl_seal} |
| OUTPUT "ENC rdl (OR sealRing sealHoles) < ${min_space_rdl_seal} MEASURE ALL ABUT<90 SINGULAR REGION" |
| } |
| |
| RULECHECK rdl.CON.1 { |
| @ rdl.CON.1: rdl or ccu1m.mk must not overlap areaid.ft (frame boundary) |
| OUTPUT "((rdl OR CU1Mmk) AND frameBndr) NOT dieCut" |
| } |
| |
| RULECHECK rdl.SP.3 { |
| @ rdl.SP.3: Min space of rdl (outside bump) and pad < ${min_sp_rdl_pad} |
| OUTPUT "EXT (rdl NOT INTERACT bump) pad < ${min_sp_rdl_pad} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| verbatim { |
| |
| // |
| // BUMP checks |
| // |
| |
| } |
| |
| ### BUMP: |
| |
| ### |
| ### Contains bump rules |
| ### |
| |
| set min_wid_bump_400_pitch 261 |
| set min_wid_bump_400_pitch_rnd 260.5 |
| set min_max_sp_bump_400_pitch 400 |
| set min_max_sp_bump_500_pitch 500 |
| set min_wid_bump_500_pitch 310 |
| set min_wid_bump_500_pitch_rnd 309.5 |
| set min_enc_bump_seal 25.0 |
| set min_size_chip_ext_500 1000 |
| set max_size_chip_ext_500 6800 |
| set min_size_chip_ext_400_a 750 |
| set min_size_chip_ext_400_b 1000 |
| set max_size_chip_ext_400 6800 |
| |
| |
| SETLAYER bump_ctr = "EXTENTS bump CENTERS 1.0" |
| SETLAYER bump_pitch_400_rect = "EXT bump_ctr == 399 ABUT < 90 OPPOSITE PARALLEL ONLY REGION" |
| SETLAYER bump_pitch_500_rect = "EXT bump_ctr == 499 ABUT < 90 OPPOSITE PARALLEL ONLY REGION" |
| SETLAYER bump_small_pitch = "bump INTERACT bump_pitch_400_rect" |
| SETLAYER bump_large_pitch = "(bump INTERACT bump_pitch_500_rect) OR (bump NOT INTERACT bump_pitch_400_rect)" |
| |
| SETLAYER ETESTPAD_x = "pad WITH TEXT \"etest\" padText" |
| |
| RULECHECK bump.CON.1 { |
| @ bump.CON.1: Bump cannot straddle areaid:ModuleCut |
| OUTPUT "bump CUT (moduleCutAREA INTERACT ETESTPAD)" |
| } |
| |
| RULECHECK bump.WID.1 { |
| @ bump.WID.1: Min width of bump ball < ${min_wid_bump_400_pitch} |
| OUTPUT "INT bump < ${min_wid_bump_400_pitch_rnd} ABUT < 90 SINGULAR PARALLEL ONLY OPPOSITE REGION" |
| } |
| |
| RULECHECK bump.WID.2 { |
| @ bump.WID.2: Min width of bump ball for pitch > 400um is < ${min_wid_bump_500_pitch} |
| OUTPUT "INT bump_large_pitch < ${min_wid_bump_500_pitch_rnd} ABUT < 90 SINGULAR PARALLEL ONLY OPPOSITE REGION" |
| } |
| |
| RULECHECK bump.SP.1 { |
| @ bump.SP.1: Min/Max pitch spacing for bump is not ${min_max_sp_bump_400_pitch} or ${min_max_sp_bump_500_pitch} |
| OUTPUT "bump NOT INTERACT (OR bump_pitch_400_rect bump_pitch_500_rect)" |
| } |
| |
| RULECHECK bump.ENC.1 { |
| @ bump.ENC.1: Min enclosure of bump by scribe_line < ${min_enc_bump_seal} |
| OUTPUT "ENC bump (OR SEALID sealHoles) < ${min_enc_bump_seal} ABUT < 90 REGION SINGULAR" |
| } |
| |
| RULECHECK bump.CON.2 { |
| @ bump.CON.2: Min size of chip extent with 500um pitch bumps < ${min_size_chip_ext_500} |
| OUTPUT "INT (sealHoles INTERACT bump_large_pitch) < ${min_size_chip_ext_500} ABUT < 90 REGION" |
| } |
| |
| RULECHECK bump.CON.3 { |
| @ bump.CON.3: Max size of chip extent with 500um pitch bumps > ${max_size_chip_ext_500} |
| OUTPUT "RECTANGLE (sealHoles INTERACT bump_large_pitch) > ${max_size_chip_ext_500}" |
| } |
| |
| RULECHECK bump.CON.4 { |
| @ bump.CON.4: Min size of chip extent with 400um pitch bumps < ${min_size_chip_ext_400_a} BY ${min_size_chip_ext_400_b} |
| OUTPUT "RECTANGLE (sealHoles INTERACT bump_small_pitch) < ${min_size_chip_ext_400_a} BY < ${min_size_chip_ext_400_b}" |
| } |
| |
| RULECHECK bump.CON.5 { |
| @ bump.CON.5: Max size of chip extent with 400um pitch bumps > ${max_size_chip_ext_400} |
| OUTPUT "RECTANGLE sealHoles > ${max_size_chip_ext_400}" |
| } |
| |
| ### JAG 4/21/20 should the following rule be in here? |
| RULECHECK bump.CON.6 { |
| @ bump.CON.6: Chip can contain only 400 pitch or 500 pitch bumps but not both |
| OUTPUT "(sealHoles INTERACT bump_small_pitch) AND (sealHoles INTERACT bump_large_pitch)" |
| } |
| |
| verbatim { |
| |
| // |
| // UBM checks |
| // |
| |
| } |
| |
| ### UBM: |
| |
| ### |
| ### Contains under bump metal (ubm) rules |
| ### |
| |
| set min_wid_ubm_400 215.0 |
| set min_wid_ubm_500 250.0 |
| set min_enc_ubm_rdl 10.0 |
| # some round-off fudging: |
| set min_enc_ubm_rdl_calc 9.95 |
| set min_sp_ubm_seal_400 155.0 |
| |
| # account for ctr being 1um2: |
| set min_sp_ubm_calc4 154.5 |
| |
| set min_sp_ubm_seal_500 195.0 |
| # account for ctr being 1um2: |
| set min_sp_ubm_calc5 194.5 |
| |
| |
| RULECHECK ubm.CON.1 { |
| @ ubm.CON.1: ubm drawn layer cannot straddle areaid:ModuleCut layer |
| OUTPUT "ubm CUT (moduleCutAREA INTERACT ETESTPAD)" |
| } |
| |
| RULECHECK ubm.WID.1 { |
| @ ubm.WID.1: Min width of ubm on 400 pitch balls (parallel opposite edges) < ${min_wid_ubm_400} |
| OUTPUT "INT (ubm AND bump_small_pitch) < ${min_wid_ubm_400} PARALLEL ONLY OPPOSITE" |
| } |
| |
| RULECHECK ubm.WID.2 { |
| @ ubm.WID.2: Min width of ubm on 500 pitch balls (parallel opposite edges) < ${min_wid_ubm_500} |
| OUTPUT "INT (ubm AND bump_large_pitch) < ${min_wid_ubm_500} PARALLEL ONLY OPPOSITE" |
| } |
| |
| RULECHECK ubm.ENC.1 { |
| @ ubm.ENC.1: Min enclosure ubm by rdl < ${min_enc_ubm_rdl} |
| OUTPUT "ENC ubm rdl < ${min_enc_ubm_rdl_calc} ABUT < 90 REGION SINGULAR" |
| } |
| |
| RULECHECK ubm.CON.2 { |
| @ ubm.CON.2: ubm must be inside RDL |
| OUTPUT "ubm NOT rdl" |
| } |
| |
| SETLAYER ubm_ctr = "EXTENTS UBM CENTERS 1" |
| |
| RULECHECK ubm.SP.1 { |
| @ ubm.SP.1: Min space between center of 400 pitch UBM to scribe_line < ${min_sp_ubm_seal_400} |
| OUTPUT "ENC (ubm_ctr AND bump_small_pitch) (sealHoles OR SEALID) < ${min_sp_ubm_calc4} ABUT < 90 REGION SINGULAR" |
| } |
| |
| RULECHECK ubm.SP.2 { |
| @ ubm.SP.2: Min space between center of 500 pitch UBM to scribe_line < ${min_sp_ubm_seal_500} |
| OUTPUT "ENC (ubm_ctr AND bump_large_pitch) (sealHoles OR SEALID) < ${min_sp_ubm_calc5} ABUT < 90 REGION SINGULAR" |
| } |
| |
| verbatim { |
| |
| // |
| // pwbm checks |
| // |
| |
| } |
| |
| ### PWBM: |
| |
| ### |
| ### Contains pwell block mask rules |
| ### |
| |
| set min_wid_pwbm 0.84 |
| set min_space_pwbm 1.27 |
| set min_space_pwbm_hole 0.84 |
| |
| SETLAYER pwbm_v20 = "pwbm AND v20" |
| SETLAYER pwbm_holes = "HOLES pwbm_v20" |
| SETLAYER pwbm_or_pwbm_holes = "pwbm_v20 OR pwbm_holes" |
| |
| RULECHECK pwbm.WID.1 { |
| @ pwbm.WID.1: Min width of pwbm < ${min_wid_pwbm} |
| OUTPUT "INT pwbm < ${min_wid_pwbm} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK pwbm.SP.1 { |
| @ pwbm.SP.1: Min space/notch of pwbm inside v20 < ${min_space_pwbm} |
| OUTPUT "EXT pwbm_v20 < ${min_space_pwbm} ABUT < 90 SINGULAR REGION" |
| } |
| |
| RULECHECK pwbm.ENC.1 { |
| @ pwbm.ENC.1: (dnwell inside v20) must be enclosed by pwbm (exempt for pwbm holes inside dnwell) |
| OUTPUT "(dnwell and v20) NOT pwbm_or_pwbm_holes" |
| } |
| |
| RULECHECK pwbm.SP.2 { |
| @ pwbm.SP.2: Min spacing of pwbm holes inside v20 < ${min_space_pwbm_hole} |
| OUTPUT "EXT (pwbm_holes AND v20) < ${min_space_pwbm_hole} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| #RULECHECK pwbm.OVL.1 { |
| #@ pwbm.OVL.1 (pwbm.3): 20V dnwell cannot straddle pwbm |
| # OUTPUT "EXPAND EDGE ((dnwell AND V20) INSIDE EDGE pwbm) OUTSIDE BY 0.05" |
| #} |
| |
| RULECHECK pwbm.ENC.2 { |
| @ pwbm.ENC.2: Min enclosure of dnwell inside v20 by pwbm (exempt for pwbm holes inside dnwell) >= 0 |
| OUTPUT "(dnwell AND v20) NOT pwbm_or_pwbm_holes" |
| } |
| |
| |
| verbatim { |
| |
| // |
| // pwde checks |
| // |
| |
| } |
| |
| ### PWDE: |
| |
| ### |
| ### Contains pwell drain extended rules |
| ### |
| |
| set min_wid_pwde 0.84 |
| set min_space_pwde 1.27 |
| set min_enc_pwde_dnw 1.0 |
| |
| SETLAYER pwde_v20 = "pwde AND v20" |
| SETLAYER pwde_uhvi_samenet = "EXTERNAL pwde_v20 < 1.27 ABUT < 90 SINGULAR REGION CONNECTED" |
| |
| RULECHECK pwde.WID.1 { |
| @ pwde.WID.1: Min width of pwde < ${min_wid_pwde} |
| OUTPUT "INT pwde < ${min_wid_pwde} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK pwde.SP.1 { |
| @ pwde.SP.1: Min space of 20v pwde < ${min_space_pwde} |
| OUTPUT "EXT pwde_v20 < ${min_space_pwde} ABUT < 90 SINGULAR REGION CONNECTED EXCLUDE FALSE" |
| } |
| |
| RULECHECK pwde.ENC.1 { |
| @ pwde.ENC.1: Layer pwde must be enclosed by v20 |
| OUTPUT "pwde NOT v20" |
| } |
| |
| RULECHECK pwde.ENC.2 { |
| @ pwde.ENC.2: Layer pwde must be enclosed by pwbm >= 0 |
| OUTPUT "pwde NOT pwbm" |
| } |
| |
| RULECHECK pwde.ENC.3 { |
| @ pwde.ENC.3: Layer pwde must be enclosed by dnwell |
| OUTPUT "pwde NOT dnwell" |
| } |
| |
| RULECHECK pwde.ENC.4 { |
| @ pwde.ENC.4: Layer pwde enclosure by dnwell in v20 < ${min_enc_pwde_dnw} |
| OUTPUT "ENC pwde_v20 dnwell_v20 < ${min_enc_pwde_dnw} MEASURE ALL ABUT < 90 SINGULAR REGION" |
| } |
| |
| |
| verbatim { |
| |
| // |
| // nikon checks |
| // |
| |
| } |
| |
| ### NIKON: |
| |
| ### |
| ### Contains NIKON rules |
| ### |
| |
| proc chk_nikon {lay_list} { |
| foreach lay $lay_list { |
| |
| set mask ${lay} |
| if {${lay} == "FOMmk"} { set mask "cfom" } |
| if {${lay} == "DNMmk"} { set mask "cdnm" } |
| if {${lay} == "NWMmk"} { set mask "cnwm" } |
| if {${lay} == "HVTPMmk"} { set mask "chvtpm" } |
| if {${lay} == "LVTNMmk"} { set mask "clvtnm" } |
| if {${lay} == "LVOMmk"} { set mask "clvom" } |
| if {${lay} == "P1Mmk"} { set mask "cp1m" } |
| if {${lay} == "NTMmk"} { set mask "cntm" } |
| if {${lay} == "HVNTMmk"} { set mask "chvntm" } |
| if {${lay} == "LDNTMmk"} { set mask "cldntm" } |
| if {${lay} == "NPCMmk"} { set mask "cnpc" } |
| if {${lay} == "NSDMmk"} { set mask "cnsdm" } |
| if {${lay} == "PSDMmk"} { set mask "cpsdm" } |
| if {${lay} == "LICM1mk"} { set mask "clicm1" } |
| if {${lay} == "LI1Mmk"} { set mask "cli1m" } |
| if {${lay} == "CTM1mk"} { set mask "cctm1" } |
| if {${lay} == "MM1mk"} { set mask "cmm1" } |
| if {${lay} == "VIMmk"} { set mask "cviam" } |
| if {${lay} == "MM2mk"} { set mask "cmm2" } |
| if {${lay} == "NSMmk"} { set mask "cnsm" } |
| if {${lay} == "PDMmk"} { set mask "cpdm" } |
| if {${lay} == "VIM2mk"} { set mask "cviam2" } |
| if {${lay} == "MM3mk"} { set mask "cmm3" } |
| if {${lay} == "VIM3mk"} { set mask "cviam3" } |
| if {${lay} == "MM4mk"} { set mask "cmm4" } |
| if {${lay} == "VIM4mk"} { set mask "cviam4" } |
| if {${lay} == "MM5mk"} { set mask "cmm5" } |
| if {${lay} == "RPMmk"} { set mask "crpm" } |
| |
| RULECHECK nikon.${mask}.CON.1 { |
| @ nikon.${mask}.CON.1: ${lay} in the nikon cross has the wrong polarity |
| SETLAYER ${lay}_and_seal = "${lay} AND SEALID" |
| if {${lay} == "DNMmk" || ${lay} == "LVTNMmk" || ${lay} == "HVNTMmk" || ${lay} == "LDNTMmk" \ |
| || ${lay} == "NPCMmk" || ${lay} == "PDMmk"} { |
| OUTPUT "${lay}_and_seal NOT (DONUT ${lay}_and_seal)" |
| } else { |
| OUTPUT "DONUT ${lay}_and_seal" |
| } |
| } |
| |
| RULECHECK nikon.${mask}.CON.2 { |
| @ nikon.${mask}.CON.2: ${lay} is missing from the nikon cross in the layout |
| OUTPUT "INTERACT SEALID ${lay} != 4" |
| } |
| } |
| } |
| |
| chk_nikon [list "FOMmk" "DNMmk" "NWMmk" "HVTPMmk" "LVTNMmk" "LVOMmk" "P1Mmk" "NTMmk" "HVNTMmk" "LDNTMmk" \ |
| "NPCMmk" "NSDMmk" "PSDMmk" "LICM1mk" "LI1Mmk" "CTM1mk" "MM1mk" "VIMmk" "MM2mk" "NSMmk" "PDMmk" "VIM2mk" \ |
| "MM3mk" "VIM3mk" "MM4mk" "VIM4mk" "MM5mk" "RPMmk"] |
| |
| RULECHECK nikon.CON.3 { |
| @ nikon.CON.3: Nikon cross cannot be placed outside areaid:seal |
| OUTPUT "nikon_cross NOT SEALID" |
| } |
| |
| verbatim { |
| |
| // |
| // fuse checks |
| // |
| |
| } |
| |
| ### FUSE: |
| ### JAG 6/24/2021 - fuse use was prohibited per PM/SWT: |
| ### |
| RULECHECK fuse.CON.1 { |
| @ fuse.CON.1: Use of the met4/fuse layer is prohibited - contact SkyWater Technology for additional information |
| OUTPUT "COPY fuse" |
| } |
| |
| RULECHECK target.CON.1 { |
| @ target.CON.1: Use of the fuse target layer is prohibited - contact SkyWater Technology for additional information |
| OUTPUT "COPY target" |
| } |
| ### Contains fuse rules |
| ### Contains fuse rules |
| ### |
| |
| #set min_wid_fuse 0.8 |
| #set max_wid_fuse 0.8 |
| #set min_len_fuse 7.2 |
| #set max_len_fuse 7.2 |
| #set max_enc_fuse_m4 0.83 |
| #set min_space_target 2.75 |
| #set min_space_fuse_cont 1.96 |
| #set min_space_fuse_target 2.75 |
| #set min_space_target_m1 3.295 |
| #set min_space_target_li1 3.295 |
| #set min_space_target_poly 2.655 |
| #set min_space_target_tap 2.635 |
| #set min_space_target_diff 3.245 |
| #set min_space_target_nw 3.315 |
| #set min_space_target_m2 3.295 |
| #set min_space_target_met_not_shield 3.295 |
| #set min_space_target_fuse_shield 2.195 |
| #set max_space_shield_target 3.30 |
| #set min_space_fuse_m4 0.6 |
| #set max_space_fuse_m4 0.6 |
| #set min_space_target_m4 3.295 |
| #set min_space_target_m5 3.295 |
| #set fuse_shield_size_1 2.4 |
| #set fuse_shield_size_2 0.5 |
| |
| #SETLAYER m4_and_fuse = "met4 AND fuse" |
| |
| #RULECHECK fuse.ANG.1 { |
| #@ fuse.ANG.1: fuse must be rectangular |
| # OUTPUT "NOT RECTANGLE m4_and_fuse ORTHOGONAL ONLY" |
| # } |
| # |
| #RULECHECK fuse.WID.1 { |
| #@ fuse.WID.1: Min width of metal4 fuse < ${min_wid_fuse} |
| # OUTPUT "INT m4_and_fuse < ${min_wid_fuse} ABUT < 90 REGION" |
| # } |
| # |
| #RULECHECK fuse.WID.2 { |
| #@ fuse.WID.2: Max width of metal4 fuse > ${max_wid_fuse} |
| # OUTPUT "WITH WIDTH m4_and_fuse > ${max_wid_fuse}" |
| # } |
| # |
| #RULECHECK fuse.LEN.1 { |
| #@ fuse.LEN.1: Min length of metal4 fuse < ${min_len_fuse} |
| # OUTPUT "INT m4_and_fuse < ${min_len_fuse} PROJECTING < ${min_len_fuse} REGION" |
| # } |
| # |
| #RULECHECK fuse.LEN.2 { |
| #@ fuse.LEN.2: Max length of metal4 fuse > ${max_len_fuse} |
| # OUTPUT "m4_and_fuse WITH EDGE (LENGTH m4_and_fuse > ${max_len_fuse})" |
| # } |
| # |
| #RULECHECK fuse.SP.1 { |
| #@ fuse.SP.1: Min space of target < ${min_space_fuse_target} |
| # OUTPUT "EXT target < ${min_space_fuse_target} ABUT < 90 SINGULAR REGION SPACE EXCLUDE FALSE" |
| # } |
| # |
| #SETLAYER fuse_m4_size = "SIZE m4_and_fuse BY ${max_enc_fuse_m4}" |
| #SETLAYER free_met4 = "(met4 INTERACT fuse) NOT TOUCH fuse" |
| # |
| #RULECHECK fuse.ENC.1 { |
| #@ fuse.ENC.1: Max extension of met4 beyond target boundary < ${max_enc_fuse_m4} |
| # OUTPUT "fuse AND (free_met4 CUT fuse_m4_size)" |
| # } |
| # |
| #SETLAYER fuse_connect = "free_met4 NOT m4_and_fuse" |
| # |
| #RULECHECK fuse.SP.2 { |
| #@ fuse.SP.2: Min spacing of met4 connection to fuse < ${min_space_fuse_cont} |
| # OUTPUT "EXT fuse_connect < ${min_space_fuse_cont} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| # } |
| # |
| #RULECHECK fuse.SP.3 { |
| #@ fuse.SP.3: Min space of target and met1 < ${min_space_target_m1} |
| # OUTPUT "EXT target met1i < ${min_space_target_m1} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| # } |
| # |
| #RULECHECK fuse.CON.1 { |
| #@ fuse.CON.1: Layer target must not overlap met1 |
| # OUTPUT "target AND met1i" |
| # } |
| # |
| #RULECHECK fuse.SP.4 { |
| #@ fuse.SP.4: Min space of target and li < ${min_space_target_li1} |
| # OUTPUT "EXT target li_i < ${min_space_target_li1} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| # } |
| # |
| #RULECHECK fuse.CON.2 { |
| #@ fuse.CON.2: Layer target must not overlap li |
| # OUTPUT "target AND li_i" |
| # } |
| # |
| #RULECHECK fuse.SP.5 { |
| #@ fuse.SP.5: Min space of target and poly < ${min_space_target_poly} |
| # OUTPUT "EXT target polyi < ${min_space_target_poly} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| # } |
| # |
| #RULECHECK fuse.CON.3 { |
| #@ fuse.CON.3: Layer target must not overlap poly |
| # OUTPUT "target AND polyi" |
| # } |
| # |
| #RULECHECK fuse.SP.6 { |
| #@ fuse.SP.6: Min space of target and tap < ${min_space_target_tap} |
| # OUTPUT "EXT target tap < ${min_space_target_tap} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| # } |
| |
| #RULECHECK fuse.CON.4 { |
| #@ fuse.CON.4: Layer target must not overlap tap |
| # OUTPUT "target AND tap" |
| # } |
| # |
| #RULECHECK fuse.SP.7 { |
| #@ fuse.SP.7: Min space of target and diff < ${min_space_target_diff} |
| # OUTPUT "EXT target diffi < ${min_space_target_diff} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| # } |
| # |
| #RULECHECK fuse.CON.4 { |
| #@ fuse.CON.4: Layer target must not overlap diff |
| # OUTPUT "target AND diffi" |
| # } |
| # |
| #RULECHECK fuse.SP.8 { |
| #@ fuse.SP.8: Min space of target and nwell < ${min_space_target_nw} |
| # OUTPUT "EXT target nwell < ${min_space_target_nw} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| # } |
| # |
| #RULECHECK fuse.CON.5 { |
| #@ fuse.CON.5: Layer target must not overlap nwell |
| # OUTPUT "target AND nwell" |
| # } |
| # |
| #RULECHECK fuse.SP.9 { |
| #@ fuse.SP.9: Min space of target and met2 < ${min_space_target_m2} |
| # OUTPUT "EXT target met2i < ${min_space_target_m2} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| # } |
| # |
| #RULECHECK fuse.CON.6 { |
| #@ fuse.CON.6: Layer target must not overlap met2 |
| # OUTPUT "target AND met2i" |
| # } |
| # |
| #SETLAYER floatingMetal = "met4 NOT (NOT TOUCH (INTERACT met4 via3) via3)" |
| #SETLAYER shieldArea = "SIZE target BY 3.3" |
| #SETLAYER fuseShieldMetal = "NOT TOUCH (INTERACT floatingMetal shieldArea) shieldArea" |
| #SETLAYER fuseShield = "RECTANGLE fuseShieldMetal == ${fuse_shield_size_1} BY == ${fuse_shield_size_2}" |
| # |
| #RULECHECK fuse.CON.7 { |
| #@ fuse.CON.7: Fuse shield should be ${fuse_shield_size_1}X${fuse_shield_size_2} |
| # OUTPUT "((EXTERNAL target floatingMetal <= 3.295 ABUT < 90 SINGULAR REGION) COINCIDENT EDGE floatingMetal) NOT COINCIDENT EDGE fuseShield" |
| # } |
| # |
| #SETLAYER non_fuse_met4 = "met4 NOT fuse" |
| #SETLAYER end_fuse = "fuse COINCIDENT EDGE non_fuse_met4" |
| #SETLAYER end_fuse_size = "EXPAND EDGE end_fuse OUTSIDE BY 0.005" |
| #SETLAYER met4_not_fuse = "(met4 NOT (fuse OR fuseShield)) OUTSIDE end_fuse_size" |
| # |
| #RULECHECK fuse.SP.10 { |
| #@ fuse.SP.10: Min space of target and (met4 not fuse) < ${min_space_target_m4} |
| # OUTPUT "EXT target met4_not_fuse < ${min_space_target_m4} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| # } |
| # |
| #SETLAYER fuse_group = "m4_and_fuse INTERACT (EXT target <= 3.995 ABUT < 90 REGION)" |
| #SETLAYER single_fuse = "m4_and_fuse NOT fuse_group" |
| #SETLAYER non_isolated_fuse_a = "(EXT single_fuse met4_not_fuse < 4.0 REGION) OUTSIDE non_fuse_met4" |
| #SETLAYER non_isolated_fuse_b = "single_fuse COINCIDENT OUTSIDE EDGE non_isolated_fuse_a" |
| # |
| #RULECHECK fuse.SP.11 { |
| #@ fuse.SP.11: Min space of target and fuse shield < ${min_space_target_fuse_shield} |
| # OUTPUT "EXT target fuseShield < ${min_space_target_fuse_shield} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| # } |
| # |
| #RULECHECK fuse.SP.12 { |
| #@ fuse.SP.12: Max space of target and fuse shield > ${max_space_shield_target} |
| # SETLAYER fuse_sp_12_good = "EXT non_isolated_fuse_b fuseShield <= 2.9 REGION" |
| # OUTPUT "((EXPAND EDGE non_isolated_fuse_b OUTSIDE BY 0.005) NOT INTERACT fuse_sp_12_good) COINCIDENT OUTSIDE EDGE single_fuse" |
| # } |
| # |
| #RULECHECK fuse.CON.8 { |
| #@ fuse.CON.8: Fuse shield is allowed for non_isolated fuse edges ONLY |
| # OUTPUT "fuseShield OUTSIDE non_isolated_fuse_a" |
| # } |
| # |
| #RULECHECK fuse.CON.9 { |
| #@ fuse.CON.9: Fuse shield is required between perimeter metal and non-isolated fuse edges |
| # OUTPUT "non_isolated_fuse_a NOT ((non_isolated_fuse_a INTERACT fuseShield) NOT TOUCH fuseShield)" |
| # } |
| # |
| #RULECHECK fuse.SP.13 { |
| #@ fuse.SP.13: Min and max space between fuse shield and met4 must be == 0.6 |
| # SETLAYER shieldedMetal = "EXPAND EDGE ((met4_not_fuse NOT fuseShield) COINCIDENT OUTSIDE EDGE non_isolated_fuse_a) INSIDE BY 0.005" |
| # SETLAYER fuse_sp_12_good = "EXT fuseShield shieldedMetal >= 0.595 <= 0.605 OPPOSITE REGION" |
| # OUTPUT "shieldedMetal NOT INTERACT fuse_sp_12_good" |
| # } |
| # |
| #RULECHECK fuse.CON.10 { |
| #@ fuse.CON.10: Only one fuse allowed per met4 line |
| # OUTPUT "free_met4 INTERACT (free_met4 AND fuse) > 1" |
| # } |
| # |
| #RULECHECK fuse.SP.14 { |
| #@ fuse.SP.14: Min space of target and met5 < ${min_space_target_m5} |
| # OUTPUT "EXT target met5i < ${min_space_target_m5} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| # } |
| # |
| #RULECHECK fuse.CON.11 { |
| #@ fuse.CON.11: Layer target must not overlap met5 |
| # OUTPUT "target AND met5i" |
| # } |
| |
| verbatim { |
| |
| // |
| // thkox checks |
| // |
| |
| } |
| |
| ### TOX: |
| |
| ### |
| ### Contains thkox rules |
| ### |
| |
| set min_wid_thkox_peri 0.6 |
| set min_space_thkox_peri 0.7 |
| set min_space_thkox_nw 0.7 |
| set min_width_thkox_core 0.15 |
| |
| RULECHECK thkox.WID.1 { |
| @ thkox.WID.1: Min width of thkox outside areaid:core < ${min_wid_thkox_peri} |
| OUTPUT "INT (thkox NOT COREID) < ${min_wid_thkox_peri} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK thkox.WID.2 { |
| @ thkox.WID.2: Min width of diff inside thkox in areaid:CORE < ${min_width_thkox_core} |
| OUTPUT "INTERNAL ((diffi AND thkox) AND COREID) < ${min_width_thkox_core} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK thkox.SP.1 { |
| @ thkox.SP.1: Min space/notch of thkox in periphery < ${min_space_thkox_peri} |
| OUTPUT "EXT (thkox NOT COREID) < ${min_space_thkox_peri} ABUT < 90 SINGULAR REGION" |
| } |
| |
| RULECHECK thkox.OVL.1 { |
| @ thkox.OVL.1: Layer thkox must not overlap layer tunm |
| OUTPUT "thkox AND tunm" |
| } |
| |
| RULECHECK thkox.SP.2 { |
| @ thkox.SP.2: Min spacing of non-butting thkox and nwell < ${min_space_thkox_nw} |
| SETLAYER non_coin_thkox_nwell_edges = "thkox NOT COINCIDENT EDGE nwell" |
| OUTPUT "EXT non_coin_thkox_nwell_edges nwell < ${min_space_thkox_nw} ABUT < 90 REGION EXCLUDE FALSE" |
| } |
| |
| ### |
| #find the highest voltage marker on nwell and use it for NW voltage checks: |
| SETLAYER nw_v20 = "nwell INTERACT (nwell AND v20)" |
| SETLAYER nw_not_v20 = "nwell NOT nw_v20" |
| SETLAYER nw_v12 = "nw_not_v20 INTERACT (nw_not_v20 AND v12)" |
| SETLAYER nw_not_v12_or_v12 = "nwell NOT (OR nw_v20 nw_v12)" |
| SETLAYER nw_v5 = "nwell INTERACT (nw_not_v12_or_v12 and v5)" |
| SETLAYER nw_nom = "nwell NOT (OR nw_v20 nw_v12 nw_v5)" |
| ### |
| |
| ### V5: |
| |
| ### |
| ### Contains v5 rules |
| ### |
| |
| set min_wid_v5 0.02 |
| set min_space_v5nw 2.0 |
| |
| verbatim { |
| // build the 5 volt network starting with v5 markers which can be over nw, diff, ptub, or poly, |
| |
| nsd_v5 = nsd AND v5 |
| psd_v5 = psd AND v5 |
| poly_v5 = poly AND v5 |
| ptub_v5 = ptub AND v5 |
| |
| // nets connect to v5 nwell |
| v5_net_1a = NET AREA RATIO nwell nw_v5 > 0 |
| v5_net_1b = NET AREA RATIO pwell nw_v5 > 0 |
| v5_net_1c = NET AREA RATIO ptub nw_v5 > 0 |
| v5_net_1d = NET AREA RATIO nsd nw_v5 > 0 |
| v5_net_1e = NET AREA RATIO psd nw_v5 > 0 |
| v5_net_1f = NET AREA RATIO poly nw_v5 > 0 |
| v5_net_1g = NET AREA RATIO li nw_v5 > 0 |
| v5_net_1h = NET AREA RATIO met1 nw_v5 > 0 |
| v5_net_1i = NET AREA RATIO met2 nw_v5 > 0 |
| v5_net_1j = NET AREA RATIO met3 nw_v5 > 0 |
| v5_net_1k = NET AREA RATIO met4 nw_v5 > 0 |
| v5_net_1l = NET AREA RATIO met5 nw_v5 > 0 |
| v5_net_1 = OR v5_net_1a v5_net_1b v5_net_1c v5_net_1d v5_net_1e v5_net_1f v5_net_1g v5_net_1h v5_net_1i v5_net_1j v5_net_1k v5_net_1l |
| |
| // nets connect to v5 nsd |
| v5_net_2a = NET AREA RATIO nwell nsd_v5 > 0 |
| v5_net_2b = NET AREA RATIO pwell nsd_v5 > 0 |
| v5_net_2c = NET AREA RATIO ptub nsd_v5 > 0 |
| v5_net_2d = NET AREA RATIO nsd nsd_v5 > 0 |
| v5_net_2e = NET AREA RATIO psd nsd_v5 > 0 |
| v5_net_2f = NET AREA RATIO poly nsd_v5 > 0 |
| v5_net_2g = NET AREA RATIO li nsd_v5 > 0 |
| v5_net_2h = NET AREA RATIO met1 nsd_v5 > 0 |
| v5_net_2i = NET AREA RATIO met2 nsd_v5 > 0 |
| v5_net_2j = NET AREA RATIO met3 nsd_v5 > 0 |
| v5_net_2k = NET AREA RATIO met4 nsd_v5 > 0 |
| v5_net_2l = NET AREA RATIO met5 nsd_v5 > 0 |
| v5_net_2 = OR v5_net_2a v5_net_2b v5_net_2c v5_net_2d v5_net_2e v5_net_2f v5_net_2g v5_net_2h v5_net_2i v5_net_2j v5_net_2k v5_net_2l |
| |
| // nets connect to v5 psd |
| v5_net_3a = NET AREA RATIO nwell psd_v5 > 0 |
| v5_net_3b = NET AREA RATIO pwell psd_v5 > 0 |
| v5_net_3c = NET AREA RATIO ptub psd_v5 > 0 |
| v5_net_3d = NET AREA RATIO nsd psd_v5 > 0 |
| v5_net_3e = NET AREA RATIO psd psd_v5 > 0 |
| v5_net_3f = NET AREA RATIO poly psd_v5 > 0 |
| v5_net_3g = NET AREA RATIO li psd_v5 > 0 |
| v5_net_3h = NET AREA RATIO met1 psd_v5 > 0 |
| v5_net_3i = NET AREA RATIO met2 psd_v5 > 0 |
| v5_net_3j = NET AREA RATIO met3 psd_v5 > 0 |
| v5_net_3k = NET AREA RATIO met4 psd_v5 > 0 |
| v5_net_3l = NET AREA RATIO met5 psd_v5 > 0 |
| v5_net_3 = OR v5_net_3a v5_net_3b v5_net_3c v5_net_3d v5_net_3e v5_net_3f v5_net_3g v5_net_3h v5_net_3i v5_net_3j v5_net_3k v5_net_3l |
| |
| // nets connect to v5 poly |
| v5_net_4a = NET AREA RATIO nwell poly_v5 > 0 |
| v5_net_4b = NET AREA RATIO pwell poly_v5 > 0 |
| v5_net_4c = NET AREA RATIO ptub poly_v5 > 0 |
| v5_net_4d = NET AREA RATIO nsd poly_v5 > 0 |
| v5_net_4e = NET AREA RATIO psd poly_v5 > 0 |
| v5_net_4f = NET AREA RATIO poly poly_v5 > 0 |
| v5_net_4g = NET AREA RATIO li poly_v5 > 0 |
| v5_net_4h = NET AREA RATIO met1 poly_v5 > 0 |
| v5_net_4i = NET AREA RATIO met2 poly_v5 > 0 |
| v5_net_4j = NET AREA RATIO met3 poly_v5 > 0 |
| v5_net_4k = NET AREA RATIO met4 poly_v5 > 0 |
| v5_net_4l = NET AREA RATIO met5 poly_v5 > 0 |
| v5_net_4 = OR v5_net_4a v5_net_4b v5_net_4c v5_net_4d v5_net_4e v5_net_4f v5_net_4g v5_net_4h v5_net_4i v5_net_4j v5_net_4k v5_net_4l |
| |
| // nets connect to v5 ptub |
| v5_net_5a = NET AREA RATIO nwell ptub_v5 > 0 |
| v5_net_5b = NET AREA RATIO pwell ptub_v5 > 0 |
| v5_net_5c = NET AREA RATIO ptub ptub_v5 > 0 |
| v5_net_5d = NET AREA RATIO nsd ptub_v5 > 0 |
| v5_net_5e = NET AREA RATIO psd ptub_v5 > 0 |
| v5_net_5f = NET AREA RATIO poly ptub_v5 > 0 |
| v5_net_5g = NET AREA RATIO li ptub_v5 > 0 |
| v5_net_5h = NET AREA RATIO met1 ptub_v5 > 0 |
| v5_net_5i = NET AREA RATIO met2 ptub_v5 > 0 |
| v5_net_5j = NET AREA RATIO met3 ptub_v5 > 0 |
| v5_net_5k = NET AREA RATIO met4 ptub_v5 > 0 |
| v5_net_5l = NET AREA RATIO met5 ptub_v5 > 0 |
| v5_net_5 = OR v5_net_5a v5_net_5b v5_net_5c v5_net_5d v5_net_5e v5_net_5f v5_net_5g v5_net_5h v5_net_5i v5_net_5j v5_net_5k v5_net_5l |
| |
| v5_net = OR v5_net_1 v5_net_2 v5_net_3 v5_net_4 v5_net_5 |
| |
| } |
| |
| SETLAYER sd_not_de = "((nsd OR psd) NOT ENID) NOT v5" |
| SETLAYER sd_v5 = "v5_net_2 OR v5_net_3" |
| |
| RULECHECK v5.WID.1 { |
| @ v5.WID.1: Min width of v5 < ${min_wid_v5} |
| OUTPUT "INT v5 < ${min_wid_v5} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK v5.OVL.1 { |
| @ v5.OVL.1: Layer v5 must not overlap areaid:core |
| OUTPUT "v5 INTERACT (v5 AND COREID)" |
| } |
| |
| RULECHECK v5.OVL.2 { |
| @ v5.OVL.2: Gate inside v5 must overlap thkox |
| OUTPUT "(((poly and diff) NOT (npn and v5)) INTERACT v5) NOT thkox" |
| } |
| |
| #RULECHECK v5.OVL.3 { |
| #@ v5.OVL.3: Poly connected to same net as a v5 source/drain must be overlapped by v5 |
| # OUTPUT "((v5_net_3f OR v5_net_2f) AND (poly NOT INTERACT polyres)) NOT INTERACT v5" |
| # } |
| |
| RULECHECK v5.OVL.4 { |
| @ v5.OVL.4: Layer v5 must not straddle v5 src/drn |
| OUTPUT "(sd_v5 AND diff) CUT v5" |
| } |
| |
| RULECHECK v5.OVL.5 { |
| @ v5.OVL.5: Layer v5 must not straddle v5 gate |
| OUTPUT "((poly AND diff) INTERACT v5) CUT v5" |
| } |
| |
| # later JAG moved all NW (any voltage) spacing rules to nwell section: |
| # removed 7/12/21 as it is covered by hnwell.SP.1: |
| #RULECHECK v5.SP.1 { |
| #@ v5.SP.1: Min spacing or v5 nwell and non-5v nwell < ${min_space_v5nw} |
| # SETLAYER nwell_v5 = OR v5_net_1a v5_net_2a v5_net_3a v5_net_4a v5_net_5a |
| # #SETLAYER nwell_v5_2 = OR v5_net_6a v5_net_7a v5_net_8a v5_net_9a v5_net_10a |
| # #SETLAYER nwell_v5 = OR nwell_v5_1 nwell_v5_2 v5_net_11a |
| # SETLAYER nwell_not_v5 = nwell NOT nwell_v5 |
| # OUTPUT "EXT nwell_v5 nwell_not_v5 < ${min_space_v5nw} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| # } |
| |
| # JAG removed rules as we do not mark metals with voltage markers |
| #proc chk_ovlp_v5_mark {lay_list} { |
| #set a 6 |
| # foreach lay $lay_list { |
| # RULECHECK v5.OVL.${a} { |
| # @ v5.OVL.${a}: v5 marker must be inside ${lay} |
| # OUTPUT "v5 INTERACT ((${lay} CUT (v5 NOT INTERACT thkox)) NOT v5_net)" |
| # } |
| #incr a |
| # } |
| #} |
| |
| #chk_ovlp_v5_mark [list "li" "met1" "met2" "met3" "met4" "met5" ] |
| |
| RULECHECK v5.OVL.6 { |
| @ v5.OVL.6: V5 must not straddle nwell |
| OUTPUT "v5 INSIDE EDGE nwell" |
| } |
| |
| RULECHECK v5.CON.9 { |
| @ v5.CON.9: v5 over diff must overlap thkox |
| OUTPUT "(v5 AND diffi) NOT thkox" |
| } |
| |
| verbatim { |
| |
| // |
| // V12 checks |
| // |
| |
| } |
| |
| ### V12: |
| |
| ### |
| ### Contains v12 rules |
| ### |
| |
| set min_wid_v12 0.02 |
| #set min_space_v12nw 11.24 |
| |
| verbatim { |
| // build the 12 v network starting with v12 markers which can be over nw, diff, ptub, or poly |
| nsd_v12 = nsd AND v12 |
| psd_v12 = psd AND v12 |
| poly_v12 = poly AND v12 |
| ptub_v12 = ptub AND v12 |
| |
| v12_net_1a = NET AREA RATIO nwell nw_v12 > 0 |
| v12_net_1b = NET AREA RATIO pwell nw_v12 > 0 |
| v12_net_1c = NET AREA RATIO ptub nw_v12 > 0 |
| v12_net_1d = NET AREA RATIO nsd nw_v12 > 0 |
| v12_net_1e = NET AREA RATIO psd nw_v12 > 0 |
| v12_net_1f = NET AREA RATIO poly nw_v12 > 0 |
| v12_net_1g = NET AREA RATIO li nw_v12 > 0 |
| v12_net_1h = NET AREA RATIO met1 nw_v12 > 0 |
| v12_net_1i = NET AREA RATIO met2 nw_v12 > 0 |
| v12_net_1j = NET AREA RATIO met3 nw_v12 > 0 |
| v12_net_1k = NET AREA RATIO met4 nw_v12 > 0 |
| v12_net_1l = NET AREA RATIO met5 nw_v12 > 0 |
| v12_net_1 = OR v12_net_1a v12_net_1b v12_net_1c v12_net_1d v12_net_1e v12_net_1f v12_net_1g v12_net_1h v12_net_1i v12_net_1j v12_net_1k v12_net_1l |
| |
| v12_net_2a = NET AREA RATIO nwell nsd_v12 > 0 |
| v12_net_2b = NET AREA RATIO pwell nsd_v12 > 0 |
| v12_net_2c = NET AREA RATIO ptub nsd_v12 > 0 |
| v12_net_2d = NET AREA RATIO nsd nsd_v12 > 0 |
| v12_net_2e = NET AREA RATIO psd nsd_v12 > 0 |
| v12_net_2f = NET AREA RATIO poly nsd_v12 > 0 |
| v12_net_2g = NET AREA RATIO li nsd_v12 > 0 |
| v12_net_2h = NET AREA RATIO met1 nsd_v12 > 0 |
| v12_net_2i = NET AREA RATIO met2 nsd_v12 > 0 |
| v12_net_2j = NET AREA RATIO met3 nsd_v12 > 0 |
| v12_net_2k = NET AREA RATIO met4 nsd_v12 > 0 |
| v12_net_2l = NET AREA RATIO met5 nsd_v12 > 0 |
| v12_net_2 = OR v12_net_2a v12_net_2b v12_net_2c v12_net_2d v12_net_2e v12_net_2f v12_net_2g v12_net_2h v12_net_2i v12_net_2j v12_net_2k v12_net_2l |
| |
| v12_net_3a = NET AREA RATIO nwell psd_v12 > 0 |
| v12_net_3b = NET AREA RATIO pwell psd_v12 > 0 |
| v12_net_3c = NET AREA RATIO ptub psd_v12 > 0 |
| v12_net_3d = NET AREA RATIO nsd psd_v12 > 0 |
| v12_net_3e = NET AREA RATIO psd psd_v12 > 0 |
| v12_net_3f = NET AREA RATIO poly psd_v12 > 0 |
| v12_net_3g = NET AREA RATIO li psd_v12 > 0 |
| v12_net_3h = NET AREA RATIO met1 psd_v12 > 0 |
| v12_net_3i = NET AREA RATIO met2 psd_v12 > 0 |
| v12_net_3j = NET AREA RATIO met3 psd_v12 > 0 |
| v12_net_3k = NET AREA RATIO met4 psd_v12 > 0 |
| v12_net_3l = NET AREA RATIO met5 psd_v12 > 0 |
| v12_net_3 = OR v12_net_3a v12_net_3b v12_net_3c v12_net_3d v12_net_3e v12_net_3f v12_net_3g v12_net_3h v12_net_3i v12_net_3j v12_net_3k v12_net_3l |
| |
| v12_net_4a = NET AREA RATIO nwell poly_v12 > 0 |
| v12_net_4b = NET AREA RATIO pwell poly_v12 > 0 |
| v12_net_4c = NET AREA RATIO ptub poly_v12 > 0 |
| v12_net_4d = NET AREA RATIO nsd poly_v12 > 0 |
| v12_net_4e = NET AREA RATIO psd poly_v12 > 0 |
| v12_net_4f = NET AREA RATIO poly poly_v12 > 0 |
| v12_net_4g = NET AREA RATIO li poly_v12 > 0 |
| v12_net_4h = NET AREA RATIO met1 poly_v12 > 0 |
| v12_net_4i = NET AREA RATIO met2 poly_v12 > 0 |
| v12_net_4j = NET AREA RATIO met3 poly_v12 > 0 |
| v12_net_4k = NET AREA RATIO met4 poly_v12 > 0 |
| v12_net_4l = NET AREA RATIO met5 poly_v12 > 0 |
| v12_net_4 = OR v12_net_4a v12_net_4b v12_net_4c v12_net_4d v12_net_4e v12_net_4f v12_net_4g v12_net_4h v12_net_4i v12_net_4j v12_net_4k v12_net_4l |
| |
| v12_net_5a = NET AREA RATIO nwell ptub_v12 > 0 |
| v12_net_5b = NET AREA RATIO pwell ptub_v12 > 0 |
| v12_net_5c = NET AREA RATIO ptub ptub_v12 > 0 |
| v12_net_5d = NET AREA RATIO nsd ptub_v12 > 0 |
| v12_net_5e = NET AREA RATIO psd ptub_v12 > 0 |
| v12_net_5f = NET AREA RATIO poly ptub_v12 > 0 |
| v12_net_5g = NET AREA RATIO li ptub_v12 > 0 |
| v12_net_5h = NET AREA RATIO met1 ptub_v12 > 0 |
| v12_net_5i = NET AREA RATIO met2 ptub_v12 > 0 |
| v12_net_5j = NET AREA RATIO met3 ptub_v12 > 0 |
| v12_net_5k = NET AREA RATIO met4 ptub_v12 > 0 |
| v12_net_5l = NET AREA RATIO met5 ptub_v12 > 0 |
| v12_net_5 = OR v12_net_5a v12_net_5b v12_net_5c v12_net_5d v12_net_5e v12_net_5f v12_net_5g v12_net_5h v12_net_5i v12_net_5j v12_net_5k v12_net_5l |
| |
| } |
| |
| SETLAYER sd_v12 = "v12_net_2 OR v12_net_3" |
| |
| RULECHECK v12.CON.1 { |
| @ v12.CON.1: diff outside areaid:extendedDrain must not be connected to src/drn inside v12 |
| OUTPUT "sd_not_de AND ((sd_v12 AND li) AND licon)" |
| } |
| |
| RULECHECK v12.WID.1 { |
| @ v12.WID.1: Min width of v12 < ${min_wid_v12} |
| OUTPUT "INT v12 < ${min_wid_v12} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK v12.OVL.1 { |
| @ v12.OVL.1: Layer v12 must not overlap areaid:core |
| OUTPUT "v12 INTERACT (v12 AND COREID)" |
| } |
| |
| RULECHECK v12.OVL.2 { |
| @ v12.OVL.2: A v12 gate must overlap thkox |
| OUTPUT "((poly and diff) INTERACT v12) NOT thkox" |
| } |
| |
| RULECHECK v12.OVL.3 { |
| @ v12.OVL.3: Poly connected to same net as a v12 source/drain must be overlapped by v12 |
| OUTPUT "((v12_net_3f OR v12_net_2f) AND (poly NOT INTERACT polyres)) NOT INTERACT v12" |
| } |
| |
| # deleted - duplicate of next rule - renumbered later OVL rules JAG |
| #RULECHECK v12.OVL.4 { |
| #@ v12.OVL.4: Layer v12 must not straddle v12 src/drn (except in V12 extended drain devices) |
| # OUTPUT "(v12 NOT ENID) CUT sd_v12" |
| # } |
| |
| RULECHECK v12.OVL.4 { |
| @ v12.OVL.5: Layer v12 must not straddle v12 src/drn (except in V12 extended drain devices) |
| OUTPUT "(v12 NOT ENID) CUT (sd_v12 AND (nsd OR psd))" |
| } |
| |
| RULECHECK v12.OVL.5 { |
| @ v12.OVL.6: Layer v12 overlapping v12 src/drn must not overlap poly (except in V12 extended drain devices) |
| OUTPUT "((v12 NOT ENID) INTERACT sd_v12) AND poly" |
| } |
| |
| RULECHECK v12.OVL.6 { |
| @ v12.OVL.7: Layer v12 must not straddle v12 poly (except in V12 extended drain devices) |
| OUTPUT "(v12 NOT INTERACT ENID) CUT ((polyi NOT INSIDE v12) INTERACT v12)" |
| } |
| |
| #RULECHECK v12.SP.1 { |
| #@ v12.SP.1: Min spacing or v12 nwell and non-12v nwell < ${min_space_v12nw} |
| # OUTPUT "EXT (nwell AND v12_net_1) (nwell NOT v12_net_1) < ${min_space_v12nw} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| # } |
| |
| RULECHECK v12.CON.6 { |
| @ v12.CON.6: v12 must not overlap v20 |
| OUTPUT "v12 AND v20" |
| } |
| |
| RULECHECK v12.CON.9 { |
| @ v12.CON.9: v12 over diff must overlap thkox |
| OUTPUT "(v12 AND diffi) NOT thkox" |
| } |
| |
| verbatim { |
| |
| // |
| // v20 checks |
| // |
| } |
| |
| ### V20: |
| |
| ### |
| ### Contains v20 rules |
| ### |
| |
| verbatim { |
| |
| // build the 20 v network starting with v20 markers which can be over nw, diff, ptub or poly |
| nsd_v20 = nsd AND v20 |
| psd_v20 = psd AND v20 |
| poly_v20 = poly AND v20 |
| ptub_v20 = ptub AND v20 |
| |
| v20_net_1a = NET AREA RATIO nwell nw_v20 > 0 |
| v20_net_1b = NET AREA RATIO pwell nw_v20 > 0 |
| v20_net_1c = NET AREA RATIO ptub nw_v20 > 0 |
| v20_net_1d = NET AREA RATIO nsd nw_v20 > 0 |
| v20_net_1e = NET AREA RATIO psd nw_v20 > 0 |
| v20_net_1f = NET AREA RATIO poly nw_v20 > 0 |
| v20_net_1g = NET AREA RATIO li nw_v20 > 0 |
| v20_net_1h = NET AREA RATIO met1 nw_v20 > 0 |
| v20_net_1i = NET AREA RATIO met2 nw_v20 > 0 |
| v20_net_1j = NET AREA RATIO met3 nw_v20 > 0 |
| v20_net_1k = NET AREA RATIO met4 nw_v20 > 0 |
| v20_net_1l = NET AREA RATIO met5 nw_v20 > 0 |
| v20_net_1 = OR v20_net_1a v20_net_1b v20_net_1c v20_net_1d v20_net_1e v20_net_1f v20_net_1g v20_net_1h v20_net_1i v20_net_1j v20_net_1k v20_net_1l |
| |
| v20_net_2a = NET AREA RATIO nwell nsd_v20 > 0 |
| v20_net_2b = NET AREA RATIO pwell nsd_v20 > 0 |
| v20_net_2c = NET AREA RATIO ptub nsd_v20 > 0 |
| v20_net_2d = NET AREA RATIO nsd nsd_v20 > 0 |
| v20_net_2e = NET AREA RATIO psd nsd_v20 > 0 |
| v20_net_2f = NET AREA RATIO poly nsd_v20 > 0 |
| v20_net_2g = NET AREA RATIO li nsd_v20 > 0 |
| v20_net_2h = NET AREA RATIO met1 nsd_v20 > 0 |
| v20_net_2i = NET AREA RATIO met2 nsd_v20 > 0 |
| v20_net_2j = NET AREA RATIO met3 nsd_v20 > 0 |
| v20_net_2k = NET AREA RATIO met4 nsd_v20 > 0 |
| v20_net_2l = NET AREA RATIO met5 nsd_v20 > 0 |
| v20_net_2 = OR v20_net_2a v20_net_2b v20_net_2c v20_net_2d v20_net_2e v20_net_2f v20_net_2g v20_net_2h v20_net_2i v20_net_2j v20_net_2k v20_net_2l |
| |
| v20_net_3a = NET AREA RATIO nwell psd_v20 > 0 |
| v20_net_3b = NET AREA RATIO pwell psd_v20 > 0 |
| v20_net_3c = NET AREA RATIO ptub psd_v20 > 0 |
| v20_net_3d = NET AREA RATIO nsd psd_v20 > 0 |
| v20_net_3e = NET AREA RATIO psd psd_v20 > 0 |
| v20_net_3f = NET AREA RATIO poly psd_v20 > 0 |
| v20_net_3g = NET AREA RATIO li psd_v20 > 0 |
| v20_net_3h = NET AREA RATIO met1 psd_v20 > 0 |
| v20_net_3i = NET AREA RATIO met2 psd_v20 > 0 |
| v20_net_3j = NET AREA RATIO met3 psd_v20 > 0 |
| v20_net_3k = NET AREA RATIO met4 psd_v20 > 0 |
| v20_net_3l = NET AREA RATIO met5 psd_v20 > 0 |
| v20_net_3 = OR v20_net_3a v20_net_3b v20_net_3c v20_net_3d v20_net_3e v20_net_3f v20_net_3g v20_net_3h v20_net_3i v20_net_3j v20_net_3k v20_net_3l |
| |
| v20_net_4a = NET AREA RATIO nwell poly_v20 > 0 |
| v20_net_4b = NET AREA RATIO pwell poly_v20 > 0 |
| v20_net_4c = NET AREA RATIO ptub poly_v20 > 0 |
| v20_net_4d = NET AREA RATIO nsd poly_v20 > 0 |
| v20_net_4e = NET AREA RATIO psd poly_v20 > 0 |
| v20_net_4f = NET AREA RATIO poly poly_v20 > 0 |
| v20_net_4g = NET AREA RATIO li poly_v20 > 0 |
| v20_net_4h = NET AREA RATIO met1 poly_v20 > 0 |
| v20_net_4i = NET AREA RATIO met2 poly_v20 > 0 |
| v20_net_4j = NET AREA RATIO met3 poly_v20 > 0 |
| v20_net_4k = NET AREA RATIO met4 poly_v20 > 0 |
| v20_net_4l = NET AREA RATIO met5 poly_v20 > 0 |
| v20_net_4 = OR v20_net_4a v20_net_4b v20_net_4c v20_net_4d v20_net_4e v20_net_4f v20_net_4g v20_net_4h v20_net_4i v20_net_4j v20_net_4k v20_net_4l |
| |
| v20_net_5a = NET AREA RATIO nwell ptub_v20 > 0 |
| v20_net_5b = NET AREA RATIO pwell ptub_v20 > 0 |
| v20_net_5c = NET AREA RATIO ptub ptub_v20 > 0 |
| v20_net_5d = NET AREA RATIO nsd ptub_v20 > 0 |
| v20_net_5e = NET AREA RATIO psd ptub_v20 > 0 |
| v20_net_5f = NET AREA RATIO poly ptub_v20 > 0 |
| v20_net_5g = NET AREA RATIO li ptub_v20 > 0 |
| v20_net_5h = NET AREA RATIO met1 ptub_v20 > 0 |
| v20_net_5i = NET AREA RATIO met2 ptub_v20 > 0 |
| v20_net_5j = NET AREA RATIO met3 ptub_v20 > 0 |
| v20_net_5k = NET AREA RATIO met4 ptub_v20 > 0 |
| v20_net_5l = NET AREA RATIO met5 ptub_v20 > 0 |
| v20_net_5 = OR v20_net_5a v20_net_5b v20_net_5c v20_net_5d v20_net_5e v20_net_5f v20_net_5g v20_net_5h v20_net_5i v20_net_5j v20_net_5k v20_net_5l |
| |
| v20_net = OR v20_net_1 v20_net_2 v20_net_3 v20_net_4 v20_net_5 |
| |
| } |
| |
| RULECHECK v20.CON.1 { |
| @ v20.CON.1: diff must not straddle v20 |
| OUTPUT "CUT difftap v20" |
| } |
| |
| RULECHECK v20.CON.2 { |
| @ v20.CON.2: poly must not straddle v20 |
| OUTPUT "polyi CUT v20" |
| } |
| |
| RULECHECK v20.ENC.1 { |
| @ v20.ENC.1: pwbm not in areaid:low_vt must be enclosed by v20 |
| OUTPUT "(NOT pwbm LOWVTID) NOT v20" |
| } |
| |
| RULECHECK v20.CON.3 { |
| @ v20.CON.3: dnwell must not straddle v20 |
| OUTPUT "CUT dnwell v20" |
| } |
| |
| #SETLAYER v20_56_xmpt = "NOT v20 (EXTENT CELL \"s8sram_tech_CD_top_s8pfn20r_a\")" |
| |
| RULECHECK v20.ENC.2 { |
| @ v20.ENC.2: v20 interacting with dnwell must fully enclose dnwell |
| OUTPUT "(dnwell INTERACT v20) NOT v20" |
| } |
| |
| RULECHECK v20.CON.4 { |
| @ v20.CON.4: areaid:low_vt must not straddle v20 |
| OUTPUT "CUT LOWVTID v20" |
| } |
| |
| # RY commented out v20.CON.5 as it is a duplicate of v20.CON.2 |
| #RULECHECK v20.CON.5 { |
| #@ v20.CON.5: v20 must not straddle poly |
| # OUTPUT "(polyi INTERACT v20) CUT v20" |
| # } |
| |
| RULECHECK v20.OVL.1 { |
| @ v20.OVL.1: v20 gate must overlap thkox |
| OUTPUT "((diff AND poly) INTERACT v20) NOT thkox" |
| } |
| |
| RULECHECK v20.CON.9 { |
| @ v20.CON.9: v20 over diff must overlap thkox |
| OUTPUT "(v20 AND diffi) NOT thkox" |
| } |
| |
| verbatim { |
| |
| // |
| // Stress Checks |
| // |
| } |
| |
| RULECHECK stress.CON.8 { |
| @ stress.CON.8: Layer areaid:notCritSide is an unsupported layer. Contact SkyWater Technologies for more information |
| OUTPUT "COPY notCritSideID" |
| } |
| |
| verbatim { |
| |
| #IFNDEF SKIP_STRESS_CHECKS |
| |
| |
| chip_area = (DONUT SEALID) OR (HOLES SEALID) |
| chipExtNotNcs = (EXTENT) NOT notCritSideID |
| q0chip_area = COPY 4000 |
| critsideNoSl = TVF CALtvfLay2OrEmpty chip_area chipExtNotNcs q0chip_area |
| critsideSl = AND chip_area critside |
| ccornerStree = AND chip_area ccorner |
| deadzone = AND chip_area deadzoneID |
| |
| } |
| |
| SETLAYER critsideStress = "critsideNoSl OR critsideSl" |
| SETLAYER critAreaStress = "((INTERACT (critsideStress OR ccornerStree) SEALID) AND chip_area) OR critSideNoSl" |
| SETLAYER exemptCells = "bondpadCuPillar OR (EXTENT CELL \"*_logo*\" \"*_partnum*\" \"partnum*\" \"*_trademark*\" \"*_copy*\" \"*datecode*\" \"lazX_*\" \"lazY_*\" \"*tech_CD*\" \"padPLadv*\" \"padPL*\" \"*_visid*\" \"pad_bond*\" ORIGINAL)" |
| SETLAYER exemptStressCells = "EXTENT CELL \"*_logo*\" \"*_partnum*\" \"partnum*\" \"*_trademark*\" \"*_copy*\" \"*datecode*\" \"lazX_*\" \"lazY_*\" \"*tech_CD*\" \"*_visid*\" ORIGINAL" |
| SETLAYER padPcells = "(EXTENT CELL \"padPLadv*\" \"padPL*\" \"pad_bond*\" ORIGINAL) OR bondpadCuPillar" |
| SETLAYER laser_target = "EXTENT CELL \"lazX_*\" \"lazY_*\" ORIGINAL" |
| |
| SETLAYER deadzoneChk = "(deadzone NOT exemptCells) AND critAreaStress" |
| SETLAYER BONDPAD2 = "pad OUTSIDE (OR SEALID moduleCutAREA fuse FRAMEID laser_target)" |
| SETLAYER critAreaNoExCells = "critAreaStress NOT exemptStressCells" |
| SETLAYER ccornerNoExCells = "ccornerStree NOT exemptStressCells" |
| SETLAYER critsideNoExCells = "critsideStress NOT exemptStressCells" |
| SETLAYER deviceLayers = "diff OR (tap OR polyres)" |
| SETLAYER exemptLayers = "deviceLayers OR exemptStressCells" |
| SETLAYER anchLayersStress = "INTERACT ((poly AND critAreaStress) AND ((li AND critAreaStress) AND ((met1 AND critAreaStress) AND ((met2 AND critAreaStress) AND ((met3 AND critAreaStress) AND (met4 AND critAreaStress)))))) (((poly AND critAreaStress) AND ((li AND critAreaStress) AND ((met1 AND critAreaStress) AND ((met2 AND critAreaStress) AND ((met3 AND critAreaStress) AND (met4 AND critAreaStress)))))) AND critAreaStress)" |
| SETLAYER alicon1Stress = "licon AND anchLayersStress" |
| SETLAYER amconStress = "mcon AND anchLayersStress" |
| SETLAYER aviaStress = "via1 AND anchLayersStress" |
| SETLAYER avia2Stress = "via2 AND anchLayersStress" |
| SETLAYER avia3Stress = "via3 AND anchLayersStress" |
| SETLAYER anchlicon1Stress = "alicon1 OUTSIDE (OR avia3 avia2 avia amcon)" |
| SETLAYER anchmconStress = "amcon OUTSIDE (OR avia3 avia2 avia alicon1)" |
| SETLAYER anchviaStress = "avia OUTSIDE (OR avia3 avia2 amcon alicon1)" |
| SETLAYER anchvia2Stress = "avia2 OUTSIDE (OR avia3 avia amcon alicon1)" |
| SETLAYER anchvia3Stress = "avia3 OUTSIDE (OR avia2 avia amcon alicon1)" |
| SETLAYER acontactsStress = "OR alicon1 amcon avia avia2 avia3" |
| SETLAYER anchcontactsStress = "OR anchlicon1 anchmcon anchvia anchvia2 anchvia3" |
| SETLAYER overlapConStress = "acontactsStress NOT anchcontactsStress" |
| SETLAYER anchorTmpStress = "((((anchLayersStress ENCLOSE licon) ENCLOSE mcon) ENCLOSE via1) ENCLOSE via2) ENCLOSE via3" |
| SETLAYER falseAnchStress = "poly CUT anchLayersStress" |
| SETLAYER anchorStress = "anchorTmpStress OUTSIDE (OR overlapCon falseAnchStress exemptLayers)" |
| |
| proc slot_rules { layer_list } { |
| |
| foreach layer $layer_list { |
| |
| if { $layer == "met5" } { |
| SETLAYER ${layer}OverCA = "(INTERACT ${layer} (AND ${layer} critAreaStress)) NOT (OR anchorStress padPcells (INSIDE CELL ${layer}ii exemptStressCells))" |
| } else { |
| SETLAYER ${layer}OverCA = "(INTERACT ${layer} (AND ${layer} critAreaStress)) NOT (OR anchorStress (INSIDE CELL ${layer}ii exemptStressCells))" |
| } |
| SETLAYER ${layer}Holes = "((HOLES ${layer}OverCA INNER EMPTY) INTERACT ((HOLES ${layer}OverCA INNER EMPTY) AND critAreaStress)) AREA < 5000" |
| SETLAYER filled_${layer} = "${layer}Holes OR ${layer}OverCA" |
| SETLAYER filled_wide${layer} = "WITH WIDTH filled_${layer} >= 25.0" |
| SETLAYER ${layer}slotAll = "((${layer}Holes WITH WIDTH < 20) NOT (${layer}Holes INTERACT (${layer}Holes AND ${layer}))) AND filled_wide${layer}" |
| SETLAYER ${layer}slotCutPad = "CUT ${layer}slotAll padPcells" |
| SETLAYER ${layer}slot = "(${layer}slotAll NOT padPcells) OR ${layer}slotCutPad" |
| |
| verbatim {#IFDEF SAVE_CONSTRUCTION_LAYERS} |
| |
| RULECHECK keep_${layer}slotCutPad { |
| @ keep: ${layer}slotCutPad |
| OUTPUT "COPY ${layer}slotCutPad" |
| } |
| |
| RULECHECK keep_${layer}slot { |
| @ keep: ${layer}slot |
| OUTPUT "COPY ${layer}slot" |
| } |
| |
| RULECHECK keep_${layer}OverCA { |
| @ keep: ${layer}OverCA |
| OUTPUT "COPY ${layer}OverCA" |
| } |
| |
| verbatim {#ENDIF} |
| |
| } |
| |
| } |
| |
| slot_rules [list "met1" "met2" "met3" "met4" "met5"] |
| |
| SETLAYER deadmetInit = "INTERACT met1 deadzoneChk" |
| SETLAYER q0met2 = "INTERACT met2 deadzoneChk" |
| SETLAYER q0deadmet = "COPY q0met2" |
| SETLAYER q0met3 = "INTERACT met3 deadzoneChk" |
| SETLAYER q1deadmet = "q0deadmet OR q0met3" |
| SETLAYER q0met4 = "INTERACT met4 deadzoneChk" |
| SETLAYER q2deadmet = "q1deadmet OR q0met4" |
| SETLAYER q0met5 = "INTERACT met5 deadzoneChk" |
| SETLAYER q3deadmet = "q2deadmet OR q0met5" |
| SETLAYER deadmet_new = "COPY q3deadmet" |
| SETLAYER deadmet_all = "deadmetInit OR deadmet_new" |
| SETLAYER deadmetCheck = "deadmet_all NOT exemptCells" |
| SETLAYER deadpoly = "(poly AND deadzoneChk) NOT (exemptCells OR anchorStress)" |
| SETLAYER deadmetWidthErr = "(WITH WIDTH (SNAP (deadmetCheck NOT anchorStress) 5) < 8.0) AND deadzoneChk" |
| SETLAYER SEALID_6um_stress = "SEALID AND ((EXTENT CELL \"advSeal_6um*\" ORIGINAL) OR (EXTENT CELL \"cuPillarAdvSeal_6um*\" ORIGINAL))" |
| SETLAYER diffNotSEALID_6um_stress = "diff NOT SEALID_6um_stress" |
| |
| RULECHECK diff.stress.1 { |
| @ diff.stress.1: diff outside areaid:seal must not overlap areaid:deadZon |
| OUTPUT "AND diffNotSEALID_6um_stress deadzoneChk" |
| } |
| |
| RULECHECK poly.stress.1 { |
| @ poly.stress.1: poly not allowed in areaid:deadZon unless poly is within Anchor region |
| OUTPUT "COPY deadpoly" |
| } |
| |
| RULECHECK met1.stress.WID.1 { |
| @ met1.stress.WID.1: Min width of met1 in Dead Zone < 8.00 |
| OUTPUT "COPY (deadmetWidthErr AND met1i)" |
| } |
| |
| RULECHECK met2.stress.WID.1 { |
| @ met2.stress.WID.1: Min width of met2 in Dead Zone < 8.00 |
| OUTPUT "COPY (deadmetWidthErr AND met2i)" |
| } |
| |
| RULECHECK met3.stress.WID.1 { |
| @ met3.stress.WID.1: Min width of met3 in Dead Zone < 8.00 |
| OUTPUT "COPY (deadmetWidthErr AND met3i)" |
| } |
| |
| RULECHECK met4.stress.WID.1 { |
| @ met4.stress.WID.1: Min width of met4 in Dead Zone < 8.00 |
| OUTPUT "COPY (deadmetWidthErr AND met4i)" |
| } |
| |
| RULECHECK met5.stress.WID.1 { |
| @ met5.stress.WID.1: Min width of met5 in Dead Zone < 8.00 |
| OUTPUT "COPY (deadmetWidthErr AND met5i)" |
| } |
| |
| |
| proc metals_stress_spacing_checks { layer_list } { |
| |
| foreach layer $layer_list { |
| |
| SETLAYER ${layer}GrabEdge = "${layer}OverCA WITH EDGE (LENGTH ${layer}OverCA >= 10.0)" |
| SETLAYER ${layer}SelectEdgeShapes = "((WITH WIDTH ${layer}GrabEdge >= 5.0) AND critAreaNoExCells) AND ${layer}OverCA" |
| SETLAYER ${layer}BusReal = "LENGTH ${layer}SelectEdgeShapes >= 10.0" |
| SETLAYER ${layer}Line = "((LENGTH (critAreaStress AND ${layer}OverCA) > 0) NOT COINCIDENT EDGE ${layer}BusReal) NOT COINCIDENT EDGE (LENGTH exemptStressCells > 0)" |
| |
| RULECHECK ${layer}.stress.SP.1 { |
| @ ${layer}.stress.SP.1: Min spacing of ${layer} bus (width >= 5.0 & length >= 10.0) & non-bus ${layer} < 0.54 |
| OUTPUT "EXTERNAL ${layer}BusReal ${layer}Line < 0.54 ABUT == 0 REGION parallel opposite EXCLUDE FALSE" |
| } |
| |
| RULECHECK ${layer}.stress.SP.2 { |
| @ ${layer}.stress.SP.2: Min spacing of ${layer} bus (width >= 5.0 & length >= 10.0) < 0.54 |
| OUTPUT "EXTERNAL ${layer}BusReal < 0.54 REGION parallel opposite" |
| } |
| } |
| } |
| |
| metals_stress_spacing_checks [list "met1" "met2" "met3" "met4" "met5"] |
| |
| SETLAYER via0 = "COPY mcon" |
| SETLAYER met0 = "COPY met1" |
| SETLAYER via1x = "COPY via1" |
| SETLAYER stress9Reg = "(INTERACT (OR critside ccorner) SEALID) AND (OR SEALID (HOLES SEALID))" |
| |
| proc standalone_and_non_standalone_metal_stress_spacing { lower_via upper_via lower_metal upper_metal metal_layer } { |
| |
| SETLAYER ${metal_layer}lowerLevelContact = "AND $lower_via $lower_metal" |
| SETLAYER ${metal_layer}upperLevelContact = "AND $upper_via $upper_metal" |
| SETLAYER ${metal_layer}OverCA_9 = "(stress9Reg AND ${metal_layer}OverCA) NOT exemptStressCells" |
| SETLAYER ${metal_layer}_LinesStandAlone = "${metal_layer}OverCA_9 AND (NOT INTERACT ${metal_layer} (OR ${metal_layer}lowerLevelContact ${metal_layer}upperLevelContact))" |
| SETLAYER ${metal_layer}_LinesSA_group = "(EXTERNAL ${metal_layer}_LinesStandAlone <= 10.0 REGION) OR ${metal_layer}_LinesStandAlone" |
| SETLAYER ${metal_layer}OverCAnotSA = "${metal_layer}OverCA_9 NOT ${metal_layer}_LinesStandAlone" |
| SETLAYER ${metal_layer}_err_stress_9 = "SIZE ${metal_layer}OverCAnotSA BY 10 INSIDE OF stress9Reg STEP 0.1" |
| SETLAYER ${metal_layer}_err_stress_9final = "(NOT INTERACT ${metal_layer}_LinesSA_group ${metal_layer}_err_stress_9) AND critAreaNoExCells" |
| |
| RULECHECK ${metal_layer}.stress.SP.3 { |
| @ ${metal_layer}.stress.SP.3: Max spacing between standalone and non-standalone ${metal_layer} in critical corner/side area = 10.0 um |
| OUTPUT "COPY ${metal_layer}_err_stress_9final" |
| } |
| |
| } |
| |
| standalone_and_non_standalone_metal_stress_spacing "via0" "via1x" "met0" "met2" "met1" |
| standalone_and_non_standalone_metal_stress_spacing "via1x" "via2" "met1" "met3" "met2" |
| standalone_and_non_standalone_metal_stress_spacing "via2" "via3" "met2" "met4" "met3" |
| standalone_and_non_standalone_metal_stress_spacing "via3" "via4" "met3" "met5" "met4" |
| standalone_and_non_standalone_metal_stress_spacing "via4" "via4" "met4" "met5" "met5" |
| |
| proc no_90_degree_bend_stress_check { layer_list } { |
| |
| foreach layer $layer_list { |
| |
| SETLAYER ${layer}Inner90DegCornerTmp = "${layer}OverCA OR (${layer} AND padPcells)" |
| SETLAYER ${layer}Inner90DegCorner = "EXTERNAL ${layer}Inner90DegCornerTmp < 0.005 ABUT > 89.9 < 90.1 SINGULAR REGION" |
| SETLAYER ${layer}Inner90DegCorNoSlot = "NOT INTERACT ${layer}Inner90DegCorner ${layer}slot" |
| SETLAYER ${layer}Bus = "WITH WIDTH ${layer}OverCA >= 5.0" |
| SETLAYER ${layer}BusInner90Deg_errCS = "SIZE ((TOUCH ${layer}Inner90DegCorNoSlot ${layer}Bus) AND critsideNoExCells) BY (10 * 0.005)" |
| SETLAYER ${layer}Inner90Deg_errCC = "SIZE (${layer}Inner90DegCorNoSlot AND ccornerNoExCells) BY (10 * 0.005)" |
| |
| RULECHECK ${layer}.stress.CON.1 { |
| @ ${layer}.stress.CON.1: 90-degree bend of inner side of 5um wide ${layer} in areaid:critSid are prohibited |
| OUTPUT "COPY ${layer}BusInner90Deg_errCS" |
| } |
| |
| RULECHECK ${layer}.stress.CON.2 { |
| @ ${layer}.stress.CON.2: 90-degree bends of inner side of ${layer} in areaid:critCorner are probited |
| OUTPUT "COPY ${layer}Inner90Deg_errCC" |
| } |
| } |
| } |
| |
| no_90_degree_bend_stress_check [list "met1" "met2" "met3" "met4" "met5"] |
| |
| proc inner_45_degree_edge_length_stress_check { layer_list } { |
| |
| foreach layer $layer_list { |
| |
| SETLAYER ${layer}Bus5_tmp = "${layer}OverCA NOT (INTERNAL ${layer}OverCA > 0 < 5.0 OPPOSITE OBTUSE ALSO REGION)" |
| SETLAYER ${layer}Bus5 = "${layer}Bus5_tmp NOT (WITH WIDTH ${layer}Bus5_tmp < 5.0)" |
| SETLAYER ${layer}Bus1_5_tmp = "INTERNAL ${layer}OverCA >= 1.0 < 5.0 OPPOSITE OBTUSE ALSO REGION" |
| SETLAYER ${layer}Bus1_5_tmp1 = "WITH WIDTH (${layer}Bus1_5_tmp AND ${layer}OverCA) >= 1.0 < 5.0" |
| SETLAYER ${layer}Bus1_5 = "COPY ${layer}Bus1_5_tmp1" |
| SETLAYER ${layer}Busless1 = "WITH WIDTH ${layer}OverCA < 1.0" |
| SETLAYER ${layer}_Turn225_225_Edge_tmp1 = "(CONVEX EDGE ${layer}OverCA ANGLE1 == 225 ANGLE2 == 225) OUTSIDE EDGE ${layer}Holes" |
| SETLAYER ${layer}_Turn225_225_EdgeSz_tmp1 = "EXPAND EDGE ${layer}_Turn225_225_Edge_tmp1 INSIDE BY 0.005 EXTEND BY (10.0 * 0.005)" |
| SETLAYER ${layer}_Turn225_225_EdgeSz_tmp2 = "${layer}_Turn225_225_EdgeSz_tmp1 INSIDE ${layer}OverCA" |
| SETLAYER ${layer}_Turn225_225_Edge = "${layer}_Turn225_225_Edge_tmp1 COINCIDENT EDGE ${layer}_Turn225_225_EdgeSz_tmp2" |
| SETLAYER ${layer}_Turn225_225_Edgeless5 = "EXPAND EDGE (LENGTH ${layer}_Turn225_225_Edge < 5.0) INSIDE BY 0.005 EXTEND BY (10.0 * 0.005)" |
| SETLAYER ${layer}_Turn225_225_Edgeless1 = "EXPAND EDGE (LENGTH ${layer}_Turn225_225_Edge < 1.0) INSIDE BY 0.005 EXTEND BY (10.0 * 0.005)" |
| SETLAYER ${layer}_Turn225_225_Edgeless05 = "EXPAND EDGE (LENGTH ${layer}_Turn225_225_Edge < 0.17) INSIDE BY 0.005 EXTEND BY (10.0 * 0.005)" |
| SETLAYER ${layer}_TurnLen_bus5Err = "((INTERACT ${layer}_Turn225_225_Edgeless5 (${layer}_Turn225_225_Edgeless5 AND ${layer}Bus5)) NOT (INTERACT ${layer}_Turn225_225_Edgeless5 (${layer}_Turn225_225_Edgeless5 AND (${layer}Bus1_5 OR ${layer}Busless1)))) AND critAreaNoExCells" |
| SETLAYER ${layer}_TurnLen_bus1_5Err = "((INTERACT ${layer}_Turn225_225_Edgeless1 (${layer}_Turn225_225_Edgeless1 AND ${layer}Bus1_5)) NOT (INTERACT ${layer}_Turn225_225_Edgeless1 (${layer}_Turn225_225_Edgeless1 AND ${layer}Busless1))) AND ccornerNoExCells" |
| SETLAYER ${layer}_TurnLen_busless1Err = "(INTERACT ${layer}_Turn225_225_Edgeless05 (${layer}_Turn225_225_Edgeless05 AND ${layer}Busless1)) AND ccornerNoExCells" |
| |
| RULECHECK ${layer}.stress.CON.3 { |
| @ ${layer}.stress.CON.3: Min inner 45-degree edge length for ${layer} >= 5.00um wide inside areaid:critCorner area < 5.0 |
| OUTPUT "COPY ${layer}_TurnLen_bus5Err" |
| } |
| |
| RULECHECK ${layer}.stress.CON.4 { |
| @ ${layer}.stress.CON.4: Min inner 45-degree edge length for ${layer} > 1.00um & < 5.00um wide inside areaid:critCorner area < 1.0 |
| OUTPUT "COPY ${layer}_TurnLen_bus1_5Err" |
| } |
| |
| RULECHECK ${layer}.stress.CON.5 { |
| @ ${layer}.stress.CON.5: Min inner 45-degree edge length for ${layer} < 1.00um wide inside areaid:critCorner < 0.17 |
| OUTPUT "COPY ${layer}_TurnLen_busless1Err" |
| } |
| } |
| } |
| |
| inner_45_degree_edge_length_stress_check [list "met1" "met2" "met3" "met4" "met5"] |
| |
| SETLAYER bondpadPcelltmp_1 = "(EXTENT CELL \"padPL*\" ORIGINAL) OR bondpadCuPillar" |
| SETLAYER bondpadPcelltmp_2 = "EXTENT CELL \"pad_bond*\" ORIGINAL" |
| SETLAYER bondpadPcelltmp = "OR bondpadPcelltmp_1 bondpadPcelltmp_2" |
| SETLAYER bondpadPcellAdv = "EXTENT CELL \"padPLadv*\" ORIGINAL" |
| SETLAYER bondpadPcell2 = "bondpadPcelltmp NOT bondpadPcellAdv" |
| SETLAYER bondpadNormal2 = "BONDPAD2 AND bondpadPcell2" |
| SETLAYER bondpadAdvan = "BONDPAD2 AND bondpadPcellAdv" |
| SETLAYER bondPadNormSz = "SIZE bondpadNormal2 BY 5" |
| SETLAYER bondPadAdvSz = "SIZE bondpadAdvan BY 2.7" |
| SETLAYER allbondPadSzTmp = "bondPadNormSz OR bondPadAdvSz" |
| SETLAYER degree45edge = "EXPAND EDGE (ANGLE allbondPadSzTmp == 45) OUTSIDE BY 0.005" |
| SETLAYER allbondPadSz = "allbondPadSzTmp OR degree45edge" |
| |
| proc no_90_degree_turn_for_metal_bus_stress_check { layer_list } { |
| |
| foreach layer $layer_list { |
| |
| SETLAYER allbondPadSz_${layer} = "allbondPadSz AND ${layer}" |
| SETLAYER bondPadCon_${layer} = "${layer} AND (WITH WIDTH (${layer} NOT allbondPadSz_${layer}) >= 5.0)" |
| SETLAYER ${layer}Bus_PadCor90 = "(EXTERNAL bondPadCon_${layer} allbondPadSz_${layer} < 0.005 ABUT > 89.9 < 90.1 SINGULAR REGION) OR (EXTERNAL allbondPadSz_${layer} < 0.005 ABUT > 89.9 < 90.1 SINGULAR REGION)" |
| SETLAYER ${layer}Bus_PadCor90Sz = "SIZE ((TOUCH ${layer}Bus_PadCor90 ${layer}) AND critAreaNoExCells) BY (10 * 0.025)" |
| |
| RULECHECK ${layer}.stress.CON.6 { |
| @ ${layer}.stress.CON.6: 90-degree turns for ${layer} bus connecting pad at the point of connection is prohibited |
| OUTPUT "COPY ${layer}Bus_PadCor90Sz" |
| } |
| } |
| } |
| |
| no_90_degree_turn_for_metal_bus_stress_check [list "met5" "met4"] |
| |
| SETLAYER convexedges_90 = "CONVEX EDGE met5 ANGLE1 == 90 ANGLE2 == 270" |
| SETLAYER convexedges_135 = "CONVEX EDGE met5 ANGLE1 == 135 ANGLE2 == 270" |
| SETLAYER convexedges_45 = "CONVEX EDGE met5 ANGLE1 > 0 ANGLE2 == 225" |
| SETLAYER met_edge_45_225 = "LENGTH convexedges_135 <= 6.4" |
| SETLAYER met_edge_135_225 = "LENGTH convexedges_45 <= 6.4" |
| SETLAYER met_edge_90_270 = "LENGTH convexedges_90 <= 6.4" |
| SETLAYER convexedges_45Sz = "EXPAND EDGE met_edge_45_225 INSIDE BY 0.005" |
| SETLAYER convexedges_135Sz = "EXPAND EDGE met_edge_135_225 INSIDE BY 0.005" |
| SETLAYER met_edge_90_270Sz = "EXPAND EDGE met_edge_90_270 INSIDE BY 0.005" |
| SETLAYER all_met_edgesSz = "EXPAND EDGE (LENGTH met5 >= 1.6 <= 3.2) INSIDE BY 0.005" |
| SETLAYER all_met_edgesNot90_270 = "all_met_edgesSz NOT (OR convexedges_45Sz convexedges_135Sz met_edge_90_270Sz)" |
| SETLAYER topmet45Sz = "EXPAND EDGE (ANGLE met5 == 45) INSIDE BY 0.005" |
| SETLAYER convexedges = "(OR convexedges_45Sz convexedges_135Sz met_edge_90_270Sz) NOT topmet45Sz" |
| SETLAYER met_edge_90_270Real = "NOT INTERACT convexedges all_met_edgesNot90_270" |
| SETLAYER met_edge_90_270Regtmp = "(EXTERNAL met_edge_90_270Real <= 3.19 PARALLEL OPPOSITE REGION) AND met5" |
| SETLAYER met_edge_90_270Reg = "NOT WITH WIDTH met_edge_90_270Regtmp == 0.005" |
| SETLAYER met_edge_90_270RegChk = "met_edge_90_270Real WITH EDGE (met_edge_90_270Real COINCIDENT OUTSIDE EDGE met_edge_90_270Reg)" |
| SETLAYER met_turn_90_270 = "INTERACT met5 (met5 AND met_edge_90_270Reg)" |
| SETLAYER met_LineEnd = "EXPAND EDGE (LENGTH (met5 NOT met_turn_90_270) <= 1.0) INSIDE BY 0.005" |
| SETLAYER met_edge_90_270Sz1 = "EXPAND EDGE met_edge_90_270RegChk OUTSIDE BY 1" |
| SETLAYER met_Line_Good = "NOT CUT met_LineEnd met_edge_90_270Sz1" |
| SETLAYER topMet45 = "ANGLE (met5 AND (critsideNoExCells OR ccornerNoExCells)) > 44.9 < 45.1" |
| SETLAYER topMet45szOut = "(EXPAND EDGE topMet45 OUTSIDE BY 0.005) NOT met5slot" |
| SETLAYER topMetInt45 = "INTERACT met5 topMet45szOut" |
| SETLAYER topMet90sz = "EXPAND EDGE (ANGLE topMetInt45 == 90) OUTSIDE BY 0.005" |
| SETLAYER topMet0sz = "EXPAND EDGE (ANGLE topMetInt45 == 0) OUTSIDE BY 0.005" |
| SETLAYER topMet45_both = "(INTERACT topMet45szOut topMet90sz) AND (INTERACT topMet45szOut topMet0sz)" |
| SETLAYER topMet0_45_2x = "INTERACT topMet0sz topMet45szOut == 2" |
| SETLAYER topMet90_45_2x = "INTERACT topMet90sz topMet45szOut == 2" |
| SETLAYER topMet45_3x = "(INTERACT topmet45szOut topMet0_45_2x) AND (INTERACT topmet45szout topMet90_45_2x)" |
| SETLAYER stress18_err90 = "EXPAND EDGE (LENGTH (topMetInt45 COINCIDENT EDGE (INTERACT topMet90sz topMet45_3x)) < 2.3) OUTSIDE BY 0.005" |
| SETLAYER stress18_err0 = "EXPAND EDGE (LENGTH (topMetInt45 COINCIDENT EDGE (INTERACT topMet0sz topMet45_3x)) < 2.3) OUTSIDE BY 0.005" |
| SETLAYER err1 = "INTERACT stress18_err90 (INTERACT topMet45_3x stress18_err0)" |
| SETLAYER err2 = "INTERACT stress18_err0 (INTERACT topMet45_3x stress18_err90)" |
| |
| RULECHECK stress.CON.7 { |
| @ stress.CON.7: Min length of non-touching angled edges for shape containing 3 consecutive 45-degree edges in areaid:cristSid or areaid:critCorner < 2.3 |
| OUTPUT "COPY err1" |
| OUTPUT "COPY err2" |
| } |
| |
| proc metal_slot_stress_check { layer_list } { |
| |
| foreach layer $layer_list { |
| |
| RULECHECK ${layer}.slot.WID.1 { |
| @ ${layer}.slot.WID.1: Min width of ${layer} slot < 2.3 |
| OUTPUT "(INTERNAL ${layer}slotAll < 2.3 PARALLEL OPPOSITE REGION) AND critAreaStress" |
| } |
| |
| RULECHECK ${layer}.slot.WID.2 { |
| @ ${layer}.slot.WID.2: Max width of ${layer} slot > 10.0 |
| OUTPUT "WITH WIDTH ${layer}slot > 10.0" |
| } |
| |
| RULECHECK ${layer}.slot.LEN.1 { |
| @ ${layer}.slot.LEN.1: Max length of ${layer} slot = 600.0 |
| OUTPUT "LENGTH (INTERACT ${layer}slotAll (${layer}slotAll AND critAreaStress)) > 600.0" |
| } |
| |
| } |
| |
| } |
| |
| metal_slot_stress_check [list "met1" "met2" "met3" "met4" "met5"] |
| |
| proc metal_stack_stress_check { via_layer metal_layer upper_metal_layer } { |
| |
| SETLAYER rivet${via_layer} = "${via_layer} NOT (SEALID OR (exemptStressCells OR padPcells))" |
| SETLAYER ${metal_layer}stack = "(${metal_layer}OverCA AND ${upper_metal_layer}) INTERACT rivet${via_layer}" |
| # a -stack- has to be connected by a via to upper level metal |
| SETLAYER ${metal_layer}stackBus = "WITH WIDTH ${metal_layer}stack >= 25.0" |
| # a -stack bus- must be stack with width >= 25um wide |
| SETLAYER ${metal_layer}stackBusCA = "${metal_layer}stackBus AND critAreaStress" |
| # a -stack bus CA- is a stack bus in critical stress area |
| SETLAYER ${metal_layer}UppBus = "(WITH WIDTH ${upper_metal_layer} >= 25.0) NOT exemptStressCells" |
| # a -metx UppBus- is met(x+1) over a met1 stacked bus |
| SETLAYER ${metal_layer}stack_uppBus = "${metal_layer}stackBus AND ${metal_layer}UppBus" |
| # a -metxstackUppBus- is the met(x) in a stacked uppBus |
| SETLAYER ${metal_layer}stack_encErr_tmp = "((ENCLOSURE ${metal_layer}stack ${upper_metal_layer} < 1.0 ABUT < 89.5 SINGULAR REGION) NOT SEALID) AND critAreaStress" |
| # a -met1stack_encErr_tmp- is a ENC met1 stack by met2 < 1.0 |
| SETLAYER ${metal_layer}stack_encErr = "${metal_layer}stack_encErr_tmp INTERACT (${metal_layer}stack_encErr_tmp AND ${metal_layer}stack_uppBus)" |
| SETLAYER ${metal_layer}stackStrUpp = "(${metal_layer}OverCA NOT ${metal_layer}stack) COINCIDENT OUTSIDE EDGE ${metal_layer}stack" |
| SETLAYER ${metal_layer}stackStrUppSz05 = "(EXPAND EDGE ${metal_layer}stackStrUpp INSIDE BY 0.5) NOT CUT ${metal_layer}OverCA" |
| SETLAYER ${metal_layer}stackStrUppExempt = "${metal_layer}stackStrUppSz05 COINCIDENT OUTSIDE EDGE ${metal_layer}stack" |
| SETLAYER ${metal_layer}stack_encErrFinal = "${metal_layer}stack_encErr NOT (EXPAND EDGE ${metal_layer}stackStrUppExempt OUTSIDE BY 0.005)" |
| if { $metal_layer == "met1" } { verbatim {CONNECT met1stackBusCA via1} } |
| if { $metal_layer == "met2" } { verbatim {CONNECT met2stackBusCA via2} } |
| if { $metal_layer == "met3" } { verbatim {CONNECT met3stackBusCA via3} } |
| if { $metal_layer == "met4" } { verbatim {CONNECT met4stackBusCA via4} } |
| SETLAYER ${metal_layer}stackNoSlots = "((${metal_layer}OverCA OR ${metal_layer}slot) AND (${upper_metal_layer} OR ${upper_metal_layer}slot)) INTERACT rivet${via_layer}" |
| # metxstackNoSlots is metx stack with and without slots |
| SETLAYER ${metal_layer}stackBusNoSlots = "WITH WIDTH ${metal_layer}stackNoSlots >= 25.0" |
| # setxstackBusNoSlots is metxstackNoSlots with width >= 25.0 |
| SETLAYER ${metal_layer}stackBusCA_NoSlots = "${metal_layer}stackBusNoSlots AND critAreaStress" |
| SETLAYER ${metal_layer}Low_slot_stack = "${metal_layer}slot AND ${metal_layer}stackBusCA_NoSlots" |
| SETLAYER ${upper_metal_layer}Upp_slot_stack = "${upper_metal_layer}slot AND ${metal_layer}stackBusCA_NoSlots" |
| SETLAYER err_coin_slots_${metal_layer} = "((${metal_layer}Low_slot_stack NOT ENCLOSE ${upper_metal_layer}Upp_slot_stack) INTERACT ((${metal_layer}Low_slot_stack NOT ENCLOSE ${upper_metal_layer}Upp_slot_stack) AND critAreaStress)) NOT (EXTENT CELL \"pad_bond*\" ORIGINAL)" |
| |
| RULECHECK ${metal_layer}.stress.CON.9 { |
| #@ ${metal_layer}.stress.CON.9: ${metal_layer}Low_slot_stack should enclose ${upper_metal_layer}Upp_slot_stack in metal stack |
| @ ${metal_layer}.slot.CON.9: ${metal_layer} in lower slotted stack should enclose ${upper_metal_layer} in the upper slotted stack. |
| OUTPUT "COPY err_coin_slots_${metal_layer}" |
| } |
| |
| RULECHECK ${metal_layer}.stress.ENC.1 { |
| @ ${metal_layer}.stress.ENC.1: Min enclosure of ${upper_metal_layer} in a slotted stack by ${metal_layer} in slotted stack < 1.0 |
| OUTPUT "ENCLOSURE (${upper_metal_layer}Upp_slot_stack AND ${metal_layer}Low_slot_stack) ${metal_layer}Low_slot_stack < 1.0 MEASURE ALL ABUT < 90 SINGULAR" |
| } |
| |
| RULECHECK ${metal_layer}.stress.ENC.2 { |
| #@ ${metal_layer}.stress.ENC.2: Min enclosure of a ${metal_layer} stack bus by ${metal_layer} upper bus in 5 um wide metal stack < 1.0 |
| @ ${metal_layer}.stress.ENC.2: Min enclosure of a ${metal_layer} stack bus by ${upper_metal_layer} bus < 1.0 |
| OUTPUT "COPY ${metal_layer}stack_encErrFinal" |
| } |
| |
| RULECHECK ${metal_layer}.stress.DEN.1 { |
| @ ${metal_layer}.stress.DEN.1: Min ${via_layer} density on wide ${metal_layer} and ${upper_metal_layer} bus stack is 3.00 percent |
| OUTPUT "NET AREA RATIO ${metal_layer}stackBusCA ${via_layer} < 0.03 \[AREA(${via_layer})/AREA(${metal_layer}stackBusCA)\] RDB ${metal_layer}.stress.DEN.1.db ${metal_layer}stackBusCA ${via_layer}" |
| } |
| |
| } |
| |
| metal_stack_stress_check "via1" "met1" "met2" |
| metal_stack_stress_check "via2" "met2" "met3" |
| metal_stack_stress_check "via3" "met3" "met4" |
| metal_stack_stress_check "via4" "met4" "met5" |
| |
| proc slot_density_check { layer_list } { |
| |
| |
| foreach layer $layer_list { |
| |
| if { $layer == "met1" } { |
| SETLAYER ${layer}Shielda = "COPY 4004" |
| SETLAYER ${layer}_over_crit_area = "WITH WIDTH ((INTERACT (filled_${layer} NOT ${layer}Shielda) ((filled_${layer} NOT ${layer}Shielda) AND ${layer}slotAll)) AND critAreaStress) > 25.0" |
| verbatim {CONNECT met1_over_crit_area met1slotAll} |
| } else { |
| SETLAYER ${layer}_over_crit_area = "WITH WIDTH ((INTERACT filled_${layer} (filled_${layer} AND ${layer}slotAll)) AND critAreaStress) > 25.0" |
| } |
| if { $layer == "met2" } { verbatim {CONNECT met2_over_crit_area met2slotAll} } |
| if { $layer == "met3" } { verbatim {CONNECT met3_over_crit_area met3slotAll} } |
| if { $layer == "met4" } { verbatim {CONNECT met4_over_crit_area met4slotAll} } |
| if { $layer == "met5" } { verbatim {CONNECT met5_over_crit_area met5slotAll} } |
| |
| RULECHECK ${layer}.slot.DEN.1 { |
| @ ${layer}.slot.DEN.1: Min slot density on wide ${layer} bus < 7.50% |
| OUTPUT "NET AREA RATIO ${layer}_over_crit_area ${layer}slotAll < 0.075 \[AREA(${layer}slotAll)/AREA(${layer}_over_crit_area)\] RDB ${layer}.slot.DEN.1.db ${layer}_over_crit_area ${layer}slotAll" |
| } |
| |
| } |
| |
| } |
| |
| slot_density_check [list "met1" "met2" "met3" "met4" "met5"] |
| |
| proc wide_metal_slot_check { layer_list } { |
| |
| foreach layer $layer_list { |
| |
| if { $layer == "met1" } { |
| SETLAYER ${layer}OverCAnoSlot = "INTERACT (WITH WIDTH (${layer}OverCA NOT ${layer}Shielda) > 25.0) ((WITH WIDTH (${layer}OverCA NOT ${layer}Shielda) > 25.0) AND critAreaStress)" |
| } elseif { $layer == "met5" } { |
| SETLAYER slotMetXmt = "${layer} AND padPcells" |
| SETLAYER ${layer}OverCAnoSlot = "INTERACT (WITH WIDTH (${layer}OverCA NOT slotMetXmt) > 25.0) ((WITH WIDTH (${layer}OverCA NOT slotMetXmt) > 25.0) AND critAreaStress)" |
| } else { |
| SETLAYER ${layer}OverCAnoSlot = "INTERACT (WITH WIDTH ${layer}OverCA > 25.0) ((WITH WIDTH ${layer}OverCA > 25.0) AND critAreaStress)" |
| } |
| |
| RULECHECK ${layer}.slot.CON.1 { |
| @ ${layer}.slot.CON.1: ${layer} wider than 25um inside areaid:critCorner or areaid:critSid must contain slot |
| OUTPUT "COPY ${layer}OverCAnoSlot" |
| } |
| RULECHECK ${layer}.slot.SP.1 { |
| @ ${layer}.slot.SP.1: Min spacing of ${layer} slot < 2.3 |
| OUTPUT "EXTERNAL ${layer}slot < 2.3 ABUT < 90 SINGULAR REGION SPACE EXCLUDE FALSE" |
| } |
| } |
| |
| } |
| |
| wide_metal_slot_check [list "met1" "met2" "met3" "met4" "met5"] |
| |
| proc metal_slot_alignment_check { layer_list } { |
| |
| foreach layer $layer_list { |
| |
| SETLAYER ${layer}_slotShortLen = "LENGTH ${layer}slot >= 2.3 <= 10.0" |
| SETLAYER ${layer}_slotShortLenSz = "EXPAND EDGE ${layer}_slotShortLen OUTSIDE BY 0.005" |
| SETLAYER ${layer}_slotShortLen1 = "EXPAND EDGE (LENGTH ${layer}_slotShortLenSz == 0.005) INSIDE BY 0.005" |
| SETLAYER ${layer}_slotShortLenSpc25 = "EXTERNAL ${layer}_slotShortLen1 <= 25.0 PARALLEL OPPOSITE REGION" |
| SETLAYER ${layer}_slotShortLen15err1 = "INTERACT (${layer}_slotShortLenSpc25 NOT (INTERACT ${layer}_slotShortLenSpc25 (${layer}_slotShortLenSpc25 AND ${layer}slot))) (EXPAND EDGE ((${layer}_slotShortLenSpc25 NOT (INTERACT ${layer}_slotShortLenSpc25 (${layer}_slotShortLenSpc25 AND ${layer}slot))) COINCIDENT OUTSIDE EDGE ${layer}slot) BY 0.005 EXTEND BY 0.005) >= 2" |
| SETLAYER ${layer}_slotShortLen15err = "INTERACT (INTERACT ${layer}_slotShortLen15err1 (${layer}_slotShortLen15err1 AND ${layer}_slotShortLenSz) >= 2) ((INTERACT ${layer}_slotShortLen15err1 (${layer}_slotShortLen15err1 AND ${layer}_slotShortLenSz) >= 2) AND critAreaStress)" |
| |
| RULECHECK ${layer}.slot.CON.2 { |
| @ ${layer}.slot.CON.2: Start and end points of ${layer} slots spaced <= 25.00um apart in adjacent rows must be offset |
| OUTPUT "COPY ${layer}_slotShortLen15err" |
| } |
| |
| } |
| |
| } |
| |
| metal_slot_alignment_check [list "met1" "met2" "met3" "met4" "met5"] |
| |
| SETLAYER allay_first = "chip_area NOT critAreaStress" |
| SETLAYER q0lay = "(dnwell AND critAreaStress) OR allay_first" |
| SETLAYER q1lay = "(nwell AND critAreaStress) OR q0lay" |
| SETLAYER q2lay = "(diff AND critAreaStress) OR q1lay" |
| SETLAYER q3lay = "(tap AND critAreaStress) OR q2lay" |
| SETLAYER q4lay = "(lvtn AND critAreaStress) OR q3lay" |
| SETLAYER q5lay = "(hvtp AND critAreaStress) OR q4lay" |
| SETLAYER q6lay = "(v5 AND critAreaStress) OR q5lay" |
| SETLAYER q7lay = "(poly AND critAreaStress) OR q6lay" |
| SETLAYER q8lay = "(npc AND critAreaStress) OR q7lay" |
| SETLAYER q9lay = "(nsdm AND critAreaStress) OR q8lay" |
| SETLAYER q10lay = "(psdm AND critAreaStress) OR q9lay" |
| SETLAYER q11lay = "(tunm AND critAreaStress) OR q10lay" |
| SETLAYER q12lay = "(licon AND critAreaStress) OR q11lay" |
| SETLAYER q13lay = "(li AND critAreaStress) OR q12lay" |
| SETLAYER q14lay = "(mcon AND critAreaStress) OR q13lay" |
| SETLAYER q15lay = "(met1 AND critAreaStress) OR q14lay" |
| SETLAYER q16lay = "(via1 AND critAreaStress) OR q15lay" |
| SETLAYER q17lay = "(met2 AND critAreaStress) OR q16lay" |
| SETLAYER q18lay = "(via2 AND critAreaStress) OR q17lay" |
| SETLAYER q19lay = "(met3 AND critAreaStress) OR q18lay" |
| SETLAYER q20lay = "(via3 AND critAreaStress) OR q19lay" |
| SETLAYER q21lay = "(met4 AND critAreaStress) OR q20lay" |
| SETLAYER q22lay = "(via4 AND critAreaStress) OR q21lay" |
| SETLAYER q23lay = "(met5 AND critAreaStress) OR q22lay" |
| SETLAYER q24lay = "(v12 AND critAreaStress) OR q23lay" |
| SETLAYER q25lay = "(pad AND critAreaStress) OR q24lay" |
| SETLAYER q26lay = "(pnp AND critAreaStress) OR q25lay" |
| SETLAYER allay = "COPY q26lay" |
| SETLAYER openArea = "DENSITY allay <= 0 WINDOW 50 STEP 25 RDB anchor.1_density.db" |
| SETLAYER openAreaAnc = "WITH WIDTH (openArea AND (INTERACT critAreaStress (critAreaStress AND SEALID))) >= 50.0" |
| |
| RULECHECK anchor.CON.1 { |
| @ anchor.CON.1: Open area anchors needed in any open window of 50umx50um in areaid:critCorner or areaid:critSid area |
| OUTPUT "COPY openAreaAnc" |
| } |
| |
| proc metal_to_anchor_width_check { layer_list } { |
| |
| foreach layer $layer_list { |
| |
| RULECHECK ${layer}.anchor.WID.1 { |
| @ ${layer}.anchor.WID.1: Min width of ${layer} overlapping anchor < 3.0 |
| OUTPUT "INTERNAL (${layer} AND anchorStress) < 3.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| } |
| |
| } |
| |
| metal_to_anchor_width_check [list "poly" "li" "met1" "met2" "met3" "met4" "met5"] |
| |
| RULECHECK anchor.SP.1 { |
| @ anchor.SP.1: Min spacing/notch of anchor < 5.0 |
| OUTPUT "EXTERNAL anchorStress < 5.0 ABUT < 90 SINGULAR REGION" |
| } |
| |
| SETLAYER licon_anc = "licon AND anchorStress" |
| SETLAYER via1_anc = "via1 AND anchorStress" |
| SETLAYER via2_anc = "via2 AND anchorStress" |
| SETLAYER via3_anc = "via3 AND anchorStress" |
| SETLAYER via4_anc = "via4 AND anchorStress" |
| SETLAYER mcon_anc = "mcon AND anchorStress" |
| |
| proc via_overlap_in_anchor_check { first_via second_via } { |
| |
| RULECHECK ${first_via}.${second_via}.anchor.CON.2 { |
| @ ${first_via}.${second_via}.anchor.CON.2: ${first_via} in anchor must not overlap ${second_via} in anchor |
| OUTPUT "AND ${first_via}_anc ${second_via}_anc" |
| } |
| |
| } |
| |
| via_overlap_in_anchor_check "licon" "mcon" |
| via_overlap_in_anchor_check "licon" "via1" |
| via_overlap_in_anchor_check "licon" "via2" |
| via_overlap_in_anchor_check "licon" "via3" |
| via_overlap_in_anchor_check "licon" "via4" |
| via_overlap_in_anchor_check "via1" "via2" |
| via_overlap_in_anchor_check "via1" "via3" |
| via_overlap_in_anchor_check "via1" "via4" |
| via_overlap_in_anchor_check "via1" "mcon" |
| via_overlap_in_anchor_check "via2" "via3" |
| via_overlap_in_anchor_check "via2" "via4" |
| via_overlap_in_anchor_check "via2" "mcon" |
| via_overlap_in_anchor_check "via3" "via4" |
| via_overlap_in_anchor_check "via3" "mcon" |
| via_overlap_in_anchor_check "via4" "mcon" |
| |
| proc via_in_anchor_spacing_check { via_layer spacing_value } { |
| |
| RULECHECK ${via_layer}.anchor.SP.1 { |
| @ ${via_layer}.anchor.SP.1: Min spacing of ${via_layer} overlapping anchor < ${spacing_value} |
| OUTPUT "EXTERNAL ${via_layer}_anc < ${spacing_value} ABUT < 90 SINGULAR REGION" |
| } |
| |
| } |
| |
| via_in_anchor_spacing_check "licon" "2.93" |
| via_in_anchor_spacing_check "mcon" "2.93" |
| via_in_anchor_spacing_check "via1" "2.95" |
| via_in_anchor_spacing_check "via2" "2.9" |
| via_in_anchor_spacing_check "via3" "2.9" |
| via_in_anchor_spacing_check "via4" "2.3" |
| |
| proc metal_connect_stress_checks { layer via_layer lower_via upper_via } { |
| |
| SETLAYER ${layer}CrossAnc = "CUT ${layer} anchorStress" |
| SETLAYER ${via_layer}LowOutsideAnc = "$lower_via OUTSIDE anchorStress" |
| SETLAYER ${via_layer}UppOutsideAnc = "$upper_via OUTSIDE anchorStress" |
| SETLAYER ${layer}CrossAncCon = "(INTERACT ${layer}CrossAnc (${layer}CrossAnc AND ${via_layer}LowOutsideAnc)) OR (INTERACT ${layer}CrossAnc (${layer}CrossAnc AND ${via_layer}UppOutsideAnc))" |
| |
| RULECHECK ${layer}.anchor.connect.CON.1 { |
| @ ${layer}.anchor.connect.CON.1: ${layer} inside ANCHOR region cannot connect to any other metal bus |
| OUTPUT "COPY ${layer}CrossAncCon" |
| } |
| |
| } |
| |
| metal_connect_stress_checks "met1" "via1" "via0" "via1" |
| metal_connect_stress_checks "met2" "via2" "via1" "via2" |
| metal_connect_stress_checks "met3" "via3" "via2" "via3" |
| metal_connect_stress_checks "met4" "via4" "via3" "via4" |
| |
| SETLAYER met5CrossAnc = "CUT met5 anchorStress" |
| SETLAYER BONDPADLowOutsideAnc = "via4 OUTSIDE anchorStress" |
| SETLAYER met5CrossAncCon = "INTERACT met5CrossAnc (met5CrossAnc AND BONDPADLowOutsideAnc)" |
| |
| RULECHECK met5.anchor.connect.CON.1 { |
| @ met5.anchor.connect.CON.1: met5 of ANCHOR cannot connect to any other metal bus |
| OUTPUT "COPY met5CrossAncCon" |
| } |
| |
| proc via_in_anchor_len_chk { via_layer met_layer } { |
| RULECHECK ${met_layer}.${via_layer}.anchor.WARN.1 { |
| @ ${met_layer}.${via_layer}.anchor.WARN.1: This ${met_layer} anchor region must contain additional ${via_layer} |
| SETLAYER center_anchor = "(INT (${met_layer} INTERACT ${via_layer}_anc) < 3.5 ABUT<90 OPPOSITE PARALLEL REGION CENTERLINE 0.10) NOT (${via_layer} INTERACT (${met_layer} INTERACT ${via_layer}_anc))" |
| SETLAYER center_anchor_edge_len_a = "NOT COINCIDENT EDGE center_anchor ${met_layer}" |
| SETLAYER center_anchor_edge_len = "NOT COINCIDENT EDGE center_anchor_edge_len_a ${via_layer}" |
| SETLAYER error_anchor = "LENGTH center_anchor_edge_len > 10" |
| SETLAYER exp_err_anc1 = "(EXPAND EDGE error_anchor OUTSIDE BY 3) AND ${met_layer}" |
| SETLAYER exp_err_anc2 = "(EXPAND EDGE error_anchor INSIDE BY 3) AND ${met_layer}" |
| OUTPUT "OR exp_err_anc1 exp_err_anc2" |
| } |
| } |
| |
| via_in_anchor_len_chk "licon" "poly" |
| via_in_anchor_len_chk "licon" "li" |
| via_in_anchor_len_chk "mcon" "li" |
| via_in_anchor_len_chk "mcon" "met1" |
| via_in_anchor_len_chk "via1" "met1" |
| via_in_anchor_len_chk "via1" "met2" |
| via_in_anchor_len_chk "via2" "met2" |
| via_in_anchor_len_chk "via2" "met3" |
| via_in_anchor_len_chk "via3" "met3" |
| via_in_anchor_len_chk "via3" "met4" |
| |
| verbatim { |
| #ENDIF |
| } |
| |
| verbatim { |
| |
| // |
| // DEEP NWELL (DNWELL) checks |
| // |
| |
| ////DISCONNECT |
| //////npccon = npc AND licon |
| ////CONNECT dnwell nwell |
| ////CONNECT nwell tap BY NTAP |
| ////CONNECT tap li BY licon |
| ////CONNECT poly li BY npccon |
| ////CONNECT li met1 BY mcon |
| ////CONNECT met1 met2 BY via1 |
| ////CONNECT met3 met2 BY via2 |
| ////CONNECT met3 met4 BY via3_c |
| ////CONNECT met4 met5 BY via4_c |
| ////CONNECT met5 pad |
| ////CONNECT rdl pad |
| |
| } |
| |
| set dnwell_width 3.0 |
| set dnwell_spacing_notch 6.3 |
| set dnwell_spacing_to_v20_samenet 2.5 |
| set dnwell_spacing_to_v20_diffnet 12.0 |
| set dnwell_in_v20_spacing_to_dnwell_outside_v20 12.0 |
| set dnwell_in_v20_spacing_to_nwell_outside_v20 9.5 |
| |
| #SETLAYER nwellring = "DONUT nwell" |
| SETLAYER dnwell_in_v20 = "dnwell AND v20" |
| |
| RULECHECK dnwell.WID.1 { |
| @ dnwell.WID.1: Min width of deep nwell < ${dnwell_width} |
| OUTPUT "INTERNAL dnwell < ${dnwell_width} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK dnwell.SP.1 { |
| @ dnwell.SP.1: Min spacing/notch of deep nwell (exempt inside v20) < ${dnwell_spacing_notch} |
| OUTPUT "EXTERNAL (OUTSIDE dnwell v20) < ${dnwell_spacing_notch} ABUT < 90 SINGULAR REGION" |
| } |
| |
| RULECHECK dnwell.CON.1 { |
| @ dnwell.CON.1: deep nwell cannot overlap pnp drawing layer |
| OUTPUT "dnwell AND pnp" |
| } |
| |
| RULECHECK dnwell.CON.2 { |
| @ dnwell.CON.2: pdiff cannot straddle deep nwell |
| OUTPUT "(diffi AND psdm) CUT dnwell" |
| } |
| |
| RULECHECK dnwell.CON.3 { |
| @ dnwell.CON.3: deep nwell cannot straddle areaid:substratecut layer |
| OUTPUT "(dnwell CUT localSub) AND localSub" |
| } |
| |
| RULECHECK dnwell.CON.4 { |
| @ dnwell.CON.4: dnwell must interact with nwell |
| OUTPUT "dnwell NOT INTERACT nwell" |
| } |
| |
| RULECHECK dnwell.SP.2 { |
| @ dnwell.SP.2: Min spacing of dnwell in v20 on same net < ${dnwell_spacing_to_v20_samenet} |
| OUTPUT "EXTERNAL dnwell_in_v20 < ${dnwell_spacing_to_v20_samenet} ABUT < 90 SINGULAR REGION CONNECTED" |
| } |
| |
| RULECHECK dnwell.SP.3 { |
| @ dnwell.SP.3: Min spacing of dwnell in v20 not on same net < ${dnwell_spacing_to_v20_diffnet} |
| OUTPUT "EXTERNAL dnwell_in_v20 < ${dnwell_spacing_to_v20_diffnet} ABUT < 90 SINGULAR REGION NOT CONNECTED" |
| } |
| |
| RULECHECK dnwell.SP.4 { |
| @ dnwell.SP.4: Min spacing of dnwell in v20 to dnwell outside v20 < ${dnwell_in_v20_spacing_to_dnwell_outside_v20} |
| OUTPUT "EXTERNAL dnwell_in_v20 (NOT dnwell v20) < ${dnwell_in_v20_spacing_to_dnwell_outside_v20} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK dnwell.SP.5 { |
| @ dnwell.SP.5: Min spacing of dnwell in v20 to nwell outside v20 < ${dnwell_in_v20_spacing_to_nwell_outside_v20} |
| OUTPUT "EXTERNAL dnwell_in_v20 (NOT nwell v20) < ${dnwell_in_v20_spacing_to_nwell_outside_v20} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| |
| verbatim { |
| |
| // |
| // Nwell checks |
| // |
| |
| } |
| |
| set nwell_min_width 0.84 |
| set nwell_lv_min_spacing 1.27 |
| set nwell_mv_min_spacing 2.0 |
| set nwell_hv_min_spacing 2.5 |
| set dnwell_over_nwell_enc 1.03 |
| set dnwell_enc_of_nwell 0.4 |
| set nwell_dnwell_no_minspace_val 4.5 |
| |
| SETLAYER tech_CD_top_cells = "EXTENT CELL \"*_tech_CD_top*\"" |
| SETLAYER dnwellNotTechCD = "dnwell NOT tech_CD_top_cells" |
| SETLAYER nwellNotTechCD = "nwell NOT tech_CD_top_cells" |
| SETLAYER nwell_exempted_regions = "OR v20 tech_CD_top_cells" |
| |
| SETLAYER nw_20v_1 = "nwell INTERACT v20" |
| SETLAYER nw_20v = "STAMP nw_20v_1 BY nwell" |
| SETLAYER nw_not_20v = "nwell NOT nw_20v" |
| SETLAYER nw_12v_1 = "nw_not_20v INTERACT v12" |
| SETLAYER nw_12v = "STAMP nw_12v_1 BY nwell" |
| SETLAYER nw_not_20v_or_12v = "nwell NOT (OR nw_20v nw_12v)" |
| SETLAYER nw_5v_1 = "nw_not_20v_or_12v INTERACT v5" |
| SETLAYER nw_5v = "STAMP nw_5v_1 BY nwell" |
| SETLAYER nw_1p8v_1 = "nwell NOT INTERACT (OR v5 v12 v20)" |
| SETLAYER nw_1p8v = "STAMP nw_1p8v_1 BY nwell" |
| SETLAYER nwell_outside_v20 = "nwell NOT INTERACT v20" |
| |
| RULECHECK nwell.WID.1 { |
| @ nwell.WID.1: Min width of nwell < ${nwell_min_width} |
| OUTPUT "INT nwell < ${nwell_min_width} ABUT < 90 SINGULAR REGION EXCLUDE FALSE" |
| } |
| |
| RULECHECK nwell.SP.1 { |
| @ nwell.SP.1: Min spacing/notch of 1.8v nwell < ${nwell_lv_min_spacing} |
| OUTPUT "EXTERNAL nw_1p8v < ${nwell_lv_min_spacing} ABUT < 90 SINGULAR REGION" |
| } |
| |
| RULECHECK nwell.SP.2 { |
| @ nwell.SP.2: Min spacing of 1.8v nwell to 5v nwell < ${nwell_lv_min_spacing} |
| OUTPUT "EXTERNAL nw_1p8v nw_5v < ${nwell_lv_min_spacing} ABUT < 90 SINGULAR REGION" |
| } |
| |
| RULECHECK nwell.SP.3 { |
| @ nwell.SP.3: Min spacing of 1.8v nwell to 12v nwell < ${nwell_mv_min_spacing} |
| OUTPUT "EXTERNAL nw_1p8v nw_12v < ${nwell_mv_min_spacing} ABUT < 90 SINGULAR REGION" |
| } |
| |
| RULECHECK nwell.SP.4 { |
| @ nwell.SP.4: Min spacing of 1.8v nwell to 20v nwell < ${nwell_hv_min_spacing} |
| OUTPUT "EXTERNAL nw_1p8v nw_20v < ${nwell_hv_min_spacing} ABUT < 90 SINGULAR REGION" |
| } |
| |
| RULECHECK nwell.SP.5 { |
| @ nwell.SP.5: Min spacing/notch of 5v nwell to 5v nwell < ${nwell_lv_min_spacing} |
| OUTPUT "EXTERNAL nw_5v < ${nwell_lv_min_spacing} ABUT < 90 SINGULAR REGION" |
| } |
| |
| RULECHECK nwell.SP.6 { |
| @ nwell.SP.6: Min spacing of 5v nwell to 12v nwell < ${nwell_mv_min_spacing} |
| OUTPUT "EXTERNAL nw_5v nw_12v < ${nwell_mv_min_spacing} ABUT < 90 SINGULAR REGION" |
| } |
| |
| RULECHECK nwell.SP.7 { |
| @ nwell.SP.7: Min spacing of 5v nwell to 20v nwell < ${nwell_hv_min_spacing} |
| OUTPUT "EXTERNAL nw_5v nw_20v < ${nwell_hv_min_spacing} ABUT < 90 SINGULAR REGION" |
| } |
| |
| RULECHECK nwell.SP.8 { |
| @ nwell.SP.8: Min spacing/notch of 12v nwell to 12v nwell < ${nwell_mv_min_spacing} |
| OUTPUT "EXTERNAL nw_12v < ${nwell_mv_min_spacing} ABUT < 90 SINGULAR REGION" |
| } |
| |
| RULECHECK nwell.SP.9 { |
| @ nwell.SP.9: Min spacing of 12v nwell to 20v nwell < ${nwell_hv_min_spacing} |
| OUTPUT "EXTERNAL nw_12v nw_20v < ${nwell_hv_min_spacing} ABUT < 90 SINGULAR REGION" |
| } |
| |
| RULECHECK nwell.SP.10 { |
| @ nwell.SP.10: Min spacing/notch of 20v nwell < ${nwell_hv_min_spacing} |
| OUTPUT "EXTERNAL nw_20v < ${nwell_hv_min_spacing} ABUT < 90 SINGULAR REGION" |
| } |
| |
| RULECHECK nwell.OVL.1 { |
| @ nwell.OVL.1: nwell must connect by ntap at least once |
| #OUTPUT "OUTSIDE (NOT nwell v20) (AND ntap licon)" |
| OUTPUT "nwell NOT ENCLOSE ntap" |
| } |
| |
| RULECHECK nwell.ENC.1 { |
| @ nwell.ENC.1: Min enclosure of deep nwell by nwell < ${dnwell_enc_of_nwell} (Rule exempted inside v20 and in cell names with \"*_tech_CD_top*\") |
| OUTPUT "ENC (NOT dnwell nwell_exempted_regions) (NOT nwell nwell_exempted_regions) < ${dnwell_enc_of_nwell} MEASURE ALL ABUT < 90 SINGULAR REGION" |
| } |
| |
| #" |
| |
| RULECHECK nwell.ENC.2 { |
| @ nwell.ENC.2: Min enclosure of nwell hole by dnwell outside v20 and in cell names with \"*_tech_CD_top*\" < ${dnwell_over_nwell_enc} |
| OUTPUT "ENC (OUTSIDE nwellHoles nwell_exempted_regions) (OUTSIDE dnwell nwell_exempted_regions) < ${dnwell_over_nwell_enc} MEASURE ALL ABUT < 90 SINGULAR REGION" |
| } |
| |
| #" |
| |
| RULECHECK nwell.SP.11 { |
| @ nwell.SP.11: Min spacing between (nwell AND deep nwell) on separate nets outside of cell names with \"*_tech_CD_top*\" < ${nwell_dnwell_no_minspace_val} |
| OUTPUT "EXTERNAL dnwellNotTechCD nwellNotTechCD < ${nwell_dnwell_no_minspace_val} MEASURE ALL NOT CONNECTED REGION" |
| } |
| |
| #" |
| |
| |
| RULECHECK nwell.ENC.3 { |
| @ nwell.ENC.3: dnwell must completely enclose nwell inside v20 |
| OUTPUT "nw_v20 NOT dnwell_v20" |
| } |
| |
| RULECHECK nwell.CON.1 { |
| @ nwell.CON.1: different voltage nwell should not be on the same net |
| OUTPUT "NET AREA RATIO nw_1p8v nw_5v > 0" |
| OUTPUT "NET AREA RATIO nw_1p8v nw_12v > 0" |
| OUTPUT "NET AREA RATIO nw_1p8v nw_20v > 0" |
| |
| OUTPUT "NET AREA RATIO nw_5v nw_1p8v > 0" |
| OUTPUT "NET AREA RATIO nw_5v nw_12v > 0" |
| OUTPUT "NET AREA RATIO nw_5v nw_20v > 0" |
| |
| OUTPUT "NET AREA RATIO nw_12v nw_1p8v > 0" |
| OUTPUT "NET AREA RATIO nw_12v nw_5v > 0" |
| OUTPUT "NET AREA RATIO nw_12v nw_20v > 0" |
| |
| OUTPUT "NET AREA RATIO nw_20v nw_1p8v > 0" |
| OUTPUT "NET AREA RATIO nw_20v nw_5v > 0" |
| OUTPUT "NET AREA RATIO nw_20v nw_12v > 0" |
| } |
| |
| RULECHECK nwell.CON.2 { |
| @ hnwell.CON.2: N-well marked with v5, v12 or v20 must be enclosed by thkox |
| OUTPUT "(OR nw_5v nw_12_20v) NOT thkox" |
| } |
| |
| RULECHECK nwell.CON.3 { |
| @ hnwell.CON.3: N-well connected to 5v source or drain must have v5 marker |
| SETLAYER psd_v5 = "psd AND v5" |
| SETLAYER nsd_v5 = "nsd AND v5" |
| OUTPUT "(NET AREA RATIO nwell psd_v5 > 0) NOT INTERACT v5" |
| OUTPUT "(NET AREA RATIO nwell nsd_v5 > 0) NOT INTERACT v5" |
| } |
| |
| RULECHECK nwell.CON.4 { |
| @ nwell.CON.4: N-well connected to 12v source or drain must have v12 marker |
| SETLAYER psd_v12 = "psd AND v12" |
| SETLAYER nsd_v12 = "nsd AND v12" |
| OUTPUT "(NET AREA RATIO nwell psd_v12 > 0) NOT INTERACT v12" |
| OUTPUT "(NET AREA RATIO nwell nsd_v12 > 0) NOT INTERACT v12" |
| } |
| |
| RULECHECK nwell.CON.5 { |
| @ nwell.CON.5: N-well connected to 20v source or drain must have v20 marker |
| SETLAYER psd_v20 = "psd AND v20" |
| SETLAYER nsd_v20 = "nsd AND v20" |
| OUTPUT "(NET AREA RATIO nwell psd_v20 > 0) NOT INTERACT v20" |
| OUTPUT "(NET AREA RATIO nwell nsd_v20 > 0) NOT INTERACT v20" |
| } |
| |
| verbatim { |
| |
| // |
| // Antenna checks |
| // |
| |
| #IFNDEF SKIP_ANTENNA_CHECKS |
| |
| DISCONNECT |
| |
| } |
| |
| SETLAYER Ant_short = "(tap NOT poly) NOT nwell" |
| SETLAYER SRCDRNTAP = "diffTap NOT poly" |
| SETLAYER Ant_diode = "SRCDRNTAP NOT Ant_short" |
| SETLAYER Gate_ant = "poly AND diffTap" |
| |
| verbatim { |
| |
| CONNECT poly Gate_ant |
| |
| } |
| |
| SETLAYER ar_poly = "NET AREA RATIO poly Gate_ant > 50 \[PERIMETER(poly) * 0.180000 / AREA(Gate_ant)\] RDB ar_poly.db poly Gate_ant BY LAYER" |
| RULECHECK poly.ANT.1 { |
| @ poly.ANT.1: Max ratio poly perimter area/gate area > 50 |
| OUTPUT "INTERACT Gate_ant ar_poly" |
| } |
| |
| verbatim { |
| |
| CONNECT poly Licon |
| |
| } |
| |
| SETLAYER ar_licon = "NET AREA RATIO Licon Gate_ant > 3 RDB ar_licon.db Licon Gate_ant BY LAYER" |
| RULECHECK licon.ANT.1 { |
| @ licon.ANT.1: Max ratio licon area/gate area > 3 |
| OUTPUT "INTERACT Gate_ant (INTERACT poly ar_licon)" |
| } |
| |
| verbatim { |
| |
| CONNECT Li poly BY Licon |
| CONNECT Li SRCDRNTAP BY licon |
| CONNECT Li Ant_diode BY licon |
| CONNECT Li Ant_short BY licon |
| |
| } |
| |
| SETLAYER fgate_1 = "NET AREA RATIO Gate_ant Ant_short == 0" |
| SETLAYER ar_li = "NET AREA RATIO fgate_1 Li Ant_diode > 0.0 \[(((PERIMETER(Li) * 0.100000 / AREA(fgate_1))-75)/450)-(AREA(Ant_diode)*!!AREA(fgate_1))\] RDB ar_Li.db fgate_1 Li Ant_diode BY LAYER" |
| RULECHECK li.ANT.1 { |
| @ li.ANT.1: Max ratio li perimeter/gate area > 75 |
| OUTPUT "COPY ar_li" |
| } |
| |
| verbatim { |
| |
| CONNECT li mcon |
| |
| } |
| |
| SETLAYER fgate_2 = "NET AREA RATIO Gate_ant Ant_short == 0" |
| SETLAYER ar_mcon = "NET AREA RATIO fgate_2 mcon ANT_diode > 0.0 \[(((AREA(mcon)/AREA(fgate_2))-3)/18)-(AREA(Ant_diode)*!!AREA(fgate_2))\] RDB ar_mcon.db fgate_2 mcon ANT_diode BY LAYER" |
| RULECHECK mcon.ANT.1 { |
| @ mcon.ANT.1: Max ratio mcon area/gate area > 3 |
| COPY ar_mcon |
| } |
| |
| verbatim { |
| |
| CONNECT met1 li BY mcon |
| |
| } |
| |
| SETLAYER fgate_3 = "NET AREA RATIO Gate_ant Ant_short == 0" |
| SETLAYER ar_met1 = "NET AREA RATIO fgate_3 Met1 Ant_diode > 0.0 \[((((PERIMETER(Met1) * 0.350000 / AREA(fgate_3))-400)-(!!AREA(Ant_diode)*2200))/400)-(AREA(Ant_diode)*!!AREA(fgate_3))\] RDB ar_met1.db fgate_3 Met1 Ant_diode BY LAYER" |
| RULECHECK met1.ANT.1 { |
| @ met1.ANT.1: Max ratio met1 perimeter/gate area > 400 |
| COPY ar_met1 |
| } |
| |
| verbatim { |
| |
| CONNECT Met1 Via1 |
| |
| } |
| |
| SETLAYER fgate_4 = "NET AREA RATIO Gate_ant Ant_short == 0" |
| SETLAYER ar_via = "NET AREA RATIO fgate_4 Via1 ANT_diode > 0.0 \[(((AREA(Via1)/AREA(fgate_4))-6)/36)-(AREA(Ant_diode)*!!AREA(fgate_4))\] RDB ar_via.db fgate_4 Via1 ANT_diode BY LAYER" |
| RULECHECK via1.ANT.1 { |
| @ via1.ANT.1: Max ratio via1 area/gate area > 6 |
| COPY ar_via |
| } |
| |
| verbatim { |
| |
| CONNECT Met2 Met1 BY Via1 |
| |
| } |
| |
| SETLAYER fgate_5 = "NET AREA RATIO Gate_ant Ant_short == 0" |
| SETLAYER ar_met2 = "NET AREA RATIO fgate_5 Met2 Ant_diode > 0.0 \[((((PERIMETER(Met2) * 0.350000 / AREA(fgate_5))-400)-(!!AREA(Ant_diode)*2200))/400)-(AREA(Ant_diode)*!!AREA(fgate_5))\] RDB ar_met2.db fgate_5 Met2 Ant_diode BY LAYER" |
| RULECHECK met2.ANT.1 { |
| @ met2.ANT.1: Max ratio met2 perimeter/gate area > 400 |
| COPY ar_met2 |
| } |
| |
| verbatim { |
| |
| CONNECT Met2 Via2 |
| |
| } |
| |
| SETLAYER fgate_6 = "NET AREA RATIO Gate_ant Ant_short == 0" |
| SETLAYER ar_via2 = "NET AREA RATIO fgate_6 Via2 ANT_diode > 0.0 \[(((AREA(Via2)/AREA(fgate_6))-6)/36)-(AREA(Ant_diode)*!!AREA(fgate_6))\] RDB ar_via2.db fgate_6 Via2 ANT_diode BY LAYER" |
| RULECHECK via2.ANT.1 { |
| @ via2.ANT.1: Max ratio via2 area/gate area > 6 |
| COPY ar_via2 |
| } |
| |
| verbatim { |
| |
| CONNECT Met3 Met2 BY Via2 |
| |
| } |
| |
| SETLAYER fgate_7 = "NET AREA RATIO Gate_ant Ant_short == 0" |
| SETLAYER ar_met3 = "NET AREA RATIO fgate_7 Met3 Ant_diode > 0.0 \[((((PERIMETER(Met3) * 0.800000 /AREA(fgate_7))-400)-(!!AREA(Ant_diode)*2200))/400)-(AREA(Ant_diode)*!!AREA(fgate_7))\] RDB ar_met3.db fgate_7 Met3 Ant_diode BY LAYER" |
| RULECHECK met3.ANT.1 { |
| @ met3.ANT.1: Max ratio met3 perimeter/gate area > 400 |
| COPY ar_met3 |
| } |
| |
| verbatim { |
| |
| CONNECT Met3 Via3 |
| |
| } |
| |
| SETLAYER fgate_8 = "NET AREA RATIO Gate_ant Ant_short == 0" |
| SETLAYER ar_via3 = "NET AREA RATIO fgate_8 Via3 ANT_diode > 0.0 \[(((AREA(Via3)/AREA(fgate_8))-6)/36)-(AREA(Ant_diode)*!!AREA(fgate_8))\] RDB ar_via3.db fgate_8 Via3 ANT_diode BY LAYER" |
| RULECHECK via3.ANT.1 { |
| @ via3.ANT.1: Max ratio via3 area/gate area > 6 |
| COPY ar_via3 |
| } |
| |
| verbatim { |
| |
| CONNECT Met4 Met3 BY Via3 |
| |
| } |
| |
| SETLAYER fgate_9 = "NET AREA RATIO Gate_ant Ant_short == 0" |
| SETLAYER ar_met4 = "NET AREA RATIO fgate_9 Met4 Ant_diode > 0.0 \[((((PERIMETER(Met4) * 0.800000 /AREA(fgate_9))-400)-(!!AREA(Ant_diode)*2200))/400)-(AREA(Ant_diode)*!!AREA(fgate_9))\] RDB ar_met4.db fgate_9 Met4 Ant_diode BY LAYER" |
| RULECHECK met4.ANT.1 { |
| @ met4.ANT.1: Max ratio met4 perimeter/gate area > 400 |
| COPY ar_met4 |
| } |
| |
| verbatim { |
| |
| CONNECT Met4 Via4 |
| |
| } |
| |
| SETLAYER fgate_10 = "NET AREA RATIO Gate_ant Ant_short == 0" |
| SETLAYER ar_via4 = "NET AREA RATIO fgate_10 Via4 ANT_diode > 0.0 \[(((AREA(Via4)/AREA(fgate_10))-6)/36)-(AREA(Ant_diode)*!!AREA(fgate_10))\] RDB ar_via4.db fgate_10 Via4 ANT_diode BY LAYER" |
| RULECHECK via4.ANT.1 { |
| @ via4.ANT.1: Max ratio via4 area/gate area > 6 |
| COPY ar_via4 |
| } |
| |
| verbatim { |
| |
| CONNECT Met5 Met4 BY Via4 |
| |
| } |
| |
| SETLAYER fgate_11 = "NET AREA RATIO Gate_ant Ant_short == 0" |
| SETLAYER ar_met5 = "NET AREA RATIO fgate_11 Met5 Ant_diode > 0.0 \[((((PERIMETER(Met5) * 1.200000 /AREA(fgate_11))-400)-(!!AREA(Ant_diode)*2200))/400)-(AREA(Ant_diode)*!!AREA(fgate_11))\] RDB ar_met5.db fgate_11 Met5 Ant_diode BY LAYER" |
| RULECHECK met5.ANT.1 { |
| @ met5.ANT.1: Max ratio met5 perimeter/gate area > 400 |
| COPY ar_met5 |
| } |
| |
| verbatim { |
| #IFNDEF SKIP_RECOMMENDED_CHECKS |
| DISCONNECT |
| CONNECT met5 met4 BY via4 |
| CONNECT met4 met3 BY via3 |
| CONNECT met3 met2 BY via2 |
| CONNECT met2 met1 BY via1 |
| CONNECT met1 li BY mcon |
| CONNECT SRCDRN li BY licon |
| CONNECT tap li BY licon |
| CONNECT ptap li BY licon |
| } |
| |
| SETLAYER met2Conntap = "NET AREA RATIO met2 tap > 0" |
| SETLAYER met2Conndiff = "NET AREA RATIO met2 SRCDRN > 0" |
| SETLAYER met2ConnPtap = "NET AREA RATIO met2 PTAP > 0" |
| SETLAYER met2Conndifftap = "met2Conntap OR met2Conndiff" |
| SETLAYER met2NotConndifftap = "met2 NOT met2Conndifftap" |
| SETLAYER met2NotConnVia = "met2NotConndifftap INTERACT via2 > 2" |
| SETLAYER met2GroundOrFloat = "met2ConnPtap OR met2NotConndifftap" |
| SETLAYER met2GroundOrFloatVia = "met2GroundOrFloat INTERACT via2 > 2" |
| SETLAYER met3_via2 = "met3 INTERACT via2" |
| SETLAYER met3_over_floatingm2 = "met3_via2 AND met2GroundOrFloat" |
| |
| verbatim { |
| CONNECT met2NotConnVia met3_over_floatingm2 BY via2 |
| CONNECT met2GroundOrFloatVia met3_over_floatingm2 BY via2 |
| } |
| |
| SETLAYER AR_MM2_more05 = "NET AREA RATIO met2NotConnVia via2 >= 20.0 \[(2*AREA(met2NotConnVia)+ PERIMETER(met2NotConnVia) * 0.35)/(AREA(via2))\]" |
| |
| SETLAYER AR_MM2_less03 = "NET AREA RATIO met2GroundOrFloatVia via2 <= 31.25 \[(2*AREA(met2GroundOrFloatVia)+PERIMETER(met2GroundOrFloatVia)*0.35)/(AREA(via2))\]" |
| |
| SETLAYER crater = "(EXTERNAL AR_MM2_more05 AR_MM2_less03 == 0.14 ABUT<90 SINGULAR REGION EXCLUDE FALSE) NOT STDCID" |
| |
| RULECHECK met2.ANT.2 { |
| @ met2.ANT.2: met2 spacing between (met2 areas with met2-to-via2 surface area ratio >=20.0) and (met2 areas with met2-to-via2 surface area ratio <= 31.25) == 0.14 |
| COPY crater |
| } |
| |
| verbatim { |
| #ENDIF //Recomended |
| #ENDIF //Antenna |
| } |
| |
| ### DENSITY: |
| |
| ### |
| ### Contains DENSITY rules |
| ### |
| |
| verbatim { #IFNDEF SKIP_DENSITY_CHECKS } |
| |
| SETLAYER chip_and_seal_hole = "SIZE sealid_hole BY -13" |
| SETLAYER chip_not_sealring_hole = "boundary NOT chip_and_seal_hole" |
| SETLAYER fill_extent = "chip_and_seal_hole OR (boundary NOT INTERACT SEALID)" |
| |
| proc chk_met_dens {layer layer_input fill_layer fill_blk_lay min_density max_density min_dens_percent max_dens_percent} { |
| |
| set a 1 |
| set local_win 200 |
| set local_step 100 |
| set chip_win 700 |
| set chip_step 70 |
| |
| |
| verbatim { #IFDEF GENERATE_PREDICTIVE_FILL } |
| |
| if {${layer_input} == "met1i" || ${layer_input} == "met2i" || ${layer_input} == "met3i" || ${layer_input} == "met4i"} { set size_amt 0.3} |
| |
| if {${layer_input} == "met1i" || ${layer_input} == "met2i" || ${layer_input} == "met3i" || ${layer_input} == "met4i"} { set rect_size_1st 2.0} |
| if {${layer_input} == "met1i" || ${layer_input} == "met2i" || ${layer_input} == "met3i" || ${layer_input} == "met4i"} { set rect_size_2nd 1.0} |
| if {${layer_input} == "met1i" || ${layer_input} == "met2i" || ${layer_input} == "met3i" || ${layer_input} == "met4i"} { set rect_size_3rd 0.58} |
| |
| if {${layer_input} == "met1i" || ${layer_input} == "met2i"} { set rect_space_1st 0.2} |
| if {${layer_input} == "met3i" || ${layer_input} == "met4i"} { set rect_space_1st 0.3} |
| |
| if {${layer_input} == "met1i" || ${layer_input} == "met2i"} { set rect_space_2nd 0.2} |
| if {${layer_input} == "met3i" || ${layer_input} == "met4i"} { set rect_space_2nd 0.3} |
| |
| if {${layer_input} == "met1i" || ${layer_input} == "met2i"} { set rect_space_3rd 0.2} |
| if {${layer_input} == "met3i" || ${layer_input} == "met4i"} { set rect_space_3rd 0.3} |
| |
| if {${layer_input} == "met5i"} { set size_amt 3.0} |
| if {${layer_input} == "met5i"} { set rect_size 3.0} |
| if {${layer_input} == "met5i"} { set rect_space 3.0} |
| |
| if {${layer_input} != "met5i"} { |
| SETLAYER keepout_1_${layer} = "SIZE ${layer_input} BY ${size_amt}" |
| SETLAYER keepout_2_${layer} = "SIZE capacitor BY 3" |
| SETLAYER keepout_3_${layer} = "SIZE target BY 3.295" |
| SETLAYER keepout_4_${layer} = "SIZE nsm BY 1" |
| SETLAYER keepout_5_${layer} = "SIZE dieCut BY 3" |
| SETLAYER keepout_6_${layer} = "SIZE ${fill_layer} BY 0.3" |
| SETLAYER keepout_7_${layer} = "SIZE (${layer}_block OR ${fill_blk_lay}) BY ${size_amt}" |
| SETLAYER keepout_${layer}_1st = "OR keepout_1_${layer} keepout_2_${layer} keepout_3_${layer} keepout_4_${layer} keepout_5_${layer} keepout_6_${layer} keepout_7_${layer}" |
| |
| SETLAYER target_fill_area_${layer}_1st = "fill_extent NOT keepout_${layer}_1st" |
| SETLAYER psuedo_fill_${layer}_1st = "RECTANGLES ${rect_size_1st} ${rect_size_1st} ${rect_space_1st} INSIDE OF LAYER target_fill_area_${layer}_1st" |
| |
| SETLAYER target_fill_area_${layer}_2nd = "target_fill_area_${layer}_1st NOT (SIZE psuedo_fill_${layer}_1st BY 0.3)" |
| SETLAYER psuedo_fill_${layer}_2nd = "RECTANGLES ${rect_size_2nd} ${rect_size_2nd} ${rect_space_2nd} INSIDE OF LAYER target_fill_area_${layer}_2nd" |
| |
| SETLAYER target_fill_area_${layer}_3rd = "target_fill_area_${layer}_2nd NOT (SIZE psuedo_fill_${layer}_2nd BY 0.3)" |
| SETLAYER psuedo_fill_${layer}_3rd = "RECTANGLES ${rect_size_3rd} ${rect_size_3rd} ${rect_space_3rd} INSIDE OF LAYER target_fill_area_${layer}_3rd" |
| |
| SETLAYER psuedo_fill_${layer} = "OR psuedo_fill_${layer}_1st psuedo_fill_${layer}_2nd psuedo_fill_${layer}_3rd" |
| RULECHECK view_${layer}_predictive_fill { OUTPUT "COPY psuedo_fill_${layer}" } |
| } else { |
| SETLAYER keepout_1_met5 = "SIZE ${layer_input} BY ${size_amt}" |
| SETLAYER keepout_2_met5 = "SIZE (capm OR cap2m) BY 3" |
| SETLAYER keepout_3_met5 = "SIZE target BY 3.295" |
| SETLAYER keepout_4_met5 = "SIZE nsm BY 1" |
| SETLAYER keepout_5_met5 = "SIZE dieCut BY 3" |
| SETLAYER keepout_6_met5 = "SIZE ${fill_layer} BY 0.3" |
| SETLAYER keepout_7_met5 = "SIZE (${layer}_block OR ${fill_blk_lay}) BY ${size_amt}" |
| SETLAYER keepout_met5 = "OR keepout_1_met5 keepout_2_met5 keepout_3_met5 keepout_4_met5 keepout_5_met5 keepout_6_met5 keepout_7_met5" |
| |
| SETLAYER target_fill_area_met5 = "fill_extent NOT keepout_met5" |
| SETLAYER psuedo_fill_${layer} = "RECTANGLES ${rect_size} ${rect_size} ${rect_space} INSIDE OF LAYER target_fill_area_met5" |
| RULECHECK view_met5_predictive_fill { OUTPUT "COPY psuedo_fill_met5" } |
| } |
| |
| verbatim { #ENDIF //predictive fill } |
| |
| verbatim { #IFDEF GENERATE_PREDICTIVE_FILL } |
| SETLAYER layer_to_check_${layer} = "OR ${layer_input} psuedo_fill_${layer} ${fill_layer}" |
| verbatim { #ENDIF //predictive fill } |
| verbatim { #IFNDEF GENERATE_PREDICTIVE_FILL } |
| |
| if {${layer_input} == "met1i" || ${layer_input} == "met2i"} { set met_over 0.6} |
| if {${layer_input} == "met3i" || ${layer_input} == "met4i"} { set met_over 1.15} |
| if {${layer_input} == "met5i"} { set met_over 0.0} |
| SETLAYER layer_to_check_${layer} = "(SIZE ${layer_input} BY ${met_over}) OR ${fill_layer}" |
| #SETLAYER layer_to_check_${layer} = "${layer_input} OR ${fill_layer}" |
| verbatim { #ENDIF //predictive fill } |
| |
| verbatim { #IFDEF GENERATE_LOCAL_DENSITY } |
| RULECHECK ${layer}.local.low.DEN.${a} { |
| @ ${layer}.local.low.DEN.${a}: Layer ${layer} local density (${local_win} square micron window stepped at ${local_step}) < ${min_density}% |
| OUTPUT "DENSITY layer_to_check_${layer} < ${min_dens_percent} WINDOW ${local_win} STEP ${local_step} INSIDE OF LAYER fill_extent RDB ${layer}_local_low_density.rdb" |
| } |
| incr a |
| RULECHECK ${layer}.local.high.DEN.${a} { |
| @ ${layer}.local.high.DEN.${a}: Layer ${layer} local density (${local_win} square micron window stepped at ${local_step}) > ${max_density}% |
| OUTPUT "DENSITY layer_to_check_${layer} > ${max_dens_percent} WINDOW ${local_win} STEP ${local_step} INSIDE OF LAYER fill_extent RDB ${layer}_local_high_density.rdb" |
| } |
| verbatim { #ENDIF } |
| incr a |
| RULECHECK ${layer}.chip.low.DEN.${a} { |
| @ ${layer}.chip.low.DEN.${a}: Layer ${layer} chip density (${chip_win} square micron window stepped at ${chip_step}) < ${min_density}% |
| OUTPUT "DENSITY layer_to_check_${layer} < ${min_dens_percent} WINDOW ${chip_win} STEP ${chip_step} INSIDE OF LAYER fill_extent RDB ${layer}_chip_low_density.rdb" |
| } |
| incr a |
| RULECHECK ${layer}.chip.high.DEN.${a} { |
| @ ${layer}.chip.high.DEN.${a}: Layer ${layer} chip density ($chip_win) square micron window stepped at ${chip_step}) > ${max_density}% |
| OUTPUT "DENSITY layer_to_check_${layer} > ${max_dens_percent} WINDOW ${chip_win} STEP ${chip_step} INSIDE OF LAYER fill_extent RDB ${layer}_chip_high_density.rdb" |
| } |
| } |
| |
| chk_met_dens "met1" "met1i" "MM1mk" "cmm1WaffleDrop" "30" "80" ".30" ".80" |
| chk_met_dens "met2" "met2i" "MM2mk" "cmm2WaffleDrop" "30" "80" ".30" ".80" |
| chk_met_dens "met3" "met3i" "MM3mk" "cmm3WaffleDrop" "30" "80" ".30" ".80" |
| chk_met_dens "met4" "met4i" "MM4mk" "cmm4WaffleDrop" "30" "80" ".30" ".80" |
| chk_met_dens "met5" "met5i" "MM5mk" "cmm5WaffleDrop" "19" "60" ".19" ".60" |
| |
| # |
| # metal local denisty under fill block |
| # |
| # |
| |
| SETLAYER chip = "COPY boundary" |
| SETLAYER chipAreaBigEnough = "AREA chip > 40000.0" |
| SETLAYER entireChipForDensity = "chip INTERACT sealHoles" |
| |
| proc met_dens_under_block { layer blayer } { |
| |
| SETLAYER ${layer}outOxide_drc = "SIZE ${layer} BY 0.6" |
| SETLAYER waffle1DropDensity70_${layer} = "DENSITY ${blayer} == 1.0 WINDOW 700 STEP 70" |
| SETLAYER ${layer}_DensityUnder70 = "DENSITY ${layer}outOxide_drc < 0.7 WINDOW 700 STEP 70 INSIDE of LAYER waffle1DropDensity70_${layer} RDB ${layer}.chip.low.DEN_under_100_fill_block.1.rdb" |
| SETLAYER ${layer}_DensityUnder70Chip = "${layer}_DensityUnder70 INTERACT entireChipForDensity" |
| SETLAYER ${layer}_DensityUnder70tmp = "${layer}_DensityUnder70 NOT ${layer}_DensityUnder70Chip" |
| SETLAYER ${layer}_DensityUnder70IP = "${layer}_DensityUnder70tmp AND chipAreaBigEnough" |
| |
| RULECHECK ${layer}.low.DEN_under_100_fill_block.1_IP { |
| @ ${layer}.low.DEN_under_100_fill_block.1_IP: <70% ${layer} density when 700x700 window 100% covered by ${layer} fill block (IP) < 70% |
| OUTPUT "COPY ${layer}_DensityUnder70IP" |
| } |
| |
| RULECHECK ${layer}.low.DEN_under_100_fill_block.1_CHIP { |
| @ ${layer}.low.DEN_under_100_fill_block.1_CHIP: <70% ${layer} density when 700x700 window 100% covered by ${layer} fill block (CHIP) < 70% |
| OUTPUT "COPY ${layer}_DensityUnder70Chip" |
| } |
| |
| SETLAYER waffle1DropDensity65_${layer} = "DENSITY ${blayer} > 0.8 <= 1.0 WINDOW 700 STEP 70" |
| SETLAYER ${layer}_DensityUnder65 = "DENSITY ${layer}outOxide_drc < 0.65 WINDOW 700 STEP 70 INSIDE of LAYER waffle1DropDensity65_${layer} RDB ${layer}.chip.low.DEN_under_80_fill_block.1.rdb" |
| SETLAYER ${layer}_DensityUnder65Chip = "INTERACT ${layer}_DensityUnder65 entireChipForDensity" |
| SETLAYER ${layer}_DensityUnder65tmp = "${layer}_DensityUnder65 NOT ${layer}_DensityUnder65Chip" |
| SETLAYER ${layer}_DensityUnder65IP = "${layer}_DensityUnder65tmp AND chipAreaBigEnough" |
| |
| RULECHECK ${layer}.low.DEN_under_80_fill_block.1_IP { |
| @ ${layer}.low.DEN_under_80_fill_block.1_IP: ${layer} density when 700x700 window 80-100% covered by ${layer} fill block (IP) < 65% |
| OUTPUT "COPY ${layer}_DensityUnder65IP" |
| } |
| |
| RULECHECK ${layer}.low.DEN_under_80_fill_block.1_CHIP { |
| @ ${layer}.low.DEN_under_80_fill_block.1_CHIP: ${layer} density when 700x700 window 80-100% covered by ${layer} fill block (CHIP) < 65% |
| OUTPUT "COPY ${layer}_DensityUnder65Chip" |
| } |
| |
| SETLAYER waffle1DropDensity60_${layer} = "DENSITY ${blayer} > 0.6 <= 0.8 WINDOW 700 STEP 70" |
| SETLAYER ${layer}_DensityUnder60 = "DENSITY ${layer}outOxide_drc < 0.6 WINDOW 700 STEP 70 INSIDE of LAYER waffle1DropDensity60_${layer} RDB ${layer}.chip.low.DEN_under_60_fill_block.1.rdb" |
| SETLAYER ${layer}_DensityUnder60Chip = "INTERACT ${layer}_DensityUnder60 entireChipForDensity" |
| SETLAYER ${layer}_DensityUnder60tmp = "${layer}_DensityUnder60 NOT ${layer}_DensityUnder60Chip" |
| SETLAYER ${layer}_DensityUnder60IP = "${layer}_DensityUnder60tmp AND chipAreaBigEnough" |
| |
| RULECHECK ${layer}.low.DEN_under_60_fill_block.1_IP { |
| @ ${layer}.low.DEN_under_60_fill_block.1_IP: ${layer} density when 700x700 window 60-80% covered by ${layer} fill block (IP) < 60% |
| OUTPUT "COPY ${layer}_DensityUnder60IP" |
| } |
| |
| RULECHECK ${layer}.low.DEN_under_60_fill_block.1_CHIP { |
| @ ${layer}.low.DEN_under_60_fill_block.1_CHIP: ${layer} density when 700x700 window 60-80% covered by ${layer} fill block (CHIP) < 60% |
| OUTPUT "COPY ${layer}_DensityUnder60Chip" |
| } |
| |
| SETLAYER waffle1DropDensity50_${layer} = "DENSITY ${blayer} > 0.5 <= 0.6 WINDOW 700 STEP 70" |
| SETLAYER ${layer}_DensityUnder50 = "DENSITY ${layer}outOxide_drc < 0.5 WINDOW 700 STEP 70 INSIDE of LAYER waffle1DropDensity50_${layer} RDB ${layer}.chip.low.DEN_under_50_fill_block.1.rdb" |
| SETLAYER ${layer}_DensityUnder50Chip = "INTERACT ${layer}_DensityUnder50 entireChipForDensity" |
| SETLAYER ${layer}_DensityUnder50tmp = "${layer}_DensityUnder50 NOT ${layer}_DensityUnder50Chip" |
| SETLAYER ${layer}_DensityUnder50IP = "${layer}_DensityUnder50tmp AND chipAreaBigEnough" |
| |
| RULECHECK ${layer}.low.DEN_under_50_fill_block.1_IP { |
| @ ${layer}.low.DEN_under_50_fill_block.1_IP: ${layer} density when 700x700 window 50-60% covered by ${layer} fill block (IP) < 50% |
| OUTPUT "COPY ${layer}_DensityUnder50IP" |
| } |
| |
| RULECHECK ${layer}.low.DEN_under_50_fill_block.1_CHIP { |
| @ ${layer}.low.DEN_under_50_fill_block.1_CHIP: ${layer} density when 700x700 window 50-60% covered by ${layer} fill block (CHIP)_ < 50% |
| OUTPUT "COPY ${layer}_DensityUnder50Chip" |
| } |
| |
| SETLAYER waffle1DropDensity40_${layer} = "DENSITY ${blayer} > 0.4 <= 0.5 WINDOW 700 STEP 70" |
| SETLAYER ${layer}_DensityUnder40 = "DENSITY ${layer}outOxide_drc < 0.4 WINDOW 700 STEP 70 INSIDE of LAYER waffle1DropDensity40_${layer} RDB ${layer}.chip.low.DEN_under_40_fill_block.1.rdb" |
| SETLAYER ${layer}_DensityUnder40Chip = "INTERACT ${layer}_DensityUnder40 entireChipForDensity" |
| SETLAYER ${layer}_DensityUnder40tmp = "${layer}_DensityUnder40 NOT ${layer}_DensityUnder40Chip" |
| SETLAYER ${layer}_DensityUnder40IP = "${layer}_DensityUnder40tmp AND chipAreaBigEnough" |
| |
| RULECHECK ${layer}.low.DEN_under_40_fill_block.1_IP { |
| @ ${layer}.low.DEN_under_40_fill_block.1_IP: ${layer} density when 700x700 window 40-50% covered by ${layer} fill block (IP) < 40% |
| OUTPUT "COPY ${layer}_DensityUnder40IP" |
| } |
| |
| RULECHECK ${layer}.low.DEN_under_40_fill_block.1_CHIP { |
| @ ${layer}.low.DEN_under_40_fill_block.1_CHIP: ${layer} density when 700x700 window 40-50% covered by ${layer} fill block (CHIP) < 40% |
| COPY ${layer}_DensityUnder40Chip |
| } |
| |
| SETLAYER waffle1DropDensity30_${layer} = "DENSITY ${blayer} > 0.3 <= 0.4 WINDOW 700 STEP 70" |
| SETLAYER ${layer}_DensityUnder30 = "DENSITY ${layer}outOxide_drc < 0.3 WINDOW 700 STEP 70 INSIDE of LAYER waffle1DropDensity30_${layer} RDB ${layer}.chip.low.DEN_under_30_fill_block.1.rdb" |
| SETLAYER ${layer}_DensityUnder30Chip = "INTERACT ${layer}_DensityUnder30 entireChipForDensity" |
| SETLAYER ${layer}_DensityUnder30tmp = "${layer}_DensityUnder30 NOT ${layer}_DensityUnder30Chip" |
| SETLAYER ${layer}_DensityUnder30IP = "${layer}_DensityUnder30tmp AND chipAreaBigEnough" |
| |
| RULECHECK ${layer}.low.DEN_under_30_fill_block.1_IP { |
| @ ${layer}.low.DEN_under_30_fill_block.1_IP: ${layer} density when 700x700 window 30-40% covered by ${layer} fill block (IP) < 30% |
| OUTPUT "COPY ${layer}_DensityUnder30IP" |
| } |
| |
| RULECHECK ${layer}.low.DEN_under_30_fill_block.1_CHIP { |
| @ ${layer}.low.DEN_under_30_fill_block.1_CHIP: ${layer} density when 700x700 window 30-40% covered by ${layer} fill block (CHIP) < 30% |
| OUTPUT "COPY ${layer}_DensityUnder30Chip" |
| } |
| |
| } |
| |
| met_dens_under_block "met1" "cmm1WaffleDrop" |
| met_dens_under_block "met2" "cmm2WaffleDrop" |
| met_dens_under_block "met3" "cmm3WaffleDrop" |
| met_dens_under_block "met4" "cmm4WaffleDrop" |
| |
| set local_win 50 |
| set local_step 25 |
| set chip_win 700 |
| set chip_step 70 |
| set diff_poly_chip_win 500 |
| set diff_poly_chip_step 100 |
| |
| # |
| # Diff/Poly section: |
| # |
| verbatim { #IFDEF GENERATE_PREDICTIVE_FILL } |
| |
| set diff_rect_size_1st 4.08 |
| set diff_rect_space_1st 4.08 |
| set diff_rect_size_2nd 2.05 |
| set diff_rect_space_2nd 1.32 |
| set diff_rect_size_3rd 1.5 |
| set diff_rect_space_3rd 1.32 |
| set diff_rect_size_4th 0.5 |
| set diff_rect_space_4th 0.4 |
| |
| set poly_rect_size_1st 0.72 |
| set poly_rect_space_1st 0.8 |
| set poly_rect_size_2nd 0.54 |
| set poly_rect_space_2nd 0.36 |
| set poly_rect_size_3rd 0.48 |
| set poly_rect_space_3rd 0.36 |
| |
| SETLAYER nwell_diff_keepout_1 = "(SIZE nwell BY 0.34) NOT (SIZE NWELL BY -0.18)" |
| SETLAYER nwell_diff_keepout_2 = "(SIZE (HOLES nwell) BY 0.34) NOT (SIZE (HOLES NWELL) BY -0.18)" |
| SETLAYER nwell_diff_poly_keepout = "nwell_diff_keepout_1 OR nwell_diff_keepout_2" |
| |
| SETLAYER diff_poly_keepout = "SIZE (OR pwbm pwres PHdiodeID) BY 0.5" |
| |
| SETLAYER diff_keepout_0 = "SIZE (OR pwbm pwres PHdiodeID) BY 0.5" |
| SETLAYER diff_keepout_1 = "SIZE diffi BY 0.5" |
| SETLAYER diff_keepout_2 = "SIZE target BY 3.295" |
| SETLAYER diff_keepout_3 = "SIZE nsm BY 1" |
| SETLAYER diff_keepout_4 = "SIZE dieCut BY 3" |
| SETLAYER diff_keepout_5 = "SIZE fomWaffDrop BY ${diff_rect_space_4th}" |
| SETLAYER diff_keepout_6 = "SIZE (OR diff_block polyi fomWaffDrop P1Mmk) BY 0.30" |
| SETLAYER diff_keepout = "OR nwell_diff_poly_keepout diff_keepout_0 diff_keepout_1 diff_keepout_2 diff_keepout_3 diff_keepout_4 diff_keepout_5 diff_keepout_6" |
| |
| SETLAYER poly_keepout_1 = "SIZE polyi BY 0.5" |
| SETLAYER poly_keepout_2 = "SIZE target BY 3.295" |
| SETLAYER poly_keepout_3 = "SIZE nsm BY 1" |
| SETLAYER poly_keepout_4 = "SIZE dieCut BY 3" |
| SETLAYER poly_keepout_5 = "SIZE (OR poly_block diffi cp1mWaffleDrop P1Mmk cfom) BY 0.30" |
| SETLAYER poly_keepout = "OR diff_poly_keepout nwell_diff_poly_keepout poly_keepout_1 poly_keepout_2 poly_keepout_3 poly_keepout_4 poly_keepout_5" |
| |
| # 1st pass fill for diff and poly |
| SETLAYER diff_target_fill_area_1st = "fill_extent NOT diff_keepout" |
| SETLAYER diff_psuedo_fill_1st = "RECTANGLES ${diff_rect_size_1st} ${diff_rect_size_1st} ${diff_rect_space_1st} INSIDE OF LAYER diff_target_fill_area_1st" |
| |
| SETLAYER poly_target_fill_area_1st = "fill_extent NOT (poly_keepout OR (SIZE diff_psuedo_fill_1st BY 0.3))" |
| SETLAYER poly_psuedo_fill_1st = "RECTANGLES ${poly_rect_size_1st} ${poly_rect_size_1st} ${poly_rect_space_1st} INSIDE OF LAYER poly_target_fill_area_1st OFFSET 1 1" |
| |
| # 2nd pass fill for diff and poly |
| SETLAYER diff_target_fill_area_2nd = "diff_target_fill_area_1st NOT (OR (SIZE diff_psuedo_fill_1st BY 0.3) (SIZE poly_psuedo_fill_1st BY 0.3))" |
| SETLAYER diff_psuedo_fill_2nd = "RECTANGLES ${diff_rect_size_2nd} ${diff_rect_size_2nd} ${diff_rect_space_2nd} INSIDE OF LAYER diff_target_fill_area_2nd" |
| |
| SETLAYER poly_target_fill_area_2nd = "poly_target_fill_area_1st NOT (OR (SIZE poly_psuedo_fill_1st BY 0.26) (SIZE diff_target_fill_area_2nd BY 0.3))" |
| SETLAYER poly_psuedo_fill_2nd = "RECTANGLES ${poly_rect_size_2nd} ${poly_rect_size_2nd} ${poly_rect_space_2nd} INSIDE OF LAYER poly_target_fill_area_2nd OFFSET 1 1" |
| |
| # 3rd pass fill for diff and poly |
| SETLAYER diff_target_fill_area_3rd = "diff_target_fill_area_2nd NOT (OR (SIZE diff_psuedo_fill_2nd BY 0.3) (SIZE poly_psuedo_fill_2nd BY 0.3))" |
| SETLAYER diff_psuedo_fill_3rd = "RECTANGLES ${diff_rect_size_3rd} ${diff_rect_size_3rd} ${diff_rect_space_3rd} INSIDE OF LAYER diff_target_fill_area_3rd OFFSET .5 .5" |
| |
| SETLAYER poly_target_fill_area_3rd = "poly_target_fill_area_2nd NOT (OR (SIZE poly_psuedo_fill_2nd BY 0.26) (SIZE diff_psuedo_fill_3rd BY 0.3))" |
| SETLAYER poly_psuedo_fill_3rd = "RECTANGLES ${poly_rect_size_3rd} ${poly_rect_size_3rd} ${poly_rect_space_3rd} INSIDE OF LAYER poly_target_fill_area_3rd OFFSET 1 1" |
| |
| # 4th pass fill for diff |
| SETLAYER diff_target_fill_area_4th = "diff_target_fill_area_3rd NOT (OR (SIZE diff_psuedo_fill_3rd BY 0.3) (SIZE poly_psuedo_fill_3rd BY 0.3))" |
| SETLAYER diff_psuedo_fill_4th = "RECTANGLES ${diff_rect_size_4th} ${diff_rect_size_4th} ${diff_rect_space_4th} INSIDE OF LAYER diff_target_fill_area_4th" |
| |
| SETLAYER diff_psuedo_fill = "OR diff_psuedo_fill_1st diff_psuedo_fill_2nd diff_psuedo_fill_3rd diff_psuedo_fill_4th" |
| |
| SETLAYER poly_psuedo_fill = "OR poly_psuedo_fill_1st poly_psuedo_fill_2nd poly_psuedo_fill_3rd" |
| |
| |
| verbatim { #ENDIF //predictive fill} |
| |
| verbatim { #IFDEF GENERATE_PREDICTIVE_FILL } |
| SETLAYER diff_layer_to_check = "OR diffi diff_psuedo_fill" |
| SETLAYER poly_layer_to_check = "OR polyi poly_psuedo_fill" |
| RULECHECK view_diff_predictive_fill { OUTPUT "COPY diff_psuedo_fill" } |
| RULECHECK view_poly_predictive_fill { OUTPUT "COPY poly_psuedo_fill" } |
| verbatim { #ENDIF //predictive fill} |
| verbatim { #IFNDEF GENERATE_PREDICTIVE_FILL } |
| SETLAYER diff_layer_to_check = "COPY diffi" |
| SETLAYER poly_layer_to_check = "COPY polyi" |
| verbatim { #ENDIF //predictive fill} |
| |
| # diff density checks: |
| |
| verbatim { #IFDEF GENERATE_LOCAL_DENSITY } |
| RULECHECK diff.local.low.DEN.1 { |
| @ diff.local.low.DEN.1: Layer diff local density (${local_win} square micron window stepped at ${local_step}) < 28% |
| OUTPUT "DENSITY diff_layer_to_check < .28 WINDOW ${local_win} STEP ${local_step} INSIDE OF LAYER fill_extent RDB diff_local_low_density.rdb" |
| } |
| RULECHECK diff.local.high.DEN.1 { |
| @ diff.local.high.DEN.1: Layer diff local density (${local_win} square micron window stepped at ${local_step}) > 62% |
| OUTPUT "DENSITY diff_layer_to_check > 0.62 WINDOW ${local_win} STEP ${local_step} INSIDE OF LAYER fill_extent RDB diff_local_high_density.rdb" |
| } |
| verbatim { #ENDIF } |
| |
| RULECHECK diff.chip.low.DEN.1 { |
| @ diff.chip.low.DEN.1: Layer diff chip density (${diff_poly_chip_win} square micron window stepped at ${diff_poly_chip_step}) < 28% |
| OUTPUT "DENSITY diff_layer_to_check < .28 WINDOW ${diff_poly_chip_win} STEP ${diff_poly_chip_step} INSIDE OF LAYER fill_extent RDB diff_chip_low_density.rdb" |
| } |
| RULECHECK diff.chip.high.DEN.1 { |
| @ diff.chip.high.DEN.1: Layer diff chip density (${diff_poly_chip_win} square micron window stepped at ${diff_poly_chip_step}) > 62% |
| OUTPUT "DENSITY diff_layer_to_check > 0.62 WINDOW ${diff_poly_chip_win} STEP ${diff_poly_chip_step} INSIDE OF LAYER fill_extent RDB diff_chip_high_density.rdb" |
| } |
| |
| |
| # poly density checks: |
| |
| verbatim { #IFDEF GENERATE_LOCAL_DENSITY } |
| RULECHECK poly.local.low.DEN.1 { |
| @ poly.local.low.DEN.1: Layer poly local density (${local_win} square micron window stepped at ${local_step}) < 30% |
| OUTPUT "DENSITY poly_layer_to_check < .30 WINDOW ${local_win} STEP ${local_step} INSIDE OF LAYER fill_extent RDB poly_local_low_density.rdb" |
| } |
| RULECHECK poly.local.high.DEN.1 { |
| @ poly.local.high.DEN.1: Layer poly local density (${local_win} square micron window stepped at ${local_step}) > 40% |
| OUTPUT "DENSITY poly_layer_to_check > 0.40 WINDOW ${local_win} STEP ${local_step} INSIDE OF LAYER fill_extent RDB poly_local_high_density.rdb" |
| } |
| verbatim { #ENDIF } |
| |
| RULECHECK poly.chip.low.DEN.1 { |
| @ poly.chip.low.DEN.1: Layer poly chip density (${diff_poly_chip_win} square micron window stepped at ${diff_poly_chip_step}) < 30% |
| OUTPUT "DENSITY poly_layer_to_check < .30 WINDOW ${diff_poly_chip_win} STEP ${diff_poly_chip_step} INSIDE OF LAYER fill_extent RDB poly_chip_low_density.rdb" |
| } |
| RULECHECK poly.chip.high.DEN.1 { |
| @ poly.chip.high.DEN.1: Layer poly chip density (${diff_poly_chip_win} square micron window stepped at ${diff_poly_chip_step}) > 52% |
| OUTPUT "DENSITY poly_layer_to_check > 0.52 WINDOW ${diff_poly_chip_win} STEP ${diff_poly_chip_step} INSIDE OF LAYER fill_extent RDB poly_chip_high_density.rdb" |
| } |
| |
| |
| verbatim { #ENDIF //skip density check} |
| |
| # |
| # LATCHUP CHECKS: |
| # |
| |
| verbatim { |
| |
| #IFNDEF SKIP_LATCHUP_CHECKS |
| |
| } |
| |
| RULECHECK latchup.WARN.1 { |
| @ latchup.WARN.1: No pads have any markers for IO, PWR or GND |
| OUTPUT "SIZE (boundary NOT INTERACT (OR (pad INTERACT pad_io) (pad INTERACT pad_gnd) (pad INTERACT pad_pwr))) BY -5.0" |
| } |
| |
| RULECHECK latchup.WARN.2 { |
| @ latchup.WARN.2: pad does not have a marker for IO, PWR or GND |
| OUTPUT "pad NOT INTERACT (OR pad_io pad_gnd pad_pwr)" |
| } |
| |
| |
| ### "GENERIC" latchup rules: |
| |
| SETLAYER diff_and_nw = "diffi AND nwell" |
| SETLAYER diff_not_pdiff = "diffi NOT diff_and_nw" |
| SETLAYER tap_and_nw = "tap AND nwell" |
| SETLAYER tap_not_nw = "tap NOT tap_and_nw" |
| SETLAYER nsrcdrn_lu = "diff_not_pdiff NOT (gate OR diffres)" |
| SETLAYER psrcdrn_lu = "diff_and_nw NOT (gate OR diffres)" |
| SETLAYER poly_no_res = "poly NOT polyres" |
| SETLAYER poly_res_lu = "poly AND polyres" |
| SETLAYER ndiff_res_lu = "diff_not_pdiff AND diffres" |
| SETLAYER pdiff_res_lu = "diff_and_nw AND diffres" |
| SETLAYER metal1 = "COPY met1i" |
| SETLAYER metal2 = "COPY met2i" |
| SETLAYER metal3 = "COPY met3i" |
| SETLAYER metal4 = "COPY met4i" |
| SETLAYER metal5 = "COPY met5i" |
| SETLAYER met1res = "COPY m1res" |
| SETLAYER met2res = "COPY m2res" |
| SETLAYER met3res = "COPY m3res" |
| SETLAYER met4res = "COPY m4res" |
| SETLAYER met5res = "COPY m5res" |
| SETLAYER m1_esd_res = "(metal1 AND met1res) AND ESDID" |
| SETLAYER m1_not_esd_res = "metal1 NOT m1_esd_res" |
| SETLAYER m2_esd_res = "(metal2 AND met2res) AND ESDID" |
| SETLAYER m2_not_esd_res = "metal2 NOT m2_esd_res" |
| SETLAYER m3_esd_res = "(metal3 AND met3res) AND ESDID" |
| SETLAYER m3_not_esd_res = "metal3 NOT m3_esd_res" |
| SETLAYER m4_esd_res = "(metal4 AND met4res) AND ESDID" |
| SETLAYER m4_not_esd_res = "metal4 NOT m4_esd_res" |
| SETLAYER m5_esd_res = "(metal5 AND met5res) AND ESDID" |
| SETLAYER m5_not_esd_res = "metal5 NOT m5_esd_res" |
| SETLAYER licon_outs_diff = "Licon OUTSIDE diffTap" |
| SETLAYER licon_not_outs_diff = "Licon NOT licon_outs_diff" |
| SETLAYER licon_nfom = "(licon_not_outs_diff AND diff_not_pdiff) OR (licon_not_outs_diff AND tap_and_nw)" |
| SETLAYER licon_pfom = "(licon_not_outs_diff AND diff_and_nw) OR (licon_not_outs_diff AND tap_not_nw)" |
| SETLAYER licon_diff = "licon_not_outs_diff AND diff" |
| SETLAYER pad_not_probe = "pad NOT (WITH TEXT pad \"probe-only\" textdraw)" |
| SETLAYER probe_pad_not_probe = "WITH TEXT pad \"probe-only\" textdraw" |
| SETLAYER switched_intPower_met1 = "WITH TEXT met1 \"switched_power\" textdraw" |
| SETLAYER dnw_and_nw = "dnwell AND nwell" |
| SETLAYER iso_sub = "boundary NOT ((dnwell NOT (SIZE dnwell BY -0.01)) OR dnw_and_nw)" |
| SETLAYER local_sub_ring = "localSub NOT (SIZE localSub BY -0.005)" |
| SETLAYER sub_local2 = "iso_sub NOT local_sub_ring" |
| SETLAYER isolated_sub = "COPY sub_local2" |
| SETLAYER isolated_sub_no_pwr = "isolated_sub NOT pwres" |
| SETLAYER iso_sub_ptap = "tap_not_nw AND isolated_sub_no_pwr" |
| |
| verbatim { |
| DISCONNECT |
| CONNECT nwell tap_and_nw |
| CONNECT isolated_sub_no_pwr tap_not_nw BY iso_sub_ptap |
| CONNECT li tap_not_nw BY licon_pfom |
| CONNECT li tap_and_nw BY licon_nfom |
| CONNECT li psrcdrn_lu BY licon_pfom |
| CONNECT li nsrcdrn_lu BY licon_nfom |
| CONNECT m1_not_esd_res li BY mcon |
| CONNECT m2_not_esd_res m1_not_esd_res BY via1 |
| CONNECT m3_not_esd_res m2_not_esd_res BY via2 |
| CONNECT m3_not_esd_res met3 |
| CONNECT m2_not_esd_res met2 |
| CONNECT m1_not_esd_res met1 |
| CONNECT nsrcdrn_lu diff |
| CONNECT psrcdrn_lu diff |
| CONNECT switched_intPower_met1 m1_not_esd_res |
| CONNECT li poly_no_res BY licon_outs_diff |
| CONNECT poly_no_res gate |
| CONNECT pad_not_probe m5_not_esd_res |
| CONNECT probe_pad_not_probe m5_not_esd_res |
| CONNECT m5_not_esd_res m4_not_esd_res BY via4_c |
| CONNECT m4_not_esd_res m3_not_esd_res BY via3_c |
| CONNECT rdl pad_not_probe BY pmm |
| CONNECT rdl probe_pad_not_probe BY pmm |
| } |
| |
| SETLAYER vccNetstap_and_nw = "NET tap_and_nw \"vpwr\" \"vpwr1\" \"vpwr3\" \"vpwr_prb\" \"vccio\" \"vpwr2\"" |
| SETLAYER vccSiptap_and_nw = "NET AREA RATIO tap_and_nw switched_intPower_met1 > 0" |
| SETLAYER vcctap_and_nw = "vccNetstap_and_nw OR vccSiptap_and_nw" |
| SETLAYER vsstap_not_nw = "NET tap_not_nw \"vgnd\" \"vgnd1\" \"vgnd3\" \"vgnd_prb\" \"vgnd_pad\" \"vssio\"" |
| SETLAYER vcctap_not_nw = "NET tap_not_nw \"vpwr\" \"vpwr1\" \"vpwr3\" \"vpwr_prb\" \"vccio\" \"vpwr2\"" |
| SETLAYER vssNSD = "NET nsrcdrn_lu \"vgnd\" \"vgnd1\" \"vgnd3\" \"vgnd_prb\" \"vgnd_pad\" \"vssio\"" |
| SETLAYER vssPSD = "NET psrcdrn_lu \"vgnd\" \"vgnd1\" \"vgnd3\" \"vgnd_prb\" \"vgnd_pad\" \"vssio\"" |
| SETLAYER vccNetsPSD = "NET psrcdrn_lu \"vpwr\" \"vpwr1\" \"vpwr3\" \"vpwr_prb\" \"vccio\" \"vpwr2\"" |
| SETLAYER vccSipPSD = "NET AREA RATIO psrcdrn_lu switched_intPower_met1 > 0" |
| SETLAYER vccNetsNSD = "NET nsrcdrn_lu \"vpwr\" \"vpwr1\" \"vpwr3\" \"vpwr_prb\" \"vccio\" \"vpwr2\"" |
| SETLAYER vccSipNSD = "NET AREA RATIO nsrcdrn_lu switched_intPower_met1 > 0" |
| SETLAYER vccPSD = "vccNetsPSD OR vccSipPSD" |
| SETLAYER vccNSD = "vccNetsNSD OR vccSipNSD" |
| SETLAYER vssNwell = "NET nwell \"vgnd\" \"vgnd1\" \"vgnd3\" \"vgnd_prb\" \"vgnd_pad\" \"vssio\"" |
| SETLAYER lvvccNwell = "COPY 4000" |
| SETLAYER ioNSDnet = "NET nsrcdrn_lu \"io\" \"io1\" \"io2\" \"io4\" \"io_prb\" \"pad5v\" \"io_pad\" \"pad\"" |
| SETLAYER ioPSDnet = "NET psrcdrn_lu \"io\" \"io1\" \"io2\" \"io4\" \"io_prb\" \"pad5v\" \"io_pad\" \"pad\"" |
| SETLAYER iotap_and_nwnet = "NET tap_and_nw \"io\" \"io1\" \"io2\" \"io4\" \"io_prb\" \"pad5v\" \"io_pad\" \"pad\"" |
| SETLAYER iotap_not_nwnet = "NET tap_not_nw \"io\" \"io1\" \"io2\" \"io4\" \"io_prb\" \"pad5v\" \"io_pad\" \"pad\"" |
| SETLAYER ioPads = "NET pad_not_probe \"io\" \"io1\" \"io2\" \"io4\" \"io_prb\" \"pad5v\" \"io_pad\" \"pad\"" |
| SETLAYER ioPadConnNSDnet = "NET AREA RATIO nsrcdrn_lu ioPads > 0" |
| SETLAYER ioPadConnPSDnet = "NET AREA RATIO psrcdrn_lu ioPads > 0" |
| SETLAYER NSDsigPad = "nsrcdrn_lu INSIDE SigPadDiff" |
| SETLAYER PSDsigPad = "psrcdrn_lu INSIDE SigPadDiff" |
| SETLAYER SigPadNtr = "SigPadMetNtr INSIDE SigPadDiff" |
| SETLAYER NSDsigPadNtr = "nsrcdrn_lu INSIDE SigPadNtr" |
| SETLAYER PSDsigPadNtr = "psrcdrn_lu INSIDE SigPadNtr" |
| SETLAYER tap_and_nwsigPad = "tap_and_nw INSIDE SigPadDiff" |
| SETLAYER tap_not_nwsigPad = "tap_not_nw INSIDE SigPadDiff" |
| SETLAYER tap_and_nwsigPadNtr = "tap_and_nw INSIDE SigPadNtr" |
| SETLAYER tap_not_nwsigPadNtr = "tap_not_nw INSIDE SigPadNtr" |
| SETLAYER SigPadWellNtr = "SigPadMetNtr INSIDE SigPadWell" |
| SETLAYER nwellSigPadNtr = "nwell INSIDE SigPadWellNtr" |
| SETLAYER NSDsigPadConn = "STAMP NSDSigPad BY nsrcdrn_lu" |
| SETLAYER PSDsigPadConn = "STAMP PSDSigPad BY psrcdrn_lu" |
| SETLAYER tap_and_nwsigPadConn = "STAMP tap_and_nwSigPad BY tap_and_nw" |
| SETLAYER tap_not_nwsigPadConn = "STAMP tap_not_nwSigPad BY tap_not_nw" |
| SETLAYER ioNSD = "NSDsigPad OR ioNSDnet" |
| SETLAYER ioPSD = "PSDsigPad OR ioPSDnet" |
| SETLAYER iotap_and_nw = "tap_and_nwsigPad OR iotap_and_nwnet" |
| SETLAYER iotap_not_nw = "tap_not_nwsigPad OR iotap_not_nwnet" |
| SETLAYER ioPadConnNSD = "NSDsigPadNtr OR ioPadConnNSDnet" |
| SETLAYER ioPadConnPSD = "PSDsigPadNtr OR ioPadConnPSDnet" |
| SETLAYER ioNSDntr = "(NSDsigPad AND sigPadMetNtr) OR ioNSDnet" |
| SETLAYER ioPSDntr = "(PSDsigPad AND sigPadMetNtr) OR ioPSDnet" |
| SETLAYER ntapRing = "(DONUT tap_and_nw) NOT SEALID" |
| SETLAYER ptapRing = "(DONUT tap_not_nw) NOT SEALID" |
| SETLAYER ptapRingFilled = "HOLES ptapRing" |
| SETLAYER pTaplicon = "licon AND tap_not_nw" |
| SETLAYER nTaplicon = "licon AND tap_and_nw" |
| SETLAYER pTapliconVss = "licon AND vsstap_not_nw" |
| SETLAYER pTapliconNonVss = "pTaplicon NOT pTapliconVss" |
| SETLAYER nTapliconVcc = "licon AND vcctap_and_nw" |
| SETLAYER POLYanddiff_not_pdiff = "poly AND diff_not_pdiff" |
| SETLAYER POLYanddiff_and_nw = "poly AND diff_and_nw" |
| SETLAYER diffCore = "diff AND COREID" |
| SETLAYER ndiffPeri = "diff_not_pdiff NOT diffCore" |
| SETLAYER pdiffPeri = "diff_and_nw NOT diffCore" |
| SETLAYER nwellArea = "(SIZE diff_and_nw BY 1.5) AND nwell" |
| SETLAYER pwellArea = "(SIZE diff_not_pdiff BY 1.5) NOT nwell" |
| SETLAYER nonVccNwell = "nwell OUTSIDE vcctap_and_nw" |
| SETLAYER nonPnpNTap = "tap_and_nw NOT pnp" |
| SETLAYER nonPnpPTap = "tap_not_nw NOT pnp" |
| SETLAYER nDiffRing = "DONUT diff_not_pdiff" |
| SETLAYER nDiffHole = "HOLES nDiffRing" |
| SETLAYER nWellTap = "nwell INSIDE tap_and_nw" |
| SETLAYER nWellTapInHole = "nDiffHole INSIDE nWellTap" |
| SETLAYER ESDnWellTapTmp = "nWellTapInHole AND ESDID" |
| SETLAYER ESDnWellTap = "STAMP ESDnWellTapTmp BY tap_and_nw" |
| SETLAYER nwellDIOESD = "nwell AND (ESDID AND DIODEID)" |
| SETLAYER ESD_diode = "nwellDIOESD OUTSIDE (ESDnWellTap OR poly)" |
| SETLAYER ESD_diff = "diff AND ESDID" |
| # JAG 5/20/21 removed these two lines (not used) |
| #SETLAYER slatchAB = "EXTENT CELL \"slatchA*\" \"slatchB*\" ORIGINAL" |
| #SETLAYER slatch_lvA = "EXTENT CELL \"slatch_lvA*\" ORIGINAL" |
| SETLAYER vssNwellNoXmtCells = "vssNwell NOT (INSIDE CELL nwell \"s8iom0s8_top_lvc_b2b_wopad\" \"s8iom0s8_top_lvclamp\" \"s8atlasana_esd_gnd2gnd_sub_dnwl\" \"s8fpafeg1_tk_lvc_b2b_wopad\")" |
| |
| SETLAYER ptapRingFilledNotRing = "ptapRingFilled NOT ptapRing" |
| SETLAYER ptapRingWithVssNwell = "ptapRingFilledNotRing INTERACT vssNwellNoXmtCells" |
| SETLAYER ptapRingNoVssNwell = "ptapRing INTERACT (ptapRingFilledNotRing NOT INTERACT vssNwellNoXmtCells)" |
| SETLAYER vssNwellPtapRing = "(ptapRing NOT ptapRingNoVssNwell) OUTSIDE ptapRingWithVssNwell" |
| |
| # SETLAYER error_lu1 = "(NOT NET tap_not_nw \"vgnd\" \"vgnd1\" \"vgnd3\" \"vgnd_prb\" \"vgnd_pad\" \"vssio\") AND vssNwellPtapRing" |
| |
| verbatim { |
| DISCONNECT |
| CONNECT met5 met4 BY via4_c |
| CONNECT met4 met3 BY via3_c |
| CONNECT met4 m4_bot_plate BY cap2m_cont_dmy |
| CONNECT met3 met2 BY via2 |
| |
| |
| CONNECT met3 m3_bot_plate BY capm_cont_dmy |
| CONNECT met2 met1 BY via1 |
| CONNECT met1 li BY mcon |
| CONNECT li nsd BY licon |
| CONNECT li psd BY licon |
| CONNECT li ntap BY licon |
| CONNECT li ptap BY licon |
| CONNECT li ptubtap BY licon |
| CONNECT li poly BY licon |
| |
| CONNECT ntap nwell |
| CONNECT ptap pwell |
| CONNECT ptubtap ptub |
| CONNECT nwell dnwell |
| |
| CONNECT met5 pad |
| CONNECT met5 uprobe_pad |
| CONNECT met5 probe_pad |
| CONNECT rdl pad |
| CONNECT rdl uprobe_pad |
| CONNECT rdl probe_pad |
| } |
| |
| SETLAYER gnd_pad = "pad INTERACT pad_gnd" |
| SETLAYER pad_gnd_net_m5 = "NET AREA RATIO met5 gnd_pad > 0" |
| SETLAYER pad_gnd_net_m4 = "NET AREA RATIO met4 gnd_pad > 0" |
| SETLAYER pad_gnd_net_m3 = "NET AREA RATIO met3 gnd_pad > 0" |
| SETLAYER pad_gnd_net_m2 = "NET AREA RATIO met2 gnd_pad > 0" |
| SETLAYER pad_gnd_net_m1 = "NET AREA RATIO met1 gnd_pad > 0" |
| SETLAYER pad_gnd_net_li = "NET AREA RATIO li gnd_pad > 0" |
| SETLAYER pad_gnd_net_nsd = "NET AREA RATIO nsd gnd_pad > 0" |
| SETLAYER pad_gnd_net_psd = "NET AREA RATIO psd gnd_pad > 0" |
| SETLAYER pad_gnd_net_poly = "NET AREA RATIO poly gnd_pad > 0" |
| SETLAYER pad_gnd_net_nw = "NET AREA RATIO nwell gnd_pad > 0" |
| SETLAYER pad_gnd_net_dnw = "NET AREA RATIO dnwell gnd_pad > 0" |
| SETLAYER pad_gnd_net_pw = "NET AREA RATIO pwell gnd_pad > 0" |
| SETLAYER pad_gnd_net_ntap = "NET AREA RATIO ntap gnd_pad > 0" |
| SETLAYER pad_gnd_net_ptap = "NET AREA RATIO ptap gnd_pad > 0" |
| SETLAYER gnd_net_to_pad1 = "OR pad_gnd_net_m5 pad_gnd_net_m4 pad_gnd_net_m3 pad_gnd_net_m2 pad_gnd_net_m1" |
| SETLAYER gnd_net_to_pad2 = "OR gnd_net_to_pad1 pad_gnd_net_nsd pad_gnd_net_psd pad_gnd_net_poly" |
| SETLAYER gnd_net_to_pad = "OR gnd_net_to_pad2 pad_gnd_net_ntap pad_gnd_net_ptap pad_gnd_net_nw pad_gnd_net_pw" |
| |
| SETLAYER sig_pad = "pad INTERACT pad_io" |
| SETLAYER pad_sig_net_m5 = "NET AREA RATIO met5 sig_pad > 0" |
| SETLAYER pad_sig_net_m4 = "NET AREA RATIO met4 sig_pad > 0" |
| SETLAYER pad_sig_net_m3 = "NET AREA RATIO met3 sig_pad > 0" |
| SETLAYER pad_sig_net_m2 = "NET AREA RATIO met2 sig_pad > 0" |
| SETLAYER pad_sig_net_m1 = "NET AREA RATIO met1 sig_pad > 0" |
| SETLAYER pad_sig_net_li = "NET AREA RATIO li sig_pad > 0" |
| SETLAYER pad_sig_net_nsd = "NET AREA RATIO nsd sig_pad > 0" |
| SETLAYER pad_sig_net_psd = "NET AREA RATIO psd sig_pad > 0" |
| SETLAYER pad_sig_net_poly = "NET AREA RATIO poly sig_pad > 0" |
| SETLAYER pad_sig_net_nw = "NET AREA RATIO nwell sig_pad > 0" |
| SETLAYER pad_sig_net_dnw = "NET AREA RATIO dnwell sig_pad > 0" |
| SETLAYER pad_sig_net_pw = "NET AREA RATIO pwell sig_pad > 0" |
| SETLAYER pad_sig_net_ntap = "NET AREA RATIO ntap sig_pad > 0" |
| SETLAYER pad_sig_net_ptap = "NET AREA RATIO ptap sig_pad > 0" |
| SETLAYER sig_net_to_pad1 = "OR pad_sig_net_m5 pad_sig_net_m4 pad_sig_net_m3 pad_sig_net_m2 pad_sig_net_m1" |
| SETLAYER sig_net_to_pad2 = "OR sig_net_to_pad1 pad_sig_net_nsd pad_sig_net_psd pad_sig_net_poly" |
| SETLAYER sig_net_to_pad = "OR sig_net_to_pad2 pad_sig_net_ntap pad_sig_net_ptap pad_sig_net_nw pad_sig_net_pw" |
| |
| SETLAYER pwr_pad = "pad INTERACT pad_pwr" |
| SETLAYER pad_pwr_net_m5 = "NET AREA RATIO met5 pwr_pad > 0" |
| SETLAYER pad_pwr_net_m4 = "NET AREA RATIO met4 pwr_pad > 0" |
| SETLAYER pad_pwr_net_m3 = "NET AREA RATIO met3 pwr_pad > 0" |
| SETLAYER pad_pwr_net_m2 = "NET AREA RATIO met2 pwr_pad > 0" |
| SETLAYER pad_pwr_net_m1 = "NET AREA RATIO met1 pwr_pad > 0" |
| SETLAYER pad_pwr_net_li = "NET AREA RATIO li pwr_pad > 0" |
| SETLAYER pad_pwr_net_nsd = "NET AREA RATIO nsd pwr_pad > 0" |
| SETLAYER pad_pwr_net_psd = "NET AREA RATIO psd pwr_pad > 0" |
| SETLAYER pad_pwr_net_ntap = "NET AREA RATIO ntap pwr_pad > 0" |
| SETLAYER pad_pwr_net_ptap = "NET AREA RATIO ptap pwr_pad > 0" |
| SETLAYER pad_pwr_net_poly = "NET AREA RATIO poly pwr_pad > 0" |
| SETLAYER pad_pwr_net_nw = "NET AREA RATIO nwell pwr_pad > 0" |
| SETLAYER pad_pwr_net_pw = "NET AREA RATIO pwell pwr_pad > 0" |
| SETLAYER pwr_net_to_pad1 = "OR pad_pwr_net_m5 pad_pwr_net_m4 pad_pwr_net_m3 pad_pwr_net_m2 pad_pwr_net_m1" |
| SETLAYER pwr_net_to_pad2 = "OR pwr_net_to_pad1 pad_pwr_net_nsd pad_pwr_net_psd pad_pwr_net_poly" |
| SETLAYER pwr_net_to_pad = "OR pwr_net_to_pad2 pad_pwr_net_ntap pad_pwr_net_ptap pad_pwr_net_nw pad_pwr_net_pw" |
| |
| # these 2 rules (1 & 2) are not in the "generic section" |
| #RULECHECK latchup.1 { |
| #@ latchup.1: ptap ring around grounded nwell must connect to a ground pad |
| # OUTPUT "ptap INTERACT (((HOLES ptap) ENCLOSE pad_gnd_net_nw) NOT (HOLES pad_gnd_net_ptap))" |
| # } |
| |
| #RULECHECK latchup.2 { |
| #@ latchup.2: Grounded nwell (not exempt) must be inside ptap isolation ring |
| # OUTPUT "pad_gnd_net_nw NOT INSIDE (HOLES pad_gnd_net_ptap)" |
| # } |
| |
| SETLAYER sealHole = "HOLES SEALID" |
| SETLAYER sig_pad_diff = "OR pad_sig_net_nsd pad_sig_net_psd pad_sig_net_ntap pad_sig_net_ptap" |
| SETLAYER io_region = "SIZE sig_pad_diff BY 50 INSIDE OF sealHole STEP 5" |
| |
| SETLAYER ptap_licon = "(ptap AND licon) NOT nwell" |
| SETLAYER ntap_licon = "(ntap AND licon) AND (nwell OR dnwell)" |
| SETLAYER ptap_licon_size_6 = "SIZE ptap_licon BY 6 OUTSIDE OF nwell STEP 0.59 TRUNCATE 2.61" |
| SETLAYER ntap_licon_size_6 = "SIZE ntap_licon BY 6 INSIDE OF (nwell OR dnwell) STEP 0.59 TRUNCATE 2.61" |
| SETLAYER ptap_licon_size_15 = "SIZE ptap_licon BY 15 OUTSIDE OF nwell STEP 0.59 TRUNCATE 2.61" |
| SETLAYER ntap_licon_size_15 = "SIZE ntap_licon BY 15 INSIDE OF (nwell OR dnwell) STEP 0.59 TRUNCATE 2.61" |
| SETLAYER ndiff_in_ioregion = "nsd AND io_region" |
| SETLAYER pdiff_in_ioregion = "psd AND io_region" |
| SETLAYER pdiff_not_in_ioregion = "psd NOT io_region" |
| SETLAYER ndiff_not_in_ioregion = "nsd NOT io_region" |
| SETLAYER pwell_has_ptap_licon = "((pwell or ptub) AND sealHole) ENCLOSE ptap_licon" |
| SETLAYER pwell_has_ptap_io_ndiff = "((pwell or ptub) AND sealHole) ENCLOSE ndiff_in_ioregion" |
| SETLAYER pwell_has_ptap_no_io_ndiff = "((pwell or ptub) AND sealHole) NOT ENCLOSE ndiff_in_ioregion" |
| SETLAYER pwell_has_both_io = "pwell_has_ptap_licon AND pwell_has_ptap_io_ndiff" |
| SETLAYER pwell_has_both_not_io = "pwell_has_ptap_licon AND pwell_has_ptap_no_io_ndiff" |
| |
| SETLAYER nwell_has_ntap_licon = "((nwell or dnwell) AND sealHole) ENCLOSE ntap_licon" |
| SETLAYER nwell_has_ntap_io_ndiff = "((nwell or dnwell) AND sealHole) ENCLOSE ndiff_in_ioregion" |
| SETLAYER nwell_has_ntap_no_io_ndiff = "((nwell or dnwell) AND sealHole) NOT ENCLOSE ndiff_in_ioregion" |
| SETLAYER nwell_has_both_io = "nwell_has_ntap_licon AND nwell_has_ntap_io_ndiff" |
| SETLAYER nwell_has_both_not_io = "nwell_has_ntap_licon AND nwell_has_ntap_no_io_ndiff" |
| |
| RULECHECK latchup.generic.2a { |
| @ latchup.generic.2a: Max spacing from center of ptap licon to any part of ndiff within the same ptub or pwell (< 50u away from diff connected to a signal pad) > 6 |
| OUTPUT "(((ndiff_in_ioregion AND nsd) NOT ESDID) NOT ptap_licon_size_6) INSIDE pwell_has_both_io" |
| } |
| |
| RULECHECK latchup.generic.2b { |
| @ latchup.generic.2b: Max spacing from center of ptap licon to any part of ndiff within the same ptub or pwell (>= 50u away from diff connected to a signal pad) > 15 |
| OUTPUT "(((ndiff_not_in_ioregion AND nsd) NOT ESDID) NOT ptap_licon_size_15) INSIDE pwell_has_both_not_io" |
| } |
| |
| SETLAYER pos_pwr_pdiff = "(ptap OR psd) AND pwr_net_to_pad" |
| SETLAYER dnw_has_pos_pwr_pdiff = "dnwell ENCLOSE pos_pwr_pdiff" |
| SETLAYER nw_has_pos_pwr_pdiff = "nwell INTERACT dnw_has_pos_pwr_pdiff" |
| SETLAYER dnw_or_nw_pwr_pdiff = "OR dnw_has_pos_pwr_pdiff nw_has_pos_pwr_pdiff" |
| SETLAYER dnw_no_pos_pwr_pdiff = "dnwell NOT ENCLOSE pos_pwr_pdiff" |
| SETLAYER nw_no_pos_pwr_pdiff = "(nwell INTERACT dnwell) NOT INTERACT dnw_has_pos_pwr_pdiff" |
| SETLAYER dnw_or_nw_no_pwr_pdiff = "OR dnw_no_pos_pwr_pdiff nw_no_pos_pwr_pdiff" |
| |
| RULECHECK latchup.generic.2.1a_b { |
| @ latchup.generic.2.1a_b: Max spacing from center of ptap licon to N+ diff within the same pwell where the deep nwell or nwell forming the pwell, does NOT contain a pdiff connected to a power pad > 6 |
| OUTPUT "((((ndiff_in_ioregion AND nsd) NOT ESDID) NOT COREID) NOT ptap_licon_size_6) INSIDE dnw_or_nw_no_pwr_pdiff" |
| } |
| |
| RULECHECK latchup.generic.3a { |
| @ latchup.generic.3a: Max spacing from center of ntap licon to pdiff within the same nwell or dnwell (< 50u away from diff connected to a signal pad ) > 6 |
| OUTPUT "((((pdiff_in_ioregion AND psd) NOT ESDID) NOT COREID) NOT ptap) NOT ntap_licon_size_6" |
| } |
| |
| RULECHECK latchup.generic.3b { |
| @ latchup.generic.3a: Max spacing from center of ntap licon pdiff within the same nwell or dnwell (>= 50u away from diff connected signal pad) > 15 |
| OUTPUT "((((pdiff_not_in_ioregion AND psd) NOT ESDID) NOT COREID) NOT ptap) NOT ntap_licon_size_15" |
| } |
| |
| RULECHECK latchup.generic.4 { |
| @ latchup.generic.4: Min distance from diffusion connected to a signal pad to areaid:core < 50.0 |
| # cannot determine the closest cell in memory core but can do a check to COREID |
| OUTPUT "EXT (COREID AND sealHole) (pad_sig_net_nsd AND sealHole) < 50.0 ABUT<90 REGION" |
| OUTPUT "EXT (COREID AND sealHole) (pad_sig_net_psd AND sealHole) < 50.0 ABUT<90 REGION" |
| OUTPUT "EXT (COREID AND sealHole) (pad_sig_net_ntap AND sealHole) < 50.0 ABUT<90 REGION" |
| OUTPUT "(EXT COREID pad_sig_net_ptap < 50.0 ABUT<90 REGION) INSIDE sealHole" |
| } |
| |
| SETLAYER upad_probe_net_m5 = "NET AREA RATIO met5 uprobe_pad > 0" |
| SETLAYER upad_probe_net_m4 = "NET AREA RATIO met4 uprobe_pad > 0" |
| SETLAYER upad_probe_net_m3 = "NET AREA RATIO met3 uprobe_pad > 0" |
| SETLAYER upad_probe_net_m2 = "NET AREA RATIO met2 uprobe_pad > 0" |
| SETLAYER upad_probe_net_m1 = "NET AREA RATIO met1 uprobe_pad > 0" |
| SETLAYER upad_probe_net_li = "NET AREA RATIO li uprobe_pad > 0" |
| SETLAYER upad_probe_net_nsd = "NET AREA RATIO nsd uprobe_pad > 0" |
| SETLAYER upad_probe_net_psd = "NET AREA RATIO psd uprobe_pad > 0" |
| |
| SETLAYER ppad_probe_net_m5 = "NET AREA RATIO met5 probe_pad > 0" |
| SETLAYER ppad_probe_net_m4 = "NET AREA RATIO met4 probe_pad > 0" |
| SETLAYER ppad_probe_net_m3 = "NET AREA RATIO met3 probe_pad > 0" |
| SETLAYER ppad_probe_net_m2 = "NET AREA RATIO met2 probe_pad > 0" |
| SETLAYER ppad_probe_net_m1 = "NET AREA RATIO met1 probe_pad > 0" |
| SETLAYER ppad_probe_net_li = "NET AREA RATIO li probe_pad > 0" |
| SETLAYER ppad_probe_net_nsd = "NET AREA RATIO nsd probe_pad > 0" |
| SETLAYER ppad_probe_net_psd = "NET AREA RATIO psd probe_pad > 0" |
| |
| SETLAYER pad_probe_net_nsd = "OR upad_probe_net_nsd ppad_probe_net_nsd" |
| SETLAYER pad_probe_net_psd = "OR upad_probe_net_psd ppad_probe_net_psd" |
| |
| RULECHECK latchup.generic.5a { |
| @ latchup.generic.5a: Min. space N+ diff to unrelated N+ diff inside a common ptub or common pwell (metallically connected to separate pads or external nets - ground, power or signal) < 3 |
| SETLAYER exempt = "OR ESDID pad_probe_net_nsd" |
| OUTPUT "(EXT (pad_sig_net_nsd NOT exempt) (pad_pwr_net_nsd NOT exempt) < 3.0 ABUT<90 REGION) INSIDE pwell" |
| OUTPUT "(EXT (pad_sig_net_nsd NOT exempt) (pad_gnd_net_nsd NOT exempt) < 3.0 ABUT<90 REGION) INSIDE pwell" |
| OUTPUT "(EXT (pad_pwr_net_nsd NOT exempt) (pad_gnd_net_nsd NOT exempt) < 3.0 ABUT<90 REGION) INSIDE pwell" |
| OUTPUT "(EXT (pad_sig_net_nsd NOT exempt) (pad_pwr_net_nsd NOT exempt) < 3.0 ABUT<90 REGION) INSIDE ptub" |
| OUTPUT "(EXT (pad_sig_net_nsd NOT exempt) (pad_gnd_net_nsd NOT exempt) < 3.0 ABUT<90 REGION) INSIDE ptub" |
| OUTPUT "(EXT (pad_pwr_net_nsd NOT exempt) (pad_gnd_net_nsd NOT exempt) < 3.0 ABUT<90 REGION) INSIDE ptub" |
| OUTPUT "(EXT (pad_sig_net_nsd NOT exempt) (pad_pwr_net_nsd NOT exempt) < 3.0 ABUT<90 REGION) INSIDE localSub" |
| OUTPUT "(EXT (pad_sig_net_nsd NOT exempt) (pad_gnd_net_nsd NOT exempt) < 3.0 ABUT<90 REGION) INSIDE localSub" |
| OUTPUT "(EXT (pad_pwr_net_nsd NOT exempt) (pad_gnd_net_nsd NOT exempt) < 3.0 ABUT<90 REGION) INSIDE localSub" |
| } |
| |
| RULECHECK latchup.generic.5b { |
| @ latchup.generic.5b: Min. space P+ diff to unrelated P+ diff inside a common nwell or dnwell (metallically connected to separate pads or external nets - ground, power or signal) < 3 |
| SETLAYER exempt = "OR ESDID pad_probe_net_psd" |
| OUTPUT "(EXT (pad_sig_net_psd NOT exempt) (pad_pwr_net_psd NOT exempt) < 3.0 ABUT<90 REGION NOT CONNECTED) INSIDE (OR nwell (dnwell NOT INTERACT ptub))" |
| OUTPUT "(EXT (pad_sig_net_psd NOT exempt) (pad_gnd_net_psd NOT exempt) < 3.0 ABUT<90 REGION NOT CONNECTED) INSIDE (OR nwell (dnwell NOT INTERACT ptub))" |
| OUTPUT "(EXT (pad_pwr_net_psd NOT exempt) (pad_gnd_net_psd NOT exempt) < 3.0 ABUT<90 REGION NOT CONNECTED) INSIDE (OR nwell (dnwell NOT INTERACT ptub))" |
| } |
| |
| ### Rules 6,7,8 and 9 marked "DELETED" |
| |
| ### Section 2: SONOS-Specific Latchup Rules marked: |
| ### Section Deleted - moved to ESD Best Practices Spec |
| |
| ### Section 3: Super High Voltage Latch-up Rules |
| ### marked Section deleted |
| |
| ### Section 4: SIGNAL PAD Latchup Rules |
| |
| # All signal pad connected n+ diffusion or n+ tap in Nwell must be |
| # separated from internal circuitry and any p+ diffusion by a pair |
| # of guard rings: |
| SETLAYER ntap_grd_ring = "HOLES ntap" |
| SETLAYER ptap_grd_ring = "HOLES ptap" |
| RULECHECK latchup.signal.2 { |
| @ latchup.signal.2: Signal connected nwell must be in a pair of guard rings |
| SETLAYER pass_1 = "pad_sig_net_nw INSIDE ntap_grd_ring" |
| SETLAYER pass_2 = "pass_1 INSIDE ptap_grd_ring" |
| OUTPUT "pad_sig_net_nw NOT pass_2" |
| } |
| |
| RULECHECK latchup.signal.2.1a { |
| @ latchup.signal.2.1a: Signal pad connected deep nwell is not allowed |
| OUTPUT "COPY pad_sig_net_dnw" |
| } |
| |
| # must short all resistors not marked 250Ohm or 1Kohm for check 2.1b in order to |
| # disciminate between those which are OK and those which are not: |
| SETLAYER diff_res_gt_250ohm = "diffres WITH TEXT \"250Ohm\" textdraw" |
| SETLAYER diff_res_gt_1kohm = "diffres WITH TEXT \"1kOhm\" textdraw" |
| SETLAYER diff_res_lg_res = "OR diff_res_gt_250ohm diff_res_gt_1kohm" |
| |
| SETLAYER poly_res_gt_250ohm = "polyres WITH TEXT \"250Ohm\" textdraw" |
| SETLAYER poly_res_gt_1kohm = "polyres WITH TEXT \"1kOhm\" textdraw" |
| SETLAYER poly_res_lg_res = "OR poly_res_gt_250ohm poly_res_gt_1kohm" |
| |
| SETLAYER li_res_gt_250ohm = "lires WITH TEXT \"250Ohm\" textdraw" |
| SETLAYER li_res_gt_1kohm = "lires WITH TEXT \"1kOhm\" textdraw" |
| SETLAYER li_res_lg_res = "OR li_res_gt_250ohm li_res_gt_1kohm" |
| |
| SETLAYER m1_res_gt_250ohm = "m1res WITH TEXT \"250Ohm\" textdraw" |
| SETLAYER m1_res_gt_1kohm = "m1res WITH TEXT \"1kOhm\" textdraw" |
| SETLAYER m1_res_lg_res = "OR m1_res_gt_250ohm m1_res_gt_1kohm" |
| |
| SETLAYER m2_res_gt_250ohm = "m2res WITH TEXT \"250Ohm\" textdraw" |
| SETLAYER m2_res_gt_1kohm = "m2res WITH TEXT \"1kOhm\" textdraw" |
| SETLAYER m2_res_lg_res = "OR m2_res_gt_250ohm m2_res_gt_1kohm" |
| |
| SETLAYER m3_res_gt_250ohm = "m3res WITH TEXT \"250Ohm\" textdraw" |
| SETLAYER m3_res_gt_1kohm = "m3res WITH TEXT \"1kOhm\" textdraw" |
| SETLAYER m3_res_lg_res = "OR m3_res_gt_250ohm m3_res_gt_1kohm" |
| |
| SETLAYER m4_res_gt_250ohm = "m4res WITH TEXT \"250Ohm\" textdraw" |
| SETLAYER m4_res_gt_1kohm = "m4res WITH TEXT \"1kOhm\" textdraw" |
| SETLAYER m4_res_lg_res = "OR m4_res_gt_250ohm m4_res_gt_1kohm" |
| |
| SETLAYER m5_res_gt_250ohm = "m5res WITH TEXT \"250Ohm\" textdraw" |
| SETLAYER m5_res_gt_1kohm = "m5res WITH TEXT \"1kOhm\" textdraw" |
| SETLAYER m5_res_lg_res = "OR m5_res_gt_250ohm m5_res_gt_1kohm" |
| |
| SETLAYER pw_res_gt_250ohm = "pwres WITH TEXT \"250Ohm\" textdraw" |
| SETLAYER pw_res_gt_1kohm = "pwres WITH TEXT \"1kOhm\" textdraw" |
| SETLAYER pw_res_lg_res = "OR pw_res_gt_250ohm pw_res_gt_1kohm" |
| |
| SETLAYER pw_lu = "pwell NOT pw_res_lg_res" |
| SETLAYER diff_lu = "diffi NOT diff_res_lg_res" |
| SETLAYER poly_lu = "polyi NOT poly_res_lg_res" |
| SETLAYER nsd_lu = "nsd NOT diff_res_lg_res" |
| SETLAYER psd_lu = "psd NOT diff_res_lg_res" |
| SETLAYER li_lu = "li_i NOT li_res_lg_res" |
| SETLAYER m1_lu = "met1i NOT m1_res_lg_res" |
| SETLAYER m2_lu = "met2i NOT m2_res_lg_res" |
| SETLAYER m3_lu = "met3i NOT m3_res_lg_res" |
| SETLAYER m4_lu = "met4i NOT m4_res_lg_res" |
| SETLAYER m5_lu = "met5i NOT m5_res_lg_res" |
| |
| verbatim { |
| DISCONNECT |
| CONNECT m5_lu m4_lu BY via4_c |
| CONNECT m4_lu m3_lu BY via3_c |
| CONNECT m3_lu m2_lu BY via2 |
| CONNECT m2_lu m1_lu BY via1 |
| CONNECT m1_lu li_lu BY mcon |
| CONNECT li_lu nsd_lu BY licon |
| CONNECT li_lu psd_lu BY licon |
| CONNECT li_lu ntap BY licon |
| CONNECT li_lu ptap BY licon |
| CONNECT li_lu ptubtap BY licon |
| CONNECT li_lu poly BY licon |
| |
| CONNECT ntap nwell |
| CONNECT ptap pw_lu |
| CONNECT ptubtap ptub |
| CONNECT nwell dnwell |
| |
| CONNECT m5_lu pad |
| CONNECT m5_lu uprobe_pad |
| CONNECT m5_lu probe_pad |
| CONNECT rdl pad |
| CONNECT rdl uprobe_pad |
| CONNECT rdl probe_pad |
| } |
| |
| SETLAYER gnd_pad2 = "pad INTERACT pad_gnd" |
| SETLAYER pad_gnd2_net_dnw = "NET AREA RATIO dnwell gnd_pad2 > 0" |
| SETLAYER pad_gnd2_net_nsd = "NET AREA RATIO nsd_lu gnd_pad2 > 0" |
| SETLAYER pad_gnd2_net_ntap = "NET AREA RATIO ntap gnd_pad2 > 0" |
| SETLAYER pad_gnd2_net_nw = "NET AREA RATIO nwell gnd_pad2 > 0" |
| |
| |
| RULECHECK latchup.signal.2.1b { |
| @ latchup.signal.2.1b: Deep nwell tied to ground through a resistance of < 250 ohm is not allowed |
| SETLAYER exempt_lu_sig_2p1b_a = "NET AREA RATIO nsd_lu gnd_pad2 > 0" |
| SETLAYER exempt_lu_sig_2p1b_b = "NET AREA RATIO dnwell gnd_pad2 > 0" |
| SETLAYER exempt_lu_sig_2p1b = "exempt_lu_sig_2p1b_b ENCLOSE exempt_lu_sig_2p1b_a" |
| OUTPUT "COPY (pad_gnd2_net_dnw NOT exempt_lu_sig_2p1b)" |
| } |
| |
| # restore normal connectivity: |
| |
| verbatim { |
| DISCONNECT |
| CONNECT met5 met4 BY via4_c |
| CONNECT met4 met3 BY via3_c |
| CONNECT met4 m4_bot_plate BY cap2m_cont_dmy |
| CONNECT met3 met2 BY via2 |
| |
| |
| CONNECT met3 m3_bot_plate BY capm_cont_dmy |
| CONNECT met2 met1 BY via1 |
| CONNECT met1 li BY mcon |
| CONNECT li nsd BY licon |
| CONNECT li psd BY licon |
| CONNECT li ntap BY licon |
| CONNECT li ptap BY licon |
| CONNECT li ptubtap BY licon |
| CONNECT li poly BY licon |
| |
| CONNECT ntap nwell |
| CONNECT ptap pwell |
| CONNECT ptap localSub |
| CONNECT ptubtap ptub |
| CONNECT nwell dnwell |
| |
| CONNECT met5 pad |
| CONNECT met5 uprobe_pad |
| CONNECT met5 probe_pad |
| CONNECT rdl pad |
| CONNECT rdl uprobe_pad |
| CONNECT rdl probe_pad |
| } |
| |
| RULECHECK latchup.signal.3 { |
| @ latchup.signal.3: All P+ diff or tap connected to signal pad must be in a pair of guard rings |
| SETLAYER pass_1 = "pad_sig_net_psd INSIDE ptap_grd_ring" |
| SETLAYER pass_2 = "pass_1 INSIDE ntap_grd_ring" |
| OUTPUT "pad_sig_net_psd NOT pass_2" |
| SETLAYER pass_1a = "pad_sig_net_ptap INSIDE ptap_grd_ring" |
| SETLAYER pass_2a = "pass_1a INSIDE ntap_grd_ring" |
| OUTPUT "pad_sig_net_ptap NOT pass_2a" |
| } |
| |
| SETLAYER pwr2_pad = "pad INTERACT pad_pwr" |
| SETLAYER pad_pwr2_net_m5 = "NET AREA RATIO met5 pwr2_pad > 0" |
| SETLAYER pad_pwr2_net_m4 = "NET AREA RATIO met4 pwr2_pad > 0" |
| SETLAYER pad_pwr2_net_m3 = "NET AREA RATIO met3 pwr2_pad > 0" |
| SETLAYER pad_pwr2_net_m2 = "NET AREA RATIO met2 pwr2_pad > 0" |
| SETLAYER pad_pwr2_net_m1 = "NET AREA RATIO met1 pwr2_pad > 0" |
| SETLAYER pad_pwr2_net_li = "NET AREA RATIO li pwr2_pad > 0" |
| SETLAYER pad_pwr2_net_nsd = "NET AREA RATIO nsd pwr2_pad > 0" |
| SETLAYER pad_pwr2_net_psd = "NET AREA RATIO psd pwr2_pad > 0" |
| SETLAYER pad_pwr2_net_poly = "NET AREA RATIO poly pwr2_pad > 0" |
| SETLAYER pad_pwr2_net_nw = "NET AREA RATIO nwell pwr2_pad > 0" |
| SETLAYER pad_pwr2_net_pw = "NET AREA RATIO pwell pwr2_pad > 0" |
| SETLAYER pad_pwr2_net_ntap = "NET AREA RATIO ntap pwr2_pad > 0" |
| SETLAYER pad_pwr2_net_ptap = "NET AREA RATIO ptap pwr2_pad > 0" |
| SETLAYER pwr2_net_to_pad1 = "OR pad_pwr2_net_m5 pad_pwr2_net_m4 pad_pwr2_net_m3 pad_pwr2_net_m2 pad_pwr2_net_m1" |
| SETLAYER pwr2_net_to_pad2 = "OR pwr2_net_to_pad1 pad_pwr2_net_nsd pad_pwr2_net_psd pad_pwr2_net_poly" |
| SETLAYER pwr2_net_to_pad = "OR pwr2_net_to_pad2 pad_pwr2_net_ntap pad_pwr2_net_ptap pad_pwr2_net_nw pad_pwr2_net_pw" |
| |
| RULECHECK latchup.signal.3.1a { |
| @ latchup.signal.3.1a: signal connected ptap must have nwell/N+ guard ring connected to positive power pad |
| OUTPUT "(ntap INTERACT (ntap_grd_ring INTERACT pad_sig_net_ptap)) NOT pad_pwr2_net_ntap" |
| } |
| |
| SETLAYER gnd3_pad = "pad INTERACT pad_gnd" |
| SETLAYER pad_gnd3_net_m5 = "NET AREA RATIO met5 gnd3_pad > 0" |
| SETLAYER pad_gnd3_net_m4 = "NET AREA RATIO met4 gnd3_pad > 0" |
| SETLAYER pad_gnd3_net_m3 = "NET AREA RATIO met3 gnd3_pad > 0" |
| SETLAYER pad_gnd3_net_m2 = "NET AREA RATIO met2 gnd3_pad > 0" |
| SETLAYER pad_gnd3_net_m1 = "NET AREA RATIO met1 gnd3_pad > 0" |
| SETLAYER pad_gnd3_net_li = "NET AREA RATIO li gnd3_pad > 0" |
| SETLAYER pad_gnd3_net_nsd = "NET AREA RATIO nsd gnd3_pad > 0" |
| SETLAYER pad_gnd3_net_psd = "NET AREA RATIO psd gnd3_pad > 0" |
| SETLAYER pad_gnd3_net_poly = "NET AREA RATIO poly gnd3_pad > 0" |
| SETLAYER pad_gnd3_net_nw = "NET AREA RATIO nwell gnd3_pad > 0" |
| # omit pwell to avoid confusing vias interacting with pw gnd signals |
| # in latchup.signal.8 rule |
| #SETLAYER pad_gnd3_net_pw = "NET AREA RATIO pwell gnd3_pad > 0" |
| SETLAYER pad_gnd3_net_ntap = "NET AREA RATIO ntap gnd3_pad > 0" |
| SETLAYER pad_gnd3_net_ptap = "NET AREA RATIO ptap gnd3_pad > 0" |
| SETLAYER gnd3_net_to_pad1 = "OR pad_gnd3_net_m5 pad_gnd3_net_m4 pad_gnd3_net_m3 pad_gnd3_net_m2 pad_gnd3_net_m1" |
| SETLAYER gnd3_net_to_pad2 = "OR gnd3_net_to_pad1 pad_gnd3_net_nsd pad_gnd3_net_psd pad_gnd3_net_poly" |
| #SETLAYER gnd3_net_to_pad = "OR gnd3_net_to_pad2 pad_gnd3_net_ntap pad_gnd3_net_ptap pad_gnd3_net_nw pad_gnd3_net_pw" |
| SETLAYER gnd3_net_to_pad = "OR gnd3_net_to_pad2 pad_gnd3_net_ntap pad_gnd3_net_ptap pad_gnd3_net_nw" |
| |
| SETLAYER pwr3_pad = "pad INTERACT pad_pwr" |
| SETLAYER pad_pwr3_net_m5 = "NET AREA RATIO met5 pwr3_pad > 0" |
| SETLAYER pad_pwr3_net_m4 = "NET AREA RATIO met4 pwr3_pad > 0" |
| SETLAYER pad_pwr3_net_m3 = "NET AREA RATIO met3 pwr3_pad > 0" |
| SETLAYER pad_pwr3_net_m2 = "NET AREA RATIO met2 pwr3_pad > 0" |
| SETLAYER pad_pwr3_net_m1 = "NET AREA RATIO met1 pwr3_pad > 0" |
| SETLAYER pad_pwr3_net_li = "NET AREA RATIO li pwr3_pad > 0" |
| SETLAYER pad_pwr3_net_nsd = "NET AREA RATIO nsd pwr3_pad > 0" |
| SETLAYER pad_pwr3_net_psd = "NET AREA RATIO psd pwr3_pad > 0" |
| SETLAYER pad_pwr3_net_poly = "NET AREA RATIO poly pwr3_pad > 0" |
| SETLAYER pad_pwr3_net_nw = "NET AREA RATIO nwell pwr3_pad > 0" |
| SETLAYER pad_pwr3_net_pw = "NET AREA RATIO pwell pwr3_pad > 0" |
| SETLAYER pad_pwr3_net_ls = "NET AREA RATIO localSub pwr3_pad > 0" |
| SETLAYER pad_pwr3_net_pt = "NET AREA RATIO ptub pwr3_pad > 0" |
| SETLAYER pad_pwr3_net_ntap = "NET AREA RATIO ntap pwr3_pad > 0" |
| SETLAYER pad_pwr3_net_ptap = "NET AREA RATIO ptap pwr3_pad > 0" |
| SETLAYER pwr3_net_to_pad1 = "OR pad_pwr3_net_m5 pad_pwr3_net_m4 pad_pwr3_net_m3 pad_pwr3_net_m2 pad_pwr3_net_m1" |
| SETLAYER pwr3_net_to_pad2 = "OR pwr3_net_to_pad1 pad_pwr3_net_nsd pad_pwr3_net_psd pad_pwr3_net_poly" |
| SETLAYER pwr3_net_to_pad = "OR pwr3_net_to_pad2 pad_pwr3_net_ntap pad_pwr3_net_ptap pad_pwr3_net_nw pad_pwr3_net_pw" |
| |
| SETLAYER sig2_pad = "pad INTERACT pad_io" |
| SETLAYER pad_sig2_net_m5 = "NET AREA RATIO met5 sig2_pad > 0" |
| SETLAYER pad_sig2_net_m4 = "NET AREA RATIO met4 sig2_pad > 0" |
| SETLAYER pad_sig2_net_m3 = "NET AREA RATIO met3 sig2_pad > 0" |
| SETLAYER pad_sig2_net_m2 = "NET AREA RATIO met2 sig2_pad > 0" |
| SETLAYER pad_sig2_net_m1 = "NET AREA RATIO met1 sig2_pad > 0" |
| SETLAYER pad_sig2_net_li = "NET AREA RATIO li sig2_pad > 0" |
| SETLAYER pad_sig2_net_nsd = "NET AREA RATIO nsd sig2_pad > 0" |
| SETLAYER pad_sig2_net_ntap = "NET AREA RATIO ntap sig2_pad > 0" |
| SETLAYER pad_sig2_net_psd = "NET AREA RATIO psd sig2_pad > 0" |
| SETLAYER pad_sig2_net_ptap = "NET AREA RATIO ptap sig2_pad > 0" |
| SETLAYER pad_sig2_net_poly = "NET AREA RATIO poly sig2_pad > 0" |
| SETLAYER pad_sig2_net_nw = "NET AREA RATIO nwell sig2_pad > 0" |
| SETLAYER pad_sig2_net_dnw = "NET AREA RATIO dnwell sig2_pad > 0" |
| SETLAYER pad_sig2_net_pw = "NET AREA RATIO pwell sig2_pad > 0" |
| SETLAYER pad_sig2_net_ls = "NET AREA RATIO localSub sig2_pad > 0" |
| SETLAYER pad_sig2_net_pt = "NET AREA RATIO ptub sig2_pad > 0" |
| SETLAYER pad_sig2_diff_all = "OR pad_sig2_net_nsd pad_sig2_net_ntap pad_sig2_net_psd pad_sig2_net_ptap" |
| |
| RULECHECK latchup.signal.3.1b { |
| @ latchup.signal.3.1b: signal connected ptap or P+ src/drn must have P+ tap guard ring connected to a ground pad |
| OUTPUT "((ptap INTERACT (ptap_grd_ring INTERACT pad_sig_net_ptap)) NOT pad_gnd3_net_ptap) NOT pad_sig_net_ptap" |
| SETLAYER exempt1 = "(pad_sig_net_psd INTERACT > 0 pad_sig2_net_nw BY NET) OR (pad_sig_net_psd INSIDE (nwell NOT pad_pwr3_net_nw))" |
| OUTPUT "(pad_sig_net_psd NOT ptap_grd_ring) NOT exempt1" |
| } |
| |
| RULECHECK latchup.signal.12a { |
| @ latchup.signal.12a: Minimum spacing between diff metallically connected to signal pad and grounded ndiff < 27.0 |
| SETLAYER exempt1 = "pad_sig_net_psd INTERACT > 0 pad_sig2_net_nw BY NET" |
| OUTPUT "EXT (pad_sig2_net_psd NOT exempt1) pad_gnd3_net_nsd < 27.0 ABUT<90 REGION" |
| } |
| |
| RULECHECK latchup.signal.12b { |
| @ latchup.signal.12b: Minimum spacing between pwell metallically connected to signal pad and grounded ndiff < 40.0 |
| OUTPUT "EXT pad_sig2_net_pw pad_gnd3_net_nsd < 40.0 ABUT<90 REGION" |
| OUTPUT "EXT pad_sig2_net_ls pad_gnd3_net_nsd < 40.0 ABUT<90 REGION" |
| OUTPUT "EXT pad_sig2_net_pt pad_gnd3_net_nsd < 40.0 ABUT<90 REGION" |
| } |
| |
| RULECHECK latchup.signal.12c { |
| @ latchup.signal.12c: Minimum spacing between pdiff metallically connected to signal pad and grounded nwell < 40.0 |
| SETLAYER exempt1 = "pad_sig_net_psd INTERACT > 0 pad_sig2_net_nw BY NET" |
| OUTPUT "EXT (pad_sig2_net_psd NOT exempt1) pad_gnd3_net_nw < 40.0 ABUT<90 REGION" |
| } |
| |
| RULECHECK latchup.signal.12d { |
| @ latchup.signal.12d: Minimum spacing between pwell metallically connected to signal pad and grounded nwell < 40.0 |
| OUTPUT "EXT pad_sig2_net_pw pad_gnd3_net_nw < 40.0 ABUT<90 REGION" |
| OUTPUT "EXT pad_sig2_net_ls pad_gnd3_net_nw < 40.0 ABUT<90 REGION" |
| OUTPUT "EXT pad_sig2_net_pt pad_gnd3_net_nw < 40.0 ABUT<90 REGION" |
| } |
| |
| RULECHECK latchup.signal.12e { |
| @ latchup.signal.12e: Minimum spacing between ndiff metallically connected to signal pad and positive power supply connected pdiff < 27.0 |
| SETLAYER exempt1 = "pad_sig_net_nsd INTERACT > 0 pad_sig2_net_pw BY NET" |
| SETLAYER exempt2 = "pad_sig_net_nsd INSIDE ptub" |
| SETLAYER exempt = "OR exempt1 exempt2" |
| OUTPUT "EXT (pad_sig2_net_nsd NOT exempt) pad_pwr3_net_psd < 27.0 ABUT<90 REGION" |
| } |
| |
| RULECHECK latchup.signal.12f { |
| @ latchup.signal.12f: Minimum spacing between nwell metallically connected to signal pad and positive power supply connected pdiff < 40.0 |
| OUTPUT "EXT pad_sig2_net_nw pad_pwr3_net_psd < 40.0 ABUT<90 REGION" |
| } |
| |
| RULECHECK latchup.signal.12g { |
| @ latchup.signal.12g: Minimum spacing between non-isolated ndiff metallically connected to signal pad and positive power supply connected pwell < 40.0 |
| SETLAYER exempt1 = "pad_sig_net_nsd INTERACT > 0 pad_sig2_net_pw BY NET" |
| SETLAYER nsd_in_ptub = "nsd AND ptub" |
| OUTPUT "EXT ((pad_sig2_net_nsd NOT nsd_in_ptub) NOT exempt1) pad_pwr3_net_pw < 40.0 ABUT<90 REGION" |
| OUTPUT "EXT ((pad_sig2_net_nsd NOT nsd_in_ptub) NOT exempt1) pad_pwr3_net_ls < 40.0 ABUT<90 REGION" |
| OUTPUT "EXT ((pad_sig2_net_nsd NOT nsd_in_ptub) NOT exempt1) pad_pwr3_net_pt < 40.0 ABUT<90 REGION" |
| } |
| |
| RULECHECK latchup.signal.12h { |
| @ latchup.signal.12h: Minimum spacing between nwell metallically connected to signal pad and positive power supply connected pwell < 40.0 |
| OUTPUT "EXT pad_sig2_net_nw pad_pwr3_net_pw < 40.0 ABUT<90 REGION" |
| OUTPUT "EXT pad_sig2_net_nw pad_pwr3_net_ls < 40.0 ABUT<90 REGION" |
| OUTPUT "EXT pad_sig2_net_nw pad_pwr3_net_pt < 40.0 ABUT<90 REGION" |
| } |
| |
| RULECHECK latchup.signal.12i { |
| @ latchup.signal.12i: Minimum spacing between pdiff metallically connected to signal pad and ndiff metallically connected to a different signal pad < 27.0 |
| OUTPUT "EXT pad_sig2_net_psd pad_sig2_net_nsd < 27.0 ABUT<90 REGION NOT CONNECTED" |
| } |
| |
| RULECHECK latchup.signal.12j { |
| @ latchup.signal.12j: Minimum spacing between pdiff metallically connected to signal pad and nwell metallically connected to a different signal pad < 40.0 |
| SETLAYER exempt1 = "pad_sig_net_psd INTERACT > 0 pad_sig2_net_nw BY NET" |
| OUTPUT "EXT (pad_sig2_net_psd NOT exempt1) pad_sig2_net_nw < 40.0 ABUT<90 REGION NOT CONNECTED" |
| } |
| |
| RULECHECK latchup.signal.12k { |
| @ latchup.signal.12k: Minimum spacing between pwell metallically connected to signal pad and ndiff metallically connected to a different signal pad < 40.0 |
| OUTPUT "EXT pad_sig2_net_pw pad_sig2_net_nsd < 40.0 ABUT<90 REGION NOT CONNECTED" |
| OUTPUT "EXT pad_sig2_net_ls pad_sig2_net_nsd < 40.0 ABUT<90 REGION NOT CONNECTED" |
| OUTPUT "EXT pad_sig2_net_pt pad_sig2_net_nsd < 40.0 ABUT<90 REGION NOT CONNECTED" |
| } |
| |
| RULECHECK latchup.signal.12l { |
| @ latchup.signal.12l: Minimum spacing between pwell metallically connected to signal pad and nwell metallically connected to a different signal pad < 40.0 |
| OUTPUT "EXT pad_sig2_net_pw pad_sig2_net_nw < 40.0 ABUT<90 REGION NOT CONNECTED" |
| OUTPUT "EXT pad_sig2_net_ls pad_sig2_net_nw < 40.0 ABUT<90 REGION NOT CONNECTED" |
| OUTPUT "EXT pad_sig2_net_pt pad_sig2_net_nw < 40.0 ABUT<90 REGION NOT CONNECTED" |
| } |
| |
| # at RISK Non_Vcc_nwell is any nwell containing p+ diffusion connected to a |
| # positive external power supply ≥ 3.3V, where the nwell is not metallically |
| # connected to the same positive power supply: |
| |
| SETLAYER hv_psd = "pad_pwr3_net_psd AND (OR v5 v12 v20)" |
| SETLAYER at_risk_non_vcc_nw = "(nwell AND (NET AREA RATIO == 0 nwell pad_pwr3_net_psd)) ENCLOSE hv_psd" |
| SETLAYER at_risk_non_vcc_nw_and_psd = "at_risk_non_vcc_nw AND hv_psd" |
| |
| SETLAYER exempt3 = "pad_sig2_net_pw ENCLOSE pad_sig2_net_nsd" |
| SETLAYER exempt4 = "pad_pwr3_net_nw ENCLOSE pad_pwr3_net_psd" |
| |
| RULECHECK latchup.signal.12m { |
| @ latchup.signal.12m: Minimum spacing between ndiff metallically connected to signal pad and pdiff in an At RISK Non_Vcc_nwell < 33.0 |
| OUTPUT "EXT (pad_sig2_net_nsd NOT exempt3) (at_risk_non_vcc_nw_and_psd NOT exempt4) < 33.0 ABUT<90 REGION" |
| } |
| |
| RULECHECK latchup.signal.12n { |
| @ latchup.signal.12n: Minimum spacing between ndiff metallically connected to signal pad and At RISK Non_Vcc_nwell < 16.75 |
| OUTPUT "EXT (pad_sig2_net_nsd NOT exempt3) (at_risk_non_vcc_nw NOT exempt4) < 16.75 ABUT<90 REGION" |
| } |
| |
| RULECHECK latchup.signal.12o { |
| @ latchup.signal.12o: Minimum spacing between pdiff metallically connected to signal pad and nwell connected to 1.8V (LV) or lower < 27.0 |
| OUTPUT "EXT pad_sig2_net_psd (nwell NOT (OR v5 v12 v20)) < 27.0 ABUT<90 REGION MEASURE ALL" |
| } |
| |
| RULECHECK latchup.signal.12p { |
| @ latchup.signal.12p: Minimum spacing between pwell metallically connected to signal pad and nwell connected to 1.8V (LV) or lower < 40.0 |
| OUTPUT "EXT pad_sig2_net_pw (nwell NOT (OR v5 v12 v20)) < 40.0 ABUT<90 REGION MEASURE ALL" |
| OUTPUT "EXT pad_sig2_net_ls (nwell NOT (OR v5 v12 v20)) < 40.0 ABUT<90 REGION MEASURE ALL" |
| OUTPUT "EXT pad_sig2_net_pt (nwell NOT (OR v5 v12 v20)) < 40.0 ABUT<90 REGION MEASURE ALL" |
| } |
| |
| SETLAYER holes_ptap_ring = "HOLES ptap" |
| SETLAYER holes_ntap_ring = "(HOLES ntap) INTERACT (HOLES nwell)" |
| |
| SETLAYER ptap_ring = "ptap TOUCH holes_ptap_ring" |
| SETLAYER ntap_ring = "(nwell INTERACT holes_ntap_ring) AND ntap" |
| |
| SETLAYER ptap_is_outer = "ptap TOUCH ((HOLES ptap) ENCLOSE ntap_ring)" |
| SETLAYER ntap_is_outer = "ntap INTERACT ((HOLES ntap) ENCLOSE ptap_ring)" |
| SETLAYER outer_ring = "OR ptap_is_outer ntap_is_outer" |
| |
| SETLAYER ptap_is_inner = "ptap INTERACT (ptap_ring INSIDE (HOLES ntap_ring))" |
| SETLAYER ntap_is_inner = "ntap INTERACT (ntap_ring INSIDE (HOLES ptap_ring))" |
| SETLAYER inner_ring = "OR ptap_is_inner ntap_is_inner" |
| |
| SETLAYER pmos_dev = "((diff AND poly) AND psdm) AND nwell" |
| SETLAYER btw_rings = "(HOLES outer_ring) NOT (inner_ring OR (HOLES inner_ring))" |
| |
| SETLAYER hole_is_outer_around_nsd_sig = "(HOLES ntap_is_outer) INTERACT pad_sig2_net_nsd" |
| SETLAYER nw_is_outer_around_nsd_sig = "(DONUT nwell) INTERACT hole_is_outer_around_nsd_sig" |
| SETLAYER btw_rings_sig_1 = "(HOLES nw_is_outer_around_nsd_sig) ENCLOSE ptap_is_inner" |
| SETLAYER btw_rings_sig_2 = "btw_rings_sig_1 NOT ptap_is_inner" |
| SETLAYER btw_rings_sig = "btw_rings_sig_2 NOT (HOLES ptap_is_inner)" |
| |
| RULECHECK latchup.signal.13 { |
| @ latchup.signal.13: P+ MOS device is not permitted between the inner p+ ring and outer n+/nwell ring or in the shared well of the outer N+/nwell ring |
| SETLAYER part_1 = "(pmos_dev AND btw_rings) INTERACT (HOLES nw_is_outer_around_nsd_sig)" |
| SETLAYER part_2 = "(nw_is_outer_around_nsd_sig INTERACT outer_ring) AND pmos_dev" |
| OUTPUT "MERGE (OR part_1 part_2)" |
| } |
| |
| SETLAYER diff_res = diffi AND diffres |
| |
| RULECHECK latchup.signal.14 { |
| @ latchup.signal.14: diff:res is not allowed inside diff connected to a signal pad or in the shared well of the outer n+/nwell ring |
| SETLAYER part_1 = "(diff_res AND btw_rings) INTERACT (HOLES nw_is_outer_around_nsd_sig)" |
| SETLAYER part_2 = "(nw_is_outer_around_nsd_sig INTERACT outer_ring) AND diff_res" |
| OUTPUT "MERGE (OR part_1 part_2)" |
| } |
| |
| SETLAYER danger_zone = "SIZE pad_sig2_diff_all BY 100 BEVEL 3" |
| SETLAYER mos_gate_in_dz = "gate AND danger_zone" |
| SETLAYER mos_sd_in_dz = "(nsd OR psd) TOUCH mos_gate_in_dz" |
| |
| #### This rule was changed to "manual check" in the latchup document and is removed: |
| #RULECHECK latchup.signal.15 { |
| # @ latchup.signal.15: Any circuitry within 100um of any diff or tap metallically connected to a signal pad must have its source and body shorted locally |
| # OUTPUT "COPY mos_sd_in_dz" |
| # } |
| |
| ### Section 5: SPECIAL Latchup Rules |
| |
| SETLAYER ptap_in_at_risk_nw = "ptap INSIDE at_risk_non_vcc_nw" |
| SETLAYER ntap_in_at_risk_nw = "ntap INSIDE at_risk_non_vcc_nw" |
| SETLAYER at_risk_nw_inner_ring = "ptap TOUCH ((HOLES ptap) ENCLOSE at_risk_non_vcc_nw)" |
| SETLAYER at_risk_nw_outer_ring = "ntap TOUCH ((HOLES ntap) ENCLOSE at_risk_non_vcc_nw)" |
| |
| RULECHECK latchup.special.1a.1 { |
| @ latchup.special.1a.1: At risk non-Vcc nwell must be in an inner P+ tap connected to ground |
| OUTPUT "at_risk_non_vcc_nw NOT INSIDE (at_risk_nw_inner_ring INTERACT pad_gnd_net_ptap)" |
| } |
| |
| SETLAYER li_in_at_risk_nw_ptap_ring = "li_i ENCLOSE ((licon AND li_i) AND at_risk_nw_inner_ring)" |
| |
| RULECHECK latchup.special.1a.2 { |
| @ latchup.special.1a.2: P+ tap around at risk Vcc nwell must be continuously strapped in local interconnect |
| OUTPUT "at_risk_non_vcc_nw NOT INSIDE (HOLES li_in_at_risk_nw_ptap_ring)" |
| } |
| |
| RULECHECK latchup.special.1b.1 { |
| @ latchup.special.1b.1: At risk non-Vcc nwell must be in an outer N+/NW guard ring connected to power |
| SETLAYER nw_outer_inter_gnd_net = "at_risk_nw_outer_ring INTERACT pad_pwr_net_ntap" |
| SETLAYER nw_inner_inter_pad_net = "at_risk_nw_inner_ring INTERACT pad_gnd_net_ptap" |
| SETLAYER holes_outer_gr_gnd = "HOLES nw_outer_inter_gnd_net" |
| SETLAYER outer_gr_enc_inner_gr = holes_outer_gr_gnd ENCLOSE nw_inner_inter_pad_net |
| OUTPUT "at_risk_non_vcc_nw NOT INSIDE outer_gr_enc_inner_gr" |
| } |
| |
| RULECHECK latchup.special.1c.1 { |
| @ latchup.special.1c.1: Maximum space between licons in inner P+ tap around at risk non-Vcc nwell > 2.0 |
| SETLAYER lic_size_atr_nw = "SIZE (licon AND at_risk_nw_inner_ring) BY 1 INSIDE OF li_i " |
| OUTPUT "(li_i AND at_risk_nw_inner_ring) NOT lic_size_atr_nw" |
| } |
| |
| RULECHECK latchup.special.1c.2 { |
| @ latchup.special.1c.2: Maximum space between licons in outer N+ tap around at risk non-Vcc nwell > 2.0 |
| SETLAYER lic_size_atr_nw = "SIZE (licon AND at_risk_nw_outer_ring) BY 1 INSIDE OF li_i " |
| OUTPUT "(li_i AND at_risk_nw_outer_ring) NOT lic_size_atr_nw" |
| } |
| |
| SETLAYER li_in_at_risk_nw_ntap_ring = "li_i ENCLOSE ((licon AND li_i) AND at_risk_nw_outer_ring)" |
| |
| RULECHECK latchup.special.1b.2 { |
| @ latchup.special.1b.2: N+ tap around at risk non-Vcc nwell must be continuously strapped in local interconnect |
| OUTPUT "at_risk_non_vcc_nw NOT INSIDE (HOLES li_in_at_risk_nw_ptap_ring)" |
| } |
| |
| RULECHECK latchup.special.2a { |
| @ latchup.special.2a: PNP bipolar transistor must be inside inner P+ guardring tied to ground |
| OUTPUT "pnp NOT INSIDE (HOLES (ptap_is_inner INTERACT pad_gnd_net_ptap))" |
| } |
| |
| RULECHECK latchup.special.2b { |
| @ latchup.special.2b: PNP bipolar transistor must be inside outer NW/N+ tap guardring tied to power |
| OUTPUT "pnp NOT INSIDE (HOLES (ntap_is_outer INTERACT pad_pwr_net_ntap))" |
| } |
| |
| SETLAYER pnp_inner_ring = "ptap TOUCH ((HOLES ptap_is_inner) ENCLOSE pnp)" |
| SETLAYER lic_size_inner_pnp = "SIZE (licon AND pnp_inner_ring) BY 1 INSIDE OF li_i " |
| SETLAYER pnp_outer_ring = "ntap TOUCH ((HOLES ntap_is_outer) ENCLOSE pnp)" |
| SETLAYER lic_size_outer_pnp = "SIZE (licon AND pnp_outer_ring) BY 1 INSIDE OF li_i " |
| |
| RULECHECK latchup.special.2c { |
| @ latchup.special.2c: Maximum space between licons in inner P+ tap around pnp > 2.0 |
| OUTPUT "(li_i AND pnp_inner_ring) NOT lic_size_inner_pnp" |
| } |
| |
| RULECHECK latchup.special.2d { |
| @ latchup.special.2d: Maximum space between licons in outer N+ tap around pnp > 2.0 |
| OUTPUT "(li_i AND pnp_outer_ring) NOT lic_size_outer_pnp" |
| } |
| |
| |
| RULECHECK latchup.special.6 { |
| @ latchup.special.6: There should not be any N+ diffusion between the P+ diffusion in the At Risk Non-Vcc nwell and the P+ tap ring |
| OUTPUT "at_risk_non_vcc_nw ENCLOSE (nsd NOT ntap)" |
| } |
| |
| RULECHECK latchup.special.7a { |
| @ latchup.special.7a: Grounded nwell must be inside a P+ tap ring |
| OUTPUT "pad_gnd3_net_nw NOT INSIDE (HOLES ptap_ring)" |
| } |
| |
| RULECHECK latchup.special.7b { |
| @ latchup.special.7b: Grounded nwell's P+ tap ring must be connected to gnd |
| OUTPUT "((HOLES ptap_ring) ENCLOSE pad_gnd3_net_nw) NOT INTERACT pad_gnd3_net_ptap" |
| } |
| |
| ### Section 6: MISCELLANEOUS Latchup Rules |
| |
| # Rule 1.4 cannot be checked in DRC as DRC disallows Soft connect - this will |
| # be checked by soft connect checks in LVS: |
| #RULECHECK latchup.misc.1.4 { |
| # @ latchup.misc.1.4: Ptap net in isolated Pwell can not conflict with substrate majority connection |
| # OUTPUT "ptub INTERACT ptap > 1" |
| # } |
| |
| SETLAYER pad_net_m5 = "NET AREA RATIO met5 pad > 0" |
| SETLAYER pad_net_m4 = "NET AREA RATIO met4 pad > 0" |
| SETLAYER pad_net_m3 = "NET AREA RATIO met3 pad > 0" |
| SETLAYER pad_net_m2 = "NET AREA RATIO met2 pad > 0" |
| SETLAYER pad_net_m1 = "NET AREA RATIO met1 pad > 0" |
| SETLAYER pad_net_li = "NET AREA RATIO li pad > 0" |
| SETLAYER pad_net_nsd = "NET AREA RATIO nsd pad > 0" |
| SETLAYER pad_net_psd = "NET AREA RATIO psd pad > 0" |
| |
| SETLAYER target_ngate = (gate NOT ESDID) TOUCH pad_net_nsd |
| SETLAYER target_ngate_2_pad = (gate NOT ESDID) INTERACT pad_net_nsd > 1 BY NET |
| SETLAYER target_pgate = (gate NOT ESDID) TOUCH pad_net_psd |
| SETLAYER target_pgate_2_pad = (gate NOT ESDID) INTERACT pad_net_psd > 1 BY NET |
| |
| RULECHECK latchup.misc.4 { |
| @ latchup.misc.4: Non-ESD nfet or pfet with src connected to one pad and drn connected to different pad min width < 2000.0 |
| SETLAYER mark1 = "LENGTH (target_ngate_2_pad NOT COINCIDENT EDGE nsd) < 2000" |
| SETLAYER mark2 = "LENGTH (target_pgate_2_pad NOT COINCIDENT EDGE psd) < 2000" |
| SETLAYER mark1_exp = "EXPAND EDGE mark1 OUTSIDE BY 0.005" |
| SETLAYER mark2_exp = "EXPAND EDGE mark2 OUTSIDE BY 0.005" |
| OUTPUT "(gate NOT ESDID) INTERACT (OR mark1_exp mark2_exp)" |
| } |
| |
| ### Section 13: SUPER HIGH VOLATGE (SHV) Latchup Rules |
| |
| # must short all resistors not marked 1Kohm for check latchup.shv.1 in order to |
| # disciminate between those which are OK and those which are not: |
| SETLAYER pw_lu_x = pwell NOT pw_res_gt_1kohm |
| SETLAYER diff_lu_x = diffi NOT diff_res_gt_1kohm |
| SETLAYER nsd_lu_x = "(((diffi AND nsdm) NOT poly) NOT nwell) NOT diff_res_gt_1kohm" |
| SETLAYER psd_lu_x = "(((diffi AND psdm) NOT poly) AND nwell) NOT diff_res_gt_1kohm" |
| SETLAYER poly_lu_x = "polyi NOT poly_res_gt_1kohm" |
| SETLAYER li_lu_x = "li_i NOT li_res_gt_1kohm" |
| SETLAYER m1_lu_x = "met1i NOT m1_res_gt_1kohm" |
| SETLAYER m2_lu_x = "met2i NOT m2_res_gt_1kohm" |
| SETLAYER m3_lu_x = "met3i NOT m3_res_gt_1kohm" |
| SETLAYER m4_lu_x = "met4i NOT m4_res_gt_1kohm" |
| SETLAYER m5_lu_x = "met5i NOT m5_res_gt_1kohm" |
| verbatim { |
| DISCONNECT |
| CONNECT m5_lu_x m4_lu_x BY via4_c |
| CONNECT m4_lu_x m3_lu_x BY via3_c |
| CONNECT m3_lu_x m2_lu_x BY via2 |
| CONNECT m2_lu_x m1_lu_x BY via1 |
| CONNECT m1_lu_x li_lu_x BY mcon |
| CONNECT li_lu_x nsd_lu_x BY licon |
| CONNECT li_lu_x psd_lu_x BY licon |
| CONNECT li_lu_x ntap BY licon |
| CONNECT li_lu_x ptap BY licon |
| CONNECT li_lu_x ptubtap BY licon |
| CONNECT li_lu_x poly_lu_x BY licon |
| |
| CONNECT ntap nwell |
| CONNECT ptap pw_lu |
| CONNECT ptubtap ptub |
| CONNECT nwell dnwell |
| |
| CONNECT m5_lu_x pad |
| CONNECT m5_lu_x uprobe_pad |
| CONNECT m5_lu_x probe_pad |
| CONNECT rdl pad |
| CONNECT rdl uprobe_pad |
| CONNECT rdl probe_pad |
| |
| } |
| |
| SETLAYER gnd_pad2_x = "pad INTERACT pad_gnd" |
| SETLAYER shv_gate = "(gate AND (v12 OR v20)) AND thkox" |
| SETLAYER dnw_with_shv_gate = "dnwell ENCLOSE shv_gate" |
| |
| RULECHECK latchup.shv.1 { |
| @ latchup.shv.1: DNW connected to ground < 1000 ohm is not allowed if the DNW contains super high voltage connected active NFETs or PFETs |
| OUTPUT "NET AREA RATIO dnw_with_shv_gate gnd_pad2_x > 0" |
| } |
| |
| SETLAYER pwr2_pad_y = "pad INTERACT pad_pwr" |
| SETLAYER pad_pwr2_net_m5_y = "NET AREA RATIO m5_lu_x pwr2_pad_y > 0" |
| SETLAYER pad_pwr2_net_m4_y = "NET AREA RATIO m4_lu_x pwr2_pad_y > 0" |
| SETLAYER pad_pwr2_net_m3_y = "NET AREA RATIO m3_lu_x pwr2_pad_y > 0" |
| SETLAYER pad_pwr2_net_m2_y = "NET AREA RATIO m2_lu_x pwr2_pad_y > 0" |
| SETLAYER pad_pwr2_net_m1_y = "NET AREA RATIO m1_lu_x pwr2_pad_y > 0" |
| SETLAYER pad_pwr2_net_li_y = "NET AREA RATIO li_lu_x pwr2_pad_y > 0" |
| SETLAYER pad_pwr2_net_nsd_y = "NET AREA RATIO nsd_lu_x pwr2_pad_y > 0" |
| SETLAYER pad_pwr2_net_ntap_y = "NET AREA RATIO ntap pwr2_pad_y > 0" |
| SETLAYER pad_pwr2_net_psd_y = "NET AREA RATIO psd_lu_x pwr2_pad_y > 0" |
| SETLAYER pad_pwr2_net_ptap_y = "NET AREA RATIO ptap pwr2_pad_y > 0" |
| SETLAYER pad_pwr2_net_poly_y = "NET AREA RATIO poly_lu_x pwr2_pad_y > 0" |
| SETLAYER pad_pwr2_net_pw_y = "NET AREA RATIO pw_lu pwr2_pad_y > 0" |
| |
| RULECHECK latchup.shv.2 { |
| @ latchup.shv.2: Minimum distance between NW/DNW connected metallically to SHV signal pad to a P+ diff connected to a positive power supply < 70 um |
| SETLAYER pad_dnw_sig_v20 = "pad_sig2_net_dnw AND (OR v12 v20)" |
| SETLAYER pad_nw_sig_v20 = "pad_sig2_net_nw AND (OR v12 v20)" |
| OUTPUT "EXT pad_dnw_sig_v20 pad_pwr2_net_psd_y < 70.0 ABUT<90 REGION" |
| OUTPUT "EXT pad_nw_sig_v20 pad_pwr2_net_psd_y < 70.0 ABUT<90 REGION" |
| OUTPUT "EXT pad_dnw_sig_v20 pad_pwr2_net_ptap_y < 70.0 ABUT<90 REGION" |
| OUTPUT "EXT pad_nw_sig_v20 pad_pwr2_net_ptap_y < 70.0 ABUT<90 REGION" |
| OUTPUT "EXT pad_dnw_sig_v20 pad_pwr2_net_pw_y < 70.0 ABUT<90 REGION MEASURE ALL" |
| OUTPUT "EXT pad_nw_sig_v20 pad_pwr2_net_pw_y < 70.0 ABUT<90 REGION MEASURE ALL" |
| } |
| |
| RULECHECK latchup.shv.3 { |
| @ latchup.shv.3: Minimum distance between PW connected metallically to SHV signal pad to any N+ diff/tap/NW/DNW connected to a ground < 100 |
| SETLAYER pad_pw_sig_v20a = "pad_sig2_net_pw AND (OR v12 v20)" |
| SETLAYER pad_pw_sig_v20b = "pad_sig2_net_ls AND (OR v12 v20)" |
| SETLAYER pad_pw_sig_v20c = "pad_sig2_net_pt AND (OR v12 v20)" |
| SETLAYER pad_pw_sig_v20 = "OR pad_pw_sig_v20a pad_pw_sig_v20b pad_pw_sig_v20c" |
| OUTPUT "EXT pad_pw_sig_v20 pad_gnd2_net_ntap < 100 ABUT<90 REGION" |
| OUTPUT "EXT pad_pw_sig_v20 pad_gnd2_net_nsd < 100 ABUT<90 REGION" |
| OUTPUT "EXT pad_pw_sig_v20 pad_gnd2_net_nw < 100 ABUT<90 REGION" |
| OUTPUT "EXT pad_pw_sig_v20 pad_gnd2_net_dnw < 100 ABUT<90 REGION" |
| } |
| |
| ### Rule SHV rule 4 is not coded pending availability of IO library |
| |
| verbatim { |
| #ENDIF //not skip latchup checks |
| } |
| |
| # JAG 7/8/21 removed as duplicate of revised nwell.OVL.1: |
| #RULECHECK nwell_missing_tap.1 { |
| #@ nwell_missing_tap.1: Nwell must connect by ntap at least once |
| # OUTPUT "nwell NOT ENCLOSE ntap" |
| # } |
| |
| # JAG 7/8/21 moved to RECOMMENDED floating rule |
| #RULECHECK pwell_missing_tap.1 { |
| #@ pwell_missing_tap.1: substrate must connect by ptap at least once |
| # OUTPUT "pwell NOT ENCLOSE ptap" |
| # } |
| |
| # JAG 7/8/21 moved to RECOMMENDED floating rule |
| #RULECHECK ptub_missing_tap.1 { |
| #@ ptub_missing_tap.1: substrate must connect by ptap at least once |
| # OUTPUT "ptub NOT ENCLOSE ptap" |
| # } |
| |
| # JAG 7/8/21 moved to RECOMMENDED floating rule |
| #RULECHECK subcut_missing_tap.1 { |
| # @ subcut_missing_tap.1: substrate in areaid:substrateCut must connect to ptap at least once |
| # OUTPUT "localSub NOT ENCLOSE ptap" |
| # } |
| |
| # JAG 7/8/21 removed as duplicate of dnwell.CON.4: |
| #RULECHECK dnwell_missing_nwell.1 { |
| #@ dnwell_missing_nwell.1: dnwell missing nwell connectection |
| # OUTPUT "dnwell NOT INTERACT nwell" |
| # } |
| |
| verbatim { |
| |
| // |
| // LONELY VIA/CONTACT rules |
| // |
| |
| #IFNDEF SKIP_RECOMMENDED_CHECKS |
| |
| //LICON (on poly): |
| // licon size 0.17 |
| // licon space 0.17 |
| // li enc licon 0.08 |
| // poly enc licon 0.05 |
| |
| } |
| |
| SETLAYER lipl = "(li_i AND polyi) NOT diffi" |
| SETLAYER lic_size_pl = "SIZE licon BY .42 INSIDE of lipl" |
| SETLAYER lic_space_size_pl = "SIZE licon BY .17 INSIDE of lipl" |
| SETLAYER lipl_no_lic = "((lipl ENCLOSE lic_size_pl) NOT lic_space_size_pl) NOT INTERACT licon" |
| SETLAYER potential_area_for_lic_pl = "WITH WIDTH lipl_no_lic > 0.29" |
| SETLAYER pl_excl_area = "polyii INSIDE CELL \"esd*\"" |
| SETLAYER li_excl_area = "li_ii INSIDE CELL \"esd*\"" |
| SETLAYER lic_excl_area_pl = "pl_excl_area OR li_excl_area" |
| SETLAYER poly_gate_stub = "(((RECTANGLE (polyii NOT gate)) TOUCH gate == 1) ENCLOSE licon == 1) NOT INTERACT met1" |
| |
| RULECHECK lonely.poly.licon.R { |
| @ lonely.poly.licon.R: There may be room for additional licon(s) in this poly/li area |
| OUTPUT "(((lipl INTERACT potential_area_for_lic_pl) NOT lic_excl_area_pl) NOT INTERACT poly_gate_stub) ENCLOSE < 2 licon" |
| } |
| |
| #poly and li encloses a licon and it is not in standard cells: |
| SETLAYER potential_area_for_more_poly = "(((polyi NOT gate) ENCLOSE licon == 1) AND li) NOT STDCID" |
| # make sure there is a minimum amount of room (2 licons spaced apart by min (0.17) plus new licon = .51): |
| SETLAYER potential_area_for_more_poly_size = "SIZE potential_area_for_more_poly BY 0.51" |
| # create a halo around the area: |
| SETLAYER potential_area_for_more_poly_size_halo = "SIZE potential_area_for_more_poly_size BY 1" |
| # start to create a blocking region |
| SETLAYER potential_area_for_more_poly_size_block1 = "(potential_area_for_more_poly_size_halo AND (OR polyi diff1 licon)) NOT potential_area_for_more_poly" |
| # make sure there is room for more poly by sizing by poly min spacing: |
| SETLAYER potential_area_for_more_poly_size_block = "SIZE (poly AND potential_area_for_more_poly_size_block1) BY 0.34" |
| # create the potential area for an additional licon: |
| SETLAYER potential_area_for_pl_lic_1 = "potential_area_for_more_poly_size_block ENCLOSE (polyi AND potential_area_for_more_poly_size_block) < 2" |
| SETLAYER potential_area_for_pl_lic_2 = "potential_area_for_more_poly_size_block ENCLOSE (li AND potential_area_for_more_poly_size_block) < 2" |
| SETLAYER potential_area_for_pl_lic_3 = "potential_area_for_more_poly_size_block ENCLOSE (diffi AND potential_area_for_more_poly_size_block) < 1" |
| SETLAYER potential_area_for_pl_lic_a = "(potential_area_for_pl_lic_1 AND potential_area_for_pl_lic_2) NOT potential_area_for_pl_lic_3" |
| # make sure this is not an area with a licon bar: |
| SETLAYER sq_licon = "RECTANGLE licon == ${licon_min_w} BY == ${licon_min_w}" |
| SETLAYER non_sq_licon = "licon NOT sq_licon" |
| SETLAYER potential_area_for_pl_lic = "potential_area_for_pl_lic_a NOT INTERACT non_sq_licon" |
| # make sure this is not a small gate extension: |
| SETLAYER gate_extension_lt_pt_5 = "(polyi NOT gate) INTERACT (INT (SIZE gate by 1 INSIDE OF polyi) < 0.505 ABUT<90 REGION)" |
| # remove small gate extensions: |
| SETLAYER potential_area_for_pl_lonely_yes = "(((potential_area_for_pl_lic INTERACT potential_area_for_more_poly) OR potential_area_for_more_poly) ENCLOSE sq_licon == 1) NOT interact gate_extension_lt_pt_5" |
| |
| RULECHECK lonely.poly.licon.a.R { |
| @ lonely.poly.licon.a.R: By adding additional poly and/or li, there may be room for additional licons |
| OUTPUT "COPY (MERGE ((((polyi AND li) NOT gate) AND potential_area_for_pl_lonely_yes) NOT poly_gate_stub))" |
| } |
| |
| verbatim { |
| //LICON (on diff): |
| // licon size 0.17 |
| // licon space 0.17 |
| // li enc licon 0.08 |
| // diff enc licon 0.12 |
| } |
| |
| SETLAYER lidf = "(li_i AND diffi) NOT polyi" |
| SETLAYER lic_size_df = "SIZE licon BY .54 INSIDE of lidf" |
| SETLAYER lic_space_size_df = "SIZE licon BY .17 INSIDE of lidf" |
| SETLAYER lidf_no_lic = "((lidf ENCLOSE lic_size_df) NOT lic_space_size_df) NOT INTERACT licon" |
| SETLAYER potential_area_for_lic_df = "WITH WIDTH lidf_no_lic > 0.29" |
| SETLAYER df_excl_area = "diffii INSIDE CELL \"esd*\"" |
| SETLAYER lic_excl_area_df = "df_excl_area OR li_excl_area" |
| |
| RULECHECK lonely.diff.licon.R { |
| @ lonely.diff.licon.R: There may be room for additional licon(s) in this diff/li area |
| OUTPUT "((lidf INTERACT potential_area_for_lic_df) NOT lic_excl_area_df) ENCLOSE < 2 licon" |
| } |
| |
| #diff and li encloses a licon and it is not in standard cells: |
| SETLAYER potential_area_for_more_diff = "(((diffi NOT gate) ENCLOSE licon == 1) AND li) NOT STDCID" |
| # make sure there is a minimum amount of room (2 licons spaced apart by min (0.17) plus new licon = .51): |
| SETLAYER potential_area_for_more_diff_size = "SIZE potential_area_for_more_diff BY 0.51" |
| # create a halo around the area: |
| SETLAYER potential_area_for_more_diff_size_halo = "SIZE potential_area_for_more_diff_size BY 1" |
| # start to create a blocking region |
| SETLAYER potential_area_for_more_diff_size_block1 = "(potential_area_for_more_diff_size_halo AND (OR polyi diff1 licon)) NOT potential_area_for_more_diff" |
| # make sure there is room for more diff by sizing by diff min spacing: |
| SETLAYER potential_area_for_more_diff_size_block = "SIZE (diffi AND potential_area_for_more_diff_size_block1) BY 0.34" |
| # create the potential area for an additional licon: |
| SETLAYER potential_area_for_df_lic_1 = "potential_area_for_more_diff_size_block ENCLOSE (diffi AND potential_area_for_more_diff_size_block) < 2" |
| SETLAYER potential_area_for_df_lic_2 = "potential_area_for_more_diff_size_block ENCLOSE (li AND potential_area_for_more_diff_size_block) < 2" |
| SETLAYER potential_area_for_df_lic_3 = "potential_area_for_more_diff_size_block ENCLOSE ((SIZE licon BY 0.17) AND potential_area_for_more_diff_size_block) < 1" |
| SETLAYER potential_area_for_df_lic_a = "(potential_area_for_df_lic_1 AND potential_area_for_df_lic_2) NOT potential_area_for_df_lic_3" |
| # make sure this is not an area with a licon bar: |
| SETLAYER potential_area_for_df_lic = "potential_area_for_df_lic_a NOT INTERACT non_sq_licon" |
| # remove small gate extensions: |
| SETLAYER potential_area_for_df_lonely_yes = "(((potential_area_for_df_lic INTERACT potential_area_for_more_diff) OR potential_area_for_more_diff) ENCLOSE sq_licon == 1) NOT interact gate_extension_lt_pt_5" |
| |
| RULECHECK lonely.diff.licon.a.R { |
| @ lonely.diff.licon.a.R: By adding additional diff and/or li, there may be room for additional licons |
| OUTPUT "COPY (MERGE (((diffi AND li) NOT gate) AND potential_area_for_df_lonely_yes))" |
| } |
| |
| |
| verbatim { |
| // MCON: |
| // mcon size 0.17 |
| // mcon space 0.19 |
| // m1 enc mcon 0.03 |
| // li enc mcon 0.0 |
| |
| } |
| |
| SETLAYER m1l1 = "met1i AND li_i" |
| SETLAYER mcon_size = "SIZE mcon BY .39 INSIDE OF m1l1" |
| SETLAYER mcon_space_size = "SIZE mcon BY .19 INSIDE OF m1l1" |
| SETLAYER m1l1_no_mcon = "((m1l1 ENCLOSE mcon_size) NOT mcon_space_size) NOT INTERACT mcon" |
| SETLAYER potential_area_for_mcon = "WITH WIDTH m1l1_no_mcon >= 0.25" |
| SETLAYER mcon_m1_excl_area = "met1ii INSIDE CELL \"esd*\"" |
| SETLAYER mcon_l1_excl_area = "li_ii INSIDE CELL \"esd*\"" |
| SETLAYER mcon_excl_area = "mcon_m1_excl_area OR mcon_l1_excl_area" |
| |
| RULECHECK lonely.mcon.R { |
| @ lonely.mcon.R: There may be room for additional metal contact(s) |
| OUTPUT "((m1l1 INTERACT potential_area_for_mcon) NOT mcon_excl_area) ENCLOSE < 2 mcon" |
| } |
| |
| #m1 and li encloses an mcon and it is not in standard cells: |
| SETLAYER potential_area_for_more_mcon = "((met1i AND li_i) ENCLOSE mcon == 1) NOT STDCID" |
| # make sure there is a minimum amount of room (2 mcons spaced apart by min (0.19) plus new licon = .53): |
| SETLAYER potential_area_for_more_mcon_size = "SIZE potential_area_for_more_mcon BY 0.53" |
| # create a halo around the area: |
| SETLAYER potential_area_for_more_mcon_size_halo = "SIZE potential_area_for_more_mcon_size BY 1" |
| # start to create a blocking region |
| SETLAYER potential_area_for_more_mcon_size_block1 = "(potential_area_for_more_mcon_size_halo AND (OR met1i li_i mcon)) NOT potential_area_for_more_mcon" |
| # make sure there is room for more met1 by sizing by met1 min spacing: |
| SETLAYER potential_area_for_more_mcon_size_block = "SIZE (met1i AND potential_area_for_more_mcon_size_block1) BY 0.28" |
| # create the potential area for an additional mcon: |
| SETLAYER potential_area_for_m1_lic_1 = "potential_area_for_more_mcon_size_block ENCLOSE (met1i AND potential_area_for_more_mcon_size_block) < 2" |
| SETLAYER potential_area_for_m1_lic_2 = "potential_area_for_more_mcon_size_block ENCLOSE (li_i AND potential_area_for_more_mcon_size_block) < 2" |
| SETLAYER potential_area_for_m1_lic_3 = "potential_area_for_more_mcon_size_block ENCLOSE ((SIZE mcon BY 0.19) AND potential_area_for_more_mcon_size_block) < 1" |
| SETLAYER potential_area_for_m1_lic = "(potential_area_for_m1_lic_1 AND potential_area_for_m1_lic_2) NOT potential_area_for_m1_lic_3" |
| SETLAYER potential_area_for_m1_lonely_yes = "(potential_area_for_m1_lic INTERACT potential_area_for_more_mcon) OR potential_area_for_more_mcon" |
| |
| RULECHECK lonely.mcon.a.R { |
| @ lonely.mcon.a.R: By adding additional met1 and/or li, there may be room for additional mcons |
| OUTPUT "COPY (MERGE ((met1i AND li) AND potential_area_for_m1_lonely_yes))" |
| } |
| |
| verbatim { |
| // VIA: |
| // via size 0.15 |
| // m1 enc via 0.085 (adj sides) |
| // via space 0.17 |
| // m2 enc via 0.085 (adj sides) |
| } |
| |
| SETLAYER m1m2 = "met1i AND met2i" |
| SETLAYER via_size = "SIZE via1 BY .405 INSIDE OF m1m2" |
| SETLAYER via_space_size = "SIZE via1 BY .17 INSIDE OF m1m2" |
| SETLAYER m1m2_no_via = "((m1m2 ENCLOSE via_size) NOT via_space_size) NOT INTERACT via1" |
| SETLAYER potential_area_for_via = "WITH WIDTH m1m2_no_via >= 0.235" |
| SETLAYER via_m1_excl_area = "met1ii INSIDE CELL \"esd*\"" |
| SETLAYER via_m2_excl_area = "met2ii INSIDE CELL \"esd*\"" |
| SETLAYER via_excl_area = "via_m1_excl_area OR via_m2_excl_area" |
| |
| RULECHECK lonely.via1.R { |
| @ lonely.via1.R: There may be room for additional via1(s) |
| OUTPUT "((m1m2 INTERACT potential_area_for_via) NOT via_excl_area) ENCLOSE < 2 via1" |
| } |
| |
| #m1 and m2 encloses a via and it is not in standard cells: |
| SETLAYER potential_area_for_more_via = "((met1i AND met2i) ENCLOSE via1 == 1) NOT STDCID" |
| # make sure there is a minimum amount of room (2 via spaced apart by min (0.17) plus new via = .49): |
| SETLAYER potential_area_for_more_via_size = "SIZE potential_area_for_more_via BY 0.49" |
| # create a halo around the area: |
| SETLAYER potential_area_for_more_via_size_halo = "SIZE potential_area_for_more_via_size BY 1" |
| # start to create a blocking region |
| SETLAYER potential_area_for_more_via_size_block1 = "(potential_area_for_more_via_size_halo AND (OR met1i via1 met2i)) NOT potential_area_for_more_via" |
| # make sure there is room for more met1 by sizing by met1 min spacing: |
| SETLAYER potential_area_for_more_via_size_block = "SIZE (met1i AND potential_area_for_more_via_size_block1) BY 0.28" |
| # create the potential area for an additional via: |
| SETLAYER potential_area_for_v1_lic_1 = "potential_area_for_more_via_size_block ENCLOSE (met1i AND potential_area_for_more_via_size_block) < 2" |
| SETLAYER potential_area_for_v1_lic_2 = "potential_area_for_more_via_size_block ENCLOSE (met2i AND potential_area_for_more_via_size_block) < 2" |
| SETLAYER potential_area_for_v1_lic_3 = "potential_area_for_more_via_size_block ENCLOSE ((SIZE via1 BY 0.17) AND potential_area_for_more_via_size_block) < 1" |
| SETLAYER potential_area_for_v1_lic = "(potential_area_for_v1_lic_1 AND potential_area_for_v1_lic_2) NOT potential_area_for_v1_lic_3" |
| SETLAYER potential_area_for_v1_lonely_yes = "(potential_area_for_v1_lic INTERACT potential_area_for_more_via) OR potential_area_for_more_via" |
| |
| RULECHECK lonely.via1.a.R { |
| @ lonely.via1.a.R: By adding additional met1 and/or met2, there may be room for additional via1s |
| OUTPUT "COPY (MERGE ((met1i AND met2i) AND potential_area_for_v1_lonely_yes))" |
| } |
| |
| |
| verbatim { |
| // VIA2: |
| // via2 size 0.2 |
| // m2 enc via2 0.065 (adj sides) |
| // via2 space 0.20 |
| // m3 enc via2 0.065 (adj sides) |
| } |
| |
| SETLAYER m2m3 = "met2i AND met3i" |
| SETLAYER via2_size = "SIZE via2 BY .465 INSIDE OF m2m3" |
| SETLAYER via2_space_size = "SIZE via2 BY .2 INSIDE OF m2m3" |
| SETLAYER m2m3_no_via2 = "((m2m3 ENCLOSE via2_size) NOT via2_space_size) NOT INTERACT via2" |
| SETLAYER potential_area_for_via2 = "WITH WIDTH m2m3_no_via2 >= 0.265" |
| SETLAYER via2_m2_excl_area = "met2ii INSIDE CELL \"esd*\"" |
| SETLAYER via2_m3_excl_area = "met3ii INSIDE CELL \"esd*\"" |
| SETLAYER via2_excl_area = "via2_m2_excl_area OR via2_m3_excl_area" |
| |
| RULECHECK lonely.via2.R { |
| @ lonely.via2.R: There may be room for additional via2(s) |
| OUTPUT "((m2m3 INTERACT potential_area_for_via2) NOT via2_excl_area) ENCLOSE < 2 via2" |
| } |
| |
| SETLAYER small_v2 = "RECTANGLE via2 == 0.2 BY == 0.2" |
| #m2 and m3 encloses a smallvia2 and it is not in standard cells: |
| SETLAYER potential_area_for_more_via2 = "((met2i AND met3i) ENCLOSE small_v2 == 1) NOT STDCID" |
| # make sure there is a minimum amount of room (2 via spaced apart by min (0.17) plus new via = .54): |
| SETLAYER potential_area_for_more_via2_size = "SIZE potential_area_for_more_via2 BY 0.54" |
| # create a halo around the area: |
| SETLAYER potential_area_for_more_via2_size_halo = "SIZE potential_area_for_more_via2_size BY 1" |
| # start to create a blocking region |
| SETLAYER potential_area_for_more_via2_size_block1 = "(potential_area_for_more_via2_size_halo AND (OR met2i via1 met3i)) NOT potential_area_for_more_via2" |
| # make sure there is room for more met2 by sizing by met2 min spacing: |
| SETLAYER potential_area_for_more_via2_size_block = "SIZE (met2i AND potential_area_for_more_via2_size_block1) BY 0.28" |
| # create the potential area for an additional via2: |
| SETLAYER potential_area_for_v2_lic_1 = "potential_area_for_more_via2_size_block ENCLOSE (met2i AND potential_area_for_more_via2_size_block) < 2" |
| SETLAYER potential_area_for_v2_lic_2 = "potential_area_for_more_via2_size_block ENCLOSE (met3i AND potential_area_for_more_via2_size_block) < 2" |
| SETLAYER potential_area_for_v2_lic_3 = "potential_area_for_more_via2_size_block ENCLOSE ((SIZE via2 BY 0.17) AND potential_area_for_more_via2_size_block) < 1" |
| SETLAYER potential_area_for_v2_lic = "(potential_area_for_v2_lic_1 AND potential_area_for_v2_lic_2) NOT potential_area_for_v2_lic_3" |
| SETLAYER potential_area_for_v2_lonely_yes = "(potential_area_for_v2_lic INTERACT potential_area_for_more_via2) OR potential_area_for_more_via2" |
| |
| RULECHECK lonely.via2.a.R { |
| @ lonely.via2.a.R: By adding additional met2 and/or met3, there may be room for additional via2s |
| OUTPUT "COPY (MERGE ((met2i AND met3i) AND potential_area_for_v2_lonely_yes))" |
| } |
| |
| |
| verbatim { |
| // VIA3: |
| // via3 size 0.2 |
| // m3 enc via3 0.09 (adj sides) |
| // via3 space 0.20 |
| // m4 enc via3 0.065 (adj sides) |
| } |
| |
| SETLAYER m3m4 = "met3i AND met4i" |
| SETLAYER via3_size = "SIZE via3 BY .49 INSIDE OF m3m4" |
| SETLAYER via3_space_size = "SIZE via3 BY .2 INSIDE OF m3m4" |
| SETLAYER m3m4_no_via3 = "((m3m4 ENCLOSE via3_size) NOT via3_space_size) NOT INTERACT via3" |
| SETLAYER potential_area_for_via3 = "WITH WIDTH m3m4_no_via3 >= 0.29" |
| SETLAYER via3_m3_excl_area = "met3ii INSIDE CELL \"esd*\"" |
| SETLAYER via3_m4_excl_area = "met4ii INSIDE CELL \"esd*\"" |
| SETLAYER via3_excl_area = "via3_m3_excl_area OR via3_m4_excl_area" |
| |
| RULECHECK lonely.via3.R { |
| @ lonely.via3.R: There may be room for additional via3(s) |
| OUTPUT "((m3m4 INTERACT potential_area_for_via3) NOT via3_excl_area) ENCLOSE < 2 via3" |
| } |
| |
| #m3 and m4 encloses a small via3 and it is not in standard cells: |
| SETLAYER small_v3 = "RECTANGLE via3 == 0.2 BY == 0.2" |
| SETLAYER potential_area_for_more_via3 = "((met3i AND met4i) ENCLOSE small_v3 == 1) NOT STDCID" |
| # make sure there is a minimum amount of room (2 via spaced apart by min (0.20) plus new via = .54): |
| SETLAYER potential_area_for_more_via3_size = "SIZE potential_area_for_more_via3 BY 0.54" |
| # create a halo around the area: |
| SETLAYER potential_area_for_more_via3_size_halo = "SIZE potential_area_for_more_via3_size BY 1" |
| # start to create a blocking region |
| SETLAYER potential_area_for_more_via3_size_block1 = "(potential_area_for_more_via3_size_halo AND (OR met3i via1 met4i)) NOT potential_area_for_more_via3" |
| # make sure there is room for more met3 by sizing by met3 min spacing: |
| SETLAYER potential_area_for_more_via3_size_block = "SIZE (met3i AND potential_area_for_more_via3_size_block1) BY 0.28" |
| # create the potential area for an additional via3: |
| SETLAYER potential_area_for_v3_lic_1 = "potential_area_for_more_via3_size_block ENCLOSE (met3i AND potential_area_for_more_via3_size_block) < 2" |
| SETLAYER potential_area_for_v3_lic_2 = "potential_area_for_more_via3_size_block ENCLOSE (met4i AND potential_area_for_more_via3_size_block) < 2" |
| SETLAYER potential_area_for_v3_lic_3 = "potential_area_for_more_via3_size_block ENCLOSE ((SIZE via3 BY 0.17) AND potential_area_for_more_via3_size_block) < 1" |
| SETLAYER potential_area_for_v3_lic = "(potential_area_for_v3_lic_1 AND potential_area_for_v3_lic_2) NOT potential_area_for_v3_lic_3" |
| SETLAYER potential_area_for_v3_lonely_yes = "(potential_area_for_v3_lic INTERACT potential_area_for_more_via3) OR potential_area_for_more_via3" |
| |
| RULECHECK lonely.via3.a.R { |
| @ lonely.via3.a.R: By adding additional met3 and/or met4, there may be room for additional via3s |
| OUTPUT "COPY (MERGE ((met3i AND met4i) AND potential_area_for_v3_lonely_yes))" |
| } |
| |
| verbatim { |
| // VIA4: |
| // via4 size 0.8 |
| // m4 enc via4 0.06 (adj sides) |
| // via4 space 0.80 |
| // m5 enc via4 0.310 (adj sides) |
| } |
| |
| SETLAYER m4m5 = "met4i AND met5i" |
| SETLAYER via4_size = "SIZE via4 BY 1.91 INSIDE OF m4m5" |
| SETLAYER via4_space_size = "SIZE via4 BY 0.8 INSIDE OF m4m5" |
| SETLAYER m4m5_no_via4 = "((m4m5 ENCLOSE via4_size) NOT via4_space_size) NOT INTERACT via4" |
| SETLAYER potential_area_for_via4 = "WITH WIDTH m4m5_no_via4 >= 1.11" |
| SETLAYER via4_m4_excl_area = "met4ii INSIDE CELL \"esd*\"" |
| SETLAYER via4_m5_excl_area = "met5ii INSIDE CELL \"esd*\"" |
| SETLAYER via4_excl_area = "via4_m4_excl_area OR via4_m5_excl_area" |
| |
| RULECHECK lonely.via4.R { |
| @ lonely.via4.R: There may be room for additional via4(s) |
| OUTPUT "((m4m5 INTERACT potential_area_for_via4) NOT via4_excl_area) ENCLOSE < 2 via4" |
| } |
| |
| #m4 and m5 encloses a via4 and it is not in standard cells: |
| SETLAYER potential_area_for_more_via4 = "((met4i AND met5i) ENCLOSE via4 == 1) NOT STDCID" |
| # make sure there is a minimum amount of room (2 via spaced apart by min (0.80) plus new via = 1.6): |
| SETLAYER potential_area_for_more_via4_size = "SIZE potential_area_for_more_via3 BY 1.6" |
| # create a halo around the area: |
| SETLAYER potential_area_for_more_via4_size_halo = "SIZE potential_area_for_more_via4_size BY 1.5" |
| # start to create a blocking region |
| SETLAYER potential_area_for_more_via4_size_block1 = "(potential_area_for_more_via4_size_halo AND (OR met4i via1 met5i)) NOT potential_area_for_more_via4" |
| # make sure there is room for more met4 by sizing by met4 min spacing: |
| SETLAYER potential_area_for_more_via4_size_block = "SIZE (met4i AND potential_area_for_more_via4_size_block1) BY 0.3" |
| # create the potential area for an additional via4: |
| SETLAYER potential_area_for_v4_lic_1 = "potential_area_for_more_via4_size_block ENCLOSE (met4i AND potential_area_for_more_via4_size_block) < 2" |
| SETLAYER potential_area_for_v4_lic_2 = "potential_area_for_more_via4_size_block ENCLOSE (met5i AND potential_area_for_more_via4_size_block) < 2" |
| SETLAYER potential_area_for_v4_lic_3 = "potential_area_for_more_via4_size_block ENCLOSE ((SIZE via4 BY 0.8) AND potential_area_for_more_via4_size_block) < 1" |
| SETLAYER potential_area_for_v4_lic = "(potential_area_for_v4_lic_1 AND potential_area_for_v4_lic_2) NOT potential_area_for_v4_lic_3" |
| SETLAYER potential_area_for_v4_lonely_yes = "(potential_area_for_v4_lic INTERACT potential_area_for_more_via4) OR potential_area_for_more_via4" |
| |
| RULECHECK lonely.via4.a.R { |
| @ lonely.via4.a.R: By adding additional met4 and/or met5, there may be room for additional via4s |
| OUTPUT "COPY (MERGE ((met4i AND met5i) AND potential_area_for_v4_lonely_yes))" |
| } |
| |
| verbatim { |
| #ENDIF |
| } |
| |
| verbatim { |
| |
| // |
| // FLOATING interconnect check |
| // |
| |
| #IFNDEF SKIP_RECOMMENDED_CHECKS |
| |
| } |
| |
| # TAPS: |
| SETLAYER ptap_1 = "(((diff AND psdm) NOT nwell) NOT ptub) NOT ptubtap" |
| SETLAYER ntap_1 = "(diff AND nsdm) AND nwell" |
| |
| # MOS: |
| SETLAYER nsd1 = "((diff and nsdm) NOT nwell) NOT gate" |
| SETLAYER psd1 = "((diff and psdm) AND nwell) NOT gate" |
| |
| SETLAYER ngate_de_12v_pw = "(((((gate and nsdm) AND v12) AND ENID) NOT nwell) AND thkox) NOT (OR v5 v20 ESDID LVID pnp npn)" |
| |
| SETLAYER ngate_de_12v_gate_conn = "ngate_de_12v_pw AND poly" |
| |
| SETLAYER nsrc_de_12v = "nsd1 INTERACT ngate_de_12v_pw" |
| |
| # 12v ngate: |
| SETLAYER ndrn_de_12v = "((((ENID ENCLOSE ntap_1) INTERACT ngate_de_12v_pw) NOT ngate_de_12v_pw) NOT nsrc_de_12v) AND nwell" |
| |
| # 12v extended drain pgate: |
| SETLAYER pgate_de_12v_pw = "(((((gate and psdm) AND v12) AND ENID) AND nwell) AND thkox) NOT (OR v5 v20 ESDID LVID pnp npn)" |
| |
| SETLAYER psrc_de_12v = "psd1 INTERACT pgate_de_12v_pw" |
| SETLAYER pdrn_de_12v = "((((ENID ENCLOSE ptap_1) ENCLOSE pgate_de_12v_pw) NOT pgate_de_12v_pw) NOT psrc_de_12v) NOT nwell" |
| |
| SETLAYER pgate_de_12v_gate_conn = "pgate_de_12v_pw AND poly" |
| |
| # RES: |
| |
| # high precision/high sheet: |
| SETLAYER pwres_rec = "(pwres AND psdm) AND ((HOLES nwell) AND dnwell) " |
| SETLAYER pwres_term = "((psdm NOT pwres) ENCLOSE diff) TOUCH pwres_rec == 1" |
| |
| SETLAYER hp_poly_1 = "poly AND polyres " |
| SETLAYER hp_poly_2 = "hp_poly_1 AND npc" |
| SETLAYER hp_poly_3 = "hp_poly_2 AND psdm" |
| SETLAYER hp_poly = "hp_poly_3 AND rpm" |
| |
| SETLAYER hs_poly_1 = "poly AND polyres " |
| SETLAYER hs_poly_2 = "hs_poly_1 AND npc" |
| SETLAYER hs_poly_3 = "hs_poly_2 AND psdm" |
| SETLAYER hs_poly = "hs_poly_3 AND urpm" |
| |
| # CAP: |
| # form cap contacts: |
| SETLAYER m4_cap_m45_con = "met4 AND cap2m" |
| SETLAYER m5_cap_m45_con = "met5 AND cap2m" |
| SETLAYER cap45_m4 = "COPY m4_cap_m45_con" |
| SETLAYER cap45_m5 = "COPY m5_cap_m45_con" |
| SETLAYER m3_cap_m34 = "met3 AND capm" |
| SETLAYER m3_cap_m34_con = "met3 AND capm" |
| SETLAYER m4_cap_m34_con = "met4 AND capm" |
| SETLAYER cap34_m3 = "COPY m3_cap_m34_con" |
| SETLAYER cap34_m4 = "COPY m4_cap_m34_con" |
| |
| # ******************************************************** |
| # End layer boolean operations |
| # ******************************************************** |
| |
| # ******************************************************** |
| # Begin connect statements |
| # ******************************************************** |
| |
| # break connective layers by resistors: |
| |
| SETLAYER li_1 = "li_i NOT lires" |
| #SETLAYER li_2 = "li_i NOT WITH TEXT \"li_float\" textdraw" |
| #SETLAYER li_3 = "li_2 NOT WITH TEXT \"li_tie\" textdraw" |
| SETLAYER li_res_term = "EXPAND EDGE (COIN OUTSIDE EDGE li_1 lires) INSIDE BY 0.005" |
| SETLAYER li_res_cont = "COPY li_res_term" |
| |
| SETLAYER m1 = "met1 NOT m1res" |
| #SETLAYER m1_2 = "m1_1 NOT WITH TEXT \"m1_float\" textdraw" |
| #SETLAYER m1_3 = "m1_1 NOT WITH TEXT \"m1_tie\" textdraw" |
| SETLAYER m1_res_term = "EXPAND EDGE (COIN OUTSIDE EDGE m1 m1res) INSIDE BY 0.005" |
| SETLAYER m1_res_cont = "COPY m1_res_term" |
| |
| SETLAYER m2 = "met2 NOT m2res" |
| #SETLAYER m2_2 = "m2_1 NOT WITH TEXT \"m2_float\" textdraw" |
| #SETLAYER m2_3 = "m2_1 NOT WITH TEXT \"m2_tie\" textdraw" |
| SETLAYER m2_res_term = "EXPAND EDGE (COIN OUTSIDE EDGE m2 m2res) INSIDE BY 0.005" |
| SETLAYER m2_res_cont = "COPY m2_res_term" |
| |
| SETLAYER m3 = "met3 NOT m3res" |
| #SETLAYER m3_2 = "m3_1 NOT WITH TEXT \"m3_float\" textdraw" |
| #SETLAYER m3_3 = "m3_1 NOT WITH TEXT \"m3_tie\" textdraw" |
| SETLAYER m3_res_term = "EXPAND EDGE (COIN OUTSIDE EDGE m3 m3res) INSIDE BY 0.005" |
| SETLAYER m3_res_cont = "COPY m3_res_term" |
| |
| SETLAYER m4 = "met4 NOT m4res" |
| #SETLAYER m4_2 = "m4_1 NOT WITH TEXT \"m4_float\" textdraw" |
| #SETLAYER m4_3 = "m4_1 NOT WITH TEXT \"m4_tie\" textdraw" |
| SETLAYER m4_res_term = "EXPAND EDGE (COIN OUTSIDE EDGE m4 m4res) INSIDE BY 0.005" |
| SETLAYER m4_res_cont = "COPY m4_res_term" |
| |
| SETLAYER m5 = "met5 NOT m5res" |
| #SETLAYER m5_2 = "m5_1 NOT WITH TEXT \"m5_float\" textdraw" |
| #SETLAYER m5_3 = "m5_1 NOT WITH TEXT \"m5_tie\" textdraw" |
| SETLAYER m5_res_term = "EXPAND EDGE (COIN OUTSIDE EDGE m5 m5res) INSIDE BY 0.005" |
| SETLAYER m5_res_cont = "COPY m5_res_term" |
| |
| SETLAYER ply = "polyi NOT polyres" |
| #SETLAYER ply_2 = "ply_1 NOT WITH TEXT \"poly_float\" textdraw" |
| #SETLAYER ply = "ply_2 NOT WITH TEXT \"poly_tie\" textdraw" |
| SETLAYER pl_res_term = "EXPAND EDGE (COIN OUTSIDE EDGE ply polyres) INSIDE BY 0.005" |
| SETLAYER pl_res_cont = "COPY pl_res_term" |
| |
| SETLAYER df_res_nterm = "EXPAND EDGE (COIN OUTSIDE EDGE nsd diffres) INSIDE BY 0.005" |
| SETLAYER df_res_pterm = "EXPAND EDGE (COIN OUTSIDE EDGE psd diffres) INSIDE BY 0.005" |
| SETLAYER df_res_ncont = "COPY df_res_nterm" |
| SETLAYER df_res_pcont = "COPY df_res_pterm" |
| |
| verbatim { |
| DISCONNECT |
| |
| CONNECT rdl pad |
| CONNECT m5 pad |
| CONNECT m5 m4 BY via4_c |
| CONNECT m5 m5_res_term BY m5_res_cont |
| CONNECT m4 m3 BY via3_c |
| CONNECT m4 m4_res_term BY m4_res_cont |
| CONNECT m5 cap45_m5 BY m5_cap_m45_con |
| CONNECT m4 cap45_m4 BY m4_cap_m45_con |
| CONNECT m4 cap34_m4 BY m4_cap_m34_con |
| CONNECT m3 cap34_m3 BY m3_cap_m34_con |
| CONNECT m3 m2 BY via2 |
| CONNECT m3 m3_res_term BY m3_res_cont |
| CONNECT m2 m1 BY via1 |
| CONNECT m2 m2_res_term BY m2_res_cont |
| CONNECT m1 li BY mcon |
| CONNECT m1 m1_res_term BY m1_res_cont |
| CONNECT li li_res_term BY li_res_cont |
| CONNECT li ply BY licon |
| CONNECT li nsd BY licon |
| CONNECT li psd BY licon |
| CONNECT li ntap BY licon |
| CONNECT li ptap BY licon |
| CONNECT li ptubtap BY licon |
| CONNECT li pwres_term BY licon |
| CONNECT li nsrc_de_12v BY licon |
| CONNECT li ndrn_de_12v BY ntap |
| CONNECT li psrc_de_12v BY licon |
| CONNECT li pdrn_de_12v BY ptubtap |
| CONNECT ply pl_res_term BY pl_res_cont |
| CONNECT ply ngate_de_12v_pw BY ngate_de_12v_gate_conn |
| CONNECT ply pgate_de_12v_pw BY pgate_de_12v_gate_conn |
| CONNECT ply gate |
| CONNECT nsd df_res_nterm BY df_res_ncont |
| CONNECT psd df_res_pterm BY df_res_pcont |
| } |
| |
| proc conn_lay_dev_float { conn_lay } { |
| set a 1 |
| set b 0 |
| SETLAYER bad_${conn_lay}_${a} = "NET AREA RATIO ${conn_lay} psd == 0" |
| incr a |
| incr b |
| SETLAYER bad_${conn_lay}_${a} = "NET AREA RATIO bad_${conn_lay}_${b} nsd == 0 " |
| incr a |
| incr b |
| SETLAYER bad_${conn_lay}_${a} = "NET AREA RATIO bad_${conn_lay}_${b} gate == 0" |
| incr a |
| incr b |
| SETLAYER bad_${conn_lay}_${a} = "NET AREA RATIO bad_${conn_lay}_${b} ntap == 0" |
| incr a |
| incr b |
| SETLAYER bad_${conn_lay}_${a} = "NET AREA RATIO bad_${conn_lay}_${b} ptap == 0" |
| incr a |
| incr b |
| SETLAYER bad_${conn_lay}_${a} = "NET AREA RATIO bad_${conn_lay}_${b} ptubtap == 0" |
| incr a |
| incr b |
| SETLAYER bad_${conn_lay}_${a} = "NET AREA RATIO bad_${conn_lay}_${b} pwres_term == 0" |
| incr a |
| incr b |
| SETLAYER bad_${conn_lay}_${a} = "NET AREA RATIO bad_${conn_lay}_${b} nsrc_de_12v == 0" |
| incr a |
| incr b |
| SETLAYER bad_${conn_lay}_${a} = "NET AREA RATIO bad_${conn_lay}_${b} ndrn_de_12v == 0" |
| incr a |
| incr b |
| SETLAYER bad_${conn_lay}_${a} = "NET AREA RATIO bad_${conn_lay}_${b} psrc_de_12v == 0" |
| incr a |
| incr b |
| SETLAYER bad_${conn_lay}_${a} = "NET AREA RATIO bad_${conn_lay}_${b} pdrn_de_12v == 0" |
| incr a |
| incr b |
| SETLAYER bad_${conn_lay}_${a} = "NET AREA RATIO bad_${conn_lay}_${b} ngate_de_12v_pw == 0" |
| incr a |
| incr b |
| SETLAYER bad_${conn_lay}_${a} = "NET AREA RATIO bad_${conn_lay}_${b} pgate_de_12v_pw == 0" |
| incr a |
| incr b |
| SETLAYER bad_${conn_lay}_${a} = "NET AREA RATIO bad_${conn_lay}_${b} cap45_m4 == 0" |
| incr a |
| incr b |
| SETLAYER bad_${conn_lay}_${a} = "NET AREA RATIO bad_${conn_lay}_${b} cap45_m5 == 0" |
| incr a |
| incr b |
| SETLAYER bad_${conn_lay}_${a} = "NET AREA RATIO bad_${conn_lay}_${b} cap34_m4 == 0" |
| incr a |
| incr b |
| SETLAYER bad_${conn_lay}_${a} = "NET AREA RATIO bad_${conn_lay}_${b} cap34_m3 == 0" |
| incr a |
| incr b |
| SETLAYER bad_${conn_lay}_${a} = "NET AREA RATIO bad_${conn_lay}_${b} li_res_term == 0" |
| incr a |
| incr b |
| SETLAYER bad_${conn_lay}_${a} = "NET AREA RATIO bad_${conn_lay}_${b} m1_res_term == 0" |
| incr a |
| incr b |
| SETLAYER bad_${conn_lay}_${a} = "NET AREA RATIO bad_${conn_lay}_${b} m2_res_term == 0" |
| incr a |
| incr b |
| SETLAYER bad_${conn_lay}_${a} = "NET AREA RATIO bad_${conn_lay}_${b} m3_res_term == 0" |
| incr a |
| incr b |
| SETLAYER bad_${conn_lay}_${a} = "NET AREA RATIO bad_${conn_lay}_${b} m4_res_term == 0" |
| incr a |
| incr b |
| SETLAYER bad_${conn_lay}_${a} = "NET AREA RATIO bad_${conn_lay}_${b} m5_res_term == 0" |
| incr a |
| incr b |
| SETLAYER bad_${conn_lay}_${a} = "NET AREA RATIO bad_${conn_lay}_${b} pl_res_term == 0" |
| incr a |
| incr b |
| SETLAYER bad_${conn_lay}_${a} = "NET AREA RATIO bad_${conn_lay}_${b} df_res_nterm == 0" |
| |
| SETLAYER bad_${conn_lay} = "NET AREA RATIO bad_${conn_lay}_${a} df_res_pterm == 0" |
| } |
| |
| conn_lay_dev_float "li" |
| conn_lay_dev_float "ply" |
| conn_lay_dev_float "m1" |
| conn_lay_dev_float "m2" |
| conn_lay_dev_float "m3" |
| conn_lay_dev_float "m4" |
| conn_lay_dev_float "m5" |
| conn_lay_dev_float "rdl" |
| |
| proc conn_lay_dev_not_float { conn_lay } { |
| set a 1 |
| set b 0 |
| SETLAYER good_${conn_lay}_${a} = "NET AREA RATIO ${conn_lay} psd > 0" |
| incr a |
| incr b |
| SETLAYER good_${conn_lay}_${a} = "NET AREA RATIO good_${conn_lay}_${b} nsd > 0 " |
| incr a |
| incr b |
| SETLAYER good_${conn_lay}_${a} = "NET AREA RATIO good_${conn_lay}_${b} gate > 0" |
| incr a |
| incr b |
| SETLAYER good_${conn_lay}_${a} = "NET AREA RATIO good_${conn_lay}_${b} ntap > 0" |
| incr a |
| incr b |
| SETLAYER good_${conn_lay}_${a} = "NET AREA RATIO good_${conn_lay}_${b} ptap > 0" |
| incr a |
| incr b |
| SETLAYER good_${conn_lay}_${a} = "NET AREA RATIO good_${conn_lay}_${b} ptubtap > 0" |
| incr a |
| incr b |
| SETLAYER good_${conn_lay}_${a} = "NET AREA RATIO good_${conn_lay}_${b} pwres_term > 0" |
| incr a |
| incr b |
| SETLAYER good_${conn_lay}_${a} = "NET AREA RATIO good_${conn_lay}_${b} nsrc_de_12v > 0" |
| incr a |
| incr b |
| SETLAYER good_${conn_lay}_${a} = "NET AREA RATIO good_${conn_lay}_${b} ndrn_de_12v > 0" |
| incr a |
| incr b |
| SETLAYER good_${conn_lay}_${a} = "NET AREA RATIO good_${conn_lay}_${b} psrc_de_12v > 0" |
| incr a |
| incr b |
| SETLAYER good_${conn_lay}_${a} = "NET AREA RATIO good_${conn_lay}_${b} pdrn_de_12v > 0" |
| incr a |
| incr b |
| SETLAYER good_${conn_lay}_${a} = "NET AREA RATIO good_${conn_lay}_${b} ngate_de_12v_pw > 0" |
| incr a |
| incr b |
| SETLAYER good_${conn_lay}_${a} = "NET AREA RATIO good_${conn_lay}_${b} pgate_de_12v_pw > 0" |
| incr a |
| incr b |
| SETLAYER good_${conn_lay}_${a} = "NET AREA RATIO good_${conn_lay}_${b} cap45_m4 > 0" |
| incr a |
| incr b |
| SETLAYER good_${conn_lay}_${a} = "NET AREA RATIO good_${conn_lay}_${b} cap45_m5 > 0" |
| incr a |
| incr b |
| SETLAYER good_${conn_lay}_${a} = "NET AREA RATIO good_${conn_lay}_${b} cap34_m4 > 0" |
| incr a |
| incr b |
| SETLAYER good_${conn_lay}_${a} = "NET AREA RATIO good_${conn_lay}_${b} cap34_m3 > 0" |
| incr a |
| incr b |
| SETLAYER good_${conn_lay}_${a} = "NET AREA RATIO good_${conn_lay}_${b} li_res_term > 0" |
| incr a |
| incr b |
| SETLAYER good_${conn_lay}_${a} = "NET AREA RATIO good_${conn_lay}_${b} m1_res_term > 0" |
| incr a |
| incr b |
| SETLAYER good_${conn_lay}_${a} = "NET AREA RATIO good_${conn_lay}_${b} m2_res_term > 0" |
| incr a |
| incr b |
| SETLAYER good_${conn_lay}_${a} = "NET AREA RATIO good_${conn_lay}_${b} m3_res_term > 0" |
| incr a |
| incr b |
| SETLAYER good_${conn_lay}_${a} = "NET AREA RATIO good_${conn_lay}_${b} m4_res_term > 0" |
| incr a |
| incr b |
| SETLAYER good_${conn_lay}_${a} = "NET AREA RATIO good_${conn_lay}_${b} m5_res_term > 0" |
| incr a |
| incr b |
| SETLAYER good_${conn_lay}_${a} = "NET AREA RATIO good_${conn_lay}_${b} pl_res_term > 0" |
| incr a |
| incr b |
| SETLAYER good_${conn_lay}_${a} = "NET AREA RATIO good_${conn_lay}_${b} df_res_nterm > 0" |
| |
| SETLAYER good_${conn_lay} = "NET AREA RATIO good_${conn_lay}_${a} df_res_pterm > 0" |
| } |
| |
| conn_lay_dev_not_float "li" |
| conn_lay_dev_not_float "ply" |
| conn_lay_dev_not_float "m1" |
| conn_lay_dev_not_float "m2" |
| conn_lay_dev_not_float "m3" |
| conn_lay_dev_not_float "m4" |
| conn_lay_dev_not_float "m5" |
| conn_lay_dev_not_float "rdl" |
| |
| SETLAYER net_not_float = "OR good_ply good_li good_m1 good_m2 good_m3 good_m4 good_m5 good_rdl" |
| SETLAYER exempt_float_li_1 = "li_ii INSIDE CELL \"text_pcell*\"" |
| SETLAYER exempt_float_li_2 = "li_ii INTERACT (OR critside ccorner)" |
| SETLAYER exempt_float_li = "OR exempt_float_li_1 exempt_float_li_2" |
| RULECHECK floating.net.li.R { |
| @ floating.net.li.R: Floating local interconnect nets - nets which do not connect to a defined device |
| OUTPUT "COPY ((bad_li NOT li_fill) NOT exempt_float_li)" |
| } |
| SETLAYER exempt_float_ply_1 = "polyii INSIDE CELL \"text_pcell*\"" |
| SETLAYER exempt_float_ply_2 = "polyii INTERACT (OR critside ccorner)" |
| SETLAYER exempt_float_ply = "OR exempt_float_ply_1 exempt_float_ply_2" |
| RULECHECK floating.net.poly.R { |
| @ floating.net.poly.R: Floating poly nets - nets which do not connect to a defined device |
| OUTPUT "COPY ((bad_ply NOT poly_fill) NOT exempt_float_ply)" |
| } |
| SETLAYER exempt_float_m1_1 = "met1ii INSIDE CELL \"text_pcell*\"" |
| SETLAYER exempt_float_m1_2 = "met1ii INTERACT (OR critside ccorner)" |
| SETLAYER exempt_float_m1 = "OR exempt_float_m1_1 exempt_float_m1_2" |
| RULECHECK floating.net.met1.R { |
| @ floating.net.met1.R: Floating met1 nets - nets which do not connect to a defined device |
| OUTPUT "COPY ((bad_m1 NOT m1_fill) NOT exempt_float_m1)" |
| } |
| SETLAYER exempt_float_m2_1 = "met2ii INSIDE CELL \"text_pcell*\"" |
| SETLAYER exempt_float_m2_2 = "met2ii INTERACT (OR critside ccorner)" |
| SETLAYER exempt_float_m2 = "OR exempt_float_m2_1 exempt_float_m2_2" |
| RULECHECK floating.net.met2.R { |
| @ floating.net.met2.R: Floating met2 nets - nets which do not connect to a defined device |
| OUTPUT "COPY ((bad_m2 NOT m2_fill) NOT exempt_float_m2)" |
| } |
| SETLAYER exempt_float_m3_1 = "met3ii INSIDE CELL \"text_pcell*\"" |
| SETLAYER exempt_float_m3_2 = "met3ii INTERACT (OR critside ccorner)" |
| SETLAYER exempt_float_m3 = "OR exempt_float_m3_1 exempt_float_m3_2" |
| RULECHECK floating.net.met3.R { |
| @ floating.net.met3.R: Floating met3 nets - nets which do not connect to a defined device |
| OUTPUT "COPY ((bad_m3 NOT m3_fill) NOT exempt_float_m3)" |
| } |
| SETLAYER exempt_float_m4_1 = "met4ii INSIDE CELL \"text_pcell*\"" |
| SETLAYER exempt_float_m4_2 = "met4ii INTERACT (OR critside ccorner)" |
| SETLAYER exempt_float_m4 = "OR exempt_float_m4_1 exempt_float_m4_2" |
| RULECHECK floating.net.met4.R { |
| @ floating.net.met4.R: Floating met4 nets - nets which do not connect to a defined device |
| OUTPUT "COPY ((bad_m4 NOT m4_fill) NOT exempt_float_m4)" |
| } |
| |
| SETLAYER exempt_float_m5 = "met5ii INSIDE CELL \"text_pcell*\"" |
| RULECHECK floating.net.met5.R { |
| @ floating.net.met5.R: Floating met5 nets - nets which do not connect to a defined device |
| OUTPUT "COPY ((bad_m5 NOT m5_fill) NOT exempt_float_m5)" |
| } |
| |
| SETLAYER connect_nets = "OR gate nsd psd ptap ntap m1res m2res m3res m4res m5res lires npn pnp diodeID capm cap2m pad" |
| |
| # JAG removed checks for lay_float improper usage as this has been replaced |
| # by using a "fill" purpose for floating layers: |
| #proc check_float {lay_list} { |
| # foreach lay $lay_list { |
| # |
| # set layname ${lay} |
| # if {${lay} == "met1"} { set layname "m1" } |
| # if {${lay} == "met2"} { set layname "m2" } |
| # if {${lay} == "met3"} { set layname "m3" } |
| # if {${lay} == "met4"} { set layname "m4" } |
| # if {${lay} == "met5"} { set layname "m5" } |
| # |
| # RULECHECK ${lay}.FL.2.R { |
| # @ ${lay}.FL.2.R: ${lay}_float or ${lay}_tie not over ${lay} |
| # SETLAYER ${lay}_float_text1 = "EXPAND TEXT \"${layname}_float\" BY (0.005 * 2)" |
| # OUTPUT "SIZE (${lay}_float_text1 NOT INTERACT ${lay}) BY 0.01" |
| # SETLAYER ${lay}_float_text2 = EXPAND TEXT \"${layname}_tie\" BY (0.005 * 2)" |
| # OUTPUT "SIZE (${lay}_float_text2 NOT INTERACT ${lay}) BY 0.01" |
| # } |
| # |
| # RULECHECK ${lay}.FL.3.R { |
| # @ ${lay}.FL.3.R: Layer marked with ${lay}_float not floating |
| # if { $lay == "li" } { |
| # SETLAYER ${lay}_with_float_text = "WITH TEXT ${lay}_i \"${layname}_float\" textdraw" |
| # } else { |
| # SETLAYER ${lay}_with_float_text = "WITH TEXT ${lay}i \"${layname}_float\" textdraw" |
| # } |
| # OUTPUT "${lay}_with_float_text INTERACT connect_nets" |
| # } |
| # RULECHECK ${lay}.FL.4.R { |
| # @ ${lay}.FL.4.R: Layer ${lay} marked with both ${lay}_float and ${lay}_tie |
| # if { $lay == "li" } { |
| # SETLAYER ${lay}_with_float_text = "WITH TEXT ${lay}_i \"${layname}_float\" textdraw" |
| # SETLAYER ${lay}_with_tie_text = "WITH TEXT ${lay}_i \"${layname}_tie\" textdraw" |
| # } else { |
| # SETLAYER ${lay}_with_float_text = "WITH TEXT ${lay}i \"${layname}_float\" textdraw" |
| # SETLAYER ${lay}_with_tie_text = "WITH TEXT ${lay}i \"${layname}_tie\" textdraw" |
| # } |
| # OUTPUT "(${lay} INTERACT ${lay}_with_float_text) AND (${lay} INTERACT ${lay}_with_tie_text)" |
| # } |
| # } |
| #} |
| # |
| #check_float [list "li" "poly" "met1" "met2" "met3" "met4" "met5"] |
| |
| RULECHECK floating.net.ptap.R { |
| @ floating.net.ptap.R: possible floating p+ tap - p+ tap not connected to pad |
| OUTPUT "NET AREA RATIO ptap pad == 0" |
| } |
| |
| RULECHECK floating.net.ntap.R { |
| @ floating.net.ntap.R: possible floating n+ tap - n+ tap not connected to pad |
| OUTPUT "NET AREA RATIO ntap pad == 0" |
| } |
| |
| RULECHECK floating.net.pwell.R { |
| @ floating.net.pwell.R: substrate not conected by ptap |
| OUTPUT "(pwell NOT INTERACT (HOLES pwbm INNER)) NOT ENCLOSE ptap" |
| } |
| |
| RULECHECK floating.net.ptub.R { |
| @ floating.net.ptub.R: isolated substrate not connected by ptap |
| OUTPUT "ptub NOT ENCLOSE ptap" |
| } |
| |
| RULECHECK floating.net.localsub.R { |
| @ floating.net.localsub.R: local substrate (areaid:substrateCut) not connected by ptap |
| OUTPUT "localSub NOT ENCLOSE ptap" |
| } |
| |
| verbatim { |
| #ENDIF |
| } |
| |
| verbatim { |
| |
| // Begin illegal device checks |
| |
| #IFNDEF SKIP_ILLEGAL_DEVICE_CHECKS |
| |
| // 4/14/21 SWT changed to permit active under pad: |
| skip_pad = COPY 7000 |
| skip_res = COPY 7001 |
| skip_dnw = COPY 7002 |
| |
| // NMOS: |
| |
| } |
| |
| SETLAYER mos_diff = "diffi NOT (OR pnp npn ENID)" |
| SETLAYER nmos_gate = "(mos_diff AND polyi) NOT nwell" |
| SETLAYER nmos_sd = "(diffi INTERACT nmos_gate) NOT nmos_gate" |
| SETLAYER nmos_1 = "nmos_gate TOUCH nmos_sd == 2" |
| SETLAYER nmos = "nmos_1 NOT (OR ESDID thkox lvtn)" |
| #-------------------------------- |
| proc illegal_nmos {lay_list} { |
| set n 1 |
| foreach lay $lay_list { |
| set lname ${lay} |
| if {${lay} == "COREID"} { set lname "areaid:core" } |
| if {${lay} == "ENID"} { set lname "areaid:extendedDrain" } |
| if {${lay} == "SEALID"} { set lname "areaid:seal" } |
| if {${lay} == "LVID"} { set lname "areaid:lvNative" } |
| if {${lay} == "ESDID"} { set lname "areaid:esd" } |
| if {${lay} == "DiodeID"} { set lname "areaid:diode" } |
| if {${lay} == "PHdiodeID"} { set lname "areaid:photo" } |
| if {${lay} == "polyModel"} { set lname "poly:model" } |
| if {${lay} == "pwres"} { set lname "pwell:res" } |
| if {${lay} == "diffres"} { set lname "diff:res" } |
| if {${lay} == "polyres"} { set lname "poly:res" } |
| if {${lay} == "lires"} { set lname "li:res" } |
| if {${lay} == "m1res"} { set lname "met1:res" } |
| if {${lay} == "m2res"} { set lname "met2:res" } |
| if {${lay} == "m3res"} { set lname "met3:res" } |
| if {${lay} == "m4res"} { set lname "met4:res" } |
| if {${lay} == "m5res"} { set lname "met5:res" } |
| |
| RULECHECK nmos.OVL.${n} { |
| @ nmos.OVL.${n}: Illegal nmos device: nmos must not overlap ${lname} |
| OUTPUT "nmos AND ${lay}" |
| } |
| incr n |
| } |
| } |
| |
| illegal_nmos [list "pwbm" "pwde" "nwell" "hvtp" "lvtn" "tunm" "thkox" "rpm" "rrpm" "urpm" "ldntm" "npc" "psdm" "nsm" "skip_pad" "fuse" "diffres" "pwres" "polyres" "lires" "skip_res" "skip_res" "skip_res" "skip_res" "skip_res" "LVID" "pnp" "npn" "DiodeID" "PHdiodeID" "COREID" "ENID" "SEALID" "v5" "v12" "v20" "polyModel"] |
| |
| ### sonos-e bit cells (not supported yet but may be in legacy data) are in: |
| ### 1 - COREID |
| ### 2 - ldntm |
| ### 3 - tunm |
| ### so for this check these are removed: |
| SETLAYER exempt_sonos = "((nmos_1 AND COREID) AND ldntm) AND tunm" |
| SETLAYER nmos_lvt = "(((nmos_1 AND lvtn) NOT LVID) NOT thkox) NOT exempt_sonos" |
| |
| #-------------------------------- |
| proc illegal_nmos_lvt {lay_list} { |
| set n 1 |
| foreach lay $lay_list { |
| set lname ${lay} |
| if {${lay} == "COREID"} { set lname "areaid:core" } |
| if {${lay} == "ENID"} { set lname "areaid:extendedDrain" } |
| if {${lay} == "SEALID"} { set lname "areaid:seal" } |
| if {${lay} == "LVID"} { set lname "areaid:lvNative" } |
| if {${lay} == "ESDID"} { set lname "areaid:esd" } |
| if {${lay} == "DiodeID"} { set lname "areaid:diode" } |
| if {${lay} == "PHdiodeID"} { set lname "areaid:photo" } |
| if {${lay} == "polyModel"} { set lname "poly:model" } |
| if {${lay} == "pwres"} { set lname "pwell:res" } |
| if {${lay} == "diffres"} { set lname "diff:res" } |
| if {${lay} == "polyres"} { set lname "poly:res" } |
| if {${lay} == "lires"} { set lname "li:res" } |
| if {${lay} == "m1res"} { set lname "met1:res" } |
| if {${lay} == "m2res"} { set lname "met2:res" } |
| if {${lay} == "m3res"} { set lname "met3:res" } |
| if {${lay} == "m4res"} { set lname "met4:res" } |
| if {${lay} == "m5res"} { set lname "met5:res" } |
| RULECHECK nmos_lvt.OVL.${n} { |
| @ nmos_lvt.OVL.${n}: Illegal nmos lvt device: nmos_lvt must not overlap ${lname} |
| OUTPUT "nmos_lvt AND ${lay}" |
| } |
| incr n |
| } |
| } |
| |
| illegal_nmos_lvt [list "pwbm" "pwde" "nwell" "hvtp" "tunm" "thkox" "rpm" "rrpm" "urpm" "ldntm" "npc" "psdm" "nsm" "skip_pad" "fuse" "diffres" "pwres" "polyres" "lires" "skip_res" "skip_res" "skip_res" "skip_res" "skip_res" "LVID" "pnp" "npn" "DiodeID" "PHdiodeID" "COREID" "ESDID" "ENID" "SEALID" "v5" "v12" "v20" "polyModel"] |
| |
| SETLAYER nmos_v5 = "(nmos_1 AND (v5 AND thkox)) NOT (OR LVID lvtn ESDID)" |
| #-------------------------------- |
| proc illegal_nmos_v5 {lay_list} { |
| set n 1 |
| foreach lay $lay_list { |
| set lname ${lay} |
| if {${lay} == "COREID"} { set lname "areaid:core" } |
| if {${lay} == "ENID"} { set lname "areaid:extendedDrain" } |
| if {${lay} == "SEALID"} { set lname "areaid:seal" } |
| if {${lay} == "LVID"} { set lname "areaid:lvNative" } |
| if {${lay} == "ESDID"} { set lname "areaid:esd" } |
| if {${lay} == "DiodeID"} { set lname "areaid:diode" } |
| if {${lay} == "PHdiodeID"} { set lname "areaid:photo" } |
| if {${lay} == "polyModel"} { set lname "poly:model" } |
| if {${lay} == "pwres"} { set lname "pwell:res" } |
| if {${lay} == "diffres"} { set lname "diff:res" } |
| if {${lay} == "polyres"} { set lname "poly:res" } |
| if {${lay} == "lires"} { set lname "li:res" } |
| if {${lay} == "m1res"} { set lname "met1:res" } |
| if {${lay} == "m2res"} { set lname "met2:res" } |
| if {${lay} == "m3res"} { set lname "met3:res" } |
| if {${lay} == "m4res"} { set lname "met4:res" } |
| if {${lay} == "m5res"} { set lname "met5:res" } |
| |
| RULECHECK nmos_v5.OVL.${n} { |
| @ nmos_v5.OVL.${n}: Illegal nmos_v5 device: nmos_v5 must not overlap ${lname} |
| OUTPUT "nmos_v5 AND ${lay}" |
| } |
| incr n |
| } |
| } |
| |
| illegal_nmos_v5 [list "pwbm" "pwde" "nwell" "hvtp" "lvtn" "tunm" "rpm" "rrpm" "urpm" "ldntm" "npc" "psdm" "nsm" "skip_pad" "fuse" "diffres" "pwres" "polyres" "lires" "skip_res" "skip_res" "skip_res" "skip_res" "skip_res" "LVID" "pnp" "npn" "DiodeID" "PHdiodeID" "COREID" "ENID" "SEALID" "v12" "v20" "polyModel"] |
| |
| SETLAYER nmos_nat_v3 = "(nmos_1 AND ((v5 AND thkox) AND LVID)) AND lvtn" |
| #-------------------------------- |
| proc illegal_nmos_nat_v3 {lay_list} { |
| set n 1 |
| foreach lay $lay_list { |
| set lname ${lay} |
| if {${lay} == "COREID"} { set lname "areaid:core" } |
| if {${lay} == "ENID"} { set lname "areaid:extendedDrain" } |
| if {${lay} == "SEALID"} { set lname "areaid:seal" } |
| if {${lay} == "LVID"} { set lname "areaid:lvNative" } |
| if {${lay} == "ESDID"} { set lname "areaid:esd" } |
| if {${lay} == "DiodeID"} { set lname "areaid:diode" } |
| if {${lay} == "PHdiodeID"} { set lname "areaid:photo" } |
| if {${lay} == "polyModel"} { set lname "poly:model" } |
| if {${lay} == "pwres"} { set lname "pwell:res" } |
| if {${lay} == "diffres"} { set lname "diff:res" } |
| if {${lay} == "polyres"} { set lname "poly:res" } |
| if {${lay} == "lires"} { set lname "li:res" } |
| if {${lay} == "m1res"} { set lname "met1:res" } |
| if {${lay} == "m2res"} { set lname "met2:res" } |
| if {${lay} == "m3res"} { set lname "met3:res" } |
| if {${lay} == "m4res"} { set lname "met4:res" } |
| if {${lay} == "m5res"} { set lname "met5:res" } |
| |
| RULECHECK nmos_nat_v3.OVL.${n} { |
| @ nmos_nat_v3.OVL.${n}: Illegal nmos_nat_v3 device: nmos_nat_v3 must not overlap ${lname} |
| OUTPUT "nmos_nat_v3 AND ${lay}" |
| } |
| incr n |
| } |
| } |
| |
| illegal_nmos_nat_v3 [list "pwbm" "pwde" "nwell" "hvtp" "tunm" "rpm" "rrpm" "urpm" "ldntm" "npc" "psdm" "nsm" "skip_pad" "fuse" "diffres" "pwres" "polyres" "lires" "skip_res" "skip_res" "skip_res" "skip_res" "skip_res" "pnp" "npn" "DiodeID" "PHdiodeID" "COREID" "ENID" "SEALID" "v12" "v20" "ESDID" "polyModel"] |
| |
| SETLAYER nmos_nat_v5 = "((nmos_1 AND ((v5 AND thkox) NOT LVID)) AND lvtn) NOT ESDID" |
| #-------------------------------- |
| proc illegal_nmos_nat_v5 {lay_list} { |
| set n 1 |
| foreach lay $lay_list { |
| set lname ${lay} |
| if {${lay} == "COREID"} { set lname "areaid:core" } |
| if {${lay} == "ENID"} { set lname "areaid:extendedDrain" } |
| if {${lay} == "SEALID"} { set lname "areaid:seal" } |
| if {${lay} == "LVID"} { set lname "areaid:lvNative" } |
| if {${lay} == "ESDID"} { set lname "areaid:esd" } |
| if {${lay} == "DiodeID"} { set lname "areaid:diode" } |
| if {${lay} == "PHdiodeID"} { set lname "areaid:photo" } |
| if {${lay} == "polyModel"} { set lname "poly:model" } |
| if {${lay} == "pwres"} { set lname "pwell:res" } |
| if {${lay} == "diffres"} { set lname "diff:res" } |
| if {${lay} == "polyres"} { set lname "poly:res" } |
| if {${lay} == "lires"} { set lname "li:res" } |
| if {${lay} == "m1res"} { set lname "met1:res" } |
| if {${lay} == "m2res"} { set lname "met2:res" } |
| if {${lay} == "m3res"} { set lname "met3:res" } |
| if {${lay} == "m4res"} { set lname "met4:res" } |
| if {${lay} == "m5res"} { set lname "met5:res" } |
| |
| RULECHECK nmos_nat_v5.OVL.${n} { |
| @ nmos_nat_v5.OVL.${n}: Illegal nmos_nat_v5 device: nmos_nat_v5 must not overlap ${lname} |
| OUTPUT "nmos_nat_v5 AND ${lay}" |
| } |
| incr n |
| } |
| } |
| |
| illegal_nmos_nat_v5 [list "pwbm" "pwde" "nwell" "hvtp" "tunm" "rpm" "rrpm" "urpm" "ldntm" "npc" "psdm" "nsm" "skip_pad" "fuse" "diffres" "pwres" "polyres" "lires" "skip_res" "skip_res" "skip_res" "skip_res" "skip_res" "pnp" "npn" "DiodeID" "PHdiodeID" "COREID" "ENID" "SEALID" "v12" "v20" "ESDID" "polyModel"] |
| |
| SETLAYER nmos_de_v12 = "((((gate and nsdm) AND v12) AND ENID) NOT nwell) AND thkox" |
| #-------------------------------- |
| proc illegal_nmos_de_v12 {lay_list} { |
| set n 1 |
| foreach lay $lay_list { |
| set lname ${lay} |
| if {${lay} == "COREID"} { set lname "areaid:core" } |
| if {${lay} == "ENID"} { set lname "areaid:extendedDrain" } |
| if {${lay} == "SEALID"} { set lname "areaid:seal" } |
| if {${lay} == "LVID"} { set lname "areaid:lvNative" } |
| if {${lay} == "ESDID"} { set lname "areaid:esd" } |
| if {${lay} == "DiodeID"} { set lname "areaid:diode" } |
| if {${lay} == "PHdiodeID"} { set lname "areaid:photo" } |
| if {${lay} == "polyModel"} { set lname "poly:model" } |
| if {${lay} == "pwres"} { set lname "pwell:res" } |
| if {${lay} == "diffres"} { set lname "diff:res" } |
| if {${lay} == "polyres"} { set lname "poly:res" } |
| if {${lay} == "lires"} { set lname "li:res" } |
| if {${lay} == "m1res"} { set lname "met1:res" } |
| if {${lay} == "m2res"} { set lname "met2:res" } |
| if {${lay} == "m3res"} { set lname "met3:res" } |
| if {${lay} == "m4res"} { set lname "met4:res" } |
| if {${lay} == "m5res"} { set lname "met5:res" } |
| |
| RULECHECK nmos_de_v12.OVL.${n} { |
| @ nmos_de_v12.OVL.${n}: Illegal nmos_de_v12 device: nmos_de_v12 must not overlap ${lname} |
| OUTPUT "nmos_de_v12 AND ${lay}" |
| } |
| incr n |
| } |
| } |
| |
| illegal_nmos_de_v12 [list "pwbm" "pwde" "hvtp" "lvtn" "tunm" "rpm" "rrpm" "urpm" "ldntm" "npc" "psdm" "nsm" "skip_pad" "fuse" "diffres" "pwres" "polyres" "lires" "skip_res" "skip_res" "skip_res" "skip_res" "skip_res" "LVID" "pnp" "npn" "DiodeID" "PHdiodeID" "COREID" "SEALID" "v5" "v20" "dnwell" "ESDID" "polyModel"] |
| |
| SETLAYER nmos_de_v20 = "ngate_v20 NOT (poly INTERACT (OR ngate_v20_nat ngate_v20_zvt ngate_v20_iso_rec))" |
| #-------------------------------- |
| proc illegal_nmos_de_v20 {lay_list} { |
| set n 1 |
| foreach lay $lay_list { |
| set lname ${lay} |
| if {${lay} == "COREID"} { set lname "areaid:core" } |
| if {${lay} == "ENID"} { set lname "areaid:extendedDrain" } |
| if {${lay} == "SEALID"} { set lname "areaid:seal" } |
| if {${lay} == "LVID"} { set lname "areaid:lvNative" } |
| if {${lay} == "ESDID"} { set lname "areaid:esd" } |
| if {${lay} == "DiodeID"} { set lname "areaid:diode" } |
| if {${lay} == "PHdiodeID"} { set lname "areaid:photo" } |
| if {${lay} == "polyModel"} { set lname "poly:model" } |
| if {${lay} == "pwres"} { set lname "pwell:res" } |
| if {${lay} == "diffres"} { set lname "diff:res" } |
| if {${lay} == "polyres"} { set lname "poly:res" } |
| if {${lay} == "lires"} { set lname "li:res" } |
| if {${lay} == "m1res"} { set lname "met1:res" } |
| if {${lay} == "m2res"} { set lname "met2:res" } |
| if {${lay} == "m3res"} { set lname "met3:res" } |
| if {${lay} == "m4res"} { set lname "met4:res" } |
| if {${lay} == "m5res"} { set lname "met5:res" } |
| |
| RULECHECK nmos_de_v20.OVL.${n} { |
| @ nmos_de_v20.OVL.${n}: Illegal nmos_de_v20 device: nmos_de_v20 must not overlap ${lname} |
| OUTPUT "nmos_de_v20 AND ${lay}" |
| } |
| incr n |
| } |
| } |
| |
| illegal_nmos_de_v20 [list "pwde" "hvtp" "tunm" "rpm" "rrpm" "urpm" "ldntm" "npc" "psdm" "nsm" "skip_pad" "fuse" "diffres" "pwres" "polyres" "lires" "skip_res" "skip_res" "skip_res" "skip_res" "skip_res" "LVID" "pnp" "npn" "DiodeID" "PHdiodeID" "COREID" "ESDID" "SEALID" "v5" "v12" "polyModel"] |
| |
| SETLAYER nmos_de_iso_v20 = "(((((gate and nsdm) AND v20) AND ENID) NOT nwell) AND thkox) INTERACT (HOLES pwbm)" |
| #-------------------------------- |
| proc illegal_nmos_de_iso_v20 {lay_list} { |
| set n 1 |
| foreach lay $lay_list { |
| set lname ${lay} |
| if {${lay} == "COREID"} { set lname "areaid:core" } |
| if {${lay} == "ENID"} { set lname "areaid:extendedDrain" } |
| if {${lay} == "SEALID"} { set lname "areaid:seal" } |
| if {${lay} == "LVID"} { set lname "areaid:lvNative" } |
| if {${lay} == "ESDID"} { set lname "areaid:esd" } |
| if {${lay} == "DiodeID"} { set lname "areaid:diode" } |
| if {${lay} == "PHdiodeID"} { set lname "areaid:photo" } |
| if {${lay} == "polyModel"} { set lname "poly:model" } |
| if {${lay} == "pwres"} { set lname "pwell:res" } |
| if {${lay} == "diffres"} { set lname "diff:res" } |
| if {${lay} == "polyres"} { set lname "poly:res" } |
| if {${lay} == "lires"} { set lname "li:res" } |
| if {${lay} == "m1res"} { set lname "met1:res" } |
| if {${lay} == "m2res"} { set lname "met2:res" } |
| if {${lay} == "m3res"} { set lname "met3:res" } |
| if {${lay} == "m4res"} { set lname "met4:res" } |
| if {${lay} == "m5res"} { set lname "met5:res" } |
| |
| RULECHECK nmos_de_iso_v20.OVL.${n} { |
| @ nmos_de_iso_v20.OVL.${n}: Illegal nmos_de_iso_v20 device: nmos_de_iso_v20 must not overlap ${lname} |
| OUTPUT "nmos_de_iso_v20 AND ${lay}" |
| } |
| incr n |
| } |
| } |
| |
| illegal_nmos_de_iso_v20 [list "pwde" "hvtp" "tunm" "rpm" "rrpm" "urpm" "ldntm" "npc" "psdm" "nsm" "skip_pad" "fuse" "diffres" "pwres" "polyres" "lires" "skip_res" "skip_res" "skip_res" "skip_res" "skip_res" "LVID" "pnp" "npn" "DiodeID" "PHdiodeID" "COREID" "ESDID" "SEALID" "v5" "v12" "polyModel"] |
| |
| SETLAYER nmos_de_nat_v20 = "((lvtn ENCLOSE nsdm) AND ngate_v20) NOT pwbm" |
| #-------------------------------- |
| proc illegal_nmos_de_nat_v20 {lay_list} { |
| set n 1 |
| foreach lay $lay_list { |
| set lname ${lay} |
| if {${lay} == "COREID"} { set lname "areaid:core" } |
| if {${lay} == "ENID"} { set lname "areaid:extendedDrain" } |
| if {${lay} == "SEALID"} { set lname "areaid:seal" } |
| if {${lay} == "LVID"} { set lname "areaid:lvNative" } |
| if {${lay} == "ESDID"} { set lname "areaid:esd" } |
| if {${lay} == "DiodeID"} { set lname "areaid:diode" } |
| if {${lay} == "PHdiodeID"} { set lname "areaid:photo" } |
| if {${lay} == "polyModel"} { set lname "poly:model" } |
| if {${lay} == "pwres"} { set lname "pwell:res" } |
| if {${lay} == "diffres"} { set lname "diff:res" } |
| if {${lay} == "polyres"} { set lname "poly:res" } |
| if {${lay} == "lires"} { set lname "li:res" } |
| if {${lay} == "m1res"} { set lname "met1:res" } |
| if {${lay} == "m2res"} { set lname "met2:res" } |
| if {${lay} == "m3res"} { set lname "met3:res" } |
| if {${lay} == "m4res"} { set lname "met4:res" } |
| if {${lay} == "m5res"} { set lname "met5:res" } |
| |
| RULECHECK nmos_de_nat_v20.OVL.${n} { |
| @ nmos_de_nat_v20.OVL.${n}: Illegal nmos_de_nat_v20 device: nmos_de_nat_v20 must not overlap ${lname} |
| OUTPUT "nmos_de_nat_v20 AND ${lay}" |
| } |
| incr n |
| } |
| } |
| |
| illegal_nmos_de_nat_v20 [list "pwde" "hvtp" "tunm" "rpm" "rrpm" "urpm" "ldntm" "npc" "psdm" "nsm" "skip_pad" "fuse" "diffres" "pwres" "polyres" "lires" "skip_res" "skip_res" "skip_res" "skip_res" "skip_res" "LVID" "pnp" "npn" "DiodeID" "PHdiodeID" "COREID" "ESDID" "SEALID" "v5" "v12" "polyModel"] |
| |
| SETLAYER nmos_de_zvt_v20 = "(((lvtn CUT nsdm) NOT (lvtn ENCLOSE nsdm)) AND ngate_v20) NOT (OR ngate_v20_iso_rec ngate_v20_nat)" |
| #-------------------------------- |
| proc illegal_nmos_de_zvt_v20 {lay_list} { |
| set n 1 |
| foreach lay $lay_list { |
| set lname ${lay} |
| if {${lay} == "COREID"} { set lname "areaid:core" } |
| if {${lay} == "ENID"} { set lname "areaid:extendedDrain" } |
| if {${lay} == "SEALID"} { set lname "areaid:seal" } |
| if {${lay} == "LVID"} { set lname "areaid:lvNative" } |
| if {${lay} == "ESDID"} { set lname "areaid:esd" } |
| if {${lay} == "DiodeID"} { set lname "areaid:diode" } |
| if {${lay} == "PHdiodeID"} { set lname "areaid:photo" } |
| if {${lay} == "polyModel"} { set lname "poly:model" } |
| if {${lay} == "pwres"} { set lname "pwell:res" } |
| if {${lay} == "diffres"} { set lname "diff:res" } |
| if {${lay} == "polyres"} { set lname "poly:res" } |
| if {${lay} == "lires"} { set lname "li:res" } |
| if {${lay} == "m1res"} { set lname "met1:res" } |
| if {${lay} == "m2res"} { set lname "met2:res" } |
| if {${lay} == "m3res"} { set lname "met3:res" } |
| if {${lay} == "m4res"} { set lname "met4:res" } |
| if {${lay} == "m5res"} { set lname "met5:res" } |
| |
| RULECHECK nmos_de_zvt_v20.OVL.${n} { |
| @ nmos_de_zvt_v20.OVL.${n}: Illegal nmos_de_zvt_v20 device: nmos_de_zvt_v20 must not overlap ${lname} |
| OUTPUT "nmos_de_zvt_v20 AND ${lay}" |
| } |
| incr n |
| } |
| } |
| |
| illegal_nmos_de_zvt_v20 [list "pwde" "hvtp" "tunm" "rpm" "rrpm" "urpm" "ldntm" "npc" "psdm" "nsm" "skip_pad" "fuse" "diffres" "pwres" "polyres" "lires" "skip_res" "skip_res" "skip_res" "skip_res" "skip_res" "LVID" "pnp" "npn" "DiodeID" "PHdiodeID" "COREID" "ESDID" "SEALID" "v5" "v12" "polyModel"] |
| |
| verbatim { |
| |
| // PMOS: |
| |
| } |
| |
| SETLAYER pmos_gate = "((mos_diff AND polyi) AND nwell) NOT ENID" |
| SETLAYER pmos_sd = "(diffi INTERACT pmos_gate) NOT pmos_gate" |
| SETLAYER pmos_1 = "pmos_gate TOUCH pmos_sd == 2" |
| SETLAYER pmos = "(pmos_1 NOT thkox) NOT lvtn" |
| #-------------------------------- |
| proc illegal_lv_pmos {lay_list} { |
| set n 1 |
| foreach lay $lay_list { |
| set lname ${lay} |
| if {${lay} == "COREID"} { set lname "areaid:core" } |
| if {${lay} == "ENID"} { set lname "areaid:extendedDrain" } |
| if {${lay} == "SEALID"} { set lname "areaid:seal" } |
| if {${lay} == "LVID"} { set lname "areaid:lvNative" } |
| if {${lay} == "ESDID"} { set lname "areaid:esd" } |
| if {${lay} == "DiodeID"} { set lname "areaid:diode" } |
| if {${lay} == "PHdiodeID"} { set lname "areaid:photo" } |
| if {${lay} == "polyModel"} { set lname "poly:model" } |
| if {${lay} == "pwres"} { set lname "pwell:res" } |
| if {${lay} == "diffres"} { set lname "diff:res" } |
| if {${lay} == "polyres"} { set lname "poly:res" } |
| if {${lay} == "lires"} { set lname "li:res" } |
| if {${lay} == "m1res"} { set lname "met1:res" } |
| if {${lay} == "m2res"} { set lname "met2:res" } |
| if {${lay} == "m3res"} { set lname "met3:res" } |
| if {${lay} == "m4res"} { set lname "met4:res" } |
| if {${lay} == "m5res"} { set lname "met5:res" } |
| |
| RULECHECK pmos.OVL.${n} { |
| @ pmos.OVL.${n}: Illegal low voltage pmos device: pmos must not overlap ${lname} |
| OUTPUT "pmos AND ${lay}" |
| } |
| incr n |
| } |
| } |
| |
| illegal_lv_pmos [list "pwbm" "pwde" "lvtn" "tunm" "thkox" "rpm" "rrpm" "urpm" "ldntm" "npc" "nsdm" "nsm" "skip_pad" "fuse" "diffres" "pwres" "polyres" "lires" "skip_res" "skip_res" "skip_res" "skip_res" "skip_res" "LVID" "pnp" "npn" "DiodeID" "PHdiodeID" "COREID" "SEALID" "v5" "v12" "v20" "ENID" "polyModel"] |
| |
| SETLAYER pmos_lvt = "pmos_1 AND lvtn" |
| #-------------------------------- |
| proc illegal_pmos_lvt {lay_list} { |
| set n 1 |
| foreach lay $lay_list { |
| set lname ${lay} |
| if {${lay} == "COREID"} { set lname "areaid:core" } |
| if {${lay} == "ENID"} { set lname "areaid:extendedDrain" } |
| if {${lay} == "SEALID"} { set lname "areaid:seal" } |
| if {${lay} == "LVID"} { set lname "areaid:lvNative" } |
| if {${lay} == "ESDID"} { set lname "areaid:esd" } |
| if {${lay} == "DiodeID"} { set lname "areaid:diode" } |
| if {${lay} == "PHdiodeID"} { set lname "areaid:photo" } |
| if {${lay} == "polyModel"} { set lname "poly:model" } |
| if {${lay} == "pwres"} { set lname "pwell:res" } |
| if {${lay} == "diffres"} { set lname "diff:res" } |
| if {${lay} == "polyres"} { set lname "poly:res" } |
| if {${lay} == "lires"} { set lname "li:res" } |
| if {${lay} == "m1res"} { set lname "met1:res" } |
| if {${lay} == "m2res"} { set lname "met2:res" } |
| if {${lay} == "m3res"} { set lname "met3:res" } |
| if {${lay} == "m4res"} { set lname "met4:res" } |
| if {${lay} == "m5res"} { set lname "met5:res" } |
| |
| RULECHECK pmos_lvt.OVL.${n} { |
| @ pmos_lvt.OVL.${n}: Illegal pmos_lvt device: pmos_lvt must not overlap ${lname} |
| OUTPUT "pmos_lvt AND ${lay}" |
| } |
| incr n |
| } |
| } |
| |
| illegal_pmos_lvt [list "pwbm" "pwde" "tunm" "thkox" "rpm" "rrpm" "urpm" "ldntm" "npc" "nsdm" "nsm" "skip_pad" "fuse" "diffres" "pwres" "polyres" "lires" "skip_res" "skip_res" "skip_res" "skip_res" "skip_res" "LVID" "pnp" "npn" "DiodeID" "PHdiodeID" "COREID" "ESDID" "SEALID" "v5" "v12" "v20" "hvtp" "ENID" "polyModel"] |
| |
| SETLAYER pmos_hvt = "pmos_1 AND hvtp" |
| #-------------------------------- |
| proc illegal_pmos_hvt {lay_list} { |
| set n 1 |
| foreach lay $lay_list { |
| set lname ${lay} |
| if {${lay} == "COREID"} { set lname "areaid:core" } |
| if {${lay} == "ENID"} { set lname "areaid:extendedDrain" } |
| if {${lay} == "SEALID"} { set lname "areaid:seal" } |
| if {${lay} == "LVID"} { set lname "areaid:lvNative" } |
| if {${lay} == "ESDID"} { set lname "areaid:esd" } |
| if {${lay} == "DiodeID"} { set lname "areaid:diode" } |
| if {${lay} == "PHdiodeID"} { set lname "areaid:photo" } |
| if {${lay} == "polyModel"} { set lname "poly:model" } |
| if {${lay} == "pwres"} { set lname "pwell:res" } |
| if {${lay} == "diffres"} { set lname "diff:res" } |
| if {${lay} == "polyres"} { set lname "poly:res" } |
| if {${lay} == "lires"} { set lname "li:res" } |
| if {${lay} == "m1res"} { set lname "met1:res" } |
| if {${lay} == "m2res"} { set lname "met2:res" } |
| if {${lay} == "m3res"} { set lname "met3:res" } |
| if {${lay} == "m4res"} { set lname "met4:res" } |
| if {${lay} == "m5res"} { set lname "met5:res" } |
| |
| RULECHECK pmos_hvt.OVL.${n} { |
| @ pmos_hvt.OVL.${n}: Illegal pmos_hvt device: pmos_hvt must not overlap ${lname} |
| OUTPUT "pmos_hvt AND ${lay}" |
| } |
| incr n |
| } |
| } |
| |
| illegal_pmos_hvt [list "pwbm" "pwde" "tunm" "thkox" "rpm" "rrpm" "urpm" "ldntm" "npc" "nsdm" "nsm" "skip_pad" "fuse" "diffres" "pwres" "polyres" "lires" "skip_res" "skip_res" "skip_res" "skip_res" "skip_res" "LVID" "pnp" "npn" "DiodeID" "PHdiodeID" "COREID" "ESDID" "SEALID" "v5" "v12" "v20" "ENID" "polyModel"] |
| |
| SETLAYER pmos_v5 = "((pmos_1 AND v5) AND thkox) NOT ESDID" |
| #-------------------------------- |
| proc illegal_pmos_v5 {lay_list} { |
| set n 1 |
| foreach lay $lay_list { |
| set lname ${lay} |
| if {${lay} == "COREID"} { set lname "areaid:core" } |
| if {${lay} == "ENID"} { set lname "areaid:extendedDrain" } |
| if {${lay} == "SEALID"} { set lname "areaid:seal" } |
| if {${lay} == "LVID"} { set lname "areaid:lvNative" } |
| if {${lay} == "ESDID"} { set lname "areaid:esd" } |
| if {${lay} == "DiodeID"} { set lname "areaid:diode" } |
| if {${lay} == "PHdiodeID"} { set lname "areaid:photo" } |
| if {${lay} == "polyModel"} { set lname "poly:model" } |
| if {${lay} == "pwres"} { set lname "pwell:res" } |
| if {${lay} == "diffres"} { set lname "diff:res" } |
| if {${lay} == "polyres"} { set lname "poly:res" } |
| if {${lay} == "lires"} { set lname "li:res" } |
| if {${lay} == "m1res"} { set lname "met1:res" } |
| if {${lay} == "m2res"} { set lname "met2:res" } |
| if {${lay} == "m3res"} { set lname "met3:res" } |
| if {${lay} == "m4res"} { set lname "met4:res" } |
| if {${lay} == "m5res"} { set lname "met5:res" } |
| |
| RULECHECK pmos_v5.OVL.${n} { |
| @ pmos_v5.OVL.${n}: Illegal pmos_v5 device: pmos_v5 must not overlap ${lname} |
| OUTPUT "pmos_v5 AND ${lay}" |
| } |
| incr n |
| } |
| } |
| |
| illegal_pmos_v5 [list "pwbm" "pwde" "hvtp" "lvtn" "tunm" "rpm" "rrpm" "urpm" "ldntm" "npc" "nsdm" "nsm" "skip_pad" "fuse" "diffres" "pwres" "polyres" "lires" "skip_res" "skip_res" "skip_res" "skip_res" "skip_res" "LVID" "pnp" "npn" "DiodeID" "PHdiodeID" "COREID" "SEALID" "v12" "v20" "ENID" "polyModel"] |
| |
| SETLAYER pmos_de_v12 = "((gate and psdm) AND v12) AND ENID" |
| |
| #-------------------------------- |
| proc illegal_pmos_de_v12 {lay_list} { |
| set n 1 |
| foreach lay $lay_list { |
| set lname ${lay} |
| if {${lay} == "COREID"} { set lname "areaid:core" } |
| if {${lay} == "ENID"} { set lname "areaid:extendedDrain" } |
| if {${lay} == "SEALID"} { set lname "areaid:seal" } |
| if {${lay} == "LVID"} { set lname "areaid:lvNative" } |
| if {${lay} == "ESDID"} { set lname "areaid:esd" } |
| if {${lay} == "DiodeID"} { set lname "areaid:diode" } |
| if {${lay} == "PHdiodeID"} { set lname "areaid:photo" } |
| if {${lay} == "polyModel"} { set lname "poly:model" } |
| if {${lay} == "pwres"} { set lname "pwell:res" } |
| if {${lay} == "diffres"} { set lname "diff:res" } |
| if {${lay} == "polyres"} { set lname "poly:res" } |
| if {${lay} == "lires"} { set lname "li:res" } |
| if {${lay} == "m1res"} { set lname "met1:res" } |
| if {${lay} == "m2res"} { set lname "met2:res" } |
| if {${lay} == "m3res"} { set lname "met3:res" } |
| if {${lay} == "m4res"} { set lname "met4:res" } |
| if {${lay} == "m5res"} { set lname "met5:res" } |
| |
| RULECHECK pmos_de_v12.OVL.${n} { |
| @ pmos_de_v12.OVL.${n}: Illegal pmos_de_v12 device: pmos_de_v12 must not overlap ${lname} |
| OUTPUT "pmos_de_v12 AND ${lay}" |
| } |
| incr n |
| } |
| } |
| |
| illegal_pmos_de_v12 [list "pwbm" "pwde" "hvtp" "lvtn" "tunm" "rpm" "rrpm" "urpm" "ldntm" "npc" "nsdm" "nsm" "skip_pad" "fuse" "diffres" "pwres" "polyres" "lires" "skip_res" "skip_res" "skip_res" "skip_res" "skip_res" "LVID" "pnp" "npn" "DiodeID" "PHdiodeID" "COREID" "ESDID" "SEALID" "v5" "v20" "polyModel"] |
| |
| SETLAYER pmos_de_v20 = "((gate and psdm) AND v20) AND ENID" |
| |
| #-------------------------------- |
| proc illegal_pmos_de_v20 {lay_list} { |
| set n 1 |
| foreach lay $lay_list { |
| set lname ${lay} |
| if {${lay} == "COREID"} { set lname "areaid:core" } |
| if {${lay} == "ENID"} { set lname "areaid:extendedDrain" } |
| if {${lay} == "SEALID"} { set lname "areaid:seal" } |
| if {${lay} == "LVID"} { set lname "areaid:lvNative" } |
| if {${lay} == "ESDID"} { set lname "areaid:esd" } |
| if {${lay} == "DiodeID"} { set lname "areaid:diode" } |
| if {${lay} == "PHdiodeID"} { set lname "areaid:photo" } |
| if {${lay} == "polyModel"} { set lname "poly:model" } |
| if {${lay} == "pwres"} { set lname "pwell:res" } |
| if {${lay} == "diffres"} { set lname "diff:res" } |
| if {${lay} == "polyres"} { set lname "poly:res" } |
| if {${lay} == "lires"} { set lname "li:res" } |
| if {${lay} == "m1res"} { set lname "met1:res" } |
| if {${lay} == "m2res"} { set lname "met2:res" } |
| if {${lay} == "m3res"} { set lname "met3:res" } |
| if {${lay} == "m4res"} { set lname "met4:res" } |
| if {${lay} == "m5res"} { set lname "met5:res" } |
| |
| RULECHECK pmos_de_v20.OVL.${n} { |
| @ pmos_de_v20.OVL.${n}: Illegal pmos_de_v20 device: pmos_de_v20 must not overlap ${lname} |
| OUTPUT "pmos_de_v20 AND ${lay}" |
| } |
| incr n |
| } |
| } |
| |
| illegal_pmos_de_v20 [list "hvtp" "tunm" "rpm" "rrpm" "urpm" "ldntm" "npc" "nsdm" "nsm" "skip_pad" "fuse" "diffres" "pwres" "polyres" "lires" "skip_res" "skip_res" "skip_res" "skip_res" "skip_res" "LVID" "pnp" "npn" "DiodeID" "PHdiodeID" "COREID" "ESDID" "SEALID" "v5" "v12" "polyModel"] |
| |
| verbatim { |
| |
| // RES: |
| |
| } |
| |
| SETLAYER hp_poly_1a = "polyi AND polyres " |
| SETLAYER hp_poly_2a = "hp_poly_1a AND npc" |
| SETLAYER hp_poly_3a = "hp_poly_2a AND psdm" |
| SETLAYER hp_polya = "hp_poly_3a AND rpm" |
| |
| #-------------------------------- |
| proc illegal_rpoly_hp {lay_list} { |
| set n 1 |
| foreach lay $lay_list { |
| set lname ${lay} |
| if {${lay} == "diffi"} { set lname "diff" } |
| if {${lay} == "COREID"} { set lname "areaid:core" } |
| if {${lay} == "ENID"} { set lname "areaid:extendedDrain" } |
| if {${lay} == "SEALID"} { set lname "areaid:seal" } |
| if {${lay} == "LVID"} { set lname "areaid:lvNative" } |
| if {${lay} == "ESDID"} { set lname "areaid:esd" } |
| if {${lay} == "DiodeID"} { set lname "areaid:diode" } |
| if {${lay} == "PHdiodeID"} { set lname "areaid:photo" } |
| if {${lay} == "polyModel"} { set lname "poly:model" } |
| if {${lay} == "pwres"} { set lname "pwell:res" } |
| if {${lay} == "diffres"} { set lname "diff:res" } |
| if {${lay} == "polyres"} { set lname "poly:res" } |
| if {${lay} == "lires"} { set lname "li:res" } |
| if {${lay} == "m1res"} { set lname "met1:res" } |
| if {${lay} == "m2res"} { set lname "met2:res" } |
| if {${lay} == "m3res"} { set lname "met3:res" } |
| if {${lay} == "m4res"} { set lname "met4:res" } |
| if {${lay} == "m5res"} { set lname "met5:res" } |
| |
| RULECHECK rpoly_hp.OVL.${n} { |
| @ rpoly_hp.OVL.${n}: Illegal rpoly_hp device: rpoly_hp must not overlap ${lname} |
| OUTPUT "hp_polya AND ${lay}" |
| } |
| incr n |
| } |
| } |
| |
| illegal_rpoly_hp [list "diffi" "tunm" "urpm" "ldntm" "nsdm" "nsm" "skip_pad" "fuse" "diffres" "pwres" "lires" "skip_res" "skip_res" "skip_res" "skip_res" "skip_res" "LVID" "pnp" "npn" "DiodeID" "PHdiodeID" "COREID" "ENID" "SEALID" "polyModel"] |
| |
| SETLAYER hs_poly_1a = "polyi AND polyres " |
| SETLAYER hs_poly_2a = "hs_poly_1a AND npc" |
| SETLAYER hs_poly_3a = "hs_poly_2a AND psdm" |
| SETLAYER hs_polya = "hs_poly_3a AND urpm" |
| |
| #-------------------------------- |
| proc illegal_rpoly_hs {lay_list} { |
| set n 1 |
| foreach lay $lay_list { |
| set lname ${lay} |
| if {${lay} == "diffi"} { set lname "diff" } |
| if {${lay} == "COREID"} { set lname "areaid:core" } |
| if {${lay} == "ENID"} { set lname "areaid:extendedDrain" } |
| if {${lay} == "SEALID"} { set lname "areaid:seal" } |
| if {${lay} == "LVID"} { set lname "areaid:lvNative" } |
| if {${lay} == "ESDID"} { set lname "areaid:esd" } |
| if {${lay} == "DiodeID"} { set lname "areaid:diode" } |
| if {${lay} == "PHdiodeID"} { set lname "areaid:photo" } |
| if {${lay} == "polyModel"} { set lname "poly:model" } |
| if {${lay} == "pwres"} { set lname "pwell:res" } |
| if {${lay} == "diffres"} { set lname "diff:res" } |
| if {${lay} == "polyres"} { set lname "poly:res" } |
| if {${lay} == "lires"} { set lname "li:res" } |
| if {${lay} == "m1res"} { set lname "met1:res" } |
| if {${lay} == "m2res"} { set lname "met2:res" } |
| if {${lay} == "m3res"} { set lname "met3:res" } |
| if {${lay} == "m4res"} { set lname "met4:res" } |
| if {${lay} == "m5res"} { set lname "met5:res" } |
| RULECHECK rpoly_hs.OVL.${n} { |
| @ rpoly_hs.OVL.${n}: Illegal rpoly_hs device: rpoly_hs must not overlap ${lname} |
| OUTPUT "hs_polya AND ${lay}" |
| } |
| incr n |
| } |
| } |
| |
| illegal_rpoly_hs [list "diffi" "tunm" "rrpm" "ldntm" "nsdm" "nsm" "skip_pad" "fuse" "diffres" "pwres" "lires" "skip_res" "skip_res" "skip_res" "skip_res" "skip_res" "LVID" "pnp" "npn" "DiodeID" "PHdiodeID" "COREID" "ENID" "SEALID" "polyModel"] |
| |
| SETLAYER rpoly_std = "(polyi AND polyres) NOT (OR hp_polya hs_polya)" |
| |
| #-------------------------------- |
| proc illegal_rpoly {lay_list} { |
| set n 1 |
| foreach lay $lay_list { |
| set lname ${lay} |
| if {${lay} == "diffi"} { set lname "diff" } |
| if {${lay} == "COREID"} { set lname "areaid:core" } |
| if {${lay} == "ENID"} { set lname "areaid:extendedDrain" } |
| if {${lay} == "SEALID"} { set lname "areaid:seal" } |
| if {${lay} == "LVID"} { set lname "areaid:lvNative" } |
| if {${lay} == "ESDID"} { set lname "areaid:esd" } |
| if {${lay} == "DiodeID"} { set lname "areaid:diode" } |
| if {${lay} == "PHdiodeID"} { set lname "areaid:photo" } |
| if {${lay} == "polyModel"} { set lname "poly:model" } |
| if {${lay} == "pwres"} { set lname "pwell:res" } |
| if {${lay} == "diffres"} { set lname "diff:res" } |
| if {${lay} == "polyres"} { set lname "poly:res" } |
| if {${lay} == "lires"} { set lname "li:res" } |
| if {${lay} == "m1res"} { set lname "met1:res" } |
| if {${lay} == "m2res"} { set lname "met2:res" } |
| if {${lay} == "m3res"} { set lname "met3:res" } |
| if {${lay} == "m4res"} { set lname "met4:res" } |
| if {${lay} == "m5res"} { set lname "met5:res" } |
| |
| RULECHECK rpoly.OVL.${n} { |
| @ rpoly.OVL.${n}: Illegal rpoly device: rpoly must not overlap ${lname} |
| OUTPUT "rpoly_std AND ${lay}" |
| } |
| incr n |
| } |
| } |
| |
| illegal_rpoly [list "diffi" "tunm" "rpm" "rrpm" "urpm" "ldntm" "psdm" "nsm" "skip_pad" "fuse" "diffres" "pwres" "lires" "skip_res" "skip_res" "skip_res" "skip_res" "skip_res" "LVID" "pnp" "npn" "DiodeID" "PHdiodeID" "COREID" "ENID" "SEALID" "polyModel"] |
| |
| SETLAYER li1r = "li_i AND lires" |
| |
| #-------------------------------- |
| proc illegal_li1r {lay_list} { |
| set n 1 |
| foreach lay $lay_list { |
| set lname ${lay} |
| if {${lay} == "diffi"} { set lname "diff" } |
| if {${lay} == "COREID"} { set lname "areaid:core" } |
| if {${lay} == "ENID"} { set lname "areaid:extendedDrain" } |
| if {${lay} == "SEALID"} { set lname "areaid:seal" } |
| if {${lay} == "LVID"} { set lname "areaid:lvNative" } |
| if {${lay} == "ESDID"} { set lname "areaid:esd" } |
| if {${lay} == "DiodeID"} { set lname "areaid:diode" } |
| if {${lay} == "PHdiodeID"} { set lname "areaid:photo" } |
| if {${lay} == "polyModel"} { set lname "poly:model" } |
| if {${lay} == "pwres"} { set lname "pwell:res" } |
| if {${lay} == "diffres"} { set lname "diff:res" } |
| if {${lay} == "polyres"} { set lname "poly:res" } |
| if {${lay} == "lires"} { set lname "li:res" } |
| if {${lay} == "m1res"} { set lname "met1:res" } |
| if {${lay} == "m2res"} { set lname "met2:res" } |
| if {${lay} == "m3res"} { set lname "met3:res" } |
| if {${lay} == "m4res"} { set lname "met4:res" } |
| if {${lay} == "m5res"} { set lname "met5:res" } |
| |
| RULECHECK lires.OVL.${n} { |
| @ lires.OVL.${n}: Illegal lires device: lires must not overlap ${lname} |
| OUTPUT "li1r AND ${lay}" |
| } |
| incr n |
| } |
| } |
| |
| illegal_li1r [list "licon" "nsm" "skip_pad" "fuse" "PHdiodeID" "COREID" "ENID" "SEALID" "polyModel" "polyres"] |
| |
| SETLAYER m1r = "met1i AND m1res" |
| |
| #-------------------------------- |
| proc illegal_m1r {lay_list} { |
| set n 1 |
| foreach lay $lay_list { |
| set lname ${lay} |
| if {${lay} == "diffi"} { set lname "diff" } |
| if {${lay} == "COREID"} { set lname "areaid:core" } |
| if {${lay} == "ENID"} { set lname "areaid:extendedDrain" } |
| if {${lay} == "SEALID"} { set lname "areaid:seal" } |
| if {${lay} == "LVID"} { set lname "areaid:lvNative" } |
| if {${lay} == "ESDID"} { set lname "areaid:esd" } |
| if {${lay} == "DiodeID"} { set lname "areaid:diode" } |
| if {${lay} == "PHdiodeID"} { set lname "areaid:photo" } |
| if {${lay} == "polyModel"} { set lname "poly:model" } |
| if {${lay} == "pwres"} { set lname "pwell:res" } |
| if {${lay} == "diffres"} { set lname "diff:res" } |
| if {${lay} == "polyres"} { set lname "poly:res" } |
| if {${lay} == "lires"} { set lname "li:res" } |
| if {${lay} == "m1res"} { set lname "met1:res" } |
| if {${lay} == "m2res"} { set lname "met2:res" } |
| if {${lay} == "m3res"} { set lname "met3:res" } |
| if {${lay} == "m4res"} { set lname "met4:res" } |
| if {${lay} == "m5res"} { set lname "met5:res" } |
| |
| RULECHECK m1res.OVL.${n} { |
| @ m1res.OVL.${n}: Illegal m1res device: m1res must not overlap ${lname} |
| OUTPUT "m1r AND ${lay}" |
| } |
| incr n |
| } |
| } |
| |
| illegal_m1r [list "nsm" "skip_pad" "fuse" "SEALID" "polyModel" "ENID"] |
| |
| SETLAYER m2r = "met2i AND m2res" |
| |
| #-------------------------------- |
| proc illegal_m2r {lay_list} { |
| set n 1 |
| foreach lay $lay_list { |
| set lname ${lay} |
| if {${lay} == "diffi"} { set lname "diff" } |
| if {${lay} == "COREID"} { set lname "areaid:core" } |
| if {${lay} == "ENID"} { set lname "areaid:extendedDrain" } |
| if {${lay} == "SEALID"} { set lname "areaid:seal" } |
| if {${lay} == "LVID"} { set lname "areaid:lvNative" } |
| if {${lay} == "ESDID"} { set lname "areaid:esd" } |
| if {${lay} == "DiodeID"} { set lname "areaid:diode" } |
| if {${lay} == "PHdiodeID"} { set lname "areaid:photo" } |
| if {${lay} == "polyModel"} { set lname "poly:model" } |
| if {${lay} == "pwres"} { set lname "pwell:res" } |
| if {${lay} == "diffres"} { set lname "diff:res" } |
| if {${lay} == "polyres"} { set lname "poly:res" } |
| if {${lay} == "lires"} { set lname "li:res" } |
| if {${lay} == "m1res"} { set lname "met1:res" } |
| if {${lay} == "m2res"} { set lname "met2:res" } |
| if {${lay} == "m3res"} { set lname "met3:res" } |
| if {${lay} == "m4res"} { set lname "met4:res" } |
| if {${lay} == "m5res"} { set lname "met5:res" } |
| |
| RULECHECK m2res.OVL.${n} { |
| @ m2res.OVL.${n}: Illegal m2res device: m2res must not overlap ${lname} |
| OUTPUT "m2r AND ${lay}" |
| } |
| incr n |
| } |
| } |
| |
| illegal_m2r [list "nsm" "skip_pad" "fuse" "SEALID" "polyModel" "ENID"] |
| |
| SETLAYER m3r = "met3i AND m3res" |
| |
| #-------------------------------- |
| proc illegal_m3r {lay_list} { |
| set n 1 |
| foreach lay $lay_list { |
| set lname ${lay} |
| if {${lay} == "diffi"} { set lname "diff" } |
| if {${lay} == "COREID"} { set lname "areaid:core" } |
| if {${lay} == "ENID"} { set lname "areaid:extendedDrain" } |
| if {${lay} == "SEALID"} { set lname "areaid:seal" } |
| if {${lay} == "LVID"} { set lname "areaid:lvNative" } |
| if {${lay} == "ESDID"} { set lname "areaid:esd" } |
| if {${lay} == "DiodeID"} { set lname "areaid:diode" } |
| if {${lay} == "PHdiodeID"} { set lname "areaid:photo" } |
| if {${lay} == "polyModel"} { set lname "poly:model" } |
| if {${lay} == "pwres"} { set lname "pwell:res" } |
| if {${lay} == "diffres"} { set lname "diff:res" } |
| if {${lay} == "polyres"} { set lname "poly:res" } |
| if {${lay} == "lires"} { set lname "li:res" } |
| if {${lay} == "m1res"} { set lname "met1:res" } |
| if {${lay} == "m2res"} { set lname "met2:res" } |
| if {${lay} == "m3res"} { set lname "met3:res" } |
| if {${lay} == "m4res"} { set lname "met4:res" } |
| if {${lay} == "m5res"} { set lname "met5:res" } |
| |
| RULECHECK m3res.OVL.${n} { |
| @ m3res.OVL.${n}: Illegal m3res device: m3res must not overlap ${lname} |
| OUTPUT "m3r AND ${lay}" |
| } |
| incr n |
| } |
| } |
| |
| illegal_m3r [list "nsm" "skip_pad" "fuse" "SEALID" "polyModel" "ENID"] |
| |
| SETLAYER m4r = "met4i AND m4res" |
| |
| #-------------------------------- |
| proc illegal_m4r {lay_list} { |
| set n 1 |
| foreach lay $lay_list { |
| set lname ${lay} |
| if {${lay} == "diffi"} { set lname "diff" } |
| if {${lay} == "COREID"} { set lname "areaid:core" } |
| if {${lay} == "ENID"} { set lname "areaid:extendedDrain" } |
| if {${lay} == "SEALID"} { set lname "areaid:seal" } |
| if {${lay} == "LVID"} { set lname "areaid:lvNative" } |
| if {${lay} == "ESDID"} { set lname "areaid:esd" } |
| if {${lay} == "DiodeID"} { set lname "areaid:diode" } |
| if {${lay} == "PHdiodeID"} { set lname "areaid:photo" } |
| if {${lay} == "polyModel"} { set lname "poly:model" } |
| if {${lay} == "pwres"} { set lname "pwell:res" } |
| if {${lay} == "diffres"} { set lname "diff:res" } |
| if {${lay} == "polyres"} { set lname "poly:res" } |
| if {${lay} == "lires"} { set lname "li:res" } |
| if {${lay} == "m1res"} { set lname "met1:res" } |
| if {${lay} == "m2res"} { set lname "met2:res" } |
| if {${lay} == "m3res"} { set lname "met3:res" } |
| if {${lay} == "m4res"} { set lname "met4:res" } |
| if {${lay} == "m5res"} { set lname "met5:res" } |
| |
| RULECHECK m4res.OVL.${n} { |
| @ m4res.OVL.${n}: Illegal m4res device: m4res must not overlap ${lname} |
| OUTPUT "m4r AND ${lay}" |
| } |
| incr n |
| } |
| } |
| |
| illegal_m4r [list "nsm" "skip_pad" "fuse" "SEALID" "polyModel" "ENID"] |
| |
| SETLAYER m5r = "met5i AND m5res" |
| |
| #-------------------------------- |
| proc illegal_m5r {lay_list} { |
| set n 1 |
| foreach lay $lay_list { |
| set lname ${lay} |
| if {${lay} == "diffi"} { set lname "diff" } |
| if {${lay} == "COREID"} { set lname "areaid:core" } |
| if {${lay} == "ENID"} { set lname "areaid:extendedDrain" } |
| if {${lay} == "SEALID"} { set lname "areaid:seal" } |
| if {${lay} == "LVID"} { set lname "areaid:lvNative" } |
| if {${lay} == "ESDID"} { set lname "areaid:esd" } |
| if {${lay} == "DiodeID"} { set lname "areaid:diode" } |
| if {${lay} == "PHdiodeID"} { set lname "areaid:photo" } |
| if {${lay} == "polyModel"} { set lname "poly:model" } |
| if {${lay} == "pwres"} { set lname "pwell:res" } |
| if {${lay} == "diffres"} { set lname "diff:res" } |
| if {${lay} == "polyres"} { set lname "poly:res" } |
| if {${lay} == "lires"} { set lname "li:res" } |
| if {${lay} == "m1res"} { set lname "met1:res" } |
| if {${lay} == "m2res"} { set lname "met2:res" } |
| if {${lay} == "m3res"} { set lname "met3:res" } |
| if {${lay} == "m4res"} { set lname "met4:res" } |
| if {${lay} == "m5res"} { set lname "met5:res" } |
| |
| RULECHECK m5res.OVL.${n} { |
| @ m5res.OVL.${n}: Illegal m5res device: m5res must not overlap ${lname} |
| OUTPUT "m5r AND ${lay}" |
| } |
| incr n |
| } |
| } |
| |
| illegal_m5r [list "nsm" "skip_pad" "fuse" "SEALID" "polyModel" "ENID"] |
| |
| SETLAYER rndiff_ill_dev = "((nsdm AND diffi) AND diffres) NOT v5" |
| |
| #-------------------------------- |
| proc illegal_rndiff {lay_list} { |
| set n 1 |
| foreach lay $lay_list { |
| set lname ${lay} |
| if {${lay} == "polyi"} { set lname "poly" } |
| if {${lay} == "diffi"} { set lname "diff" } |
| if {${lay} == "COREID"} { set lname "areaid:core" } |
| if {${lay} == "ENID"} { set lname "areaid:extendedDrain" } |
| if {${lay} == "SEALID"} { set lname "areaid:seal" } |
| if {${lay} == "LVID"} { set lname "areaid:lvNative" } |
| if {${lay} == "ESDID"} { set lname "areaid:esd" } |
| if {${lay} == "DiodeID"} { set lname "areaid:diode" } |
| if {${lay} == "PHdiodeID"} { set lname "areaid:photo" } |
| if {${lay} == "polyModel"} { set lname "poly:model" } |
| if {${lay} == "pwres"} { set lname "pwell:res" } |
| if {${lay} == "diffres"} { set lname "diff:res" } |
| if {${lay} == "polyres"} { set lname "poly:res" } |
| if {${lay} == "lires"} { set lname "li:res" } |
| if {${lay} == "m1res"} { set lname "met1:res" } |
| if {${lay} == "m2res"} { set lname "met2:res" } |
| if {${lay} == "m3res"} { set lname "met3:res" } |
| if {${lay} == "m4res"} { set lname "met4:res" } |
| if {${lay} == "m5res"} { set lname "met5:res" } |
| |
| RULECHECK rndiff.OVL.${n} { |
| @ rndiff.OVL.${n}: Illegal rndiff device: rndiff must not overlap ${lname} |
| OUTPUT "rndiff_ill_dev AND ${lay}" |
| } |
| incr n |
| } |
| } |
| |
| illegal_rndiff [list "pwbm" "nwell" "hvtp" "lvtn" "tunm" "thkox" "rpm" "rrpm" "urpm" "ldntm" "psdm" "nsm" "skip_pad" "fuse" "polyres" "LVID" "pnp" "npn" "DiodeID" "PHdiodeID" "COREID" "ENID" "SEALID" "v5" "v12" "v20" "polyModel" "pwde" "polyi" "npc" "lires" ] |
| |
| SETLAYER rpdiff_ill_dev = "((psdm AND diffi) AND diffres) NOT v5" |
| |
| #-------------------------------- |
| proc illegal_rpdiff {lay_list} { |
| set n 1 |
| foreach lay $lay_list { |
| set lname ${lay} |
| if {${lay} == "polyi"} { set lname "poly" } |
| if {${lay} == "diffi"} { set lname "diff" } |
| if {${lay} == "COREID"} { set lname "areaid:core" } |
| if {${lay} == "ENID"} { set lname "areaid:extendedDrain" } |
| if {${lay} == "SEALID"} { set lname "areaid:seal" } |
| if {${lay} == "LVID"} { set lname "areaid:lvNative" } |
| if {${lay} == "ESDID"} { set lname "areaid:esd" } |
| if {${lay} == "DiodeID"} { set lname "areaid:diode" } |
| if {${lay} == "PHdiodeID"} { set lname "areaid:photo" } |
| if {${lay} == "polyModel"} { set lname "poly:model" } |
| if {${lay} == "pwres"} { set lname "pwell:res" } |
| if {${lay} == "diffres"} { set lname "diff:res" } |
| if {${lay} == "polyres"} { set lname "poly:res" } |
| if {${lay} == "lires"} { set lname "li:res" } |
| if {${lay} == "m1res"} { set lname "met1:res" } |
| if {${lay} == "m2res"} { set lname "met2:res" } |
| if {${lay} == "m3res"} { set lname "met3:res" } |
| if {${lay} == "m4res"} { set lname "met4:res" } |
| if {${lay} == "m5res"} { set lname "met5:res" } |
| |
| RULECHECK rpdiff.OVL.${n} { |
| @ rpdiff.OVL.${n}: Illegal rpdiff device: rpdiff must not overlap ${lname} |
| OUTPUT "rpdiff_ill_dev AND ${lay}" |
| } |
| incr n |
| } |
| } |
| |
| illegal_rpdiff [list "pwbm" "hvtp" "lvtn" "tunm" "thkox" "rpm" "rrpm" "urpm" "ldntm" "nsdm" "nsm" "skip_pad" "fuse" "polyres" "LVID" "pnp" "npn" "DiodeID" "PHdiodeID" "COREID" "ENID" "SEALID" "v5" "v12" "v20" "polyModel" "pwde" "polyi" "npc" "lires" ] |
| |
| SETLAYER rndiff_v5 = "((nsdm AND diffi) AND diffres) AND v5" |
| SETLAYER id_dummy3 = "COPY 5000" |
| |
| #-------------------------------- |
| proc illegal_rndiff_v5 {lay_list} { |
| set n 1 |
| foreach lay $lay_list { |
| set lname ${lay} |
| if {${lay} == "polyi"} { set lname "poly" } |
| if {${lay} == "diffi"} { set lname "diff" } |
| if {${lay} == "COREID"} { set lname "areaid:core" } |
| if {${lay} == "ENID"} { set lname "areaid:extendedDrain" } |
| if {${lay} == "SEALID"} { set lname "areaid:seal" } |
| if {${lay} == "LVID"} { set lname "areaid:lvNative" } |
| if {${lay} == "ESDID"} { set lname "areaid:esd" } |
| if {${lay} == "DiodeID"} { set lname "areaid:diode" } |
| if {${lay} == "PHdiodeID"} { set lname "areaid:photo" } |
| if {${lay} == "polyModel"} { set lname "poly:model" } |
| if {${lay} == "pwres"} { set lname "pwell:res" } |
| if {${lay} == "diffres"} { set lname "diff:res" } |
| if {${lay} == "polyres"} { set lname "poly:res" } |
| if {${lay} == "lires"} { set lname "li:res" } |
| if {${lay} == "m1res"} { set lname "met1:res" } |
| if {${lay} == "m2res"} { set lname "met2:res" } |
| if {${lay} == "m3res"} { set lname "met3:res" } |
| if {${lay} == "m4res"} { set lname "met4:res" } |
| if {${lay} == "m5res"} { set lname "met5:res" } |
| |
| |
| RULECHECK rndiff_v5.OVL.${n} { |
| @ rndiff_v5.OVL.${n}: Illegal rndiff_v5 device: rndiff_v5 must not overlap ${lname} |
| OUTPUT "rndiff_v5 AND ${lay}" |
| } |
| incr n |
| } |
| } |
| |
| illegal_rndiff_v5 [list "pwbm" "nwell" "hvtp" "lvtn" "tunm" "id_dummy3" "rpm" "rrpm" "urpm" "ldntm" "psdm" "nsm" "skip_pad" "fuse" "polyres" "LVID" "pnp" "npn" "DiodeID" "PHdiodeID" "COREID" "ENID" "SEALID" "v12" "v20" "polyModel" "pwde" "polyi" "npc" "lires" ] |
| |
| SETLAYER rpdiff_v5 = "((psdm AND diffi) AND diffres) AND v5" |
| |
| #-------------------------------- |
| proc illegal_rpdiff_v5 {lay_list} { |
| set n 1 |
| foreach lay $lay_list { |
| set lname ${lay} |
| if {${lay} == "polyi"} { set lname "poly" } |
| if {${lay} == "diffi"} { set lname "diff" } |
| if {${lay} == "COREID"} { set lname "areaid:core" } |
| if {${lay} == "ENID"} { set lname "areaid:extendedDrain" } |
| if {${lay} == "SEALID"} { set lname "areaid:seal" } |
| if {${lay} == "LVID"} { set lname "areaid:lvNative" } |
| if {${lay} == "ESDID"} { set lname "areaid:esd" } |
| if {${lay} == "DiodeID"} { set lname "areaid:diode" } |
| if {${lay} == "PHdiodeID"} { set lname "areaid:photo" } |
| if {${lay} == "polyModel"} { set lname "poly:model" } |
| if {${lay} == "pwres"} { set lname "pwell:res" } |
| if {${lay} == "diffres"} { set lname "diff:res" } |
| if {${lay} == "polyres"} { set lname "poly:res" } |
| if {${lay} == "lires"} { set lname "li:res" } |
| if {${lay} == "m1res"} { set lname "met1:res" } |
| if {${lay} == "m2res"} { set lname "met2:res" } |
| if {${lay} == "m3res"} { set lname "met3:res" } |
| if {${lay} == "m4res"} { set lname "met4:res" } |
| if {${lay} == "m5res"} { set lname "met5:res" } |
| |
| RULECHECK rpdiff_v5.OVL.${n} { |
| @ rpdiff_v5.OVL.${n}: Illegal rpdiff_v5 device: rpdiff_v5 must not overlap ${lname} |
| OUTPUT "rpdiff_v5 AND ${lay}" |
| } |
| incr n |
| } |
| } |
| |
| illegal_rpdiff_v5 [list "pwbm" "hvtp" "lvtn" "tunm" "id_dummy3" "rpm" "rrpm" "urpm" "ldntm" "nsdm" "nsm" "skip_pad" "fuse" "polyres" "LVID" "pnp" "npn" "DiodeID" "PHdiodeID" "COREID" "ENID" "SEALID" "v12" "v20" "polyModel" "pwde" "polyi" "npc" "lires" ] |
| |
| SETLAYER rpwell = "(pwres AND psdm) AND ((HOLES nwell) AND dnwell)" |
| |
| #-------------------------------- |
| proc illegal_rpwell {lay_list} { |
| set n 1 |
| foreach lay $lay_list { |
| set lname ${lay} |
| if {${lay} == "polyi"} { set lname "poly" } |
| if {${lay} == "diffi"} { set lname "diff" } |
| if {${lay} == "COREID"} { set lname "areaid:core" } |
| if {${lay} == "ENID"} { set lname "areaid:extendedDrain" } |
| if {${lay} == "SEALID"} { set lname "areaid:seal" } |
| if {${lay} == "LVID"} { set lname "areaid:lvNative" } |
| if {${lay} == "ESDID"} { set lname "areaid:esd" } |
| if {${lay} == "DiodeID"} { set lname "areaid:diode" } |
| if {${lay} == "PHdiodeID"} { set lname "areaid:photo" } |
| if {${lay} == "polyModel"} { set lname "poly:model" } |
| if {${lay} == "pwres"} { set lname "pwell:res" } |
| if {${lay} == "diffres"} { set lname "diff:res" } |
| if {${lay} == "polyres"} { set lname "poly:res" } |
| if {${lay} == "lires"} { set lname "li:res" } |
| if {${lay} == "m1res"} { set lname "met1:res" } |
| if {${lay} == "m2res"} { set lname "met2:res" } |
| if {${lay} == "m3res"} { set lname "met3:res" } |
| if {${lay} == "m4res"} { set lname "met4:res" } |
| if {${lay} == "m5res"} { set lname "met5:res" } |
| |
| RULECHECK rpwell.OVL.${n} { |
| @ rpwell.OVL.${n}: Illegal rpwell device: rpwell must not overlap ${lname} |
| OUTPUT "rpwell AND ${lay}" |
| } |
| incr n |
| } |
| } |
| |
| # replaced pnp with 'id_dummy' as this was deleted per PM 12/2/2020 |
| # create id_dummy2: |
| SETLAYER id_dummy2 = "COPY 4998" |
| # replaced npn with 'id_dummy2' as this was deleted per PM 12/2/2020 |
| |
| illegal_rpwell [list "pwbm" "pwde" "hvtp" "lvtn" "tunm" "thkox" "rpm" "rrpm" "urpm" "polyi" "ldntm" "npc" "nsm" "skip_pad" "fuse" "polyres" "LVID" "id_dummy" "id_dummy2" "PHdiodeID" "COREID" "ENID" "SEALID" "v5" "v12" "v20" "polyModel" "nwell" "diffres" "lires"] |
| |
| verbatim { |
| |
| // CAP: |
| |
| } |
| |
| SETLAYER cap_34a = "(met3 AND met4) AND capm" |
| |
| #-------------------------------- |
| proc illegal_cap34 {lay_list} { |
| set n 1 |
| foreach lay $lay_list { |
| set lname ${lay} |
| if {${lay} == "polyi"} { set lname "poly" } |
| if {${lay} == "diffi"} { set lname "diff" } |
| if {${lay} == "COREID"} { set lname "areaid:core" } |
| if {${lay} == "ENID"} { set lname "areaid:extendedDrain" } |
| if {${lay} == "SEALID"} { set lname "areaid:seal" } |
| if {${lay} == "LVID"} { set lname "areaid:lvNative" } |
| if {${lay} == "ESDID"} { set lname "areaid:esd" } |
| if {${lay} == "DiodeID"} { set lname "areaid:diode" } |
| if {${lay} == "PHdiodeID"} { set lname "areaid:photo" } |
| if {${lay} == "polyModel"} { set lname "poly:model" } |
| if {${lay} == "pwres"} { set lname "pwell:res" } |
| if {${lay} == "diffres"} { set lname "diff:res" } |
| if {${lay} == "polyres"} { set lname "poly:res" } |
| if {${lay} == "lires"} { set lname "li:res" } |
| if {${lay} == "m1res"} { set lname "met1:res" } |
| if {${lay} == "m2res"} { set lname "met2:res" } |
| if {${lay} == "m3res"} { set lname "met3:res" } |
| if {${lay} == "m4res"} { set lname "met4:res" } |
| if {${lay} == "m5res"} { set lname "met5:res" } |
| |
| RULECHECK capm3m4.OVL.${n} { |
| @ capm3m4.OVL.${n}: Illegal capm3m4 device: capm3m4 must not overlap ${lname} |
| OUTPUT "cap_34a AND ${lay}" |
| } |
| incr n |
| } |
| } |
| |
| illegal_cap34 [list "nsm" "skip_pad" "LVID" "PHdiodeID" "COREID" "ENID" "fuse" "SEALID" "polyModel"] |
| |
| SETLAYER cap_45a = "(met4 AND met5) AND cap2m" |
| |
| #-------------------------------- |
| proc illegal_cap45 {lay_list} { |
| set n 1 |
| foreach lay $lay_list { |
| set lname ${lay} |
| if {${lay} == "polyi"} { set lname "poly" } |
| if {${lay} == "diffi"} { set lname "diff" } |
| if {${lay} == "COREID"} { set lname "areaid:core" } |
| if {${lay} == "ENID"} { set lname "areaid:extendedDrain" } |
| if {${lay} == "SEALID"} { set lname "areaid:seal" } |
| if {${lay} == "LVID"} { set lname "areaid:lvNative" } |
| if {${lay} == "ESDID"} { set lname "areaid:esd" } |
| if {${lay} == "DiodeID"} { set lname "areaid:diode" } |
| if {${lay} == "PHdiodeID"} { set lname "areaid:photo" } |
| if {${lay} == "polyModel"} { set lname "poly:model" } |
| if {${lay} == "pwres"} { set lname "pwell:res" } |
| if {${lay} == "diffres"} { set lname "diff:res" } |
| if {${lay} == "polyres"} { set lname "poly:res" } |
| if {${lay} == "lires"} { set lname "li:res" } |
| if {${lay} == "m1res"} { set lname "met1:res" } |
| if {${lay} == "m2res"} { set lname "met2:res" } |
| if {${lay} == "m3res"} { set lname "met3:res" } |
| if {${lay} == "m4res"} { set lname "met4:res" } |
| if {${lay} == "m5res"} { set lname "met5:res" } |
| |
| RULECHECK capm4m5.OVL.${n} { |
| @ capm4m5.OVL.${n}: Illegal capm4m5 device: capm4m5 must not overlap ${lname} |
| OUTPUT "cap_45a AND ${lay}" |
| } |
| incr n |
| } |
| } |
| |
| illegal_cap45 [list "nsm" "skip_pad" "LVID" "PHdiodeID" "COREID" "ENID" "fuse" "SEALID" "polyModel"] |
| |
| verbatim { |
| |
| // DIO: |
| |
| } |
| |
| SETLAYER diode_dnsd_pw = "(((diodeID AND nsdm) NOT nwell) AND diffi) NOT (OR ESDID v5 v12 v20 lvtn hvtp LVID)" |
| |
| #-------------------------------- |
| proc illegal_dnsd_pw {lay_list} { |
| set n 1 |
| foreach lay $lay_list { |
| set lname ${lay} |
| if {${lay} == "polyi"} { set lname "poly" } |
| if {${lay} == "diffi"} { set lname "diff" } |
| if {${lay} == "COREID"} { set lname "areaid:core" } |
| if {${lay} == "ENID"} { set lname "areaid:extendedDrain" } |
| if {${lay} == "SEALID"} { set lname "areaid:seal" } |
| if {${lay} == "LVID"} { set lname "areaid:lvNative" } |
| if {${lay} == "ESDID"} { set lname "areaid:esd" } |
| if {${lay} == "DiodeID"} { set lname "areaid:diode" } |
| if {${lay} == "PHdiodeID"} { set lname "areaid:photo" } |
| if {${lay} == "polyModel"} { set lname "poly:model" } |
| if {${lay} == "pwres"} { set lname "pwell:res" } |
| if {${lay} == "diffres"} { set lname "diff:res" } |
| if {${lay} == "polyres"} { set lname "poly:res" } |
| if {${lay} == "lires"} { set lname "li:res" } |
| if {${lay} == "m1res"} { set lname "met1:res" } |
| if {${lay} == "m2res"} { set lname "met2:res" } |
| if {${lay} == "m3res"} { set lname "met3:res" } |
| if {${lay} == "m4res"} { set lname "met4:res" } |
| if {${lay} == "m5res"} { set lname "met5:res" } |
| |
| RULECHECK dnsd_pw.OVL.${n} { |
| @ dnsd_pw.OVL.${n}: Illegal dnsd_pw device: dnsd_pw must not overlap ${lname} |
| OUTPUT "diode_dnsd_pw AND ${lay}" |
| } |
| incr n |
| } |
| } |
| |
| illegal_dnsd_pw [list "pwbm" "nwell" "hvtp" "lvtn" "tunm" "thkox" "rpm" "rrpm" "urpm" "polyi" "ldntm" "psdm" "nsm" "skip_pad" "fuse" "diffres" "polyres" "lires" "LVID" "pnp" "npn" "PHdiodeID" "ENID" "v5" "v12" "v20" "npc" "SEALID" "polyModel"] |
| |
| SETLAYER diode_dnsd_pw_v5 = "(((((diodeID AND nsdm) NOT nwell) AND diffi) AND v5) AND thkox) NOT (OR v12 v20 lvtn hvtp ESDID LVID)" |
| |
| #-------------------------------- |
| proc illegal_dnsd_pw_v5 {lay_list} { |
| set n 1 |
| foreach lay $lay_list { |
| set lname ${lay} |
| if {${lay} == "polyi"} { set lname "poly" } |
| if {${lay} == "diffi"} { set lname "diff" } |
| if {${lay} == "COREID"} { set lname "areaid:core" } |
| if {${lay} == "ENID"} { set lname "areaid:extendedDrain" } |
| if {${lay} == "SEALID"} { set lname "areaid:seal" } |
| if {${lay} == "LVID"} { set lname "areaid:lvNative" } |
| if {${lay} == "ESDID"} { set lname "areaid:esd" } |
| if {${lay} == "DiodeID"} { set lname "areaid:diode" } |
| if {${lay} == "PHdiodeID"} { set lname "areaid:photo" } |
| if {${lay} == "polyModel"} { set lname "poly:model" } |
| if {${lay} == "pwres"} { set lname "pwell:res" } |
| if {${lay} == "diffres"} { set lname "diff:res" } |
| if {${lay} == "polyres"} { set lname "poly:res" } |
| if {${lay} == "lires"} { set lname "li:res" } |
| if {${lay} == "m1res"} { set lname "met1:res" } |
| if {${lay} == "m2res"} { set lname "met2:res" } |
| if {${lay} == "m3res"} { set lname "met3:res" } |
| if {${lay} == "m4res"} { set lname "met4:res" } |
| if {${lay} == "m5res"} { set lname "met5:res" } |
| |
| RULECHECK dnsd_pw_v5.OVL.${n} { |
| @ dnsd_pw_v5.OVL.${n}: Illegal dnsd_pw_v5 device: dnsd_pw_v5 must not overlap ${lname} |
| OUTPUT "diode_dnsd_pw_v5 AND ${lay}" |
| } |
| incr n |
| } |
| } |
| |
| illegal_dnsd_pw_v5 [list "pwbm" "nwell" "hvtp" "lvtn" "tunm" "rpm" "rrpm" "urpm" "polyi" "ldntm" "psdm" "nsm" "skip_pad" "fuse" "diffres" "polyres" "lires" "LVID" "pnp" "npn" "PHdiodeID" "COREID" "ENID" "v12" "v20" "npc" "SEALID" "polyModel" "pwde" "pwres" "polyres"] |
| |
| SETLAYER diode_dnsd_pw_lvt = "((((diodeID AND nsdm) NOT nwell) AND diffi) AND lvtn) NOT (OR v5 v12 v20 hvtp ESDID LVID)" |
| |
| #-------------------------------- |
| proc illegal_dnsd_pw_lvt {lay_list} { |
| set n 1 |
| foreach lay $lay_list { |
| set lname ${lay} |
| if {${lay} == "polyi"} { set lname "poly" } |
| if {${lay} == "diffi"} { set lname "diff" } |
| if {${lay} == "COREID"} { set lname "areaid:core" } |
| if {${lay} == "ENID"} { set lname "areaid:extendedDrain" } |
| if {${lay} == "SEALID"} { set lname "areaid:seal" } |
| if {${lay} == "LVID"} { set lname "areaid:lvNative" } |
| if {${lay} == "ESDID"} { set lname "areaid:esd" } |
| if {${lay} == "DiodeID"} { set lname "areaid:diode" } |
| if {${lay} == "PHdiodeID"} { set lname "areaid:photo" } |
| if {${lay} == "polyModel"} { set lname "poly:model" } |
| if {${lay} == "pwres"} { set lname "pwell:res" } |
| if {${lay} == "diffres"} { set lname "diff:res" } |
| if {${lay} == "polyres"} { set lname "poly:res" } |
| if {${lay} == "lires"} { set lname "li:res" } |
| if {${lay} == "m1res"} { set lname "met1:res" } |
| if {${lay} == "m2res"} { set lname "met2:res" } |
| if {${lay} == "m3res"} { set lname "met3:res" } |
| if {${lay} == "m4res"} { set lname "met4:res" } |
| if {${lay} == "m5res"} { set lname "met5:res" } |
| |
| RULECHECK dnsd_pw_lvt.OVL.${n} { |
| @ dnsd_pw_lvt.OVL.${n}: Illegal dnsd_pw_lvt device: dnsd_pw_lvt must not overlap ${lname} |
| OUTPUT "diode_dnsd_pw_lvt AND ${lay}" |
| } |
| incr n |
| } |
| } |
| |
| illegal_dnsd_pw_lvt [list "pwbm" "pwde" "tunm" "rpm" "rrpm" "urpm" "polyi" "ldntm" "npc" "psdm" "nsm" "skip_pad" "fuse" "pwres" "polyres" "polyModel" "PHDiodeID" "ENID" "SEALID" "v5" "V12" "v20"] |
| |
| SETLAYER diode_dnsd_pw_nat = "(((((diodeID AND nsdm) NOT nwell) AND diffi) AND LVID) AND lvtn) NOT (OR ESDID v5 v12 v20 hvtp)" |
| |
| #-------------------------------- |
| proc illegal_dnsd_pw_nat {lay_list} { |
| set n 1 |
| foreach lay $lay_list { |
| set lname ${lay} |
| if {${lay} == "polyi"} { set lname "poly" } |
| if {${lay} == "diffi"} { set lname "diff" } |
| if {${lay} == "COREID"} { set lname "areaid:core" } |
| if {${lay} == "ENID"} { set lname "areaid:extendedDrain" } |
| if {${lay} == "SEALID"} { set lname "areaid:seal" } |
| if {${lay} == "LVID"} { set lname "areaid:lvNative" } |
| if {${lay} == "ESDID"} { set lname "areaid:esd" } |
| if {${lay} == "DiodeID"} { set lname "areaid:diode" } |
| if {${lay} == "PHdiodeID"} { set lname "areaid:photo" } |
| if {${lay} == "polyModel"} { set lname "poly:model" } |
| if {${lay} == "pwres"} { set lname "pwell:res" } |
| if {${lay} == "diffres"} { set lname "diff:res" } |
| if {${lay} == "polyres"} { set lname "poly:res" } |
| if {${lay} == "lires"} { set lname "li:res" } |
| if {${lay} == "m1res"} { set lname "met1:res" } |
| if {${lay} == "m2res"} { set lname "met2:res" } |
| if {${lay} == "m3res"} { set lname "met3:res" } |
| if {${lay} == "m4res"} { set lname "met4:res" } |
| if {${lay} == "m5res"} { set lname "met5:res" } |
| |
| RULECHECK dnsd_pw_nat.OVL.${n} { |
| @ dnsd_pw_nat.OVL.${n}: Illegal dnsd_pw_nat device: dnsd_pw_nat must not overlap ${lname} |
| OUTPUT "diode_dnsd_pw_nat AND ${lay}" |
| } |
| incr n |
| } |
| } |
| |
| # create an empty dummy layer to stand in for a deleted layer to minimize |
| # impact to test structures: |
| SETLAYER id_dummy = "COPY 4999" |
| # Here 'thkox' was removed and replaced with 'ill_dummy': |
| illegal_dnsd_pw_nat [list "pwbm" "tunm" "id_dummy" "rpm" "rrpm" "urpm" "polyi" "ldntm" "npc" "psdm" "nsm" "skip_pad" "fuse" "PHdiodeID" "ENID" "SEALID" "v5" "v12" "v20" "polyModel" "pwde" "pwres" "polyres"] |
| |
| SETLAYER diode_dpsd_nw = "(((diodeID AND psdm) AND nwell) AND diffi) NOT (OR thkox v5 v12 v20 lvtn hvtp ESDID LVID)" |
| |
| #-------------------------------- |
| proc illegal_dpsd_nw {lay_list} { |
| set n 1 |
| foreach lay $lay_list { |
| set lname ${lay} |
| if {${lay} == "polyi"} { set lname "poly" } |
| if {${lay} == "diffi"} { set lname "diff" } |
| if {${lay} == "COREID"} { set lname "areaid:core" } |
| if {${lay} == "ENID"} { set lname "areaid:extendedDrain" } |
| if {${lay} == "SEALID"} { set lname "areaid:seal" } |
| if {${lay} == "LVID"} { set lname "areaid:lvNative" } |
| if {${lay} == "ESDID"} { set lname "areaid:esd" } |
| if {${lay} == "DiodeID"} { set lname "areaid:diode" } |
| if {${lay} == "PHdiodeID"} { set lname "areaid:photo" } |
| if {${lay} == "polyModel"} { set lname "poly:model" } |
| if {${lay} == "pwres"} { set lname "pwell:res" } |
| if {${lay} == "diffres"} { set lname "diff:res" } |
| if {${lay} == "polyres"} { set lname "poly:res" } |
| if {${lay} == "lires"} { set lname "li:res" } |
| if {${lay} == "m1res"} { set lname "met1:res" } |
| if {${lay} == "m2res"} { set lname "met2:res" } |
| if {${lay} == "m3res"} { set lname "met3:res" } |
| if {${lay} == "m4res"} { set lname "met4:res" } |
| if {${lay} == "m5res"} { set lname "met5:res" } |
| |
| RULECHECK dpsd_nw.OVL.${n} { |
| @ dpsd_nw.OVL.${n}: Illegal dpsd_nw device: dpsd_nw must not overlap ${lname} |
| OUTPUT "diode_dpsd_nw AND ${lay}" |
| } |
| incr n |
| } |
| } |
| |
| illegal_dpsd_nw [list "pwbm" "hvtp" "lvtn" "tunm" "thkox" "rpm" "rrpm" "urpm" "polyi" "ldntm" "npc" "nsdm" "nsm" "skip_pad" "fuse" "diffres" "polyres" "lires" "LVID" "ENID" "SEALID" "v5" "v12" "v20" "polyModel" "pwde" "pwres" "polyres" "pnp" "npn"] |
| |
| SETLAYER diode_dpsd_nw_v5 = "(((((diodeID AND psdm) AND nwell) AND diffi) AND thkox) AND v5) NOT (OR v12 v20 lvtn hvtp ESDID LVID)" |
| |
| #-------------------------------- |
| proc illegal_dpsd_nw_v5 {lay_list} { |
| set n 1 |
| foreach lay $lay_list { |
| set lname ${lay} |
| if {${lay} == "polyi"} { set lname "poly" } |
| if {${lay} == "diffi"} { set lname "diff" } |
| if {${lay} == "COREID"} { set lname "areaid:core" } |
| if {${lay} == "ENID"} { set lname "areaid:extendedDrain" } |
| if {${lay} == "SEALID"} { set lname "areaid:seal" } |
| if {${lay} == "LVID"} { set lname "areaid:lvNative" } |
| if {${lay} == "ESDID"} { set lname "areaid:esd" } |
| if {${lay} == "DiodeID"} { set lname "areaid:diode" } |
| if {${lay} == "PHdiodeID"} { set lname "areaid:photo" } |
| if {${lay} == "polyModel"} { set lname "poly:model" } |
| if {${lay} == "pwres"} { set lname "pwell:res" } |
| if {${lay} == "diffres"} { set lname "diff:res" } |
| if {${lay} == "polyres"} { set lname "poly:res" } |
| if {${lay} == "lires"} { set lname "li:res" } |
| if {${lay} == "m1res"} { set lname "met1:res" } |
| if {${lay} == "m2res"} { set lname "met2:res" } |
| if {${lay} == "m3res"} { set lname "met3:res" } |
| if {${lay} == "m4res"} { set lname "met4:res" } |
| if {${lay} == "m5res"} { set lname "met5:res" } |
| |
| RULECHECK dpsd_nw_v5.OVL.${n} { |
| @ dpsd_nw_v5.OVL.${n}: Illegal dpsd_nw_v5 device: dpsd_nw_v5 must not overlap ${lname} |
| OUTPUT "diode_dpsd_nw_v5 AND ${lay}" |
| } |
| incr n |
| } |
| } |
| |
| illegal_dpsd_nw_v5 [list "pwbm" "hvtp" "lvtn" "tunm" "rpm" "rrpm" "urpm" "polyi" "ldntm" "npc" "nsdm" "nsm" "skip_pad" "fuse" "diffres" "polyres" "lires" "LVID" "ENID" "SEALID" "v12" "v20" "polyModel" "pwde" "pwres" "pnp" "npn" "PHdiodeID"] |
| |
| SETLAYER diode_dpsd_nw_lvt = "((((diodeID AND psdm) AND nwell) AND diffi) AND lvtn) NOT (OR thkox v5 v12 v20 hvtp ESDID LVID)" |
| |
| #-------------------------------- |
| proc illegal_dpsd_nw_lvt {lay_list} { |
| set n 1 |
| foreach lay $lay_list { |
| set lname ${lay} |
| if {${lay} == "polyi"} { set lname "poly" } |
| if {${lay} == "diffi"} { set lname "diff" } |
| if {${lay} == "COREID"} { set lname "areaid:core" } |
| if {${lay} == "ENID"} { set lname "areaid:extendedDrain" } |
| if {${lay} == "SEALID"} { set lname "areaid:seal" } |
| if {${lay} == "LVID"} { set lname "areaid:lvNative" } |
| if {${lay} == "ESDID"} { set lname "areaid:esd" } |
| if {${lay} == "DiodeID"} { set lname "areaid:diode" } |
| if {${lay} == "PHdiodeID"} { set lname "areaid:photo" } |
| if {${lay} == "polyModel"} { set lname "poly:model" } |
| if {${lay} == "pwres"} { set lname "pwell:res" } |
| if {${lay} == "diffres"} { set lname "diff:res" } |
| if {${lay} == "polyres"} { set lname "poly:res" } |
| if {${lay} == "lires"} { set lname "li:res" } |
| if {${lay} == "m1res"} { set lname "met1:res" } |
| if {${lay} == "m2res"} { set lname "met2:res" } |
| if {${lay} == "m3res"} { set lname "met3:res" } |
| if {${lay} == "m4res"} { set lname "met4:res" } |
| if {${lay} == "m5res"} { set lname "met5:res" } |
| |
| RULECHECK dpsd_nw_lvt.OVL.${n} { |
| @ dpsd_nw_lvt.OVL.${n}: Illegal dpsd_nw_lvt device: dpsd_nw_lvt must not overlap ${lname} |
| OUTPUT "diode_dpsd_nw_lvt AND ${lay}" |
| } |
| incr n |
| } |
| } |
| |
| illegal_dpsd_nw_lvt [list "pwbm" "hvtp" "tunm" "rpm" "rrpm" "urpm" "polyi" "ldntm" "npc" "nsdm" "nsm" "skip_pad" "fuse" "diffres" "polyres" "lires" "LVID" "pnp" "npn" "PHdiodeID" "ENID" "COREID" "SEALID" "v5" "v12" "v20" "thkox" "polyModel" "pwde" "pwres"] |
| |
| SETLAYER diode_dpsd_nw_hvt = "((((diodeID AND psdm) AND nwell) AND diffi) AND hvtp) NOT (OR thkox v5 v12 v20 lvtn ESDID LVID)" |
| |
| #-------------------------------- |
| proc illegal_dpsd_nw_hvt {lay_list} { |
| set n 1 |
| foreach lay $lay_list { |
| set lname ${lay} |
| if {${lay} == "polyi"} { set lname "poly" } |
| if {${lay} == "diffi"} { set lname "diff" } |
| if {${lay} == "COREID"} { set lname "areaid:core" } |
| if {${lay} == "ENID"} { set lname "areaid:extendedDrain" } |
| if {${lay} == "SEALID"} { set lname "areaid:seal" } |
| if {${lay} == "LVID"} { set lname "areaid:lvNative" } |
| if {${lay} == "ESDID"} { set lname "areaid:esd" } |
| if {${lay} == "DiodeID"} { set lname "areaid:diode" } |
| if {${lay} == "PHdiodeID"} { set lname "areaid:photo" } |
| if {${lay} == "polyModel"} { set lname "poly:model" } |
| if {${lay} == "pwres"} { set lname "pwell:res" } |
| if {${lay} == "diffres"} { set lname "diff:res" } |
| if {${lay} == "polyres"} { set lname "poly:res" } |
| if {${lay} == "lires"} { set lname "li:res" } |
| if {${lay} == "m1res"} { set lname "met1:res" } |
| if {${lay} == "m2res"} { set lname "met2:res" } |
| if {${lay} == "m3res"} { set lname "met3:res" } |
| if {${lay} == "m4res"} { set lname "met4:res" } |
| if {${lay} == "m5res"} { set lname "met5:res" } |
| |
| RULECHECK dpsd_nw_hvt.OVL.${n} { |
| @ dpsd_nw_hvt.OVL.${n}: Illegal dpsd_nw_hvt device: dpsd_nw_hvt must not overlap ${lname} |
| OUTPUT "diode_dpsd_nw_hvt AND ${lay}" |
| } |
| incr n |
| } |
| } |
| |
| illegal_dpsd_nw_hvt [list "pwbm" "tunm" "thkox" "rpm" "rrpm" "urpm" "polyi" "ldntm" "npc" "nsdm" "nsm" "skip_pad" "fuse" "PHdiodeID" "ENID" "SEALID" "v5" "v12" "v20" "polyModel" "pwde" "diffres" "polyres" "pwres" "LVID" "pnp" "npn" "COREID"] |
| |
| verbatim { |
| |
| // BJT: |
| |
| } |
| |
| SETLAYER pnp1x = "(pnp INTERACT (RECTANGLE (pnp AND diffi) == 0.68 ASPECT == 1)) NOT (OR thkox v5 v12 v20)" |
| |
| #-------------------------------- |
| proc illegal_pnp {lay_list} { |
| set n 1 |
| foreach lay $lay_list { |
| set lname ${lay} |
| if {${lay} == "polyi"} { set lname "poly" } |
| if {${lay} == "diffi"} { set lname "diff" } |
| if {${lay} == "COREID"} { set lname "areaid:core" } |
| if {${lay} == "ENID"} { set lname "areaid:extendedDrain" } |
| if {${lay} == "SEALID"} { set lname "areaid:seal" } |
| if {${lay} == "LVID"} { set lname "areaid:lvNative" } |
| if {${lay} == "ESDID"} { set lname "areaid:esd" } |
| if {${lay} == "DiodeID"} { set lname "areaid:diode" } |
| if {${lay} == "PHdiodeID"} { set lname "areaid:photo" } |
| if {${lay} == "polyModel"} { set lname "poly:model" } |
| if {${lay} == "pwres"} { set lname "pwell:res" } |
| if {${lay} == "diffres"} { set lname "diff:res" } |
| if {${lay} == "polyres"} { set lname "poly:res" } |
| if {${lay} == "lires"} { set lname "li:res" } |
| if {${lay} == "m1res"} { set lname "met1:res" } |
| if {${lay} == "m2res"} { set lname "met2:res" } |
| if {${lay} == "m3res"} { set lname "met3:res" } |
| if {${lay} == "m4res"} { set lname "met4:res" } |
| if {${lay} == "m5res"} { set lname "met5:res" } |
| |
| RULECHECK pnp.OVL.${n} { |
| @ pnp.OVL.${n}: Illegal pnp device: pnp must not overlap ${lname} |
| OUTPUT "pnp1x AND ${lay}" |
| } |
| incr n |
| } |
| } |
| |
| # replaced hvtp with 'id_dummy' as this was deleted per PM 12/2/2020: |
| illegal_pnp [list "dnwell" "pwbm" "pwde" "id_dummy" "lvtn" "tunm" "thkox" "rpm" "rrpm" "urpm" "polyi" "ldntm" "npc" "nsm" "skip_pad" "fuse" "diffres" "pwres" "polyres" "polyModel" "lires" "skip_res" "skip_res" "skip_res" "skip_res" "skip_res" "LVID" "npn" "DiodeID" "PHdiodeID" "COREID" "ESDID" "ENID" "SEALID" "v5" "v12" "v20"] |
| |
| SETLAYER pnp5x = "(pnp INTERACT (RECTANGLE (pnp AND diffi) == 3.4 ASPECT == 1)) NOT (OR thkox v5 v12 v20)" |
| |
| #-------------------------------- |
| proc illegal_pnp5x {lay_list} { |
| set n 1 |
| foreach lay $lay_list { |
| set lname ${lay} |
| if {${lay} == "polyi"} { set lname "poly" } |
| if {${lay} == "diffi"} { set lname "diff" } |
| if {${lay} == "COREID"} { set lname "areaid:core" } |
| if {${lay} == "ENID"} { set lname "areaid:extendedDrain" } |
| if {${lay} == "SEALID"} { set lname "areaid:seal" } |
| if {${lay} == "LVID"} { set lname "areaid:lvNative" } |
| if {${lay} == "ESDID"} { set lname "areaid:esd" } |
| if {${lay} == "DiodeID"} { set lname "areaid:diode" } |
| if {${lay} == "PHdiodeID"} { set lname "areaid:photo" } |
| if {${lay} == "polyModel"} { set lname "poly:model" } |
| if {${lay} == "pwres"} { set lname "pwell:res" } |
| if {${lay} == "diffres"} { set lname "diff:res" } |
| if {${lay} == "polyres"} { set lname "poly:res" } |
| if {${lay} == "lires"} { set lname "li:res" } |
| if {${lay} == "m1res"} { set lname "met1:res" } |
| if {${lay} == "m2res"} { set lname "met2:res" } |
| if {${lay} == "m3res"} { set lname "met3:res" } |
| if {${lay} == "m4res"} { set lname "met4:res" } |
| if {${lay} == "m5res"} { set lname "met5:res" } |
| |
| RULECHECK pnp_5x.OVL.${n} { |
| @ pnp.OVL_5x.${n}: Illegal pnp_5x device: pnp_5x must not overlap ${lname} |
| OUTPUT "pnp5x AND ${lay}" |
| } |
| incr n |
| } |
| } |
| |
| # replaced hvtp with 'id_dummy' as this was deleted per PM 12/2/2020: |
| illegal_pnp5x [list "dnwell" "pwbm" "pwde" "id_dummy" "lvtn" "tunm" "thkox" "rpm" "rrpm" "urpm" "polyi" "ldntm" "npc" "nsm" "skip_pad" "fuse" "diffres" "pwres" "polyres" "polyModel" "lires" "skip_res" "skip_res" "skip_res" "skip_res" "skip_res" "LVID" "npn" "DiodeID" "PHdiodeID" "COREID" "ESDID" "ENID" "SEALID" "v5" "v12" "v20"] |
| |
| SETLAYER npn_ndiff = "((npn AND diffi) AND nsdm) INSIDE npn_1" |
| SETLAYER npn_emit = "npn_ndiff NOT nwell" |
| SETLAYER donut_nw = "HOLES nwell" |
| SETLAYER dnw_over_nw_hole = "dnwell ENCLOSE donut_nw" |
| SETLAYER npn_1 = "(nwell or (HOLES nwell)) ENCLOSE dnw_over_nw_hole" |
| SETLAYER npn1x = "(npn_1 ENCLOSE (AREA npn_emit == 1)) NOT (OR thkox v5 v12 v20)" |
| |
| #-------------------------------- |
| proc illegal_npn {lay_list} { |
| set n 1 |
| foreach lay $lay_list { |
| set lname ${lay} |
| if {${lay} == "polyi"} { set lname "poly" } |
| if {${lay} == "diffi"} { set lname "diff" } |
| if {${lay} == "COREID"} { set lname "areaid:core" } |
| if {${lay} == "ENID"} { set lname "areaid:extendedDrain" } |
| if {${lay} == "SEALID"} { set lname "areaid:seal" } |
| if {${lay} == "LVID"} { set lname "areaid:lvNative" } |
| if {${lay} == "ESDID"} { set lname "areaid:esd" } |
| if {${lay} == "DiodeID"} { set lname "areaid:diode" } |
| if {${lay} == "PHdiodeID"} { set lname "areaid:photo" } |
| if {${lay} == "polyModel"} { set lname "poly:model" } |
| if {${lay} == "pwres"} { set lname "pwell:res" } |
| if {${lay} == "diffres"} { set lname "diff:res" } |
| if {${lay} == "polyres"} { set lname "poly:res" } |
| if {${lay} == "lires"} { set lname "li:res" } |
| if {${lay} == "m1res"} { set lname "met1:res" } |
| if {${lay} == "m2res"} { set lname "met2:res" } |
| if {${lay} == "m3res"} { set lname "met3:res" } |
| if {${lay} == "m4res"} { set lname "met4:res" } |
| if {${lay} == "m5res"} { set lname "met5:res" } |
| |
| RULECHECK npn.OVL.${n} { |
| @ npn.OVL_5x.${n}: Illegal npn device: npn must not overlap ${lname} |
| OUTPUT "npn1x AND ${lay}" |
| } |
| incr n |
| } |
| } |
| |
| # removed ldntm per PM 12/3/20 |
| illegal_npn [list "pwbm" "pwde" "lvtn" "tunm" "rpm" "rrpm" "urpm" "nsm" "skip_pad" "fuse" "diffres" "pwres" "polyres" "polyModel" "lires" "LVID" "pnp" "DiodeID" "PHdiodeID" "COREID" "ESDID" "ENID" "SEALID" "v5" "v12" "v20" "thkox" "polyi"] |
| |
| SETLAYER npn_ndiff_oct_1 = "EXPAND EDGE (ANGLE npn_ndiff == 45) OUTSIDE BY 0.005" |
| SETLAYER npn_ndiff_oct = "(VERTEX == 8 npn_ndiff) INTERACT npn_ndiff_oct_1 == 4" |
| SETLAYER npn_v5 = "(npn_1 ENCLOSE npn_ndiff_oct) AND (thkox AND v5)" |
| |
| #-------------------------------- |
| proc illegal_npn_v5 {lay_list} { |
| set n 1 |
| foreach lay $lay_list { |
| set lname ${lay} |
| if {${lay} == "polyi"} { set lname "poly" } |
| if {${lay} == "diffi"} { set lname "diff" } |
| if {${lay} == "COREID"} { set lname "areaid:core" } |
| if {${lay} == "ENID"} { set lname "areaid:extendedDrain" } |
| if {${lay} == "SEALID"} { set lname "areaid:seal" } |
| if {${lay} == "LVID"} { set lname "areaid:lvNative" } |
| if {${lay} == "ESDID"} { set lname "areaid:esd" } |
| if {${lay} == "DiodeID"} { set lname "areaid:diode" } |
| if {${lay} == "PHdiodeID"} { set lname "areaid:photo" } |
| if {${lay} == "polyModel"} { set lname "poly:model" } |
| if {${lay} == "pwres"} { set lname "pwell:res" } |
| if {${lay} == "diffres"} { set lname "diff:res" } |
| if {${lay} == "polyres"} { set lname "poly:res" } |
| if {${lay} == "lires"} { set lname "li:res" } |
| if {${lay} == "m1res"} { set lname "met1:res" } |
| if {${lay} == "m2res"} { set lname "met2:res" } |
| if {${lay} == "m3res"} { set lname "met3:res" } |
| if {${lay} == "m4res"} { set lname "met4:res" } |
| if {${lay} == "m5res"} { set lname "met5:res" } |
| |
| RULECHECK npn_v5.OVL.${n} { |
| @ npn.OVL_v5.${n}: Illegal npn_v5 device: npn_v5 must not overlap ${lname} |
| OUTPUT "npn_v5 AND ${lay}" |
| } |
| incr n |
| } |
| } |
| |
| illegal_npn_v5 [list "pwbm" "pwde" "lvtn" "tunm" "rpm" "rrpm" "urpm" "nsm" "skip_pad" "fuse" "diffres" "pwres" "polyres" "polyModel" "lires" "LVID" "pnp" "DiodeID" "PHdiodeID" "COREID" "ESDID" "ENID" "SEALID" "v12" "v20"] |
| |
| SETLAYER npn_1x2 = "(npn_1 ENCLOSE (AREA npn_emit == 2)) NOT (OR thkox v5 v12 v20)" |
| |
| #-------------------------------- |
| proc illegal_npn_1x2 {lay_list} { |
| set n 1 |
| foreach lay $lay_list { |
| set lname ${lay} |
| if {${lay} == "polyi"} { set lname "poly" } |
| if {${lay} == "diffi"} { set lname "diff" } |
| if {${lay} == "COREID"} { set lname "areaid:core" } |
| if {${lay} == "ENID"} { set lname "areaid:extendedDrain" } |
| if {${lay} == "SEALID"} { set lname "areaid:seal" } |
| if {${lay} == "LVID"} { set lname "areaid:lvNative" } |
| if {${lay} == "ESDID"} { set lname "areaid:esd" } |
| if {${lay} == "DiodeID"} { set lname "areaid:diode" } |
| if {${lay} == "PHdiodeID"} { set lname "areaid:photo" } |
| if {${lay} == "polyModel"} { set lname "poly:model" } |
| if {${lay} == "pwres"} { set lname "pwell:res" } |
| if {${lay} == "diffres"} { set lname "diff:res" } |
| if {${lay} == "polyres"} { set lname "poly:res" } |
| if {${lay} == "lires"} { set lname "li:res" } |
| if {${lay} == "m1res"} { set lname "met1:res" } |
| if {${lay} == "m2res"} { set lname "met2:res" } |
| if {${lay} == "m3res"} { set lname "met3:res" } |
| if {${lay} == "m4res"} { set lname "met4:res" } |
| if {${lay} == "m5res"} { set lname "met5:res" } |
| |
| RULECHECK npn_1x2.OVL.${n} { |
| @ npn.OVL_1x2.${n}: Illegal npn_1x2 device: npn_1x2 must not overlap ${lname} |
| OUTPUT "npn_1x2 AND ${lay}" |
| } |
| incr n |
| } |
| } |
| |
| illegal_npn_1x2 [list "pwbm" "pwde" "lvtn" "tunm" "thkox" "polyi" "nsm" "skip_pad" "fuse" "diffres" "pwres" "polyres" "polyModel" "lires" "LVID" "pnp" "DiodeID" "PHdiodeID" "COREID" "ESDID" "ENID" "SEALID" "v5" "v12" "v20" "rpm" "rrpm" "urpm"] |
| |
| verbatim { |
| |
| // PAD: |
| |
| } |
| |
| #-------------------------------- |
| proc illegal_pad {lay_list} { |
| set n 2 |
| foreach lay $lay_list { |
| set lname ${lay} |
| if {${lay} == "polyi"} { set lname "poly" } |
| if {${lay} == "diffi"} { set lname "diff" } |
| if {${lay} == "COREID"} { set lname "areaid:core" } |
| if {${lay} == "ENID"} { set lname "areaid:extendedDrain" } |
| if {${lay} == "SEALID"} { set lname "areaid:seal" } |
| if {${lay} == "LVID"} { set lname "areaid:lvNative" } |
| if {${lay} == "ESDID"} { set lname "areaid:esd" } |
| if {${lay} == "DiodeID"} { set lname "areaid:diode" } |
| if {${lay} == "PHdiodeID"} { set lname "areaid:photo" } |
| if {${lay} == "polyModel"} { set lname "poly:model" } |
| if {${lay} == "pwres"} { set lname "pwell:res" } |
| if {${lay} == "diffres"} { set lname "diff:res" } |
| if {${lay} == "polyres"} { set lname "poly:res" } |
| if {${lay} == "lires"} { set lname "li:res" } |
| if {${lay} == "m1res"} { set lname "met1:res" } |
| if {${lay} == "m2res"} { set lname "met2:res" } |
| if {${lay} == "m3res"} { set lname "met3:res" } |
| if {${lay} == "m4res"} { set lname "met4:res" } |
| if {${lay} == "met4i"} { set lname "met4" } |
| if {${lay} == "m5res"} { set lname "met5:res" } |
| |
| RULECHECK pad.OVL.${n} { |
| @ pad.OVL.${n}: Illegal pad device: pad must not overlap ${lname} |
| OUTPUT "pad AND ${lay}" |
| } |
| incr n |
| } |
| } |
| |
| illegal_pad [list "nsm" "fuse" "SEALID" "met4i"] |
| |
| #-------------------------------- |
| proc illegal_seal {lay_list} { |
| set n 1 |
| foreach lay $lay_list { |
| set lname ${lay} |
| if {${lay} == "polyi"} { set lname "poly" } |
| if {${lay} == "diffi"} { set lname "diff" } |
| if {${lay} == "COREID"} { set lname "areaid:core" } |
| if {${lay} == "ENID"} { set lname "areaid:extendedDrain" } |
| if {${lay} == "SEALID"} { set lname "areaid:seal" } |
| if {${lay} == "LVID"} { set lname "areaid:lvNative" } |
| if {${lay} == "ESDID"} { set lname "areaid:esd" } |
| if {${lay} == "DiodeID"} { set lname "areaid:diode" } |
| if {${lay} == "PHdiodeID"} { set lname "areaid:photo" } |
| if {${lay} == "polyModel"} { set lname "poly:model" } |
| if {${lay} == "pwres"} { set lname "pwell:res" } |
| if {${lay} == "diffres"} { set lname "diff:res" } |
| if {${lay} == "polyres"} { set lname "poly:res" } |
| if {${lay} == "lires"} { set lname "li:res" } |
| if {${lay} == "m1res"} { set lname "met1:res" } |
| if {${lay} == "m2res"} { set lname "met2:res" } |
| if {${lay} == "m3res"} { set lname "met3:res" } |
| if {${lay} == "m4res"} { set lname "met4:res" } |
| if {${lay} == "m5res"} { set lname "met5:res" } |
| if {${lay} == "li_i"} { set lname "li" } |
| if {${lay} == "met1i"} { set lname "met1" } |
| if {${lay} == "met2i"} { set lname "met2" } |
| if {${lay} == "met3i"} { set lname "met3" } |
| if {${lay} == "met4i"} { set lname "met4" } |
| if {${lay} == "met5i"} { set lname "met5" } |
| |
| RULECHECK seal.OVL.${n} { |
| @ seal.OVL.${n}: Illegal seal device: areaid:seal must not overlap ${lname} |
| OUTPUT "SEALID AND ${lay}" |
| } |
| incr n |
| } |
| } |
| |
| illegal_seal [list "dnwell" "pwbm" "pwde" "nwell" "hvtp" "lvtn" "tunm" "thkox" "rpm" "rrpm" "urpm" "polyi" "ldntm" "npc" "nsdm" "psdm" "licon" "li_i" "capm" "cap2m" "met1i" "met2i" "met3i" "met4i" "met5i" "pad" "rdl" "fuse" "diffres" "pwres" "polyres" "lires" "m1res" "m2res" "m3res" "m4res" "m5res" "LVID" "pnp" "npn" "localSub" "DiodeID" "PHdiodeID" "COREID" "ESDID" "ENID" "v5" "v12" "v20" "polyModel"] |
| |
| verbatim { |
| |
| // FUSE: |
| |
| } |
| |
| ### |
| ### 6/24/2021 JAG - SWT (PM) removed fuse device |
| ### |
| #-------------------------------- |
| #proc illegal_fuse {lay_list} { |
| # set n 1 |
| # foreach lay $lay_list { |
| # set lname ${lay} |
| # if {${lay} == "polyi"} { set lname "poly" } |
| # if {${lay} == "diffi"} { set lname "diff" } |
| # if {${lay} == "COREID"} { set lname "areaid:core" } |
| # if {${lay} == "ENID"} { set lname "areaid:extendedDrain" } |
| # if {${lay} == "SEALID"} { set lname "areaid:seal" } |
| # if {${lay} == "LVID"} { set lname "areaid:lvNative" } |
| # if {${lay} == "ESDID"} { set lname "areaid:esd" } |
| # if {${lay} == "DiodeID"} { set lname "areaid:diode" } |
| # if {${lay} == "PHdiodeID"} { set lname "areaid:photo" } |
| # if {${lay} == "polyModel"} { set lname "poly:model" } |
| # if {${lay} == "pwres"} { set lname "pwell:res" } |
| # if {${lay} == "diffres"} { set lname "diff:res" } |
| # if {${lay} == "polyres"} { set lname "poly:res" } |
| # if {${lay} == "lires"} { set lname "li:res" } |
| # if {${lay} == "m1res"} { set lname "met1:res" } |
| # if {${lay} == "m2res"} { set lname "met2:res" } |
| # if {${lay} == "m3res"} { set lname "met3:res" } |
| # if {${lay} == "m4res"} { set lname "met4:res" } |
| # if {${lay} == "met4i"} { set lname "met4" } |
| # if {${lay} == "m5res"} { set lname "met5:res" } |
| # if {${lay} == "li_i"} { set lname "li" } |
| # if {${lay} == "met1i"} { set lname "met1" } |
| # if {${lay} == "met2i"} { set lname "met2" } |
| # if {${lay} == "met3i"} { set lname "met3" } |
| # if {${lay} == "met4i"} { set lname "met4" } |
| # if {${lay} == "met5i"} { set lname "met5" } |
| # |
| # RULECHECK fuse.OVL.${n} { |
| # @ fuse.OVL.${n}: Illegal fuse device: fuse must not overlap ${lname} |
| # OUTPUT "fuse AND ${lay}" |
| # } |
| # incr n |
| # } |
| #} |
| # |
| #illegal_fuse [list "diffi" "rpm" "rrpm" "urpm" "polyi" "licon" "li_i" "capm" "cap2m" "met1i" "met2i" "met3i" "met5i" "nsm" "pad" "rdl" "diffres" "pwres" "polyres" "lires" "m1res" "m2res" "m3res" "m4res" "m5res" "LVID" "pnp" "npn" "DiodeID" "PHdiodeID" "COREID" "ESDID" "ENID" "SEALID" "v5" "v12" "v20" "polyModel" "tunm"] |
| |
| verbatim { |
| |
| // ESD MOS: |
| |
| } |
| |
| SETLAYER nmos_esd_5v = "((((gate AND nsdm) AND v5) AND ESDID) AND thkox) NOT (OR v12 v20 lvtn LVID pnp npn)" |
| |
| #-------------------------------- |
| proc illegal_nmos_esd_5v {lay_list} { |
| set n 1 |
| foreach lay $lay_list { |
| set lname ${lay} |
| if {${lay} == "polyi"} { set lname "poly" } |
| if {${lay} == "diffi"} { set lname "diff" } |
| if {${lay} == "COREID"} { set lname "areaid:core" } |
| if {${lay} == "ENID"} { set lname "areaid:extendedDrain" } |
| if {${lay} == "SEALID"} { set lname "areaid:seal" } |
| if {${lay} == "LVID"} { set lname "areaid:lvNative" } |
| if {${lay} == "ESDID"} { set lname "areaid:esd" } |
| if {${lay} == "DiodeID"} { set lname "areaid:diode" } |
| if {${lay} == "PHdiodeID"} { set lname "areaid:photo" } |
| if {${lay} == "polyModel"} { set lname "poly:model" } |
| if {${lay} == "pwres"} { set lname "pwell:res" } |
| if {${lay} == "diffres"} { set lname "diff:res" } |
| if {${lay} == "polyres"} { set lname "poly:res" } |
| if {${lay} == "lires"} { set lname "li:res" } |
| if {${lay} == "m1res"} { set lname "met1:res" } |
| if {${lay} == "m2res"} { set lname "met2:res" } |
| if {${lay} == "m3res"} { set lname "met3:res" } |
| if {${lay} == "m4res"} { set lname "met4:res" } |
| if {${lay} == "met4i"} { set lname "met4" } |
| if {${lay} == "m5res"} { set lname "met5:res" } |
| |
| RULECHECK nmos_esd_5v.OVL.${n} { |
| @ nmos_esd_5v.OVL.${n}: Illegal nmos_esd_5v device: nmos_esd_5v must not overlap ${lname} |
| OUTPUT "nmos_esd_5v AND ${lay}" |
| } |
| incr n |
| } |
| } |
| |
| illegal_nmos_esd_5v [list "pwbm" "pwde" "hvtp" "lvtn" "tunm" "rpm" "rrpm" "urpm" "ldntm" "npc" "psdm" "nsm" "skip_pad" "fuse" "diffres" "pwres" "polyres" "lires" "LVID" "pnp" "npn" "DiodeID" "PHdiodeID" "COREID" "ENID" "SEALID" "v12" "v20" "nwell"] |
| |
| SETLAYER nmos_esd_nat_5v = "((((gate and nsdm) AND lvtn) AND v5) AND thkox) NOT (OR v12 v20 LVID pnp npn)" |
| |
| |
| #-------------------------------- |
| proc illegal_nmos_esd_nat_5v {lay_list} { |
| set n 1 |
| foreach lay $lay_list { |
| set lname ${lay} |
| if {${lay} == "polyi"} { set lname "poly" } |
| if {${lay} == "diffi"} { set lname "diff" } |
| if {${lay} == "COREID"} { set lname "areaid:core" } |
| if {${lay} == "ENID"} { set lname "areaid:extendedDrain" } |
| if {${lay} == "SEALID"} { set lname "areaid:seal" } |
| if {${lay} == "LVID"} { set lname "areaid:lvNative" } |
| if {${lay} == "ESDID"} { set lname "areaid:esd" } |
| if {${lay} == "DiodeID"} { set lname "areaid:diode" } |
| if {${lay} == "PHdiodeID"} { set lname "areaid:photo" } |
| if {${lay} == "polyModel"} { set lname "poly:model" } |
| if {${lay} == "pwres"} { set lname "pwell:res" } |
| if {${lay} == "diffres"} { set lname "diff:res" } |
| if {${lay} == "polyres"} { set lname "poly:res" } |
| if {${lay} == "lires"} { set lname "li:res" } |
| if {${lay} == "m1res"} { set lname "met1:res" } |
| if {${lay} == "m2res"} { set lname "met2:res" } |
| if {${lay} == "m3res"} { set lname "met3:res" } |
| if {${lay} == "m4res"} { set lname "met4:res" } |
| if {${lay} == "met4i"} { set lname "met4" } |
| if {${lay} == "m5res"} { set lname "met5:res" } |
| |
| RULECHECK nmos_esd_nat_5v.OVL.${n} { |
| @ nmos_esd_nat_5v.OVL.${n}: Illegal nmos_esd_nat_5v device: nmos_esd_nat_5v must not overlap ${lname} |
| OUTPUT "nmos_esd_nat_5v AND ${lay}" |
| } |
| incr n |
| } |
| } |
| |
| illegal_nmos_esd_nat_5v [list "pwbm" "pwde" "nwell" "hvtp" "tunm" "rpm" "rrpm" "urpm" "ldntm" "npc" "psdm" "nsm" "skip_pad" "fuse" "diffres" "pwres" "polyres" "lires" "LVID" "pnp" "npn" "DiodeID" "PHdiodeID" "COREID" "ENID" "SEALID" "v12" "v20"] |
| |
| SETLAYER nmos_esd = "((gate and nsdm) AND ESDID) NOT (OR v5 v12 v20 LVID pnp npn lvtn)" |
| |
| |
| #-------------------------------- |
| proc illegal_nmos_esd {lay_list} { |
| set n 1 |
| foreach lay $lay_list { |
| set lname ${lay} |
| if {${lay} == "polyi"} { set lname "poly" } |
| if {${lay} == "diffi"} { set lname "diff" } |
| if {${lay} == "COREID"} { set lname "areaid:core" } |
| if {${lay} == "ENID"} { set lname "areaid:extendedDrain" } |
| if {${lay} == "SEALID"} { set lname "areaid:seal" } |
| if {${lay} == "LVID"} { set lname "areaid:lvNative" } |
| if {${lay} == "ESDID"} { set lname "areaid:esd" } |
| if {${lay} == "DiodeID"} { set lname "areaid:diode" } |
| if {${lay} == "PHdiodeID"} { set lname "areaid:photo" } |
| if {${lay} == "polyModel"} { set lname "poly:model" } |
| if {${lay} == "pwres"} { set lname "pwell:res" } |
| if {${lay} == "diffres"} { set lname "diff:res" } |
| if {${lay} == "polyres"} { set lname "poly:res" } |
| if {${lay} == "lires"} { set lname "li:res" } |
| if {${lay} == "m1res"} { set lname "met1:res" } |
| if {${lay} == "m2res"} { set lname "met2:res" } |
| if {${lay} == "m3res"} { set lname "met3:res" } |
| if {${lay} == "m4res"} { set lname "met4:res" } |
| if {${lay} == "met4i"} { set lname "met4" } |
| if {${lay} == "m5res"} { set lname "met5:res" } |
| |
| RULECHECK nmos_esd.OVL.${n} { |
| @ nmos_esd.OVL.${n}: Illegal nmos_esd device: nmos_esd must not overlap ${lname} |
| OUTPUT "nmos_esd AND ${lay}" |
| } |
| incr n |
| } |
| } |
| |
| illegal_nmos_esd [list "pwbm" "pwde" "hvtp" "lvtn" "tunm" "rpm" "rrpm" "urpm" "ldntm" "npc" "psdm" "nsm" "skip_pad" "fuse" "LVID" "pnp" "npn" "DiodeID" "PHdiodeID" "COREID" "ENID" "SEALID" "v5" "v12" "v20" "nwell" "thkox"] |
| |
| SETLAYER pmos_esd_5v = "((((gate and psdm) AND v5) AND ESDID) AND thkox) NOT (OR v12 v20 LVID npn pnp ENID)" |
| |
| #-------------------------------- |
| proc illegal_pmos_esd_5v {lay_list} { |
| set n 1 |
| foreach lay $lay_list { |
| set lname ${lay} |
| if {${lay} == "polyi"} { set lname "poly" } |
| if {${lay} == "diffi"} { set lname "diff" } |
| if {${lay} == "COREID"} { set lname "areaid:core" } |
| if {${lay} == "ENID"} { set lname "areaid:extendedDrain" } |
| if {${lay} == "SEALID"} { set lname "areaid:seal" } |
| if {${lay} == "LVID"} { set lname "areaid:lvNative" } |
| if {${lay} == "ESDID"} { set lname "areaid:esd" } |
| if {${lay} == "DiodeID"} { set lname "areaid:diode" } |
| if {${lay} == "PHdiodeID"} { set lname "areaid:photo" } |
| if {${lay} == "polyModel"} { set lname "poly:model" } |
| if {${lay} == "pwres"} { set lname "pwell:res" } |
| if {${lay} == "diffres"} { set lname "diff:res" } |
| if {${lay} == "polyres"} { set lname "poly:res" } |
| if {${lay} == "lires"} { set lname "li:res" } |
| if {${lay} == "m1res"} { set lname "met1:res" } |
| if {${lay} == "m2res"} { set lname "met2:res" } |
| if {${lay} == "m3res"} { set lname "met3:res" } |
| if {${lay} == "m4res"} { set lname "met4:res" } |
| if {${lay} == "met4i"} { set lname "met4" } |
| if {${lay} == "m5res"} { set lname "met5:res" } |
| |
| RULECHECK pmos_esd_5v.OVL.${n} { |
| @ pmos_esd_5v.OVL.${n}: Illegal pmos_esd_5v device: pmos_esd_5v must not overlap ${lname} |
| OUTPUT "pmos_esd_5v AND ${lay}" |
| } |
| incr n |
| } |
| } |
| |
| illegal_pmos_esd_5v [list "pwbm" "pwde" "hvtp" "lvtn" "tunm" "rpm" "rrpm" "urpm" "ldntm" "npc" "nsdm" "nsm" "skip_pad" "fuse" "diffres" "pwres" "polyres" "lires" "LVID" "pnp" "npn" "DiodeID" "PHdiodeID" "COREID" "ENID" "SEALID" "v12" "v20" "polyModel"] |
| |
| SETLAYER nsd_pw_esd = "((((diodeID AND nsdm) NOT nwell) AND diffi) AND ESDID) NOT (OR v5 v12 v20 lvtn hvtp LVID)" |
| |
| #-------------------------------- |
| proc illegal_nsd_pw_esd {lay_list} { |
| set n 1 |
| foreach lay $lay_list { |
| set lname ${lay} |
| if {${lay} == "polyi"} { set lname "poly" } |
| if {${lay} == "diffi"} { set lname "diff" } |
| if {${lay} == "COREID"} { set lname "areaid:core" } |
| if {${lay} == "ENID"} { set lname "areaid:extendedDrain" } |
| if {${lay} == "SEALID"} { set lname "areaid:seal" } |
| if {${lay} == "LVID"} { set lname "areaid:lvNative" } |
| if {${lay} == "ESDID"} { set lname "areaid:esd" } |
| if {${lay} == "DiodeID"} { set lname "areaid:diode" } |
| if {${lay} == "PHdiodeID"} { set lname "areaid:photo" } |
| if {${lay} == "polyModel"} { set lname "poly:model" } |
| if {${lay} == "pwres"} { set lname "pwell:res" } |
| if {${lay} == "diffres"} { set lname "diff:res" } |
| if {${lay} == "polyres"} { set lname "poly:res" } |
| if {${lay} == "lires"} { set lname "li:res" } |
| if {${lay} == "m1res"} { set lname "met1:res" } |
| if {${lay} == "m2res"} { set lname "met2:res" } |
| if {${lay} == "m3res"} { set lname "met3:res" } |
| if {${lay} == "m4res"} { set lname "met4:res" } |
| if {${lay} == "met4i"} { set lname "met4" } |
| if {${lay} == "m5res"} { set lname "met5:res" } |
| |
| RULECHECK dnsd_pw_esd.OVL.${n} { |
| @ nsd_pw_esd.OVL.${n}: Illegal nsd_pw_esd device: nsd_pw_esd must not overlap ${lname} |
| OUTPUT "nsd_pw_esd AND ${lay}" |
| } |
| incr n |
| } |
| } |
| |
| illegal_nsd_pw_esd [list "pwbm" "hvtp" "lvtn" "tunm" "thkox" "psdm" "nsm" "skip_pad" "fuse" "diffres" "pwres" "polyres" "lires" "LVID" "pnp" "npn" "PHdiodeID" "COREID" "ENID" "SEALID" "v5" "v12" "v20" "nwell" "polyi" "polyModel"] |
| |
| SETLAYER psd_nw_esd = "((((diodeID AND psdm) AND nwell) AND diffi) AND ESDID) NOT (OR v5 v12 v20 lvtn hvtp LVID)" |
| |
| #-------------------------------- |
| proc illegal_psd_nw_esd {lay_list} { |
| set n 1 |
| foreach lay $lay_list { |
| set lname ${lay} |
| if {${lay} == "polyi"} { set lname "poly" } |
| if {${lay} == "diffi"} { set lname "diff" } |
| if {${lay} == "COREID"} { set lname "areaid:core" } |
| if {${lay} == "ENID"} { set lname "areaid:extendedDrain" } |
| if {${lay} == "SEALID"} { set lname "areaid:seal" } |
| if {${lay} == "LVID"} { set lname "areaid:lvNative" } |
| if {${lay} == "ESDID"} { set lname "areaid:esd" } |
| if {${lay} == "DiodeID"} { set lname "areaid:diode" } |
| if {${lay} == "PHdiodeID"} { set lname "areaid:photo" } |
| if {${lay} == "polyModel"} { set lname "poly:model" } |
| if {${lay} == "pwres"} { set lname "pwell:res" } |
| if {${lay} == "diffres"} { set lname "diff:res" } |
| if {${lay} == "polyres"} { set lname "poly:res" } |
| if {${lay} == "lires"} { set lname "li:res" } |
| if {${lay} == "m1res"} { set lname "met1:res" } |
| if {${lay} == "m2res"} { set lname "met2:res" } |
| if {${lay} == "m3res"} { set lname "met3:res" } |
| if {${lay} == "m4res"} { set lname "met4:res" } |
| if {${lay} == "met4i"} { set lname "met4" } |
| if {${lay} == "m5res"} { set lname "met5:res" } |
| |
| RULECHECK dpsd_nw_esd.OVL.${n} { |
| @ psd_nw_esd.OVL.${n}: Illegal psd_nw_esd device: psd_nw_esd must not overlap ${lname} |
| OUTPUT "psd_nw_esd AND ${lay}" |
| } |
| incr n |
| } |
| } |
| |
| illegal_psd_nw_esd [list "pwbm" "hvtp" "lvtn" "tunm" "thkox" "polyi" "nsdm" "nsm" "skip_pad" "fuse" "diffres" "pwres" "polyres" "lires" "LVID" "pnp" "npn" "PHdiodeID" "COREID" "ENID" "SEALID" "v5" "v12" "v20" "polyModel"] |
| |
| SETLAYER nsd_pw_esd_v5_a = "diodeID AND nsdm" |
| SETLAYER nsd_pw_esd_v5_b = "nsd_pw_esd_v5_a NOT nwell" |
| SETLAYER nsd_pw_esd_v5_c = "nsd_pw_esd_v5_b AND diffi" |
| SETLAYER nsd_pw_esd_v5_d = "nsd_pw_esd_v5_c AND ESDID" |
| SETLAYER nsd_pw_esd_v5_e = "nsd_pw_esd_v5_d AND v5" |
| SETLAYER nsd_pw_esd_v5_f = "nsd_pw_esd_v5_e AND thkox" |
| SETLAYER nsd_pw_esd_v5 = "nsd_pw_esd_v5_f NOT (OR v12 v20 lvtn hvtp LVID)" |
| |
| #-------------------------------- |
| proc illegal_nsd_pw_esd_v5 {lay_list} { |
| set n 1 |
| foreach lay $lay_list { |
| set lname ${lay} |
| if {${lay} == "polyi"} { set lname "poly" } |
| if {${lay} == "diffi"} { set lname "diff" } |
| if {${lay} == "COREID"} { set lname "areaid:core" } |
| if {${lay} == "ENID"} { set lname "areaid:extendedDrain" } |
| if {${lay} == "SEALID"} { set lname "areaid:seal" } |
| if {${lay} == "LVID"} { set lname "areaid:lvNative" } |
| if {${lay} == "ESDID"} { set lname "areaid:esd" } |
| if {${lay} == "DiodeID"} { set lname "areaid:diode" } |
| if {${lay} == "PHdiodeID"} { set lname "areaid:photo" } |
| if {${lay} == "polyModel"} { set lname "poly:model" } |
| if {${lay} == "pwres"} { set lname "pwell:res" } |
| if {${lay} == "diffres"} { set lname "diff:res" } |
| if {${lay} == "polyres"} { set lname "poly:res" } |
| if {${lay} == "lires"} { set lname "li:res" } |
| if {${lay} == "m1res"} { set lname "met1:res" } |
| if {${lay} == "m2res"} { set lname "met2:res" } |
| if {${lay} == "m3res"} { set lname "met3:res" } |
| if {${lay} == "m4res"} { set lname "met4:res" } |
| if {${lay} == "met4i"} { set lname "met4" } |
| if {${lay} == "m5res"} { set lname "met5:res" } |
| |
| RULECHECK dnsd_pw_esd_v5.OVL.${n} { |
| @ nsd_pw_esd_v5.OVL.${n}: Illegal nsd_pw_esd_v5 device: nsd_pw_esd_v5 must not overlap ${lname} |
| OUTPUT "nsd_pw_esd_v5 AND ${lay}" |
| } |
| incr n |
| } |
| } |
| |
| illegal_nsd_pw_esd_v5 [list "skip_dnw" "pwbm" "nwell" "hvtp" "lvtn" "tunm" "rpm" "rrpm" "urpm" "polyi" "psdm" "nsm" "skip_pad" "fuse" "diffres" "pwres" "polyres" "lires" "LVID" "pnp" "npn" "PHdiodeID" "COREID" "ENID" "SEALID" "v12" "v20" "polyModel"] |
| |
| SETLAYER psd_nw_esd_v5_a = "diodeID AND psdm" |
| SETLAYER psd_nw_esd_v5_b = "psd_nw_esd_v5_a AND nwell" |
| SETLAYER psd_nw_esd_v5_c = "psd_nw_esd_v5_b AND diffi" |
| SETLAYER psd_nw_esd_v5_d = "psd_nw_esd_v5_c AND ESDID" |
| SETLAYER psd_nw_esd_v5_e = "psd_nw_esd_v5_d AND v5" |
| SETLAYER psd_nw_esd_v5_f = "psd_nw_esd_v5_e AND thkox" |
| SETLAYER psd_nw_esd_v5 = "psd_nw_esd_v5_f NOT (OR v12 v20 lvtn hvtp LVID)" |
| |
| #-------------------------------- |
| proc illegal_psd_nw_esd_v5 {lay_list} { |
| set n 1 |
| foreach lay $lay_list { |
| set lname ${lay} |
| if {${lay} == "polyi"} { set lname "poly" } |
| if {${lay} == "diffi"} { set lname "diff" } |
| if {${lay} == "COREID"} { set lname "areaid:core" } |
| if {${lay} == "ENID"} { set lname "areaid:extendedDrain" } |
| if {${lay} == "SEALID"} { set lname "areaid:seal" } |
| if {${lay} == "LVID"} { set lname "areaid:lvNative" } |
| if {${lay} == "ESDID"} { set lname "areaid:esd" } |
| if {${lay} == "DiodeID"} { set lname "areaid:diode" } |
| if {${lay} == "PHdiodeID"} { set lname "areaid:photo" } |
| if {${lay} == "polyModel"} { set lname "poly:model" } |
| if {${lay} == "pwres"} { set lname "pwell:res" } |
| if {${lay} == "diffres"} { set lname "diff:res" } |
| if {${lay} == "polyres"} { set lname "poly:res" } |
| if {${lay} == "lires"} { set lname "li:res" } |
| if {${lay} == "m1res"} { set lname "met1:res" } |
| if {${lay} == "m2res"} { set lname "met2:res" } |
| if {${lay} == "m3res"} { set lname "met3:res" } |
| if {${lay} == "m4res"} { set lname "met4:res" } |
| if {${lay} == "met4i"} { set lname "met4" } |
| if {${lay} == "m5res"} { set lname "met5:res" } |
| |
| RULECHECK dpsd_nw_esd_v5.OVL.${n} { |
| @ psd_nw_esd_v5.OVL.${n}: Illegal psd_nw_esd_v5 device: psd_nw_esd_v5 must not overlap ${lname} |
| OUTPUT "psd_nw_esd_v5 AND ${lay}" |
| } |
| incr n |
| } |
| } |
| |
| illegal_psd_nw_esd_v5 [list "pwbm" "hvtp" "lvtn" "tunm" "rpm" "rrpm" "urpm" "polyi" "nsdm" "nsm" "skip_pad" "fuse" "diffres" "pwres" "polyres" "lires" "LVID" "pnp" "npn" "PHdiodeID" "COREID" "ENID" "SEALID" "v12" "v20" "polyModel"] |
| |
| verbatim { |
| #ENDIF |
| // end illegal device checks |
| |
| } |
| |
| verbatim { |
| |
| // |
| // Fill checks |
| // |
| |
| } |
| |
| proc fill_no_touch_dwg {lay_list} { |
| |
| set a 1 |
| |
| foreach lay $lay_list { |
| |
| if {${lay} == "diff"} { set lname "diff" } |
| if {${lay} == "poly"} { set lname "poly" } |
| if {${lay} == "m1"} { set lname "met1" } |
| if {${lay} == "m2"} { set lname "met2" } |
| if {${lay} == "m3"} { set lname "met3" } |
| if {${lay} == "m4"} { set lname "met4" } |
| if {${lay} == "m5"} { set lname "met5" } |
| |
| if {${lay} == "diff"} { set lay2 "diffii" } |
| if {${lay} == "poly"} { set lay2 "polyii" } |
| if {${lay} == "m1"} { set lay2 "met1ii" } |
| if {${lay} == "m2"} { set lay2 "met2ii" } |
| if {${lay} == "m3"} { set lay2 "met3ii" } |
| if {${lay} == "m4"} { set lay2 "met4ii" } |
| if {${lay} == "m5"} { set lay2 "met5ii" } |
| |
| RULECHECK fill.OVL.${a} { |
| @ fill.OVL.${a}: Layer ${lay}_fill must be outside ${lname}/drawing |
| OUTPUT "${lay}_fill AND ${lay2}" |
| } |
| |
| incr a |
| |
| } |
| } |
| |
| fill_no_touch_dwg [list "diff" "poly" "li" "m1" "m2" "m3" "m4" "m5"] |
| |
| RULECHECK fill.CON.1 { |
| @ fill.CON.1: Layer diff_fill must float |
| OUTPUT "(diff_fill NOT (OR critSide ccorner)) INTERACT licon" |
| } |
| |
| RULECHECK fill.CON.2 { |
| @ fill.CON.2: Layer poly_fill must float |
| OUTPUT "(poly_fill NOT (OR critSide ccorner)) INTERACT licon" |
| } |
| |
| RULECHECK fill.CON.3 { |
| @ fill.CON.3: Layer li_fill must float |
| OUTPUT "(li_fill NOT (OR critSide ccorner)) INTERACT licon" |
| OUTPUT "(li_fill NOT (OR critSide ccorner)) INTERACT mcon" |
| } |
| |
| RULECHECK fill.CON.4 { |
| @ fill.CON.4: Layer m1_fill must float |
| OUTPUT "(m1_fill NOT (OR critSide ccorner)) INTERACT mcon" |
| OUTPUT "(m1_fill NOT (OR critSide ccorner)) INTERACT via1" |
| } |
| |
| RULECHECK fill.CON.5 { |
| @ fill.CON.5: Layer m2_fill must float |
| OUTPUT "(m2_fill NOT (OR critSide ccorner)) INTERACT via1" |
| OUTPUT "(m2_fill NOT (OR critSide ccorner)) INTERACT via2" |
| } |
| |
| RULECHECK fill.CON.6 { |
| @ fill.CON.6: Layer m3_fill must float |
| OUTPUT "(m3_fill NOT (OR critSide ccorner)) INTERACT via2" |
| OUTPUT "(m3_fill NOT (OR critSide ccorner)) INTERACT via3" |
| } |
| |
| RULECHECK fill.CON.7 { |
| @ fill.CON.7: Layer m4_fill must float |
| OUTPUT "(m4_fill NOT (OR critSide ccorner)) INTERACT via3" |
| OUTPUT "(m4_fill NOT (OR critSide ccorner)) INTERACT via4" |
| } |
| |
| RULECHECK fill.CON.8 { |
| @ fill.CON.8: Layer m5_fill must float |
| OUTPUT "m5_fill INTERACT via4" |
| } |
