blob: 3183a43b06b87537da8198e29f23c9ab3e8f7d9b [file] [log] [blame]
;;;
;;; $Id: tech.env 1 2018/02/19 21:34:13 GMT jszemiot Exp $
;;;
;;; tech.env
;;;
;;; Copyright (c) 2012 by Cypress Semiconductor
;;; Cypress Kentucky CAD Center (KYCC)
;;;
;;; Date : Apr 17, 2012
;;; Author: Srabosti Datta (osd) @ KYCC
;;;
;;; Description:
;;;
;;; Revision History:
;;;
;;;
;;; osd 04/17/12 new file
;;; mmwn 01/23/13 removing recommended_rules from drc
;;; mmwn 02/18/13 removing recommended_rules from latchup
;;; mmwn 12/19/13 TDR CZ - Adding nfet_in_dnwell for drc
;;; mmwn 02/14/14 TDR DA - Adding notPublicCell
;;; mmwn 03/06/14 TDR DB - Removing pmm from default CLDRC
;;; kuc 10/02/14 TDR rev DH, adding subiso_recommended to latchup, luRes
;;; cva 2015-06-01 TDR rev DR, hvnvtm removal
;;; cva 2015-08-19 TDR rev DV, waffle_mm5
;;; cva 2015-10-30 SHV net addition to form
;;;
;; maskadd/drop defaults
;;;These are here for (CALIBRE, current physver tool)
verification maskLayers string "fom dnm nwm lvtnm hvtpm tunm onom lvom p1m ntm hvntm ldntm npcm nsdm psdm licm1 li1m ctm1 mm1 vim mm2 vim2 mm3 nsm vim3 mm4 vim4 mm5 pdm pbo cu1m rpm pmm2 hvtrm"
verification maskAddLayers string "fom p1m nsdm psdm licm1 li1m hvtpm lvtnm ntm"
verification maskDropLayers string "fom p1m nsdm psdm licm1 li1m hvtpm lvtnm ntm"
verification streamNetLayers string "dnwell nwell tap licon1 li1 mcon met1 via met2 via2 met3 via3 met4 via4 met5 rdl"
verification streamNetSwitches string "mult_sub local_sub filter"
verification cldrcDefaultSwitches string "no_opc"
verification cldrcInvalidSwitches string "no_opc"
verification cldrcSwitches string "waffle_chip waffle_frame no_chrome no_opc photo_PD fom_30pd fom_35pd mm1_70opd mm2_70opd mm3_70opd mm4_70opd waffle_mm5"
verification drcSwitches string "fine_pitch padfuse_only no_padfuse no_cldrc floating_labels IP_block nfet_in_dnwell notPublicCell"
verification drcInvalidSwitches string "notPublicCell"
verification latchupSwitches string "local_sub block_level OLD_TAPPING_RULE_RevU active_esd exemptTextOff subiso_recommended"
verification latchupInvalidSwitches string "block_level OLD_TAPPING_RULE_RevU"
verification latchupIPvalidSwitches string "block_level"
verification latchupDefaultSwitches string ""
verification luResSwitches string "block_level subiso_recommended"
verification luResDefaultSwitches string ""
verification stressSwitches string "critCornerReg NoCritSideReg deadZoneReg"
verification stressDefaultSwitches string ""
verification lvsExtSwitches string "local_sub"
verification lvsExtDefaultSwitches string ""
calibre graphicalViewEnable boolean t
calibre starRCFlowEnable boolean t
calibre bridgeDFTEnable boolean t
verification softSwitches string "local_sub"
verification latchupTechSpecificNets string "Inp_PadNets_5v:Inp Pad Nets(5v)@OuporIo_PadNets_5v:Output or IO Pad Nets(5v)@Vpp_pad:Vpp pad@esd7_6Nets:Esd 7_6Nets@esd8_4Nets:Esd 8_4Nets@Main_Ground_Supply:Main Ground Supply@Main_Power_Supply:Main Power Supply@Power_Net_Lv:Lv Power Supply(1.8v)@Power_Net_Hv:Hv Power Supply(3.3 or 5v)@Pwr_Gnd_Pairs:Power Ground Pairs@VCSEL_pairs:VCSEL driver pairs@Power_Net_SHV:SHV Power Nets(5.5v)"
;; LOD comparison
compareLOD tolerance float 0.2