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// 2020/05/14 Suriono (UZMN)
// Why : "mult" is not an industry standard
// What : Replace "mult" by "m"
*Auto-converted /home/ped/ethel_disk1/ped/modelwa/s8dia_3.1/spectrexlate_s8dia_3.4_beta1/spectremodels/xcmvpp.mod by model_spectre_vppmaker.rb
// converted from amsmodels/xcmvpp.mod
simulator lang=spectre
// spectre mismatch params here
parameters xcmvpp2_nmos_nat_v510x4_slope = 0.0
parameters xcmvpp2_pmos_v55x4_slope = 0.0
statistics {
mismatch {
vary xcmvpp2_nmos_nat_v510x4_slope dist=gauss std=0.00914
vary xcmvpp2_pmos_v55x4_slope dist=gauss std=0.00914
}
}
inline subckt xcmvpp2_nmos_nat_v510x4 (c0 c1 b)
parameters
+ lvpp = 3.6 wm1 = 0.14 wm2 = 0.14 wli = 0.17
+ ctot_a = 0.988e-15*lvpp*lvpp*cvpp2_nmos_nat_v510x4_cor + 1.04204/sqrt(m/0.35036)*xcmvpp2_nmos_nat_v510x4_slope*0.988e-15*lvpp*lvpp*cvpp2_nmos_nat_v510x4_cor
// **Note: The dev/gauss for this assumes only m=1 because this device is black boxed; if copying this line to a similar vpp then an m-factor must be added to the end of the dev/gauss. See other VPP's as an example
+ rat_m2 = 0.4325
+ rat_m1 = 0.3175
+ rat_li = 0.25
+ cap_m2 = rat_m2*ctot_a
+ cap_m1 = rat_m1*ctot_a
+ cap_li = rat_li*ctot_a
+ caps_li = cvpp2_nmos_nat_v510x4_sub
+ nvia = 11 // Each side
+ ncon = 10 // Each side
+ nf = 6 // Each side
rm21 (c0 a1) resistor r = 2*rm2_rsh*lvpp/wm2*(1/3)*(1/nf)
xcmvpp2_nmos_nat_v510x4 (a1 c1) capacitor c = cap_m2
rvia1 (c0 d0) resistor r = rcvia/nvia
rvia2 (c1 d1) resistor r = rcvia/nvia
rm11 (d0 b1) resistor r = 2*rm1_rsh*lvpp/wm1*(1/3)*(1/nf)
cm1 (b1 d1) capacitor c = cap_m1
rcon1 (d0 e0) resistor r = rcl1/ncon
rcon2 (d1 e1) resistor r = rcl1/ncon
rli1 (e0 f1) resistor r = 2*rl1*lvpp/wli*(1/3)*(1/nf)
cli (f1 e1) capacitor c = cap_li
csli1 (e0 b) capacitor c = caps_li
csli2 (e1 b) capacitor c = caps_li
ends xcmvpp2_nmos_nat_v510x4
inline subckt xcmvpp2_pmos_v55x4 (c0 c1 b)
parameters
+ lvpp = 3.6 wm1 = 0.14 wm2 = 0.14 wli = 0.17
+ ctot_a = 0.988e-15*lvpp*lvpp*cvpp2_pmos_v55x4_cor + 1.04204/sqrt(m/0.35036)*xcmvpp2_pmos_v55x4_slope*0.988e-15*lvpp*lvpp*cvpp2_pmos_v55x4_cor
// **Note: The dev/gauss for this assumes only m=1 because this device is black boxed; if copying this line to a similar vpp then an m-factor must be added to the end of the dev/gauss. See other VPP's as an example
+ rat_m2 = 0.4325
+ rat_m1 = 0.3175
+ rat_li = 0.25
+ cap_m2 = rat_m2*ctot_a
+ cap_m1 = rat_m1*ctot_a
+ cap_li = rat_li*ctot_a
+ caps_li = cvpp2_pmos_v55x4_sub
+ nvia = 11 // Each side
+ ncon = 10 // Each side
+ nf = 6 // Each side
rm21 (c0 a1) resistor r = 2*rm2_rsh*lvpp/wm2*(1/3)*(1/nf)
xcmvpp2_pmos_v55x4 (a1 c1) capacitor c = cap_m2
rvia1 (c0 d0) resistor r = rcvia/nvia
rvia2 (c1 d1) resistor r = rcvia/nvia
rm11 (d0 b1) resistor r = 2*rm1_rsh*lvpp/wm1*(1/3)*(1/nf)
cm1 (b1 d1) capacitor c = cap_m1
rcon1 (d0 e0) resistor r = rcl1/ncon
rcon2 (d1 e1) resistor r = rcl1/ncon
rli1 (e0 f1) resistor r = 2*rl1*lvpp/wli*(1/3)*(1/nf)
cli (f1 e1) capacitor c = cap_li
csli1 (e0 b) capacitor c = caps_li
csli2 (e1 b) capacitor c = caps_li
ends xcmvpp2_pmos_v55x4