| // 2020/03/09 Suriono |
| // Why : New S130 models for S130 PDK |
| // What : Remove "mult" and "mf" parameters, it is not used anymore. |
| // =========================================================== |
| |
| **************************************************************** |
| *Subckt Model to allow adition of non-linear resistor model and gate-drain capacitance model |
| ******* |
| * pmos_de_v12 * |
| ******* |
| simulator lang = spice |
| .subckt pmos_de_v12 d g s b w=5.0 l=0.66 ad=0 as=0 pd=0 ps=0.0 nrd=0 nrs=0 sa=0.28 sb=1.19 sd=0 |
| .param rdiff='8.900000e+003*pmos_de_v12_rdiff_mult' |
| .param rdiff_tc1=2.500000e-003 |
| .param rdiff_tc2=2.200000e-006 |
| ****sb fixed value based on TDR rule depmos.6, for hardcoded number in CAD flow |
| .param sb_cadfixedvalue_pmos_de_v12=1.19 |
| ***sd intentionally left out for pmos_de_v12 devices because poly-poly spacing not uniform in DE FET |
| main1 d1 g s b pmos_de_v12_base w=w l=l ad=0 as=as pd=0 ps=ps nrd=nrd nrs=nrs sa=sa sb=sb_cadfixedvalue_pmos_de_v12 |
| *rldd d d1 '(1/w)*rdiff' tc1='rdiff_tc1' tc2='rdiff_tc2' |
| rldd d d1 '(1/w)*rdiff' tc1='rdiff_tc1' tc2='rdiff_tc2' |
| dnw1 d b dnwdiode_pmos_de_v12 area='ad/2' pj='pd/2' |
| dnw2 d1 b dnwdiode_pmos_de_v12 area='ad/2' pj='pd/2' |
| .ends pmos_de_v12 |
