| //Verilog HDL for "s8fmlt64k", "s8fmlt64k_saendel1" "behavioral" |
| |
| `timescale 1ns/1ps |
| module s8fmlt64k_saendel1 ( out, in, nbias, pbias, rst1, vgnd, vpwr ); |
| |
| input vpwr; |
| input nbias; |
| input in; |
| input vgnd; |
| input rst1; |
| input pbias; |
| output out; |
| |
| wire supply_ok = (vgnd===1'b0) & (vpwr===1'b1); |
| reg rout; |
| |
| assign out = supply_ok ? rout : 1'bx; |
| |
| always @ (rst1 or nbias or pbias or in) |
| begin // { |
| #0.1; |
| if (rst1 === 1'b1) |
| begin // { |
| rout = 1'b0; |
| end // } |
| else if ((rst1 === 1'b0) && (nbias === 1'b1) && (pbias === 1'b0)) |
| begin // { |
| #7.5 rout = in; |
| end // } |
| else |
| begin // { |
| //rout = 1'bx; //leakage prevents the x |
| end // } |
| end // } |
| |
| endmodule |
