| * |
| ************************************************************************ |
| * Copyright (c) 2013 by Cypress Semiconductor |
| * Cypress Confidential Information |
| ************************************************************************ |
| * |
| * Wed Feb 27 13:54:42 -0700 2013 |
| * |
| * Technology Information |
| * FLOW s8pf-10r |
| * TDR 001-01905/CN |
| * EDR nil/nil |
| * MTDR 001-69087/*F |
| * PAD/STRESS 01-70004/AV |
| * ESDMTDR 001-67310/*D |
| * RELIABILITY 001-09864/*I |
| * MODELS models.3.5 |
| * |
| * Explicit Options |
| * s8fmlt_preboot layout s8fmlt_preboot schematic -extViewName extracted -checkExtraFeedthroughs |
| * NO -lib2 s8fmlt -metopDefault -lsf_R type==X86_64&&maxmem>480 -abortRcxIfLvsDirty |
| * -excludeNets vgnd vpwr vpb vnb READ2 VNEG_C read -gndNode vgnd -runDir |
| * /proj/verify/cxz/s8fmlt_preboot/extLvs -bsub -coupFactor 1 -noGndCaps -noLog |
| * -formLog -decouplingThreshold 5 -compareShortElements YES -xcal_maxd_mode |
| * custom -remote -noReplay -join -noTcoeff -lib s8fmlt -metopLayer met3 -lvsCorrespondencePoints |
| * minimum -cdslib /disks/zulu_disk1/cxz/WA/cxz_s8fmlt_dev_45/cds.lib -unshortDevPinR |
| * 0.0001 -LVS -reduceRonly -accuracyTICER 4.0 -drcMaxResults 20000 -fminTICER |
| * 2.0 -SPICE -isolateShortsIn ALL |
| * |
| * Platform Information |
| * // Calibre v2009.2_27.17 Fri Jun 5 14:24:13 PDT 2009 |
| * Linux dfuchsia4 2.6.18-308.4.1.el5 #1 SMP Tue Apr 17 17:08:00 EDT 2012 x86_64 x86_64 x86_64 GNU/Linux |
| * |
| * Nominal Temperature: 27C |
| * Circuit Temperature: 27C |
| * |
| .subckt s8fmlt_preboot vgnd vnb aclk VNEG_C vpb vpwr read READ2 |
| + preboot |
| * |
| * preboot preboot |
| * aclk aclk |
| * |
| * Net Section |
| * |
| *|NET Xpreboot_gen/XI13/net12 8.84907e-17 |
| cg_1 Xpreboot_gen/XI13/net12 vgnd 8.84907e-17 |
| * |
| *|NET Xpreboot_gen/XI11/net13 8.33904e-17 |
| cg_2 Xpreboot_gen/XI11/net13 vgnd 8.33904e-17 |
| * |
| *|NET aclk 1.54318e-15 |
| caclk/0 aclk#33 vgnd 2.78398e-16 |
| caclk/1 aclk#29 vgnd 1.92936e-16 |
| caclk/2 Xpreboot_gen/XI9/Mn0__2#g vgnd 6.6499e-16 |
| caclk/3 Xpreboot_gen/XI9/Mn0#g vgnd 2.23376e-16 |
| caclk/4 Xpreboot_gen/XI9/Mp0#g vgnd 1.83483e-16 |
| raclk/5 aclk#45 aclk#47 12.862 |
| raclk/6 aclk aclk#45 19.5566 |
| raclk/7 aclk aclk#47 5.5876 |
| raclk/8 aclk#33 aclk#35 51.5128 |
| raclk/9 aclk#33 aclk#47 85.9106 |
| raclk/10 aclk#29 aclk#31 51.5128 |
| raclk/11 aclk#29 aclk#45 72.9892 |
| raclk/12 aclk#29 aclk#33 77.1257 |
| raclk/13 Xpreboot_gen/XI9/Mn0__2#g aclk#35 1797.24 |
| raclk/14 Xpreboot_gen/XI9/Mp0__2#g aclk#31 1084.5 |
| raclk/15 Xpreboot_gen/XI9/Mn0#g aclk#35 1797.24 |
| raclk/16 Xpreboot_gen/XI9/Mp0#g aclk#31 1084.5 |
| * |
| *|NET preboot1 5.62863e-14 |
| cpreboot1/273 preboot1#278 vgnd 2.15529e-16 |
| cpreboot1/274 preboot1#274 vgnd 4.91839e-16 |
| cpreboot1/275 preboot1#265 vgnd 2.14795e-16 |
| cpreboot1/276 preboot1#261 vgnd 4.85375e-16 |
| cpreboot1/277 preboot1#253 vgnd 1.8568e-15 |
| cpreboot1/278 preboot1#251 vgnd 1.10156e-15 |
| cpreboot1/279 preboot1#218 vgnd 3.46785e-16 |
| cpreboot1/280 Xpreboot_gen/XI8/M7__3#d vgnd 5.06184e-16 |
| cpreboot1/281 Xpreboot_gen/XI8/M7#d vgnd 4.99763e-16 |
| cpreboot1/282 preboot1#177 vgnd 5.99485e-16 |
| cpreboot1/283 preboot1#173 vgnd 7.56102e-16 |
| cpreboot1/284 preboot1#153 vgnd 4.99781e-16 |
| cpreboot1/285 preboot1#136 vgnd 7.34456e-16 |
| cpreboot1/286 preboot1#130 vgnd 1.71761e-16 |
| cpreboot1/287 preboot1#92 vgnd 9.77355e-16 |
| cpreboot1/288 preboot1#87 vgnd 1.05307e-15 |
| rpreboot1/289 preboot1#314 preboot1 0.160209 |
| rpreboot1/290 preboot1#313 preboot1#314 0.0812168 |
| rpreboot1/291 preboot1#312 preboot1#313 1.38069 |
| rpreboot1/292 preboot1#311 preboot1#312 0.0812168 |
| rpreboot1/293 preboot1#310 preboot1#311 0.324867 |
| rpreboot1/294 preboot1#309 preboot1#310 0.0812168 |
| rpreboot1/295 preboot1#306 preboot1#307 0.0812168 |
| rpreboot1/296 preboot1#278 preboot1#280 0.493904 |
| rpreboot1/297 preboot1#276 preboot1#277 3.29269 |
| rpreboot1/298 preboot1#274 preboot1#276 56.1404 |
| rpreboot1/299 preboot1#265 preboot1#267 0.493904 |
| rpreboot1/300 preboot1#262 preboot1#264 3.29269 |
| rpreboot1/301 preboot1#261 preboot1#262 56.1404 |
| rpreboot1/302 preboot1#255 preboot1#277 3.62295 |
| rpreboot1/303 preboot1#255 preboot1#274 3.55879 |
| rpreboot1/304 preboot1#253 preboot1 1.99988 |
| rpreboot1/305 preboot1#253 preboot1#267 4.65 |
| rpreboot1/306 preboot1#253 preboot1#280 4.84892 |
| rpreboot1/307 preboot1#251 preboot1#255 0.184417 |
| rpreboot1/308 preboot1#251 preboot1#264 3.54508 |
| rpreboot1/309 preboot1#251 preboot1#261 3.48092 |
| rpreboot1/310 preboot1#218 preboot1#265 11.0305 |
| rpreboot1/311 preboot1#218 preboot1#278 11.0305 |
| rpreboot1/312 preboot1#210 preboot1#218 37.5307 |
| rpreboot1/313 preboot1#210 preboot1#264 7.73783 |
| rpreboot1/314 preboot1#210 preboot1#277 7.73783 |
| rpreboot1/315 Xpreboot_gen/XI8/M7__3#d preboot1#276 85.7143 |
| rpreboot1/316 Xpreboot_gen/XI8/M7__3#d preboot1#274 175.111 |
| rpreboot1/317 Xpreboot_gen/XI8/M7#d preboot1#262 85.7143 |
| rpreboot1/318 Xpreboot_gen/XI8/M7#d preboot1#261 175.111 |
| rpreboot1/319 Xpreboot_gen/XI8/M8__3#d preboot1#280 143.23 |
| rpreboot1/320 Xpreboot_gen/XI8/M8__3#d preboot1#278 121.333 |
| rpreboot1/321 Xpreboot_gen/XI8/M8#d preboot1#267 143.23 |
| rpreboot1/322 Xpreboot_gen/XI8/M8#d preboot1#265 121.333 |
| rpreboot1/323 preboot1#177 preboot1 3.1 |
| rpreboot1/324 preboot1#173 preboot1#182 0.887833 |
| rpreboot1/325 preboot1#173 preboot1#177 360.422 |
| rpreboot1/326 preboot1#157 preboot1#313 0.516667 |
| rpreboot1/327 preboot1#157 preboot1#312 0.516667 |
| rpreboot1/328 preboot1#157 preboot1#311 1.86 |
| rpreboot1/329 preboot1#157 preboot1#314 3.1 |
| rpreboot1/330 preboot1#157 preboot1#177 16.6583 |
| rpreboot1/331 preboot1#153 preboot1#182 0.516667 |
| rpreboot1/332 preboot1#145 preboot1#310 1.86 |
| rpreboot1/333 preboot1#145 preboot1#309 0.516667 |
| rpreboot1/334 preboot1#145 preboot1#306 3.1 |
| rpreboot1/335 preboot1#145 preboot1#307 0.516667 |
| rpreboot1/336 preboot1#136 preboot1#306 3.26243 |
| rpreboot1/337 preboot1#136 preboot1#145 16.6583 |
| rpreboot1/338 preboot1#136 preboot1#153 360.422 |
| rpreboot1/339 preboot1#130 preboot1#191 0.785609 |
| rpreboot1/340 preboot1#130 preboot1#132 1.13509 |
| rpreboot1/341 preboot1#124 preboot1#130 13.2138 |
| rpreboot1/342 preboot1#124 preboot1#157 3.42259 |
| rpreboot1/343 preboot1#118 preboot1#191 0.489474 |
| rpreboot1/344 preboot1#118 preboot1#120 1.13509 |
| rpreboot1/345 preboot1#112 preboot1#118 13.2138 |
| rpreboot1/346 preboot1#112 preboot1#145 3.42259 |
| rpreboot1/347 preboot1#109 preboot1#118 0.564015 |
| rpreboot1/348 preboot1#109 preboot1#191 1.39826 |
| rpreboot1/349 preboot1#106 preboot1#307 0.055628 |
| rpreboot1/350 preboot1#106 preboot1#309 1.32484 |
| rpreboot1/351 preboot1#104 preboot1#106 1.125 |
| rpreboot1/352 preboot1#104 preboot1#109 2.82449 |
| rpreboot1/353 preboot1#102 preboot1#104 0.831795 |
| rpreboot1/354 preboot1#102 preboot1#251 6.34755 |
| rpreboot1/355 preboot1#99 preboot1#153 0.591208 |
| rpreboot1/356 preboot1#99 preboot1#182 1.31705 |
| rpreboot1/357 preboot1#99 preboot1#102 2.085 |
| rpreboot1/358 preboot1#92 preboot1#132 4.94528 |
| rpreboot1/359 preboot1#92 preboot1#177 360.422 |
| rpreboot1/360 preboot1#90 preboot1#92 42.6995 |
| rpreboot1/361 preboot1#89 preboot1#157 19.4148 |
| rpreboot1/362 preboot1#89 preboot1#90 570.897 |
| rpreboot1/363 preboot1#89 preboot1#145 19.4148 |
| rpreboot1/364 preboot1#88 preboot1#89 570.897 |
| rpreboot1/365 preboot1#88 preboot1#153 42.6995 |
| rpreboot1/366 preboot1#87 preboot1#120 4.94528 |
| rpreboot1/367 preboot1#87 preboot1#136 360.422 |
| rpreboot1/368 preboot1#73 preboot1#157 3.42259 |
| rpreboot1/369 preboot1#70 preboot1#73 14.3489 |
| rpreboot1/370 preboot1#70 preboot1#173 4.94528 |
| rpreboot1/371 preboot1#63 preboot1#88 10.7032 |
| rpreboot1/372 preboot1#63 preboot1#173 31.9963 |
| rpreboot1/373 preboot1#55 preboot1#87 31.9963 |
| rpreboot1/374 preboot1#55 preboot1#90 10.7032 |
| rpreboot1/375 preboot1#45 preboot1#145 3.42259 |
| rpreboot1/376 preboot1#42 preboot1#45 14.3489 |
| rpreboot1/377 preboot1#42 preboot1#153 4.94528 |
| rpreboot1/378 Xpreboot_cap/MI125#b preboot1#177 2.4678 |
| rpreboot1/379 Xpreboot_cap/MI125#b preboot1#136 2.4678 |
| rpreboot1/380 Xpreboot_cap/MI125#b preboot1#63 2.4678 |
| rpreboot1/381 Xpreboot_cap/MI125#b preboot1#55 2.4678 |
| rpreboot1/382 Xpreboot_cap/MI125__4#s preboot1#132 30.0 |
| rpreboot1/383 Xpreboot_cap/MI125__4#d preboot1#124 30.0 |
| rpreboot1/384 Xpreboot_cap/MI125__3#s preboot1#73 30.0 |
| rpreboot1/385 Xpreboot_cap/MI125__3#d preboot1#70 30.0 |
| rpreboot1/386 Xpreboot_cap/MI125__2#s preboot1#120 30.0 |
| rpreboot1/387 Xpreboot_cap/MI125__2#d preboot1#112 30.0 |
| rpreboot1/388 Xpreboot_cap/MI125#s preboot1#45 30.0 |
| rpreboot1/389 Xpreboot_cap/MI125#d preboot1#42 30.0 |
| rpreboot1/390 X0/X4_noxref#d1 Xpreboot_cap/MI125#b 0.0001 |
| rpreboot1/391 Xpreboot_cap/MI125__4#b Xpreboot_cap/MI125#b 0.0001 |
| rpreboot1/392 Xpreboot_cap/MI125__3#b Xpreboot_cap/MI125#b 0.0001 |
| rpreboot1/393 Xpreboot_cap/MI125__2#b Xpreboot_cap/MI125#b 0.0001 |
| rpreboot1/394 Xpreboot_gen/XI8/M8__2#d Xpreboot_gen/XI8/M8#d 0.0001 |
| rpreboot1/395 Xpreboot_gen/XI8/M8__4#d Xpreboot_gen/XI8/M8__3#d 0.0001 |
| rpreboot1/396 Xpreboot_gen/XI8/M7__2#d Xpreboot_gen/XI8/M7#d 0.0001 |
| rpreboot1/397 Xpreboot_gen/XI8/M7__4#d Xpreboot_gen/XI8/M7__3#d 0.0001 |
| * |
| *|NET preboot 5.30708e-14 |
| cpreboot/273 preboot vgnd 1.15368e-15 |
| cpreboot/274 preboot#216 vgnd 2.29671e-15 |
| cpreboot/275 preboot#210 vgnd 8.70523e-16 |
| cpreboot/276 preboot#208 vgnd 5.58484e-16 |
| cpreboot/277 preboot#200 vgnd 1.69802e-15 |
| cpreboot/278 preboot#74 vgnd 4.90886e-16 |
| cpreboot/279 preboot#71 vgnd 2.26855e-16 |
| rpreboot/280 preboot#234 preboot#235 211.053 |
| rpreboot/281 preboot#225 preboot#227 221.818 |
| rpreboot/282 preboot#216 preboot 3.16674 |
| rpreboot/283 preboot#210 preboot#235 7.07925 |
| rpreboot/284 preboot#210 preboot#234 3.81043 |
| rpreboot/285 preboot#208 preboot#227 7.07925 |
| rpreboot/286 preboot#208 preboot#210 0.415334 |
| rpreboot/287 preboot#201 preboot#225 7.07925 |
| rpreboot/288 preboot#201 Xpreboot_gen/XI11/RI107#pos 0.0770416 |
| rpreboot/289 preboot#200 preboot#201 0.0375578 |
| rpreboot/290 preboot#200 preboot#216 2.99692 |
| rpreboot/291 preboot#200 preboot#208 0.653645 |
| rpreboot/292 Xpreboot_gen/MI123__2#s preboot#235 33.0909 |
| rpreboot/293 Xpreboot_gen/MI123__2#s preboot#234 43.8556 |
| rpreboot/294 Xpreboot_gen/MI123#s preboot#227 33.0909 |
| rpreboot/295 Xpreboot_gen/MI123#s preboot#225 33.0909 |
| rpreboot/296 preboot#130 preboot#178 61.8897 |
| rpreboot/297 Xpreboot_cap/MI125__4#g preboot#130 23.0456 |
| rpreboot/298 preboot#119 preboot#166 61.8897 |
| rpreboot/299 preboot#119 Xpreboot_cap/MI125__4#g 23.0456 |
| rpreboot/300 preboot#114 preboot#171 385.81 |
| rpreboot/301 Xpreboot_cap/MI125__3#g preboot#114 23.0456 |
| rpreboot/302 preboot#105 preboot#159 362.323 |
| rpreboot/303 preboot#105 Xpreboot_cap/MI125__3#g 23.0456 |
| rpreboot/304 preboot#102 preboot#154 61.8897 |
| rpreboot/305 Xpreboot_cap/MI125__2#g preboot#102 23.0456 |
| rpreboot/306 preboot#91 preboot#142 61.8897 |
| rpreboot/307 preboot#91 Xpreboot_cap/MI125__2#g 23.0396 |
| rpreboot/308 preboot#86 preboot#147 362.323 |
| rpreboot/309 Xpreboot_cap/MI125#g preboot#86 23.0456 |
| rpreboot/310 preboot#77 preboot#135 373.414 |
| rpreboot/311 preboot#77 Xpreboot_cap/MI125#g 23.0396 |
| rpreboot/312 preboot#76 preboot#130 337.205 |
| rpreboot/313 preboot#76 preboot#178 126.567 |
| rpreboot/314 preboot#74 preboot#216 4.20697 |
| rpreboot/315 preboot#74 preboot#76 3.1 |
| rpreboot/316 preboot#74 preboot#178 4.11488 |
| rpreboot/317 preboot#73 preboot#171 107.321 |
| rpreboot/318 preboot#73 preboot#114 32.5314 |
| rpreboot/319 preboot#71 preboot 1.70672 |
| rpreboot/320 preboot#71 preboot#73 3.72 |
| rpreboot/321 preboot#71 preboot#171 4.53245 |
| rpreboot/322 preboot#70 preboot#119 337.205 |
| rpreboot/323 preboot#70 preboot#166 126.567 |
| rpreboot/324 preboot#68 preboot#70 3.1 |
| rpreboot/325 preboot#68 preboot#74 1.79759 |
| rpreboot/326 preboot#68 preboot#166 4.09686 |
| rpreboot/327 preboot#67 preboot#102 337.205 |
| rpreboot/328 preboot#67 preboot#154 126.567 |
| rpreboot/329 preboot#65 preboot#67 3.1 |
| rpreboot/330 preboot#65 preboot#68 0.174257 |
| rpreboot/331 preboot#65 preboot#154 4.09686 |
| rpreboot/332 preboot#64 preboot#159 130.807 |
| rpreboot/333 preboot#64 preboot#105 32.5314 |
| rpreboot/334 preboot#62 preboot#64 3.1 |
| rpreboot/335 preboot#62 preboot#71 1.92431 |
| rpreboot/336 preboot#62 preboot#159 4.13169 |
| rpreboot/337 preboot#61 preboot#147 130.807 |
| rpreboot/338 preboot#61 preboot#86 32.5314 |
| rpreboot/339 preboot#59 preboot#61 3.1 |
| rpreboot/340 preboot#59 preboot#62 0.169414 |
| rpreboot/341 preboot#59 preboot#147 4.13169 |
| rpreboot/342 preboot#58 preboot#91 337.205 |
| rpreboot/343 preboot#58 preboot#142 126.567 |
| rpreboot/344 preboot#57 preboot#58 3.1 |
| rpreboot/345 preboot#57 preboot#65 1.80728 |
| rpreboot/346 preboot#57 preboot#142 4.12102 |
| rpreboot/347 preboot#56 preboot#135 119.717 |
| rpreboot/348 preboot#56 preboot#77 32.5314 |
| rpreboot/349 preboot#55 preboot#56 3.1 |
| rpreboot/350 preboot#55 preboot#59 1.95447 |
| rpreboot/351 preboot#55 preboot#135 4.04009 |
| rpreboot/352 Xpreboot_gen/MI123__3#s Xpreboot_gen/MI123__2#s 0.0001 |
| cc_3 preboot#55 preboot1#42 4.62939e-17 |
| cc_4 preboot#55 preboot1#89 1.23838e-20 |
| cc_5 preboot#55 preboot1#99 2.82834e-17 |
| cc_6 preboot#55 preboot1#102 3.36355e-17 |
| cc_7 preboot#55 preboot1#136 4.6435e-17 |
| cc_8 preboot#55 preboot1#145 4.67577e-19 |
| cc_9 preboot#55 preboot1#153 9.88104e-19 |
| cc_10 preboot#55 preboot1#251 1.05731e-19 |
| cc_11 preboot#55 preboot1#253 1.42169e-17 |
| cc_12 preboot#55 preboot1 3.76983e-20 |
| cc_13 preboot#57 preboot1#87 5.68402e-17 |
| cc_14 preboot#57 preboot1#99 2.86367e-17 |
| cc_15 preboot#57 preboot1#102 3.35587e-17 |
| cc_16 preboot#57 preboot1#112 5.08906e-17 |
| cc_17 preboot#57 preboot1#130 7.8221e-19 |
| cc_18 preboot#57 preboot1#136 8.85255e-18 |
| cc_19 preboot#57 preboot1#191 1.11107e-19 |
| cc_20 preboot#58 Xpreboot_cap/MI125#b 1.46415e-19 |
| cc_21 preboot#58 preboot1#87 1.62737e-17 |
| cc_22 preboot#58 preboot1#99 3.81933e-19 |
| cc_23 preboot#58 preboot1#102 4.47578e-19 |
| cc_24 preboot#58 preboot1#112 1.99156e-17 |
| cc_25 preboot#58 preboot1#130 2.39611e-19 |
| cc_26 preboot#58 preboot1#136 2.61096e-18 |
| cc_27 preboot#58 preboot1#145 1.88912e-19 |
| cc_28 preboot#58 preboot1#191 3.40349e-20 |
| cc_29 preboot#58 preboot1#253 2.01021e-19 |
| cc_30 preboot#59 preboot1#42 1.05928e-15 |
| cc_31 preboot#59 preboot1#89 1.39079e-17 |
| cc_32 preboot#59 preboot1#99 6.85934e-17 |
| cc_33 preboot#59 preboot1#102 1.1633e-16 |
| cc_34 preboot#59 preboot1#145 1.048e-18 |
| cc_35 preboot#59 preboot1#251 1.70318e-17 |
| cc_36 preboot#59 preboot1#253 2.38748e-16 |
| cc_37 preboot#59 preboot1 2.76087e-18 |
| cc_38 preboot#62 Xpreboot_cap/MI125#b 2.41476e-18 |
| cc_39 preboot#62 preboot1#42 1.29392e-18 |
| cc_40 preboot#62 preboot1#70 1.95864e-16 |
| cc_41 preboot#62 preboot1#89 4.47016e-17 |
| cc_42 preboot#62 preboot1#102 2.0788e-19 |
| cc_43 preboot#62 preboot1#145 2.07606e-19 |
| cc_44 preboot#62 preboot1#157 1.87519e-18 |
| cc_45 preboot#62 preboot1#177 1.40309e-20 |
| cc_46 preboot#62 preboot1#251 5.13055e-17 |
| cc_47 preboot#62 preboot1#253 8.12924e-17 |
| cc_48 preboot#62 preboot1 9.40063e-19 |
| cc_49 preboot#65 preboot1#90 1.26861e-17 |
| cc_50 preboot#65 preboot1#99 7.31552e-17 |
| cc_51 preboot#65 preboot1#102 8.57288e-17 |
| cc_52 preboot#65 preboot1#112 1.24195e-15 |
| cc_53 preboot#65 preboot1#130 6.8632e-17 |
| cc_54 preboot#65 preboot1#191 9.74866e-18 |
| cc_55 preboot#67 Xpreboot_cap/MI125#b 1.40137e-19 |
| cc_56 preboot#67 preboot1#55 7.92705e-20 |
| cc_57 preboot#67 preboot1#89 3.44102e-19 |
| cc_58 preboot#67 preboot1#90 1.78147e-17 |
| cc_59 preboot#67 preboot1#112 1.9692e-17 |
| cc_60 preboot#67 preboot1#130 9.52162e-19 |
| cc_61 preboot#67 preboot1#145 3.63289e-20 |
| cc_62 preboot#67 preboot1#191 1.35248e-19 |
| cc_63 preboot#67 preboot1#253 2.01021e-19 |
| cc_64 preboot#68 Xpreboot_cap/MI125#b 1.17364e-17 |
| cc_65 preboot#68 preboot1#89 3.45764e-19 |
| cc_66 preboot#68 preboot1#90 5.32907e-17 |
| cc_67 preboot#68 preboot1#124 4.89412e-17 |
| cc_68 preboot#68 preboot1#130 1.92094e-17 |
| cc_69 preboot#68 preboot1#191 2.55325e-18 |
| cc_70 preboot#70 Xpreboot_cap/MI125#b 1.40137e-19 |
| cc_71 preboot#70 preboot1#89 1.85507e-19 |
| cc_72 preboot#70 preboot1#90 1.77351e-17 |
| cc_73 preboot#70 preboot1#92 1.58844e-19 |
| cc_74 preboot#70 preboot1#124 1.9692e-17 |
| cc_75 preboot#70 preboot1#130 9.52162e-19 |
| cc_76 preboot#70 preboot1#157 1.94923e-19 |
| cc_77 preboot#70 preboot1#191 1.35248e-19 |
| cc_78 preboot#70 preboot1#253 2.01021e-19 |
| cc_79 preboot#71 Xpreboot_cap/MI125#b 7.70544e-18 |
| cc_80 preboot#71 preboot1#42 2.77653e-19 |
| cc_81 preboot#71 preboot1#70 9.2535e-16 |
| cc_82 preboot#71 preboot1#89 6.80243e-18 |
| cc_83 preboot#71 preboot1#102 5.35942e-19 |
| cc_84 preboot#71 preboot1#145 4.45488e-20 |
| cc_85 preboot#71 preboot1#157 4.02384e-19 |
| cc_86 preboot#71 preboot1#173 1.42738e-18 |
| cc_87 preboot#71 preboot1#177 7.09933e-17 |
| cc_88 preboot#71 preboot1#251 1.22534e-16 |
| cc_89 preboot#71 preboot1#253 3.33285e-16 |
| cc_90 preboot#71 preboot1 3.72642e-18 |
| cc_91 preboot#74 Xpreboot_cap/MI125#b 9.56061e-18 |
| cc_92 preboot#74 preboot1#89 5.28856e-21 |
| cc_93 preboot#74 preboot1#90 6.21061e-19 |
| cc_94 preboot#74 preboot1#92 5.40934e-17 |
| cc_95 preboot#74 preboot1#124 1.27407e-15 |
| cc_96 preboot#74 preboot1#130 5.83364e-17 |
| cc_97 preboot#74 preboot1#177 8.58635e-18 |
| cc_98 preboot#74 preboot1#191 8.28357e-18 |
| cc_99 preboot#76 Xpreboot_cap/MI125#b 1.46415e-19 |
| cc_100 preboot#76 preboot1#92 1.63165e-17 |
| cc_101 preboot#76 preboot1#124 1.95588e-17 |
| cc_102 preboot#76 preboot1#130 8.16916e-19 |
| cc_103 preboot#76 preboot1#177 2.82362e-18 |
| cc_104 preboot#76 preboot1#191 1.16037e-19 |
| cc_105 preboot#76 preboot1#253 2.01021e-19 |
| cc_106 preboot#77 Xpreboot_cap/MI125#b 3.77594e-18 |
| cc_107 preboot#77 preboot1#42 5.15269e-16 |
| cc_108 preboot#77 preboot1#99 9.80188e-18 |
| cc_109 preboot#77 preboot1#102 1.75426e-17 |
| cc_110 preboot#77 preboot1#136 4.70321e-16 |
| cc_111 preboot#77 preboot1#145 4.8719e-18 |
| cc_112 preboot#77 preboot1#153 1.89152e-17 |
| cc_113 preboot#77 preboot1#173 1.94006e-18 |
| cc_114 preboot#77 preboot1#182 2.25352e-19 |
| cc_115 preboot#77 preboot1#251 1.30454e-18 |
| cc_116 preboot#77 preboot1#253 2.58004e-18 |
| cc_117 preboot#86 Xpreboot_cap/MI125#b 1.30281e-15 |
| cc_118 preboot#86 preboot1#42 6.08365e-15 |
| cc_119 preboot#86 preboot1#88 1.85636e-17 |
| cc_120 preboot#86 preboot1#89 5.59142e-16 |
| cc_121 preboot#86 preboot1#136 3.04355e-16 |
| cc_122 preboot#86 preboot1#145 8.20247e-18 |
| cc_123 preboot#86 preboot1#153 2.11622e-17 |
| cc_124 preboot#86 preboot1#173 3.43323e-17 |
| cc_125 preboot#86 preboot1#182 3.98794e-18 |
| cc_126 preboot#86 preboot1#251 6.53898e-17 |
| cc_127 preboot#86 preboot1#253 1.48489e-17 |
| cc_128 preboot#91 Xpreboot_cap/MI125#b 3.76174e-18 |
| cc_129 preboot#91 preboot1#87 4.18109e-16 |
| cc_130 preboot#91 preboot1#99 9.81276e-18 |
| cc_131 preboot#91 preboot1#102 1.14993e-17 |
| cc_132 preboot#91 preboot1#112 5.11677e-16 |
| cc_133 preboot#91 preboot1#130 6.15616e-18 |
| cc_134 preboot#91 preboot1#136 6.70816e-17 |
| cc_135 preboot#91 preboot1#145 4.85358e-18 |
| cc_136 preboot#91 preboot1#191 8.74436e-19 |
| cc_137 preboot#91 preboot1#253 5.1647e-18 |
| cc_138 preboot#102 Xpreboot_cap/MI125#b 1.30392e-15 |
| cc_139 preboot#102 preboot1#55 5.4021e-18 |
| cc_140 preboot#102 preboot1#87 2.79811e-16 |
| cc_141 preboot#102 preboot1#89 1.59598e-17 |
| cc_142 preboot#102 preboot1#90 5.67804e-16 |
| cc_143 preboot#102 preboot1#112 6.08841e-15 |
| cc_144 preboot#102 preboot1#130 4.22972e-17 |
| cc_145 preboot#102 preboot1#136 4.48322e-17 |
| cc_146 preboot#102 preboot1#145 8.19995e-18 |
| cc_147 preboot#102 preboot1#191 6.00801e-18 |
| cc_148 preboot#102 preboot1#253 2.25164e-17 |
| cc_149 preboot#102 preboot1 2.00654e-19 |
| cc_150 preboot#105 Xpreboot_cap/MI125#b 2.5483e-18 |
| cc_151 preboot#105 preboot1#63 5.25632e-18 |
| cc_152 preboot#105 preboot1#70 5.02152e-16 |
| cc_153 preboot#105 preboot1#88 2.42087e-18 |
| cc_154 preboot#105 preboot1#89 4.51652e-16 |
| cc_155 preboot#105 preboot1#157 5.02155e-18 |
| cc_156 preboot#105 preboot1#173 1.79374e-17 |
| cc_157 preboot#105 preboot1#182 1.90082e-18 |
| cc_158 preboot#105 preboot1#251 3.77421e-17 |
| cc_159 preboot#105 preboot1#253 2.57727e-18 |
| cc_160 preboot#114 Xpreboot_cap/MI125#b 1.30941e-15 |
| cc_161 preboot#114 preboot1#63 7.43863e-18 |
| cc_162 preboot#114 preboot1#70 6.08278e-15 |
| cc_163 preboot#114 preboot1#88 5.21626e-19 |
| cc_164 preboot#114 preboot1#89 9.82879e-17 |
| cc_165 preboot#114 preboot1#102 5.06685e-19 |
| cc_166 preboot#114 preboot1#157 6.41992e-18 |
| cc_167 preboot#114 preboot1#173 6.79462e-17 |
| cc_168 preboot#114 preboot1#177 7.70976e-16 |
| cc_169 preboot#114 preboot1#182 3.38053e-18 |
| cc_170 preboot#114 preboot1#251 1.02412e-16 |
| cc_171 preboot#114 preboot1#253 1.44094e-17 |
| cc_172 preboot#119 Xpreboot_cap/MI125#b 3.60044e-18 |
| cc_173 preboot#119 preboot1#89 4.76611e-18 |
| cc_174 preboot#119 preboot1#90 4.55656e-16 |
| cc_175 preboot#119 preboot1#92 4.08106e-18 |
| cc_176 preboot#119 preboot1#124 5.05934e-16 |
| cc_177 preboot#119 preboot1#130 2.44633e-17 |
| cc_178 preboot#119 preboot1#157 5.00804e-18 |
| cc_179 preboot#119 preboot1#191 3.47482e-18 |
| cc_180 preboot#119 preboot1#253 5.1647e-18 |
| cc_181 preboot#130 Xpreboot_cap/MI125#b 1.30679e-15 |
| cc_182 preboot#130 preboot1#89 2.00258e-18 |
| cc_183 preboot#130 preboot1#90 1.06725e-16 |
| cc_184 preboot#130 preboot1#92 6.97602e-16 |
| cc_185 preboot#130 preboot1#124 6.08e-15 |
| cc_186 preboot#130 preboot1#130 4.71394e-17 |
| cc_187 preboot#130 preboot1#157 6.41992e-18 |
| cc_188 preboot#130 preboot1#177 1.22906e-16 |
| cc_189 preboot#130 preboot1#191 6.6958e-18 |
| cc_190 preboot#130 preboot1#253 2.25164e-17 |
| cc_191 preboot#130 preboot1 2.00654e-19 |
| cc_192 preboot#135 Xpreboot_cap/MI125#b 1.32218e-19 |
| cc_193 preboot#135 preboot1#42 2.7383e-17 |
| cc_194 preboot#135 preboot1#99 8.25475e-18 |
| cc_195 preboot#135 preboot1#102 9.8856e-18 |
| cc_196 preboot#135 preboot1#136 3.05503e-17 |
| cc_197 preboot#135 preboot1#145 1.76443e-19 |
| cc_198 preboot#135 preboot1#153 9.61979e-19 |
| cc_199 preboot#135 preboot1#173 6.79329e-20 |
| cc_200 preboot#135 preboot1#182 7.89088e-21 |
| cc_201 preboot#135 preboot1#251 4.56794e-20 |
| cc_202 preboot#135 preboot1#253 2.31725e-19 |
| cc_203 preboot#142 preboot1#87 1.20992e-18 |
| cc_204 preboot#142 preboot1#99 9.06534e-18 |
| cc_205 preboot#142 preboot1#102 1.06235e-17 |
| cc_206 preboot#142 preboot1#112 1.07027e-17 |
| cc_207 preboot#142 preboot1#136 1.2065e-19 |
| cc_208 preboot#147 Xpreboot_cap/MI125#b 9.20611e-20 |
| cc_209 preboot#147 preboot1#42 2.92546e-17 |
| cc_210 preboot#147 preboot1#88 3.21118e-19 |
| cc_211 preboot#147 preboot1#89 2.0791e-17 |
| cc_212 preboot#147 preboot1#145 3.38105e-20 |
| cc_213 preboot#147 preboot1#153 1.30636e-20 |
| cc_214 preboot#147 preboot1#173 5.9118e-19 |
| cc_215 preboot#147 preboot1#182 6.86697e-20 |
| cc_216 preboot#147 preboot1#251 4.45474e-18 |
| cc_217 preboot#147 preboot1#253 9.31075e-20 |
| cc_218 preboot#154 preboot1#90 4.07945e-18 |
| cc_219 preboot#154 preboot1#112 1.05111e-17 |
| cc_220 preboot#154 preboot1#130 5.53476e-18 |
| cc_221 preboot#154 preboot1#191 7.86171e-19 |
| cc_222 preboot#159 Xpreboot_cap/MI125#b 9.20611e-20 |
| cc_223 preboot#159 preboot1#63 1.89892e-19 |
| cc_224 preboot#159 preboot1#70 2.92546e-17 |
| cc_225 preboot#159 preboot1#88 8.74575e-20 |
| cc_226 preboot#159 preboot1#89 2.06434e-17 |
| cc_227 preboot#159 preboot1#157 1.81411e-19 |
| cc_228 preboot#159 preboot1#173 6.48012e-19 |
| cc_229 preboot#159 preboot1#182 6.86697e-20 |
| cc_230 preboot#159 preboot1#251 4.45474e-18 |
| cc_231 preboot#159 preboot1#253 9.31075e-20 |
| cc_232 preboot#166 preboot1#90 4.07945e-18 |
| cc_233 preboot#166 preboot1#124 1.05111e-17 |
| cc_234 preboot#166 preboot1#130 5.53476e-18 |
| cc_235 preboot#166 preboot1#191 7.86171e-19 |
| cc_236 preboot#171 Xpreboot_cap/MI125#b 1.2797e-19 |
| cc_237 preboot#171 preboot1#70 2.34788e-17 |
| cc_238 preboot#171 preboot1#102 6.70989e-21 |
| cc_239 preboot#171 preboot1#173 9.51665e-19 |
| cc_240 preboot#171 preboot1#177 2.10097e-17 |
| cc_241 preboot#171 preboot1#182 2.58894e-20 |
| cc_242 preboot#171 preboot1#251 2.6521e-18 |
| cc_243 preboot#171 preboot1#253 8.74395e-20 |
| cc_244 preboot#178 preboot1#92 9.05613e-18 |
| cc_245 preboot#178 preboot1#124 1.06542e-17 |
| cc_246 preboot#178 preboot1#177 1.43481e-18 |
| cc_247 preboot#216 Xpreboot_cap/MI125#b 1.39556e-17 |
| cc_248 preboot#216 preboot1#92 3.93198e-17 |
| cc_249 preboot#216 preboot1#177 6.25354e-18 |
| cc_250 preboot#216 preboot1#210 3.48367e-17 |
| cc_251 preboot#216 preboot1#218 6.09627e-17 |
| cc_252 preboot#216 preboot1#251 2.7702e-18 |
| cc_253 preboot#216 preboot1#253 8.79846e-17 |
| cc_254 preboot#216 preboot1#255 3.62865e-18 |
| cc_255 preboot#216 preboot1#264 3.80096e-19 |
| cc_256 preboot#216 preboot1#265 5.51768e-19 |
| cc_257 preboot#216 preboot1#277 3.27284e-19 |
| cc_258 preboot#216 preboot1#278 7.45794e-18 |
| cc_259 preboot#216 preboot1#280 2.32483e-18 |
| cc_260 preboot#216 preboot1 3.59751e-19 |
| cc_261 preboot Xpreboot_cap/MI125#b 2.51748e-18 |
| cc_262 preboot preboot1#102 4.57226e-19 |
| cc_263 preboot preboot1#173 3.33656e-19 |
| cc_264 preboot preboot1#177 1.59421e-17 |
| cc_265 preboot preboot1#210 7.13264e-17 |
| cc_266 preboot preboot1#218 9.84653e-17 |
| cc_267 preboot preboot1#251 1.02949e-16 |
| cc_268 preboot preboot1#253 1.58809e-16 |
| cc_269 preboot preboot1#255 8.66295e-18 |
| cc_270 preboot preboot1#264 1.04762e-18 |
| cc_271 preboot preboot1#265 2.87633e-19 |
| cc_272 preboot preboot1#277 9.02058e-19 |
| cc_273 preboot preboot1#278 3.88777e-18 |
| cc_274 preboot preboot1#280 1.40565e-18 |
| cc_275 preboot preboot1 1.41059e-18 |
| * |
| *|NET Xpreboot_gen/int1 4.29178e-15 |
| cXpreboot_gen/int1/0 Xpreboot_gen/int1 vgnd 1.25016e-15 |
| cXpreboot_gen/int1/1 Xpreboot_gen/int1#75 vgnd 8.01709e-16 |
| cXpreboot_gen/int1/2 Xpreboot_gen/int1#47 vgnd 2.12631e-16 |
| cXpreboot_gen/int1/3 Xpreboot_gen/XI8/M8__4#g vgnd 9.61201e-17 |
| cXpreboot_gen/int1/4 Xpreboot_gen/XI8/M7__4#g vgnd 2.71123e-16 |
| cXpreboot_gen/int1/5 Xpreboot_gen/XI8/M7__3#g vgnd 1.98687e-16 |
| cXpreboot_gen/int1/6 Xpreboot_gen/XI8/M7__2#g vgnd 1.99288e-16 |
| cXpreboot_gen/int1/7 Xpreboot_gen/XI8/M8#g vgnd 1.06745e-16 |
| cXpreboot_gen/int1/8 Xpreboot_gen/XI8/M7#g vgnd 2.76448e-16 |
| cXpreboot_gen/int1/9 Xpreboot_gen/XI9/Mp0#d vgnd 3.09441e-16 |
| cXpreboot_gen/int1/10 Xpreboot_gen/XI9/Mp1#d vgnd 3.36207e-16 |
| cXpreboot_gen/int1/11 Xpreboot_gen/XI9/Mn0#d vgnd 2.33218e-16 |
| rXpreboot_gen/int1/12 Xpreboot_gen/int1#75 Xpreboot_gen/int1 112.511 |
| rXpreboot_gen/int1/13 Xpreboot_gen/int1#47 Xpreboot_gen/int1 200.914 |
| rXpreboot_gen/int1/14 Xpreboot_gen/int1#46 Xpreboot_gen/int1#47 75.1904 |
| rXpreboot_gen/int1/15 Xpreboot_gen/int1#45 Xpreboot_gen/int1#46 75.1904 |
| rXpreboot_gen/int1/16 Xpreboot_gen/int1#43 Xpreboot_gen/int1#45 75.1904 |
| rXpreboot_gen/int1/17 Xpreboot_gen/XI8/M8__4#g Xpreboot_gen/int1#47 511.997 |
| rXpreboot_gen/int1/18 Xpreboot_gen/XI8/M7__4#g Xpreboot_gen/int1#47 2004.15 |
| rXpreboot_gen/int1/19 Xpreboot_gen/XI8/M8__3#g Xpreboot_gen/int1#46 511.997 |
| rXpreboot_gen/int1/20 Xpreboot_gen/XI8/M7__3#g Xpreboot_gen/int1#46 2004.15 |
| rXpreboot_gen/int1/21 Xpreboot_gen/XI8/M8__2#g Xpreboot_gen/int1#45 511.997 |
| rXpreboot_gen/int1/22 Xpreboot_gen/XI8/M7__2#g Xpreboot_gen/int1#45 2004.15 |
| rXpreboot_gen/int1/23 Xpreboot_gen/XI8/M8#g Xpreboot_gen/int1#43 511.997 |
| rXpreboot_gen/int1/24 Xpreboot_gen/XI8/M7#g Xpreboot_gen/int1#43 2004.15 |
| rXpreboot_gen/int1/25 Xpreboot_gen/XI9/Mp0#d Xpreboot_gen/int1#75 112.023 |
| rXpreboot_gen/int1/26 Xpreboot_gen/XI9/Mp1#d Xpreboot_gen/int1#75 125.523 |
| rXpreboot_gen/int1/27 Xpreboot_gen/XI9/Mn0#d Xpreboot_gen/int1 65.1944 |
| rXpreboot_gen/int1/28 Xpreboot_gen/XI9/Mn0__2#d Xpreboot_gen/XI9/Mn0#d 0.0001 |
| rXpreboot_gen/int1/29 Xpreboot_gen/XI9/Mp1__2#d Xpreboot_gen/XI9/Mp1#d 0.0001 |
| rXpreboot_gen/int1/30 Xpreboot_gen/XI9/Mp0__2#d Xpreboot_gen/XI9/Mp0#d 0.0001 |
| * |
| *|NET Xpreboot_gen/net32 1.43607e-15 |
| cXpreboot_gen/net32/0 Xpreboot_gen/XI12/RI108#pos vgnd 1.77517e-16 |
| cXpreboot_gen/net32/1 Xpreboot_gen/XI9/Mn1__2#g vgnd 2.33962e-16 |
| cXpreboot_gen/net32/2 Xpreboot_gen/XI9/Mp1__2#g vgnd 5.27889e-16 |
| cXpreboot_gen/net32/3 Xpreboot_gen/XI9/Mn1#g vgnd 2.04685e-16 |
| cXpreboot_gen/net32/4 Xpreboot_gen/XI9/Mp1#g vgnd 2.92018e-16 |
| rXpreboot_gen/net32/5 Xpreboot_gen/net32#27 Xpreboot_gen/net32#29 15.7375 |
| rXpreboot_gen/net32/6 Xpreboot_gen/net32#24 Xpreboot_gen/net32#27 59.4528 |
| rXpreboot_gen/net32/7 Xpreboot_gen/net32#23 Xpreboot_gen/net32 3.86321 |
| rXpreboot_gen/net32/8 Xpreboot_gen/net32#23 Xpreboot_gen/XI13/RI104#neg 3.86321 |
| rXpreboot_gen/net32/9 Xpreboot_gen/net32#23 Xpreboot_gen/net32#27 72.64 |
| rXpreboot_gen/net32/10 Xpreboot_gen/XI12/RI108#pos Xpreboot_gen/net32#23 4.74279 |
| rXpreboot_gen/net32/11 Xpreboot_gen/XI9/Mn1__2#g Xpreboot_gen/net32#29 1429.85 |
| rXpreboot_gen/net32/12 Xpreboot_gen/XI9/Mp1__2#g Xpreboot_gen/net32#29 2045.17 |
| rXpreboot_gen/net32/13 Xpreboot_gen/XI9/Mn1#g Xpreboot_gen/net32#24 1429.85 |
| rXpreboot_gen/net32/14 Xpreboot_gen/XI9/Mp1#g Xpreboot_gen/net32#24 2045.17 |
| rXpreboot_gen/net32/15 Xpreboot_gen/XI13/RI105#pos Xpreboot_gen/net32 0.0001 |
| * |
| *|NET Xpreboot_gen/XI9/int1 1.28801e-15 |
| cXpreboot_gen/XI9/int1/0 Xpreboot_gen/XI9/int1 vgnd 1.28801e-15 |
| rXpreboot_gen/XI9/int1/1 Xpreboot_gen/XI9/Mn0__2#s Xpreboot_gen/XI9/int1 43.9686 |
| rXpreboot_gen/XI9/int1/2 Xpreboot_gen/XI9/Mn1__2#d Xpreboot_gen/XI9/int1 43.6789 |
| rXpreboot_gen/XI9/int1/3 Xpreboot_gen/XI9/Mn1#d Xpreboot_gen/XI9/int1 43.9686 |
| rXpreboot_gen/XI9/int1/4 Xpreboot_gen/XI9/Mn0#s Xpreboot_gen/XI9/Mn1__2#d 0.0001 |
| * |
| * |
| * Instance Section |
| * |
| Mpreboot_cap/I125 Xpreboot_cap/MI125#d Xpreboot_cap/MI125#g Xpreboot_cap/MI125#s |
| + Xpreboot_cap/MI125#b phv nrd=0.0 l=8.0 w=7.0 m=1 ad=1.855 ps=14.53 sa=0.265 nrs=0.0 sb=0.265 |
| + as=1.855 pd=14.53 |
| Mpreboot_cap/I125__2 Xpreboot_cap/MI125__2#d Xpreboot_cap/MI125__2#g Xpreboot_cap/MI125__2#s |
| + Xpreboot_cap/MI125__2#b phv nrd=0.0 l=8.0 w=7.0 m=1 ad=1.855 ps=14.53 sa=0.265 nrs=0.0 sb=0.265 |
| + as=1.855 pd=14.53 |
| Mpreboot_cap/I125__3 Xpreboot_cap/MI125__3#d Xpreboot_cap/MI125__3#g Xpreboot_cap/MI125__3#s |
| + Xpreboot_cap/MI125__3#b phv nrd=0.0 l=8.0 w=7.0 m=1 ad=1.855 ps=14.53 sa=0.265 nrs=0.0 sb=0.265 |
| + as=1.855 pd=14.53 |
| Mpreboot_cap/I125__4 Xpreboot_cap/MI125__4#d Xpreboot_cap/MI125__4#g Xpreboot_cap/MI125__4#s |
| + Xpreboot_cap/MI125__4#b phv nrd=0.0 l=8.0 w=7.0 m=1 ad=1.855 ps=14.53 sa=0.265 nrs=0.0 sb=0.265 |
| + as=1.855 pd=14.53 |
| D0/4_noxref vgnd X0/X4_noxref#d1 nwdiode pj=73.88 area=340.418 |
| Mpreboot_gen/XI8/8 Xpreboot_gen/XI8/M8#d Xpreboot_gen/XI8/M8#g vgnd vnb nshort nrd=0.0 l=0.15 w=1.26 |
| + m=1 ad=0.1764 ps=3.05 sa=0.265 nrs=0.0 sb=1.555 as=0.3339 pd=1.54 |
| Mpreboot_gen/XI8/8__2 Xpreboot_gen/XI8/M8__2#d Xpreboot_gen/XI8/M8__2#g vgnd vnb nshort nrd=0.0 |
| + l=0.15 w=1.26 m=1 ad=0.1764 ps=1.54 sa=0.695 nrs=0.0 sb=1.125 as=0.1764 pd=1.54 |
| Mpreboot_gen/XI8/8__3 Xpreboot_gen/XI8/M8__3#d Xpreboot_gen/XI8/M8__3#g vgnd vnb nshort nrd=0.0 |
| + l=0.15 w=1.26 m=1 ad=0.1764 ps=1.54 sa=1.125 nrs=0.0 sb=0.695 as=0.1764 pd=1.54 |
| Mpreboot_gen/XI8/8__4 Xpreboot_gen/XI8/M8__4#d Xpreboot_gen/XI8/M8__4#g vgnd vnb nshort nrd=0.0 |
| + l=0.15 w=1.26 m=1 ad=0.1764 ps=3.05 sa=1.555 nrs=0.0 sb=0.265 as=0.3339 pd=1.54 |
| Mpreboot_gen/XI9/n1 Xpreboot_gen/XI9/Mn1#d Xpreboot_gen/XI9/Mn1#g vgnd vnb nshort nrd=0.0 l=0.15 |
| + w=3.0 m=1 ad=0.795 ps=3.28 sa=0.265 nrs=0.0 sb=1.555 as=0.42 pd=6.53 |
| Mpreboot_gen/XI9/n1__2 Xpreboot_gen/XI9/Mn1__2#d Xpreboot_gen/XI9/Mn1__2#g vgnd vnb nshort nrd=0.0 |
| + l=0.15 w=3.0 m=1 ad=0.42 ps=3.28 sa=0.695 nrs=0.0 sb=1.125 as=0.42 pd=3.28 |
| Mpreboot_gen/XI9/n0 Xpreboot_gen/XI9/Mn0#d Xpreboot_gen/XI9/Mn0#g Xpreboot_gen/XI9/Mn0#s vnb nshort |
| + nrd=0.0 l=0.15 w=3.0 m=1 ad=0.42 ps=3.28 sa=1.125 nrs=0.0 sb=0.695 as=0.42 pd=3.28 |
| Mpreboot_gen/XI9/n0__2 Xpreboot_gen/XI9/Mn0__2#d Xpreboot_gen/XI9/Mn0__2#g Xpreboot_gen/XI9/Mn0__2#s |
| + vnb nshort nrd=0.0 l=0.15 w=3.0 m=1 ad=0.42 ps=6.53 sa=1.555 nrs=0.0 sb=0.265 |
| + as=0.795 pd=3.28 |
| Mpreboot_gen/I123 READ2 READ2 Xpreboot_gen/MI123#s VNEG_C ntvnative nrd=0.0 l=0.5 w=4.0 m=1 |
| + ad=0.56 ps=8.53 sa=0.265 nrs=0.0 sb=1.825 as=1.06 pd=4.28 |
| Mpreboot_gen/I123__2 READ2 READ2 Xpreboot_gen/MI123__2#s VNEG_C ntvnative nrd=0.0 l=0.5 w=4.0 m=1 |
| + ad=0.56 ps=4.28 sa=1.045 nrs=0.0 sb=1.045 as=0.56 pd=4.28 |
| Mpreboot_gen/I123__3 READ2 READ2 Xpreboot_gen/MI123__3#s VNEG_C ntvnative nrd=0.0 l=0.5 w=4.0 m=1 |
| + ad=1.06 ps=4.28 sa=1.825 nrs=0.0 sb=0.265 as=0.56 pd=8.53 |
| Mpreboot_gen/XI8/7 Xpreboot_gen/XI8/M7#d Xpreboot_gen/XI8/M7#g vpwr vpb phighvt nrd=0.0 l=0.15 w=5.0 |
| + m=1 ad=0.7 ps=10.53 sa=0.265 nrs=0.0 sb=1.555 as=1.325 pd=5.28 |
| Mpreboot_gen/XI8/7__2 Xpreboot_gen/XI8/M7__2#d Xpreboot_gen/XI8/M7__2#g vpwr vpb phighvt nrd=0.0 |
| + l=0.15 w=5.0 m=1 ad=0.7 ps=5.28 sa=0.695 nrs=0.0 sb=1.125 as=0.7 pd=5.28 |
| Mpreboot_gen/XI8/7__3 Xpreboot_gen/XI8/M7__3#d Xpreboot_gen/XI8/M7__3#g vpwr vpb phighvt nrd=0.0 |
| + l=0.15 w=5.0 m=1 ad=0.7 ps=5.28 sa=1.125 nrs=0.0 sb=0.695 as=0.7 pd=5.28 |
| Mpreboot_gen/XI8/7__4 Xpreboot_gen/XI8/M7__4#d Xpreboot_gen/XI8/M7__4#g vpwr vpb phighvt nrd=0.0 |
| + l=0.15 w=5.0 m=1 ad=0.7 ps=10.53 sa=1.555 nrs=0.0 sb=0.265 as=1.325 pd=5.28 |
| Mpreboot_gen/XI9/p1 Xpreboot_gen/XI9/Mp1#d Xpreboot_gen/XI9/Mp1#g vpwr vpb phighvt nrd=0.0 l=0.15 |
| + w=3.0 m=1 ad=0.42 ps=6.53 sa=0.265 nrs=0.0 sb=1.555 as=0.795 pd=3.28 |
| Mpreboot_gen/XI9/p1__2 Xpreboot_gen/XI9/Mp1__2#d Xpreboot_gen/XI9/Mp1__2#g vpwr vpb phighvt nrd=0.0 |
| + l=0.15 w=3.0 m=1 ad=0.42 ps=3.28 sa=0.695 nrs=0.0 sb=1.125 as=0.42 pd=3.28 |
| Mpreboot_gen/XI9/p0 Xpreboot_gen/XI9/Mp0#d Xpreboot_gen/XI9/Mp0#g vpwr vpb phighvt nrd=0.0 l=0.15 |
| + w=3.0 m=1 ad=0.42 ps=3.28 sa=1.125 nrs=0.0 sb=0.695 as=0.42 pd=3.28 |
| Mpreboot_gen/XI9/p0__2 Xpreboot_gen/XI9/Mp0__2#d Xpreboot_gen/XI9/Mp0__2#g vpwr vpb phighvt nrd=0.0 |
| + l=0.15 w=3.0 m=1 ad=0.42 ps=6.53 sa=1.555 nrs=0.0 sb=0.265 as=0.795 pd=3.28 |
| D1/21_noxref vgnd vpb dnwdiode_psub pj=68.84 area=167.312 |
| D1/22_noxref vnb vpb dnwdiode_pw pj=0.0 area=34.8794 |
| dD1/22_noxref_nwdiode vnb vpb nwdiode pj=25.77 area=0.0 |
| D1/23_noxref VNEG_C vpb dnwdiode_pw pj=0.0 area=21.1621 |
| dD1/23_noxref_nwdiode VNEG_C vpb nwdiode pj=18.85 area=0.0 |
| rpreboot_gen/XI13/I104 Xpreboot_gen/XI13/net12 Xpreboot_gen/XI13/RI104#neg 0.01 |
| rpreboot_gen/XI13/I105 Xpreboot_gen/XI13/RI105#pos read 0.01 |
| rpreboot_gen/XI11/I108 Xpreboot_gen/XI11/net13 READ2 0.01 |
| rpreboot_gen/XI12/I107 vgnd Xpreboot_gen/XI12/net9 0.01 |
| rpreboot_gen/XI12/I108 Xpreboot_gen/XI12/RI108#pos Xpreboot_gen/XI12/net13 0.01 |
| rpreboot_gen/XI11/I107 Xpreboot_gen/XI11/RI107#pos Xpreboot_gen/XI11/net9 0.01 |
| * |
| .ends |
| * |
| * |
| * CYUJID: v1.1-130227.135433-amd64-p14296-r5137@xext@cxz@dfuchsia4 |
| * |
| * Complete Listing of Options |
| * Layout Cell s8fmlt_preboot |
| * Layout View layout |
| * Schematic Cell s8fmlt_preboot |
| * Schematic View schematic |
| * |
| * -hostCpus nil |
| * -streamOutErrors nil |
| * -layerMapGdsGen nil |
| * -mtlb_quiet nil |
| * -lb_allow_tmp nil |
| * -lsf_I nil |
| * -expandCell nil |
| * -mtlb_cpctfree nil |
| * -lsf_sp nil |
| * -hyper nil |
| * -lb_group nil |
| * -graphDeviceScale nil |
| * -lsf_J nil |
| * -mtlb_minswapfree nil |
| * -lsf_K nil |
| * -extViewName extracted |
| * -checkExtraFeedthroughs NO |
| * -flattenKeeps nil |
| * -metopNumber nil |
| * -lsf_L nil |
| * -rcgExtViewName nil |
| * -clean nil |
| * -mtlb_mintmpfree nil |
| * -recognizeGates nil |
| * -lsf_M nil |
| * -mtflex32bit nil |
| * -mtlsf_a nil |
| * -prependDigitWith nil |
| * -netFile nil |
| * -lsf_N nil |
| * -xCellFile nil |
| * -dupCellFile /proj/verify/cxz/s8fmlt_preboot/extLvs/cells.renamedGDS |
| * -blackBoxCellsFile nil |
| * -ignoreNameMatchPorts nil |
| * -v15 nil |
| * -mtlsf_b nil |
| * -expandAll nil |
| * -lib2 s8fmlt |
| * -lb_maxphysmem nil |
| * -noResOnLayer nil |
| * -resistanceFractureLength nil |
| * -lsf_P nil |
| * -cdl nil |
| * -selectNets nil |
| * -mtlsf_c nil |
| * -viaClusterLimit nil |
| * -veloceRF nil |
| * -hCells nil |
| * -shortNets nil |
| * -noFloats nil |
| * -metopDefault true |
| * -lb_quiet nil |
| * -mtlb_maxcpower nil |
| * -noReduce nil |
| * -selectNetsFile nil |
| * -noPexFmtSpfLumpedModelMode nil |
| * -lsf_R type==X86_64&&maxmem>480 |
| * -lb_maxjobs nil |
| * -mtlb_maxjobs nil |
| * -lsf_S nil |
| * -mtlsf_f nil |
| * -abortRcxIfLvsDirty true |
| * -excludeNets vgnd vpwr vpb vnb READ2 VNEG_C read |
| * -lsf_T nil |
| * -externalCompression nil |
| * -mtlsf_g nil |
| * -lsf_is nil |
| * -lsf_U nil |
| * -lsf_Ip nil |
| * -extractFloats nil |
| * -gndNode vgnd |
| * -lb_prio nil |
| * -lsf_V nil |
| * -runDir /proj/verify/cxz/s8fmlt_preboot/extLvs |
| * -assuraHFsnd nil |
| * -fmtSvrfHook nil |
| * -lvsSvrfHook nil |
| * -mtlb_mincwdfree nil |
| * -convertPathToPoly nil |
| * -lsf_W nil |
| * -bsub true |
| * -lsf_Is nil |
| * -mtlsf_k nil |
| * -phdbSvrfHook nil |
| * -vccNets nil |
| * -mtlsf_wa nil |
| * -fixedModelMap nil |
| * -ipclean nil |
| * -lsf_oo nil |
| * -preserveNodes nil |
| * -noConvertPathToPoly nil |
| * -rcxFilter nil |
| * -lsf_Lp nil |
| * -extWaffles nil |
| * -lb_cpower nil |
| * -mtlsf_m nil |
| * -waivedFile nil |
| * -showSeedPromotions nil |
| * -lsf_sla nil |
| * -lb_email_cjob nil |
| * -dontBindInstNames nil |
| * -lb_minswapfree nil |
| * -mtlsf_n nil |
| * -skillHook nil |
| * -coupFactor 1 |
| * -noGndCaps true |
| * -noBsub nil |
| * -machine nil |
| * -mtlsf_p nil |
| * -mtlb_force nil |
| * -dontBindNetNames nil |
| * -mtlsf_q nil |
| * -lb_d nil |
| * -mtlb_uname nil |
| * -mtlsf_r nil |
| * -predReduction nil |
| * -fetFolding nil |
| * -comanche nil |
| * -oasis nil |
| * -mtlsf_s nil |
| * -dontAbortOnDuplicateRenamedHcells nil |
| * -doWorkAroundDupInstAndBaseNode nil |
| * -lvsMaxResults nil |
| * -lsf_a nil |
| * -maxCap nil |
| * -skillFile nil |
| * -onlyArea nil |
| * -dontCheckCDLforHRCX nil |
| * -lsf_b nil |
| * -noLog true |
| * -dontBboxFixedLayouts nil |
| * -mtlsf_t nil |
| * -lsf_eo nil |
| * -lsf_c nil |
| * -formLog true |
| * -mtlsf_u nil |
| * -mtflexWait nil |
| * -SPEF nil |
| * -hCellFile nil |
| * -mtlsf_v nil |
| * -seismIC nil |
| * -ioNets nil |
| * -shortChecker nil |
| * -flatFile nil |
| * -lsf_e nil |
| * -mtlsf_w nil |
| * -runHRCXwithSourceErrors nil |
| * -extractOneThirdR nil |
| * -lsf_f nil |
| * -decouplingThreshold 5 |
| * -qrun nil |
| * -mtlsf_x nil |
| * -mtlb_allow_tmp nil |
| * -compareShortElements YES |
| * -selectPrune nil |
| * -lb_uname nil |
| * -lb_force nil |
| * -h nil |
| * -threeExtViews nil |
| * -xcal_maxd_mode custom |
| * -flattenCell nil |
| * -CCI nil |
| * -mtlsf_sla nil |
| * -lsf_g nil |
| * -rcxMap nil |
| * -excludeNetsFile nil |
| * -mtlb_short nil |
| * -lb_n nil |
| * -openIsError nil |
| * -allowUnsupportedCentOS nil |
| * -noExpandPcells nil |
| * -lsf_h nil |
| * -pdbSvrfHook nil |
| * -textDepth nil |
| * -cdl2 nil |
| * -noTurboLitho nil |
| * -lsfLogfile nil |
| * -pinData nil |
| * -lsf_i nil |
| * -noTurbo nil |
| * -doGndCaps nil |
| * -mtflex nil |
| * -shortV nil |
| * -lsf_wa nil |
| * -graphArrayParasitics nil |
| * -noNewCalOptions nil |
| * -outFlatFile nil |
| * -mtlb_minphysmem nil |
| * -lsf_k nil |
| * -lb_mintmpfree nil |
| * -noWPE nil |
| * -turbo_litho nil |
| * -addScalingParams nil |
| * -rcxModels nil |
| * -noQrun nil |
| * -remote true |
| * -noReplay true |
| * -couplingFile nil |
| * -xCells nil |
| * -mtlsf_wt nil |
| * -maxRes nil |
| * -join true |
| * -incrementalRCX nil |
| * -lsf_m nil |
| * -noMSSR nil |
| * -noTcoeff true |
| * -noViaReduction nil |
| * -bridgingFaults nil |
| * -compareLOD nil |
| * -mtflexFile nil |
| * -starRC nil |
| * -lsf_n nil |
| * -newCalOptions nil |
| * -ignoreCell nil |
| * -lvsGlobalsArePorts nil |
| * -lb_v nil |
| * -mtlb_cpower nil |
| * -runRcxIfLvsDirty nil |
| * -expandPcells nil |
| * -turbo nil |
| * -lsf_o nil |
| * -mtlb_jobname nil |
| * -lsf_p nil |
| * -lb_short nil |
| * -lb_jobname nil |
| * -rOnlyNetsFile nil |
| * -q nil |
| * -siAnalysis nil |
| * -qstream nil |
| * -mtlsf_B nil |
| * -lib s8fmlt |
| * -lsf_q nil |
| * -r nil |
| * -GRAPH nil |
| * -AGDS nil |
| * -mtlsf_C nil |
| * -lsf_r nil |
| * -lb_cpctfree nil |
| * -DSPF nil |
| * -mtlsf_Zs nil |
| * -minCap nil |
| * -mtlsf_D nil |
| * -lsf_s nil |
| * -blackBoxCells nil |
| * -mtlsf_E nil |
| * -lsf_t nil |
| * -latchupRCX nil |
| * -relaxWaiverConstraints nil |
| * -mtlb_minswap nil |
| * -gds nil |
| * -drcCadRepDir nil |
| * -allowInefficientLicenseUsage nil |
| * -mtlsf_F nil |
| * -mtlb_maxphysmem nil |
| * -lsf_u nil |
| * -lb_mincwdfree nil |
| * -lb_maxcpower nil |
| * -lb_minswap nil |
| * -noDiodes nil |
| * -noExportNetPort nil |
| * -mtlsf_G nil |
| * -fmtWarnings nil |
| * -lsf_v nil |
| * -vssNets nil |
| * -mtlb_prio nil |
| * -isolateShortsNets nil |
| * -mtlsf_H nil |
| * -lsf_w nil |
| * -layerMap nil |
| * -accuracy nil |
| * -allowSolaris nil |
| * -selectCheck nil |
| * -lsf_x nil |
| * -lb_rsh_n_emulate nil |
| * -noFractureNetOnLabel nil |
| * -dontWorkAroundDupInstAndBaseNode nil |
| * -mtlsf_J nil |
| * -graphArrayDevs nil |
| * -ignoreNameMatchPortsFile nil |
| * -mtlsf_sp nil |
| * -noCaps nil |
| * -snet nil |
| * -mtlb_rsh_n_emulate nil |
| * -metopLayer met3 |
| * -pdbrSvrfHook nil |
| * -fmax nil |
| * -decoupleCmin nil |
| * -mtlsf_L nil |
| * -graphViewType nil |
| * -boxHcellsinPhdb nil |
| * -noNetFragmentCheck nil |
| * -mtlsf_M nil |
| * -lvsCorrespondencePoints minimum |
| * -lsf_ext nil |
| * -tcoeff nil |
| * -graphParaScale nil |
| * -mtlsf_N nil |
| * -help_long nil |
| * -lsfDetach nil |
| * -minRes nil |
| * -cdslib /disks/zulu_disk1/cxz/WA/cxz_s8fmlt_dev_45/cds.lib |
| * -lsf_wt nil |
| * -log /proj/verify/cxz/s8fmlt_preboot/extLvs/s8fmlt_preboot.log |
| * -email nil |
| * -postSvrfHook nil |
| * -noExtView nil |
| * -mtlsf_P nil |
| * -preShellHook nil |
| * -pushDownBackAnnotationBetaTest nil |
| * -unshortDevPinR 0.0001 |
| * -reduceSplitGates nil |
| * -mtlb_email_cjob nil |
| * -stl nil |
| * -noStats nil |
| * -32bit nil |
| * -rccExtViewName nil |
| * -ignoreCase nil |
| * -doPortLayerText nil |
| * -mtlsf_R nil |
| * -noRes nil |
| * -mtlsf_S nil |
| * -noRmodel nil |
| * -reduceRonly true |
| * -LVS true |
| * -fuseGen nil |
| * -mtlb_group nil |
| * -ignoreNameMatchNetsFile nil |
| * -lsf_B nil |
| * -viaClustering nil |
| * -extractFusesByNet nil |
| * -lvsLODtolerance nil |
| * -keepTemp nil |
| * -mtlsf_T nil |
| * -accuracyTICER 4.0 |
| * -drcMaxResults 20000 |
| * -lsf_Zs nil |
| * -lsf_C nil |
| * -metopMerge nil |
| * -mtlsf_U nil |
| * -cgExtViewName nil |
| * -lsf_D nil |
| * -assuraHFsim nil |
| * -noHyper nil |
| * -postShellHook nil |
| * -fminTICER 2.0 |
| * -SPICE true |
| * -lsf_E nil |
| * -rOnlyNets nil |
| * -mtlsf_W nil |
| * -tieGndR nil |
| * -mergeParallel nil |
| * -switch nil |
| * -lsf_F nil |
| * -noCalDesignRev nil |
| * -forcePredSol nil |
| * -mtlb_logfile nil |
| * -preSvrfHook nil |
| * -isolateShortsIn ALL |
| * -lsf_G nil |
| * -lb_logfile nil |
| * -lb_minphysmem nil |
| * -latchupRules nil |
| * -precision nil |
| * -mtlsf_ext nil |
| * -mtlb_v nil |
| * -lsf_H nil |
| * -ignoreNameMatchNets nil |
| * -full nil |
| * -mtlsf_Lp nil |
| * |
| * Fet Diffusion Sheet Resistance Table |
| * ---------------------------------- |
| * Sheet Seed |
| * Model Rho Layer |
| * ---------------------------------- |
| * phvesd 191.0 phvesd |
| * nhvnativeesd 114.0 nhvnativeesd |
| * nhvesd 114.0 nhvesd |
| * nshortesd 120.0 nshortesd |
| * phv 191.0 phv |
| * plowvt 197.0 plowvt |
| * phighvt 197.0 phighvt |
| * pshort 197.0 pshort |
| * ntvnative 114.0 ntvnative |
| * nhvnative 114.0 nhvnative |
| * nhv 114.0 nhv |
| * fnpass 120.0 fnpass |
| * sonos_e 120.0 sonos_e |
| * nlowvt 120.0 nlowvt |
| * nshort 120.0 nshort |
| * |
| * Layer Sheet Resistance Table |
| * -------------------------------------------------- |
| * Sheet Spice |
| * Layer Rho Model deltaW TC1 TC2 TREF |
| * -------------------------------------------------- |
| * PAD_cond 0.0000 - nil |
| * MET5_cond 0.0285 mrm5 0.000 |
| * MET4_cond 0.0470 mrm4 0.000 |
| * MET3_cond 0.0470 mrm3 0.025 |
| * MET2_cond 0.1250 mrm2 0.039 |
| * MET1_cond 0.1250 mrm1 0.039 |
| * LI1_cond 12.2000 mrl1 -0.017 |
| * POLY_cond 48.2000 mrp1 0.056 |
| * |
| * Layer Contact Resistance Table |
| * ------------------------------------------------------------------- |
| * Contact Res Area Model TC1 TC2 TREF |
| * ------------------------------------------------------------------- |
| * rdl4_MET5 0.00010 5958.0000 - |
| * rdl3_MET5 0.00011 4487.0000 - |
| * rdl2_MET5 0.00013 3253.0000 - |
| * rdl1_MET5 0.00013 3485.0000 - |
| * via4 0.38000 0.6400 mrcvia4 |
| * via3 3.41000 0.0400 mrcvia3 |
| * via2 3.41000 0.0400 mrcvia2 |
| * via 4.50000 0.0225 mrcvia |
| * mcon 9.30000 0.0289 mrcl1 |
| * licon1_POLY 145.28000 0.0289 mrcp1 |
| * licon1_PTAP_notbjt 600.00000 0.0289 mrcp |
| * licon1_NTAP_notbjt 182.00000 0.0289 mrcn |
| * licon1_PDIFF 600.00000 0.0289 mrcp |
| * licon1_NDIFF 182.00000 0.0289 mrcn |
| * |
| * Capacitance Model Version |
| * // Generated on Fri Sep 7 14:34:57 2012 by xCalibrate v2006.3_29.23 Tue Oct 3 13:45:20 PDT 2006 |
| * |
| * Rule File Version |
| * /// : //depot/icm/proj/cad-s8/001-59001-rel/other/s8p12-10r-calibre/lvsExt.il#6 |
| * |
